Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.40 94.56 78.98 86.17 70.51 84.50 98.52 42.55


Total test records in report: 415
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T288 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1273919510 Jun 10 05:40:31 PM PDT 24 Jun 10 05:40:34 PM PDT 24 149742221 ps
T289 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.4047086209 Jun 10 05:40:41 PM PDT 24 Jun 10 05:40:52 PM PDT 24 3035275994 ps
T290 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1180812678 Jun 10 05:40:54 PM PDT 24 Jun 10 05:40:56 PM PDT 24 165995574 ps
T291 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.481738279 Jun 10 05:40:33 PM PDT 24 Jun 10 05:40:36 PM PDT 24 122136487 ps
T292 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2187139903 Jun 10 05:40:52 PM PDT 24 Jun 10 05:41:11 PM PDT 24 34106432046 ps
T130 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2481707255 Jun 10 05:40:41 PM PDT 24 Jun 10 05:40:49 PM PDT 24 3388878361 ps
T293 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1239995050 Jun 10 05:40:51 PM PDT 24 Jun 10 05:40:58 PM PDT 24 2416300833 ps
T294 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3372586390 Jun 10 05:40:26 PM PDT 24 Jun 10 05:41:14 PM PDT 24 36958242414 ps
T295 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3570244968 Jun 10 05:40:25 PM PDT 24 Jun 10 05:40:27 PM PDT 24 543819987 ps
T114 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.801741025 Jun 10 05:40:45 PM PDT 24 Jun 10 05:40:48 PM PDT 24 173225935 ps
T296 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1929964395 Jun 10 05:40:20 PM PDT 24 Jun 10 05:40:24 PM PDT 24 392419112 ps
T297 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2341078702 Jun 10 05:40:47 PM PDT 24 Jun 10 05:40:50 PM PDT 24 81349296 ps
T122 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2847233020 Jun 10 05:40:27 PM PDT 24 Jun 10 05:40:35 PM PDT 24 3113257265 ps
T106 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.90643563 Jun 10 05:40:36 PM PDT 24 Jun 10 05:40:44 PM PDT 24 461601587 ps
T123 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2101615957 Jun 10 05:40:30 PM PDT 24 Jun 10 05:40:37 PM PDT 24 1853422572 ps
T298 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.797241009 Jun 10 05:40:27 PM PDT 24 Jun 10 05:41:32 PM PDT 24 49053811031 ps
T299 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3538638682 Jun 10 05:40:29 PM PDT 24 Jun 10 05:40:31 PM PDT 24 814630695 ps
T300 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2834854349 Jun 10 05:40:44 PM PDT 24 Jun 10 05:40:51 PM PDT 24 1974631332 ps
T301 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2517575542 Jun 10 05:40:53 PM PDT 24 Jun 10 05:41:00 PM PDT 24 1884664341 ps
T124 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3734210195 Jun 10 05:40:44 PM PDT 24 Jun 10 05:40:52 PM PDT 24 563655090 ps
T99 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1560870231 Jun 10 05:40:29 PM PDT 24 Jun 10 05:40:45 PM PDT 24 5181038626 ps
T302 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.266453667 Jun 10 05:40:29 PM PDT 24 Jun 10 05:40:59 PM PDT 24 10942478589 ps
T303 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2673336139 Jun 10 05:40:29 PM PDT 24 Jun 10 05:40:49 PM PDT 24 22536873612 ps
T137 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1137974164 Jun 10 05:40:38 PM PDT 24 Jun 10 05:40:49 PM PDT 24 1303821321 ps
T304 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3272355270 Jun 10 05:40:43 PM PDT 24 Jun 10 05:40:47 PM PDT 24 1209283231 ps
T42 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3605044510 Jun 10 05:40:39 PM PDT 24 Jun 10 05:41:58 PM PDT 24 41340763040 ps
T305 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2033871761 Jun 10 05:40:44 PM PDT 24 Jun 10 05:40:45 PM PDT 24 268388272 ps
T306 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3825369431 Jun 10 05:40:58 PM PDT 24 Jun 10 05:41:06 PM PDT 24 4543795369 ps
T131 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.889319554 Jun 10 05:40:37 PM PDT 24 Jun 10 05:40:56 PM PDT 24 1349503850 ps
T307 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2729337656 Jun 10 05:41:02 PM PDT 24 Jun 10 05:41:05 PM PDT 24 177273406 ps
T308 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3619471393 Jun 10 05:40:35 PM PDT 24 Jun 10 05:40:39 PM PDT 24 425349671 ps
T309 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2500197556 Jun 10 05:40:32 PM PDT 24 Jun 10 05:40:36 PM PDT 24 1318892099 ps
T310 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.589547971 Jun 10 05:40:53 PM PDT 24 Jun 10 05:41:21 PM PDT 24 14377532975 ps
T311 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1824878173 Jun 10 05:40:13 PM PDT 24 Jun 10 05:41:23 PM PDT 24 22681740420 ps
T312 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.797350004 Jun 10 05:40:38 PM PDT 24 Jun 10 05:41:26 PM PDT 24 17740220422 ps
T125 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2558308141 Jun 10 05:40:51 PM PDT 24 Jun 10 05:41:00 PM PDT 24 1195578862 ps
T313 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3710383430 Jun 10 05:40:31 PM PDT 24 Jun 10 05:40:36 PM PDT 24 3186075237 ps
T314 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2517545652 Jun 10 05:40:44 PM PDT 24 Jun 10 05:40:54 PM PDT 24 5076871683 ps
T115 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3590949501 Jun 10 05:40:53 PM PDT 24 Jun 10 05:40:56 PM PDT 24 200641721 ps
T315 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2258975833 Jun 10 05:40:53 PM PDT 24 Jun 10 05:40:56 PM PDT 24 357980411 ps
T316 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.976153679 Jun 10 05:40:15 PM PDT 24 Jun 10 05:40:16 PM PDT 24 79004561 ps
T317 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.743337126 Jun 10 05:40:55 PM PDT 24 Jun 10 05:41:00 PM PDT 24 2815734749 ps
T132 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.796663872 Jun 10 05:40:43 PM PDT 24 Jun 10 05:41:07 PM PDT 24 3165758119 ps
T318 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.128640180 Jun 10 05:40:41 PM PDT 24 Jun 10 05:40:46 PM PDT 24 769701285 ps
T319 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1175795811 Jun 10 05:40:21 PM PDT 24 Jun 10 05:40:23 PM PDT 24 252964336 ps
T320 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3822035678 Jun 10 05:40:15 PM PDT 24 Jun 10 05:40:17 PM PDT 24 611791431 ps
T321 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.357210679 Jun 10 05:40:46 PM PDT 24 Jun 10 05:41:00 PM PDT 24 7955231387 ps
T322 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2317224930 Jun 10 05:40:56 PM PDT 24 Jun 10 05:41:12 PM PDT 24 29071360066 ps
T107 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2044691965 Jun 10 05:40:19 PM PDT 24 Jun 10 05:40:24 PM PDT 24 305104777 ps
T108 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3183591873 Jun 10 05:40:49 PM PDT 24 Jun 10 05:40:53 PM PDT 24 1325812990 ps
T323 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2592584362 Jun 10 05:40:17 PM PDT 24 Jun 10 05:40:34 PM PDT 24 53519856026 ps
T43 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2009549649 Jun 10 05:40:12 PM PDT 24 Jun 10 05:41:26 PM PDT 24 42058032416 ps
T324 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2592794065 Jun 10 05:40:29 PM PDT 24 Jun 10 05:40:31 PM PDT 24 452705400 ps
T325 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3606230374 Jun 10 05:40:55 PM PDT 24 Jun 10 05:41:00 PM PDT 24 2868713859 ps
T326 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.225613791 Jun 10 05:40:45 PM PDT 24 Jun 10 05:40:46 PM PDT 24 315966237 ps
T327 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3033592679 Jun 10 05:40:45 PM PDT 24 Jun 10 05:41:02 PM PDT 24 3949751918 ps
T328 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.921920114 Jun 10 05:40:47 PM PDT 24 Jun 10 05:40:50 PM PDT 24 108388008 ps
T329 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4079972692 Jun 10 05:40:54 PM PDT 24 Jun 10 05:40:58 PM PDT 24 3131954934 ps
T330 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.235798522 Jun 10 05:40:42 PM PDT 24 Jun 10 05:40:47 PM PDT 24 173702870 ps
T331 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3669143405 Jun 10 05:40:43 PM PDT 24 Jun 10 05:40:45 PM PDT 24 215452053 ps
T135 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1490889723 Jun 10 05:41:03 PM PDT 24 Jun 10 05:41:21 PM PDT 24 3015559704 ps
T136 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2802831957 Jun 10 05:40:47 PM PDT 24 Jun 10 05:41:12 PM PDT 24 5634021854 ps
T142 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4053854698 Jun 10 05:40:42 PM PDT 24 Jun 10 05:42:15 PM PDT 24 34545017724 ps
T332 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2890033523 Jun 10 05:40:29 PM PDT 24 Jun 10 05:40:45 PM PDT 24 9922621764 ps
T116 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2306847610 Jun 10 05:40:27 PM PDT 24 Jun 10 05:41:34 PM PDT 24 1136120981 ps
T333 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.4047888308 Jun 10 05:40:39 PM PDT 24 Jun 10 05:40:42 PM PDT 24 204403677 ps
T334 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.152212511 Jun 10 05:40:16 PM PDT 24 Jun 10 05:40:22 PM PDT 24 239929641 ps
T100 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1368635136 Jun 10 05:40:29 PM PDT 24 Jun 10 05:40:45 PM PDT 24 5749537301 ps
T335 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3826855821 Jun 10 05:40:25 PM PDT 24 Jun 10 05:40:28 PM PDT 24 1174811585 ps
T336 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2669852670 Jun 10 05:40:15 PM PDT 24 Jun 10 05:40:46 PM PDT 24 5949887951 ps
T337 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2463749044 Jun 10 05:40:19 PM PDT 24 Jun 10 05:40:20 PM PDT 24 39275120 ps
T338 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.382937790 Jun 10 05:40:18 PM PDT 24 Jun 10 05:40:22 PM PDT 24 632954757 ps
T339 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2064758658 Jun 10 05:40:31 PM PDT 24 Jun 10 05:41:14 PM PDT 24 53990271024 ps
T340 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1723918125 Jun 10 05:40:36 PM PDT 24 Jun 10 05:40:42 PM PDT 24 432162042 ps
T141 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3392912440 Jun 10 05:40:44 PM PDT 24 Jun 10 05:40:53 PM PDT 24 814633483 ps
T341 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3536323297 Jun 10 05:40:25 PM PDT 24 Jun 10 05:41:00 PM PDT 24 3424028256 ps
T342 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3561051956 Jun 10 05:40:28 PM PDT 24 Jun 10 05:40:29 PM PDT 24 71260690 ps
T101 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3121184935 Jun 10 05:40:13 PM PDT 24 Jun 10 05:40:24 PM PDT 24 12063592631 ps
T343 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4230030339 Jun 10 05:40:33 PM PDT 24 Jun 10 05:40:38 PM PDT 24 1289285463 ps
T344 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3556752751 Jun 10 05:40:26 PM PDT 24 Jun 10 05:40:32 PM PDT 24 10238879235 ps
T345 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.691142468 Jun 10 05:40:20 PM PDT 24 Jun 10 05:40:23 PM PDT 24 566850013 ps
T346 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2537206224 Jun 10 05:40:45 PM PDT 24 Jun 10 05:40:56 PM PDT 24 7097243900 ps
T347 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1773787600 Jun 10 05:40:21 PM PDT 24 Jun 10 05:40:29 PM PDT 24 16528433266 ps
T138 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1204975214 Jun 10 05:40:57 PM PDT 24 Jun 10 05:41:07 PM PDT 24 802702043 ps
T348 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3034089483 Jun 10 05:40:19 PM PDT 24 Jun 10 05:40:21 PM PDT 24 2902229982 ps
T349 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.541886045 Jun 10 05:40:30 PM PDT 24 Jun 10 05:40:32 PM PDT 24 355916142 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3271252778 Jun 10 05:40:14 PM PDT 24 Jun 10 05:40:24 PM PDT 24 9621927388 ps
T351 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2381568434 Jun 10 05:40:37 PM PDT 24 Jun 10 05:40:41 PM PDT 24 1662036914 ps
T109 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1051802457 Jun 10 05:40:20 PM PDT 24 Jun 10 05:40:24 PM PDT 24 273667010 ps
T352 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1050642059 Jun 10 05:40:21 PM PDT 24 Jun 10 05:41:13 PM PDT 24 73971127338 ps
T353 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3233726677 Jun 10 05:40:15 PM PDT 24 Jun 10 05:40:16 PM PDT 24 60577071 ps
T354 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1786592106 Jun 10 05:40:30 PM PDT 24 Jun 10 05:40:57 PM PDT 24 71102386852 ps
T355 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2743185224 Jun 10 05:40:45 PM PDT 24 Jun 10 05:40:51 PM PDT 24 2042681788 ps
T356 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.538983363 Jun 10 05:40:33 PM PDT 24 Jun 10 05:40:36 PM PDT 24 105606670 ps
T134 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2057133918 Jun 10 05:40:54 PM PDT 24 Jun 10 05:41:18 PM PDT 24 3841411615 ps
T357 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2269967318 Jun 10 05:40:46 PM PDT 24 Jun 10 05:40:50 PM PDT 24 226863895 ps
T110 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3675351079 Jun 10 05:40:50 PM PDT 24 Jun 10 05:40:57 PM PDT 24 186033500 ps
T358 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1441215565 Jun 10 05:40:46 PM PDT 24 Jun 10 05:40:48 PM PDT 24 231739043 ps
T359 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.22673907 Jun 10 05:40:18 PM PDT 24 Jun 10 05:40:28 PM PDT 24 8460325833 ps
T360 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3527401188 Jun 10 05:40:47 PM PDT 24 Jun 10 05:40:52 PM PDT 24 804186034 ps
T361 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.923940360 Jun 10 05:40:26 PM PDT 24 Jun 10 05:41:02 PM PDT 24 22562029819 ps
T119 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2537199819 Jun 10 05:40:38 PM PDT 24 Jun 10 05:40:40 PM PDT 24 199315322 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2001832466 Jun 10 05:40:18 PM PDT 24 Jun 10 05:40:20 PM PDT 24 782582782 ps
T363 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2676284098 Jun 10 05:40:37 PM PDT 24 Jun 10 05:40:39 PM PDT 24 631053089 ps
T120 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1563192264 Jun 10 05:40:41 PM PDT 24 Jun 10 05:40:44 PM PDT 24 216707570 ps
T364 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.803939561 Jun 10 05:40:28 PM PDT 24 Jun 10 05:40:30 PM PDT 24 100985385 ps
T365 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3318506688 Jun 10 05:40:15 PM PDT 24 Jun 10 05:40:18 PM PDT 24 755906582 ps
T121 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3382586835 Jun 10 05:40:21 PM PDT 24 Jun 10 05:41:14 PM PDT 24 5896447122 ps
T111 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3310150152 Jun 10 05:41:01 PM PDT 24 Jun 10 05:41:04 PM PDT 24 177512212 ps
T366 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1120178012 Jun 10 05:40:41 PM PDT 24 Jun 10 05:40:44 PM PDT 24 2033372292 ps
T367 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.424923359 Jun 10 05:40:44 PM PDT 24 Jun 10 05:40:47 PM PDT 24 457421904 ps
T368 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.568023864 Jun 10 05:40:51 PM PDT 24 Jun 10 05:40:53 PM PDT 24 345724336 ps
T369 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.775692224 Jun 10 05:40:09 PM PDT 24 Jun 10 05:40:11 PM PDT 24 359291690 ps
T370 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4123801305 Jun 10 05:40:17 PM PDT 24 Jun 10 05:40:18 PM PDT 24 487816243 ps
T371 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1134063363 Jun 10 05:40:39 PM PDT 24 Jun 10 05:40:40 PM PDT 24 244816121 ps
T372 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2335151671 Jun 10 05:40:28 PM PDT 24 Jun 10 05:40:43 PM PDT 24 5089289898 ps
T373 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.115092875 Jun 10 05:40:46 PM PDT 24 Jun 10 05:40:50 PM PDT 24 557537756 ps
T374 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2424731014 Jun 10 05:40:37 PM PDT 24 Jun 10 05:40:40 PM PDT 24 424027856 ps
T375 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1760272455 Jun 10 05:40:13 PM PDT 24 Jun 10 05:40:18 PM PDT 24 492430051 ps
T376 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.644473070 Jun 10 05:40:51 PM PDT 24 Jun 10 05:40:53 PM PDT 24 396024847 ps
T377 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1187786891 Jun 10 05:40:27 PM PDT 24 Jun 10 05:40:29 PM PDT 24 87164808 ps
T378 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.741478520 Jun 10 05:40:47 PM PDT 24 Jun 10 05:40:50 PM PDT 24 523290386 ps
T112 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3816690478 Jun 10 05:40:42 PM PDT 24 Jun 10 05:40:46 PM PDT 24 1190485184 ps
T379 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2874822906 Jun 10 05:40:50 PM PDT 24 Jun 10 05:40:54 PM PDT 24 1131767525 ps
T380 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.31995540 Jun 10 05:40:34 PM PDT 24 Jun 10 05:40:39 PM PDT 24 3733487473 ps
T381 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4030277722 Jun 10 05:40:18 PM PDT 24 Jun 10 05:40:47 PM PDT 24 4756351240 ps
T382 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3069072428 Jun 10 05:40:16 PM PDT 24 Jun 10 05:40:18 PM PDT 24 31698149 ps
T139 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3257684501 Jun 10 05:40:37 PM PDT 24 Jun 10 05:40:47 PM PDT 24 2048869729 ps
T383 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2632152448 Jun 10 05:40:34 PM PDT 24 Jun 10 05:40:35 PM PDT 24 237207852 ps
T384 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1021936507 Jun 10 05:40:35 PM PDT 24 Jun 10 05:40:39 PM PDT 24 2839430126 ps
T385 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3281231059 Jun 10 05:40:38 PM PDT 24 Jun 10 05:40:43 PM PDT 24 463565133 ps
T386 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.635753412 Jun 10 05:40:41 PM PDT 24 Jun 10 05:42:13 PM PDT 24 94961015063 ps
T113 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3527680170 Jun 10 05:40:34 PM PDT 24 Jun 10 05:40:37 PM PDT 24 82686817 ps
T387 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3281132113 Jun 10 05:40:49 PM PDT 24 Jun 10 05:40:56 PM PDT 24 267452249 ps
T388 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3089748617 Jun 10 05:40:40 PM PDT 24 Jun 10 05:40:49 PM PDT 24 6459014433 ps
T389 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.4103469510 Jun 10 05:40:41 PM PDT 24 Jun 10 05:40:45 PM PDT 24 238611934 ps
T390 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3355440686 Jun 10 05:40:42 PM PDT 24 Jun 10 05:41:11 PM PDT 24 10160373167 ps
T391 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.980246394 Jun 10 05:40:25 PM PDT 24 Jun 10 05:40:29 PM PDT 24 1675010699 ps
T392 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3646598092 Jun 10 05:40:26 PM PDT 24 Jun 10 05:40:37 PM PDT 24 14473521819 ps
T393 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.52048860 Jun 10 05:40:54 PM PDT 24 Jun 10 05:40:57 PM PDT 24 200641094 ps
T394 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.342208083 Jun 10 05:40:19 PM PDT 24 Jun 10 05:40:23 PM PDT 24 828279822 ps
T395 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.787579222 Jun 10 05:40:54 PM PDT 24 Jun 10 05:41:01 PM PDT 24 355112698 ps
T396 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3339800611 Jun 10 05:40:52 PM PDT 24 Jun 10 05:40:55 PM PDT 24 140007216 ps
T397 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.715248520 Jun 10 05:40:37 PM PDT 24 Jun 10 05:40:40 PM PDT 24 418042333 ps
T398 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2861836740 Jun 10 05:40:49 PM PDT 24 Jun 10 05:40:52 PM PDT 24 255360505 ps
T399 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.661343053 Jun 10 05:40:33 PM PDT 24 Jun 10 05:41:05 PM PDT 24 10335168439 ps
T400 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2624329642 Jun 10 05:40:41 PM PDT 24 Jun 10 05:40:58 PM PDT 24 2818285890 ps
T401 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2258190580 Jun 10 05:40:44 PM PDT 24 Jun 10 05:40:47 PM PDT 24 435410256 ps
T402 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2961579980 Jun 10 05:40:38 PM PDT 24 Jun 10 05:40:42 PM PDT 24 273986517 ps
T403 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4209770126 Jun 10 05:40:43 PM PDT 24 Jun 10 05:40:47 PM PDT 24 182278984 ps
T404 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3034484350 Jun 10 05:40:31 PM PDT 24 Jun 10 05:40:33 PM PDT 24 240374611 ps
T405 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.959762356 Jun 10 05:40:24 PM PDT 24 Jun 10 05:40:28 PM PDT 24 313351250 ps
T406 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2081548610 Jun 10 05:40:17 PM PDT 24 Jun 10 05:41:05 PM PDT 24 30353462234 ps
T407 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.599987243 Jun 10 05:40:19 PM PDT 24 Jun 10 05:40:22 PM PDT 24 714628705 ps
T408 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2566192251 Jun 10 05:40:49 PM PDT 24 Jun 10 05:40:51 PM PDT 24 273969949 ps
T409 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2772155312 Jun 10 05:40:51 PM PDT 24 Jun 10 05:41:14 PM PDT 24 15559760128 ps
T410 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.4221954111 Jun 10 05:40:46 PM PDT 24 Jun 10 05:40:58 PM PDT 24 15909637811 ps
T411 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2778023755 Jun 10 05:40:46 PM PDT 24 Jun 10 05:40:53 PM PDT 24 450317329 ps
T117 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.4224943556 Jun 10 05:40:39 PM PDT 24 Jun 10 05:40:42 PM PDT 24 105774400 ps
T412 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.101187757 Jun 10 05:40:39 PM PDT 24 Jun 10 05:40:42 PM PDT 24 84264403 ps
T140 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1156744099 Jun 10 05:40:49 PM PDT 24 Jun 10 05:41:13 PM PDT 24 4642178955 ps
T413 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.738057405 Jun 10 05:40:46 PM PDT 24 Jun 10 05:40:48 PM PDT 24 654550272 ps
T118 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1416838274 Jun 10 05:40:14 PM PDT 24 Jun 10 05:41:32 PM PDT 24 4021925038 ps
T414 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4076413268 Jun 10 05:40:44 PM PDT 24 Jun 10 05:40:46 PM PDT 24 1247640962 ps
T415 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3349165635 Jun 10 05:40:45 PM PDT 24 Jun 10 05:40:47 PM PDT 24 249622081 ps

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.288023807
Short name T3
Test name
Test status
Simulation time 5553140351 ps
CPU time 7.44 seconds
Started Jun 10 05:41:29 PM PDT 24
Finished Jun 10 05:41:36 PM PDT 24
Peak memory 205244 kb
Host smart-39189b86-3bf2-4c86-b350-fd7ede851d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288023807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.288023807
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.108682863
Short name T6
Test name
Test status
Simulation time 10139962144 ps
CPU time 15.68 seconds
Started Jun 10 05:41:39 PM PDT 24
Finished Jun 10 05:41:55 PM PDT 24
Peak memory 205032 kb
Host smart-bbf2a3f5-7d4c-4f2a-af2e-1439a07f937f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108682863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.108682863
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2329633399
Short name T51
Test name
Test status
Simulation time 4126919698 ps
CPU time 19.44 seconds
Started Jun 10 05:40:46 PM PDT 24
Finished Jun 10 05:41:05 PM PDT 24
Peak memory 213312 kb
Host smart-1489998b-e850-407b-bcb0-88175a4bf460
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329633399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
329633399
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1459085614
Short name T38
Test name
Test status
Simulation time 100162564 ps
CPU time 0.98 seconds
Started Jun 10 05:41:27 PM PDT 24
Finished Jun 10 05:41:28 PM PDT 24
Peak memory 204764 kb
Host smart-878d0689-32e2-413e-ba59-a06275a1a581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459085614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1459085614
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.2964539574
Short name T9
Test name
Test status
Simulation time 5815570036 ps
CPU time 16.09 seconds
Started Jun 10 05:41:25 PM PDT 24
Finished Jun 10 05:41:41 PM PDT 24
Peak memory 205080 kb
Host smart-b8ce40e6-81e3-4a8a-82cd-2d05b48ffbfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964539574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2964539574
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3972661763
Short name T84
Test name
Test status
Simulation time 1581288187 ps
CPU time 7.1 seconds
Started Jun 10 05:41:06 PM PDT 24
Finished Jun 10 05:41:14 PM PDT 24
Peak memory 213292 kb
Host smart-b5af83c6-f2d0-4acd-9b39-a9d23251ce71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972661763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3972661763
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3138142720
Short name T34
Test name
Test status
Simulation time 11158644308 ps
CPU time 32.56 seconds
Started Jun 10 05:40:54 PM PDT 24
Finished Jun 10 05:41:27 PM PDT 24
Peak memory 204932 kb
Host smart-417e5bc4-8c5c-4170-9736-bbdc38f09043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138142720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3138142720
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3219029522
Short name T65
Test name
Test status
Simulation time 25576321252 ps
CPU time 9.12 seconds
Started Jun 10 05:41:44 PM PDT 24
Finished Jun 10 05:41:54 PM PDT 24
Peak memory 213424 kb
Host smart-a0fa7492-e34a-4ab4-8752-8ec82b65096d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219029522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3219029522
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3075828613
Short name T88
Test name
Test status
Simulation time 6815409988 ps
CPU time 76.93 seconds
Started Jun 10 05:40:30 PM PDT 24
Finished Jun 10 05:41:48 PM PDT 24
Peak memory 213500 kb
Host smart-e6f9ba94-f6d2-4448-81a5-8d9a2509465c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075828613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3075828613
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.1507711709
Short name T5
Test name
Test status
Simulation time 11808650138 ps
CPU time 8.51 seconds
Started Jun 10 05:41:19 PM PDT 24
Finished Jun 10 05:41:28 PM PDT 24
Peak memory 205076 kb
Host smart-0eb9924d-2999-489a-a9e3-9a9349701cd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507711709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1507711709
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2741060945
Short name T39
Test name
Test status
Simulation time 570805940 ps
CPU time 1.14 seconds
Started Jun 10 05:41:10 PM PDT 24
Finished Jun 10 05:41:11 PM PDT 24
Peak memory 228348 kb
Host smart-90063a4d-db05-4f18-8972-54dbcb606de6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741060945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2741060945
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.346606593
Short name T52
Test name
Test status
Simulation time 6444838256 ps
CPU time 23.21 seconds
Started Jun 10 05:40:15 PM PDT 24
Finished Jun 10 05:40:38 PM PDT 24
Peak memory 213464 kb
Host smart-ee9da75c-09fd-4a65-bf8d-b14758d4785f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346606593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.346606593
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3605044510
Short name T42
Test name
Test status
Simulation time 41340763040 ps
CPU time 78.88 seconds
Started Jun 10 05:40:39 PM PDT 24
Finished Jun 10 05:41:58 PM PDT 24
Peak memory 221600 kb
Host smart-df67a25c-8cf6-40f4-ad91-5a760ca0164c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605044510 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3605044510
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.1741654039
Short name T32
Test name
Test status
Simulation time 171116405 ps
CPU time 0.87 seconds
Started Jun 10 05:41:03 PM PDT 24
Finished Jun 10 05:41:05 PM PDT 24
Peak memory 204748 kb
Host smart-283082d7-8090-4dc5-ad90-202339a17cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741654039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.1741654039
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.664459161
Short name T25
Test name
Test status
Simulation time 100528061 ps
CPU time 0.84 seconds
Started Jun 10 05:41:04 PM PDT 24
Finished Jun 10 05:41:06 PM PDT 24
Peak memory 212972 kb
Host smart-f524c8d9-b220-4e98-9bf6-d99ba5fed206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664459161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.664459161
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.4286951031
Short name T8
Test name
Test status
Simulation time 865463883 ps
CPU time 1.62 seconds
Started Jun 10 05:41:05 PM PDT 24
Finished Jun 10 05:41:07 PM PDT 24
Peak memory 204744 kb
Host smart-8fe34f23-dc64-4dbd-bd55-eecd627b0e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286951031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.4286951031
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.4224943556
Short name T117
Test name
Test status
Simulation time 105774400 ps
CPU time 2.62 seconds
Started Jun 10 05:40:39 PM PDT 24
Finished Jun 10 05:40:42 PM PDT 24
Peak memory 213216 kb
Host smart-07e939ea-01cf-4d3f-9e23-9179c9d3976e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224943556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.4224943556
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.90643563
Short name T106
Test name
Test status
Simulation time 461601587 ps
CPU time 7.55 seconds
Started Jun 10 05:40:36 PM PDT 24
Finished Jun 10 05:40:44 PM PDT 24
Peak memory 205100 kb
Host smart-880e323d-bb6d-43dc-a0ee-fcc279ed5408
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90643563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_cs
r_outstanding.90643563
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.234712021
Short name T30
Test name
Test status
Simulation time 158035006 ps
CPU time 1.09 seconds
Started Jun 10 05:41:09 PM PDT 24
Finished Jun 10 05:41:11 PM PDT 24
Peak memory 204712 kb
Host smart-d437bf0d-2332-46a2-988a-c6803bd911d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234712021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.234712021
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.669335560
Short name T29
Test name
Test status
Simulation time 13613052119 ps
CPU time 37.2 seconds
Started Jun 10 05:41:24 PM PDT 24
Finished Jun 10 05:42:02 PM PDT 24
Peak memory 213332 kb
Host smart-1d093ef5-4529-4733-9299-40652ee8696f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669335560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.669335560
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3826119338
Short name T175
Test name
Test status
Simulation time 79692263 ps
CPU time 0.8 seconds
Started Jun 10 05:41:23 PM PDT 24
Finished Jun 10 05:41:25 PM PDT 24
Peak memory 204836 kb
Host smart-69ebda06-fcff-49a8-ae96-342e2dd16a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826119338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3826119338
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.796663872
Short name T132
Test name
Test status
Simulation time 3165758119 ps
CPU time 22.81 seconds
Started Jun 10 05:40:43 PM PDT 24
Finished Jun 10 05:41:07 PM PDT 24
Peak memory 213316 kb
Host smart-5f188e46-297d-4ae0-87ea-ec1a8281e765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796663872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.796663872
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3719866318
Short name T70
Test name
Test status
Simulation time 219819894 ps
CPU time 0.95 seconds
Started Jun 10 05:40:37 PM PDT 24
Finished Jun 10 05:40:38 PM PDT 24
Peak memory 204720 kb
Host smart-ee92bace-5334-4b60-adc6-a0bf29b51c99
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719866318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3719866318
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3121184935
Short name T101
Test name
Test status
Simulation time 12063592631 ps
CPU time 11.04 seconds
Started Jun 10 05:40:13 PM PDT 24
Finished Jun 10 05:40:24 PM PDT 24
Peak memory 205180 kb
Host smart-bdf0e24c-0f34-4498-b1a2-c7c910945b9a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121184935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3121184935
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2592408637
Short name T57
Test name
Test status
Simulation time 195702789 ps
CPU time 1.72 seconds
Started Jun 10 05:40:55 PM PDT 24
Finished Jun 10 05:40:58 PM PDT 24
Peak memory 213372 kb
Host smart-f68b4911-38a2-4154-9292-e5c1419b5837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592408637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2592408637
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.122394510
Short name T222
Test name
Test status
Simulation time 48321397145 ps
CPU time 40.35 seconds
Started Jun 10 05:40:51 PM PDT 24
Finished Jun 10 05:41:32 PM PDT 24
Peak memory 213420 kb
Host smart-2427ef65-8f9c-4620-a9d0-185dd87eb922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122394510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.122394510
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2994074387
Short name T22
Test name
Test status
Simulation time 570603420 ps
CPU time 1.51 seconds
Started Jun 10 05:40:54 PM PDT 24
Finished Jun 10 05:40:56 PM PDT 24
Peak memory 204624 kb
Host smart-2be3c9a0-d521-4fa9-a106-ccf414afb909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994074387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2994074387
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.192168921
Short name T14
Test name
Test status
Simulation time 4223130313 ps
CPU time 4.03 seconds
Started Jun 10 05:40:58 PM PDT 24
Finished Jun 10 05:41:02 PM PDT 24
Peak memory 205084 kb
Host smart-c3aec5d1-e633-4504-b92b-ee983f93c1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192168921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.192168921
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2802831957
Short name T136
Test name
Test status
Simulation time 5634021854 ps
CPU time 23.76 seconds
Started Jun 10 05:40:47 PM PDT 24
Finished Jun 10 05:41:12 PM PDT 24
Peak memory 213376 kb
Host smart-7aff605f-0926-4ca7-87f3-4f9466637afa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802831957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
802831957
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1416838274
Short name T118
Test name
Test status
Simulation time 4021925038 ps
CPU time 77.6 seconds
Started Jun 10 05:40:14 PM PDT 24
Finished Jun 10 05:41:32 PM PDT 24
Peak memory 213368 kb
Host smart-2fbf3f5e-c612-44e1-9166-dd9078036b4f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416838274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1416838274
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2669852670
Short name T336
Test name
Test status
Simulation time 5949887951 ps
CPU time 29.94 seconds
Started Jun 10 05:40:15 PM PDT 24
Finished Jun 10 05:40:46 PM PDT 24
Peak memory 213356 kb
Host smart-79d41b41-6f08-4235-a440-210b23d43e9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669852670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2669852670
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3318506688
Short name T365
Test name
Test status
Simulation time 755906582 ps
CPU time 2.67 seconds
Started Jun 10 05:40:15 PM PDT 24
Finished Jun 10 05:40:18 PM PDT 24
Peak memory 213476 kb
Host smart-85a40ea8-45fe-4ac1-b208-e54c82361ba6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318506688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3318506688
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1653962531
Short name T82
Test name
Test status
Simulation time 115595100 ps
CPU time 2.26 seconds
Started Jun 10 05:40:17 PM PDT 24
Finished Jun 10 05:40:20 PM PDT 24
Peak memory 216856 kb
Host smart-20a2bbd2-a617-4f08-bcc1-19ae888af9f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653962531 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1653962531
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.224564923
Short name T56
Test name
Test status
Simulation time 80598937 ps
CPU time 1.62 seconds
Started Jun 10 05:40:19 PM PDT 24
Finished Jun 10 05:40:21 PM PDT 24
Peak memory 213124 kb
Host smart-33df06d5-2589-40ec-801c-409e17e19c01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224564923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.224564923
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1824878173
Short name T311
Test name
Test status
Simulation time 22681740420 ps
CPU time 68.97 seconds
Started Jun 10 05:40:13 PM PDT 24
Finished Jun 10 05:41:23 PM PDT 24
Peak memory 205056 kb
Host smart-114b4bd3-28f7-461c-a697-2905dba4f296
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824878173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1824878173
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3271252778
Short name T350
Test name
Test status
Simulation time 9621927388 ps
CPU time 9.52 seconds
Started Jun 10 05:40:14 PM PDT 24
Finished Jun 10 05:40:24 PM PDT 24
Peak memory 204968 kb
Host smart-eb13a712-731e-41ab-a7f7-d2b1cc7fd686
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271252778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.3271252778
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1798813890
Short name T270
Test name
Test status
Simulation time 3039365045 ps
CPU time 9.49 seconds
Started Jun 10 05:40:13 PM PDT 24
Finished Jun 10 05:40:23 PM PDT 24
Peak memory 204960 kb
Host smart-1d6bb788-77d7-4653-b943-8e71cea0a105
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798813890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
798813890
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3822035678
Short name T320
Test name
Test status
Simulation time 611791431 ps
CPU time 1.48 seconds
Started Jun 10 05:40:15 PM PDT 24
Finished Jun 10 05:40:17 PM PDT 24
Peak memory 204716 kb
Host smart-7867939b-ef52-4751-ab28-d3a64b53920b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822035678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3822035678
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2592584362
Short name T323
Test name
Test status
Simulation time 53519856026 ps
CPU time 15.79 seconds
Started Jun 10 05:40:17 PM PDT 24
Finished Jun 10 05:40:34 PM PDT 24
Peak memory 205036 kb
Host smart-03080493-da4d-4ce9-9a0c-90dd9a2b7e86
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592584362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2592584362
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.775692224
Short name T369
Test name
Test status
Simulation time 359291690 ps
CPU time 1.57 seconds
Started Jun 10 05:40:09 PM PDT 24
Finished Jun 10 05:40:11 PM PDT 24
Peak memory 204804 kb
Host smart-1d492f70-524b-4302-b855-9a425241f8f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775692224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_hw_reset.775692224
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4123801305
Short name T370
Test name
Test status
Simulation time 487816243 ps
CPU time 0.78 seconds
Started Jun 10 05:40:17 PM PDT 24
Finished Jun 10 05:40:18 PM PDT 24
Peak memory 204728 kb
Host smart-105bcb65-081a-4454-8ec3-7fc5136107af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123801305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.4
123801305
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.976153679
Short name T316
Test name
Test status
Simulation time 79004561 ps
CPU time 0.71 seconds
Started Jun 10 05:40:15 PM PDT 24
Finished Jun 10 05:40:16 PM PDT 24
Peak memory 204652 kb
Host smart-51619276-9e3f-473c-887c-6bbeb0a64723
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976153679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.976153679
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3233726677
Short name T353
Test name
Test status
Simulation time 60577071 ps
CPU time 0.68 seconds
Started Jun 10 05:40:15 PM PDT 24
Finished Jun 10 05:40:16 PM PDT 24
Peak memory 204716 kb
Host smart-36ac7ae0-49f3-4996-a3f8-48563f99ab20
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233726677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3233726677
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2044691965
Short name T107
Test name
Test status
Simulation time 305104777 ps
CPU time 4.4 seconds
Started Jun 10 05:40:19 PM PDT 24
Finished Jun 10 05:40:24 PM PDT 24
Peak memory 205104 kb
Host smart-eac0b5e7-b8d7-4ff9-8c77-0c38ac3fdddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044691965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2044691965
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2009549649
Short name T43
Test name
Test status
Simulation time 42058032416 ps
CPU time 73.47 seconds
Started Jun 10 05:40:12 PM PDT 24
Finished Jun 10 05:41:26 PM PDT 24
Peak memory 221616 kb
Host smart-4eedc4c9-0c16-4339-a623-df6ff42e0507
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009549649 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.2009549649
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1760272455
Short name T375
Test name
Test status
Simulation time 492430051 ps
CPU time 4.84 seconds
Started Jun 10 05:40:13 PM PDT 24
Finished Jun 10 05:40:18 PM PDT 24
Peak memory 213188 kb
Host smart-db14ffb8-2dfe-4c8c-8188-85fbd9ca3c10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760272455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1760272455
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3017197439
Short name T102
Test name
Test status
Simulation time 2548638334 ps
CPU time 32.34 seconds
Started Jun 10 05:40:14 PM PDT 24
Finished Jun 10 05:40:47 PM PDT 24
Peak memory 213432 kb
Host smart-f929730d-49ae-443b-8683-d9212af68876
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017197439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3017197439
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4030277722
Short name T381
Test name
Test status
Simulation time 4756351240 ps
CPU time 28.62 seconds
Started Jun 10 05:40:18 PM PDT 24
Finished Jun 10 05:40:47 PM PDT 24
Peak memory 213448 kb
Host smart-39469dfe-0e3b-4152-ae27-dd8afe059978
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030277722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4030277722
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.715300678
Short name T91
Test name
Test status
Simulation time 128301351 ps
CPU time 1.82 seconds
Started Jun 10 05:40:17 PM PDT 24
Finished Jun 10 05:40:20 PM PDT 24
Peak memory 213280 kb
Host smart-efcf7bed-71b6-4227-99b6-012e6f6d73ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715300678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.715300678
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1003703556
Short name T81
Test name
Test status
Simulation time 2068314766 ps
CPU time 2.9 seconds
Started Jun 10 05:40:22 PM PDT 24
Finished Jun 10 05:40:26 PM PDT 24
Peak memory 213344 kb
Host smart-15ff7aa5-9d2d-41b9-9d76-0d7331204fe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003703556 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1003703556
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1278219355
Short name T103
Test name
Test status
Simulation time 266599243 ps
CPU time 2.44 seconds
Started Jun 10 05:40:19 PM PDT 24
Finished Jun 10 05:40:23 PM PDT 24
Peak memory 213316 kb
Host smart-867f3fff-1449-48f6-ac87-4ce002cab957
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278219355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1278219355
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1517386704
Short name T269
Test name
Test status
Simulation time 65938143 ps
CPU time 0.77 seconds
Started Jun 10 05:40:15 PM PDT 24
Finished Jun 10 05:40:17 PM PDT 24
Peak memory 204736 kb
Host smart-41b214e0-9085-4a48-a45d-0ffc4e862705
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517386704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1517386704
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3034089483
Short name T348
Test name
Test status
Simulation time 2902229982 ps
CPU time 1.72 seconds
Started Jun 10 05:40:19 PM PDT 24
Finished Jun 10 05:40:21 PM PDT 24
Peak memory 204312 kb
Host smart-d95e87c6-0ba9-4cc8-b346-b8ef2703952a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034089483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3034089483
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2217746826
Short name T271
Test name
Test status
Simulation time 1085202955 ps
CPU time 1.91 seconds
Started Jun 10 05:40:16 PM PDT 24
Finished Jun 10 05:40:19 PM PDT 24
Peak memory 205044 kb
Host smart-57f28072-23a1-4548-8612-b80bf79b7c91
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217746826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
217746826
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2001832466
Short name T362
Test name
Test status
Simulation time 782582782 ps
CPU time 0.99 seconds
Started Jun 10 05:40:18 PM PDT 24
Finished Jun 10 05:40:20 PM PDT 24
Peak memory 204720 kb
Host smart-0696f765-cdf0-4d64-9220-53f9ddb45126
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001832466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2001832466
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.22673907
Short name T359
Test name
Test status
Simulation time 8460325833 ps
CPU time 8.52 seconds
Started Jun 10 05:40:18 PM PDT 24
Finished Jun 10 05:40:28 PM PDT 24
Peak memory 205020 kb
Host smart-fce2e1e5-5a1e-44a1-b9bb-0df101eb44b4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22673907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_
bit_bash.22673907
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.599987243
Short name T407
Test name
Test status
Simulation time 714628705 ps
CPU time 1.73 seconds
Started Jun 10 05:40:19 PM PDT 24
Finished Jun 10 05:40:22 PM PDT 24
Peak memory 204724 kb
Host smart-e57ffc07-a55b-4318-84ac-56c959401794
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599987243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.599987243
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.342208083
Short name T394
Test name
Test status
Simulation time 828279822 ps
CPU time 2.85 seconds
Started Jun 10 05:40:19 PM PDT 24
Finished Jun 10 05:40:23 PM PDT 24
Peak memory 204036 kb
Host smart-204d38d2-907d-4d31-90d9-95ede8c14f99
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342208083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.342208083
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3069072428
Short name T382
Test name
Test status
Simulation time 31698149 ps
CPU time 0.72 seconds
Started Jun 10 05:40:16 PM PDT 24
Finished Jun 10 05:40:18 PM PDT 24
Peak memory 204556 kb
Host smart-ee8aaa2b-4930-4ecb-a488-37c2ec95782c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069072428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3069072428
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.743042771
Short name T277
Test name
Test status
Simulation time 95710670 ps
CPU time 0.72 seconds
Started Jun 10 05:40:15 PM PDT 24
Finished Jun 10 05:40:17 PM PDT 24
Peak memory 204712 kb
Host smart-ce61beee-769a-4f07-8fdc-7fb0a2f65410
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743042771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.743042771
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4151500898
Short name T94
Test name
Test status
Simulation time 850880529 ps
CPU time 7.24 seconds
Started Jun 10 05:40:22 PM PDT 24
Finished Jun 10 05:40:30 PM PDT 24
Peak memory 205084 kb
Host smart-4e693aa9-dfa5-438e-bfb0-fd850f82800d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151500898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.4151500898
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2081548610
Short name T406
Test name
Test status
Simulation time 30353462234 ps
CPU time 47.21 seconds
Started Jun 10 05:40:17 PM PDT 24
Finished Jun 10 05:41:05 PM PDT 24
Peak memory 221560 kb
Host smart-a280d3ee-cceb-4bbd-af91-fa15332d2f0d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081548610 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2081548610
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.152212511
Short name T334
Test name
Test status
Simulation time 239929641 ps
CPU time 4.98 seconds
Started Jun 10 05:40:16 PM PDT 24
Finished Jun 10 05:40:22 PM PDT 24
Peak memory 213228 kb
Host smart-e98e306a-7885-4299-a2ff-a1be8234c5fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152212511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.152212511
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3084847898
Short name T133
Test name
Test status
Simulation time 1061481511 ps
CPU time 8.77 seconds
Started Jun 10 05:40:17 PM PDT 24
Finished Jun 10 05:40:27 PM PDT 24
Peak memory 213320 kb
Host smart-80b6bac2-13cf-4f44-8eaf-cd64e0eb83b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084847898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3084847898
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.4103469510
Short name T389
Test name
Test status
Simulation time 238611934 ps
CPU time 3.12 seconds
Started Jun 10 05:40:41 PM PDT 24
Finished Jun 10 05:40:45 PM PDT 24
Peak memory 219044 kb
Host smart-4e364a01-1f53-48cf-97f7-deec3276e332
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103469510 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.4103469510
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.921920114
Short name T328
Test name
Test status
Simulation time 108388008 ps
CPU time 2.36 seconds
Started Jun 10 05:40:47 PM PDT 24
Finished Jun 10 05:40:50 PM PDT 24
Peak memory 213376 kb
Host smart-f24fbcd3-47ca-423f-8efd-c15bb6731545
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921920114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.921920114
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3355440686
Short name T390
Test name
Test status
Simulation time 10160373167 ps
CPU time 28.45 seconds
Started Jun 10 05:40:42 PM PDT 24
Finished Jun 10 05:41:11 PM PDT 24
Peak memory 205108 kb
Host smart-c3aad299-c909-40a6-87cc-8eeda26baba9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355440686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.3355440686
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.4157301573
Short name T268
Test name
Test status
Simulation time 4054722026 ps
CPU time 3.72 seconds
Started Jun 10 05:40:45 PM PDT 24
Finished Jun 10 05:40:49 PM PDT 24
Peak memory 204992 kb
Host smart-fdc4fec4-e707-4434-b5ff-6d3d3acecdc6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157301573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
4157301573
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2258190580
Short name T401
Test name
Test status
Simulation time 435410256 ps
CPU time 1.76 seconds
Started Jun 10 05:40:44 PM PDT 24
Finished Jun 10 05:40:47 PM PDT 24
Peak memory 204664 kb
Host smart-7e0d703a-2946-49e5-8e37-fc8c8551f701
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258190580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2258190580
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3511449917
Short name T58
Test name
Test status
Simulation time 2572886132 ps
CPU time 4.14 seconds
Started Jun 10 05:40:46 PM PDT 24
Finished Jun 10 05:40:51 PM PDT 24
Peak memory 205164 kb
Host smart-27696053-4d31-4384-af04-16b01da355d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511449917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3511449917
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1597839965
Short name T54
Test name
Test status
Simulation time 90771747 ps
CPU time 4.17 seconds
Started Jun 10 05:40:46 PM PDT 24
Finished Jun 10 05:40:51 PM PDT 24
Peak memory 213296 kb
Host smart-1a0f1e28-8cbc-4a1f-8011-1979ee312da1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597839965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1597839965
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.741478520
Short name T378
Test name
Test status
Simulation time 523290386 ps
CPU time 2.6 seconds
Started Jun 10 05:40:47 PM PDT 24
Finished Jun 10 05:40:50 PM PDT 24
Peak memory 218496 kb
Host smart-102b8bfe-0741-4288-ae09-664e5abc8cdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741478520 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.741478520
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.101187757
Short name T412
Test name
Test status
Simulation time 84264403 ps
CPU time 2.3 seconds
Started Jun 10 05:40:39 PM PDT 24
Finished Jun 10 05:40:42 PM PDT 24
Peak memory 213300 kb
Host smart-0be193ca-7553-42df-9473-0505a051a53e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101187757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.101187757
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.357210679
Short name T321
Test name
Test status
Simulation time 7955231387 ps
CPU time 12.6 seconds
Started Jun 10 05:40:46 PM PDT 24
Finished Jun 10 05:41:00 PM PDT 24
Peak memory 205028 kb
Host smart-b0f7e3fa-381a-4269-bc9f-c649205f4f3e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357210679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
rv_dm_jtag_dmi_csr_bit_bash.357210679
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1691489726
Short name T273
Test name
Test status
Simulation time 4264742255 ps
CPU time 6.87 seconds
Started Jun 10 05:40:37 PM PDT 24
Finished Jun 10 05:40:45 PM PDT 24
Peak memory 205024 kb
Host smart-8cb053a4-1f1b-4427-a4f1-99e0285d32f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691489726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1691489726
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.384225496
Short name T93
Test name
Test status
Simulation time 596733749 ps
CPU time 8.09 seconds
Started Jun 10 05:40:35 PM PDT 24
Finished Jun 10 05:40:44 PM PDT 24
Peak memory 205096 kb
Host smart-a5117d2c-9ae0-4f06-94b9-b685ad240cea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384225496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.384225496
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.235798522
Short name T330
Test name
Test status
Simulation time 173702870 ps
CPU time 4.26 seconds
Started Jun 10 05:40:42 PM PDT 24
Finished Jun 10 05:40:47 PM PDT 24
Peak memory 212312 kb
Host smart-10adb63c-026b-494e-b323-9f4f68a76eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235798522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.235798522
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3392912440
Short name T141
Test name
Test status
Simulation time 814633483 ps
CPU time 8.05 seconds
Started Jun 10 05:40:44 PM PDT 24
Finished Jun 10 05:40:53 PM PDT 24
Peak memory 213312 kb
Host smart-23bf2406-cf43-4599-b69f-1bfc399bb893
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392912440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
392912440
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2861836740
Short name T398
Test name
Test status
Simulation time 255360505 ps
CPU time 2.57 seconds
Started Jun 10 05:40:49 PM PDT 24
Finished Jun 10 05:40:52 PM PDT 24
Peak memory 213332 kb
Host smart-8932fa5b-79b0-41e2-b1c9-ab979f87a531
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861836740 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2861836740
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3669143405
Short name T331
Test name
Test status
Simulation time 215452053 ps
CPU time 2.31 seconds
Started Jun 10 05:40:43 PM PDT 24
Finished Jun 10 05:40:45 PM PDT 24
Peak memory 213276 kb
Host smart-5629d851-c6c4-4277-8b22-3aed91d092bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669143405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3669143405
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2537206224
Short name T346
Test name
Test status
Simulation time 7097243900 ps
CPU time 10.37 seconds
Started Jun 10 05:40:45 PM PDT 24
Finished Jun 10 05:40:56 PM PDT 24
Peak memory 205040 kb
Host smart-bbcec4c6-9134-4879-ba83-f0788b9ed8ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537206224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2537206224
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2576129342
Short name T283
Test name
Test status
Simulation time 1721084108 ps
CPU time 5.34 seconds
Started Jun 10 05:40:47 PM PDT 24
Finished Jun 10 05:40:53 PM PDT 24
Peak memory 204724 kb
Host smart-68446672-f45d-4693-bb86-f6ca2769ee5f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576129342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2576129342
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2033871761
Short name T305
Test name
Test status
Simulation time 268388272 ps
CPU time 0.84 seconds
Started Jun 10 05:40:44 PM PDT 24
Finished Jun 10 05:40:45 PM PDT 24
Peak memory 204664 kb
Host smart-76d43e69-2738-4dcb-beae-67ef4b055876
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033871761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2033871761
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2778023755
Short name T411
Test name
Test status
Simulation time 450317329 ps
CPU time 6.91 seconds
Started Jun 10 05:40:46 PM PDT 24
Finished Jun 10 05:40:53 PM PDT 24
Peak memory 205100 kb
Host smart-b00300c6-8606-4da8-aeb9-8229bb636d5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778023755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2778023755
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.873354516
Short name T74
Test name
Test status
Simulation time 426333978 ps
CPU time 4.63 seconds
Started Jun 10 05:40:41 PM PDT 24
Finished Jun 10 05:40:47 PM PDT 24
Peak memory 213316 kb
Host smart-12db8ce2-5a6b-47f7-aa15-e8c86195fa48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873354516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.873354516
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2624329642
Short name T400
Test name
Test status
Simulation time 2818285890 ps
CPU time 16.36 seconds
Started Jun 10 05:40:41 PM PDT 24
Finished Jun 10 05:40:58 PM PDT 24
Peak memory 213384 kb
Host smart-ea6ba0b1-f496-4370-ab62-cf60ec3661c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624329642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
624329642
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.128640180
Short name T318
Test name
Test status
Simulation time 769701285 ps
CPU time 4.03 seconds
Started Jun 10 05:40:41 PM PDT 24
Finished Jun 10 05:40:46 PM PDT 24
Peak memory 219236 kb
Host smart-cc69ea01-3293-4549-86b5-ae6520a30011
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128640180 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.128640180
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2834854349
Short name T300
Test name
Test status
Simulation time 1974631332 ps
CPU time 6.21 seconds
Started Jun 10 05:40:44 PM PDT 24
Finished Jun 10 05:40:51 PM PDT 24
Peak memory 205044 kb
Host smart-2b027ff7-f5b0-44e2-bf7f-594582fc1e1b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834854349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2834854349
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3272355270
Short name T304
Test name
Test status
Simulation time 1209283231 ps
CPU time 3.12 seconds
Started Jun 10 05:40:43 PM PDT 24
Finished Jun 10 05:40:47 PM PDT 24
Peak memory 204940 kb
Host smart-ca82f1e7-de27-4ea7-89c0-40dcace57b1a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272355270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3272355270
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4238899561
Short name T71
Test name
Test status
Simulation time 416852839 ps
CPU time 1.5 seconds
Started Jun 10 05:40:49 PM PDT 24
Finished Jun 10 05:40:51 PM PDT 24
Peak memory 204732 kb
Host smart-a0af75bc-7cbb-43b3-ad10-361207ea553b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238899561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
4238899561
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3281132113
Short name T387
Test name
Test status
Simulation time 267452249 ps
CPU time 7.06 seconds
Started Jun 10 05:40:49 PM PDT 24
Finished Jun 10 05:40:56 PM PDT 24
Peak memory 205188 kb
Host smart-05924465-def4-4291-b3cd-325472cb5bfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281132113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3281132113
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2743185224
Short name T355
Test name
Test status
Simulation time 2042681788 ps
CPU time 5.66 seconds
Started Jun 10 05:40:45 PM PDT 24
Finished Jun 10 05:40:51 PM PDT 24
Peak memory 213208 kb
Host smart-c2bd3b33-0ecb-41c2-a0b0-749ee10e02d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743185224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2743185224
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3606230374
Short name T325
Test name
Test status
Simulation time 2868713859 ps
CPU time 4.72 seconds
Started Jun 10 05:40:55 PM PDT 24
Finished Jun 10 05:41:00 PM PDT 24
Peak memory 213476 kb
Host smart-19aafdbd-4e16-4d40-910c-88722ec6c18c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606230374 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3606230374
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2543356095
Short name T89
Test name
Test status
Simulation time 73108239 ps
CPU time 1.58 seconds
Started Jun 10 05:40:48 PM PDT 24
Finished Jun 10 05:40:50 PM PDT 24
Peak memory 213296 kb
Host smart-e0417168-916e-4339-9703-a79d4d30ec88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543356095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2543356095
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2772155312
Short name T409
Test name
Test status
Simulation time 15559760128 ps
CPU time 23.18 seconds
Started Jun 10 05:40:51 PM PDT 24
Finished Jun 10 05:41:14 PM PDT 24
Peak memory 205064 kb
Host smart-08d55787-1f1b-4f82-835a-d97defa462ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772155312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.2772155312
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2517545652
Short name T314
Test name
Test status
Simulation time 5076871683 ps
CPU time 8.56 seconds
Started Jun 10 05:40:44 PM PDT 24
Finished Jun 10 05:40:54 PM PDT 24
Peak memory 205028 kb
Host smart-7461df62-5ef4-404e-b4c6-d3adf017f7dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517545652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2517545652
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1441215565
Short name T358
Test name
Test status
Simulation time 231739043 ps
CPU time 1.28 seconds
Started Jun 10 05:40:46 PM PDT 24
Finished Jun 10 05:40:48 PM PDT 24
Peak memory 204740 kb
Host smart-e2e3a533-747b-4be4-96ea-afc68ae5ee9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441215565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1441215565
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3183591873
Short name T108
Test name
Test status
Simulation time 1325812990 ps
CPU time 3.64 seconds
Started Jun 10 05:40:49 PM PDT 24
Finished Jun 10 05:40:53 PM PDT 24
Peak memory 205228 kb
Host smart-bc811839-d253-4c17-8964-e26259599e65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183591873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3183591873
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.350530590
Short name T96
Test name
Test status
Simulation time 80313801 ps
CPU time 2.84 seconds
Started Jun 10 05:40:45 PM PDT 24
Finished Jun 10 05:40:49 PM PDT 24
Peak memory 213216 kb
Host smart-ae90c1e8-7664-49e0-bd1b-a06b60e3dc65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350530590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.350530590
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.52048860
Short name T393
Test name
Test status
Simulation time 200641094 ps
CPU time 2.22 seconds
Started Jun 10 05:40:54 PM PDT 24
Finished Jun 10 05:40:57 PM PDT 24
Peak memory 215672 kb
Host smart-a0a61701-b823-4701-8691-74eef1dd9e6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52048860 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.52048860
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.801741025
Short name T114
Test name
Test status
Simulation time 173225935 ps
CPU time 2.54 seconds
Started Jun 10 05:40:45 PM PDT 24
Finished Jun 10 05:40:48 PM PDT 24
Peak memory 213292 kb
Host smart-39aa819d-c23e-46aa-8059-984ceb6f12b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801741025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.801741025
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2187139903
Short name T292
Test name
Test status
Simulation time 34106432046 ps
CPU time 18.31 seconds
Started Jun 10 05:40:52 PM PDT 24
Finished Jun 10 05:41:11 PM PDT 24
Peak memory 204844 kb
Host smart-f7106261-5cc8-4ca2-b900-f197cfafe4de
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187139903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.2187139903
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.935738968
Short name T275
Test name
Test status
Simulation time 10939179195 ps
CPU time 9 seconds
Started Jun 10 05:40:47 PM PDT 24
Finished Jun 10 05:40:57 PM PDT 24
Peak memory 205040 kb
Host smart-cdedb7d0-117b-40b0-87e0-b87d3894743d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935738968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.935738968
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.738057405
Short name T413
Test name
Test status
Simulation time 654550272 ps
CPU time 1.04 seconds
Started Jun 10 05:40:46 PM PDT 24
Finished Jun 10 05:40:48 PM PDT 24
Peak memory 204736 kb
Host smart-35df04c2-938b-43ac-9389-07a9c93e175a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738057405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.738057405
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3675351079
Short name T110
Test name
Test status
Simulation time 186033500 ps
CPU time 6.71 seconds
Started Jun 10 05:40:50 PM PDT 24
Finished Jun 10 05:40:57 PM PDT 24
Peak memory 205116 kb
Host smart-4a999553-07ee-448c-abce-508ce0dc64f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675351079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3675351079
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2341078702
Short name T297
Test name
Test status
Simulation time 81349296 ps
CPU time 2.73 seconds
Started Jun 10 05:40:47 PM PDT 24
Finished Jun 10 05:40:50 PM PDT 24
Peak memory 213268 kb
Host smart-26b951e5-2417-4ab0-b1d3-2396a2b40c80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341078702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2341078702
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3033592679
Short name T327
Test name
Test status
Simulation time 3949751918 ps
CPU time 16.23 seconds
Started Jun 10 05:40:45 PM PDT 24
Finished Jun 10 05:41:02 PM PDT 24
Peak memory 213352 kb
Host smart-914069da-d6e3-4f89-8e84-cb66f5802313
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033592679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
033592679
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.568023864
Short name T368
Test name
Test status
Simulation time 345724336 ps
CPU time 2.03 seconds
Started Jun 10 05:40:51 PM PDT 24
Finished Jun 10 05:40:53 PM PDT 24
Peak memory 214392 kb
Host smart-45590943-3334-43a7-9498-ff352aad5a01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568023864 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.568023864
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.589547971
Short name T310
Test name
Test status
Simulation time 14377532975 ps
CPU time 27.95 seconds
Started Jun 10 05:40:53 PM PDT 24
Finished Jun 10 05:41:21 PM PDT 24
Peak memory 205020 kb
Host smart-1ad2e6b4-9c40-42b7-93d4-fd50b657f778
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589547971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
rv_dm_jtag_dmi_csr_bit_bash.589547971
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2517575542
Short name T301
Test name
Test status
Simulation time 1884664341 ps
CPU time 6.43 seconds
Started Jun 10 05:40:53 PM PDT 24
Finished Jun 10 05:41:00 PM PDT 24
Peak memory 204928 kb
Host smart-a06dbca8-a6e3-45df-8876-d300608ff457
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517575542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2517575542
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3349165635
Short name T415
Test name
Test status
Simulation time 249622081 ps
CPU time 1.35 seconds
Started Jun 10 05:40:45 PM PDT 24
Finished Jun 10 05:40:47 PM PDT 24
Peak memory 204708 kb
Host smart-aee75546-5942-42ba-9745-0126a6e6bb10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349165635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3349165635
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2558308141
Short name T125
Test name
Test status
Simulation time 1195578862 ps
CPU time 7.92 seconds
Started Jun 10 05:40:51 PM PDT 24
Finished Jun 10 05:41:00 PM PDT 24
Peak memory 205140 kb
Host smart-f5ca0cfc-15d8-48c8-9e09-0b6c7eaa6636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558308141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.2558308141
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2566192251
Short name T408
Test name
Test status
Simulation time 273969949 ps
CPU time 1.99 seconds
Started Jun 10 05:40:49 PM PDT 24
Finished Jun 10 05:40:51 PM PDT 24
Peak memory 213308 kb
Host smart-135c6e9a-f9ad-4bb8-88b7-ebc3d4354d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566192251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2566192251
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2057133918
Short name T134
Test name
Test status
Simulation time 3841411615 ps
CPU time 23.09 seconds
Started Jun 10 05:40:54 PM PDT 24
Finished Jun 10 05:41:18 PM PDT 24
Peak memory 213368 kb
Host smart-821c9f4a-a795-4f77-9aab-054b287dc265
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057133918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
057133918
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2729337656
Short name T307
Test name
Test status
Simulation time 177273406 ps
CPU time 2.42 seconds
Started Jun 10 05:41:02 PM PDT 24
Finished Jun 10 05:41:05 PM PDT 24
Peak memory 214756 kb
Host smart-bd470c3a-40a2-4e95-9e86-1a4ffe397860
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729337656 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2729337656
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3339800611
Short name T396
Test name
Test status
Simulation time 140007216 ps
CPU time 2.5 seconds
Started Jun 10 05:40:52 PM PDT 24
Finished Jun 10 05:40:55 PM PDT 24
Peak memory 213296 kb
Host smart-7ccd0893-83ce-4a3e-8e57-48b4d5409ff9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339800611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3339800611
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.4221954111
Short name T410
Test name
Test status
Simulation time 15909637811 ps
CPU time 11.63 seconds
Started Jun 10 05:40:46 PM PDT 24
Finished Jun 10 05:40:58 PM PDT 24
Peak memory 205008 kb
Host smart-779cac4d-a6b9-4a38-a31e-2324a33b6ec5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221954111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.4221954111
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2874822906
Short name T379
Test name
Test status
Simulation time 1131767525 ps
CPU time 3.64 seconds
Started Jun 10 05:40:50 PM PDT 24
Finished Jun 10 05:40:54 PM PDT 24
Peak memory 204940 kb
Host smart-614c859e-7d96-4de8-88f8-d8d4a435e6fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874822906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2874822906
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.225613791
Short name T326
Test name
Test status
Simulation time 315966237 ps
CPU time 0.9 seconds
Started Jun 10 05:40:45 PM PDT 24
Finished Jun 10 05:40:46 PM PDT 24
Peak memory 204748 kb
Host smart-87c750ec-db30-429d-9557-e5b5a635327c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225613791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.225613791
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.771246374
Short name T105
Test name
Test status
Simulation time 526609186 ps
CPU time 4.11 seconds
Started Jun 10 05:41:01 PM PDT 24
Finished Jun 10 05:41:05 PM PDT 24
Peak memory 205100 kb
Host smart-1690e5f9-e66c-4ee5-aae6-c84b4642865b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771246374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.771246374
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2269967318
Short name T357
Test name
Test status
Simulation time 226863895 ps
CPU time 3.07 seconds
Started Jun 10 05:40:46 PM PDT 24
Finished Jun 10 05:40:50 PM PDT 24
Peak memory 213276 kb
Host smart-9c470e95-14bd-4db1-b992-80c4552c0555
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269967318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2269967318
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1156744099
Short name T140
Test name
Test status
Simulation time 4642178955 ps
CPU time 23.46 seconds
Started Jun 10 05:40:49 PM PDT 24
Finished Jun 10 05:41:13 PM PDT 24
Peak memory 213508 kb
Host smart-d31304e0-692b-4c0d-9340-723546fce38e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156744099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
156744099
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2258975833
Short name T315
Test name
Test status
Simulation time 357980411 ps
CPU time 2.55 seconds
Started Jun 10 05:40:53 PM PDT 24
Finished Jun 10 05:40:56 PM PDT 24
Peak memory 221452 kb
Host smart-3a77ee0f-8f4f-4a0c-ab03-bda108f4ab21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258975833 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2258975833
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3590949501
Short name T115
Test name
Test status
Simulation time 200641721 ps
CPU time 2.3 seconds
Started Jun 10 05:40:53 PM PDT 24
Finished Jun 10 05:40:56 PM PDT 24
Peak memory 213244 kb
Host smart-7b5e9aed-9773-4f63-904b-a648a3c9e56f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590949501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3590949501
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3825369431
Short name T306
Test name
Test status
Simulation time 4543795369 ps
CPU time 7.46 seconds
Started Jun 10 05:40:58 PM PDT 24
Finished Jun 10 05:41:06 PM PDT 24
Peak memory 205064 kb
Host smart-c8413c92-ea47-487d-ab52-db77e9f5936a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825369431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.3825369431
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1295139496
Short name T281
Test name
Test status
Simulation time 1210475866 ps
CPU time 1.81 seconds
Started Jun 10 05:40:59 PM PDT 24
Finished Jun 10 05:41:01 PM PDT 24
Peak memory 204896 kb
Host smart-900be78d-7434-4515-bb56-d1feb9f0a2a7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295139496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1295139496
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1180812678
Short name T290
Test name
Test status
Simulation time 165995574 ps
CPU time 0.82 seconds
Started Jun 10 05:40:54 PM PDT 24
Finished Jun 10 05:40:56 PM PDT 24
Peak memory 204856 kb
Host smart-5369a406-12e1-4a23-a4e6-89a67bec1b39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180812678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1180812678
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.787579222
Short name T395
Test name
Test status
Simulation time 355112698 ps
CPU time 6.52 seconds
Started Jun 10 05:40:54 PM PDT 24
Finished Jun 10 05:41:01 PM PDT 24
Peak memory 205192 kb
Host smart-9c399f08-a695-44dc-9a8b-b8b1a9f6241d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787579222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.787579222
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.743337126
Short name T317
Test name
Test status
Simulation time 2815734749 ps
CPU time 5.51 seconds
Started Jun 10 05:40:55 PM PDT 24
Finished Jun 10 05:41:00 PM PDT 24
Peak memory 213196 kb
Host smart-47b9e62a-4140-4890-aa2a-a65d9321af9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743337126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.743337126
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1490889723
Short name T135
Test name
Test status
Simulation time 3015559704 ps
CPU time 17.3 seconds
Started Jun 10 05:41:03 PM PDT 24
Finished Jun 10 05:41:21 PM PDT 24
Peak memory 213384 kb
Host smart-510c517a-2cf6-473e-ae8d-8e8abe0f5b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490889723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
490889723
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1239995050
Short name T293
Test name
Test status
Simulation time 2416300833 ps
CPU time 6.64 seconds
Started Jun 10 05:40:51 PM PDT 24
Finished Jun 10 05:40:58 PM PDT 24
Peak memory 221044 kb
Host smart-5148d4ba-962d-4562-b75a-382fb839217d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239995050 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1239995050
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3310150152
Short name T111
Test name
Test status
Simulation time 177512212 ps
CPU time 2.58 seconds
Started Jun 10 05:41:01 PM PDT 24
Finished Jun 10 05:41:04 PM PDT 24
Peak memory 213316 kb
Host smart-5602f4ea-d5a6-462b-92e2-c5acfd5117ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310150152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3310150152
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2317224930
Short name T322
Test name
Test status
Simulation time 29071360066 ps
CPU time 15.91 seconds
Started Jun 10 05:40:56 PM PDT 24
Finished Jun 10 05:41:12 PM PDT 24
Peak memory 204848 kb
Host smart-adb40bfa-c0ba-4e80-8043-7187084ace2b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317224930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2317224930
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4079972692
Short name T329
Test name
Test status
Simulation time 3131954934 ps
CPU time 3.63 seconds
Started Jun 10 05:40:54 PM PDT 24
Finished Jun 10 05:40:58 PM PDT 24
Peak memory 204992 kb
Host smart-6f74eab8-5624-43d1-8fb4-07b2e4f82263
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079972692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
4079972692
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.644473070
Short name T376
Test name
Test status
Simulation time 396024847 ps
CPU time 1.28 seconds
Started Jun 10 05:40:51 PM PDT 24
Finished Jun 10 05:40:53 PM PDT 24
Peak memory 204720 kb
Host smart-272f0bde-1adb-42ab-acf5-9cb77b87fa10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644473070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.644473070
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.496177513
Short name T90
Test name
Test status
Simulation time 407716291 ps
CPU time 4.21 seconds
Started Jun 10 05:40:54 PM PDT 24
Finished Jun 10 05:40:58 PM PDT 24
Peak memory 205072 kb
Host smart-fff5d432-51f7-4306-8711-7421a48eabcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496177513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.496177513
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1204975214
Short name T138
Test name
Test status
Simulation time 802702043 ps
CPU time 9.43 seconds
Started Jun 10 05:40:57 PM PDT 24
Finished Jun 10 05:41:07 PM PDT 24
Peak memory 213384 kb
Host smart-611561fb-ee85-4b9a-809b-4028943db7d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204975214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
204975214
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3549242854
Short name T104
Test name
Test status
Simulation time 3518885733 ps
CPU time 32.19 seconds
Started Jun 10 05:40:20 PM PDT 24
Finished Jun 10 05:40:53 PM PDT 24
Peak memory 205180 kb
Host smart-04e8b26b-f0b8-4c13-87cc-5fdeb13c6d99
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549242854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3549242854
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3382586835
Short name T121
Test name
Test status
Simulation time 5896447122 ps
CPU time 51.43 seconds
Started Jun 10 05:40:21 PM PDT 24
Finished Jun 10 05:41:14 PM PDT 24
Peak memory 213440 kb
Host smart-087a555e-241e-4601-aa00-3d83245022a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382586835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3382586835
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1051802457
Short name T109
Test name
Test status
Simulation time 273667010 ps
CPU time 2.65 seconds
Started Jun 10 05:40:20 PM PDT 24
Finished Jun 10 05:40:24 PM PDT 24
Peak memory 213380 kb
Host smart-fde0c3fa-2723-427f-8012-e3b9c959c4e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051802457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1051802457
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3826855821
Short name T335
Test name
Test status
Simulation time 1174811585 ps
CPU time 3.14 seconds
Started Jun 10 05:40:25 PM PDT 24
Finished Jun 10 05:40:28 PM PDT 24
Peak memory 221472 kb
Host smart-2ab56fdd-5f1a-4b9c-b7a0-3976155923f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826855821 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3826855821
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1011311618
Short name T92
Test name
Test status
Simulation time 92512248 ps
CPU time 1.5 seconds
Started Jun 10 05:40:22 PM PDT 24
Finished Jun 10 05:40:24 PM PDT 24
Peak memory 213044 kb
Host smart-1d46fa16-26f6-41a6-b5f9-128d0c5063ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011311618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1011311618
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3713447739
Short name T278
Test name
Test status
Simulation time 93128092110 ps
CPU time 163.6 seconds
Started Jun 10 05:40:23 PM PDT 24
Finished Jun 10 05:43:07 PM PDT 24
Peak memory 205084 kb
Host smart-95025bf3-8c06-4795-8366-a43b2cd02a47
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713447739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3713447739
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3556752751
Short name T344
Test name
Test status
Simulation time 10238879235 ps
CPU time 6.69 seconds
Started Jun 10 05:40:26 PM PDT 24
Finished Jun 10 05:40:32 PM PDT 24
Peak memory 204928 kb
Host smart-73f5021c-19c0-4ddd-b09c-63d513b28ef3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556752751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.3556752751
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1890538163
Short name T98
Test name
Test status
Simulation time 9576079428 ps
CPU time 14.08 seconds
Started Jun 10 05:40:20 PM PDT 24
Finished Jun 10 05:40:35 PM PDT 24
Peak memory 205200 kb
Host smart-f1f8ae7c-8b3a-4933-a54f-f573410f2e9b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890538163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1890538163
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3646598092
Short name T392
Test name
Test status
Simulation time 14473521819 ps
CPU time 11.53 seconds
Started Jun 10 05:40:26 PM PDT 24
Finished Jun 10 05:40:37 PM PDT 24
Peak memory 204952 kb
Host smart-b31a3feb-c04d-4ecb-b878-ffd8d715a341
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646598092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
646598092
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1175795811
Short name T319
Test name
Test status
Simulation time 252964336 ps
CPU time 1.4 seconds
Started Jun 10 05:40:21 PM PDT 24
Finished Jun 10 05:40:23 PM PDT 24
Peak memory 204760 kb
Host smart-6e75e318-61cd-45df-a5d6-058415720529
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175795811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.1175795811
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1773787600
Short name T347
Test name
Test status
Simulation time 16528433266 ps
CPU time 7.3 seconds
Started Jun 10 05:40:21 PM PDT 24
Finished Jun 10 05:40:29 PM PDT 24
Peak memory 205072 kb
Host smart-6ff0b5b4-bdb7-4331-9ef8-73a3ec1e9a5f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773787600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1773787600
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.691142468
Short name T345
Test name
Test status
Simulation time 566850013 ps
CPU time 1.58 seconds
Started Jun 10 05:40:20 PM PDT 24
Finished Jun 10 05:40:23 PM PDT 24
Peak memory 204760 kb
Host smart-56c2b914-7e56-4398-8846-6ff276173db5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691142468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.691142468
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.382937790
Short name T338
Test name
Test status
Simulation time 632954757 ps
CPU time 2.22 seconds
Started Jun 10 05:40:18 PM PDT 24
Finished Jun 10 05:40:22 PM PDT 24
Peak memory 204700 kb
Host smart-886849bf-25da-47c6-9b67-8d3cadb19de2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382937790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.382937790
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.685222003
Short name T276
Test name
Test status
Simulation time 39122068 ps
CPU time 0.72 seconds
Started Jun 10 05:40:21 PM PDT 24
Finished Jun 10 05:40:22 PM PDT 24
Peak memory 204564 kb
Host smart-5aa6ab9b-e242-48c0-8d58-4fde5a7d5528
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685222003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.685222003
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2463749044
Short name T337
Test name
Test status
Simulation time 39275120 ps
CPU time 0.73 seconds
Started Jun 10 05:40:19 PM PDT 24
Finished Jun 10 05:40:20 PM PDT 24
Peak memory 204724 kb
Host smart-0ed05d2e-cb64-40aa-9f70-8becae30b125
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463749044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2463749044
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.959762356
Short name T405
Test name
Test status
Simulation time 313351250 ps
CPU time 3.99 seconds
Started Jun 10 05:40:24 PM PDT 24
Finished Jun 10 05:40:28 PM PDT 24
Peak memory 205060 kb
Host smart-f9f6e311-06ad-4708-8ecc-202a76fd500f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959762356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.959762356
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1050642059
Short name T352
Test name
Test status
Simulation time 73971127338 ps
CPU time 51.56 seconds
Started Jun 10 05:40:21 PM PDT 24
Finished Jun 10 05:41:13 PM PDT 24
Peak memory 225500 kb
Host smart-6ddabfa8-5d8d-47b9-bd0b-24ee5b460d4d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050642059 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.1050642059
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1929964395
Short name T296
Test name
Test status
Simulation time 392419112 ps
CPU time 2.96 seconds
Started Jun 10 05:40:20 PM PDT 24
Finished Jun 10 05:40:24 PM PDT 24
Peak memory 213344 kb
Host smart-3e05a753-7442-429c-8bec-0ebb3c6e61a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929964395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1929964395
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.814455043
Short name T85
Test name
Test status
Simulation time 4542445208 ps
CPU time 18.17 seconds
Started Jun 10 05:40:22 PM PDT 24
Finished Jun 10 05:40:41 PM PDT 24
Peak memory 213316 kb
Host smart-55f85777-3d00-44f9-a645-a2da0bdc9a36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814455043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.814455043
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3536323297
Short name T341
Test name
Test status
Simulation time 3424028256 ps
CPU time 34.98 seconds
Started Jun 10 05:40:25 PM PDT 24
Finished Jun 10 05:41:00 PM PDT 24
Peak memory 213384 kb
Host smart-0338a19b-0ca1-48c8-8262-5c070fdc74be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536323297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3536323297
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.803939561
Short name T364
Test name
Test status
Simulation time 100985385 ps
CPU time 1.68 seconds
Started Jun 10 05:40:28 PM PDT 24
Finished Jun 10 05:40:30 PM PDT 24
Peak memory 213300 kb
Host smart-e190fbb4-7500-4b0d-b6d8-d4e9174ad3d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803939561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.803939561
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.980246394
Short name T391
Test name
Test status
Simulation time 1675010699 ps
CPU time 3.31 seconds
Started Jun 10 05:40:25 PM PDT 24
Finished Jun 10 05:40:29 PM PDT 24
Peak memory 213312 kb
Host smart-e04d51dc-2c36-46da-85fe-315b80ba7886
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980246394 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.980246394
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1187786891
Short name T377
Test name
Test status
Simulation time 87164808 ps
CPU time 2.2 seconds
Started Jun 10 05:40:27 PM PDT 24
Finished Jun 10 05:40:29 PM PDT 24
Peak memory 213108 kb
Host smart-42e30616-5ff4-47d2-a645-8cb1137e2c33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187786891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1187786891
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.797241009
Short name T298
Test name
Test status
Simulation time 49053811031 ps
CPU time 65.21 seconds
Started Jun 10 05:40:27 PM PDT 24
Finished Jun 10 05:41:32 PM PDT 24
Peak memory 205032 kb
Host smart-13599964-250b-46c8-9523-a8124945d1dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797241009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.797241009
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3372586390
Short name T294
Test name
Test status
Simulation time 36958242414 ps
CPU time 47.78 seconds
Started Jun 10 05:40:26 PM PDT 24
Finished Jun 10 05:41:14 PM PDT 24
Peak memory 204948 kb
Host smart-b7330bfb-ac25-4668-bc39-1256e2f0eb0e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372586390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.3372586390
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1368635136
Short name T100
Test name
Test status
Simulation time 5749537301 ps
CPU time 16.36 seconds
Started Jun 10 05:40:29 PM PDT 24
Finished Jun 10 05:40:45 PM PDT 24
Peak memory 205232 kb
Host smart-601017d7-812a-4973-88c3-0c59b134db94
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368635136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1368635136
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.692052287
Short name T280
Test name
Test status
Simulation time 9513511166 ps
CPU time 28.32 seconds
Started Jun 10 05:40:27 PM PDT 24
Finished Jun 10 05:40:55 PM PDT 24
Peak memory 204908 kb
Host smart-f2b6e998-ef14-4df6-8607-98a960303848
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692052287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.692052287
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3570244968
Short name T295
Test name
Test status
Simulation time 543819987 ps
CPU time 1.72 seconds
Started Jun 10 05:40:25 PM PDT 24
Finished Jun 10 05:40:27 PM PDT 24
Peak memory 204696 kb
Host smart-e6e48d7a-22fc-4a28-9c69-7355a14f37f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570244968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3570244968
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2673336139
Short name T303
Test name
Test status
Simulation time 22536873612 ps
CPU time 20.03 seconds
Started Jun 10 05:40:29 PM PDT 24
Finished Jun 10 05:40:49 PM PDT 24
Peak memory 205092 kb
Host smart-f268da98-501e-46d9-b5f0-f2f4d64e30d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673336139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2673336139
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2592794065
Short name T324
Test name
Test status
Simulation time 452705400 ps
CPU time 1.4 seconds
Started Jun 10 05:40:29 PM PDT 24
Finished Jun 10 05:40:31 PM PDT 24
Peak memory 204740 kb
Host smart-90af1b47-162a-4f5d-b181-7164402b2eee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592794065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2592794065
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.538549650
Short name T69
Test name
Test status
Simulation time 1007876147 ps
CPU time 3.52 seconds
Started Jun 10 05:40:26 PM PDT 24
Finished Jun 10 05:40:29 PM PDT 24
Peak memory 204732 kb
Host smart-18ef47ab-0135-4546-8f0a-c0ced5192a9c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538549650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.538549650
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3700663960
Short name T286
Test name
Test status
Simulation time 112706851 ps
CPU time 0.71 seconds
Started Jun 10 05:40:27 PM PDT 24
Finished Jun 10 05:40:28 PM PDT 24
Peak memory 204612 kb
Host smart-75e43152-b1f7-458d-9931-26d2ac4352b1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700663960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3700663960
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3561051956
Short name T342
Test name
Test status
Simulation time 71260690 ps
CPU time 0.77 seconds
Started Jun 10 05:40:28 PM PDT 24
Finished Jun 10 05:40:29 PM PDT 24
Peak memory 204704 kb
Host smart-80c49f69-449f-4bc9-9e8b-4a8c6ae98e94
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561051956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3561051956
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2847233020
Short name T122
Test name
Test status
Simulation time 3113257265 ps
CPU time 7.81 seconds
Started Jun 10 05:40:27 PM PDT 24
Finished Jun 10 05:40:35 PM PDT 24
Peak memory 205144 kb
Host smart-845e3d76-691c-437b-bc02-be242ec8659a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847233020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2847233020
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3423056350
Short name T55
Test name
Test status
Simulation time 529027710 ps
CPU time 3.37 seconds
Started Jun 10 05:40:23 PM PDT 24
Finished Jun 10 05:40:27 PM PDT 24
Peak memory 213360 kb
Host smart-cfc38e73-bd35-4277-bd22-397fea8cee1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423056350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3423056350
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1886656101
Short name T80
Test name
Test status
Simulation time 945201080 ps
CPU time 10.55 seconds
Started Jun 10 05:40:27 PM PDT 24
Finished Jun 10 05:40:38 PM PDT 24
Peak memory 213208 kb
Host smart-f445645a-eb25-4127-8b6a-3c45e86439aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886656101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1886656101
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2306847610
Short name T116
Test name
Test status
Simulation time 1136120981 ps
CPU time 66.56 seconds
Started Jun 10 05:40:27 PM PDT 24
Finished Jun 10 05:41:34 PM PDT 24
Peak memory 213308 kb
Host smart-5b3dd7e7-b510-45e9-a79e-0a8f8c07b698
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306847610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2306847610
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4291777291
Short name T287
Test name
Test status
Simulation time 12851585214 ps
CPU time 36.68 seconds
Started Jun 10 05:40:31 PM PDT 24
Finished Jun 10 05:41:08 PM PDT 24
Peak memory 213424 kb
Host smart-eb54f1b1-a9b2-4ce2-a2f8-4b8a817194b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291777291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.4291777291
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3034484350
Short name T404
Test name
Test status
Simulation time 240374611 ps
CPU time 1.67 seconds
Started Jun 10 05:40:31 PM PDT 24
Finished Jun 10 05:40:33 PM PDT 24
Peak memory 213180 kb
Host smart-446a5499-8d16-4ea3-8795-7601c1a77084
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034484350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3034484350
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2577045669
Short name T83
Test name
Test status
Simulation time 4650809187 ps
CPU time 7.44 seconds
Started Jun 10 05:40:29 PM PDT 24
Finished Jun 10 05:40:36 PM PDT 24
Peak memory 219812 kb
Host smart-c70c90cb-edbe-484c-8d89-8106729b2597
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577045669 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2577045669
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.481738279
Short name T291
Test name
Test status
Simulation time 122136487 ps
CPU time 2.35 seconds
Started Jun 10 05:40:33 PM PDT 24
Finished Jun 10 05:40:36 PM PDT 24
Peak memory 213280 kb
Host smart-303fc828-652e-4e75-ab9e-9c363b623be7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481738279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.481738279
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4277607763
Short name T272
Test name
Test status
Simulation time 21819442683 ps
CPU time 35.91 seconds
Started Jun 10 05:40:30 PM PDT 24
Finished Jun 10 05:41:06 PM PDT 24
Peak memory 205032 kb
Host smart-70039e03-c333-4dba-a2cf-c12c5c2c2d29
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277607763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.4277607763
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2064758658
Short name T339
Test name
Test status
Simulation time 53990271024 ps
CPU time 42.38 seconds
Started Jun 10 05:40:31 PM PDT 24
Finished Jun 10 05:41:14 PM PDT 24
Peak memory 205052 kb
Host smart-0bfffa36-b354-4f4d-bedd-8b0c041184d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064758658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.2064758658
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1560870231
Short name T99
Test name
Test status
Simulation time 5181038626 ps
CPU time 15.09 seconds
Started Jun 10 05:40:29 PM PDT 24
Finished Jun 10 05:40:45 PM PDT 24
Peak memory 205164 kb
Host smart-84452723-91bb-4a67-bf5a-f9388d7472d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560870231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1560870231
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3710383430
Short name T313
Test name
Test status
Simulation time 3186075237 ps
CPU time 5.22 seconds
Started Jun 10 05:40:31 PM PDT 24
Finished Jun 10 05:40:36 PM PDT 24
Peak memory 205056 kb
Host smart-c0df2fab-0611-46c1-b7c5-962a1719262e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710383430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
710383430
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2500197556
Short name T309
Test name
Test status
Simulation time 1318892099 ps
CPU time 3.79 seconds
Started Jun 10 05:40:32 PM PDT 24
Finished Jun 10 05:40:36 PM PDT 24
Peak memory 204720 kb
Host smart-a67580b1-4e58-4db9-b7d6-85b2b6051861
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500197556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2500197556
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2890033523
Short name T332
Test name
Test status
Simulation time 9922621764 ps
CPU time 15.2 seconds
Started Jun 10 05:40:29 PM PDT 24
Finished Jun 10 05:40:45 PM PDT 24
Peak memory 205040 kb
Host smart-247dd2ea-3948-4212-9378-1f1ad24be632
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890033523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2890033523
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3538638682
Short name T299
Test name
Test status
Simulation time 814630695 ps
CPU time 0.91 seconds
Started Jun 10 05:40:29 PM PDT 24
Finished Jun 10 05:40:31 PM PDT 24
Peak memory 204736 kb
Host smart-ef18ff5e-34ae-4602-96ba-693be39bfdd0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538638682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3538638682
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.4230030339
Short name T343
Test name
Test status
Simulation time 1289285463 ps
CPU time 4.21 seconds
Started Jun 10 05:40:33 PM PDT 24
Finished Jun 10 05:40:38 PM PDT 24
Peak memory 204728 kb
Host smart-f84f2a57-75cd-4da5-8809-450642d89ec2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230030339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.4
230030339
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.445318840
Short name T274
Test name
Test status
Simulation time 67981936 ps
CPU time 0.71 seconds
Started Jun 10 05:40:31 PM PDT 24
Finished Jun 10 05:40:32 PM PDT 24
Peak memory 204648 kb
Host smart-29241473-cd56-4a25-9993-7788778b0904
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445318840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.445318840
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.169337182
Short name T279
Test name
Test status
Simulation time 70879973 ps
CPU time 0.68 seconds
Started Jun 10 05:40:28 PM PDT 24
Finished Jun 10 05:40:29 PM PDT 24
Peak memory 204724 kb
Host smart-49f3b0c1-6425-4966-b6b8-a2b74d5ac0ae
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169337182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.169337182
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2101615957
Short name T123
Test name
Test status
Simulation time 1853422572 ps
CPU time 7.26 seconds
Started Jun 10 05:40:30 PM PDT 24
Finished Jun 10 05:40:37 PM PDT 24
Peak memory 205060 kb
Host smart-9f948d64-712e-4c8c-836d-2d04c4fed631
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101615957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2101615957
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.923940360
Short name T361
Test name
Test status
Simulation time 22562029819 ps
CPU time 35.87 seconds
Started Jun 10 05:40:26 PM PDT 24
Finished Jun 10 05:41:02 PM PDT 24
Peak memory 221548 kb
Host smart-3f5cbd94-c6a6-4aa0-879d-f1d02dad5383
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923940360 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.923940360
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1273919510
Short name T288
Test name
Test status
Simulation time 149742221 ps
CPU time 2.25 seconds
Started Jun 10 05:40:31 PM PDT 24
Finished Jun 10 05:40:34 PM PDT 24
Peak memory 213328 kb
Host smart-aee83a48-5323-4515-adca-e19570a831b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273919510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1273919510
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4163029150
Short name T53
Test name
Test status
Simulation time 1715463330 ps
CPU time 20.8 seconds
Started Jun 10 05:40:31 PM PDT 24
Finished Jun 10 05:40:52 PM PDT 24
Peak memory 213336 kb
Host smart-2c5c8335-3139-4194-a305-d02c07b6ec88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163029150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.4163029150
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2961579980
Short name T402
Test name
Test status
Simulation time 273986517 ps
CPU time 3.21 seconds
Started Jun 10 05:40:38 PM PDT 24
Finished Jun 10 05:40:42 PM PDT 24
Peak memory 217848 kb
Host smart-14a7a8bb-bfcc-46b7-aaa2-6bbd57bd7f7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961579980 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2961579980
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.538983363
Short name T356
Test name
Test status
Simulation time 105606670 ps
CPU time 2.26 seconds
Started Jun 10 05:40:33 PM PDT 24
Finished Jun 10 05:40:36 PM PDT 24
Peak memory 213324 kb
Host smart-b5dab7e9-7143-4dd9-9bb4-beda65649009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538983363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.538983363
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.266453667
Short name T302
Test name
Test status
Simulation time 10942478589 ps
CPU time 29.54 seconds
Started Jun 10 05:40:29 PM PDT 24
Finished Jun 10 05:40:59 PM PDT 24
Peak memory 205068 kb
Host smart-b3fd8917-430b-4fb5-ae12-0b6ecd29cf59
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266453667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r
v_dm_jtag_dmi_csr_bit_bash.266453667
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2335151671
Short name T372
Test name
Test status
Simulation time 5089289898 ps
CPU time 15.02 seconds
Started Jun 10 05:40:28 PM PDT 24
Finished Jun 10 05:40:43 PM PDT 24
Peak memory 204988 kb
Host smart-2e0df115-7cda-4df1-a59d-02111dfe6611
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335151671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
335151671
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.541886045
Short name T349
Test name
Test status
Simulation time 355916142 ps
CPU time 1.17 seconds
Started Jun 10 05:40:30 PM PDT 24
Finished Jun 10 05:40:32 PM PDT 24
Peak memory 204664 kb
Host smart-d46527a5-400b-4d82-9583-9152da57c1cc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541886045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.541886045
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3281231059
Short name T385
Test name
Test status
Simulation time 463565133 ps
CPU time 4.37 seconds
Started Jun 10 05:40:38 PM PDT 24
Finished Jun 10 05:40:43 PM PDT 24
Peak memory 205120 kb
Host smart-b979d45a-5451-4763-bd4b-7baa0f42a2e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281231059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3281231059
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1786592106
Short name T354
Test name
Test status
Simulation time 71102386852 ps
CPU time 26.54 seconds
Started Jun 10 05:40:30 PM PDT 24
Finished Jun 10 05:40:57 PM PDT 24
Peak memory 229888 kb
Host smart-9e48c3bc-895b-477a-b6fd-410daf639544
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786592106 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.1786592106
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1723918125
Short name T340
Test name
Test status
Simulation time 432162042 ps
CPU time 5.34 seconds
Started Jun 10 05:40:36 PM PDT 24
Finished Jun 10 05:40:42 PM PDT 24
Peak memory 213316 kb
Host smart-e5b0ae3e-5842-44cd-8469-d1ba53c381ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723918125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1723918125
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3257684501
Short name T139
Test name
Test status
Simulation time 2048869729 ps
CPU time 9.46 seconds
Started Jun 10 05:40:37 PM PDT 24
Finished Jun 10 05:40:47 PM PDT 24
Peak memory 213320 kb
Host smart-ad1b3448-b0bd-4ea1-80ba-e3dd5b7a5bac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257684501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3257684501
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2481707255
Short name T130
Test name
Test status
Simulation time 3388878361 ps
CPU time 6.84 seconds
Started Jun 10 05:40:41 PM PDT 24
Finished Jun 10 05:40:49 PM PDT 24
Peak memory 213324 kb
Host smart-3ecb1343-e87e-4f23-a823-42c195d11db2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481707255 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2481707255
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3527680170
Short name T113
Test name
Test status
Simulation time 82686817 ps
CPU time 2.22 seconds
Started Jun 10 05:40:34 PM PDT 24
Finished Jun 10 05:40:37 PM PDT 24
Peak memory 213276 kb
Host smart-5c3025dd-a2e0-418e-8649-c966177c9d97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527680170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3527680170
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2143767320
Short name T285
Test name
Test status
Simulation time 11397159439 ps
CPU time 12.53 seconds
Started Jun 10 05:40:31 PM PDT 24
Finished Jun 10 05:40:44 PM PDT 24
Peak memory 205016 kb
Host smart-1b74c65b-2b56-44ad-9224-5819119c0047
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143767320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.2143767320
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1120178012
Short name T366
Test name
Test status
Simulation time 2033372292 ps
CPU time 2.18 seconds
Started Jun 10 05:40:41 PM PDT 24
Finished Jun 10 05:40:44 PM PDT 24
Peak memory 204828 kb
Host smart-fc5c0e31-f2ea-4cae-903b-e8556fc93edd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120178012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
120178012
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2676284098
Short name T363
Test name
Test status
Simulation time 631053089 ps
CPU time 1.18 seconds
Started Jun 10 05:40:37 PM PDT 24
Finished Jun 10 05:40:39 PM PDT 24
Peak memory 204740 kb
Host smart-e934fb2d-cfff-428e-b438-5d7eec53397c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676284098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
676284098
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.661343053
Short name T399
Test name
Test status
Simulation time 10335168439 ps
CPU time 31.34 seconds
Started Jun 10 05:40:33 PM PDT 24
Finished Jun 10 05:41:05 PM PDT 24
Peak memory 219432 kb
Host smart-b1d71a92-b85a-4543-916c-e7c0eebe0d6e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661343053 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.661343053
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.715248520
Short name T397
Test name
Test status
Simulation time 418042333 ps
CPU time 2.23 seconds
Started Jun 10 05:40:37 PM PDT 24
Finished Jun 10 05:40:40 PM PDT 24
Peak memory 213296 kb
Host smart-0876835b-aaec-428b-8c28-4d3cb4146e42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715248520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.715248520
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1137974164
Short name T137
Test name
Test status
Simulation time 1303821321 ps
CPU time 10.86 seconds
Started Jun 10 05:40:38 PM PDT 24
Finished Jun 10 05:40:49 PM PDT 24
Peak memory 213368 kb
Host smart-e76196c2-4aa4-41bf-af6f-70c5572d2690
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137974164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1137974164
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2381568434
Short name T351
Test name
Test status
Simulation time 1662036914 ps
CPU time 3.43 seconds
Started Jun 10 05:40:37 PM PDT 24
Finished Jun 10 05:40:41 PM PDT 24
Peak memory 213376 kb
Host smart-885bbb01-6253-4ada-a147-d69ccec0cdf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381568434 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2381568434
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2537199819
Short name T119
Test name
Test status
Simulation time 199315322 ps
CPU time 1.54 seconds
Started Jun 10 05:40:38 PM PDT 24
Finished Jun 10 05:40:40 PM PDT 24
Peak memory 213108 kb
Host smart-9b00a1b8-62bc-4e78-a307-0f5ac0481098
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537199819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2537199819
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1990142607
Short name T284
Test name
Test status
Simulation time 12449505664 ps
CPU time 18.92 seconds
Started Jun 10 05:40:36 PM PDT 24
Finished Jun 10 05:40:56 PM PDT 24
Peak memory 205032 kb
Host smart-bf547935-082a-4c7d-b242-9cd302c0c984
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990142607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.1990142607
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1021936507
Short name T384
Test name
Test status
Simulation time 2839430126 ps
CPU time 3.7 seconds
Started Jun 10 05:40:35 PM PDT 24
Finished Jun 10 05:40:39 PM PDT 24
Peak memory 204972 kb
Host smart-1eda20b6-8ea8-4157-a8df-d331e9a54e60
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021936507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
021936507
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1134063363
Short name T371
Test name
Test status
Simulation time 244816121 ps
CPU time 0.9 seconds
Started Jun 10 05:40:39 PM PDT 24
Finished Jun 10 05:40:40 PM PDT 24
Peak memory 204524 kb
Host smart-4a84cacc-bf4e-4e8b-9760-db23b22d1efd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134063363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
134063363
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3816690478
Short name T112
Test name
Test status
Simulation time 1190485184 ps
CPU time 4.17 seconds
Started Jun 10 05:40:42 PM PDT 24
Finished Jun 10 05:40:46 PM PDT 24
Peak memory 205092 kb
Host smart-5af52249-cfa4-49e8-bc1f-8d43f8d167a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816690478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3816690478
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4053854698
Short name T142
Test name
Test status
Simulation time 34545017724 ps
CPU time 93.15 seconds
Started Jun 10 05:40:42 PM PDT 24
Finished Jun 10 05:42:15 PM PDT 24
Peak memory 220480 kb
Host smart-a4700d19-831d-4ea8-905d-7d3c05b8b459
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053854698 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.4053854698
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3619471393
Short name T308
Test name
Test status
Simulation time 425349671 ps
CPU time 2.7 seconds
Started Jun 10 05:40:35 PM PDT 24
Finished Jun 10 05:40:39 PM PDT 24
Peak memory 213316 kb
Host smart-42eaf99f-5751-4a37-819b-ad298bcf9dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619471393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3619471393
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.889319554
Short name T131
Test name
Test status
Simulation time 1349503850 ps
CPU time 18.07 seconds
Started Jun 10 05:40:37 PM PDT 24
Finished Jun 10 05:40:56 PM PDT 24
Peak memory 213336 kb
Host smart-64fb3c81-071a-4120-a94f-d9d3c2bdeace
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889319554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.889319554
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3089748617
Short name T388
Test name
Test status
Simulation time 6459014433 ps
CPU time 8.4 seconds
Started Jun 10 05:40:40 PM PDT 24
Finished Jun 10 05:40:49 PM PDT 24
Peak memory 221360 kb
Host smart-bf4e3b8a-2322-4461-8d55-ae958752a8c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089748617 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3089748617
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1563192264
Short name T120
Test name
Test status
Simulation time 216707570 ps
CPU time 2.45 seconds
Started Jun 10 05:40:41 PM PDT 24
Finished Jun 10 05:40:44 PM PDT 24
Peak memory 213484 kb
Host smart-a2313922-ce9e-473e-9baa-be96c9f80818
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563192264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1563192264
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.519158099
Short name T282
Test name
Test status
Simulation time 53654033276 ps
CPU time 47.92 seconds
Started Jun 10 05:40:49 PM PDT 24
Finished Jun 10 05:41:38 PM PDT 24
Peak memory 204944 kb
Host smart-2eb0e82c-ce6d-4457-92c2-b58d92fe56c9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519158099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
v_dm_jtag_dmi_csr_bit_bash.519158099
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.31995540
Short name T380
Test name
Test status
Simulation time 3733487473 ps
CPU time 3.66 seconds
Started Jun 10 05:40:34 PM PDT 24
Finished Jun 10 05:40:39 PM PDT 24
Peak memory 205032 kb
Host smart-198fa23b-9fb6-423b-85f9-8fd89ae4dd44
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31995540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.31995540
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2632152448
Short name T383
Test name
Test status
Simulation time 237207852 ps
CPU time 1.37 seconds
Started Jun 10 05:40:34 PM PDT 24
Finished Jun 10 05:40:35 PM PDT 24
Peak memory 204752 kb
Host smart-8ebc6845-7f2d-4adc-af76-3162e779707f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632152448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
632152448
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3734210195
Short name T124
Test name
Test status
Simulation time 563655090 ps
CPU time 7.94 seconds
Started Jun 10 05:40:44 PM PDT 24
Finished Jun 10 05:40:52 PM PDT 24
Peak memory 205096 kb
Host smart-d3883712-f64d-419c-9eb8-fea2bd2311a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734210195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.3734210195
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.4047888308
Short name T333
Test name
Test status
Simulation time 204403677 ps
CPU time 2.6 seconds
Started Jun 10 05:40:39 PM PDT 24
Finished Jun 10 05:40:42 PM PDT 24
Peak memory 213328 kb
Host smart-363f1438-68a1-4f8a-8205-ef3fc03a356c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047888308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.4047888308
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.506657608
Short name T97
Test name
Test status
Simulation time 758555290 ps
CPU time 8.54 seconds
Started Jun 10 05:40:45 PM PDT 24
Finished Jun 10 05:40:54 PM PDT 24
Peak memory 213328 kb
Host smart-52e706db-eeaa-47b6-a2ab-48d6acd29755
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506657608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.506657608
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.115092875
Short name T373
Test name
Test status
Simulation time 557537756 ps
CPU time 3.82 seconds
Started Jun 10 05:40:46 PM PDT 24
Finished Jun 10 05:40:50 PM PDT 24
Peak memory 218264 kb
Host smart-e45305a7-6ee9-4a2d-8141-565df2bb8c78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115092875 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.115092875
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2424731014
Short name T374
Test name
Test status
Simulation time 424027856 ps
CPU time 2.38 seconds
Started Jun 10 05:40:37 PM PDT 24
Finished Jun 10 05:40:40 PM PDT 24
Peak memory 213312 kb
Host smart-45e256ab-cca6-47d0-977a-48786ba07486
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424731014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2424731014
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.797350004
Short name T312
Test name
Test status
Simulation time 17740220422 ps
CPU time 47.73 seconds
Started Jun 10 05:40:38 PM PDT 24
Finished Jun 10 05:41:26 PM PDT 24
Peak memory 205008 kb
Host smart-d6c6ac23-9b5e-4504-8976-f94593049dfa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797350004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r
v_dm_jtag_dmi_csr_bit_bash.797350004
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4076413268
Short name T414
Test name
Test status
Simulation time 1247640962 ps
CPU time 1.9 seconds
Started Jun 10 05:40:44 PM PDT 24
Finished Jun 10 05:40:46 PM PDT 24
Peak memory 204924 kb
Host smart-6c363084-799d-4ad5-a1b1-dee7dcc68bbe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076413268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.4
076413268
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.424923359
Short name T367
Test name
Test status
Simulation time 457421904 ps
CPU time 1.93 seconds
Started Jun 10 05:40:44 PM PDT 24
Finished Jun 10 05:40:47 PM PDT 24
Peak memory 204700 kb
Host smart-94e2f676-7201-4153-965a-b52904a0fced
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424923359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.424923359
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.4209770126
Short name T403
Test name
Test status
Simulation time 182278984 ps
CPU time 3.62 seconds
Started Jun 10 05:40:43 PM PDT 24
Finished Jun 10 05:40:47 PM PDT 24
Peak memory 205044 kb
Host smart-d2ae5977-6f97-4527-8dc8-596bb0488cef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209770126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.4209770126
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.635753412
Short name T386
Test name
Test status
Simulation time 94961015063 ps
CPU time 91.94 seconds
Started Jun 10 05:40:41 PM PDT 24
Finished Jun 10 05:42:13 PM PDT 24
Peak memory 225688 kb
Host smart-be65631c-c68f-4b53-836c-e450d4b5c1e5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635753412 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.635753412
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3527401188
Short name T360
Test name
Test status
Simulation time 804186034 ps
CPU time 4.63 seconds
Started Jun 10 05:40:47 PM PDT 24
Finished Jun 10 05:40:52 PM PDT 24
Peak memory 213312 kb
Host smart-fe8a7f36-48f6-4873-a428-18de2287a27d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527401188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3527401188
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.4047086209
Short name T289
Test name
Test status
Simulation time 3035275994 ps
CPU time 10.6 seconds
Started Jun 10 05:40:41 PM PDT 24
Finished Jun 10 05:40:52 PM PDT 24
Peak memory 213320 kb
Host smart-d20e7ccc-f253-455b-9e10-0a459691c207
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047086209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.4047086209
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3990005532
Short name T76
Test name
Test status
Simulation time 35147113 ps
CPU time 0.8 seconds
Started Jun 10 05:41:04 PM PDT 24
Finished Jun 10 05:41:05 PM PDT 24
Peak memory 204804 kb
Host smart-97a31c8c-fc5d-414b-a4be-806ef2631e4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990005532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3990005532
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3103367000
Short name T68
Test name
Test status
Simulation time 7551872052 ps
CPU time 7.8 seconds
Started Jun 10 05:40:51 PM PDT 24
Finished Jun 10 05:40:59 PM PDT 24
Peak memory 205460 kb
Host smart-760e21a5-c1ee-4645-a802-94d90fb8ae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103367000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3103367000
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1648211231
Short name T12
Test name
Test status
Simulation time 10009923001 ps
CPU time 12.14 seconds
Started Jun 10 05:41:03 PM PDT 24
Finished Jun 10 05:41:15 PM PDT 24
Peak memory 205036 kb
Host smart-b651f75e-9d1a-467c-a36a-fb6a4237e325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648211231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1648211231
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3002210320
Short name T19
Test name
Test status
Simulation time 9600030816 ps
CPU time 28.97 seconds
Started Jun 10 05:40:57 PM PDT 24
Finished Jun 10 05:41:26 PM PDT 24
Peak memory 205024 kb
Host smart-d7b8455a-8e67-4516-9166-f3d0a4b8c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002210320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3002210320
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2798539916
Short name T16
Test name
Test status
Simulation time 198679770 ps
CPU time 0.93 seconds
Started Jun 10 05:41:09 PM PDT 24
Finished Jun 10 05:41:10 PM PDT 24
Peak memory 204696 kb
Host smart-24cedbec-8336-4c11-9f1f-9fb0eef68dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798539916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2798539916
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3940232331
Short name T235
Test name
Test status
Simulation time 2219706488 ps
CPU time 6.46 seconds
Started Jun 10 05:40:57 PM PDT 24
Finished Jun 10 05:41:04 PM PDT 24
Peak memory 205252 kb
Host smart-f1ad0c5a-29d6-4ae0-a0fe-65cec0c7d2d3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3940232331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3940232331
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2965841580
Short name T86
Test name
Test status
Simulation time 572218603 ps
CPU time 1.19 seconds
Started Jun 10 05:40:58 PM PDT 24
Finished Jun 10 05:41:00 PM PDT 24
Peak memory 204728 kb
Host smart-4ae83cce-d429-4725-bc06-6c525669aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965841580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2965841580
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1889510089
Short name T194
Test name
Test status
Simulation time 537094560 ps
CPU time 1.15 seconds
Started Jun 10 05:40:57 PM PDT 24
Finished Jun 10 05:40:59 PM PDT 24
Peak memory 204616 kb
Host smart-29948547-3f3b-49be-8a67-ddde59fd76cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889510089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1889510089
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1047357294
Short name T46
Test name
Test status
Simulation time 930448888 ps
CPU time 1.09 seconds
Started Jun 10 05:40:56 PM PDT 24
Finished Jun 10 05:40:57 PM PDT 24
Peak memory 204568 kb
Host smart-4281f1f6-82bc-4820-9bab-101d2d204422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047357294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1047357294
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1867184594
Short name T242
Test name
Test status
Simulation time 2159218937 ps
CPU time 2.31 seconds
Started Jun 10 05:40:58 PM PDT 24
Finished Jun 10 05:41:01 PM PDT 24
Peak memory 204844 kb
Host smart-dbefd36f-1e14-45db-ac17-5eedec5ecc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867184594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1867184594
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.4007496386
Short name T261
Test name
Test status
Simulation time 1536959897 ps
CPU time 5.64 seconds
Started Jun 10 05:40:58 PM PDT 24
Finished Jun 10 05:41:04 PM PDT 24
Peak memory 204904 kb
Host smart-9cca61a6-4d87-46b4-b8ae-1c4c0b0cdfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007496386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.4007496386
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3962413737
Short name T44
Test name
Test status
Simulation time 244822178 ps
CPU time 1.2 seconds
Started Jun 10 05:40:57 PM PDT 24
Finished Jun 10 05:40:59 PM PDT 24
Peak memory 204628 kb
Host smart-9f2e2dbd-65ac-4772-bc69-bfca667361bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962413737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3962413737
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1260613319
Short name T182
Test name
Test status
Simulation time 141886819 ps
CPU time 1.12 seconds
Started Jun 10 05:41:04 PM PDT 24
Finished Jun 10 05:41:05 PM PDT 24
Peak memory 204708 kb
Host smart-b249f311-5eb9-4f58-ab16-84737929d406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260613319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1260613319
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3379233496
Short name T15
Test name
Test status
Simulation time 2226225171 ps
CPU time 2.16 seconds
Started Jun 10 05:40:57 PM PDT 24
Finished Jun 10 05:41:00 PM PDT 24
Peak memory 204788 kb
Host smart-87abd56a-8517-475e-8a30-f36290caa960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379233496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3379233496
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3173384696
Short name T87
Test name
Test status
Simulation time 441046760 ps
CPU time 1.46 seconds
Started Jun 10 05:41:06 PM PDT 24
Finished Jun 10 05:41:08 PM PDT 24
Peak memory 204700 kb
Host smart-da687a6a-063f-4de9-bde7-f21c568aa9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173384696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3173384696
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2161208140
Short name T49
Test name
Test status
Simulation time 12158471664 ps
CPU time 31.22 seconds
Started Jun 10 05:41:06 PM PDT 24
Finished Jun 10 05:41:37 PM PDT 24
Peak memory 205220 kb
Host smart-fea362d4-65e2-4b43-80de-48115fb98d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161208140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2161208140
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3491892021
Short name T40
Test name
Test status
Simulation time 719294226 ps
CPU time 2.88 seconds
Started Jun 10 05:41:08 PM PDT 24
Finished Jun 10 05:41:11 PM PDT 24
Peak memory 237164 kb
Host smart-f2c60c52-49bd-4da5-8f44-13acee942183
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491892021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3491892021
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2444876895
Short name T180
Test name
Test status
Simulation time 2674952559 ps
CPU time 7.76 seconds
Started Jun 10 05:40:51 PM PDT 24
Finished Jun 10 05:41:00 PM PDT 24
Peak memory 204704 kb
Host smart-3a74ee5d-8258-4b02-88a2-f07075d6b654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444876895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2444876895
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1590848682
Short name T33
Test name
Test status
Simulation time 207764515 ps
CPU time 1.04 seconds
Started Jun 10 05:41:05 PM PDT 24
Finished Jun 10 05:41:06 PM PDT 24
Peak memory 204740 kb
Host smart-d8bd07e0-d442-4685-ba4c-ca99f11508e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590848682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1590848682
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3656566763
Short name T263
Test name
Test status
Simulation time 47358363 ps
CPU time 0.72 seconds
Started Jun 10 05:41:05 PM PDT 24
Finished Jun 10 05:41:07 PM PDT 24
Peak memory 204800 kb
Host smart-e6264066-bf21-4a01-89a8-0c702e9471ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656566763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3656566763
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3325300866
Short name T205
Test name
Test status
Simulation time 10116235087 ps
CPU time 31.01 seconds
Started Jun 10 05:40:57 PM PDT 24
Finished Jun 10 05:41:29 PM PDT 24
Peak memory 213340 kb
Host smart-8c8a5f49-50ed-43e7-9e79-657d497a7376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325300866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3325300866
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1876762673
Short name T257
Test name
Test status
Simulation time 8215256266 ps
CPU time 12.8 seconds
Started Jun 10 05:40:59 PM PDT 24
Finished Jun 10 05:41:12 PM PDT 24
Peak memory 213452 kb
Host smart-89760ee4-4f56-4f75-becc-2c576f6ce212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876762673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1876762673
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2538892329
Short name T13
Test name
Test status
Simulation time 13313697377 ps
CPU time 11.1 seconds
Started Jun 10 05:41:00 PM PDT 24
Finished Jun 10 05:41:11 PM PDT 24
Peak memory 205112 kb
Host smart-f6f80ff1-b69d-4502-9058-99eb787b4591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538892329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2538892329
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2985544324
Short name T27
Test name
Test status
Simulation time 1241412503 ps
CPU time 2.61 seconds
Started Jun 10 05:40:56 PM PDT 24
Finished Jun 10 05:40:59 PM PDT 24
Peak memory 204684 kb
Host smart-562789d9-ad7f-4732-947a-f72c26112f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985544324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2985544324
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1302809281
Short name T21
Test name
Test status
Simulation time 2211177009 ps
CPU time 3.9 seconds
Started Jun 10 05:41:03 PM PDT 24
Finished Jun 10 05:41:07 PM PDT 24
Peak memory 204712 kb
Host smart-5ae35399-8be3-4aa3-947f-b9d6125688c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302809281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1302809281
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.152068464
Short name T20
Test name
Test status
Simulation time 8766934886 ps
CPU time 7.18 seconds
Started Jun 10 05:40:56 PM PDT 24
Finished Jun 10 05:41:04 PM PDT 24
Peak memory 204964 kb
Host smart-3bba6efb-983f-4f3d-8ea6-dc1ad425b017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152068464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.152068464
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2658838445
Short name T151
Test name
Test status
Simulation time 135432188 ps
CPU time 0.82 seconds
Started Jun 10 05:41:06 PM PDT 24
Finished Jun 10 05:41:07 PM PDT 24
Peak memory 204728 kb
Host smart-30633a75-8357-4cb6-9e8e-9674f13dec52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658838445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2658838445
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2873638597
Short name T197
Test name
Test status
Simulation time 1353303654 ps
CPU time 2.22 seconds
Started Jun 10 05:40:57 PM PDT 24
Finished Jun 10 05:40:59 PM PDT 24
Peak memory 205064 kb
Host smart-435a4ce5-e30a-4890-8f8e-c848a6702c57
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2873638597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2873638597
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1516584255
Short name T26
Test name
Test status
Simulation time 2622830104 ps
CPU time 4.4 seconds
Started Jun 10 05:40:59 PM PDT 24
Finished Jun 10 05:41:04 PM PDT 24
Peak memory 204956 kb
Host smart-1acd368b-f4d4-4a23-be9e-66306b14001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516584255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1516584255
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3900474147
Short name T11
Test name
Test status
Simulation time 196809784 ps
CPU time 0.74 seconds
Started Jun 10 05:41:07 PM PDT 24
Finished Jun 10 05:41:08 PM PDT 24
Peak memory 204628 kb
Host smart-e2ad6910-2fcc-4580-b2f9-0c4a373478bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900474147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3900474147
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1862726170
Short name T236
Test name
Test status
Simulation time 571586336 ps
CPU time 2.27 seconds
Started Jun 10 05:41:00 PM PDT 24
Finished Jun 10 05:41:03 PM PDT 24
Peak memory 204616 kb
Host smart-cc823549-f42d-49a8-b7a9-d68ed3f39814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862726170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1862726170
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2905605631
Short name T250
Test name
Test status
Simulation time 621779200 ps
CPU time 1.13 seconds
Started Jun 10 05:41:06 PM PDT 24
Finished Jun 10 05:41:08 PM PDT 24
Peak memory 204600 kb
Host smart-358d4349-8d9c-4b26-bd12-e1992e5fbaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905605631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2905605631
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1561241816
Short name T203
Test name
Test status
Simulation time 3236073356 ps
CPU time 2.56 seconds
Started Jun 10 05:41:06 PM PDT 24
Finished Jun 10 05:41:09 PM PDT 24
Peak memory 204548 kb
Host smart-503a85bd-70d1-436a-9639-9802157add69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561241816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1561241816
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1406512786
Short name T231
Test name
Test status
Simulation time 118580618 ps
CPU time 0.84 seconds
Started Jun 10 05:41:00 PM PDT 24
Finished Jun 10 05:41:02 PM PDT 24
Peak memory 204556 kb
Host smart-33947f0d-032b-45ac-b6bb-5ffefb6291d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406512786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1406512786
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3382396651
Short name T256
Test name
Test status
Simulation time 201753450 ps
CPU time 0.81 seconds
Started Jun 10 05:41:10 PM PDT 24
Finished Jun 10 05:41:11 PM PDT 24
Peak memory 204704 kb
Host smart-9c1c2450-1c3f-4a13-981d-2276312db6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382396651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3382396651
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3832751324
Short name T10
Test name
Test status
Simulation time 897105684 ps
CPU time 3.21 seconds
Started Jun 10 05:40:57 PM PDT 24
Finished Jun 10 05:41:01 PM PDT 24
Peak memory 204912 kb
Host smart-fb49d14f-530e-4351-94ff-2103cfc177be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832751324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3832751324
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.4177836310
Short name T251
Test name
Test status
Simulation time 3906872285 ps
CPU time 11.21 seconds
Started Jun 10 05:41:03 PM PDT 24
Finished Jun 10 05:41:15 PM PDT 24
Peak memory 204884 kb
Host smart-ce08385e-b100-45a2-b479-1e533178a135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177836310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.4177836310
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.4127826863
Short name T7
Test name
Test status
Simulation time 199549099 ps
CPU time 1.33 seconds
Started Jun 10 05:41:09 PM PDT 24
Finished Jun 10 05:41:10 PM PDT 24
Peak memory 204864 kb
Host smart-f5151d29-299e-43df-a5b1-86a8cac95868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127826863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.4127826863
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2452902
Short name T31
Test name
Test status
Simulation time 465704517 ps
CPU time 0.81 seconds
Started Jun 10 05:41:05 PM PDT 24
Finished Jun 10 05:41:07 PM PDT 24
Peak memory 204712 kb
Host smart-78100816-c2ac-4ee4-b7eb-0666450ab113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2452902
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3549070327
Short name T24
Test name
Test status
Simulation time 116382986 ps
CPU time 0.8 seconds
Started Jun 10 05:41:11 PM PDT 24
Finished Jun 10 05:41:12 PM PDT 24
Peak memory 212956 kb
Host smart-34881d9e-de9e-4f1a-a749-005e73c04818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549070327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3549070327
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1032397236
Short name T200
Test name
Test status
Simulation time 10152017225 ps
CPU time 28.35 seconds
Started Jun 10 05:40:57 PM PDT 24
Finished Jun 10 05:41:25 PM PDT 24
Peak memory 205208 kb
Host smart-03035f50-9c13-48c4-ad33-e144b6d21c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032397236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1032397236
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3515169889
Short name T62
Test name
Test status
Simulation time 2592028558 ps
CPU time 3.15 seconds
Started Jun 10 05:41:09 PM PDT 24
Finished Jun 10 05:41:15 PM PDT 24
Peak memory 229132 kb
Host smart-b6e3fe77-0096-479c-a0e1-034dd83ec4db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515169889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3515169889
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2240201456
Short name T253
Test name
Test status
Simulation time 1248240389 ps
CPU time 1.63 seconds
Started Jun 10 05:41:00 PM PDT 24
Finished Jun 10 05:41:02 PM PDT 24
Peak memory 204604 kb
Host smart-586cb30c-637e-4eec-936c-904e3b2cb039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240201456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2240201456
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2992750063
Short name T188
Test name
Test status
Simulation time 39345468 ps
CPU time 0.72 seconds
Started Jun 10 05:41:17 PM PDT 24
Finished Jun 10 05:41:18 PM PDT 24
Peak memory 204820 kb
Host smart-b492b73a-adab-4313-853e-b2468e119b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992750063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2992750063
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3575460742
Short name T228
Test name
Test status
Simulation time 22137245024 ps
CPU time 14.27 seconds
Started Jun 10 05:41:11 PM PDT 24
Finished Jun 10 05:41:26 PM PDT 24
Peak memory 213464 kb
Host smart-36f2136e-deb6-4d14-8b75-e983a3c30cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575460742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3575460742
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1768781837
Short name T198
Test name
Test status
Simulation time 5062166836 ps
CPU time 6.76 seconds
Started Jun 10 05:41:12 PM PDT 24
Finished Jun 10 05:41:19 PM PDT 24
Peak memory 214536 kb
Host smart-1cfd4b5e-c38c-4f78-98a2-c2b5f7b4da02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768781837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1768781837
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.4062238469
Short name T223
Test name
Test status
Simulation time 976128592 ps
CPU time 1.54 seconds
Started Jun 10 05:41:15 PM PDT 24
Finished Jun 10 05:41:17 PM PDT 24
Peak memory 205064 kb
Host smart-bba98819-ec28-451d-84ef-e498ededc778
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4062238469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.4062238469
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1109549524
Short name T226
Test name
Test status
Simulation time 8265569770 ps
CPU time 6.42 seconds
Started Jun 10 05:41:15 PM PDT 24
Finished Jun 10 05:41:22 PM PDT 24
Peak memory 205204 kb
Host smart-6edc54fa-d058-4726-84cd-58fa8f2d3b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109549524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1109549524
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.2789728546
Short name T149
Test name
Test status
Simulation time 4791688487 ps
CPU time 7.55 seconds
Started Jun 10 05:41:14 PM PDT 24
Finished Jun 10 05:41:22 PM PDT 24
Peak memory 213196 kb
Host smart-a0b98837-a09e-4526-b59f-f5b49a4add4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789728546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2789728546
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3504232221
Short name T78
Test name
Test status
Simulation time 54881172 ps
CPU time 0.85 seconds
Started Jun 10 05:41:43 PM PDT 24
Finished Jun 10 05:41:44 PM PDT 24
Peak memory 204720 kb
Host smart-a680d8bc-9a14-4b40-a16c-7854f507a8f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504232221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3504232221
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1210980764
Short name T227
Test name
Test status
Simulation time 11814194242 ps
CPU time 8.18 seconds
Started Jun 10 05:41:15 PM PDT 24
Finished Jun 10 05:41:24 PM PDT 24
Peak memory 213504 kb
Host smart-9dab783e-3429-4db0-b5f3-8c44984fe533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210980764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1210980764
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.989241070
Short name T249
Test name
Test status
Simulation time 2897471603 ps
CPU time 9 seconds
Started Jun 10 05:41:13 PM PDT 24
Finished Jun 10 05:41:22 PM PDT 24
Peak memory 205284 kb
Host smart-d9da0c22-d6b6-48c8-9da6-f378e0937cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989241070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.989241070
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.888555291
Short name T232
Test name
Test status
Simulation time 2561145883 ps
CPU time 3.38 seconds
Started Jun 10 05:41:26 PM PDT 24
Finished Jun 10 05:41:34 PM PDT 24
Peak memory 205164 kb
Host smart-1cd69326-aa48-478d-bad1-077cd8512045
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888555291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.888555291
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.4137322923
Short name T243
Test name
Test status
Simulation time 1094613113 ps
CPU time 1.42 seconds
Started Jun 10 05:41:45 PM PDT 24
Finished Jun 10 05:41:47 PM PDT 24
Peak memory 205088 kb
Host smart-a7f1192c-6cca-48d9-9a61-73ce4e236cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137322923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.4137322923
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1662002280
Short name T165
Test name
Test status
Simulation time 163450282 ps
CPU time 0.82 seconds
Started Jun 10 05:41:17 PM PDT 24
Finished Jun 10 05:41:18 PM PDT 24
Peak memory 204808 kb
Host smart-24af5272-1fd9-4c12-9828-66e2a0da5129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662002280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1662002280
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.1907118320
Short name T67
Test name
Test status
Simulation time 4007687195 ps
CPU time 3.1 seconds
Started Jun 10 05:41:32 PM PDT 24
Finished Jun 10 05:41:35 PM PDT 24
Peak memory 213380 kb
Host smart-7c1cc127-4edb-4793-a134-1aa066b7c87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907118320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1907118320
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.815269005
Short name T265
Test name
Test status
Simulation time 3541752917 ps
CPU time 3.82 seconds
Started Jun 10 05:41:33 PM PDT 24
Finished Jun 10 05:41:37 PM PDT 24
Peak memory 213308 kb
Host smart-cc232a2c-7744-4c27-9a4b-d159306287ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815269005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.815269005
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.4122771189
Short name T209
Test name
Test status
Simulation time 5577924290 ps
CPU time 5.46 seconds
Started Jun 10 05:41:30 PM PDT 24
Finished Jun 10 05:41:36 PM PDT 24
Peak memory 205208 kb
Host smart-1539da41-1ecd-4006-aa06-f65c1001d000
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122771189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.4122771189
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.488795224
Short name T179
Test name
Test status
Simulation time 7104496081 ps
CPU time 6.17 seconds
Started Jun 10 05:41:38 PM PDT 24
Finished Jun 10 05:41:45 PM PDT 24
Peak memory 205160 kb
Host smart-30f142d5-e234-492b-ac2b-132843f406f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488795224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.488795224
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.4073195157
Short name T156
Test name
Test status
Simulation time 95578299 ps
CPU time 0.77 seconds
Started Jun 10 05:41:19 PM PDT 24
Finished Jun 10 05:41:20 PM PDT 24
Peak memory 204816 kb
Host smart-913777b3-e1d7-40a2-a312-c746868cdf84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073195157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4073195157
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2228350935
Short name T237
Test name
Test status
Simulation time 3727402737 ps
CPU time 4.24 seconds
Started Jun 10 05:41:26 PM PDT 24
Finished Jun 10 05:41:31 PM PDT 24
Peak memory 205052 kb
Host smart-a1d3e828-6731-4b7d-9375-f09f457620ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228350935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2228350935
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3267120273
Short name T213
Test name
Test status
Simulation time 5389018644 ps
CPU time 11.07 seconds
Started Jun 10 05:41:26 PM PDT 24
Finished Jun 10 05:41:38 PM PDT 24
Peak memory 205200 kb
Host smart-ebc1ae7d-8683-411a-9255-a6772792502a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267120273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3267120273
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1446943111
Short name T199
Test name
Test status
Simulation time 2796297602 ps
CPU time 8.17 seconds
Started Jun 10 05:41:22 PM PDT 24
Finished Jun 10 05:41:31 PM PDT 24
Peak memory 205300 kb
Host smart-80b5003d-3792-4a32-9803-d9767d26a04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446943111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1446943111
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.2889207949
Short name T154
Test name
Test status
Simulation time 6364537117 ps
CPU time 11.41 seconds
Started Jun 10 05:41:25 PM PDT 24
Finished Jun 10 05:41:37 PM PDT 24
Peak memory 205056 kb
Host smart-ffe986d5-854e-4744-abc2-b755d1babc84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889207949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2889207949
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.408076306
Short name T167
Test name
Test status
Simulation time 98245211 ps
CPU time 0.85 seconds
Started Jun 10 05:41:37 PM PDT 24
Finished Jun 10 05:41:38 PM PDT 24
Peak memory 204796 kb
Host smart-35dc8734-bc56-4c4e-80c9-841859a993a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408076306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.408076306
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4155133675
Short name T221
Test name
Test status
Simulation time 5313910244 ps
CPU time 14.46 seconds
Started Jun 10 05:41:20 PM PDT 24
Finished Jun 10 05:41:35 PM PDT 24
Peak memory 205224 kb
Host smart-1c157528-949c-4e8c-abc9-3f5eaf5bb2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155133675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4155133675
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3731371272
Short name T259
Test name
Test status
Simulation time 9742700822 ps
CPU time 7.95 seconds
Started Jun 10 05:41:44 PM PDT 24
Finished Jun 10 05:41:53 PM PDT 24
Peak memory 205216 kb
Host smart-6804035d-5ee5-4322-99b0-45684916e2b9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731371272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3731371272
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.4036936944
Short name T73
Test name
Test status
Simulation time 2544505100 ps
CPU time 2.91 seconds
Started Jun 10 05:41:23 PM PDT 24
Finished Jun 10 05:41:27 PM PDT 24
Peak memory 205328 kb
Host smart-26aae34c-868d-4714-97a4-d66397a0e24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036936944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.4036936944
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.314633718
Short name T146
Test name
Test status
Simulation time 5573870663 ps
CPU time 7.46 seconds
Started Jun 10 05:41:24 PM PDT 24
Finished Jun 10 05:41:32 PM PDT 24
Peak memory 205108 kb
Host smart-7eab41c0-387b-4f9e-b8ae-302483605a60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314633718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.314633718
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2235547422
Short name T247
Test name
Test status
Simulation time 156576220 ps
CPU time 0.77 seconds
Started Jun 10 05:41:23 PM PDT 24
Finished Jun 10 05:41:24 PM PDT 24
Peak memory 204816 kb
Host smart-9abb8702-24ea-472d-8521-0e809bc8970b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235547422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2235547422
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3090989785
Short name T240
Test name
Test status
Simulation time 17402964997 ps
CPU time 28.65 seconds
Started Jun 10 05:41:32 PM PDT 24
Finished Jun 10 05:42:01 PM PDT 24
Peak memory 213412 kb
Host smart-081cc40d-e978-4fbc-bee7-f2c01d8b2fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090989785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3090989785
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1378453145
Short name T266
Test name
Test status
Simulation time 8313795440 ps
CPU time 11.53 seconds
Started Jun 10 05:41:22 PM PDT 24
Finished Jun 10 05:41:34 PM PDT 24
Peak memory 213392 kb
Host smart-b18e9464-efb1-4658-b3b1-ebe772760c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378453145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1378453145
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.136921577
Short name T186
Test name
Test status
Simulation time 1640119046 ps
CPU time 2.26 seconds
Started Jun 10 05:41:48 PM PDT 24
Finished Jun 10 05:41:51 PM PDT 24
Peak memory 205120 kb
Host smart-1a6c5f3f-d6db-49dc-873a-dc9148fdfd5a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=136921577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.136921577
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.484263141
Short name T47
Test name
Test status
Simulation time 4324962813 ps
CPU time 6.96 seconds
Started Jun 10 05:41:46 PM PDT 24
Finished Jun 10 05:41:53 PM PDT 24
Peak memory 205176 kb
Host smart-80a999c7-c7b2-4a7c-93cf-325bff49b413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484263141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.484263141
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.384365345
Short name T241
Test name
Test status
Simulation time 25567592192 ps
CPU time 9.71 seconds
Started Jun 10 05:41:20 PM PDT 24
Finished Jun 10 05:41:30 PM PDT 24
Peak memory 205112 kb
Host smart-cb7efd2c-eaa4-4ff7-b771-35b2c02640bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384365345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.384365345
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.921231830
Short name T155
Test name
Test status
Simulation time 70348183 ps
CPU time 0.72 seconds
Started Jun 10 05:41:26 PM PDT 24
Finished Jun 10 05:41:27 PM PDT 24
Peak memory 204764 kb
Host smart-29a35ae1-1a77-4ef1-8ad7-1f5e86b314a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921231830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.921231830
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.589314028
Short name T60
Test name
Test status
Simulation time 7548836944 ps
CPU time 7.68 seconds
Started Jun 10 05:41:29 PM PDT 24
Finished Jun 10 05:41:37 PM PDT 24
Peak memory 215452 kb
Host smart-663e2c9a-66bc-4819-bd21-4ccc2771fc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589314028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.589314028
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1882578801
Short name T193
Test name
Test status
Simulation time 3814669285 ps
CPU time 9.74 seconds
Started Jun 10 05:41:43 PM PDT 24
Finished Jun 10 05:41:53 PM PDT 24
Peak memory 205212 kb
Host smart-5ae4b24e-5d5b-4ee1-bf4e-860fd2ec0546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882578801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1882578801
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1684836334
Short name T230
Test name
Test status
Simulation time 4579458783 ps
CPU time 4.13 seconds
Started Jun 10 05:41:27 PM PDT 24
Finished Jun 10 05:41:31 PM PDT 24
Peak memory 205080 kb
Host smart-d9f22fd1-b051-42f6-b8ee-5353b61dd5e7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1684836334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1684836334
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2088137924
Short name T238
Test name
Test status
Simulation time 5259155632 ps
CPU time 14.27 seconds
Started Jun 10 05:41:24 PM PDT 24
Finished Jun 10 05:41:38 PM PDT 24
Peak memory 205236 kb
Host smart-2dee292f-b3c4-4b7a-97e0-b890b8838c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088137924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2088137924
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3342937777
Short name T50
Test name
Test status
Simulation time 14087907119 ps
CPU time 41.56 seconds
Started Jun 10 05:41:24 PM PDT 24
Finished Jun 10 05:42:06 PM PDT 24
Peak memory 213472 kb
Host smart-6f734165-1a5e-49aa-b3dc-054740241c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342937777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3342937777
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3234645348
Short name T36
Test name
Test status
Simulation time 6634136347 ps
CPU time 5.57 seconds
Started Jun 10 05:41:22 PM PDT 24
Finished Jun 10 05:41:28 PM PDT 24
Peak memory 205176 kb
Host smart-2e623b63-d7c4-4014-8919-3a8826b7a59f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3234645348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3234645348
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.2695615782
Short name T233
Test name
Test status
Simulation time 8662723595 ps
CPU time 14.01 seconds
Started Jun 10 05:41:26 PM PDT 24
Finished Jun 10 05:41:41 PM PDT 24
Peak memory 205232 kb
Host smart-792dda68-bafb-4750-b10b-d225b16498b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695615782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2695615782
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3590250619
Short name T219
Test name
Test status
Simulation time 98283411 ps
CPU time 0.92 seconds
Started Jun 10 05:41:23 PM PDT 24
Finished Jun 10 05:41:25 PM PDT 24
Peak memory 204840 kb
Host smart-be4b9f5b-2d9d-40ef-a217-10d1fafc7978
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590250619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3590250619
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3188610754
Short name T17
Test name
Test status
Simulation time 6328921893 ps
CPU time 7.84 seconds
Started Jun 10 05:41:27 PM PDT 24
Finished Jun 10 05:41:35 PM PDT 24
Peak memory 205172 kb
Host smart-6e32465d-0f3c-4ba4-a77b-bb4f81700c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188610754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3188610754
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.29211518
Short name T66
Test name
Test status
Simulation time 4266646949 ps
CPU time 3.1 seconds
Started Jun 10 05:41:34 PM PDT 24
Finished Jun 10 05:41:38 PM PDT 24
Peak memory 205256 kb
Host smart-ac1d5fcf-0116-459d-9c34-1a4bb41bd9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29211518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.29211518
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.4215737049
Short name T216
Test name
Test status
Simulation time 2477915957 ps
CPU time 7.5 seconds
Started Jun 10 05:41:25 PM PDT 24
Finished Jun 10 05:41:33 PM PDT 24
Peak memory 205224 kb
Host smart-18a85406-183b-4853-b3e7-a32095fdca5b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4215737049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.4215737049
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1445338665
Short name T95
Test name
Test status
Simulation time 5924967326 ps
CPU time 4.36 seconds
Started Jun 10 05:41:25 PM PDT 24
Finished Jun 10 05:41:30 PM PDT 24
Peak memory 205244 kb
Host smart-991219c7-8670-4532-a845-f6242a1e9ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445338665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1445338665
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.4027031229
Short name T153
Test name
Test status
Simulation time 6090706408 ps
CPU time 6.01 seconds
Started Jun 10 05:41:36 PM PDT 24
Finished Jun 10 05:41:42 PM PDT 24
Peak memory 205104 kb
Host smart-d2eec450-5489-4fc2-a3c8-451c3bccc549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027031229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.4027031229
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.105984248
Short name T196
Test name
Test status
Simulation time 68802424 ps
CPU time 0.83 seconds
Started Jun 10 05:41:40 PM PDT 24
Finished Jun 10 05:41:41 PM PDT 24
Peak memory 204776 kb
Host smart-7dd35aca-41b6-4d30-9f48-712d0a8e68c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105984248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.105984248
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.851776239
Short name T248
Test name
Test status
Simulation time 15581802158 ps
CPU time 45.84 seconds
Started Jun 10 05:41:24 PM PDT 24
Finished Jun 10 05:42:10 PM PDT 24
Peak memory 213416 kb
Host smart-2b3a6174-fd3b-4bf7-8c66-960965b8e2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851776239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.851776239
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3095055860
Short name T260
Test name
Test status
Simulation time 2107918596 ps
CPU time 2.53 seconds
Started Jun 10 05:41:34 PM PDT 24
Finished Jun 10 05:41:37 PM PDT 24
Peak memory 205064 kb
Host smart-8e759430-1d6b-4e62-8a19-0a9dde383b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095055860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3095055860
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2396713301
Short name T264
Test name
Test status
Simulation time 4438847591 ps
CPU time 13.44 seconds
Started Jun 10 05:41:36 PM PDT 24
Finished Jun 10 05:41:50 PM PDT 24
Peak memory 205264 kb
Host smart-089b1545-fc25-4527-ad4b-b6916c4a307d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2396713301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.2396713301
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.639258662
Short name T178
Test name
Test status
Simulation time 4705597595 ps
CPU time 7.65 seconds
Started Jun 10 05:41:39 PM PDT 24
Finished Jun 10 05:41:47 PM PDT 24
Peak memory 205196 kb
Host smart-721e8537-9665-473f-9a9b-e5244efd7f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639258662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.639258662
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.4012858222
Short name T145
Test name
Test status
Simulation time 5882808530 ps
CPU time 19.42 seconds
Started Jun 10 05:41:22 PM PDT 24
Finished Jun 10 05:41:42 PM PDT 24
Peak memory 205056 kb
Host smart-d0de4048-c48e-4288-bda5-37d16df578f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012858222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.4012858222
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2320738077
Short name T190
Test name
Test status
Simulation time 74636424 ps
CPU time 0.74 seconds
Started Jun 10 05:41:06 PM PDT 24
Finished Jun 10 05:41:07 PM PDT 24
Peak memory 204804 kb
Host smart-f21f54dd-955c-484f-8fc6-237d99da16aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320738077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2320738077
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.750153783
Short name T184
Test name
Test status
Simulation time 58053176784 ps
CPU time 86.75 seconds
Started Jun 10 05:41:01 PM PDT 24
Finished Jun 10 05:42:28 PM PDT 24
Peak memory 213452 kb
Host smart-cdbae9f1-a41f-418c-886a-e05ece1e1ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750153783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.750153783
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3950072152
Short name T234
Test name
Test status
Simulation time 7257152610 ps
CPU time 13.06 seconds
Started Jun 10 05:41:03 PM PDT 24
Finished Jun 10 05:41:16 PM PDT 24
Peak memory 205224 kb
Host smart-019184fa-3c07-43a6-83ea-c98004dd20f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950072152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3950072152
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3129395048
Short name T210
Test name
Test status
Simulation time 1875896334 ps
CPU time 2.5 seconds
Started Jun 10 05:41:01 PM PDT 24
Finished Jun 10 05:41:04 PM PDT 24
Peak memory 205136 kb
Host smart-fb0aaa92-ea7f-4d14-aa16-903bec0a2648
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3129395048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3129395048
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2317209904
Short name T215
Test name
Test status
Simulation time 229306520 ps
CPU time 1.34 seconds
Started Jun 10 05:41:05 PM PDT 24
Finished Jun 10 05:41:07 PM PDT 24
Peak memory 204528 kb
Host smart-7b3f2a3f-7a8f-4203-9bae-18d16850d7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317209904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2317209904
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3799947375
Short name T214
Test name
Test status
Simulation time 12438060246 ps
CPU time 8.82 seconds
Started Jun 10 05:41:09 PM PDT 24
Finished Jun 10 05:41:18 PM PDT 24
Peak memory 205252 kb
Host smart-b5448e44-bdb0-4515-b5e7-251e417b3d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799947375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3799947375
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1984440421
Short name T61
Test name
Test status
Simulation time 393349759 ps
CPU time 1.14 seconds
Started Jun 10 05:41:05 PM PDT 24
Finished Jun 10 05:41:07 PM PDT 24
Peak memory 229304 kb
Host smart-44003ffc-f997-4a5c-a18e-ef3d52c8039e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984440421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1984440421
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.509309891
Short name T168
Test name
Test status
Simulation time 47345176 ps
CPU time 0.8 seconds
Started Jun 10 05:41:25 PM PDT 24
Finished Jun 10 05:41:27 PM PDT 24
Peak memory 204824 kb
Host smart-7ec6d04b-3f27-4be4-b18d-b0feda1f6538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509309891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.509309891
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.3345372954
Short name T23
Test name
Test status
Simulation time 26557947161 ps
CPU time 74.16 seconds
Started Jun 10 05:41:26 PM PDT 24
Finished Jun 10 05:42:40 PM PDT 24
Peak memory 205040 kb
Host smart-891e6cac-c68f-4866-ae6d-35ac0ea6228c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345372954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3345372954
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1557907774
Short name T171
Test name
Test status
Simulation time 117016678 ps
CPU time 0.69 seconds
Started Jun 10 05:41:33 PM PDT 24
Finished Jun 10 05:41:34 PM PDT 24
Peak memory 204644 kb
Host smart-571242a9-af26-4fa7-bca4-259e9a05f86f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557907774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1557907774
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2756131429
Short name T157
Test name
Test status
Simulation time 115686509 ps
CPU time 0.83 seconds
Started Jun 10 05:41:26 PM PDT 24
Finished Jun 10 05:41:27 PM PDT 24
Peak memory 204768 kb
Host smart-72214c3b-c623-44b3-868b-ddcd0f2548e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756131429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2756131429
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3832565070
Short name T129
Test name
Test status
Simulation time 94268507 ps
CPU time 0.79 seconds
Started Jun 10 05:41:23 PM PDT 24
Finished Jun 10 05:41:24 PM PDT 24
Peak memory 204836 kb
Host smart-91ca7d5a-9a2e-496b-8921-76b826c29254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832565070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3832565070
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1857192944
Short name T201
Test name
Test status
Simulation time 245798215 ps
CPU time 0.74 seconds
Started Jun 10 05:41:43 PM PDT 24
Finished Jun 10 05:41:44 PM PDT 24
Peak memory 204756 kb
Host smart-c65ffe53-bec5-4fee-b358-d6710ae94a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857192944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1857192944
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1223817267
Short name T189
Test name
Test status
Simulation time 68880464 ps
CPU time 0.75 seconds
Started Jun 10 05:41:25 PM PDT 24
Finished Jun 10 05:41:27 PM PDT 24
Peak memory 204804 kb
Host smart-0ace5158-1570-4844-b1ef-be3ba87e470b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223817267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1223817267
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.377848446
Short name T172
Test name
Test status
Simulation time 43394172 ps
CPU time 0.79 seconds
Started Jun 10 05:41:25 PM PDT 24
Finished Jun 10 05:41:27 PM PDT 24
Peak memory 204780 kb
Host smart-058b0246-158b-431f-bd50-53f27d115cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377848446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.377848446
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.4012483065
Short name T169
Test name
Test status
Simulation time 141199813 ps
CPU time 0.77 seconds
Started Jun 10 05:41:29 PM PDT 24
Finished Jun 10 05:41:30 PM PDT 24
Peak memory 204804 kb
Host smart-d38bc385-0d57-4fc6-99a1-033aab438390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012483065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4012483065
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3863390889
Short name T185
Test name
Test status
Simulation time 115409482 ps
CPU time 0.77 seconds
Started Jun 10 05:41:24 PM PDT 24
Finished Jun 10 05:41:26 PM PDT 24
Peak memory 204824 kb
Host smart-c533eeba-7d55-4066-a21d-956810ee59dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863390889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3863390889
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1879641140
Short name T126
Test name
Test status
Simulation time 76416368 ps
CPU time 0.7 seconds
Started Jun 10 05:41:02 PM PDT 24
Finished Jun 10 05:41:03 PM PDT 24
Peak memory 204824 kb
Host smart-fd73c058-44d8-468a-95ed-f9594ac124be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879641140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1879641140
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3865528095
Short name T239
Test name
Test status
Simulation time 72376847038 ps
CPU time 51.2 seconds
Started Jun 10 05:41:05 PM PDT 24
Finished Jun 10 05:41:56 PM PDT 24
Peak memory 215580 kb
Host smart-38cb2552-d21a-4762-a7bd-772b5084155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865528095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3865528095
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1384299671
Short name T183
Test name
Test status
Simulation time 13125128721 ps
CPU time 4.98 seconds
Started Jun 10 05:41:05 PM PDT 24
Finished Jun 10 05:41:10 PM PDT 24
Peak memory 205400 kb
Host smart-c938a748-0060-4a67-bfd7-360c3cf02999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384299671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1384299671
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3629109794
Short name T181
Test name
Test status
Simulation time 9244779383 ps
CPU time 14.7 seconds
Started Jun 10 05:41:10 PM PDT 24
Finished Jun 10 05:41:25 PM PDT 24
Peak memory 205264 kb
Host smart-f33b6fdb-87ec-41ae-b631-5bcc4e38dd83
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629109794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3629109794
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.833483307
Short name T212
Test name
Test status
Simulation time 363156199 ps
CPU time 0.9 seconds
Started Jun 10 05:41:05 PM PDT 24
Finished Jun 10 05:41:06 PM PDT 24
Peak memory 204608 kb
Host smart-a8adcdd9-5b03-4061-a1bf-de4ce7ad5598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833483307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.833483307
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1424568055
Short name T255
Test name
Test status
Simulation time 4242351016 ps
CPU time 8.21 seconds
Started Jun 10 05:41:06 PM PDT 24
Finished Jun 10 05:41:15 PM PDT 24
Peak memory 205112 kb
Host smart-19e5617f-e6fe-4946-87ac-f3d8ec126149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424568055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1424568055
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2522071241
Short name T41
Test name
Test status
Simulation time 1397602990 ps
CPU time 4.63 seconds
Started Jun 10 05:41:05 PM PDT 24
Finished Jun 10 05:41:10 PM PDT 24
Peak memory 229616 kb
Host smart-912770a8-a07b-418e-a579-8aa8a5972feb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522071241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2522071241
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.1720439573
Short name T143
Test name
Test status
Simulation time 23492505027 ps
CPU time 71.9 seconds
Started Jun 10 05:41:05 PM PDT 24
Finished Jun 10 05:42:17 PM PDT 24
Peak memory 213172 kb
Host smart-ee14f7e7-fee7-4c88-b14e-cafbf1dd4f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720439573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1720439573
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.4150629843
Short name T35
Test name
Test status
Simulation time 63423192 ps
CPU time 0.86 seconds
Started Jun 10 05:41:41 PM PDT 24
Finished Jun 10 05:41:42 PM PDT 24
Peak memory 204808 kb
Host smart-6fba29b2-ae60-4593-8a3d-f88d6324e199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150629843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.4150629843
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.921957377
Short name T152
Test name
Test status
Simulation time 14816718169 ps
CPU time 45.74 seconds
Started Jun 10 05:41:26 PM PDT 24
Finished Jun 10 05:42:13 PM PDT 24
Peak memory 205044 kb
Host smart-40ae2009-3ca2-40a6-8c9b-4294e660b84b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921957377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.921957377
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1721967043
Short name T161
Test name
Test status
Simulation time 55913412 ps
CPU time 0.75 seconds
Started Jun 10 05:41:33 PM PDT 24
Finished Jun 10 05:41:34 PM PDT 24
Peak memory 204832 kb
Host smart-8626b8d1-410a-4f40-836e-161adf4270f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721967043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1721967043
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.34917342
Short name T177
Test name
Test status
Simulation time 90820431 ps
CPU time 0.81 seconds
Started Jun 10 05:41:45 PM PDT 24
Finished Jun 10 05:41:46 PM PDT 24
Peak memory 204780 kb
Host smart-19a1ad83-2648-45ff-b45d-ac12b968ae49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34917342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.34917342
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.3835896588
Short name T148
Test name
Test status
Simulation time 13276162596 ps
CPU time 9.46 seconds
Started Jun 10 05:41:46 PM PDT 24
Finished Jun 10 05:41:55 PM PDT 24
Peak memory 205032 kb
Host smart-b5a813a7-0694-4832-8a4a-d7c2de13195d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835896588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3835896588
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.131800128
Short name T176
Test name
Test status
Simulation time 82104196 ps
CPU time 0.72 seconds
Started Jun 10 05:41:41 PM PDT 24
Finished Jun 10 05:41:42 PM PDT 24
Peak memory 204800 kb
Host smart-b53f9ed9-8219-4003-ab93-4d3ef0963256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131800128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.131800128
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.4277332220
Short name T204
Test name
Test status
Simulation time 163061342 ps
CPU time 0.73 seconds
Started Jun 10 05:41:41 PM PDT 24
Finished Jun 10 05:41:42 PM PDT 24
Peak memory 204804 kb
Host smart-9c874871-9a2b-4950-b283-a4abacce5259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277332220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.4277332220
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.367855759
Short name T144
Test name
Test status
Simulation time 6675426640 ps
CPU time 10.03 seconds
Started Jun 10 05:41:32 PM PDT 24
Finished Jun 10 05:41:42 PM PDT 24
Peak memory 205096 kb
Host smart-d330af0f-e31e-4b09-ab8e-0fd7e8db2484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367855759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.367855759
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3743530725
Short name T173
Test name
Test status
Simulation time 44541559 ps
CPU time 0.74 seconds
Started Jun 10 05:41:54 PM PDT 24
Finished Jun 10 05:41:55 PM PDT 24
Peak memory 204820 kb
Host smart-312dac7d-e599-4cde-977e-641eccc44b47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743530725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3743530725
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2515508250
Short name T252
Test name
Test status
Simulation time 7146552761 ps
CPU time 12.94 seconds
Started Jun 10 05:41:34 PM PDT 24
Finished Jun 10 05:41:47 PM PDT 24
Peak memory 205104 kb
Host smart-3fd6b69a-9df3-4b2c-a297-b0380880e23b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515508250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2515508250
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.499016055
Short name T162
Test name
Test status
Simulation time 44265059 ps
CPU time 0.74 seconds
Started Jun 10 05:41:50 PM PDT 24
Finished Jun 10 05:41:51 PM PDT 24
Peak memory 204784 kb
Host smart-560c100c-34c3-427d-a1be-7f146f3303c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499016055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.499016055
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.1821782968
Short name T150
Test name
Test status
Simulation time 6289177721 ps
CPU time 7.17 seconds
Started Jun 10 05:41:49 PM PDT 24
Finished Jun 10 05:41:56 PM PDT 24
Peak memory 213080 kb
Host smart-039b4843-6c2d-4bde-8f5e-bc13635165ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821782968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1821782968
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2013610869
Short name T158
Test name
Test status
Simulation time 123534476 ps
CPU time 0.83 seconds
Started Jun 10 05:41:31 PM PDT 24
Finished Jun 10 05:41:32 PM PDT 24
Peak memory 204808 kb
Host smart-348677b4-0376-4040-945f-9bd2bcb98da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013610869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2013610869
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3618481811
Short name T59
Test name
Test status
Simulation time 47352403 ps
CPU time 0.89 seconds
Started Jun 10 05:41:35 PM PDT 24
Finished Jun 10 05:41:36 PM PDT 24
Peak memory 204932 kb
Host smart-dfd38ea8-392a-4ef7-95fb-c16e53705cab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618481811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3618481811
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1087114210
Short name T77
Test name
Test status
Simulation time 108727691 ps
CPU time 0.72 seconds
Started Jun 10 05:41:39 PM PDT 24
Finished Jun 10 05:41:40 PM PDT 24
Peak memory 204752 kb
Host smart-4995e911-461c-48e2-b3a7-ad5f2f928226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087114210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1087114210
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2197770181
Short name T164
Test name
Test status
Simulation time 131857395 ps
CPU time 0.78 seconds
Started Jun 10 05:41:04 PM PDT 24
Finished Jun 10 05:41:05 PM PDT 24
Peak memory 204804 kb
Host smart-639c36ab-6a72-4e6a-b098-6d7e959a3c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197770181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2197770181
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1682236540
Short name T207
Test name
Test status
Simulation time 25576937231 ps
CPU time 42.91 seconds
Started Jun 10 05:41:07 PM PDT 24
Finished Jun 10 05:41:50 PM PDT 24
Peak memory 213268 kb
Host smart-4eb4a713-4889-4cff-bff7-9228508cf9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682236540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1682236540
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.682796028
Short name T63
Test name
Test status
Simulation time 7183150943 ps
CPU time 6.18 seconds
Started Jun 10 05:41:05 PM PDT 24
Finished Jun 10 05:41:12 PM PDT 24
Peak memory 213372 kb
Host smart-c2fbf364-e061-41f5-8300-00a63947b541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682796028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.682796028
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1109913204
Short name T64
Test name
Test status
Simulation time 3182884106 ps
CPU time 5.65 seconds
Started Jun 10 05:41:05 PM PDT 24
Finished Jun 10 05:41:11 PM PDT 24
Peak memory 205228 kb
Host smart-efe62413-15b7-47d6-88de-29c80f7f353a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1109913204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1109913204
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1581116353
Short name T206
Test name
Test status
Simulation time 101958057 ps
CPU time 0.85 seconds
Started Jun 10 05:41:06 PM PDT 24
Finished Jun 10 05:41:08 PM PDT 24
Peak memory 204616 kb
Host smart-a6f2efc0-e054-4fb0-9ed6-6c26787869cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581116353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1581116353
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.4204227355
Short name T220
Test name
Test status
Simulation time 2263409047 ps
CPU time 6.38 seconds
Started Jun 10 05:41:07 PM PDT 24
Finished Jun 10 05:41:14 PM PDT 24
Peak memory 205128 kb
Host smart-5835d5d1-76f8-4422-adb2-a64dbfdbf47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204227355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.4204227355
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1225138533
Short name T166
Test name
Test status
Simulation time 75016453 ps
CPU time 0.72 seconds
Started Jun 10 05:41:32 PM PDT 24
Finished Jun 10 05:41:33 PM PDT 24
Peak memory 204816 kb
Host smart-cbf18d1e-f4ad-4d0c-abe1-1fb456517320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225138533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1225138533
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2057176533
Short name T75
Test name
Test status
Simulation time 93180704 ps
CPU time 0.7 seconds
Started Jun 10 05:41:34 PM PDT 24
Finished Jun 10 05:41:36 PM PDT 24
Peak memory 204824 kb
Host smart-35efc80e-8f6a-4596-9449-e2d8f75799fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057176533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2057176533
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3686238186
Short name T37
Test name
Test status
Simulation time 58226403 ps
CPU time 0.76 seconds
Started Jun 10 05:41:36 PM PDT 24
Finished Jun 10 05:41:37 PM PDT 24
Peak memory 204936 kb
Host smart-832f2aab-4915-46a5-b28c-d60fd4275f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686238186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3686238186
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.3115398287
Short name T18
Test name
Test status
Simulation time 6194589339 ps
CPU time 11.52 seconds
Started Jun 10 05:41:32 PM PDT 24
Finished Jun 10 05:41:44 PM PDT 24
Peak memory 205020 kb
Host smart-995a8c20-2e97-4f4f-ad47-74fc1c3fb983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115398287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3115398287
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1285585649
Short name T163
Test name
Test status
Simulation time 241419090 ps
CPU time 0.71 seconds
Started Jun 10 05:41:38 PM PDT 24
Finished Jun 10 05:41:39 PM PDT 24
Peak memory 204812 kb
Host smart-64020814-ecb9-422c-931f-999727299a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285585649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1285585649
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.4239097633
Short name T160
Test name
Test status
Simulation time 66259592 ps
CPU time 0.79 seconds
Started Jun 10 05:41:52 PM PDT 24
Finished Jun 10 05:41:53 PM PDT 24
Peak memory 204796 kb
Host smart-ad3f6a9a-3bf0-4336-b53c-1f861f9da78f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239097633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.4239097633
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.3516027171
Short name T147
Test name
Test status
Simulation time 10359446676 ps
CPU time 15.59 seconds
Started Jun 10 05:41:48 PM PDT 24
Finished Jun 10 05:42:04 PM PDT 24
Peak memory 213264 kb
Host smart-81698443-7728-424f-a2e7-39bb74e14406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516027171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3516027171
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1637636111
Short name T128
Test name
Test status
Simulation time 93440320 ps
CPU time 0.75 seconds
Started Jun 10 05:41:38 PM PDT 24
Finished Jun 10 05:41:40 PM PDT 24
Peak memory 204832 kb
Host smart-ded23929-3def-4385-9fb2-017f8fc43d9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637636111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1637636111
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3232442680
Short name T72
Test name
Test status
Simulation time 130529532 ps
CPU time 1.04 seconds
Started Jun 10 05:41:37 PM PDT 24
Finished Jun 10 05:41:39 PM PDT 24
Peak memory 204772 kb
Host smart-01235d0a-1258-4870-b058-f632e16efc66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232442680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3232442680
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2311750206
Short name T79
Test name
Test status
Simulation time 54553047 ps
CPU time 0.78 seconds
Started Jun 10 05:41:49 PM PDT 24
Finished Jun 10 05:41:50 PM PDT 24
Peak memory 204824 kb
Host smart-9ae40338-c2d9-481d-8c0f-378c73265f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311750206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2311750206
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.1537755009
Short name T45
Test name
Test status
Simulation time 6637179297 ps
CPU time 19.04 seconds
Started Jun 10 05:41:37 PM PDT 24
Finished Jun 10 05:41:56 PM PDT 24
Peak memory 205104 kb
Host smart-b6935a29-5752-459c-9147-e32d9e743cf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537755009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1537755009
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.4232776465
Short name T245
Test name
Test status
Simulation time 119169719 ps
CPU time 1.06 seconds
Started Jun 10 05:41:40 PM PDT 24
Finished Jun 10 05:41:42 PM PDT 24
Peak memory 204808 kb
Host smart-19ae753a-5198-45f3-aa8a-5b1eb487bca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232776465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.4232776465
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3300516746
Short name T217
Test name
Test status
Simulation time 77694061 ps
CPU time 0.72 seconds
Started Jun 10 05:41:54 PM PDT 24
Finished Jun 10 05:41:56 PM PDT 24
Peak memory 204812 kb
Host smart-5a21a275-b110-45e9-bb0e-795d9042bd13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300516746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3300516746
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2072689509
Short name T170
Test name
Test status
Simulation time 80161578 ps
CPU time 0.75 seconds
Started Jun 10 05:41:09 PM PDT 24
Finished Jun 10 05:41:10 PM PDT 24
Peak memory 204804 kb
Host smart-58e0d528-e39c-45c8-9de7-3465e7b4f046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072689509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2072689509
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.4075016872
Short name T2
Test name
Test status
Simulation time 2559814722 ps
CPU time 3.36 seconds
Started Jun 10 05:41:07 PM PDT 24
Finished Jun 10 05:41:11 PM PDT 24
Peak memory 205200 kb
Host smart-36dec93b-27f7-4e68-a9c8-6f0109e2d9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075016872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.4075016872
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3359301256
Short name T246
Test name
Test status
Simulation time 6306938320 ps
CPU time 18.7 seconds
Started Jun 10 05:41:09 PM PDT 24
Finished Jun 10 05:41:28 PM PDT 24
Peak memory 213440 kb
Host smart-46223d3f-5064-439e-8e45-fb07e9f72071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359301256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3359301256
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.515125850
Short name T202
Test name
Test status
Simulation time 9374905857 ps
CPU time 26.73 seconds
Started Jun 10 05:41:04 PM PDT 24
Finished Jun 10 05:41:31 PM PDT 24
Peak memory 205248 kb
Host smart-74a5c022-92af-4b97-9de3-b0c398ae0414
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=515125850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.515125850
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.927206220
Short name T191
Test name
Test status
Simulation time 1994504785 ps
CPU time 6.52 seconds
Started Jun 10 05:41:07 PM PDT 24
Finished Jun 10 05:41:14 PM PDT 24
Peak memory 205124 kb
Host smart-486a47ee-c52b-4532-a966-f95e23f6aa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927206220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.927206220
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2775134760
Short name T174
Test name
Test status
Simulation time 58565568 ps
CPU time 0.74 seconds
Started Jun 10 05:41:14 PM PDT 24
Finished Jun 10 05:41:15 PM PDT 24
Peak memory 204784 kb
Host smart-eced2ef8-c7aa-484b-ae36-df52de0bab69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775134760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2775134760
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3731351641
Short name T225
Test name
Test status
Simulation time 131919069754 ps
CPU time 191.84 seconds
Started Jun 10 05:41:16 PM PDT 24
Finished Jun 10 05:44:28 PM PDT 24
Peak memory 218372 kb
Host smart-91a7232d-c3a3-45e1-9a91-1ccec4fdbea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731351641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3731351641
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1355339002
Short name T267
Test name
Test status
Simulation time 2256674515 ps
CPU time 4.41 seconds
Started Jun 10 05:41:12 PM PDT 24
Finished Jun 10 05:41:17 PM PDT 24
Peak memory 205304 kb
Host smart-040a51b7-a1d9-4d8c-8e04-7e82aad1b327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355339002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1355339002
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2699069361
Short name T195
Test name
Test status
Simulation time 1193713655 ps
CPU time 4.61 seconds
Started Jun 10 05:41:12 PM PDT 24
Finished Jun 10 05:41:17 PM PDT 24
Peak memory 205064 kb
Host smart-d4e8513a-e976-4d21-8b5c-730e214996b6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2699069361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2699069361
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2464377536
Short name T254
Test name
Test status
Simulation time 2211868255 ps
CPU time 7.29 seconds
Started Jun 10 05:41:12 PM PDT 24
Finished Jun 10 05:41:24 PM PDT 24
Peak memory 205236 kb
Host smart-89ab79ed-07f0-41bc-806d-7154dfee64a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464377536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2464377536
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.3324994148
Short name T28
Test name
Test status
Simulation time 6029661808 ps
CPU time 15.85 seconds
Started Jun 10 05:41:12 PM PDT 24
Finished Jun 10 05:41:29 PM PDT 24
Peak memory 205060 kb
Host smart-4fb8e8a1-63ed-47c9-a46d-8a6bff275ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324994148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3324994148
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3806296594
Short name T159
Test name
Test status
Simulation time 119110550 ps
CPU time 0.73 seconds
Started Jun 10 05:41:10 PM PDT 24
Finished Jun 10 05:41:11 PM PDT 24
Peak memory 204812 kb
Host smart-225b4e6d-b6ac-4111-90b0-351b14359ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806296594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3806296594
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1228675103
Short name T4
Test name
Test status
Simulation time 6075878004 ps
CPU time 17.7 seconds
Started Jun 10 05:41:08 PM PDT 24
Finished Jun 10 05:41:26 PM PDT 24
Peak memory 205184 kb
Host smart-b250ba1e-b891-462b-b9ed-eac97bd232e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228675103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1228675103
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1343520407
Short name T244
Test name
Test status
Simulation time 2543713672 ps
CPU time 2.65 seconds
Started Jun 10 05:41:15 PM PDT 24
Finished Jun 10 05:41:18 PM PDT 24
Peak memory 205272 kb
Host smart-e9af39e3-7db7-48a9-8dc6-5976e8eec7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343520407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1343520407
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2544319122
Short name T218
Test name
Test status
Simulation time 5813643440 ps
CPU time 17.3 seconds
Started Jun 10 05:41:11 PM PDT 24
Finished Jun 10 05:41:29 PM PDT 24
Peak memory 205232 kb
Host smart-6ce44206-b268-4f0f-9349-0c4f29f59663
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2544319122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2544319122
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3302366019
Short name T211
Test name
Test status
Simulation time 1709934946 ps
CPU time 3.35 seconds
Started Jun 10 05:41:08 PM PDT 24
Finished Jun 10 05:41:12 PM PDT 24
Peak memory 205120 kb
Host smart-23863c61-f6e9-4575-9683-0d60cf4959da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302366019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3302366019
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1835002584
Short name T48
Test name
Test status
Simulation time 39419397 ps
CPU time 0.8 seconds
Started Jun 10 05:41:24 PM PDT 24
Finished Jun 10 05:41:25 PM PDT 24
Peak memory 204804 kb
Host smart-20ffff97-a51f-4358-9537-021d95dcfc86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835002584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1835002584
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1537020498
Short name T258
Test name
Test status
Simulation time 7830092879 ps
CPU time 22.45 seconds
Started Jun 10 05:41:11 PM PDT 24
Finished Jun 10 05:41:33 PM PDT 24
Peak memory 205296 kb
Host smart-7140eac9-9f01-4fc7-a931-01b21aebf2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537020498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1537020498
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3191499899
Short name T229
Test name
Test status
Simulation time 2726556903 ps
CPU time 3.41 seconds
Started Jun 10 05:41:13 PM PDT 24
Finished Jun 10 05:41:17 PM PDT 24
Peak memory 205080 kb
Host smart-eb180fc6-9105-4ccc-8857-7ff5a859a3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191499899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3191499899
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.378245885
Short name T192
Test name
Test status
Simulation time 5307553674 ps
CPU time 8.56 seconds
Started Jun 10 05:41:14 PM PDT 24
Finished Jun 10 05:41:23 PM PDT 24
Peak memory 205160 kb
Host smart-4a8236bb-62d2-48f6-bb8e-8ddad2f7de62
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378245885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.378245885
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1361040308
Short name T208
Test name
Test status
Simulation time 6569309672 ps
CPU time 4.42 seconds
Started Jun 10 05:41:09 PM PDT 24
Finished Jun 10 05:41:14 PM PDT 24
Peak memory 205236 kb
Host smart-f3171f07-c901-4c03-a477-f56f00dc2aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361040308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1361040308
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2688475383
Short name T127
Test name
Test status
Simulation time 140597711 ps
CPU time 1.07 seconds
Started Jun 10 05:41:23 PM PDT 24
Finished Jun 10 05:41:24 PM PDT 24
Peak memory 204808 kb
Host smart-de9893c0-2406-41b4-bee9-88a1bcac4c1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688475383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2688475383
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.785434749
Short name T224
Test name
Test status
Simulation time 32557883478 ps
CPU time 42.53 seconds
Started Jun 10 05:41:14 PM PDT 24
Finished Jun 10 05:41:57 PM PDT 24
Peak memory 213476 kb
Host smart-a20dbbb2-62f7-4512-a446-76c6c80a0ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785434749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.785434749
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2268208273
Short name T262
Test name
Test status
Simulation time 888417421 ps
CPU time 1.75 seconds
Started Jun 10 05:41:21 PM PDT 24
Finished Jun 10 05:41:23 PM PDT 24
Peak memory 205116 kb
Host smart-34c802f8-eda9-4d30-a7d9-81a136a62206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268208273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2268208273
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3610258710
Short name T187
Test name
Test status
Simulation time 16196441671 ps
CPU time 24.51 seconds
Started Jun 10 05:41:15 PM PDT 24
Finished Jun 10 05:41:40 PM PDT 24
Peak memory 205388 kb
Host smart-400755a3-a4d4-4a17-9d27-26d1bcc63d82
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3610258710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3610258710
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3040282504
Short name T1
Test name
Test status
Simulation time 3267594748 ps
CPU time 6.91 seconds
Started Jun 10 05:41:15 PM PDT 24
Finished Jun 10 05:41:23 PM PDT 24
Peak memory 205196 kb
Host smart-547eaed8-15d4-4b63-b8fb-a37e141b51cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040282504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3040282504
Directory /workspace/9.rv_dm_sba_tl_access/latest
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