Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.04 94.56 78.90 86.17 71.79 84.50 98.52 38.82


Total test records in report: 411
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T285 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3497452715 Jun 11 03:43:39 PM PDT 24 Jun 11 03:43:41 PM PDT 24 50883337 ps
T157 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.104105840 Jun 11 03:43:23 PM PDT 24 Jun 11 03:43:30 PM PDT 24 291381806 ps
T286 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1567300240 Jun 11 03:43:56 PM PDT 24 Jun 11 03:43:59 PM PDT 24 144299122 ps
T136 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2130924586 Jun 11 03:44:02 PM PDT 24 Jun 11 03:44:23 PM PDT 24 1436216848 ps
T287 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3194590862 Jun 11 03:43:55 PM PDT 24 Jun 11 03:44:00 PM PDT 24 69595834 ps
T95 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1721985146 Jun 11 03:43:55 PM PDT 24 Jun 11 03:43:58 PM PDT 24 158274735 ps
T103 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2667700454 Jun 11 03:43:46 PM PDT 24 Jun 11 03:43:55 PM PDT 24 1795921271 ps
T288 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2852288930 Jun 11 03:43:56 PM PDT 24 Jun 11 03:44:01 PM PDT 24 927534614 ps
T289 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1894603511 Jun 11 03:44:05 PM PDT 24 Jun 11 03:44:08 PM PDT 24 256298144 ps
T104 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.113408429 Jun 11 03:44:05 PM PDT 24 Jun 11 03:44:15 PM PDT 24 719192566 ps
T290 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1206141546 Jun 11 03:43:38 PM PDT 24 Jun 11 03:43:40 PM PDT 24 472439947 ps
T291 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2331839050 Jun 11 03:43:57 PM PDT 24 Jun 11 03:44:06 PM PDT 24 2581148402 ps
T292 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.68333851 Jun 11 03:43:37 PM PDT 24 Jun 11 03:44:33 PM PDT 24 35295927267 ps
T293 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.260428596 Jun 11 03:43:56 PM PDT 24 Jun 11 03:44:02 PM PDT 24 289993900 ps
T294 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.537538158 Jun 11 03:43:59 PM PDT 24 Jun 11 03:44:02 PM PDT 24 423922522 ps
T105 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2209320537 Jun 11 03:43:55 PM PDT 24 Jun 11 03:44:00 PM PDT 24 549659233 ps
T295 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1418607317 Jun 11 03:43:47 PM PDT 24 Jun 11 03:44:05 PM PDT 24 17976104591 ps
T296 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1983925596 Jun 11 03:43:49 PM PDT 24 Jun 11 03:44:04 PM PDT 24 4628116742 ps
T297 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.576934157 Jun 11 03:44:05 PM PDT 24 Jun 11 03:44:16 PM PDT 24 3109894313 ps
T106 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.328718027 Jun 11 03:44:02 PM PDT 24 Jun 11 03:44:12 PM PDT 24 1185494464 ps
T298 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3094587763 Jun 11 03:43:56 PM PDT 24 Jun 11 03:44:01 PM PDT 24 180200297 ps
T122 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.996627883 Jun 11 03:44:11 PM PDT 24 Jun 11 03:44:16 PM PDT 24 485277212 ps
T99 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.340267591 Jun 11 03:43:48 PM PDT 24 Jun 11 03:43:57 PM PDT 24 8566844136 ps
T299 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2047664729 Jun 11 03:43:55 PM PDT 24 Jun 11 03:44:01 PM PDT 24 5880446043 ps
T107 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2087454132 Jun 11 03:43:38 PM PDT 24 Jun 11 03:43:41 PM PDT 24 214297782 ps
T300 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.125665978 Jun 11 03:43:50 PM PDT 24 Jun 11 03:43:59 PM PDT 24 2902620330 ps
T108 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.621132417 Jun 11 03:43:57 PM PDT 24 Jun 11 03:44:07 PM PDT 24 474673498 ps
T133 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3350295057 Jun 11 03:44:11 PM PDT 24 Jun 11 03:44:31 PM PDT 24 4447343546 ps
T301 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.734258675 Jun 11 03:43:59 PM PDT 24 Jun 11 03:44:05 PM PDT 24 582234164 ps
T302 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1606186886 Jun 11 03:44:04 PM PDT 24 Jun 11 03:44:07 PM PDT 24 458394983 ps
T303 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3664970458 Jun 11 03:43:59 PM PDT 24 Jun 11 03:44:02 PM PDT 24 516954732 ps
T304 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2222977456 Jun 11 03:43:58 PM PDT 24 Jun 11 03:44:03 PM PDT 24 583361620 ps
T305 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2319735216 Jun 11 03:43:22 PM PDT 24 Jun 11 03:43:35 PM PDT 24 3652478434 ps
T306 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.882459096 Jun 11 03:44:00 PM PDT 24 Jun 11 03:44:15 PM PDT 24 4094553756 ps
T123 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3332676801 Jun 11 03:43:56 PM PDT 24 Jun 11 03:44:05 PM PDT 24 255005533 ps
T307 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2838103364 Jun 11 03:44:06 PM PDT 24 Jun 11 03:44:12 PM PDT 24 510657047 ps
T308 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.511658942 Jun 11 03:44:08 PM PDT 24 Jun 11 03:44:37 PM PDT 24 9826375824 ps
T309 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1037068287 Jun 11 03:44:02 PM PDT 24 Jun 11 03:44:43 PM PDT 24 15286913954 ps
T310 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.785817338 Jun 11 03:43:19 PM PDT 24 Jun 11 03:43:35 PM PDT 24 1960142874 ps
T311 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1187147596 Jun 11 03:43:48 PM PDT 24 Jun 11 03:43:53 PM PDT 24 2944285799 ps
T135 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4092924553 Jun 11 03:44:01 PM PDT 24 Jun 11 03:44:15 PM PDT 24 2858228295 ps
T312 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2190027387 Jun 11 03:43:49 PM PDT 24 Jun 11 03:44:09 PM PDT 24 7043784170 ps
T313 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3329424324 Jun 11 03:43:29 PM PDT 24 Jun 11 03:43:32 PM PDT 24 223706228 ps
T314 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2704021289 Jun 11 03:43:48 PM PDT 24 Jun 11 03:44:11 PM PDT 24 23612270037 ps
T315 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.908567898 Jun 11 03:44:04 PM PDT 24 Jun 11 03:44:12 PM PDT 24 497043782 ps
T100 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2921537598 Jun 11 03:43:40 PM PDT 24 Jun 11 03:44:19 PM PDT 24 14535259002 ps
T113 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2207279731 Jun 11 03:43:30 PM PDT 24 Jun 11 03:43:34 PM PDT 24 286792972 ps
T316 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3428296917 Jun 11 03:43:58 PM PDT 24 Jun 11 03:44:07 PM PDT 24 2375739914 ps
T317 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2822258474 Jun 11 03:43:49 PM PDT 24 Jun 11 03:43:55 PM PDT 24 394041987 ps
T109 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3868508861 Jun 11 03:43:48 PM PDT 24 Jun 11 03:43:54 PM PDT 24 1516804247 ps
T134 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3825252577 Jun 11 03:44:03 PM PDT 24 Jun 11 03:44:14 PM PDT 24 2121597014 ps
T114 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3494920176 Jun 11 03:44:04 PM PDT 24 Jun 11 03:44:07 PM PDT 24 116814272 ps
T318 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3099959613 Jun 11 03:43:58 PM PDT 24 Jun 11 03:44:11 PM PDT 24 1015979392 ps
T319 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.795839994 Jun 11 03:43:48 PM PDT 24 Jun 11 03:45:53 PM PDT 24 70249131714 ps
T320 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2549102554 Jun 11 03:43:46 PM PDT 24 Jun 11 03:44:23 PM PDT 24 21161998764 ps
T321 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4052972686 Jun 11 03:43:55 PM PDT 24 Jun 11 03:43:59 PM PDT 24 780323995 ps
T322 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1246987065 Jun 11 03:44:07 PM PDT 24 Jun 11 03:44:13 PM PDT 24 317772712 ps
T323 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.376863879 Jun 11 03:43:37 PM PDT 24 Jun 11 03:43:41 PM PDT 24 205378827 ps
T324 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.458920481 Jun 11 03:43:23 PM PDT 24 Jun 11 03:43:53 PM PDT 24 9888591004 ps
T325 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3030485242 Jun 11 03:44:02 PM PDT 24 Jun 11 03:44:06 PM PDT 24 373311154 ps
T326 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1301974782 Jun 11 03:43:57 PM PDT 24 Jun 11 03:44:25 PM PDT 24 18105768299 ps
T327 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2976894306 Jun 11 03:43:31 PM PDT 24 Jun 11 03:44:50 PM PDT 24 61448129630 ps
T328 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3710199331 Jun 11 03:44:06 PM PDT 24 Jun 11 03:44:08 PM PDT 24 652947454 ps
T115 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1562592199 Jun 11 03:43:23 PM PDT 24 Jun 11 03:43:27 PM PDT 24 161595409 ps
T137 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1840784636 Jun 11 03:43:58 PM PDT 24 Jun 11 03:44:11 PM PDT 24 1816031094 ps
T329 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.817634885 Jun 11 03:43:39 PM PDT 24 Jun 11 03:47:43 PM PDT 24 81209260964 ps
T330 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.884762218 Jun 11 03:43:37 PM PDT 24 Jun 11 03:43:47 PM PDT 24 2919939952 ps
T331 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3344265955 Jun 11 03:44:08 PM PDT 24 Jun 11 03:44:24 PM PDT 24 4348523308 ps
T332 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.56909462 Jun 11 03:43:48 PM PDT 24 Jun 11 03:43:52 PM PDT 24 1601598042 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3468794160 Jun 11 03:43:30 PM PDT 24 Jun 11 03:43:32 PM PDT 24 44135498 ps
T334 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3853292865 Jun 11 03:43:23 PM PDT 24 Jun 11 03:43:52 PM PDT 24 24141010137 ps
T335 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3611893882 Jun 11 03:43:23 PM PDT 24 Jun 11 03:43:26 PM PDT 24 1007152691 ps
T116 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.268714198 Jun 11 03:44:10 PM PDT 24 Jun 11 03:44:13 PM PDT 24 122267097 ps
T336 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3864896661 Jun 11 03:44:03 PM PDT 24 Jun 11 03:44:08 PM PDT 24 354072474 ps
T337 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.768593249 Jun 11 03:44:08 PM PDT 24 Jun 11 03:44:11 PM PDT 24 290765437 ps
T338 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1108959602 Jun 11 03:43:46 PM PDT 24 Jun 11 03:44:08 PM PDT 24 3400751968 ps
T339 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3939908558 Jun 11 03:44:09 PM PDT 24 Jun 11 03:44:16 PM PDT 24 3358863921 ps
T340 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1090563658 Jun 11 03:43:50 PM PDT 24 Jun 11 03:43:53 PM PDT 24 227640127 ps
T341 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2318052566 Jun 11 03:43:58 PM PDT 24 Jun 11 03:44:03 PM PDT 24 2406765988 ps
T342 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2928083338 Jun 11 03:43:55 PM PDT 24 Jun 11 03:44:22 PM PDT 24 34147110836 ps
T343 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3783795319 Jun 11 03:43:56 PM PDT 24 Jun 11 03:44:19 PM PDT 24 7422332134 ps
T344 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.491271952 Jun 11 03:43:57 PM PDT 24 Jun 11 03:44:05 PM PDT 24 238278153 ps
T345 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2836082385 Jun 11 03:43:57 PM PDT 24 Jun 11 03:44:57 PM PDT 24 81083263878 ps
T346 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1180402586 Jun 11 03:43:51 PM PDT 24 Jun 11 03:43:54 PM PDT 24 280544947 ps
T347 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2392793223 Jun 11 03:43:46 PM PDT 24 Jun 11 03:43:50 PM PDT 24 119803748 ps
T348 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3122563805 Jun 11 03:43:49 PM PDT 24 Jun 11 03:43:51 PM PDT 24 201007469 ps
T349 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3481043568 Jun 11 03:44:02 PM PDT 24 Jun 11 03:44:05 PM PDT 24 265243480 ps
T117 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.633240 Jun 11 03:43:37 PM PDT 24 Jun 11 03:44:32 PM PDT 24 10883399787 ps
T350 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3696304563 Jun 11 03:43:38 PM PDT 24 Jun 11 03:43:41 PM PDT 24 871259037 ps
T351 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2249433768 Jun 11 03:43:23 PM PDT 24 Jun 11 03:43:57 PM PDT 24 6966713481 ps
T352 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.6333828 Jun 11 03:43:58 PM PDT 24 Jun 11 03:44:08 PM PDT 24 3765710224 ps
T132 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.427575569 Jun 11 03:43:30 PM PDT 24 Jun 11 03:43:51 PM PDT 24 5184698332 ps
T353 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3284992199 Jun 11 03:44:07 PM PDT 24 Jun 11 03:44:22 PM PDT 24 2116177841 ps
T354 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3685981075 Jun 11 03:43:46 PM PDT 24 Jun 11 03:43:49 PM PDT 24 234840574 ps
T355 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2396415874 Jun 11 03:43:47 PM PDT 24 Jun 11 03:43:51 PM PDT 24 778944637 ps
T356 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1305913323 Jun 11 03:44:03 PM PDT 24 Jun 11 03:44:10 PM PDT 24 6085317347 ps
T138 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.628295921 Jun 11 03:43:59 PM PDT 24 Jun 11 03:44:19 PM PDT 24 2840294544 ps
T357 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.107575704 Jun 11 03:43:29 PM PDT 24 Jun 11 03:43:32 PM PDT 24 197595951 ps
T358 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.240236912 Jun 11 03:43:57 PM PDT 24 Jun 11 03:44:11 PM PDT 24 18535880517 ps
T118 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2592007334 Jun 11 03:43:23 PM PDT 24 Jun 11 03:44:20 PM PDT 24 7388678495 ps
T359 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2177027553 Jun 11 03:43:49 PM PDT 24 Jun 11 03:43:52 PM PDT 24 358102008 ps
T360 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1757011020 Jun 11 03:43:39 PM PDT 24 Jun 11 03:44:41 PM PDT 24 21142024734 ps
T361 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2495827107 Jun 11 03:43:37 PM PDT 24 Jun 11 03:43:39 PM PDT 24 75139790 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4188554956 Jun 11 03:43:28 PM PDT 24 Jun 11 03:43:44 PM PDT 24 4595107249 ps
T363 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1596260383 Jun 11 03:43:30 PM PDT 24 Jun 11 03:43:32 PM PDT 24 112605411 ps
T119 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2443584337 Jun 11 03:43:57 PM PDT 24 Jun 11 03:44:00 PM PDT 24 164059176 ps
T364 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.437290430 Jun 11 03:44:04 PM PDT 24 Jun 11 03:44:24 PM PDT 24 23319666738 ps
T120 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1966460683 Jun 11 03:43:22 PM PDT 24 Jun 11 03:43:56 PM PDT 24 7957928346 ps
T365 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3676005264 Jun 11 03:43:56 PM PDT 24 Jun 11 03:44:01 PM PDT 24 98613141 ps
T110 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3351162743 Jun 11 03:43:48 PM PDT 24 Jun 11 03:45:04 PM PDT 24 3487144024 ps
T111 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3282687471 Jun 11 03:43:57 PM PDT 24 Jun 11 03:44:03 PM PDT 24 441271551 ps
T366 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1490341561 Jun 11 03:43:46 PM PDT 24 Jun 11 03:45:52 PM PDT 24 46615007694 ps
T367 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2568401412 Jun 11 03:43:29 PM PDT 24 Jun 11 03:43:36 PM PDT 24 2397556913 ps
T368 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.562069486 Jun 11 03:43:47 PM PDT 24 Jun 11 03:46:29 PM PDT 24 120724922567 ps
T369 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2648353423 Jun 11 03:43:29 PM PDT 24 Jun 11 03:43:57 PM PDT 24 6967543033 ps
T370 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1573375438 Jun 11 03:43:23 PM PDT 24 Jun 11 03:43:26 PM PDT 24 51656133 ps
T101 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1266817907 Jun 11 03:43:29 PM PDT 24 Jun 11 03:43:37 PM PDT 24 8422758674 ps
T371 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1991577914 Jun 11 03:43:49 PM PDT 24 Jun 11 03:43:54 PM PDT 24 953353441 ps
T372 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.956733960 Jun 11 03:43:49 PM PDT 24 Jun 11 03:43:54 PM PDT 24 225848500 ps
T373 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1246813725 Jun 11 03:43:59 PM PDT 24 Jun 11 03:44:11 PM PDT 24 3080316461 ps
T374 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.4294316482 Jun 11 03:44:08 PM PDT 24 Jun 11 03:44:16 PM PDT 24 448789961 ps
T375 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2614579992 Jun 11 03:44:07 PM PDT 24 Jun 11 03:44:19 PM PDT 24 4437324492 ps
T376 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2880494142 Jun 11 03:43:23 PM PDT 24 Jun 11 03:43:36 PM PDT 24 3556123926 ps
T377 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1512736249 Jun 11 03:43:58 PM PDT 24 Jun 11 03:44:03 PM PDT 24 2175414296 ps
T378 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.784539162 Jun 11 03:44:03 PM PDT 24 Jun 11 03:44:18 PM PDT 24 4991067362 ps
T379 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3620051148 Jun 11 03:43:56 PM PDT 24 Jun 11 03:44:00 PM PDT 24 305769131 ps
T380 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2625866809 Jun 11 03:43:47 PM PDT 24 Jun 11 03:44:30 PM PDT 24 15266533127 ps
T381 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3646588461 Jun 11 03:43:27 PM PDT 24 Jun 11 03:43:33 PM PDT 24 2350295164 ps
T382 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2480774552 Jun 11 03:43:54 PM PDT 24 Jun 11 03:43:59 PM PDT 24 343156676 ps
T383 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2794717844 Jun 11 03:43:46 PM PDT 24 Jun 11 03:43:54 PM PDT 24 341806503 ps
T384 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3592683722 Jun 11 03:44:08 PM PDT 24 Jun 11 03:44:14 PM PDT 24 4110929128 ps
T102 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.421375549 Jun 11 03:43:38 PM PDT 24 Jun 11 03:44:02 PM PDT 24 21627495015 ps
T385 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3115012880 Jun 11 03:43:32 PM PDT 24 Jun 11 03:43:33 PM PDT 24 275066614 ps
T386 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2534463944 Jun 11 03:44:03 PM PDT 24 Jun 11 03:44:09 PM PDT 24 1342606941 ps
T387 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1369650064 Jun 11 03:43:37 PM PDT 24 Jun 11 03:43:50 PM PDT 24 15150536404 ps
T388 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3863444610 Jun 11 03:43:36 PM PDT 24 Jun 11 03:43:39 PM PDT 24 227766923 ps
T389 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3436640742 Jun 11 03:43:22 PM PDT 24 Jun 11 03:43:27 PM PDT 24 1395758356 ps
T390 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1594928987 Jun 11 03:43:39 PM PDT 24 Jun 11 03:44:07 PM PDT 24 671323273 ps
T391 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3815374364 Jun 11 03:43:48 PM PDT 24 Jun 11 03:43:51 PM PDT 24 244090724 ps
T392 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.193490134 Jun 11 03:43:39 PM PDT 24 Jun 11 03:43:44 PM PDT 24 514287675 ps
T393 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3609809925 Jun 11 03:44:08 PM PDT 24 Jun 11 03:44:12 PM PDT 24 200155686 ps
T121 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.4063106467 Jun 11 03:43:39 PM PDT 24 Jun 11 03:43:42 PM PDT 24 716179438 ps
T394 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1812732387 Jun 11 03:44:06 PM PDT 24 Jun 11 03:44:09 PM PDT 24 112496218 ps
T395 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.279959976 Jun 11 03:44:07 PM PDT 24 Jun 11 03:44:11 PM PDT 24 4730838821 ps
T396 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1358532688 Jun 11 03:43:29 PM PDT 24 Jun 11 03:43:35 PM PDT 24 454760991 ps
T397 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.394300012 Jun 11 03:43:40 PM PDT 24 Jun 11 03:43:44 PM PDT 24 495830430 ps
T398 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1430635545 Jun 11 03:43:38 PM PDT 24 Jun 11 03:43:41 PM PDT 24 102797605 ps
T399 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2841320671 Jun 11 03:43:20 PM PDT 24 Jun 11 03:43:23 PM PDT 24 158314271 ps
T400 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1557731559 Jun 11 03:43:24 PM PDT 24 Jun 11 03:43:29 PM PDT 24 331649320 ps
T401 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.566673924 Jun 11 03:43:24 PM PDT 24 Jun 11 03:43:27 PM PDT 24 62794380 ps
T402 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.286264910 Jun 11 03:44:07 PM PDT 24 Jun 11 03:44:23 PM PDT 24 2260214977 ps
T403 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3497475220 Jun 11 03:43:48 PM PDT 24 Jun 11 03:43:52 PM PDT 24 271593475 ps
T404 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.630972 Jun 11 03:43:48 PM PDT 24 Jun 11 03:43:57 PM PDT 24 466590665 ps
T405 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1048814307 Jun 11 03:43:58 PM PDT 24 Jun 11 03:44:04 PM PDT 24 1688456836 ps
T406 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2704690758 Jun 11 03:43:39 PM PDT 24 Jun 11 03:43:41 PM PDT 24 165785880 ps
T407 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2609513701 Jun 11 03:43:55 PM PDT 24 Jun 11 03:45:09 PM PDT 24 50004469615 ps
T112 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1741877699 Jun 11 03:43:28 PM PDT 24 Jun 11 03:43:31 PM PDT 24 155177817 ps
T408 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1148492935 Jun 11 03:43:22 PM PDT 24 Jun 11 03:43:28 PM PDT 24 1190642839 ps
T409 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1226214301 Jun 11 03:43:48 PM PDT 24 Jun 11 03:44:02 PM PDT 24 4108215463 ps
T410 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2688958254 Jun 11 03:43:38 PM PDT 24 Jun 11 03:43:41 PM PDT 24 94151570 ps
T411 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2888511194 Jun 11 03:44:03 PM PDT 24 Jun 11 03:44:07 PM PDT 24 229415272 ps

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1107441342
Short name T4
Test name
Test status
Simulation time 5955099771 ps
CPU time 3.23 seconds
Started Jun 11 02:06:39 PM PDT 24
Finished Jun 11 02:06:45 PM PDT 24
Peak memory 213372 kb
Host smart-570c6e8e-8a80-4c17-a384-4213391b7889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107441342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1107441342
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2794646908
Short name T52
Test name
Test status
Simulation time 57958989506 ps
CPU time 166.19 seconds
Started Jun 11 03:43:46 PM PDT 24
Finished Jun 11 03:46:34 PM PDT 24
Peak memory 221600 kb
Host smart-db128ae8-271b-4e34-aab2-a9133e143200
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794646908 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.2794646908
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.1832518036
Short name T11
Test name
Test status
Simulation time 15167470048 ps
CPU time 43.4 seconds
Started Jun 11 02:06:44 PM PDT 24
Finished Jun 11 02:07:30 PM PDT 24
Peak memory 205040 kb
Host smart-31aa5665-4661-4aeb-acd1-32b6d34134ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832518036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1832518036
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.1476752842
Short name T42
Test name
Test status
Simulation time 18117230711 ps
CPU time 8.67 seconds
Started Jun 11 02:06:56 PM PDT 24
Finished Jun 11 02:07:07 PM PDT 24
Peak memory 205048 kb
Host smart-7be19833-d9be-44b5-8977-f49a62368b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476752842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1476752842
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3013177582
Short name T3
Test name
Test status
Simulation time 63236379 ps
CPU time 0.85 seconds
Started Jun 11 02:06:59 PM PDT 24
Finished Jun 11 02:07:01 PM PDT 24
Peak memory 204768 kb
Host smart-076da7e4-3c6d-4024-ab79-ebce016195a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013177582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3013177582
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2980898559
Short name T96
Test name
Test status
Simulation time 2551354400 ps
CPU time 12.1 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:44:01 PM PDT 24
Peak memory 213148 kb
Host smart-bdc539ac-4e76-491a-94c4-e279e2c10e69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980898559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2980898559
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1849782039
Short name T130
Test name
Test status
Simulation time 5160400594 ps
CPU time 8.32 seconds
Started Jun 11 02:06:42 PM PDT 24
Finished Jun 11 02:06:53 PM PDT 24
Peak memory 215032 kb
Host smart-3be34528-e2c5-4eb9-952c-5a1873ac1224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849782039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1849782039
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.2869091312
Short name T31
Test name
Test status
Simulation time 23723791048 ps
CPU time 33.55 seconds
Started Jun 11 02:06:39 PM PDT 24
Finished Jun 11 02:07:16 PM PDT 24
Peak memory 204912 kb
Host smart-d842184d-03db-4a40-a5e0-4883d2b751eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869091312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2869091312
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.902968299
Short name T49
Test name
Test status
Simulation time 406789191 ps
CPU time 2.23 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:30 PM PDT 24
Peak memory 237672 kb
Host smart-1a0ef324-6458-4036-8c64-27cf136663e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902968299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.902968299
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2130924586
Short name T136
Test name
Test status
Simulation time 1436216848 ps
CPU time 19.45 seconds
Started Jun 11 03:44:02 PM PDT 24
Finished Jun 11 03:44:23 PM PDT 24
Peak memory 213264 kb
Host smart-330c303b-a1e0-419f-9254-606cfd051b8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130924586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
130924586
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3490985185
Short name T87
Test name
Test status
Simulation time 90914219 ps
CPU time 1.62 seconds
Started Jun 11 03:43:58 PM PDT 24
Finished Jun 11 03:44:02 PM PDT 24
Peak memory 213324 kb
Host smart-eb4c75e3-b2e1-444b-b8f1-2c79feb7e52b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490985185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3490985185
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.1264402656
Short name T7
Test name
Test status
Simulation time 143236119 ps
CPU time 1.05 seconds
Started Jun 11 02:06:23 PM PDT 24
Finished Jun 11 02:06:25 PM PDT 24
Peak memory 204572 kb
Host smart-8f1573ed-75e9-41e2-97d2-81eef0a5b839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264402656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.1264402656
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.653343284
Short name T72
Test name
Test status
Simulation time 2736527922 ps
CPU time 9 seconds
Started Jun 11 02:06:43 PM PDT 24
Finished Jun 11 02:06:54 PM PDT 24
Peak memory 205064 kb
Host smart-feda065e-e36b-40f4-9552-7e7543f89590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653343284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.653343284
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.377616826
Short name T39
Test name
Test status
Simulation time 167406881 ps
CPU time 0.88 seconds
Started Jun 11 02:06:23 PM PDT 24
Finished Jun 11 02:06:25 PM PDT 24
Peak memory 212880 kb
Host smart-e50fd512-1825-4fae-8a52-6d4307b91955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377616826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.377616826
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1895023887
Short name T6
Test name
Test status
Simulation time 5080484805 ps
CPU time 14.02 seconds
Started Jun 11 02:06:22 PM PDT 24
Finished Jun 11 02:06:38 PM PDT 24
Peak memory 204968 kb
Host smart-03f452e2-3ea7-40ad-8058-2aecfaa21a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895023887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1895023887
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3350295057
Short name T133
Test name
Test status
Simulation time 4447343546 ps
CPU time 18.25 seconds
Started Jun 11 03:44:11 PM PDT 24
Finished Jun 11 03:44:31 PM PDT 24
Peak memory 213504 kb
Host smart-bc49a250-4544-4f4b-9ca7-56cff10595f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350295057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
350295057
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2087454132
Short name T107
Test name
Test status
Simulation time 214297782 ps
CPU time 2.26 seconds
Started Jun 11 03:43:38 PM PDT 24
Finished Jun 11 03:43:41 PM PDT 24
Peak memory 213320 kb
Host smart-9cf3d60e-4627-4869-9b4c-b5080f7969f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087454132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2087454132
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1748422245
Short name T47
Test name
Test status
Simulation time 170359149 ps
CPU time 0.95 seconds
Started Jun 11 02:06:22 PM PDT 24
Finished Jun 11 02:06:25 PM PDT 24
Peak memory 204668 kb
Host smart-2e6a4b71-622c-4834-b0b1-e5d799796da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748422245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1748422245
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.2905272318
Short name T22
Test name
Test status
Simulation time 26053496058 ps
CPU time 19.34 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:56 PM PDT 24
Peak memory 205016 kb
Host smart-0d1afee7-4a01-4249-9269-cb78288e40f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905272318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2905272318
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.210006484
Short name T234
Test name
Test status
Simulation time 25708354432 ps
CPU time 77.99 seconds
Started Jun 11 02:06:21 PM PDT 24
Finished Jun 11 02:07:41 PM PDT 24
Peak memory 205112 kb
Host smart-379e4724-4707-4b63-b73c-4af4dc09ed34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210006484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.210006484
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2274699487
Short name T84
Test name
Test status
Simulation time 517265726 ps
CPU time 4.2 seconds
Started Jun 11 03:43:54 PM PDT 24
Finished Jun 11 03:43:59 PM PDT 24
Peak memory 213404 kb
Host smart-d02a5948-3411-4e2b-8957-a62ed01d4ab1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274699487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2274699487
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3696197049
Short name T75
Test name
Test status
Simulation time 373745112 ps
CPU time 1.21 seconds
Started Jun 11 03:43:32 PM PDT 24
Finished Jun 11 03:43:34 PM PDT 24
Peak memory 204712 kb
Host smart-b1886a46-eea3-4fc5-84eb-a679ef0a3f91
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696197049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3696197049
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3762236812
Short name T89
Test name
Test status
Simulation time 1147750682 ps
CPU time 8.63 seconds
Started Jun 11 03:43:21 PM PDT 24
Finished Jun 11 03:43:32 PM PDT 24
Peak memory 205080 kb
Host smart-48fc278e-5610-47da-95e6-9b3e5510b11d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762236812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3762236812
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1266817907
Short name T101
Test name
Test status
Simulation time 8422758674 ps
CPU time 6.64 seconds
Started Jun 11 03:43:29 PM PDT 24
Finished Jun 11 03:43:37 PM PDT 24
Peak memory 205148 kb
Host smart-4ca81649-405f-4768-94a9-c6d42575895e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266817907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1266817907
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2173804344
Short name T37
Test name
Test status
Simulation time 841561171 ps
CPU time 2.9 seconds
Started Jun 11 02:06:26 PM PDT 24
Finished Jun 11 02:06:31 PM PDT 24
Peak memory 204552 kb
Host smart-bb7ce83e-8e0a-43c5-a902-c6fe06150c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173804344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2173804344
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3050551859
Short name T14
Test name
Test status
Simulation time 2328073610 ps
CPU time 6.76 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:34 PM PDT 24
Peak memory 204704 kb
Host smart-b140322b-ec46-44cb-af00-8f656e63e302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050551859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3050551859
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.62153986
Short name T196
Test name
Test status
Simulation time 88672505 ps
CPU time 0.72 seconds
Started Jun 11 02:06:44 PM PDT 24
Finished Jun 11 02:06:47 PM PDT 24
Peak memory 204668 kb
Host smart-31f75adc-9ac5-4d7d-a835-f6c44089110d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62153986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.62153986
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4092924553
Short name T135
Test name
Test status
Simulation time 2858228295 ps
CPU time 11.96 seconds
Started Jun 11 03:44:01 PM PDT 24
Finished Jun 11 03:44:15 PM PDT 24
Peak memory 221532 kb
Host smart-0eaac5d7-c3d2-48dc-894d-966efdc689c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092924553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.4
092924553
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3825252577
Short name T134
Test name
Test status
Simulation time 2121597014 ps
CPU time 9.3 seconds
Started Jun 11 03:44:03 PM PDT 24
Finished Jun 11 03:44:14 PM PDT 24
Peak memory 213336 kb
Host smart-4d2dc950-5fa6-45f8-8945-3cd020edb408
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825252577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
825252577
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1966460683
Short name T120
Test name
Test status
Simulation time 7957928346 ps
CPU time 31.39 seconds
Started Jun 11 03:43:22 PM PDT 24
Finished Jun 11 03:43:56 PM PDT 24
Peak memory 205392 kb
Host smart-3d52900c-d2e4-4d3c-9546-6ea7dd43d019
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966460683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1966460683
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2592007334
Short name T118
Test name
Test status
Simulation time 7388678495 ps
CPU time 54.53 seconds
Started Jun 11 03:43:23 PM PDT 24
Finished Jun 11 03:44:20 PM PDT 24
Peak memory 213456 kb
Host smart-bd86dfc8-e7f1-4b20-83b1-b40d349ba941
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592007334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2592007334
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1557731559
Short name T400
Test name
Test status
Simulation time 331649320 ps
CPU time 2.88 seconds
Started Jun 11 03:43:24 PM PDT 24
Finished Jun 11 03:43:29 PM PDT 24
Peak memory 213480 kb
Host smart-8eae254a-670e-4b97-acd1-48e67f7d432d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557731559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1557731559
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1841849311
Short name T156
Test name
Test status
Simulation time 193366387 ps
CPU time 4.19 seconds
Started Jun 11 03:43:19 PM PDT 24
Finished Jun 11 03:43:26 PM PDT 24
Peak memory 219208 kb
Host smart-415f972d-73f2-4d98-b4f5-a74ca417d005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841849311 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1841849311
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1562592199
Short name T115
Test name
Test status
Simulation time 161595409 ps
CPU time 1.82 seconds
Started Jun 11 03:43:23 PM PDT 24
Finished Jun 11 03:43:27 PM PDT 24
Peak memory 213296 kb
Host smart-bbe3e5cd-74a4-40f8-bc2d-6f790b5eb282
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562592199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1562592199
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1850022282
Short name T272
Test name
Test status
Simulation time 8861218589 ps
CPU time 4.77 seconds
Started Jun 11 03:43:23 PM PDT 24
Finished Jun 11 03:43:31 PM PDT 24
Peak memory 205092 kb
Host smart-2c77fa53-15e3-4390-ba45-e18533f85700
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850022282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.1850022282
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.458920481
Short name T324
Test name
Test status
Simulation time 9888591004 ps
CPU time 27.01 seconds
Started Jun 11 03:43:23 PM PDT 24
Finished Jun 11 03:43:53 PM PDT 24
Peak memory 205088 kb
Host smart-db318ba4-2815-4f23-a5bb-8bb187270f9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458920481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.458920481
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2319735216
Short name T305
Test name
Test status
Simulation time 3652478434 ps
CPU time 10.95 seconds
Started Jun 11 03:43:22 PM PDT 24
Finished Jun 11 03:43:35 PM PDT 24
Peak memory 205060 kb
Host smart-8254998e-9ad2-404e-9cac-3694b3ed59e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319735216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
319735216
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3436640742
Short name T389
Test name
Test status
Simulation time 1395758356 ps
CPU time 2.61 seconds
Started Jun 11 03:43:22 PM PDT 24
Finished Jun 11 03:43:27 PM PDT 24
Peak memory 204720 kb
Host smart-f10a9bef-0637-43ed-8b43-ef170ce48c25
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436640742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3436640742
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2880494142
Short name T376
Test name
Test status
Simulation time 3556123926 ps
CPU time 10.63 seconds
Started Jun 11 03:43:23 PM PDT 24
Finished Jun 11 03:43:36 PM PDT 24
Peak memory 204948 kb
Host smart-387f762a-4226-401f-86d4-b3121a577c29
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880494142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2880494142
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3611893882
Short name T335
Test name
Test status
Simulation time 1007152691 ps
CPU time 1.06 seconds
Started Jun 11 03:43:23 PM PDT 24
Finished Jun 11 03:43:26 PM PDT 24
Peak memory 204776 kb
Host smart-693914a3-7bd9-4f68-888d-72a27ad58eef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611893882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3611893882
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2841320671
Short name T399
Test name
Test status
Simulation time 158314271 ps
CPU time 0.92 seconds
Started Jun 11 03:43:20 PM PDT 24
Finished Jun 11 03:43:23 PM PDT 24
Peak memory 204700 kb
Host smart-50e25974-0e97-48a5-b777-6bbd49b55761
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841320671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
841320671
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.566673924
Short name T401
Test name
Test status
Simulation time 62794380 ps
CPU time 0.71 seconds
Started Jun 11 03:43:24 PM PDT 24
Finished Jun 11 03:43:27 PM PDT 24
Peak memory 204676 kb
Host smart-864ccffd-79ff-4ec8-8872-5cb1100ab44e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566673924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.566673924
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1573375438
Short name T370
Test name
Test status
Simulation time 51656133 ps
CPU time 0.69 seconds
Started Jun 11 03:43:23 PM PDT 24
Finished Jun 11 03:43:26 PM PDT 24
Peak memory 204760 kb
Host smart-e47a318f-c9b5-416e-ab58-a521bdcb44b5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573375438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1573375438
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3853292865
Short name T334
Test name
Test status
Simulation time 24141010137 ps
CPU time 27 seconds
Started Jun 11 03:43:23 PM PDT 24
Finished Jun 11 03:43:52 PM PDT 24
Peak memory 221556 kb
Host smart-c1d99429-a543-4ae1-9639-f70afa46c57c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853292865 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3853292865
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.104105840
Short name T157
Test name
Test status
Simulation time 291381806 ps
CPU time 4.73 seconds
Started Jun 11 03:43:23 PM PDT 24
Finished Jun 11 03:43:30 PM PDT 24
Peak memory 213288 kb
Host smart-1560520a-7b31-4be0-abef-b5baeefe26b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104105840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.104105840
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.785817338
Short name T310
Test name
Test status
Simulation time 1960142874 ps
CPU time 13.09 seconds
Started Jun 11 03:43:19 PM PDT 24
Finished Jun 11 03:43:35 PM PDT 24
Peak memory 213200 kb
Host smart-8b854555-b2bb-4987-bb0a-2ca6c334c629
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785817338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.785817338
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2249433768
Short name T351
Test name
Test status
Simulation time 6966713481 ps
CPU time 32.11 seconds
Started Jun 11 03:43:23 PM PDT 24
Finished Jun 11 03:43:57 PM PDT 24
Peak memory 205280 kb
Host smart-47d44a49-6805-40cd-9f39-a86ee9331613
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249433768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2249433768
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2270449816
Short name T91
Test name
Test status
Simulation time 10213647312 ps
CPU time 34.93 seconds
Started Jun 11 03:43:29 PM PDT 24
Finished Jun 11 03:44:04 PM PDT 24
Peak memory 213488 kb
Host smart-e2a77b2e-b490-4256-97a4-4bb97d5b23f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270449816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2270449816
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2207279731
Short name T113
Test name
Test status
Simulation time 286792972 ps
CPU time 2.62 seconds
Started Jun 11 03:43:30 PM PDT 24
Finished Jun 11 03:43:34 PM PDT 24
Peak memory 213464 kb
Host smart-67fcd772-f765-4fdb-a230-2ea6b36a0a2e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207279731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2207279731
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3329424324
Short name T313
Test name
Test status
Simulation time 223706228 ps
CPU time 2.28 seconds
Started Jun 11 03:43:29 PM PDT 24
Finished Jun 11 03:43:32 PM PDT 24
Peak memory 215952 kb
Host smart-625e9dc3-dec1-4609-81fb-8dca203edc61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329424324 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3329424324
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1741877699
Short name T112
Test name
Test status
Simulation time 155177817 ps
CPU time 2.12 seconds
Started Jun 11 03:43:28 PM PDT 24
Finished Jun 11 03:43:31 PM PDT 24
Peak memory 213248 kb
Host smart-3869d71a-f840-412b-b619-c84ca35868cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741877699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1741877699
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1529981033
Short name T259
Test name
Test status
Simulation time 17065093680 ps
CPU time 12.27 seconds
Started Jun 11 03:43:30 PM PDT 24
Finished Jun 11 03:43:44 PM PDT 24
Peak memory 204968 kb
Host smart-7a8a7030-2003-43e4-b4f8-c2485e93f75b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529981033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1529981033
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3646588461
Short name T381
Test name
Test status
Simulation time 2350295164 ps
CPU time 4.78 seconds
Started Jun 11 03:43:27 PM PDT 24
Finished Jun 11 03:43:33 PM PDT 24
Peak memory 205152 kb
Host smart-6ca45d78-7f1a-486b-b1ee-39ddd50b77dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646588461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
646588461
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4188554956
Short name T362
Test name
Test status
Simulation time 4595107249 ps
CPU time 14.4 seconds
Started Jun 11 03:43:28 PM PDT 24
Finished Jun 11 03:43:44 PM PDT 24
Peak memory 205016 kb
Host smart-96b3be1c-53ff-488f-a0b5-4aa36ee557e3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188554956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.4188554956
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1148492935
Short name T408
Test name
Test status
Simulation time 1190642839 ps
CPU time 3.04 seconds
Started Jun 11 03:43:22 PM PDT 24
Finished Jun 11 03:43:28 PM PDT 24
Peak memory 204780 kb
Host smart-e88e42fd-6db0-4df3-9149-12167fbe3b92
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148492935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1148492935
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.107575704
Short name T357
Test name
Test status
Simulation time 197595951 ps
CPU time 1.25 seconds
Started Jun 11 03:43:29 PM PDT 24
Finished Jun 11 03:43:32 PM PDT 24
Peak memory 204736 kb
Host smart-6095ced1-2ae4-4237-a31d-492ad86cb26b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107575704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.107575704
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3468794160
Short name T333
Test name
Test status
Simulation time 44135498 ps
CPU time 0.76 seconds
Started Jun 11 03:43:30 PM PDT 24
Finished Jun 11 03:43:32 PM PDT 24
Peak memory 204656 kb
Host smart-5f3bebf0-b549-4044-be7b-9caa8c54b366
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468794160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3468794160
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1596260383
Short name T363
Test name
Test status
Simulation time 112605411 ps
CPU time 0.85 seconds
Started Jun 11 03:43:30 PM PDT 24
Finished Jun 11 03:43:32 PM PDT 24
Peak memory 204752 kb
Host smart-9e99c591-e1ee-4cb7-8d8f-efecf8a29d05
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596260383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1596260383
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2568401412
Short name T367
Test name
Test status
Simulation time 2397556913 ps
CPU time 5.04 seconds
Started Jun 11 03:43:29 PM PDT 24
Finished Jun 11 03:43:36 PM PDT 24
Peak memory 205232 kb
Host smart-fdcfcb54-a707-4d88-ad05-0f5a960e6280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568401412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2568401412
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2976894306
Short name T327
Test name
Test status
Simulation time 61448129630 ps
CPU time 78.18 seconds
Started Jun 11 03:43:31 PM PDT 24
Finished Jun 11 03:44:50 PM PDT 24
Peak memory 222424 kb
Host smart-cd98e2d0-ac2b-4898-bda1-d55da90e5025
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976894306 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2976894306
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1358532688
Short name T396
Test name
Test status
Simulation time 454760991 ps
CPU time 4.98 seconds
Started Jun 11 03:43:29 PM PDT 24
Finished Jun 11 03:43:35 PM PDT 24
Peak memory 213336 kb
Host smart-d56d61c7-cdfd-4974-a97a-20f0d0c0a39a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358532688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1358532688
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.427575569
Short name T132
Test name
Test status
Simulation time 5184698332 ps
CPU time 18.94 seconds
Started Jun 11 03:43:30 PM PDT 24
Finished Jun 11 03:43:51 PM PDT 24
Peak memory 213508 kb
Host smart-125d8f08-09bc-4701-ba49-d2705845a154
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427575569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.427575569
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3271817608
Short name T56
Test name
Test status
Simulation time 1833868715 ps
CPU time 2.62 seconds
Started Jun 11 03:43:58 PM PDT 24
Finished Jun 11 03:44:02 PM PDT 24
Peak memory 215400 kb
Host smart-c2eeb7ad-4eda-453f-abc5-8ca39c55643b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271817608 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3271817608
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1301974782
Short name T326
Test name
Test status
Simulation time 18105768299 ps
CPU time 25.64 seconds
Started Jun 11 03:43:57 PM PDT 24
Finished Jun 11 03:44:25 PM PDT 24
Peak memory 205216 kb
Host smart-7931bf72-2773-49d4-be94-b1c68d298c2c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301974782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.1301974782
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1512736249
Short name T377
Test name
Test status
Simulation time 2175414296 ps
CPU time 2.41 seconds
Started Jun 11 03:43:58 PM PDT 24
Finished Jun 11 03:44:03 PM PDT 24
Peak memory 204912 kb
Host smart-c4323b3f-89ed-40e9-b165-88689d4bb862
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512736249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1512736249
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2222977456
Short name T304
Test name
Test status
Simulation time 583361620 ps
CPU time 2.25 seconds
Started Jun 11 03:43:58 PM PDT 24
Finished Jun 11 03:44:03 PM PDT 24
Peak memory 204756 kb
Host smart-df158de1-f156-4cdc-a034-e8c113fab764
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222977456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2222977456
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.621132417
Short name T108
Test name
Test status
Simulation time 474673498 ps
CPU time 7.79 seconds
Started Jun 11 03:43:57 PM PDT 24
Finished Jun 11 03:44:07 PM PDT 24
Peak memory 205192 kb
Host smart-b078f1f7-500a-48aa-ac61-544441daef1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621132417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.621132417
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2480774552
Short name T382
Test name
Test status
Simulation time 343156676 ps
CPU time 4.13 seconds
Started Jun 11 03:43:54 PM PDT 24
Finished Jun 11 03:43:59 PM PDT 24
Peak memory 213320 kb
Host smart-ba69850b-a13f-406a-bafb-d70e9ee2ad16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480774552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2480774552
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3099959613
Short name T318
Test name
Test status
Simulation time 1015979392 ps
CPU time 10.9 seconds
Started Jun 11 03:43:58 PM PDT 24
Finished Jun 11 03:44:11 PM PDT 24
Peak memory 213376 kb
Host smart-829ee994-9863-42e1-830e-687398e0b30c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099959613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
099959613
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2331839050
Short name T291
Test name
Test status
Simulation time 2581148402 ps
CPU time 7.39 seconds
Started Jun 11 03:43:57 PM PDT 24
Finished Jun 11 03:44:06 PM PDT 24
Peak memory 219352 kb
Host smart-c143351e-1c07-435e-bede-9f418ce3e1d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331839050 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2331839050
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3620051148
Short name T379
Test name
Test status
Simulation time 305769131 ps
CPU time 1.56 seconds
Started Jun 11 03:43:56 PM PDT 24
Finished Jun 11 03:44:00 PM PDT 24
Peak memory 213336 kb
Host smart-793059eb-83ca-4f43-9c8d-5dcef32566c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620051148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3620051148
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1627138339
Short name T275
Test name
Test status
Simulation time 42485810966 ps
CPU time 38 seconds
Started Jun 11 03:43:56 PM PDT 24
Finished Jun 11 03:44:36 PM PDT 24
Peak memory 205064 kb
Host smart-b1a07d2e-19ed-4528-9e3f-514374ff576d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627138339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1627138339
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2318052566
Short name T341
Test name
Test status
Simulation time 2406765988 ps
CPU time 2.88 seconds
Started Jun 11 03:43:58 PM PDT 24
Finished Jun 11 03:44:03 PM PDT 24
Peak memory 205000 kb
Host smart-5d8bb38e-9932-4507-b83a-6535940f8d27
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318052566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2318052566
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.537538158
Short name T294
Test name
Test status
Simulation time 423922522 ps
CPU time 1 seconds
Started Jun 11 03:43:59 PM PDT 24
Finished Jun 11 03:44:02 PM PDT 24
Peak memory 204736 kb
Host smart-3f7fce68-cb4b-4d6d-aadf-5a9c7ac41375
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537538158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.537538158
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2101310788
Short name T90
Test name
Test status
Simulation time 186506348 ps
CPU time 6.44 seconds
Started Jun 11 03:43:57 PM PDT 24
Finished Jun 11 03:44:06 PM PDT 24
Peak memory 205172 kb
Host smart-101614ef-fbcd-4635-ad41-f2009fb3d078
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101310788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2101310788
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3094587763
Short name T298
Test name
Test status
Simulation time 180200297 ps
CPU time 3.58 seconds
Started Jun 11 03:43:56 PM PDT 24
Finished Jun 11 03:44:01 PM PDT 24
Peak memory 213336 kb
Host smart-37679112-6d3b-4210-8ac0-f28e80cd535c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094587763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3094587763
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1246813725
Short name T373
Test name
Test status
Simulation time 3080316461 ps
CPU time 9.96 seconds
Started Jun 11 03:43:59 PM PDT 24
Finished Jun 11 03:44:11 PM PDT 24
Peak memory 213408 kb
Host smart-7d715777-cb34-4e23-9596-bc597c1b5f3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246813725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
246813725
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.734258675
Short name T301
Test name
Test status
Simulation time 582234164 ps
CPU time 4.35 seconds
Started Jun 11 03:43:59 PM PDT 24
Finished Jun 11 03:44:05 PM PDT 24
Peak memory 221536 kb
Host smart-b7ef4421-9f0b-4b73-a867-b6b3664fc56f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734258675 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.734258675
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3527771037
Short name T93
Test name
Test status
Simulation time 1231781596 ps
CPU time 2.47 seconds
Started Jun 11 03:43:57 PM PDT 24
Finished Jun 11 03:44:01 PM PDT 24
Peak memory 213336 kb
Host smart-72a085da-d8eb-4831-88bb-505d8524ebb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527771037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3527771037
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2629636052
Short name T284
Test name
Test status
Simulation time 22790138912 ps
CPU time 65.66 seconds
Started Jun 11 03:43:57 PM PDT 24
Finished Jun 11 03:45:05 PM PDT 24
Peak memory 205012 kb
Host smart-8ca49930-31c7-4a73-8247-7676f14a3db2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629636052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2629636052
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.882459096
Short name T306
Test name
Test status
Simulation time 4094553756 ps
CPU time 12.88 seconds
Started Jun 11 03:44:00 PM PDT 24
Finished Jun 11 03:44:15 PM PDT 24
Peak memory 205000 kb
Host smart-f5ca07ec-b516-46ed-831c-4fa9ea08cb66
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882459096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.882459096
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3664970458
Short name T303
Test name
Test status
Simulation time 516954732 ps
CPU time 1.43 seconds
Started Jun 11 03:43:59 PM PDT 24
Finished Jun 11 03:44:02 PM PDT 24
Peak memory 204772 kb
Host smart-4dfdc122-3cba-413b-ba9e-39fe40981fd1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664970458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3664970458
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3282687471
Short name T111
Test name
Test status
Simulation time 441271551 ps
CPU time 3.95 seconds
Started Jun 11 03:43:57 PM PDT 24
Finished Jun 11 03:44:03 PM PDT 24
Peak memory 205116 kb
Host smart-8248b59e-5871-4f54-ad78-84f74afc5d23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282687471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3282687471
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3446976469
Short name T83
Test name
Test status
Simulation time 1540717301 ps
CPU time 10.21 seconds
Started Jun 11 03:43:58 PM PDT 24
Finished Jun 11 03:44:11 PM PDT 24
Peak memory 213336 kb
Host smart-4e4f735c-583c-4c9a-8fb5-2409fd221a16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446976469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
446976469
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2394597971
Short name T269
Test name
Test status
Simulation time 114455029 ps
CPU time 2.41 seconds
Started Jun 11 03:44:04 PM PDT 24
Finished Jun 11 03:44:08 PM PDT 24
Peak memory 217076 kb
Host smart-8c8a5d6a-da27-43e5-86f8-a9bd04961602
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394597971 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2394597971
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2888511194
Short name T411
Test name
Test status
Simulation time 229415272 ps
CPU time 2.33 seconds
Started Jun 11 03:44:03 PM PDT 24
Finished Jun 11 03:44:07 PM PDT 24
Peak memory 213320 kb
Host smart-eaed87f6-fd5f-4e61-9fb3-f0ec0f0abd97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888511194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2888511194
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.240236912
Short name T358
Test name
Test status
Simulation time 18535880517 ps
CPU time 11.99 seconds
Started Jun 11 03:43:57 PM PDT 24
Finished Jun 11 03:44:11 PM PDT 24
Peak memory 205216 kb
Host smart-e5e6a48c-6daa-419d-b25e-62bfc368cc00
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240236912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
rv_dm_jtag_dmi_csr_bit_bash.240236912
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2852098686
Short name T263
Test name
Test status
Simulation time 2972768994 ps
CPU time 9.2 seconds
Started Jun 11 03:44:00 PM PDT 24
Finished Jun 11 03:44:11 PM PDT 24
Peak memory 204988 kb
Host smart-a326853d-3e44-4c5b-aa48-4026450649e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852098686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2852098686
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1567300240
Short name T286
Test name
Test status
Simulation time 144299122 ps
CPU time 1 seconds
Started Jun 11 03:43:56 PM PDT 24
Finished Jun 11 03:43:59 PM PDT 24
Peak memory 204764 kb
Host smart-ff27a35f-5d67-42ac-a32c-4e73ce9ca836
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567300240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1567300240
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.328718027
Short name T106
Test name
Test status
Simulation time 1185494464 ps
CPU time 8.38 seconds
Started Jun 11 03:44:02 PM PDT 24
Finished Jun 11 03:44:12 PM PDT 24
Peak memory 205084 kb
Host smart-bced2eb7-a1c2-4279-8e6e-7000a7ea1419
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328718027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.328718027
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.47610416
Short name T97
Test name
Test status
Simulation time 244281318 ps
CPU time 2.76 seconds
Started Jun 11 03:44:04 PM PDT 24
Finished Jun 11 03:44:08 PM PDT 24
Peak memory 213344 kb
Host smart-dfe75603-3333-4a98-bbc7-b7c8f8a03baf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47610416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.47610416
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1812732387
Short name T394
Test name
Test status
Simulation time 112496218 ps
CPU time 2.23 seconds
Started Jun 11 03:44:06 PM PDT 24
Finished Jun 11 03:44:09 PM PDT 24
Peak memory 221440 kb
Host smart-ca94fba1-7f5c-4c2f-bd6f-1bc5d6829722
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812732387 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1812732387
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3494920176
Short name T114
Test name
Test status
Simulation time 116814272 ps
CPU time 2.46 seconds
Started Jun 11 03:44:04 PM PDT 24
Finished Jun 11 03:44:07 PM PDT 24
Peak memory 213244 kb
Host smart-76a952b4-2cad-4c77-84f9-a94dec02c19e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494920176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3494920176
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3053448652
Short name T261
Test name
Test status
Simulation time 23211414897 ps
CPU time 37.41 seconds
Started Jun 11 03:44:07 PM PDT 24
Finished Jun 11 03:44:46 PM PDT 24
Peak memory 205080 kb
Host smart-9f94107b-fc65-4353-b5ec-0b36aa269147
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053448652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.3053448652
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.784539162
Short name T378
Test name
Test status
Simulation time 4991067362 ps
CPU time 13.52 seconds
Started Jun 11 03:44:03 PM PDT 24
Finished Jun 11 03:44:18 PM PDT 24
Peak memory 205052 kb
Host smart-4ae3d092-bb90-41d2-9227-12636ceb0b3b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784539162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.784539162
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4286505475
Short name T266
Test name
Test status
Simulation time 339131378 ps
CPU time 1.68 seconds
Started Jun 11 03:44:02 PM PDT 24
Finished Jun 11 03:44:05 PM PDT 24
Peak memory 204780 kb
Host smart-006233bf-d3fe-4c9f-ba20-0f6e9a7dd634
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286505475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
4286505475
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.113408429
Short name T104
Test name
Test status
Simulation time 719192566 ps
CPU time 8.26 seconds
Started Jun 11 03:44:05 PM PDT 24
Finished Jun 11 03:44:15 PM PDT 24
Peak memory 205128 kb
Host smart-af29ad7f-2b8d-48e9-8f5c-6cb591ff4d57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113408429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_
csr_outstanding.113408429
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.908567898
Short name T315
Test name
Test status
Simulation time 497043782 ps
CPU time 5.37 seconds
Started Jun 11 03:44:04 PM PDT 24
Finished Jun 11 03:44:12 PM PDT 24
Peak memory 213268 kb
Host smart-e34309b8-7b9e-4a38-b2b3-ea3f45ea3290
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908567898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.908567898
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.536983731
Short name T77
Test name
Test status
Simulation time 368390205 ps
CPU time 3.57 seconds
Started Jun 11 03:44:05 PM PDT 24
Finished Jun 11 03:44:10 PM PDT 24
Peak memory 219584 kb
Host smart-3d32fa95-1b75-4120-adc2-6b1dd8deb5d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536983731 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.536983731
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.175630430
Short name T94
Test name
Test status
Simulation time 51685596 ps
CPU time 2.11 seconds
Started Jun 11 03:44:06 PM PDT 24
Finished Jun 11 03:44:10 PM PDT 24
Peak memory 213320 kb
Host smart-cd584375-47e6-4579-b82b-3e914c4ec9a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175630430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.175630430
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.65798509
Short name T270
Test name
Test status
Simulation time 26189819422 ps
CPU time 80.24 seconds
Started Jun 11 03:44:03 PM PDT 24
Finished Jun 11 03:45:25 PM PDT 24
Peak memory 205096 kb
Host smart-35e6c109-da8b-4f1c-a227-32953c931a96
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65798509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.r
v_dm_jtag_dmi_csr_bit_bash.65798509
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1305913323
Short name T356
Test name
Test status
Simulation time 6085317347 ps
CPU time 5.04 seconds
Started Jun 11 03:44:03 PM PDT 24
Finished Jun 11 03:44:10 PM PDT 24
Peak memory 205048 kb
Host smart-f359ca3b-daf6-4ff5-9a66-9e428fb62a9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305913323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1305913323
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3481043568
Short name T349
Test name
Test status
Simulation time 265243480 ps
CPU time 1.47 seconds
Started Jun 11 03:44:02 PM PDT 24
Finished Jun 11 03:44:05 PM PDT 24
Peak memory 204764 kb
Host smart-afc26145-109f-45e6-b20a-d4b0d40eee15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481043568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3481043568
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3864896661
Short name T336
Test name
Test status
Simulation time 354072474 ps
CPU time 4.52 seconds
Started Jun 11 03:44:03 PM PDT 24
Finished Jun 11 03:44:08 PM PDT 24
Peak memory 205336 kb
Host smart-cc0772f2-8ff9-43de-9d54-0faf519d228c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864896661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3864896661
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2534463944
Short name T386
Test name
Test status
Simulation time 1342606941 ps
CPU time 5.33 seconds
Started Jun 11 03:44:03 PM PDT 24
Finished Jun 11 03:44:09 PM PDT 24
Peak memory 213340 kb
Host smart-3aa4bafe-3523-4db9-b8e9-5f2de4ec4e15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534463944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2534463944
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.766381121
Short name T76
Test name
Test status
Simulation time 704633821 ps
CPU time 3.91 seconds
Started Jun 11 03:44:07 PM PDT 24
Finished Jun 11 03:44:12 PM PDT 24
Peak memory 219576 kb
Host smart-fc5c486e-b521-40e7-aff9-c3d38e675a30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766381121 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.766381121
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3030485242
Short name T325
Test name
Test status
Simulation time 373311154 ps
CPU time 2.32 seconds
Started Jun 11 03:44:02 PM PDT 24
Finished Jun 11 03:44:06 PM PDT 24
Peak memory 213360 kb
Host smart-d1df6467-065a-4641-9a6f-df45e9ee4b3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030485242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3030485242
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.437290430
Short name T364
Test name
Test status
Simulation time 23319666738 ps
CPU time 18.24 seconds
Started Jun 11 03:44:04 PM PDT 24
Finished Jun 11 03:44:24 PM PDT 24
Peak memory 205096 kb
Host smart-2813f45a-3776-433d-9cc1-5f6d3a0e873e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437290430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
rv_dm_jtag_dmi_csr_bit_bash.437290430
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1037068287
Short name T309
Test name
Test status
Simulation time 15286913954 ps
CPU time 39.83 seconds
Started Jun 11 03:44:02 PM PDT 24
Finished Jun 11 03:44:43 PM PDT 24
Peak memory 205072 kb
Host smart-03aa70aa-3527-4044-a281-344cc502c311
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037068287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1037068287
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1606186886
Short name T302
Test name
Test status
Simulation time 458394983 ps
CPU time 1.83 seconds
Started Jun 11 03:44:04 PM PDT 24
Finished Jun 11 03:44:07 PM PDT 24
Peak memory 204740 kb
Host smart-272d8a7f-db3c-4762-97f6-aaf144159e0c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606186886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1606186886
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1246987065
Short name T322
Test name
Test status
Simulation time 317772712 ps
CPU time 4.48 seconds
Started Jun 11 03:44:07 PM PDT 24
Finished Jun 11 03:44:13 PM PDT 24
Peak memory 205140 kb
Host smart-3168358c-fa42-4eb6-9e58-dd14fb24de28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246987065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1246987065
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1821790162
Short name T125
Test name
Test status
Simulation time 281292218 ps
CPU time 5.73 seconds
Started Jun 11 03:44:04 PM PDT 24
Finished Jun 11 03:44:11 PM PDT 24
Peak memory 213292 kb
Host smart-f89308a8-3318-48ff-8252-96058437d3e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821790162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1821790162
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.286264910
Short name T402
Test name
Test status
Simulation time 2260214977 ps
CPU time 14.34 seconds
Started Jun 11 03:44:07 PM PDT 24
Finished Jun 11 03:44:23 PM PDT 24
Peak memory 213188 kb
Host smart-8f017881-42ce-4452-b477-7c87f211ab25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286264910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.286264910
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2614579992
Short name T375
Test name
Test status
Simulation time 4437324492 ps
CPU time 10.58 seconds
Started Jun 11 03:44:07 PM PDT 24
Finished Jun 11 03:44:19 PM PDT 24
Peak memory 219548 kb
Host smart-0197b920-fe28-4e59-8de0-44e794daf3b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614579992 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2614579992
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2067387950
Short name T59
Test name
Test status
Simulation time 217662815 ps
CPU time 2.68 seconds
Started Jun 11 03:44:09 PM PDT 24
Finished Jun 11 03:44:13 PM PDT 24
Peak memory 213172 kb
Host smart-f6ff6d8e-8d58-4d7a-9925-b8c69fe6cdc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067387950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2067387950
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.957518124
Short name T265
Test name
Test status
Simulation time 2981112279 ps
CPU time 6.02 seconds
Started Jun 11 03:44:09 PM PDT 24
Finished Jun 11 03:44:16 PM PDT 24
Peak memory 204860 kb
Host smart-2b6f6e6c-7338-45d0-bdcc-963c26de7798
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957518124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.957518124
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.576934157
Short name T297
Test name
Test status
Simulation time 3109894313 ps
CPU time 9.13 seconds
Started Jun 11 03:44:05 PM PDT 24
Finished Jun 11 03:44:16 PM PDT 24
Peak memory 204940 kb
Host smart-c49b63d5-0ecd-40ab-b95f-7f623cfd2f37
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576934157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.576934157
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3710199331
Short name T328
Test name
Test status
Simulation time 652947454 ps
CPU time 0.97 seconds
Started Jun 11 03:44:06 PM PDT 24
Finished Jun 11 03:44:08 PM PDT 24
Peak memory 204752 kb
Host smart-0e40d82c-f248-4835-b86e-a9cea178b707
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710199331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3710199331
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2838103364
Short name T307
Test name
Test status
Simulation time 510657047 ps
CPU time 4.25 seconds
Started Jun 11 03:44:06 PM PDT 24
Finished Jun 11 03:44:12 PM PDT 24
Peak memory 205124 kb
Host smart-37f70962-64d0-4c9b-8dd1-bb9c6f21e40a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838103364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2838103364
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1678954419
Short name T280
Test name
Test status
Simulation time 276313500 ps
CPU time 3.86 seconds
Started Jun 11 03:44:04 PM PDT 24
Finished Jun 11 03:44:09 PM PDT 24
Peak memory 213332 kb
Host smart-6b1c0cb0-f1f3-459c-a757-0c825b5016d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678954419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1678954419
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3284992199
Short name T353
Test name
Test status
Simulation time 2116177841 ps
CPU time 13.08 seconds
Started Jun 11 03:44:07 PM PDT 24
Finished Jun 11 03:44:22 PM PDT 24
Peak memory 213404 kb
Host smart-01daa10c-4d37-4bb7-b574-c84b8507ba6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284992199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
284992199
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.279959976
Short name T395
Test name
Test status
Simulation time 4730838821 ps
CPU time 2.56 seconds
Started Jun 11 03:44:07 PM PDT 24
Finished Jun 11 03:44:11 PM PDT 24
Peak memory 218008 kb
Host smart-abb00b4d-9f36-40cc-a01d-9380a9870b20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279959976 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.279959976
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1894603511
Short name T289
Test name
Test status
Simulation time 256298144 ps
CPU time 1.48 seconds
Started Jun 11 03:44:05 PM PDT 24
Finished Jun 11 03:44:08 PM PDT 24
Peak memory 213220 kb
Host smart-90d73570-a33c-48f3-9e9b-fc001aa7fafe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894603511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1894603511
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3344265955
Short name T331
Test name
Test status
Simulation time 4348523308 ps
CPU time 13.89 seconds
Started Jun 11 03:44:08 PM PDT 24
Finished Jun 11 03:44:24 PM PDT 24
Peak memory 204924 kb
Host smart-66ec847b-8de5-4af0-9e50-920490b32679
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344265955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.3344265955
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3592683722
Short name T384
Test name
Test status
Simulation time 4110929128 ps
CPU time 4.5 seconds
Started Jun 11 03:44:08 PM PDT 24
Finished Jun 11 03:44:14 PM PDT 24
Peak memory 205000 kb
Host smart-5c325e7a-1736-456e-aaf0-41df0632cc3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592683722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3592683722
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.768593249
Short name T337
Test name
Test status
Simulation time 290765437 ps
CPU time 1.16 seconds
Started Jun 11 03:44:08 PM PDT 24
Finished Jun 11 03:44:11 PM PDT 24
Peak memory 204608 kb
Host smart-e9aa21c3-48ae-4acd-8a1e-8a212282da2f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768593249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.768593249
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1370287459
Short name T88
Test name
Test status
Simulation time 226694752 ps
CPU time 3.6 seconds
Started Jun 11 03:44:04 PM PDT 24
Finished Jun 11 03:44:09 PM PDT 24
Peak memory 205052 kb
Host smart-79fa462a-8f2e-488c-b1b8-452e82d481f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370287459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1370287459
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3609809925
Short name T393
Test name
Test status
Simulation time 200155686 ps
CPU time 2.57 seconds
Started Jun 11 03:44:08 PM PDT 24
Finished Jun 11 03:44:12 PM PDT 24
Peak memory 213168 kb
Host smart-8775a212-7623-47cf-89bd-7c5702a3083b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609809925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3609809925
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3447744063
Short name T128
Test name
Test status
Simulation time 2221900754 ps
CPU time 17.92 seconds
Started Jun 11 03:44:07 PM PDT 24
Finished Jun 11 03:44:27 PM PDT 24
Peak memory 221556 kb
Host smart-5acb1408-2a99-4df7-bfe2-3448c1d834b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447744063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
447744063
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3939908558
Short name T339
Test name
Test status
Simulation time 3358863921 ps
CPU time 5.23 seconds
Started Jun 11 03:44:09 PM PDT 24
Finished Jun 11 03:44:16 PM PDT 24
Peak memory 219244 kb
Host smart-3d8efdfd-4bf0-4dda-95cc-6b24e124770e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939908558 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3939908558
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.268714198
Short name T116
Test name
Test status
Simulation time 122267097 ps
CPU time 1.72 seconds
Started Jun 11 03:44:10 PM PDT 24
Finished Jun 11 03:44:13 PM PDT 24
Peak memory 213228 kb
Host smart-2e050a84-f486-4e86-a9c6-464bc1cc350f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268714198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.268714198
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.511658942
Short name T308
Test name
Test status
Simulation time 9826375824 ps
CPU time 27.23 seconds
Started Jun 11 03:44:08 PM PDT 24
Finished Jun 11 03:44:37 PM PDT 24
Peak memory 205016 kb
Host smart-593e45b9-01b8-4f08-9945-7411df825644
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511658942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.511658942
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.689651974
Short name T274
Test name
Test status
Simulation time 1560048988 ps
CPU time 3.02 seconds
Started Jun 11 03:44:07 PM PDT 24
Finished Jun 11 03:44:12 PM PDT 24
Peak memory 204884 kb
Host smart-9388f6b3-76b5-4186-9b8a-f8338428f58a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689651974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.689651974
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1748617656
Short name T268
Test name
Test status
Simulation time 705808192 ps
CPU time 1.01 seconds
Started Jun 11 03:44:06 PM PDT 24
Finished Jun 11 03:44:08 PM PDT 24
Peak memory 204768 kb
Host smart-e451e890-7f39-4de6-a47a-62abe7654aca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748617656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1748617656
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.996627883
Short name T122
Test name
Test status
Simulation time 485277212 ps
CPU time 4.2 seconds
Started Jun 11 03:44:11 PM PDT 24
Finished Jun 11 03:44:16 PM PDT 24
Peak memory 205072 kb
Host smart-b0d4adf2-3f9f-4038-af09-253835fd475c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996627883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.996627883
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.4294316482
Short name T374
Test name
Test status
Simulation time 448789961 ps
CPU time 5.66 seconds
Started Jun 11 03:44:08 PM PDT 24
Finished Jun 11 03:44:16 PM PDT 24
Peak memory 213260 kb
Host smart-f788dd93-b84a-44ab-b5a7-cf4a9ac83348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294316482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.4294316482
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2648353423
Short name T369
Test name
Test status
Simulation time 6967543033 ps
CPU time 27.03 seconds
Started Jun 11 03:43:29 PM PDT 24
Finished Jun 11 03:43:57 PM PDT 24
Peak memory 205160 kb
Host smart-1e052a9d-8e0b-49df-aae8-43df406475e2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648353423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2648353423
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.633240
Short name T117
Test name
Test status
Simulation time 10883399787 ps
CPU time 53.88 seconds
Started Jun 11 03:43:37 PM PDT 24
Finished Jun 11 03:44:32 PM PDT 24
Peak memory 213408 kb
Host smart-3ba0d61e-a04d-44b2-85ea-8ce6ff01a457
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.633240
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.193490134
Short name T392
Test name
Test status
Simulation time 514287675 ps
CPU time 3.49 seconds
Started Jun 11 03:43:39 PM PDT 24
Finished Jun 11 03:43:44 PM PDT 24
Peak memory 214432 kb
Host smart-d74234c5-ca13-4767-80a8-cc0618929e60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193490134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.193490134
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3584547068
Short name T58
Test name
Test status
Simulation time 548117181 ps
CPU time 3.26 seconds
Started Jun 11 03:43:40 PM PDT 24
Finished Jun 11 03:43:44 PM PDT 24
Peak memory 221516 kb
Host smart-8725db42-4103-4462-93ba-36061907866c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584547068 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3584547068
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1430635545
Short name T398
Test name
Test status
Simulation time 102797605 ps
CPU time 2.43 seconds
Started Jun 11 03:43:38 PM PDT 24
Finished Jun 11 03:43:41 PM PDT 24
Peak memory 213540 kb
Host smart-529edd54-d743-4c91-b2bd-038573a0994b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430635545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1430635545
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.817634885
Short name T329
Test name
Test status
Simulation time 81209260964 ps
CPU time 242.8 seconds
Started Jun 11 03:43:39 PM PDT 24
Finished Jun 11 03:47:43 PM PDT 24
Peak memory 205076 kb
Host smart-0e042b9f-b491-4ac4-aacc-a95a16c343bf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817634885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.817634885
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1757011020
Short name T360
Test name
Test status
Simulation time 21142024734 ps
CPU time 61.17 seconds
Started Jun 11 03:43:39 PM PDT 24
Finished Jun 11 03:44:41 PM PDT 24
Peak memory 205092 kb
Host smart-1afeb73a-846d-47e0-b8fd-5370e1b8938c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757011020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1757011020
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2921537598
Short name T100
Test name
Test status
Simulation time 14535259002 ps
CPU time 38.25 seconds
Started Jun 11 03:43:40 PM PDT 24
Finished Jun 11 03:44:19 PM PDT 24
Peak memory 205204 kb
Host smart-cc2e35f8-3e95-4f13-91bc-3daa87452f0c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921537598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2921537598
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.884762218
Short name T330
Test name
Test status
Simulation time 2919939952 ps
CPU time 9 seconds
Started Jun 11 03:43:37 PM PDT 24
Finished Jun 11 03:43:47 PM PDT 24
Peak memory 205004 kb
Host smart-ccf66398-c6fa-4a04-a5ee-2f77bb5f160b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884762218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.884762218
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3696304563
Short name T350
Test name
Test status
Simulation time 871259037 ps
CPU time 1.16 seconds
Started Jun 11 03:43:38 PM PDT 24
Finished Jun 11 03:43:41 PM PDT 24
Peak memory 204756 kb
Host smart-283b9a63-02f4-4019-b557-ae24f9eefb86
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696304563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3696304563
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1536799616
Short name T281
Test name
Test status
Simulation time 43819295789 ps
CPU time 58.88 seconds
Started Jun 11 03:43:29 PM PDT 24
Finished Jun 11 03:44:29 PM PDT 24
Peak memory 205048 kb
Host smart-1ba0864a-9e6c-44f6-9bf0-293d4d446253
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536799616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1536799616
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2257722552
Short name T74
Test name
Test status
Simulation time 1389103461 ps
CPU time 4.47 seconds
Started Jun 11 03:43:28 PM PDT 24
Finished Jun 11 03:43:34 PM PDT 24
Peak memory 204732 kb
Host smart-6739b538-b888-45c0-af92-de4394d0ae04
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257722552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2257722552
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3115012880
Short name T385
Test name
Test status
Simulation time 275066614 ps
CPU time 0.95 seconds
Started Jun 11 03:43:32 PM PDT 24
Finished Jun 11 03:43:33 PM PDT 24
Peak memory 204728 kb
Host smart-53f17a54-dbea-4945-ae9a-968c55322c21
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115012880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
115012880
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2688958254
Short name T410
Test name
Test status
Simulation time 94151570 ps
CPU time 0.88 seconds
Started Jun 11 03:43:38 PM PDT 24
Finished Jun 11 03:43:41 PM PDT 24
Peak memory 204692 kb
Host smart-e2f2ca21-a7a2-4d04-be9e-23c42ac28a3b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688958254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2688958254
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2704690758
Short name T406
Test name
Test status
Simulation time 165785880 ps
CPU time 0.73 seconds
Started Jun 11 03:43:39 PM PDT 24
Finished Jun 11 03:43:41 PM PDT 24
Peak memory 204724 kb
Host smart-b7379cfb-b3b2-4bc5-9d56-a446d95f284e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704690758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2704690758
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.376863879
Short name T323
Test name
Test status
Simulation time 205378827 ps
CPU time 3.67 seconds
Started Jun 11 03:43:37 PM PDT 24
Finished Jun 11 03:43:41 PM PDT 24
Peak memory 205116 kb
Host smart-d9c7595c-8fd5-4337-8e34-81abc248ff95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376863879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.376863879
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2324055052
Short name T78
Test name
Test status
Simulation time 29170471815 ps
CPU time 45.05 seconds
Started Jun 11 03:43:37 PM PDT 24
Finished Jun 11 03:44:23 PM PDT 24
Peak memory 221504 kb
Host smart-0178e9e9-7e2e-41d5-8962-cfe63f4e2417
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324055052 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2324055052
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.394300012
Short name T397
Test name
Test status
Simulation time 495830430 ps
CPU time 3.26 seconds
Started Jun 11 03:43:40 PM PDT 24
Finished Jun 11 03:43:44 PM PDT 24
Peak memory 213392 kb
Host smart-d24f718b-e18a-48c0-a58a-2c6e35ee06ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394300012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.394300012
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.656260311
Short name T126
Test name
Test status
Simulation time 3842484153 ps
CPU time 9.87 seconds
Started Jun 11 03:43:36 PM PDT 24
Finished Jun 11 03:43:46 PM PDT 24
Peak memory 213464 kb
Host smart-3a3b16ab-7bac-456f-9451-5c78dbecb471
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656260311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.656260311
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1594928987
Short name T390
Test name
Test status
Simulation time 671323273 ps
CPU time 26.34 seconds
Started Jun 11 03:43:39 PM PDT 24
Finished Jun 11 03:44:07 PM PDT 24
Peak memory 213356 kb
Host smart-78e96e1a-0908-44a2-9309-99490b4dc81c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594928987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1594928987
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2625866809
Short name T380
Test name
Test status
Simulation time 15266533127 ps
CPU time 41.49 seconds
Started Jun 11 03:43:47 PM PDT 24
Finished Jun 11 03:44:30 PM PDT 24
Peak memory 213504 kb
Host smart-55e99796-9eba-478c-ad93-05fb90af89bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625866809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2625866809
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.4063106467
Short name T121
Test name
Test status
Simulation time 716179438 ps
CPU time 2.78 seconds
Started Jun 11 03:43:39 PM PDT 24
Finished Jun 11 03:43:42 PM PDT 24
Peak memory 214420 kb
Host smart-4643a775-cb03-4f5e-9326-52458cc3fb78
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063106467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.4063106467
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2198193255
Short name T278
Test name
Test status
Simulation time 4555151734 ps
CPU time 7.78 seconds
Started Jun 11 03:43:46 PM PDT 24
Finished Jun 11 03:43:55 PM PDT 24
Peak memory 221392 kb
Host smart-f21a3f39-94af-4ad2-b644-373c22d54c1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198193255 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2198193255
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.265540308
Short name T260
Test name
Test status
Simulation time 111049606551 ps
CPU time 307.73 seconds
Started Jun 11 03:43:38 PM PDT 24
Finished Jun 11 03:48:47 PM PDT 24
Peak memory 205080 kb
Host smart-a6d8845d-70d7-4031-9e08-4b9d380babdd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265540308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.265540308
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1369650064
Short name T387
Test name
Test status
Simulation time 15150536404 ps
CPU time 11.78 seconds
Started Jun 11 03:43:37 PM PDT 24
Finished Jun 11 03:43:50 PM PDT 24
Peak memory 205104 kb
Host smart-045f2f5a-1aa1-4a58-8497-9c62f298a23d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369650064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.1369650064
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.421375549
Short name T102
Test name
Test status
Simulation time 21627495015 ps
CPU time 22.51 seconds
Started Jun 11 03:43:38 PM PDT 24
Finished Jun 11 03:44:02 PM PDT 24
Peak memory 213412 kb
Host smart-0e46ac43-a76f-443a-b677-4cd31ee107aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421375549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.421375549
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1503006472
Short name T271
Test name
Test status
Simulation time 6520844334 ps
CPU time 6.9 seconds
Started Jun 11 03:43:38 PM PDT 24
Finished Jun 11 03:43:46 PM PDT 24
Peak memory 205092 kb
Host smart-b557022e-6ef2-4c24-b52c-dd308733d705
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503006472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
503006472
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4066650156
Short name T283
Test name
Test status
Simulation time 3487112920 ps
CPU time 2.43 seconds
Started Jun 11 03:43:40 PM PDT 24
Finished Jun 11 03:43:44 PM PDT 24
Peak memory 204772 kb
Host smart-aea80c7b-e418-41fd-8d97-e761e29016e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066650156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.4066650156
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3475437882
Short name T277
Test name
Test status
Simulation time 8079141506 ps
CPU time 6.8 seconds
Started Jun 11 03:43:39 PM PDT 24
Finished Jun 11 03:43:47 PM PDT 24
Peak memory 205020 kb
Host smart-ec9e3668-7d6e-4dc5-9ddc-a4cc708e4e24
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475437882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3475437882
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1206141546
Short name T290
Test name
Test status
Simulation time 472439947 ps
CPU time 0.97 seconds
Started Jun 11 03:43:38 PM PDT 24
Finished Jun 11 03:43:40 PM PDT 24
Peak memory 204776 kb
Host smart-dc2895b9-41fd-40f7-902b-92eaa41179b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206141546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1206141546
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3181111679
Short name T279
Test name
Test status
Simulation time 423934120 ps
CPU time 1.73 seconds
Started Jun 11 03:43:38 PM PDT 24
Finished Jun 11 03:43:41 PM PDT 24
Peak memory 204768 kb
Host smart-b9fcdb19-6a78-454e-b53c-84caab86c56b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181111679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
181111679
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2495827107
Short name T361
Test name
Test status
Simulation time 75139790 ps
CPU time 0.75 seconds
Started Jun 11 03:43:37 PM PDT 24
Finished Jun 11 03:43:39 PM PDT 24
Peak memory 204664 kb
Host smart-810f3f17-1b72-4f48-82e8-21fd759b686c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495827107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2495827107
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3497452715
Short name T285
Test name
Test status
Simulation time 50883337 ps
CPU time 0.67 seconds
Started Jun 11 03:43:39 PM PDT 24
Finished Jun 11 03:43:41 PM PDT 24
Peak memory 204764 kb
Host smart-f3bad4b9-26d1-4f8c-a614-09ae492149c2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497452715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3497452715
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.630972
Short name T404
Test name
Test status
Simulation time 466590665 ps
CPU time 7.36 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:43:57 PM PDT 24
Peak memory 205196 kb
Host smart-f3e87fbd-d8ba-4a91-9044-6f8be99b27da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_csr_
outstanding.630972
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.68333851
Short name T292
Test name
Test status
Simulation time 35295927267 ps
CPU time 54.51 seconds
Started Jun 11 03:43:37 PM PDT 24
Finished Jun 11 03:44:33 PM PDT 24
Peak memory 221596 kb
Host smart-d82883e4-9b87-458d-83dd-af2207dd6399
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68333851 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.68333851
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3863444610
Short name T388
Test name
Test status
Simulation time 227766923 ps
CPU time 2.59 seconds
Started Jun 11 03:43:36 PM PDT 24
Finished Jun 11 03:43:39 PM PDT 24
Peak memory 213308 kb
Host smart-6ae8fc33-8607-4fcf-a7ce-33cfc758f47e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863444610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3863444610
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1735082372
Short name T127
Test name
Test status
Simulation time 1649487209 ps
CPU time 21.67 seconds
Started Jun 11 03:43:38 PM PDT 24
Finished Jun 11 03:44:00 PM PDT 24
Peak memory 213400 kb
Host smart-073eccea-3ab8-491e-a45a-4df34a4234e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735082372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1735082372
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3351162743
Short name T110
Test name
Test status
Simulation time 3487144024 ps
CPU time 74.85 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:45:04 PM PDT 24
Peak memory 213396 kb
Host smart-eae05844-03af-4fb2-a384-1bc7fa1305b1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351162743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3351162743
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1882117638
Short name T92
Test name
Test status
Simulation time 10314441380 ps
CPU time 33.79 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:44:23 PM PDT 24
Peak memory 205384 kb
Host smart-d70d74dc-8d88-42dd-bd2a-92fcb3b98fc8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882117638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1882117638
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1180402586
Short name T346
Test name
Test status
Simulation time 280544947 ps
CPU time 1.63 seconds
Started Jun 11 03:43:51 PM PDT 24
Finished Jun 11 03:43:54 PM PDT 24
Peak memory 213324 kb
Host smart-2b02caab-4051-4a50-8127-f96614882a5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180402586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1180402586
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.125665978
Short name T300
Test name
Test status
Simulation time 2902620330 ps
CPU time 7.43 seconds
Started Jun 11 03:43:50 PM PDT 24
Finished Jun 11 03:43:59 PM PDT 24
Peak memory 218452 kb
Host smart-3553f1e9-00fa-4ddd-9222-db7d3c8e0d3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125665978 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.125665978
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1090563658
Short name T340
Test name
Test status
Simulation time 227640127 ps
CPU time 1.55 seconds
Started Jun 11 03:43:50 PM PDT 24
Finished Jun 11 03:43:53 PM PDT 24
Peak memory 213376 kb
Host smart-5c4cb8c5-9cf1-4eaf-b659-46b34c04241d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090563658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1090563658
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.562069486
Short name T368
Test name
Test status
Simulation time 120724922567 ps
CPU time 160.61 seconds
Started Jun 11 03:43:47 PM PDT 24
Finished Jun 11 03:46:29 PM PDT 24
Peak memory 205024 kb
Host smart-c9c54d12-0535-464f-9a6e-0a6d7d601c24
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562069486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.562069486
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2704021289
Short name T314
Test name
Test status
Simulation time 23612270037 ps
CPU time 21.33 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:44:11 PM PDT 24
Peak memory 204652 kb
Host smart-5125b47b-044b-495c-bff7-ea40985f09f7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704021289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.2704021289
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.340267591
Short name T99
Test name
Test status
Simulation time 8566844136 ps
CPU time 6.93 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:43:57 PM PDT 24
Peak memory 205252 kb
Host smart-53efaa8b-89de-473a-86c2-1dc9c5a5410d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340267591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.340267591
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.384453063
Short name T264
Test name
Test status
Simulation time 5212596625 ps
CPU time 14.51 seconds
Started Jun 11 03:43:47 PM PDT 24
Finished Jun 11 03:44:03 PM PDT 24
Peak memory 205056 kb
Host smart-a85af13a-1175-4cc1-9100-99831eae2064
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384453063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.384453063
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1991577914
Short name T371
Test name
Test status
Simulation time 953353441 ps
CPU time 3.1 seconds
Started Jun 11 03:43:49 PM PDT 24
Finished Jun 11 03:43:54 PM PDT 24
Peak memory 204760 kb
Host smart-30ecff7b-ebf5-4eb4-9206-c6c6900a0dae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991577914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1991577914
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1983925596
Short name T296
Test name
Test status
Simulation time 4628116742 ps
CPU time 12.92 seconds
Started Jun 11 03:43:49 PM PDT 24
Finished Jun 11 03:44:04 PM PDT 24
Peak memory 205052 kb
Host smart-3e99222a-9d31-40e9-934e-e80f1a546446
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983925596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1983925596
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2396415874
Short name T355
Test name
Test status
Simulation time 778944637 ps
CPU time 2.56 seconds
Started Jun 11 03:43:47 PM PDT 24
Finished Jun 11 03:43:51 PM PDT 24
Peak memory 204788 kb
Host smart-40bdcf43-4cdc-49fe-bd63-7236f961e942
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396415874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2396415874
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3122563805
Short name T348
Test name
Test status
Simulation time 201007469 ps
CPU time 1.01 seconds
Started Jun 11 03:43:49 PM PDT 24
Finished Jun 11 03:43:51 PM PDT 24
Peak memory 204744 kb
Host smart-2fdf4f0c-387b-4da5-b61d-ee216a5bc8f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122563805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
122563805
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3591241580
Short name T262
Test name
Test status
Simulation time 66489449 ps
CPU time 0.87 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:43:51 PM PDT 24
Peak memory 204652 kb
Host smart-0c53a7bf-b0cc-4116-a5dc-5fd5939f5ee5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591241580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3591241580
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3665195792
Short name T276
Test name
Test status
Simulation time 82318491 ps
CPU time 0.67 seconds
Started Jun 11 03:43:46 PM PDT 24
Finished Jun 11 03:43:48 PM PDT 24
Peak memory 204760 kb
Host smart-d958bc66-5091-4b1d-add3-3363d1c0854d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665195792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3665195792
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3868508861
Short name T109
Test name
Test status
Simulation time 1516804247 ps
CPU time 4.3 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:43:54 PM PDT 24
Peak memory 205092 kb
Host smart-0c6050da-73c7-431d-876e-31e5e8a1bd50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868508861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3868508861
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2549102554
Short name T320
Test name
Test status
Simulation time 21161998764 ps
CPU time 35.15 seconds
Started Jun 11 03:43:46 PM PDT 24
Finished Jun 11 03:44:23 PM PDT 24
Peak memory 219864 kb
Host smart-a4385ffc-3eeb-4163-b22f-bb04d1ae6bff
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549102554 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2549102554
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2392793223
Short name T347
Test name
Test status
Simulation time 119803748 ps
CPU time 3.08 seconds
Started Jun 11 03:43:46 PM PDT 24
Finished Jun 11 03:43:50 PM PDT 24
Peak memory 213328 kb
Host smart-9d6c48e7-f2fe-4eda-bad8-bd52ff41b0cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392793223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2392793223
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1108959602
Short name T338
Test name
Test status
Simulation time 3400751968 ps
CPU time 21.14 seconds
Started Jun 11 03:43:46 PM PDT 24
Finished Jun 11 03:44:08 PM PDT 24
Peak memory 213416 kb
Host smart-76cc4500-e0a7-4332-ad64-efa9c1f97431
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108959602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1108959602
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2908913463
Short name T151
Test name
Test status
Simulation time 1686664790 ps
CPU time 6.1 seconds
Started Jun 11 03:43:50 PM PDT 24
Finished Jun 11 03:43:57 PM PDT 24
Peak memory 220300 kb
Host smart-5a84422c-1877-4053-9fc7-e480640542e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908913463 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2908913463
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3497475220
Short name T403
Test name
Test status
Simulation time 271593475 ps
CPU time 2.54 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:43:52 PM PDT 24
Peak memory 213396 kb
Host smart-dcf0e70b-cf54-4fd2-82e0-ef52bfea2113
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497475220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3497475220
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1418607317
Short name T295
Test name
Test status
Simulation time 17976104591 ps
CPU time 16.79 seconds
Started Jun 11 03:43:47 PM PDT 24
Finished Jun 11 03:44:05 PM PDT 24
Peak memory 205036 kb
Host smart-c9890a62-ad5d-46fd-8c1d-08d2718d782d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418607317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.1418607317
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2190027387
Short name T312
Test name
Test status
Simulation time 7043784170 ps
CPU time 18.6 seconds
Started Jun 11 03:43:49 PM PDT 24
Finished Jun 11 03:44:09 PM PDT 24
Peak memory 205020 kb
Host smart-4dcdad52-d9eb-4fb0-bd74-5b84aa0d7887
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190027387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
190027387
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2177027553
Short name T359
Test name
Test status
Simulation time 358102008 ps
CPU time 1.17 seconds
Started Jun 11 03:43:49 PM PDT 24
Finished Jun 11 03:43:52 PM PDT 24
Peak memory 204716 kb
Host smart-6f9a7f74-293c-4e02-8d62-39431cac849a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177027553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
177027553
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2794717844
Short name T383
Test name
Test status
Simulation time 341806503 ps
CPU time 6.73 seconds
Started Jun 11 03:43:46 PM PDT 24
Finished Jun 11 03:43:54 PM PDT 24
Peak memory 205048 kb
Host smart-875ddea9-d637-4d1f-9ea4-de2849d2ff9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794717844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2794717844
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.795839994
Short name T319
Test name
Test status
Simulation time 70249131714 ps
CPU time 123.13 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:45:53 PM PDT 24
Peak memory 224388 kb
Host smart-335ccc46-12a3-43ec-bf17-ef03c24bd366
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795839994 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.795839994
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.956733960
Short name T372
Test name
Test status
Simulation time 225848500 ps
CPU time 3.13 seconds
Started Jun 11 03:43:49 PM PDT 24
Finished Jun 11 03:43:54 PM PDT 24
Peak memory 213224 kb
Host smart-c4e64387-cb1a-4f0b-90c3-5ecfa36bc34d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956733960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.956733960
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1226214301
Short name T409
Test name
Test status
Simulation time 4108215463 ps
CPU time 12.01 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:44:02 PM PDT 24
Peak memory 213444 kb
Host smart-b6548f7d-642c-483b-af34-eada4a0a77d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226214301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1226214301
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3094051046
Short name T57
Test name
Test status
Simulation time 281555689 ps
CPU time 2.29 seconds
Started Jun 11 03:43:49 PM PDT 24
Finished Jun 11 03:43:53 PM PDT 24
Peak memory 215432 kb
Host smart-d15dfd96-13fe-453d-9b9e-ec50e1ae4e5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094051046 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3094051046
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3815374364
Short name T391
Test name
Test status
Simulation time 244090724 ps
CPU time 2.31 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:43:51 PM PDT 24
Peak memory 213356 kb
Host smart-42018eda-f577-4fd2-b442-bb81102ef6ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815374364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3815374364
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1490341561
Short name T366
Test name
Test status
Simulation time 46615007694 ps
CPU time 123.65 seconds
Started Jun 11 03:43:46 PM PDT 24
Finished Jun 11 03:45:52 PM PDT 24
Peak memory 205000 kb
Host smart-093779b4-41ff-4dbf-882b-895496bf2959
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490341561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.1490341561
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1187147596
Short name T311
Test name
Test status
Simulation time 2944285799 ps
CPU time 3.59 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:43:53 PM PDT 24
Peak memory 204996 kb
Host smart-448de07b-3217-4e30-b9cd-b114915a29bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187147596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
187147596
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1071107849
Short name T73
Test name
Test status
Simulation time 1138016955 ps
CPU time 2.09 seconds
Started Jun 11 03:43:47 PM PDT 24
Finished Jun 11 03:43:50 PM PDT 24
Peak memory 204656 kb
Host smart-c4483c5a-d849-4056-a04b-a5c31fb4f03f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071107849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
071107849
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2667700454
Short name T103
Test name
Test status
Simulation time 1795921271 ps
CPU time 7.42 seconds
Started Jun 11 03:43:46 PM PDT 24
Finished Jun 11 03:43:55 PM PDT 24
Peak memory 205116 kb
Host smart-baae7ac5-c146-425f-aaaa-8c4dd073b671
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667700454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2667700454
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2822258474
Short name T317
Test name
Test status
Simulation time 394041987 ps
CPU time 4.58 seconds
Started Jun 11 03:43:49 PM PDT 24
Finished Jun 11 03:43:55 PM PDT 24
Peak memory 213356 kb
Host smart-d3c64639-ff81-49d1-b02b-21dd4d7940c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822258474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2822258474
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3676005264
Short name T365
Test name
Test status
Simulation time 98613141 ps
CPU time 2.42 seconds
Started Jun 11 03:43:56 PM PDT 24
Finished Jun 11 03:44:01 PM PDT 24
Peak memory 221628 kb
Host smart-67fe96df-0ded-4a2f-a7b6-85670cb287b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676005264 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3676005264
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4052972686
Short name T321
Test name
Test status
Simulation time 780323995 ps
CPU time 1.61 seconds
Started Jun 11 03:43:55 PM PDT 24
Finished Jun 11 03:43:59 PM PDT 24
Peak memory 213272 kb
Host smart-fb1af771-bcc5-4490-b0c6-6846bb3b1ebe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052972686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.4052972686
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.4259540455
Short name T282
Test name
Test status
Simulation time 23109270837 ps
CPU time 61.57 seconds
Started Jun 11 03:43:58 PM PDT 24
Finished Jun 11 03:45:02 PM PDT 24
Peak memory 204968 kb
Host smart-b3fc24f9-b7ea-4222-896c-669b1f21373d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259540455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.4259540455
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.56909462
Short name T332
Test name
Test status
Simulation time 1601598042 ps
CPU time 1.72 seconds
Started Jun 11 03:43:48 PM PDT 24
Finished Jun 11 03:43:52 PM PDT 24
Peak memory 204928 kb
Host smart-2b977407-4230-4cbf-a5aa-2cd3d077a480
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56909462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.56909462
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3685981075
Short name T354
Test name
Test status
Simulation time 234840574 ps
CPU time 1.27 seconds
Started Jun 11 03:43:46 PM PDT 24
Finished Jun 11 03:43:49 PM PDT 24
Peak memory 204776 kb
Host smart-ef64876f-6d20-475d-a2cc-8ff9bd5ccac7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685981075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
685981075
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3332676801
Short name T123
Test name
Test status
Simulation time 255005533 ps
CPU time 6.59 seconds
Started Jun 11 03:43:56 PM PDT 24
Finished Jun 11 03:44:05 PM PDT 24
Peak memory 205096 kb
Host smart-717f86cf-39f0-4095-9b8b-2ed8c96569d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332676801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3332676801
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1405743336
Short name T53
Test name
Test status
Simulation time 70280090792 ps
CPU time 126.17 seconds
Started Jun 11 03:43:57 PM PDT 24
Finished Jun 11 03:46:05 PM PDT 24
Peak memory 225896 kb
Host smart-d14b6299-54ec-4f51-95d4-aa47516fcaa5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405743336 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1405743336
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.260428596
Short name T293
Test name
Test status
Simulation time 289993900 ps
CPU time 4.69 seconds
Started Jun 11 03:43:56 PM PDT 24
Finished Jun 11 03:44:02 PM PDT 24
Peak memory 213428 kb
Host smart-a7010521-5008-415c-a39b-c424a7feadc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260428596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.260428596
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.628295921
Short name T138
Test name
Test status
Simulation time 2840294544 ps
CPU time 18.09 seconds
Started Jun 11 03:43:59 PM PDT 24
Finished Jun 11 03:44:19 PM PDT 24
Peak memory 213400 kb
Host smart-3c0c7480-6311-49dd-927c-57604bfac16b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628295921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.628295921
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1048814307
Short name T405
Test name
Test status
Simulation time 1688456836 ps
CPU time 3.54 seconds
Started Jun 11 03:43:58 PM PDT 24
Finished Jun 11 03:44:04 PM PDT 24
Peak memory 221072 kb
Host smart-51d1de74-2b2a-41b9-b431-4a01f2b6cb6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048814307 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1048814307
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2443584337
Short name T119
Test name
Test status
Simulation time 164059176 ps
CPU time 1.62 seconds
Started Jun 11 03:43:57 PM PDT 24
Finished Jun 11 03:44:00 PM PDT 24
Peak memory 213324 kb
Host smart-3a0f75f6-0b81-49e8-b1ca-a4f0414a65f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443584337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2443584337
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2836082385
Short name T345
Test name
Test status
Simulation time 81083263878 ps
CPU time 57.48 seconds
Started Jun 11 03:43:57 PM PDT 24
Finished Jun 11 03:44:57 PM PDT 24
Peak memory 205068 kb
Host smart-7dc8fb20-ca53-49a6-84e2-82b009000b87
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836082385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.2836082385
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2047664729
Short name T299
Test name
Test status
Simulation time 5880446043 ps
CPU time 4.55 seconds
Started Jun 11 03:43:55 PM PDT 24
Finished Jun 11 03:44:01 PM PDT 24
Peak memory 205076 kb
Host smart-75b6a1bd-25db-4a76-a655-0abb60271255
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047664729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2
047664729
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2852288930
Short name T288
Test name
Test status
Simulation time 927534614 ps
CPU time 3.19 seconds
Started Jun 11 03:43:56 PM PDT 24
Finished Jun 11 03:44:01 PM PDT 24
Peak memory 204736 kb
Host smart-ff085e5b-8016-45a7-9289-68e50376441a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852288930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
852288930
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.6333828
Short name T352
Test name
Test status
Simulation time 3765710224 ps
CPU time 8.18 seconds
Started Jun 11 03:43:58 PM PDT 24
Finished Jun 11 03:44:08 PM PDT 24
Peak memory 205184 kb
Host smart-3fc2894f-ada6-49d0-adc8-02dced2a2f02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6333828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_csr
_outstanding.6333828
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2928083338
Short name T342
Test name
Test status
Simulation time 34147110836 ps
CPU time 26.42 seconds
Started Jun 11 03:43:55 PM PDT 24
Finished Jun 11 03:44:22 PM PDT 24
Peak memory 221620 kb
Host smart-eee2675a-5d88-499f-99a2-1e54d87f25d5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928083338 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.2928083338
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.491271952
Short name T344
Test name
Test status
Simulation time 238278153 ps
CPU time 5.95 seconds
Started Jun 11 03:43:57 PM PDT 24
Finished Jun 11 03:44:05 PM PDT 24
Peak memory 213344 kb
Host smart-58a6a21e-cffa-4177-a3f6-90a4ec5e5705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491271952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.491271952
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1866424277
Short name T131
Test name
Test status
Simulation time 4588273122 ps
CPU time 20.85 seconds
Started Jun 11 03:43:54 PM PDT 24
Finished Jun 11 03:44:16 PM PDT 24
Peak memory 213628 kb
Host smart-fcce67ae-f11f-484c-8340-cbf6a154643c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866424277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1866424277
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3428296917
Short name T316
Test name
Test status
Simulation time 2375739914 ps
CPU time 6.92 seconds
Started Jun 11 03:43:58 PM PDT 24
Finished Jun 11 03:44:07 PM PDT 24
Peak memory 218968 kb
Host smart-653610dc-51ce-42d5-97cb-34832a240e36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428296917 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3428296917
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1721985146
Short name T95
Test name
Test status
Simulation time 158274735 ps
CPU time 1.48 seconds
Started Jun 11 03:43:55 PM PDT 24
Finished Jun 11 03:43:58 PM PDT 24
Peak memory 213248 kb
Host smart-a69980b8-fb93-4238-a952-9c5009db8c54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721985146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1721985146
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3783795319
Short name T343
Test name
Test status
Simulation time 7422332134 ps
CPU time 21.34 seconds
Started Jun 11 03:43:56 PM PDT 24
Finished Jun 11 03:44:19 PM PDT 24
Peak memory 205024 kb
Host smart-7988b8c0-080c-4a69-92ae-07d94ddc7f86
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783795319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3783795319
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3626878695
Short name T267
Test name
Test status
Simulation time 6678008680 ps
CPU time 17.34 seconds
Started Jun 11 03:43:57 PM PDT 24
Finished Jun 11 03:44:17 PM PDT 24
Peak memory 205056 kb
Host smart-f3a46180-9cd4-41ef-bfc5-eb2cf8772923
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626878695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
626878695
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4281509643
Short name T273
Test name
Test status
Simulation time 655364247 ps
CPU time 0.86 seconds
Started Jun 11 03:43:55 PM PDT 24
Finished Jun 11 03:43:57 PM PDT 24
Peak memory 204744 kb
Host smart-ba39dd46-6d54-491a-ae84-c351160ff52f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281509643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.4
281509643
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2209320537
Short name T105
Test name
Test status
Simulation time 549659233 ps
CPU time 3.67 seconds
Started Jun 11 03:43:55 PM PDT 24
Finished Jun 11 03:44:00 PM PDT 24
Peak memory 205168 kb
Host smart-108f1baa-d674-4d90-a5fb-9fed910c6d96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209320537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2209320537
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2609513701
Short name T407
Test name
Test status
Simulation time 50004469615 ps
CPU time 73.18 seconds
Started Jun 11 03:43:55 PM PDT 24
Finished Jun 11 03:45:09 PM PDT 24
Peak memory 221584 kb
Host smart-307f6441-f5e6-4633-93b2-54c1a0298cb8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609513701 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2609513701
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3194590862
Short name T287
Test name
Test status
Simulation time 69595834 ps
CPU time 4.2 seconds
Started Jun 11 03:43:55 PM PDT 24
Finished Jun 11 03:44:00 PM PDT 24
Peak memory 213292 kb
Host smart-f82e24f2-9c92-4459-8563-5918fb25c065
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194590862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3194590862
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1840784636
Short name T137
Test name
Test status
Simulation time 1816031094 ps
CPU time 11.38 seconds
Started Jun 11 03:43:58 PM PDT 24
Finished Jun 11 03:44:11 PM PDT 24
Peak memory 213344 kb
Host smart-aaa1132d-e7a8-4149-a04a-ea74f3b6d257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840784636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1840784636
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.4133734064
Short name T153
Test name
Test status
Simulation time 184577503 ps
CPU time 0.71 seconds
Started Jun 11 02:06:24 PM PDT 24
Finished Jun 11 02:06:26 PM PDT 24
Peak memory 204652 kb
Host smart-bbedf343-7be7-411a-a69e-c61a670a9493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133734064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.4133734064
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1988732748
Short name T230
Test name
Test status
Simulation time 5963085913 ps
CPU time 5.62 seconds
Started Jun 11 02:06:23 PM PDT 24
Finished Jun 11 02:06:30 PM PDT 24
Peak memory 205168 kb
Host smart-0c791466-1b0c-4886-95c3-88a16887e103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988732748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1988732748
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3603738526
Short name T143
Test name
Test status
Simulation time 24439886610 ps
CPU time 6.65 seconds
Started Jun 11 02:06:23 PM PDT 24
Finished Jun 11 02:06:31 PM PDT 24
Peak memory 205088 kb
Host smart-095992bc-3aa3-4ebd-b02c-9676719d26a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603738526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3603738526
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.434381813
Short name T27
Test name
Test status
Simulation time 7085211590 ps
CPU time 20.34 seconds
Started Jun 11 02:06:24 PM PDT 24
Finished Jun 11 02:06:46 PM PDT 24
Peak memory 204968 kb
Host smart-0365f234-023e-48ef-8f97-08df765a271d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434381813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.434381813
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2732389872
Short name T5
Test name
Test status
Simulation time 451286584 ps
CPU time 0.98 seconds
Started Jun 11 02:06:27 PM PDT 24
Finished Jun 11 02:06:30 PM PDT 24
Peak memory 204648 kb
Host smart-8bfa9a31-f5b7-4e44-83a2-822f483400ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732389872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2732389872
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3829022809
Short name T237
Test name
Test status
Simulation time 3246601070 ps
CPU time 4.38 seconds
Started Jun 11 02:06:23 PM PDT 24
Finished Jun 11 02:06:29 PM PDT 24
Peak memory 205192 kb
Host smart-67fd1ecf-5902-42d7-8e2f-bcbb0aca7094
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3829022809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3829022809
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2063364868
Short name T41
Test name
Test status
Simulation time 487152876 ps
CPU time 1.48 seconds
Started Jun 11 02:06:26 PM PDT 24
Finished Jun 11 02:06:30 PM PDT 24
Peak memory 204664 kb
Host smart-d9700f84-db3c-4977-aacc-234c9f0b0ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063364868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2063364868
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1217758866
Short name T243
Test name
Test status
Simulation time 197418293 ps
CPU time 0.86 seconds
Started Jun 11 02:06:27 PM PDT 24
Finished Jun 11 02:06:30 PM PDT 24
Peak memory 204520 kb
Host smart-52d149cb-1e3a-4459-b010-b33be888ecd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217758866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1217758866
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2888385905
Short name T19
Test name
Test status
Simulation time 2911060866 ps
CPU time 8.5 seconds
Started Jun 11 02:06:24 PM PDT 24
Finished Jun 11 02:06:35 PM PDT 24
Peak memory 204620 kb
Host smart-b90b8ade-f12a-4ccb-b686-1ebb6c843d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888385905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2888385905
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2783006302
Short name T249
Test name
Test status
Simulation time 1376334580 ps
CPU time 1.98 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:29 PM PDT 24
Peak memory 204560 kb
Host smart-e33c5260-77b8-4ea0-8c67-25a774087f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783006302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2783006302
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2743329326
Short name T23
Test name
Test status
Simulation time 1266860954 ps
CPU time 2.62 seconds
Started Jun 11 02:06:20 PM PDT 24
Finished Jun 11 02:06:24 PM PDT 24
Peak memory 204724 kb
Host smart-c8ed2922-1e5d-4af9-ac03-86a5e68d8721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743329326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2743329326
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1546981934
Short name T26
Test name
Test status
Simulation time 101852051 ps
CPU time 0.82 seconds
Started Jun 11 02:06:26 PM PDT 24
Finished Jun 11 02:06:29 PM PDT 24
Peak memory 204500 kb
Host smart-025c37dd-7875-44a4-8fb9-bdc9736b4829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546981934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1546981934
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2006571862
Short name T145
Test name
Test status
Simulation time 750056584 ps
CPU time 1.6 seconds
Started Jun 11 02:06:22 PM PDT 24
Finished Jun 11 02:06:25 PM PDT 24
Peak memory 204632 kb
Host smart-dedd6bd9-a000-40bc-a9e2-b01ed013e18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006571862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2006571862
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3786491262
Short name T147
Test name
Test status
Simulation time 3311684801 ps
CPU time 9.9 seconds
Started Jun 11 02:06:24 PM PDT 24
Finished Jun 11 02:06:36 PM PDT 24
Peak memory 204964 kb
Host smart-4fbf749d-2173-40d5-98f3-689765a70f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786491262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3786491262
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3915860862
Short name T20
Test name
Test status
Simulation time 1137361850 ps
CPU time 4.16 seconds
Started Jun 11 02:06:24 PM PDT 24
Finished Jun 11 02:06:31 PM PDT 24
Peak memory 204704 kb
Host smart-cad349ca-7be1-4994-b669-58d4573e4bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915860862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3915860862
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.544504602
Short name T46
Test name
Test status
Simulation time 261012065 ps
CPU time 0.87 seconds
Started Jun 11 02:06:27 PM PDT 24
Finished Jun 11 02:06:30 PM PDT 24
Peak memory 204576 kb
Host smart-d35c5d6c-f016-4dcf-8277-3474d8f4c60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544504602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.544504602
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.4259106316
Short name T40
Test name
Test status
Simulation time 77751083 ps
CPU time 1.01 seconds
Started Jun 11 02:06:22 PM PDT 24
Finished Jun 11 02:06:24 PM PDT 24
Peak memory 212832 kb
Host smart-4b8d0b31-eeb1-4f83-8e8d-259c6f48e94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259106316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.4259106316
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3599757935
Short name T192
Test name
Test status
Simulation time 7066561865 ps
CPU time 10.76 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:38 PM PDT 24
Peak memory 205200 kb
Host smart-6cbba213-2b94-4dfe-9a5d-615e39390569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599757935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3599757935
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2527420999
Short name T51
Test name
Test status
Simulation time 643820027 ps
CPU time 1.89 seconds
Started Jun 11 02:06:26 PM PDT 24
Finished Jun 11 02:06:30 PM PDT 24
Peak memory 237596 kb
Host smart-f201b558-dc2d-424d-b914-f5f8757dde22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527420999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2527420999
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.4169978679
Short name T194
Test name
Test status
Simulation time 1075496844 ps
CPU time 4.1 seconds
Started Jun 11 02:06:26 PM PDT 24
Finished Jun 11 02:06:32 PM PDT 24
Peak memory 204724 kb
Host smart-f232770a-31c6-4534-9065-b35e9659d76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169978679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.4169978679
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2903350797
Short name T30
Test name
Test status
Simulation time 5778852713 ps
CPU time 10.22 seconds
Started Jun 11 02:06:27 PM PDT 24
Finished Jun 11 02:06:39 PM PDT 24
Peak memory 204724 kb
Host smart-12ca12ff-f7e1-4fb0-905d-df4192f81535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903350797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2903350797
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.623311202
Short name T48
Test name
Test status
Simulation time 392965523 ps
CPU time 1.03 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:28 PM PDT 24
Peak memory 204632 kb
Host smart-20b9bbc9-e7a6-48d4-be7c-29cdb918a291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623311202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.623311202
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1205811703
Short name T154
Test name
Test status
Simulation time 59925401 ps
CPU time 0.73 seconds
Started Jun 11 02:06:27 PM PDT 24
Finished Jun 11 02:06:30 PM PDT 24
Peak memory 204716 kb
Host smart-9c911e45-14fb-46cc-aa32-313ead8657bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205811703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1205811703
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2907502030
Short name T240
Test name
Test status
Simulation time 37509990624 ps
CPU time 53.73 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:07:22 PM PDT 24
Peak memory 213416 kb
Host smart-28ac350f-d1aa-4df6-b2cb-bcf167e5b78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907502030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2907502030
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.760760919
Short name T209
Test name
Test status
Simulation time 7932291408 ps
CPU time 9.41 seconds
Started Jun 11 02:06:22 PM PDT 24
Finished Jun 11 02:06:33 PM PDT 24
Peak memory 213312 kb
Host smart-66d0a63c-fd7b-497d-b475-44158f96dacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760760919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.760760919
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.4218517147
Short name T9
Test name
Test status
Simulation time 36383326021 ps
CPU time 40.22 seconds
Started Jun 11 02:06:24 PM PDT 24
Finished Jun 11 02:07:07 PM PDT 24
Peak memory 205040 kb
Host smart-59dc2d3a-c4ba-48a3-96cd-4ba2a35582ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218517147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.4218517147
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.295568634
Short name T45
Test name
Test status
Simulation time 732360591 ps
CPU time 1.79 seconds
Started Jun 11 02:06:27 PM PDT 24
Finished Jun 11 02:06:31 PM PDT 24
Peak memory 204644 kb
Host smart-31fadcca-ab1d-41c7-9f13-d4068303676e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295568634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.295568634
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3881175194
Short name T38
Test name
Test status
Simulation time 533768282 ps
CPU time 2.21 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:29 PM PDT 24
Peak memory 204524 kb
Host smart-fbd74816-4453-4348-8a42-68f2aeaf6659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881175194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3881175194
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2218691666
Short name T195
Test name
Test status
Simulation time 13473797421 ps
CPU time 8.12 seconds
Started Jun 11 02:06:26 PM PDT 24
Finished Jun 11 02:06:36 PM PDT 24
Peak memory 205036 kb
Host smart-fe4ae8b5-f66c-4234-9757-4bbae3660491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218691666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2218691666
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1121531903
Short name T29
Test name
Test status
Simulation time 329339961 ps
CPU time 1.64 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:29 PM PDT 24
Peak memory 204664 kb
Host smart-c4929074-7e90-452a-aa74-4ccff9cd2dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121531903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1121531903
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3817501200
Short name T36
Test name
Test status
Simulation time 4267540780 ps
CPU time 2.76 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:30 PM PDT 24
Peak memory 205224 kb
Host smart-2a4cb1b3-b585-4baf-8520-47be2acbb5ac
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817501200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3817501200
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1255407661
Short name T18
Test name
Test status
Simulation time 1495187970 ps
CPU time 1.85 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:29 PM PDT 24
Peak memory 204664 kb
Host smart-ba319b10-efbe-46a2-a432-129e4a7619e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255407661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1255407661
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.306229498
Short name T178
Test name
Test status
Simulation time 469769011 ps
CPU time 0.9 seconds
Started Jun 11 02:06:24 PM PDT 24
Finished Jun 11 02:06:27 PM PDT 24
Peak memory 204580 kb
Host smart-e2f12175-8474-4d4d-8899-c479fa06c021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306229498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.306229498
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.814446387
Short name T228
Test name
Test status
Simulation time 861678862 ps
CPU time 2.2 seconds
Started Jun 11 02:06:26 PM PDT 24
Finished Jun 11 02:06:31 PM PDT 24
Peak memory 204736 kb
Host smart-afb16c8b-f24b-4216-a80f-12357904ebfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814446387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.814446387
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3995419490
Short name T225
Test name
Test status
Simulation time 1899191551 ps
CPU time 5.58 seconds
Started Jun 11 02:06:26 PM PDT 24
Finished Jun 11 02:06:34 PM PDT 24
Peak memory 204544 kb
Host smart-fe5b6c50-8d21-4f46-bcfc-67302c39b962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995419490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3995419490
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.728920522
Short name T257
Test name
Test status
Simulation time 884701029 ps
CPU time 2.22 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:30 PM PDT 24
Peak memory 204684 kb
Host smart-e26147c5-8215-402d-940a-4fcb224db103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728920522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.728920522
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1622163744
Short name T238
Test name
Test status
Simulation time 208649236 ps
CPU time 0.81 seconds
Started Jun 11 02:06:26 PM PDT 24
Finished Jun 11 02:06:29 PM PDT 24
Peak memory 204536 kb
Host smart-b53330ff-69a6-4787-83d2-6507f91fc264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622163744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1622163744
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1762045667
Short name T10
Test name
Test status
Simulation time 365934269 ps
CPU time 1.65 seconds
Started Jun 11 02:06:27 PM PDT 24
Finished Jun 11 02:06:31 PM PDT 24
Peak memory 204576 kb
Host smart-40cc819d-4863-4d06-89cf-18d4874c2c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762045667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1762045667
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3401852706
Short name T17
Test name
Test status
Simulation time 733652041 ps
CPU time 2.01 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:29 PM PDT 24
Peak memory 204708 kb
Host smart-f92ad263-a1ee-4650-8711-fbda7b87ce2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401852706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3401852706
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3462587456
Short name T86
Test name
Test status
Simulation time 3726249387 ps
CPU time 6 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:34 PM PDT 24
Peak memory 205024 kb
Host smart-43c4a65f-a4d6-451a-8857-e9e11381ab23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462587456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3462587456
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.578457570
Short name T43
Test name
Test status
Simulation time 1072454511 ps
CPU time 2.97 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:30 PM PDT 24
Peak memory 204684 kb
Host smart-fa3e84c4-60b3-4704-bda7-39d5c11ebee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578457570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.578457570
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3481973669
Short name T62
Test name
Test status
Simulation time 3115093436 ps
CPU time 9.1 seconds
Started Jun 11 02:06:27 PM PDT 24
Finished Jun 11 02:06:38 PM PDT 24
Peak memory 205036 kb
Host smart-260d495a-a05a-4f0e-bf8b-2e1508b2f52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481973669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3481973669
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2632831693
Short name T1
Test name
Test status
Simulation time 2092895491 ps
CPU time 6.87 seconds
Started Jun 11 02:06:25 PM PDT 24
Finished Jun 11 02:06:34 PM PDT 24
Peak memory 204532 kb
Host smart-e991359f-5060-4de0-998c-4bf42d0216f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632831693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2632831693
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.2506879093
Short name T252
Test name
Test status
Simulation time 16618820814 ps
CPU time 25.58 seconds
Started Jun 11 02:06:24 PM PDT 24
Finished Jun 11 02:06:52 PM PDT 24
Peak memory 204952 kb
Host smart-a98e86a2-02d2-4ed7-b22b-8a1228444974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506879093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2506879093
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.537909379
Short name T163
Test name
Test status
Simulation time 44879569 ps
CPU time 0.84 seconds
Started Jun 11 02:06:39 PM PDT 24
Finished Jun 11 02:06:43 PM PDT 24
Peak memory 204664 kb
Host smart-7018704f-ab5b-4d0f-8f10-e891ee0ac494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537909379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.537909379
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3706611155
Short name T188
Test name
Test status
Simulation time 22485990170 ps
CPU time 37.16 seconds
Started Jun 11 02:06:39 PM PDT 24
Finished Jun 11 02:07:20 PM PDT 24
Peak memory 213352 kb
Host smart-6692d50b-4e22-4eab-b8dd-99056d9fa694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706611155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3706611155
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1783171875
Short name T250
Test name
Test status
Simulation time 7171539156 ps
CPU time 7.63 seconds
Started Jun 11 02:06:34 PM PDT 24
Finished Jun 11 02:06:43 PM PDT 24
Peak memory 214628 kb
Host smart-0878ffb9-cd89-4bee-b4f4-1c60883e9444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783171875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1783171875
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.75555148
Short name T181
Test name
Test status
Simulation time 10681306063 ps
CPU time 4.11 seconds
Started Jun 11 02:06:38 PM PDT 24
Finished Jun 11 02:06:45 PM PDT 24
Peak memory 205124 kb
Host smart-56e7a341-7c54-4dc6-afba-76afa49999f4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75555148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_tl
_access.75555148
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1994186457
Short name T13
Test name
Test status
Simulation time 2848941448 ps
CPU time 4.78 seconds
Started Jun 11 02:06:40 PM PDT 24
Finished Jun 11 02:06:48 PM PDT 24
Peak memory 205172 kb
Host smart-5a6068e0-66c3-4bf4-806b-5f635980313d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994186457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1994186457
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.3572894277
Short name T139
Test name
Test status
Simulation time 30354081552 ps
CPU time 23.9 seconds
Started Jun 11 02:06:38 PM PDT 24
Finished Jun 11 02:07:05 PM PDT 24
Peak memory 213168 kb
Host smart-05e52d69-fee5-4db8-9748-0a73813f1456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572894277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3572894277
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.23976823
Short name T199
Test name
Test status
Simulation time 33075776 ps
CPU time 0.76 seconds
Started Jun 11 02:06:37 PM PDT 24
Finished Jun 11 02:06:41 PM PDT 24
Peak memory 204664 kb
Host smart-10c003e4-6a07-4401-bc4f-261b3e239baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23976823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.23976823
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.483297468
Short name T16
Test name
Test status
Simulation time 45896961723 ps
CPU time 24.08 seconds
Started Jun 11 02:06:39 PM PDT 24
Finished Jun 11 02:07:06 PM PDT 24
Peak memory 221488 kb
Host smart-7a56ecb5-1bde-412b-bc8b-84257ae5aeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483297468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.483297468
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2116136267
Short name T222
Test name
Test status
Simulation time 1307986070 ps
CPU time 1.88 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:40 PM PDT 24
Peak memory 205028 kb
Host smart-b13d1a65-b7ad-4a66-96ab-a196b514d061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116136267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2116136267
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.4284964048
Short name T212
Test name
Test status
Simulation time 10506287631 ps
CPU time 5.61 seconds
Started Jun 11 02:06:40 PM PDT 24
Finished Jun 11 02:06:49 PM PDT 24
Peak memory 205204 kb
Host smart-c21db4ed-1c4b-4a52-a279-3830488f649c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4284964048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.4284964048
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1342159580
Short name T2
Test name
Test status
Simulation time 7066731924 ps
CPU time 10.77 seconds
Started Jun 11 02:06:38 PM PDT 24
Finished Jun 11 02:06:52 PM PDT 24
Peak memory 205188 kb
Host smart-f4d3f0b7-ab57-4a14-805a-7a346c2c82f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342159580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1342159580
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.3336722483
Short name T144
Test name
Test status
Simulation time 19522088471 ps
CPU time 15.31 seconds
Started Jun 11 02:06:38 PM PDT 24
Finished Jun 11 02:06:57 PM PDT 24
Peak memory 205048 kb
Host smart-07526f1e-da20-45e0-9d92-268ad442b202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336722483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3336722483
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2109602349
Short name T175
Test name
Test status
Simulation time 41253194 ps
CPU time 0.76 seconds
Started Jun 11 02:06:43 PM PDT 24
Finished Jun 11 02:06:46 PM PDT 24
Peak memory 204692 kb
Host smart-97a37211-663a-47cb-af25-a18a89a7f215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109602349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2109602349
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3808234090
Short name T256
Test name
Test status
Simulation time 4502925971 ps
CPU time 5.36 seconds
Started Jun 11 02:06:43 PM PDT 24
Finished Jun 11 02:06:51 PM PDT 24
Peak memory 204968 kb
Host smart-f690c40a-97f9-4c1b-81e6-7b3dfe5aa199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808234090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3808234090
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3388571464
Short name T211
Test name
Test status
Simulation time 11945592929 ps
CPU time 17.11 seconds
Started Jun 11 02:06:39 PM PDT 24
Finished Jun 11 02:06:59 PM PDT 24
Peak memory 205180 kb
Host smart-d58bd92c-f4f5-4373-bec9-8e73a7160987
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388571464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3388571464
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.35311651
Short name T241
Test name
Test status
Simulation time 3083414843 ps
CPU time 5.02 seconds
Started Jun 11 02:06:38 PM PDT 24
Finished Jun 11 02:06:46 PM PDT 24
Peak memory 205204 kb
Host smart-6e3d1ffc-700b-4c39-ac8c-d1ce77779e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35311651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.35311651
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.127803232
Short name T12
Test name
Test status
Simulation time 19633008725 ps
CPU time 54.58 seconds
Started Jun 11 02:06:39 PM PDT 24
Finished Jun 11 02:07:37 PM PDT 24
Peak memory 213208 kb
Host smart-1178b67e-81ae-497e-9836-b362ef50650e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127803232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.127803232
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3205262420
Short name T79
Test name
Test status
Simulation time 162602977 ps
CPU time 1.09 seconds
Started Jun 11 02:06:43 PM PDT 24
Finished Jun 11 02:06:46 PM PDT 24
Peak memory 204516 kb
Host smart-9ddd47d6-63f5-4856-90d7-c8cdeef31ef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205262420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3205262420
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.3246654000
Short name T183
Test name
Test status
Simulation time 3843140953 ps
CPU time 3.56 seconds
Started Jun 11 02:06:39 PM PDT 24
Finished Jun 11 02:06:46 PM PDT 24
Peak memory 214256 kb
Host smart-f47ac588-8b9c-430d-b8b1-a2d9e02318fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246654000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3246654000
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2604789104
Short name T236
Test name
Test status
Simulation time 1020367711 ps
CPU time 1.84 seconds
Started Jun 11 02:06:38 PM PDT 24
Finished Jun 11 02:06:43 PM PDT 24
Peak memory 204960 kb
Host smart-c7f6b46e-f4cf-4469-8a29-67973474e5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604789104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2604789104
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1308682509
Short name T231
Test name
Test status
Simulation time 10020142175 ps
CPU time 11.6 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:50 PM PDT 24
Peak memory 205188 kb
Host smart-996615c5-40f8-4d71-a96c-3cf6f3fc8241
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1308682509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1308682509
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1645265316
Short name T206
Test name
Test status
Simulation time 3201148714 ps
CPU time 7.77 seconds
Started Jun 11 02:06:37 PM PDT 24
Finished Jun 11 02:06:48 PM PDT 24
Peak memory 205180 kb
Host smart-efd2cb7b-e2d9-420a-b87e-31d9e37fe825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645265316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1645265316
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2093766996
Short name T229
Test name
Test status
Simulation time 51327780 ps
CPU time 0.78 seconds
Started Jun 11 02:06:37 PM PDT 24
Finished Jun 11 02:06:41 PM PDT 24
Peak memory 204712 kb
Host smart-072aba35-8dc4-4d8f-885d-6efb3b00ba0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093766996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2093766996
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2805660629
Short name T190
Test name
Test status
Simulation time 118541493496 ps
CPU time 128.29 seconds
Started Jun 11 02:06:39 PM PDT 24
Finished Jun 11 02:08:50 PM PDT 24
Peak memory 218212 kb
Host smart-dcaf9680-52ad-49f0-85d5-7e1ef9dc929c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805660629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2805660629
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1022769574
Short name T69
Test name
Test status
Simulation time 1094071560 ps
CPU time 3.7 seconds
Started Jun 11 02:06:40 PM PDT 24
Finished Jun 11 02:06:47 PM PDT 24
Peak memory 204924 kb
Host smart-b9e5222d-8a5e-493c-89a0-edd4b2593929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022769574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1022769574
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1982378361
Short name T180
Test name
Test status
Simulation time 2684789119 ps
CPU time 8.98 seconds
Started Jun 11 02:06:39 PM PDT 24
Finished Jun 11 02:06:51 PM PDT 24
Peak memory 205160 kb
Host smart-7fb183e7-d2a2-40fa-9c7f-bf35e301fb56
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982378361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1982378361
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2766405574
Short name T232
Test name
Test status
Simulation time 1075776651 ps
CPU time 3.84 seconds
Started Jun 11 02:06:38 PM PDT 24
Finished Jun 11 02:06:45 PM PDT 24
Peak memory 205260 kb
Host smart-3718c718-7d18-49b4-bb28-79dfc5db0485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766405574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2766405574
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1000116373
Short name T174
Test name
Test status
Simulation time 92778992 ps
CPU time 0.89 seconds
Started Jun 11 02:06:40 PM PDT 24
Finished Jun 11 02:06:44 PM PDT 24
Peak memory 204756 kb
Host smart-503b19b5-6d8a-4ab7-888e-d5433cc89501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000116373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1000116373
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.4036770203
Short name T182
Test name
Test status
Simulation time 5484131742 ps
CPU time 8.25 seconds
Started Jun 11 02:06:43 PM PDT 24
Finished Jun 11 02:06:54 PM PDT 24
Peak memory 205228 kb
Host smart-4c31999a-1f17-4d5d-a6bc-9853c7f609e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036770203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.4036770203
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2752478726
Short name T219
Test name
Test status
Simulation time 4840311439 ps
CPU time 7.62 seconds
Started Jun 11 02:06:40 PM PDT 24
Finished Jun 11 02:06:51 PM PDT 24
Peak memory 213312 kb
Host smart-0aa3f700-5c99-4110-9b98-57cc9b6de19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752478726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2752478726
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.638275929
Short name T201
Test name
Test status
Simulation time 3762043192 ps
CPU time 11.42 seconds
Started Jun 11 02:06:39 PM PDT 24
Finished Jun 11 02:06:53 PM PDT 24
Peak memory 205108 kb
Host smart-b2b91ad6-7e87-4599-8bca-f748522028b3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=638275929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.638275929
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1929373512
Short name T254
Test name
Test status
Simulation time 5190769844 ps
CPU time 5.66 seconds
Started Jun 11 02:06:38 PM PDT 24
Finished Jun 11 02:06:47 PM PDT 24
Peak memory 205172 kb
Host smart-0a018f76-7287-49b0-acab-ce66f8874323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929373512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1929373512
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.81262265
Short name T28
Test name
Test status
Simulation time 6615916079 ps
CPU time 17.92 seconds
Started Jun 11 02:06:43 PM PDT 24
Finished Jun 11 02:07:04 PM PDT 24
Peak memory 204976 kb
Host smart-d4b5c131-c676-4592-86ce-9907de6813e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81262265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.81262265
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1240436334
Short name T165
Test name
Test status
Simulation time 41727715 ps
CPU time 0.78 seconds
Started Jun 11 02:06:42 PM PDT 24
Finished Jun 11 02:06:45 PM PDT 24
Peak memory 204752 kb
Host smart-5a6983b7-ec84-43c9-9ce3-e87069b53b6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240436334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1240436334
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1792933549
Short name T70
Test name
Test status
Simulation time 3431925427 ps
CPU time 4.02 seconds
Started Jun 11 02:06:44 PM PDT 24
Finished Jun 11 02:06:50 PM PDT 24
Peak memory 205264 kb
Host smart-bf3cc403-f42c-4fa3-8a42-a943353a9e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792933549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1792933549
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1588087925
Short name T214
Test name
Test status
Simulation time 5163257707 ps
CPU time 2.34 seconds
Started Jun 11 02:06:48 PM PDT 24
Finished Jun 11 02:06:51 PM PDT 24
Peak memory 205076 kb
Host smart-92b8b6da-964f-4735-9648-053ed4bae922
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588087925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1588087925
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2663997268
Short name T205
Test name
Test status
Simulation time 4434847735 ps
CPU time 11.89 seconds
Started Jun 11 02:06:52 PM PDT 24
Finished Jun 11 02:07:05 PM PDT 24
Peak memory 205376 kb
Host smart-c420d7fe-4d4f-4687-a6ff-565f10848f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663997268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2663997268
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.907534955
Short name T227
Test name
Test status
Simulation time 40374076 ps
CPU time 0.79 seconds
Started Jun 11 02:06:44 PM PDT 24
Finished Jun 11 02:06:47 PM PDT 24
Peak memory 204696 kb
Host smart-4668005d-f635-4f4b-9308-c052c4415d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907534955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.907534955
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3436734882
Short name T235
Test name
Test status
Simulation time 2209518837 ps
CPU time 7.22 seconds
Started Jun 11 02:06:45 PM PDT 24
Finished Jun 11 02:06:54 PM PDT 24
Peak memory 205364 kb
Host smart-8abb57d0-1309-473d-a165-c6aad47a66ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436734882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3436734882
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1716844936
Short name T242
Test name
Test status
Simulation time 12979040836 ps
CPU time 36.62 seconds
Started Jun 11 02:06:50 PM PDT 24
Finished Jun 11 02:07:28 PM PDT 24
Peak memory 213308 kb
Host smart-a58271b6-527e-48dd-a17d-24831ec18fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716844936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1716844936
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3543420490
Short name T68
Test name
Test status
Simulation time 2744177323 ps
CPU time 3.11 seconds
Started Jun 11 02:06:44 PM PDT 24
Finished Jun 11 02:06:49 PM PDT 24
Peak memory 205140 kb
Host smart-2122f2c3-a51a-4179-8868-ab6187869725
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543420490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3543420490
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1513050680
Short name T213
Test name
Test status
Simulation time 4417320366 ps
CPU time 11.91 seconds
Started Jun 11 02:06:43 PM PDT 24
Finished Jun 11 02:06:57 PM PDT 24
Peak memory 205152 kb
Host smart-67f416ee-dbfc-49f0-b1ca-e607e83d6404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513050680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1513050680
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2099914786
Short name T71
Test name
Test status
Simulation time 71836219 ps
CPU time 0.71 seconds
Started Jun 11 02:06:43 PM PDT 24
Finished Jun 11 02:06:46 PM PDT 24
Peak memory 204776 kb
Host smart-4bc1a09a-3187-4f8b-afa4-8865114e03c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099914786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2099914786
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.4262781315
Short name T189
Test name
Test status
Simulation time 18037329001 ps
CPU time 18.03 seconds
Started Jun 11 02:06:48 PM PDT 24
Finished Jun 11 02:07:07 PM PDT 24
Peak memory 216764 kb
Host smart-33e6ffa0-09dd-4129-b27c-dc6b08c59b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262781315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.4262781315
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3422014081
Short name T248
Test name
Test status
Simulation time 5887940723 ps
CPU time 9.81 seconds
Started Jun 11 02:06:50 PM PDT 24
Finished Jun 11 02:07:01 PM PDT 24
Peak memory 205340 kb
Host smart-6cd13209-5939-4538-897c-267639375307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422014081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3422014081
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1763909559
Short name T67
Test name
Test status
Simulation time 2313505243 ps
CPU time 6.91 seconds
Started Jun 11 02:06:42 PM PDT 24
Finished Jun 11 02:06:51 PM PDT 24
Peak memory 205160 kb
Host smart-ca164c89-a3cf-493f-add6-5f30bc3a9417
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1763909559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1763909559
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.221905924
Short name T258
Test name
Test status
Simulation time 13381392606 ps
CPU time 10.6 seconds
Started Jun 11 02:06:44 PM PDT 24
Finished Jun 11 02:06:56 PM PDT 24
Peak memory 205192 kb
Host smart-cf32b299-07c4-4fd8-8fd3-516480705020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221905924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.221905924
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1392238893
Short name T176
Test name
Test status
Simulation time 134180496 ps
CPU time 0.85 seconds
Started Jun 11 02:06:46 PM PDT 24
Finished Jun 11 02:06:48 PM PDT 24
Peak memory 204684 kb
Host smart-eeb06844-b9b5-4f68-91cf-28f1f95c06ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392238893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1392238893
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2157989653
Short name T239
Test name
Test status
Simulation time 2378878404 ps
CPU time 7.99 seconds
Started Jun 11 02:06:41 PM PDT 24
Finished Jun 11 02:06:52 PM PDT 24
Peak memory 205116 kb
Host smart-5830032b-7591-4272-acb2-190d5f0b12f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157989653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2157989653
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.329312455
Short name T220
Test name
Test status
Simulation time 2861210080 ps
CPU time 8.26 seconds
Started Jun 11 02:06:52 PM PDT 24
Finished Jun 11 02:07:01 PM PDT 24
Peak memory 205332 kb
Host smart-9189794c-7143-4579-a45f-7e4e0af69228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329312455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.329312455
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.4063924386
Short name T35
Test name
Test status
Simulation time 6883801794 ps
CPU time 7.73 seconds
Started Jun 11 02:06:48 PM PDT 24
Finished Jun 11 02:06:56 PM PDT 24
Peak memory 205036 kb
Host smart-37eded68-9a2a-427d-befd-4ed4ccb579d8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063924386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.4063924386
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.196155544
Short name T208
Test name
Test status
Simulation time 8682174227 ps
CPU time 7.29 seconds
Started Jun 11 02:06:48 PM PDT 24
Finished Jun 11 02:06:56 PM PDT 24
Peak memory 205084 kb
Host smart-e980a866-9fbc-4fc7-afa3-560a657f7f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196155544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.196155544
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3343528629
Short name T129
Test name
Test status
Simulation time 74484078 ps
CPU time 0.87 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:38 PM PDT 24
Peak memory 204680 kb
Host smart-194472ba-b691-4628-8bb1-dc0a3aea2e7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343528629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3343528629
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3052568602
Short name T187
Test name
Test status
Simulation time 3034151511 ps
CPU time 4.92 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:42 PM PDT 24
Peak memory 205188 kb
Host smart-108ef672-572c-4f48-8dc9-80bbba5e00cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052568602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3052568602
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3432955736
Short name T207
Test name
Test status
Simulation time 7413038014 ps
CPU time 16.66 seconds
Started Jun 11 02:06:36 PM PDT 24
Finished Jun 11 02:06:55 PM PDT 24
Peak memory 215028 kb
Host smart-71a23622-f770-4f74-9d0e-ddf2db95f9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432955736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3432955736
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2217639564
Short name T245
Test name
Test status
Simulation time 1990539784 ps
CPU time 2.34 seconds
Started Jun 11 02:06:32 PM PDT 24
Finished Jun 11 02:06:36 PM PDT 24
Peak memory 205028 kb
Host smart-7400cc19-8dae-4bad-96fd-d7ad61b4dc8a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2217639564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2217639564
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2191700853
Short name T54
Test name
Test status
Simulation time 534428437 ps
CPU time 2.24 seconds
Started Jun 11 02:06:36 PM PDT 24
Finished Jun 11 02:06:41 PM PDT 24
Peak memory 204548 kb
Host smart-2c6456ae-4cf7-44e5-ac76-704cd02f1299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191700853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2191700853
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1241678935
Short name T179
Test name
Test status
Simulation time 1630466923 ps
CPU time 3.18 seconds
Started Jun 11 02:06:32 PM PDT 24
Finished Jun 11 02:06:38 PM PDT 24
Peak memory 205004 kb
Host smart-9556063f-63ed-4db8-846d-a5bcaf1552ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241678935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1241678935
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1381596189
Short name T50
Test name
Test status
Simulation time 500217446 ps
CPU time 2.32 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:40 PM PDT 24
Peak memory 236324 kb
Host smart-53da86ae-3028-4b65-8e1b-de21f2430655
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381596189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1381596189
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3215116530
Short name T80
Test name
Test status
Simulation time 73651957 ps
CPU time 0.71 seconds
Started Jun 11 02:06:51 PM PDT 24
Finished Jun 11 02:06:53 PM PDT 24
Peak memory 204912 kb
Host smart-cfaf56cc-aad2-4fba-a91f-1a255f07ff0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215116530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3215116530
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.4272744410
Short name T148
Test name
Test status
Simulation time 245116445 ps
CPU time 0.73 seconds
Started Jun 11 02:06:53 PM PDT 24
Finished Jun 11 02:06:55 PM PDT 24
Peak memory 204756 kb
Host smart-275de6ce-89a1-4123-abc8-3d04808e158b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272744410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.4272744410
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.642695934
Short name T55
Test name
Test status
Simulation time 30635798 ps
CPU time 0.75 seconds
Started Jun 11 02:06:50 PM PDT 24
Finished Jun 11 02:06:52 PM PDT 24
Peak memory 204744 kb
Host smart-c2c5abfe-a933-4016-92f4-2887c6348797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642695934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.642695934
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3233576578
Short name T169
Test name
Test status
Simulation time 33735434 ps
CPU time 0.76 seconds
Started Jun 11 02:06:50 PM PDT 24
Finished Jun 11 02:06:52 PM PDT 24
Peak memory 204740 kb
Host smart-af133740-1d6c-4b7b-aac0-c7930cd7a398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233576578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3233576578
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.4207442261
Short name T158
Test name
Test status
Simulation time 41364492 ps
CPU time 0.8 seconds
Started Jun 11 02:06:47 PM PDT 24
Finished Jun 11 02:06:49 PM PDT 24
Peak memory 204688 kb
Host smart-c7acb715-2def-406e-a43f-7c69725df764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207442261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.4207442261
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1451312819
Short name T171
Test name
Test status
Simulation time 54953875 ps
CPU time 0.74 seconds
Started Jun 11 02:06:46 PM PDT 24
Finished Jun 11 02:06:48 PM PDT 24
Peak memory 204728 kb
Host smart-e0e54958-1466-4767-9f44-357f80cc0b67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451312819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1451312819
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2451019905
Short name T186
Test name
Test status
Simulation time 90174975 ps
CPU time 0.88 seconds
Started Jun 11 02:06:52 PM PDT 24
Finished Jun 11 02:06:54 PM PDT 24
Peak memory 204644 kb
Host smart-1fbb1f52-f7a2-4060-8545-439c24aa07c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451019905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2451019905
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.257500288
Short name T170
Test name
Test status
Simulation time 68312148 ps
CPU time 0.72 seconds
Started Jun 11 02:06:51 PM PDT 24
Finished Jun 11 02:06:52 PM PDT 24
Peak memory 204908 kb
Host smart-3f866df6-b4af-4eba-bfe9-3a8328b32206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257500288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.257500288
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.4035805381
Short name T8
Test name
Test status
Simulation time 16850517997 ps
CPU time 10.08 seconds
Started Jun 11 02:06:52 PM PDT 24
Finished Jun 11 02:07:04 PM PDT 24
Peak memory 204960 kb
Host smart-98e039b3-d09a-4609-b014-a5a7a6239035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035805381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.4035805381
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2992478400
Short name T253
Test name
Test status
Simulation time 98698352 ps
CPU time 0.93 seconds
Started Jun 11 02:06:43 PM PDT 24
Finished Jun 11 02:06:46 PM PDT 24
Peak memory 204752 kb
Host smart-bd0df0f5-9d45-4c35-aab3-3f5cf747e2be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992478400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2992478400
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.219430170
Short name T21
Test name
Test status
Simulation time 16954350148 ps
CPU time 25.11 seconds
Started Jun 11 02:06:52 PM PDT 24
Finished Jun 11 02:07:19 PM PDT 24
Peak memory 213180 kb
Host smart-fee4d262-f0ce-4793-86e6-ca98c99179ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219430170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.219430170
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1615122106
Short name T172
Test name
Test status
Simulation time 39220047 ps
CPU time 0.77 seconds
Started Jun 11 02:06:41 PM PDT 24
Finished Jun 11 02:06:45 PM PDT 24
Peak memory 204744 kb
Host smart-a9f9d909-11c1-4c37-8bf9-fd550272dc65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615122106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1615122106
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.613423669
Short name T202
Test name
Test status
Simulation time 1595304581 ps
CPU time 4.85 seconds
Started Jun 11 02:06:32 PM PDT 24
Finished Jun 11 02:06:39 PM PDT 24
Peak memory 205044 kb
Host smart-3ad67193-36b8-4916-9d66-9c7b84364522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613423669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.613423669
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2935374087
Short name T184
Test name
Test status
Simulation time 3801468874 ps
CPU time 6.88 seconds
Started Jun 11 02:06:33 PM PDT 24
Finished Jun 11 02:06:42 PM PDT 24
Peak memory 213364 kb
Host smart-9426c53a-5b07-4501-bc2d-68e0b627308c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935374087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2935374087
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1272648087
Short name T34
Test name
Test status
Simulation time 8780720894 ps
CPU time 14.59 seconds
Started Jun 11 02:06:36 PM PDT 24
Finished Jun 11 02:06:53 PM PDT 24
Peak memory 205144 kb
Host smart-a3f8faaf-8139-4c6c-b9e5-9d93cf64fd94
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272648087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1272648087
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.377281292
Short name T177
Test name
Test status
Simulation time 455539287 ps
CPU time 1.57 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:39 PM PDT 24
Peak memory 204576 kb
Host smart-0ba26fd7-ac8b-42a3-8a21-92c4c36f86f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377281292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.377281292
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2143314119
Short name T204
Test name
Test status
Simulation time 2251265162 ps
CPU time 4.38 seconds
Started Jun 11 02:06:31 PM PDT 24
Finished Jun 11 02:06:37 PM PDT 24
Peak memory 205184 kb
Host smart-d49f41e9-d60d-4f02-a89c-33398ad67144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143314119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2143314119
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.283945635
Short name T64
Test name
Test status
Simulation time 372491461 ps
CPU time 1.14 seconds
Started Jun 11 02:06:38 PM PDT 24
Finished Jun 11 02:06:43 PM PDT 24
Peak memory 237376 kb
Host smart-56be2d6f-2a90-498b-91f2-3f5bb1316746
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283945635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.283945635
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3363830789
Short name T150
Test name
Test status
Simulation time 82235593 ps
CPU time 0.83 seconds
Started Jun 11 02:06:55 PM PDT 24
Finished Jun 11 02:06:58 PM PDT 24
Peak memory 204744 kb
Host smart-c8cc2742-cc6a-42ce-94a4-648541f01be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363830789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3363830789
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.525944476
Short name T160
Test name
Test status
Simulation time 65099405 ps
CPU time 0.72 seconds
Started Jun 11 02:06:53 PM PDT 24
Finished Jun 11 02:06:55 PM PDT 24
Peak memory 204736 kb
Host smart-e10b1f4b-9118-442f-b45f-351f746c4dfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525944476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.525944476
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.2463663611
Short name T140
Test name
Test status
Simulation time 18456310134 ps
CPU time 12.41 seconds
Started Jun 11 02:06:56 PM PDT 24
Finished Jun 11 02:07:10 PM PDT 24
Peak memory 215376 kb
Host smart-666ccf28-b009-4956-83ad-fb6d053c6f57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463663611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2463663611
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3132825811
Short name T85
Test name
Test status
Simulation time 65242653 ps
CPU time 0.71 seconds
Started Jun 11 02:06:54 PM PDT 24
Finished Jun 11 02:06:56 PM PDT 24
Peak memory 204744 kb
Host smart-94e338e9-1777-4fa3-8248-80633111b685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132825811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3132825811
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.4212643566
Short name T152
Test name
Test status
Simulation time 67355051 ps
CPU time 0.82 seconds
Started Jun 11 02:06:55 PM PDT 24
Finished Jun 11 02:06:57 PM PDT 24
Peak memory 204764 kb
Host smart-f95799fb-17c7-4b93-9eb8-c7deb52fec2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212643566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.4212643566
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3965387126
Short name T166
Test name
Test status
Simulation time 177211072 ps
CPU time 0.71 seconds
Started Jun 11 02:06:59 PM PDT 24
Finished Jun 11 02:07:01 PM PDT 24
Peak memory 204908 kb
Host smart-b1cb3555-7652-4443-8dd2-3c82aba56916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965387126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3965387126
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1950672112
Short name T159
Test name
Test status
Simulation time 171817938 ps
CPU time 0.82 seconds
Started Jun 11 02:06:54 PM PDT 24
Finished Jun 11 02:06:56 PM PDT 24
Peak memory 204752 kb
Host smart-fa551fe5-43f3-49c6-8d5f-b8499a118072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950672112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1950672112
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.3001322750
Short name T141
Test name
Test status
Simulation time 8186518247 ps
CPU time 24.85 seconds
Started Jun 11 02:06:55 PM PDT 24
Finished Jun 11 02:07:22 PM PDT 24
Peak memory 204948 kb
Host smart-d54cdc90-c10c-4392-b8b9-070f779d6e81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001322750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3001322750
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1778324829
Short name T155
Test name
Test status
Simulation time 203374707 ps
CPU time 0.71 seconds
Started Jun 11 02:06:54 PM PDT 24
Finished Jun 11 02:06:57 PM PDT 24
Peak memory 204688 kb
Host smart-a9550663-012a-4bbc-9713-c84ddb164e2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778324829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1778324829
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.2475176946
Short name T44
Test name
Test status
Simulation time 24537389069 ps
CPU time 20.83 seconds
Started Jun 11 02:06:55 PM PDT 24
Finished Jun 11 02:07:18 PM PDT 24
Peak memory 204980 kb
Host smart-009b7e55-7d31-4c39-ae3b-a4c5d3ce94c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475176946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2475176946
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2948241916
Short name T66
Test name
Test status
Simulation time 53236416 ps
CPU time 0.87 seconds
Started Jun 11 02:07:00 PM PDT 24
Finished Jun 11 02:07:02 PM PDT 24
Peak memory 204752 kb
Host smart-f7606eec-e5ee-49af-a6e6-d87a18a008f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948241916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2948241916
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.72347920
Short name T167
Test name
Test status
Simulation time 74982832 ps
CPU time 0.72 seconds
Started Jun 11 02:06:55 PM PDT 24
Finished Jun 11 02:06:58 PM PDT 24
Peak memory 204736 kb
Host smart-030cc6e2-7691-4299-a9f5-367480e92e99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72347920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.72347920
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1724379980
Short name T162
Test name
Test status
Simulation time 90283985 ps
CPU time 0.9 seconds
Started Jun 11 02:06:54 PM PDT 24
Finished Jun 11 02:06:57 PM PDT 24
Peak memory 204664 kb
Host smart-ffaaad5c-ac03-4306-aba7-e934396f291e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724379980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1724379980
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.857830864
Short name T224
Test name
Test status
Simulation time 61790102 ps
CPU time 0.7 seconds
Started Jun 11 02:06:36 PM PDT 24
Finished Jun 11 02:06:40 PM PDT 24
Peak memory 204704 kb
Host smart-32209aef-c568-4dba-8266-862c905daa5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857830864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.857830864
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1323190281
Short name T255
Test name
Test status
Simulation time 11381209071 ps
CPU time 21.8 seconds
Started Jun 11 02:06:33 PM PDT 24
Finished Jun 11 02:06:56 PM PDT 24
Peak memory 213324 kb
Host smart-e427595d-37c2-40fb-b91e-fb8775f01674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323190281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1323190281
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1653857272
Short name T198
Test name
Test status
Simulation time 6222529545 ps
CPU time 18.02 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:56 PM PDT 24
Peak memory 205196 kb
Host smart-437e6129-d1c3-4136-a326-132b85eb0e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653857272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1653857272
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.324373785
Short name T200
Test name
Test status
Simulation time 1762131447 ps
CPU time 5.88 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:43 PM PDT 24
Peak memory 205016 kb
Host smart-45aa9d55-4c96-4647-a944-9ec0d759dd60
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=324373785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl
_access.324373785
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.572345389
Short name T63
Test name
Test status
Simulation time 50098019 ps
CPU time 0.76 seconds
Started Jun 11 02:06:39 PM PDT 24
Finished Jun 11 02:06:43 PM PDT 24
Peak memory 204472 kb
Host smart-6894673b-f4f4-4f2d-a7c3-fde2d7de5955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572345389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.572345389
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2989917285
Short name T233
Test name
Test status
Simulation time 4295022763 ps
CPU time 3.78 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:42 PM PDT 24
Peak memory 205160 kb
Host smart-be63fd6b-11e9-4c4d-8f50-322ba1ccfadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989917285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2989917285
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1794558309
Short name T65
Test name
Test status
Simulation time 2226166619 ps
CPU time 2.38 seconds
Started Jun 11 02:06:34 PM PDT 24
Finished Jun 11 02:06:39 PM PDT 24
Peak memory 237736 kb
Host smart-2f0f3f79-9909-4a05-8cd3-936a71771be4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794558309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1794558309
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.451368394
Short name T142
Test name
Test status
Simulation time 17253273080 ps
CPU time 13.58 seconds
Started Jun 11 02:06:38 PM PDT 24
Finished Jun 11 02:06:55 PM PDT 24
Peak memory 205048 kb
Host smart-97df0bb0-57dc-40cf-af60-1acaecc0782e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451368394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.451368394
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1271665549
Short name T61
Test name
Test status
Simulation time 69449636 ps
CPU time 0.79 seconds
Started Jun 11 02:06:53 PM PDT 24
Finished Jun 11 02:06:56 PM PDT 24
Peak memory 204776 kb
Host smart-31087e67-10f4-4296-8a3f-f474ac1099a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271665549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1271665549
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3354080221
Short name T32
Test name
Test status
Simulation time 88423781 ps
CPU time 0.87 seconds
Started Jun 11 02:06:57 PM PDT 24
Finished Jun 11 02:07:00 PM PDT 24
Peak memory 204748 kb
Host smart-3dd2f6cb-c461-4176-a40b-3276826580df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354080221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3354080221
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1755561635
Short name T81
Test name
Test status
Simulation time 32095422 ps
CPU time 0.74 seconds
Started Jun 11 02:06:57 PM PDT 24
Finished Jun 11 02:07:00 PM PDT 24
Peak memory 204892 kb
Host smart-13cb4a15-8c1d-4086-93b9-d99f21e95e3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755561635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1755561635
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2495903202
Short name T124
Test name
Test status
Simulation time 45586015 ps
CPU time 0.82 seconds
Started Jun 11 02:06:57 PM PDT 24
Finished Jun 11 02:07:00 PM PDT 24
Peak memory 204740 kb
Host smart-a385a553-5a08-4386-b7f4-a37fbec09705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495903202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2495903202
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2719233094
Short name T164
Test name
Test status
Simulation time 73105926 ps
CPU time 0.76 seconds
Started Jun 11 02:06:56 PM PDT 24
Finished Jun 11 02:06:58 PM PDT 24
Peak memory 204660 kb
Host smart-023beb12-3675-4f4a-9329-04465f3c76d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719233094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2719233094
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2965027198
Short name T82
Test name
Test status
Simulation time 72928565 ps
CPU time 0.72 seconds
Started Jun 11 02:06:55 PM PDT 24
Finished Jun 11 02:06:58 PM PDT 24
Peak memory 204740 kb
Host smart-af92764e-d472-466a-8f3c-d77b1a99d7e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965027198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2965027198
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1246863661
Short name T146
Test name
Test status
Simulation time 3738943199 ps
CPU time 2.29 seconds
Started Jun 11 02:06:58 PM PDT 24
Finished Jun 11 02:07:02 PM PDT 24
Peak memory 204776 kb
Host smart-f3142bc1-7c1e-4776-9151-f499a059898e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246863661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1246863661
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3361511942
Short name T161
Test name
Test status
Simulation time 75742000 ps
CPU time 0.8 seconds
Started Jun 11 02:06:55 PM PDT 24
Finished Jun 11 02:06:58 PM PDT 24
Peak memory 204732 kb
Host smart-4851a072-9f9f-49d7-aa4a-3bbb9366fc98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361511942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3361511942
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2514608399
Short name T33
Test name
Test status
Simulation time 76063547 ps
CPU time 0.78 seconds
Started Jun 11 02:06:57 PM PDT 24
Finished Jun 11 02:06:59 PM PDT 24
Peak memory 204748 kb
Host smart-d512a6f7-f444-4939-ae9c-058a411470fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514608399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2514608399
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.622091583
Short name T149
Test name
Test status
Simulation time 35311680 ps
CPU time 0.74 seconds
Started Jun 11 02:07:00 PM PDT 24
Finished Jun 11 02:07:02 PM PDT 24
Peak memory 204740 kb
Host smart-27dad3ec-45b7-455c-872a-115b62671a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622091583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.622091583
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2796254721
Short name T173
Test name
Test status
Simulation time 49435115 ps
CPU time 0.73 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:39 PM PDT 24
Peak memory 204684 kb
Host smart-02e7bc54-56c7-481a-8791-a1c7f391c34a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796254721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2796254721
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.444351361
Short name T24
Test name
Test status
Simulation time 47624015464 ps
CPU time 64.67 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:07:43 PM PDT 24
Peak memory 213316 kb
Host smart-4333c6b9-f0dd-409a-a61f-cedd97f1016d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444351361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.444351361
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.4037085416
Short name T15
Test name
Test status
Simulation time 21414289505 ps
CPU time 17.77 seconds
Started Jun 11 02:06:31 PM PDT 24
Finished Jun 11 02:06:50 PM PDT 24
Peak memory 213328 kb
Host smart-9adc1501-f18c-40c1-a1b2-4fd291b8c82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037085416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.4037085416
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.4078125609
Short name T217
Test name
Test status
Simulation time 7814382346 ps
CPU time 5.15 seconds
Started Jun 11 02:06:36 PM PDT 24
Finished Jun 11 02:06:44 PM PDT 24
Peak memory 205184 kb
Host smart-4e666c59-0ed0-4438-8cf0-6538f541dc0a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4078125609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.4078125609
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1952246047
Short name T197
Test name
Test status
Simulation time 3180187824 ps
CPU time 3.86 seconds
Started Jun 11 02:06:33 PM PDT 24
Finished Jun 11 02:06:39 PM PDT 24
Peak memory 205116 kb
Host smart-847e3ec1-dc79-42e5-8ace-534fd1ee637a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952246047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1952246047
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.4043222226
Short name T168
Test name
Test status
Simulation time 40155597 ps
CPU time 0.73 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:38 PM PDT 24
Peak memory 204728 kb
Host smart-b00d2b92-d48b-4947-92b8-942f53bdfaaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043222226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.4043222226
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1975142113
Short name T25
Test name
Test status
Simulation time 24457830792 ps
CPU time 37.65 seconds
Started Jun 11 02:06:38 PM PDT 24
Finished Jun 11 02:07:20 PM PDT 24
Peak memory 216856 kb
Host smart-f337c98c-cb45-4b93-a006-6d7e76497612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975142113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1975142113
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.4024666762
Short name T247
Test name
Test status
Simulation time 2812793163 ps
CPU time 8.58 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:47 PM PDT 24
Peak memory 213348 kb
Host smart-97cdbf16-48e3-48fc-9ccc-2a3e5cd4f3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024666762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.4024666762
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.136586012
Short name T210
Test name
Test status
Simulation time 1919640220 ps
CPU time 3.1 seconds
Started Jun 11 02:06:38 PM PDT 24
Finished Jun 11 02:06:45 PM PDT 24
Peak memory 205008 kb
Host smart-c337455c-8f5e-4185-9942-8260ddeda973
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=136586012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.136586012
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3470554629
Short name T98
Test name
Test status
Simulation time 885470779 ps
CPU time 2.15 seconds
Started Jun 11 02:06:34 PM PDT 24
Finished Jun 11 02:06:39 PM PDT 24
Peak memory 205064 kb
Host smart-947dc019-589c-437c-8877-06496ffaae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470554629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3470554629
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2721305162
Short name T218
Test name
Test status
Simulation time 178945222 ps
CPU time 0.8 seconds
Started Jun 11 02:06:40 PM PDT 24
Finished Jun 11 02:06:44 PM PDT 24
Peak memory 204752 kb
Host smart-3dd3a34b-0c48-47eb-a134-ff3f522ed5a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721305162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2721305162
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.2502467933
Short name T221
Test name
Test status
Simulation time 17056641119 ps
CPU time 16.7 seconds
Started Jun 11 02:06:36 PM PDT 24
Finished Jun 11 02:06:56 PM PDT 24
Peak memory 213336 kb
Host smart-7b82b7a8-34aa-43bb-ad3a-28f77064b013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502467933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2502467933
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3487410023
Short name T244
Test name
Test status
Simulation time 5921679670 ps
CPU time 3.09 seconds
Started Jun 11 02:06:34 PM PDT 24
Finished Jun 11 02:06:40 PM PDT 24
Peak memory 205096 kb
Host smart-9baa506e-7f4e-46c0-ba56-d965dbf8dd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487410023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3487410023
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2597997286
Short name T215
Test name
Test status
Simulation time 4510141341 ps
CPU time 13.44 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:52 PM PDT 24
Peak memory 205224 kb
Host smart-f35f9e54-7219-44ce-bebd-e274b9e0ddfc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597997286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2597997286
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1209487280
Short name T185
Test name
Test status
Simulation time 1073213965 ps
CPU time 3.99 seconds
Started Jun 11 02:06:33 PM PDT 24
Finished Jun 11 02:06:39 PM PDT 24
Peak memory 205016 kb
Host smart-fa2035ed-3781-44ef-8908-a0d9cd3600ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209487280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1209487280
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2534489413
Short name T193
Test name
Test status
Simulation time 75277482 ps
CPU time 0.76 seconds
Started Jun 11 02:06:34 PM PDT 24
Finished Jun 11 02:06:36 PM PDT 24
Peak memory 204740 kb
Host smart-2c870848-1280-43ff-b688-ff82594fd351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534489413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2534489413
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.274627376
Short name T203
Test name
Test status
Simulation time 27630775872 ps
CPU time 16.89 seconds
Started Jun 11 02:06:36 PM PDT 24
Finished Jun 11 02:06:56 PM PDT 24
Peak memory 213336 kb
Host smart-ec4d3ae8-75a5-4868-bcaf-2fe671af44e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274627376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.274627376
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.439455644
Short name T226
Test name
Test status
Simulation time 4965807061 ps
CPU time 7.88 seconds
Started Jun 11 02:06:37 PM PDT 24
Finished Jun 11 02:06:48 PM PDT 24
Peak memory 205128 kb
Host smart-31982a7c-ad99-459e-9875-84582d5968e5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439455644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.439455644
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.2037726104
Short name T223
Test name
Test status
Simulation time 5055778144 ps
CPU time 14.17 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:53 PM PDT 24
Peak memory 205124 kb
Host smart-eb5595cb-4bf5-4685-8c50-6aa61297bae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037726104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2037726104
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.4272621707
Short name T60
Test name
Test status
Simulation time 28240288 ps
CPU time 0.74 seconds
Started Jun 11 02:06:44 PM PDT 24
Finished Jun 11 02:06:46 PM PDT 24
Peak memory 204748 kb
Host smart-38bb7b63-abfe-4919-b212-1fefef2e0f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272621707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.4272621707
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.2661887710
Short name T191
Test name
Test status
Simulation time 21183905562 ps
CPU time 67.53 seconds
Started Jun 11 02:06:38 PM PDT 24
Finished Jun 11 02:07:49 PM PDT 24
Peak memory 213560 kb
Host smart-7672666a-c079-4ac1-a177-e3b0e5fb397b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661887710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2661887710
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.551767242
Short name T251
Test name
Test status
Simulation time 1009885053 ps
CPU time 1.53 seconds
Started Jun 11 02:06:41 PM PDT 24
Finished Jun 11 02:06:45 PM PDT 24
Peak memory 205008 kb
Host smart-bcf6661e-28db-4a05-8a26-81ea423afd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551767242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.551767242
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.4127514479
Short name T246
Test name
Test status
Simulation time 2112719083 ps
CPU time 2.88 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:41 PM PDT 24
Peak memory 204980 kb
Host smart-95e36abe-7cb4-4ce8-ba56-9f0cb99d3b18
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4127514479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.4127514479
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1224499350
Short name T216
Test name
Test status
Simulation time 17672166468 ps
CPU time 10.95 seconds
Started Jun 11 02:06:35 PM PDT 24
Finished Jun 11 02:06:49 PM PDT 24
Peak memory 205100 kb
Host smart-7a22624f-e1ba-4c2d-8e00-0adc20fcd7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224499350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1224499350
Directory /workspace/9.rv_dm_sba_tl_access/latest
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