Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
78.72 94.56 78.90 86.17 71.79 84.50 98.31 36.80


Total test records in report: 409
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T287 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2145512632 Jun 13 02:15:32 PM PDT 24 Jun 13 02:15:40 PM PDT 24 2814048584 ps
T288 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.233362890 Jun 13 02:15:49 PM PDT 24 Jun 13 02:16:03 PM PDT 24 11544146512 ps
T125 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3643514711 Jun 13 02:16:01 PM PDT 24 Jun 13 02:16:19 PM PDT 24 4178115519 ps
T289 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.677845271 Jun 13 02:15:48 PM PDT 24 Jun 13 02:15:50 PM PDT 24 675734418 ps
T290 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3679224585 Jun 13 02:15:39 PM PDT 24 Jun 13 02:15:44 PM PDT 24 858925843 ps
T291 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1949914667 Jun 13 02:15:33 PM PDT 24 Jun 13 02:16:17 PM PDT 24 16492396818 ps
T95 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1640901362 Jun 13 02:16:07 PM PDT 24 Jun 13 02:16:10 PM PDT 24 103354129 ps
T171 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2806577785 Jun 13 02:16:20 PM PDT 24 Jun 13 02:16:28 PM PDT 24 112167316 ps
T118 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.908520711 Jun 13 02:16:11 PM PDT 24 Jun 13 02:16:15 PM PDT 24 204439203 ps
T292 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3211158865 Jun 13 02:16:05 PM PDT 24 Jun 13 02:16:14 PM PDT 24 2947237354 ps
T293 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1662709304 Jun 13 02:15:34 PM PDT 24 Jun 13 02:15:36 PM PDT 24 163462105 ps
T294 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3561748955 Jun 13 02:15:23 PM PDT 24 Jun 13 02:15:43 PM PDT 24 21517341021 ps
T96 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3111554650 Jun 13 02:15:28 PM PDT 24 Jun 13 02:16:39 PM PDT 24 69973828283 ps
T112 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3380205472 Jun 13 02:15:31 PM PDT 24 Jun 13 02:15:40 PM PDT 24 558675401 ps
T133 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2750370610 Jun 13 02:15:22 PM PDT 24 Jun 13 02:17:00 PM PDT 24 66539338663 ps
T295 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.924868461 Jun 13 02:15:34 PM PDT 24 Jun 13 02:15:39 PM PDT 24 1117219473 ps
T296 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.764543659 Jun 13 02:16:01 PM PDT 24 Jun 13 02:16:14 PM PDT 24 4843146623 ps
T90 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2785114006 Jun 13 02:15:25 PM PDT 24 Jun 13 02:15:34 PM PDT 24 10775826557 ps
T297 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1276546504 Jun 13 02:15:31 PM PDT 24 Jun 13 02:16:33 PM PDT 24 1536754276 ps
T119 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2257066087 Jun 13 02:15:31 PM PDT 24 Jun 13 02:15:35 PM PDT 24 369052613 ps
T298 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1228624586 Jun 13 02:16:10 PM PDT 24 Jun 13 02:16:13 PM PDT 24 220614448 ps
T299 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3334711388 Jun 13 02:16:20 PM PDT 24 Jun 13 02:16:26 PM PDT 24 1295807631 ps
T110 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2514632915 Jun 13 02:15:39 PM PDT 24 Jun 13 02:16:14 PM PDT 24 5749571732 ps
T300 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2120286116 Jun 13 02:16:01 PM PDT 24 Jun 13 02:16:07 PM PDT 24 3216305856 ps
T97 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1320778105 Jun 13 02:15:56 PM PDT 24 Jun 13 02:16:03 PM PDT 24 152827491 ps
T104 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2801082985 Jun 13 02:15:35 PM PDT 24 Jun 13 02:16:43 PM PDT 24 2270004945 ps
T105 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1912953385 Jun 13 02:15:59 PM PDT 24 Jun 13 02:16:02 PM PDT 24 123469378 ps
T106 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1676596562 Jun 13 02:16:15 PM PDT 24 Jun 13 02:16:18 PM PDT 24 191301616 ps
T301 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.61894686 Jun 13 02:16:15 PM PDT 24 Jun 13 02:16:26 PM PDT 24 7333705228 ps
T107 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.38792461 Jun 13 02:16:02 PM PDT 24 Jun 13 02:16:05 PM PDT 24 121760007 ps
T302 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2005600054 Jun 13 02:15:21 PM PDT 24 Jun 13 02:15:22 PM PDT 24 569945405 ps
T303 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2247496116 Jun 13 02:16:08 PM PDT 24 Jun 13 02:16:33 PM PDT 24 14522216388 ps
T304 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1532937977 Jun 13 02:15:22 PM PDT 24 Jun 13 02:15:24 PM PDT 24 81435722 ps
T305 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1097832832 Jun 13 02:15:32 PM PDT 24 Jun 13 02:15:36 PM PDT 24 456286286 ps
T121 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.862634319 Jun 13 02:15:45 PM PDT 24 Jun 13 02:16:46 PM PDT 24 97561269127 ps
T306 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2834081511 Jun 13 02:15:31 PM PDT 24 Jun 13 02:15:33 PM PDT 24 141900393 ps
T307 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1104489906 Jun 13 02:15:40 PM PDT 24 Jun 13 02:15:46 PM PDT 24 325047830 ps
T308 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2272085656 Jun 13 02:16:03 PM PDT 24 Jun 13 02:16:07 PM PDT 24 809931657 ps
T309 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3709323393 Jun 13 02:15:47 PM PDT 24 Jun 13 02:16:28 PM PDT 24 31911547751 ps
T310 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3196759538 Jun 13 02:15:46 PM PDT 24 Jun 13 02:15:48 PM PDT 24 170177433 ps
T108 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.480450193 Jun 13 02:16:20 PM PDT 24 Jun 13 02:16:25 PM PDT 24 116700810 ps
T109 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2453840350 Jun 13 02:15:59 PM PDT 24 Jun 13 02:16:02 PM PDT 24 287723088 ps
T98 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2521699574 Jun 13 02:15:24 PM PDT 24 Jun 13 02:16:40 PM PDT 24 15502426432 ps
T311 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2362953552 Jun 13 02:16:18 PM PDT 24 Jun 13 02:16:24 PM PDT 24 136665830 ps
T312 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2550390331 Jun 13 02:15:39 PM PDT 24 Jun 13 02:16:11 PM PDT 24 7207465650 ps
T122 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2606829734 Jun 13 02:15:45 PM PDT 24 Jun 13 02:16:20 PM PDT 24 15893814887 ps
T313 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3838607289 Jun 13 02:16:12 PM PDT 24 Jun 13 02:16:19 PM PDT 24 97357936 ps
T314 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1231176967 Jun 13 02:15:44 PM PDT 24 Jun 13 02:16:24 PM PDT 24 14363903157 ps
T315 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.14548081 Jun 13 02:15:46 PM PDT 24 Jun 13 02:15:49 PM PDT 24 216458185 ps
T316 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.703307386 Jun 13 02:16:13 PM PDT 24 Jun 13 02:16:19 PM PDT 24 1010927585 ps
T317 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2457976625 Jun 13 02:15:36 PM PDT 24 Jun 13 02:15:38 PM PDT 24 1514563890 ps
T126 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3434559289 Jun 13 02:16:14 PM PDT 24 Jun 13 02:16:40 PM PDT 24 3651228137 ps
T129 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1886665405 Jun 13 02:15:24 PM PDT 24 Jun 13 02:15:41 PM PDT 24 1314605548 ps
T318 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2813608591 Jun 13 02:15:34 PM PDT 24 Jun 13 02:15:57 PM PDT 24 17567265575 ps
T319 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3114195589 Jun 13 02:16:03 PM PDT 24 Jun 13 02:16:11 PM PDT 24 1868536837 ps
T320 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.942173383 Jun 13 02:16:18 PM PDT 24 Jun 13 02:16:22 PM PDT 24 317354457 ps
T99 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2899156266 Jun 13 02:15:33 PM PDT 24 Jun 13 02:15:36 PM PDT 24 154196885 ps
T321 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2847647806 Jun 13 02:16:03 PM PDT 24 Jun 13 02:16:19 PM PDT 24 5302090907 ps
T322 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2301484374 Jun 13 02:15:31 PM PDT 24 Jun 13 02:15:33 PM PDT 24 155600252 ps
T323 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1017093722 Jun 13 02:16:14 PM PDT 24 Jun 13 02:16:16 PM PDT 24 136815644 ps
T324 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1000802018 Jun 13 02:15:35 PM PDT 24 Jun 13 02:15:37 PM PDT 24 244057365 ps
T325 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.48370795 Jun 13 02:15:51 PM PDT 24 Jun 13 02:16:02 PM PDT 24 2596911198 ps
T130 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.435665449 Jun 13 02:16:01 PM PDT 24 Jun 13 02:16:11 PM PDT 24 1328498357 ps
T326 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.61396825 Jun 13 02:15:29 PM PDT 24 Jun 13 02:15:57 PM PDT 24 756344944 ps
T327 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2481689817 Jun 13 02:15:41 PM PDT 24 Jun 13 02:15:44 PM PDT 24 153935151 ps
T131 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4034337208 Jun 13 02:15:47 PM PDT 24 Jun 13 02:15:57 PM PDT 24 1233176659 ps
T328 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.888423714 Jun 13 02:15:32 PM PDT 24 Jun 13 02:15:40 PM PDT 24 4682762568 ps
T91 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.832686656 Jun 13 02:15:31 PM PDT 24 Jun 13 02:15:57 PM PDT 24 9847739187 ps
T113 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1524148685 Jun 13 02:16:25 PM PDT 24 Jun 13 02:16:33 PM PDT 24 161553874 ps
T329 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.161078358 Jun 13 02:15:31 PM PDT 24 Jun 13 02:16:04 PM PDT 24 11960060748 ps
T330 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3179681058 Jun 13 02:15:29 PM PDT 24 Jun 13 02:15:59 PM PDT 24 1225767745 ps
T331 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2272561959 Jun 13 02:16:15 PM PDT 24 Jun 13 02:17:30 PM PDT 24 30688455884 ps
T111 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.292150503 Jun 13 02:15:40 PM PDT 24 Jun 13 02:15:43 PM PDT 24 101490897 ps
T332 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4217507751 Jun 13 02:15:52 PM PDT 24 Jun 13 02:15:55 PM PDT 24 77071611 ps
T333 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4030826785 Jun 13 02:15:36 PM PDT 24 Jun 13 02:15:38 PM PDT 24 546752800 ps
T128 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4246089390 Jun 13 02:16:18 PM PDT 24 Jun 13 02:16:45 PM PDT 24 2114289923 ps
T334 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.62851976 Jun 13 02:15:35 PM PDT 24 Jun 13 02:15:37 PM PDT 24 108667506 ps
T335 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.790777784 Jun 13 02:16:14 PM PDT 24 Jun 13 02:16:17 PM PDT 24 386711801 ps
T336 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3213513983 Jun 13 02:15:46 PM PDT 24 Jun 13 02:18:34 PM PDT 24 58836035898 ps
T337 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3536537926 Jun 13 02:15:29 PM PDT 24 Jun 13 02:15:59 PM PDT 24 5353237964 ps
T100 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.467041113 Jun 13 02:15:39 PM PDT 24 Jun 13 02:15:43 PM PDT 24 620562660 ps
T338 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3098600044 Jun 13 02:15:44 PM PDT 24 Jun 13 02:15:48 PM PDT 24 63536128 ps
T101 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2677494597 Jun 13 02:15:30 PM PDT 24 Jun 13 02:15:36 PM PDT 24 1614764529 ps
T339 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.865955146 Jun 13 02:15:46 PM PDT 24 Jun 13 02:15:50 PM PDT 24 598384435 ps
T340 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1417497554 Jun 13 02:16:11 PM PDT 24 Jun 13 02:16:19 PM PDT 24 6691881008 ps
T341 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3781327167 Jun 13 02:15:30 PM PDT 24 Jun 13 02:15:32 PM PDT 24 2114344498 ps
T342 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.87907300 Jun 13 02:16:17 PM PDT 24 Jun 13 02:16:24 PM PDT 24 189926455 ps
T343 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.356427653 Jun 13 02:15:53 PM PDT 24 Jun 13 02:15:56 PM PDT 24 223494131 ps
T114 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3085864525 Jun 13 02:15:46 PM PDT 24 Jun 13 02:15:55 PM PDT 24 776602961 ps
T344 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1357369955 Jun 13 02:16:02 PM PDT 24 Jun 13 02:16:07 PM PDT 24 219769252 ps
T345 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3980502984 Jun 13 02:15:52 PM PDT 24 Jun 13 02:15:54 PM PDT 24 121328426 ps
T346 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2972766112 Jun 13 02:15:33 PM PDT 24 Jun 13 02:15:39 PM PDT 24 491962864 ps
T347 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1508845239 Jun 13 02:15:29 PM PDT 24 Jun 13 02:16:19 PM PDT 24 62051956177 ps
T348 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.714248354 Jun 13 02:15:36 PM PDT 24 Jun 13 02:16:00 PM PDT 24 27884566653 ps
T349 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1584097304 Jun 13 02:15:42 PM PDT 24 Jun 13 02:15:44 PM PDT 24 95837271 ps
T350 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2452376723 Jun 13 02:16:12 PM PDT 24 Jun 13 02:16:18 PM PDT 24 201679145 ps
T351 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2605555896 Jun 13 02:15:52 PM PDT 24 Jun 13 02:15:55 PM PDT 24 220244781 ps
T352 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1824326992 Jun 13 02:16:21 PM PDT 24 Jun 13 02:16:27 PM PDT 24 3169230888 ps
T353 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.955000977 Jun 13 02:15:24 PM PDT 24 Jun 13 02:15:26 PM PDT 24 569065223 ps
T354 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2660358764 Jun 13 02:15:47 PM PDT 24 Jun 13 02:15:53 PM PDT 24 365346374 ps
T355 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2105323128 Jun 13 02:15:59 PM PDT 24 Jun 13 02:16:01 PM PDT 24 98923032 ps
T356 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3774747674 Jun 13 02:15:22 PM PDT 24 Jun 13 02:15:25 PM PDT 24 453593944 ps
T357 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2985313081 Jun 13 02:16:05 PM PDT 24 Jun 13 02:16:11 PM PDT 24 2336149098 ps
T358 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2803038544 Jun 13 02:15:31 PM PDT 24 Jun 13 02:15:33 PM PDT 24 34924667 ps
T123 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3865312861 Jun 13 02:15:33 PM PDT 24 Jun 13 02:15:57 PM PDT 24 6887871398 ps
T359 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3305546975 Jun 13 02:15:42 PM PDT 24 Jun 13 02:15:48 PM PDT 24 2038521979 ps
T360 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.565973606 Jun 13 02:15:42 PM PDT 24 Jun 13 02:16:13 PM PDT 24 10394517753 ps
T361 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4267363829 Jun 13 02:16:18 PM PDT 24 Jun 13 02:16:27 PM PDT 24 1507718685 ps
T362 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3381058312 Jun 13 02:16:10 PM PDT 24 Jun 13 02:16:19 PM PDT 24 411613648 ps
T363 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2000703352 Jun 13 02:15:56 PM PDT 24 Jun 13 02:16:00 PM PDT 24 138796487 ps
T364 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3245904567 Jun 13 02:15:59 PM PDT 24 Jun 13 02:16:02 PM PDT 24 341606768 ps
T365 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3301960597 Jun 13 02:16:17 PM PDT 24 Jun 13 02:16:30 PM PDT 24 2063012008 ps
T366 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3341655422 Jun 13 02:16:03 PM PDT 24 Jun 13 02:16:13 PM PDT 24 3131120403 ps
T367 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3212898595 Jun 13 02:16:00 PM PDT 24 Jun 13 02:18:00 PM PDT 24 42603532484 ps
T368 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2655793855 Jun 13 02:16:23 PM PDT 24 Jun 13 02:16:29 PM PDT 24 55464149 ps
T369 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1230919700 Jun 13 02:16:12 PM PDT 24 Jun 13 02:16:18 PM PDT 24 217048344 ps
T370 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2622096779 Jun 13 02:15:46 PM PDT 24 Jun 13 02:17:08 PM PDT 24 26977596549 ps
T371 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1967620221 Jun 13 02:16:01 PM PDT 24 Jun 13 02:16:08 PM PDT 24 1000584691 ps
T372 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4182950643 Jun 13 02:15:58 PM PDT 24 Jun 13 02:16:04 PM PDT 24 1377250827 ps
T373 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1485641847 Jun 13 02:15:47 PM PDT 24 Jun 13 02:15:52 PM PDT 24 4210963553 ps
T374 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.952832802 Jun 13 02:16:03 PM PDT 24 Jun 13 02:16:06 PM PDT 24 397347181 ps
T375 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.272935788 Jun 13 02:16:01 PM PDT 24 Jun 13 02:16:04 PM PDT 24 1776880899 ps
T376 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.857624553 Jun 13 02:16:18 PM PDT 24 Jun 13 02:16:25 PM PDT 24 262221266 ps
T377 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3995777871 Jun 13 02:16:13 PM PDT 24 Jun 13 02:16:20 PM PDT 24 10890589122 ps
T378 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3445686182 Jun 13 02:16:05 PM PDT 24 Jun 13 02:16:28 PM PDT 24 19412236996 ps
T379 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1065043568 Jun 13 02:16:01 PM PDT 24 Jun 13 02:16:06 PM PDT 24 342752353 ps
T380 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2061658782 Jun 13 02:15:30 PM PDT 24 Jun 13 02:15:35 PM PDT 24 1614454023 ps
T381 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3172355814 Jun 13 02:16:11 PM PDT 24 Jun 13 02:16:16 PM PDT 24 178024725 ps
T382 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2453460546 Jun 13 02:15:45 PM PDT 24 Jun 13 02:15:47 PM PDT 24 92242327 ps
T383 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1420569490 Jun 13 02:16:00 PM PDT 24 Jun 13 02:16:23 PM PDT 24 2334648003 ps
T102 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3383681897 Jun 13 02:15:45 PM PDT 24 Jun 13 02:15:51 PM PDT 24 355641976 ps
T384 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2436245617 Jun 13 02:15:59 PM PDT 24 Jun 13 02:16:04 PM PDT 24 122974835 ps
T385 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2724505703 Jun 13 02:16:22 PM PDT 24 Jun 13 02:16:52 PM PDT 24 9349141553 ps
T386 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2934791332 Jun 13 02:16:13 PM PDT 24 Jun 13 02:16:19 PM PDT 24 207600553 ps
T387 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1175669431 Jun 13 02:16:03 PM PDT 24 Jun 13 02:16:06 PM PDT 24 130309721 ps
T388 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1198989770 Jun 13 02:16:07 PM PDT 24 Jun 13 02:16:15 PM PDT 24 371968904 ps
T132 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2005032010 Jun 13 02:15:52 PM PDT 24 Jun 13 02:16:02 PM PDT 24 999272752 ps
T389 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.62235688 Jun 13 02:15:29 PM PDT 24 Jun 13 02:15:43 PM PDT 24 15928510204 ps
T390 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3590863289 Jun 13 02:15:42 PM PDT 24 Jun 13 02:15:45 PM PDT 24 1426754055 ps
T391 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3021524708 Jun 13 02:15:52 PM PDT 24 Jun 13 02:16:50 PM PDT 24 18563815117 ps
T392 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4260842336 Jun 13 02:16:17 PM PDT 24 Jun 13 02:16:23 PM PDT 24 62214821 ps
T393 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.163555582 Jun 13 02:16:23 PM PDT 24 Jun 13 02:16:36 PM PDT 24 14060089164 ps
T394 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2968057312 Jun 13 02:15:59 PM PDT 24 Jun 13 02:16:02 PM PDT 24 580066934 ps
T103 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3786324360 Jun 13 02:16:19 PM PDT 24 Jun 13 02:16:30 PM PDT 24 620075931 ps
T395 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.725935056 Jun 13 02:16:08 PM PDT 24 Jun 13 02:16:15 PM PDT 24 3389256026 ps
T396 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2228558293 Jun 13 02:16:12 PM PDT 24 Jun 13 02:16:16 PM PDT 24 618970422 ps
T397 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4293884884 Jun 13 02:15:44 PM PDT 24 Jun 13 02:15:47 PM PDT 24 2302351951 ps
T398 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1853208293 Jun 13 02:15:33 PM PDT 24 Jun 13 02:15:37 PM PDT 24 231276663 ps
T399 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.962096030 Jun 13 02:15:54 PM PDT 24 Jun 13 02:15:56 PM PDT 24 1618213551 ps
T400 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3669628853 Jun 13 02:15:24 PM PDT 24 Jun 13 02:15:27 PM PDT 24 455145911 ps
T401 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2287019124 Jun 13 02:16:10 PM PDT 24 Jun 13 02:16:21 PM PDT 24 3549788058 ps
T402 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1381767206 Jun 13 02:15:28 PM PDT 24 Jun 13 02:15:39 PM PDT 24 6626192399 ps
T403 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1428426051 Jun 13 02:15:31 PM PDT 24 Jun 13 02:15:32 PM PDT 24 99247092 ps
T404 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1928890383 Jun 13 02:15:41 PM PDT 24 Jun 13 02:15:44 PM PDT 24 8175132191 ps
T405 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3834805962 Jun 13 02:16:10 PM PDT 24 Jun 13 02:16:19 PM PDT 24 7246854828 ps
T406 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2386503650 Jun 13 02:16:25 PM PDT 24 Jun 13 02:16:32 PM PDT 24 181534417 ps
T407 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2666418614 Jun 13 02:16:00 PM PDT 24 Jun 13 02:16:08 PM PDT 24 768535071 ps
T408 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2883080022 Jun 13 02:15:27 PM PDT 24 Jun 13 02:15:39 PM PDT 24 13568897382 ps
T409 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3498009199 Jun 13 02:15:59 PM PDT 24 Jun 13 02:16:05 PM PDT 24 561803504 ps

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.343251316
Short name T3
Test name
Test status
Simulation time 7637641376 ps
CPU time 6.43 seconds
Started Jun 13 02:47:26 PM PDT 24
Finished Jun 13 02:47:38 PM PDT 24
Peak memory 215324 kb
Host smart-303de2ef-a2ec-4dda-9359-59293d5f16bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343251316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.343251316
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.1347212434
Short name T11
Test name
Test status
Simulation time 41844700562 ps
CPU time 101.78 seconds
Started Jun 13 02:47:27 PM PDT 24
Finished Jun 13 02:49:14 PM PDT 24
Peak memory 205420 kb
Host smart-15baf209-e02b-4837-bc9d-2e4cd05d16fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347212434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1347212434
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2753083675
Short name T52
Test name
Test status
Simulation time 35804473 ps
CPU time 0.75 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:38 PM PDT 24
Peak memory 205096 kb
Host smart-8563ab8e-5979-4498-a512-de9fd24d32d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753083675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2753083675
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.644936637
Short name T50
Test name
Test status
Simulation time 6377851300 ps
CPU time 10.91 seconds
Started Jun 13 02:16:23 PM PDT 24
Finished Jun 13 02:16:38 PM PDT 24
Peak memory 213788 kb
Host smart-2402d9ac-dff4-4379-8935-4e2fdb78f827
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644936637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.644936637
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4041266320
Short name T47
Test name
Test status
Simulation time 80145668419 ps
CPU time 53.7 seconds
Started Jun 13 02:15:40 PM PDT 24
Finished Jun 13 02:16:35 PM PDT 24
Peak memory 223632 kb
Host smart-e0e0ff49-77d5-4edb-aef0-5960f97acaef
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041266320 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.4041266320
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3562077630
Short name T29
Test name
Test status
Simulation time 3779439351 ps
CPU time 11.18 seconds
Started Jun 13 02:47:32 PM PDT 24
Finished Jun 13 02:47:55 PM PDT 24
Peak memory 205552 kb
Host smart-773c6d49-a6c3-4465-b086-202e4b458d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562077630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3562077630
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.592097000
Short name T181
Test name
Test status
Simulation time 55647167324 ps
CPU time 38.61 seconds
Started Jun 13 02:47:20 PM PDT 24
Finished Jun 13 02:48:01 PM PDT 24
Peak memory 213752 kb
Host smart-340b0022-b54a-4098-a195-2a2ad838dacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592097000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.592097000
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.643543685
Short name T19
Test name
Test status
Simulation time 37524943020 ps
CPU time 77.38 seconds
Started Jun 13 02:47:26 PM PDT 24
Finished Jun 13 02:48:48 PM PDT 24
Peak memory 205408 kb
Host smart-ee3da149-a66a-4ff0-b6b3-f1d4ab3742cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643543685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.643543685
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1531899909
Short name T1
Test name
Test status
Simulation time 28320436925 ps
CPU time 40.03 seconds
Started Jun 13 02:47:30 PM PDT 24
Finished Jun 13 02:48:20 PM PDT 24
Peak memory 205368 kb
Host smart-91d9f17a-e531-40c9-b58b-633f26829ada
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531899909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1531899909
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2303884606
Short name T81
Test name
Test status
Simulation time 504324545 ps
CPU time 7.89 seconds
Started Jun 13 02:16:13 PM PDT 24
Finished Jun 13 02:16:23 PM PDT 24
Peak memory 205488 kb
Host smart-d365ff13-b1ae-4cab-9454-73389837cf3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303884606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2303884606
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3305704226
Short name T45
Test name
Test status
Simulation time 1378934343 ps
CPU time 1.62 seconds
Started Jun 13 02:47:10 PM PDT 24
Finished Jun 13 02:47:20 PM PDT 24
Peak memory 237372 kb
Host smart-de5a6dba-0d4f-4a02-82e8-6b461f557962
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305704226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3305704226
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1885756906
Short name T33
Test name
Test status
Simulation time 54453652 ps
CPU time 0.94 seconds
Started Jun 13 02:47:03 PM PDT 24
Finished Jun 13 02:47:11 PM PDT 24
Peak memory 213356 kb
Host smart-9094e066-a3ab-48cf-8120-668df38008cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885756906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1885756906
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.473818875
Short name T49
Test name
Test status
Simulation time 904311342 ps
CPU time 9.01 seconds
Started Jun 13 02:15:44 PM PDT 24
Finished Jun 13 02:15:55 PM PDT 24
Peak memory 213636 kb
Host smart-68a6822c-aebd-4e48-9f41-e99b2994c157
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473818875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.473818875
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.4013909136
Short name T42
Test name
Test status
Simulation time 354818079 ps
CPU time 0.89 seconds
Started Jun 13 02:47:04 PM PDT 24
Finished Jun 13 02:47:12 PM PDT 24
Peak memory 205072 kb
Host smart-159e6d30-31a4-438c-814f-9dab77464254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013909136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.4013909136
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2521699574
Short name T98
Test name
Test status
Simulation time 15502426432 ps
CPU time 75.44 seconds
Started Jun 13 02:15:24 PM PDT 24
Finished Jun 13 02:16:40 PM PDT 24
Peak memory 205640 kb
Host smart-770cf571-42ff-4899-905b-f821d1f98634
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521699574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.2521699574
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1001001989
Short name T38
Test name
Test status
Simulation time 1345221765 ps
CPU time 1.97 seconds
Started Jun 13 02:47:01 PM PDT 24
Finished Jun 13 02:47:11 PM PDT 24
Peak memory 205348 kb
Host smart-8b05f201-3498-4ab1-98c7-0d44af86cd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001001989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1001001989
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3865312861
Short name T123
Test name
Test status
Simulation time 6887871398 ps
CPU time 21.51 seconds
Started Jun 13 02:15:33 PM PDT 24
Finished Jun 13 02:15:57 PM PDT 24
Peak memory 213780 kb
Host smart-f95dfda9-9d06-402e-85be-9d9b6d247830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865312861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3865312861
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.286924445
Short name T40
Test name
Test status
Simulation time 1051986838 ps
CPU time 2.3 seconds
Started Jun 13 02:46:57 PM PDT 24
Finished Jun 13 02:47:09 PM PDT 24
Peak memory 205124 kb
Host smart-5e653e90-7e14-4ac4-929a-4e344c8821f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286924445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.286924445
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.295293858
Short name T46
Test name
Test status
Simulation time 57891184846 ps
CPU time 49.6 seconds
Started Jun 13 02:16:00 PM PDT 24
Finished Jun 13 02:16:50 PM PDT 24
Peak memory 221544 kb
Host smart-4682bb87-2d96-4142-a05f-5869a3fb72bb
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295293858 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.295293858
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1421020528
Short name T2
Test name
Test status
Simulation time 87514305 ps
CPU time 0.79 seconds
Started Jun 13 02:47:24 PM PDT 24
Finished Jun 13 02:47:29 PM PDT 24
Peak memory 205304 kb
Host smart-2f2cf734-ff0d-4e14-8b76-545fe727ea27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421020528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1421020528
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.30411054
Short name T17
Test name
Test status
Simulation time 642454586 ps
CPU time 1.08 seconds
Started Jun 13 02:47:01 PM PDT 24
Finished Jun 13 02:47:09 PM PDT 24
Peak memory 205008 kb
Host smart-8481cc70-d786-4f2f-82bd-e91d33015b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30411054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.30411054
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.385107860
Short name T86
Test name
Test status
Simulation time 277660032 ps
CPU time 1.77 seconds
Started Jun 13 02:15:30 PM PDT 24
Finished Jun 13 02:15:33 PM PDT 24
Peak memory 213716 kb
Host smart-520bd88b-2d3e-404d-badf-91b0d4c26d53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385107860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.385107860
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3691321686
Short name T283
Test name
Test status
Simulation time 12949767608 ps
CPU time 33.7 seconds
Started Jun 13 02:15:23 PM PDT 24
Finished Jun 13 02:15:58 PM PDT 24
Peak memory 205500 kb
Host smart-8955a6e6-657f-45c6-9f2c-1f333b041db1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691321686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3691321686
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2785114006
Short name T90
Test name
Test status
Simulation time 10775826557 ps
CPU time 8.85 seconds
Started Jun 13 02:15:25 PM PDT 24
Finished Jun 13 02:15:34 PM PDT 24
Peak memory 205572 kb
Host smart-358569cc-0700-47c8-b604-7834d066dc3e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785114006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2785114006
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.435665449
Short name T130
Test name
Test status
Simulation time 1328498357 ps
CPU time 8.98 seconds
Started Jun 13 02:16:01 PM PDT 24
Finished Jun 13 02:16:11 PM PDT 24
Peak memory 213684 kb
Host smart-c0c008f2-bf3b-4b15-8283-afd3872aa5ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435665449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.435665449
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2665989742
Short name T53
Test name
Test status
Simulation time 7145080033 ps
CPU time 6.27 seconds
Started Jun 13 02:47:11 PM PDT 24
Finished Jun 13 02:47:22 PM PDT 24
Peak memory 213788 kb
Host smart-ed8900ce-63cc-4628-acef-a479f5de3a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665989742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2665989742
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3851305535
Short name T31
Test name
Test status
Simulation time 3772634714 ps
CPU time 1.77 seconds
Started Jun 13 02:46:58 PM PDT 24
Finished Jun 13 02:47:06 PM PDT 24
Peak memory 204988 kb
Host smart-57dfcb89-a8cf-48b5-a4ab-c51877e123b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851305535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3851305535
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3160289241
Short name T35
Test name
Test status
Simulation time 3034381387 ps
CPU time 2.7 seconds
Started Jun 13 02:47:03 PM PDT 24
Finished Jun 13 02:47:12 PM PDT 24
Peak memory 205400 kb
Host smart-2c000cd3-2136-4f4f-94a4-eac948cdac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160289241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3160289241
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.61396825
Short name T326
Test name
Test status
Simulation time 756344944 ps
CPU time 27.27 seconds
Started Jun 13 02:15:29 PM PDT 24
Finished Jun 13 02:15:57 PM PDT 24
Peak memory 213660 kb
Host smart-a11b04f1-67b6-44dd-b4fe-d46b8642d914
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61396825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.61396825
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1676183361
Short name T79
Test name
Test status
Simulation time 139270095 ps
CPU time 2.6 seconds
Started Jun 13 02:15:30 PM PDT 24
Finished Jun 13 02:15:33 PM PDT 24
Peak memory 214124 kb
Host smart-71a27df4-fc40-493e-8860-31d8f69538b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676183361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1676183361
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2145512632
Short name T287
Test name
Test status
Simulation time 2814048584 ps
CPU time 6.59 seconds
Started Jun 13 02:15:32 PM PDT 24
Finished Jun 13 02:15:40 PM PDT 24
Peak memory 220628 kb
Host smart-44bb4532-dfdc-4cf3-9c51-367607f0a335
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145512632 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2145512632
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3561748955
Short name T294
Test name
Test status
Simulation time 21517341021 ps
CPU time 18.75 seconds
Started Jun 13 02:15:23 PM PDT 24
Finished Jun 13 02:15:43 PM PDT 24
Peak memory 205500 kb
Host smart-8d5c8223-e55c-4484-b864-44dee6b75691
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561748955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3561748955
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2883080022
Short name T408
Test name
Test status
Simulation time 13568897382 ps
CPU time 11.63 seconds
Started Jun 13 02:15:27 PM PDT 24
Finished Jun 13 02:15:39 PM PDT 24
Peak memory 205504 kb
Host smart-364c900a-e546-45b8-93ca-7e16a8e7962d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883080022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.2883080022
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2901517561
Short name T272
Test name
Test status
Simulation time 1189633840 ps
CPU time 4.08 seconds
Started Jun 13 02:15:23 PM PDT 24
Finished Jun 13 02:15:27 PM PDT 24
Peak memory 205388 kb
Host smart-08bf7c59-c98c-4c67-a692-fe6c80455f91
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901517561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
901517561
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.955000977
Short name T353
Test name
Test status
Simulation time 569065223 ps
CPU time 1.38 seconds
Started Jun 13 02:15:24 PM PDT 24
Finished Jun 13 02:15:26 PM PDT 24
Peak memory 205224 kb
Host smart-df9df8cb-c6ec-4116-97c2-24c3d1aa09dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955000977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.955000977
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2005600054
Short name T302
Test name
Test status
Simulation time 569945405 ps
CPU time 0.82 seconds
Started Jun 13 02:15:21 PM PDT 24
Finished Jun 13 02:15:22 PM PDT 24
Peak memory 205228 kb
Host smart-8709eaae-42e5-486a-b632-56f4e9873f42
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005600054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2005600054
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3669628853
Short name T400
Test name
Test status
Simulation time 455145911 ps
CPU time 1.84 seconds
Started Jun 13 02:15:24 PM PDT 24
Finished Jun 13 02:15:27 PM PDT 24
Peak memory 205196 kb
Host smart-1dc948c8-67aa-4f73-a359-628faff6fba4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669628853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
669628853
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1532937977
Short name T304
Test name
Test status
Simulation time 81435722 ps
CPU time 0.74 seconds
Started Jun 13 02:15:22 PM PDT 24
Finished Jun 13 02:15:24 PM PDT 24
Peak memory 205140 kb
Host smart-9d74a60b-4326-4907-b194-ecc4cb72be67
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532937977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1532937977
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1593409890
Short name T277
Test name
Test status
Simulation time 83676662 ps
CPU time 0.68 seconds
Started Jun 13 02:15:22 PM PDT 24
Finished Jun 13 02:15:23 PM PDT 24
Peak memory 205208 kb
Host smart-64cc909c-e7c2-41cd-9324-b0501d96a742
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593409890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1593409890
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3380205472
Short name T112
Test name
Test status
Simulation time 558675401 ps
CPU time 7.66 seconds
Started Jun 13 02:15:31 PM PDT 24
Finished Jun 13 02:15:40 PM PDT 24
Peak memory 205548 kb
Host smart-23dfb124-82d6-4268-93da-3b55650d899e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380205472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3380205472
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2750370610
Short name T133
Test name
Test status
Simulation time 66539338663 ps
CPU time 97.33 seconds
Started Jun 13 02:15:22 PM PDT 24
Finished Jun 13 02:17:00 PM PDT 24
Peak memory 223504 kb
Host smart-a0c6cb11-1f14-47df-aa4c-11b31ce6f20f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750370610 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.2750370610
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3774747674
Short name T356
Test name
Test status
Simulation time 453593944 ps
CPU time 3.17 seconds
Started Jun 13 02:15:22 PM PDT 24
Finished Jun 13 02:15:25 PM PDT 24
Peak memory 213672 kb
Host smart-00fdc88d-9ad9-4198-910f-444d91a29d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774747674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3774747674
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1886665405
Short name T129
Test name
Test status
Simulation time 1314605548 ps
CPU time 16.44 seconds
Started Jun 13 02:15:24 PM PDT 24
Finished Jun 13 02:15:41 PM PDT 24
Peak memory 213660 kb
Host smart-bf970fe4-f238-4d2d-973c-08706b8b3a6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886665405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1886665405
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3179681058
Short name T330
Test name
Test status
Simulation time 1225767745 ps
CPU time 28.97 seconds
Started Jun 13 02:15:29 PM PDT 24
Finished Jun 13 02:15:59 PM PDT 24
Peak memory 213660 kb
Host smart-6d4e8167-3eea-4d44-85f1-8b59c9185953
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179681058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3179681058
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3111554650
Short name T96
Test name
Test status
Simulation time 69973828283 ps
CPU time 69.44 seconds
Started Jun 13 02:15:28 PM PDT 24
Finished Jun 13 02:16:39 PM PDT 24
Peak memory 205540 kb
Host smart-1f6a3d3a-6daf-464a-ab69-e3c100d41890
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111554650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3111554650
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1853208293
Short name T398
Test name
Test status
Simulation time 231276663 ps
CPU time 2.35 seconds
Started Jun 13 02:15:33 PM PDT 24
Finished Jun 13 02:15:37 PM PDT 24
Peak memory 213660 kb
Host smart-ca374e88-b5e6-4f0f-a47a-c2348df68c1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853208293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1853208293
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2972766112
Short name T346
Test name
Test status
Simulation time 491962864 ps
CPU time 3.87 seconds
Started Jun 13 02:15:33 PM PDT 24
Finished Jun 13 02:15:39 PM PDT 24
Peak memory 219864 kb
Host smart-32446a10-6146-426c-81de-bb59ad27f9ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972766112 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2972766112
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1097832832
Short name T305
Test name
Test status
Simulation time 456286286 ps
CPU time 2.4 seconds
Started Jun 13 02:15:32 PM PDT 24
Finished Jun 13 02:15:36 PM PDT 24
Peak memory 213672 kb
Host smart-bdce05cf-35dc-4e01-b11e-da9739b9ff62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097832832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1097832832
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1508845239
Short name T347
Test name
Test status
Simulation time 62051956177 ps
CPU time 48.79 seconds
Started Jun 13 02:15:29 PM PDT 24
Finished Jun 13 02:16:19 PM PDT 24
Peak memory 205428 kb
Host smart-15dd76d6-f807-47fb-96d1-a30c6f115425
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508845239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1508845239
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.888423714
Short name T328
Test name
Test status
Simulation time 4682762568 ps
CPU time 7.41 seconds
Started Jun 13 02:15:32 PM PDT 24
Finished Jun 13 02:15:40 PM PDT 24
Peak memory 205532 kb
Host smart-6b41314f-95e2-4f12-b989-2036617659a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888423714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r
v_dm_jtag_dmi_csr_bit_bash.888423714
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.623492423
Short name T281
Test name
Test status
Simulation time 1518538534 ps
CPU time 2.91 seconds
Started Jun 13 02:15:28 PM PDT 24
Finished Jun 13 02:15:31 PM PDT 24
Peak memory 205464 kb
Host smart-fd28c485-9ebd-4f61-bce4-9d6cfa763f09
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623492423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.623492423
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1381767206
Short name T402
Test name
Test status
Simulation time 6626192399 ps
CPU time 9.81 seconds
Started Jun 13 02:15:28 PM PDT 24
Finished Jun 13 02:15:39 PM PDT 24
Peak memory 205504 kb
Host smart-7c75f57f-8f24-4dd3-afe7-f5e97baf6016
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381767206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
381767206
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.863341752
Short name T60
Test name
Test status
Simulation time 1059231395 ps
CPU time 1.46 seconds
Started Jun 13 02:15:29 PM PDT 24
Finished Jun 13 02:15:31 PM PDT 24
Peak memory 205164 kb
Host smart-1fedc4b7-770a-4dfb-aba4-bbfee7b56256
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863341752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.863341752
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.62235688
Short name T389
Test name
Test status
Simulation time 15928510204 ps
CPU time 13.35 seconds
Started Jun 13 02:15:29 PM PDT 24
Finished Jun 13 02:15:43 PM PDT 24
Peak memory 205492 kb
Host smart-60f20b97-b53f-4dc9-b8c8-8619a8dbc48b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62235688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_
bit_bash.62235688
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2061658782
Short name T380
Test name
Test status
Simulation time 1614454023 ps
CPU time 4.28 seconds
Started Jun 13 02:15:30 PM PDT 24
Finished Jun 13 02:15:35 PM PDT 24
Peak memory 205180 kb
Host smart-942cdde9-2fe0-43cb-8964-7cd59240b7d9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061658782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2061658782
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2301484374
Short name T322
Test name
Test status
Simulation time 155600252 ps
CPU time 0.82 seconds
Started Jun 13 02:15:31 PM PDT 24
Finished Jun 13 02:15:33 PM PDT 24
Peak memory 205188 kb
Host smart-0adb559d-38f1-49ec-8fd3-3ee374f82172
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301484374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
301484374
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1428426051
Short name T403
Test name
Test status
Simulation time 99247092 ps
CPU time 0.83 seconds
Started Jun 13 02:15:31 PM PDT 24
Finished Jun 13 02:15:32 PM PDT 24
Peak memory 205156 kb
Host smart-fc2c0acb-297d-4520-b7cc-9d7cbc76590c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428426051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1428426051
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2803038544
Short name T358
Test name
Test status
Simulation time 34924667 ps
CPU time 0.74 seconds
Started Jun 13 02:15:31 PM PDT 24
Finished Jun 13 02:15:33 PM PDT 24
Peak memory 205184 kb
Host smart-158c051e-a582-49a8-9add-64636eebb394
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803038544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2803038544
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2677494597
Short name T101
Test name
Test status
Simulation time 1614764529 ps
CPU time 4.94 seconds
Started Jun 13 02:15:30 PM PDT 24
Finished Jun 13 02:15:36 PM PDT 24
Peak memory 205432 kb
Host smart-51dfb64e-d358-4797-aefe-16731e790cde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677494597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2677494597
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.161078358
Short name T329
Test name
Test status
Simulation time 11960060748 ps
CPU time 32.39 seconds
Started Jun 13 02:15:31 PM PDT 24
Finished Jun 13 02:16:04 PM PDT 24
Peak memory 221956 kb
Host smart-22d3320c-cf06-4504-bc7b-e8807ed0b72e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161078358 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.161078358
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2257066087
Short name T119
Test name
Test status
Simulation time 369052613 ps
CPU time 3.17 seconds
Started Jun 13 02:15:31 PM PDT 24
Finished Jun 13 02:15:35 PM PDT 24
Peak memory 213712 kb
Host smart-ac0d8217-1135-40a9-889a-162f5dc01b90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257066087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2257066087
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1744490133
Short name T124
Test name
Test status
Simulation time 3096959034 ps
CPU time 22.68 seconds
Started Jun 13 02:15:36 PM PDT 24
Finished Jun 13 02:16:00 PM PDT 24
Peak memory 221820 kb
Host smart-8951b98f-ba7c-405d-ae07-edfa7fcfaf9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744490133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1744490133
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1874932139
Short name T71
Test name
Test status
Simulation time 3973416426 ps
CPU time 6.17 seconds
Started Jun 13 02:16:00 PM PDT 24
Finished Jun 13 02:16:08 PM PDT 24
Peak memory 213876 kb
Host smart-903b2df9-69ac-4b7c-9882-1c25204aa715
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874932139 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1874932139
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.904041818
Short name T77
Test name
Test status
Simulation time 1264018734 ps
CPU time 2.5 seconds
Started Jun 13 02:16:03 PM PDT 24
Finished Jun 13 02:16:07 PM PDT 24
Peak memory 213680 kb
Host smart-64f65cd4-6acf-4cd8-a0e0-e6c9291202a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904041818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.904041818
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2847647806
Short name T321
Test name
Test status
Simulation time 5302090907 ps
CPU time 14.37 seconds
Started Jun 13 02:16:03 PM PDT 24
Finished Jun 13 02:16:19 PM PDT 24
Peak memory 205492 kb
Host smart-7348654a-23ab-4f18-b03b-a7285704544d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847647806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.2847647806
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.272935788
Short name T375
Test name
Test status
Simulation time 1776880899 ps
CPU time 1.42 seconds
Started Jun 13 02:16:01 PM PDT 24
Finished Jun 13 02:16:04 PM PDT 24
Peak memory 205380 kb
Host smart-8e9c3cdb-028f-475e-b4d1-5891884c1ecb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272935788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.272935788
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3245904567
Short name T364
Test name
Test status
Simulation time 341606768 ps
CPU time 1.6 seconds
Started Jun 13 02:15:59 PM PDT 24
Finished Jun 13 02:16:02 PM PDT 24
Peak memory 205180 kb
Host smart-591f2968-300c-4ec2-9eae-6d612928ddfa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245904567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3245904567
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3498009199
Short name T409
Test name
Test status
Simulation time 561803504 ps
CPU time 4.25 seconds
Started Jun 13 02:15:59 PM PDT 24
Finished Jun 13 02:16:05 PM PDT 24
Peak memory 205428 kb
Host smart-0605d6bb-5366-4ac1-a344-59b0888eb3dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498009199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3498009199
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2169360831
Short name T70
Test name
Test status
Simulation time 1133858750 ps
CPU time 5.92 seconds
Started Jun 13 02:16:03 PM PDT 24
Finished Jun 13 02:16:11 PM PDT 24
Peak memory 213720 kb
Host smart-3b7a6c6a-9bd6-4092-aab2-91f1cb37118d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169360831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2169360831
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1420569490
Short name T383
Test name
Test status
Simulation time 2334648003 ps
CPU time 21.39 seconds
Started Jun 13 02:16:00 PM PDT 24
Finished Jun 13 02:16:23 PM PDT 24
Peak memory 213740 kb
Host smart-23dfe18c-0415-4897-bb4e-dbadfb53fc16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420569490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
420569490
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2120286116
Short name T300
Test name
Test status
Simulation time 3216305856 ps
CPU time 5.04 seconds
Started Jun 13 02:16:01 PM PDT 24
Finished Jun 13 02:16:07 PM PDT 24
Peak memory 220896 kb
Host smart-425e6aa6-9cf3-49b3-9c77-a921afac0b80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120286116 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2120286116
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2453840350
Short name T109
Test name
Test status
Simulation time 287723088 ps
CPU time 1.52 seconds
Started Jun 13 02:15:59 PM PDT 24
Finished Jun 13 02:16:02 PM PDT 24
Peak memory 213692 kb
Host smart-ff6e11f2-9c08-4580-976b-54967ab79e7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453840350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2453840350
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1519385149
Short name T263
Test name
Test status
Simulation time 4170053973 ps
CPU time 3.68 seconds
Started Jun 13 02:16:01 PM PDT 24
Finished Jun 13 02:16:06 PM PDT 24
Peak memory 205508 kb
Host smart-105e143b-906c-4472-915b-0d66bbd9c417
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519385149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1519385149
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2810374758
Short name T267
Test name
Test status
Simulation time 3656987582 ps
CPU time 5.92 seconds
Started Jun 13 02:16:01 PM PDT 24
Finished Jun 13 02:16:09 PM PDT 24
Peak memory 205504 kb
Host smart-2506aac0-bb49-4975-bdc8-635cf1baaac7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810374758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2810374758
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.952832802
Short name T374
Test name
Test status
Simulation time 397347181 ps
CPU time 1.18 seconds
Started Jun 13 02:16:03 PM PDT 24
Finished Jun 13 02:16:06 PM PDT 24
Peak memory 205204 kb
Host smart-02da4283-7884-46e1-bf18-f06459b686ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952832802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.952832802
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1479365216
Short name T93
Test name
Test status
Simulation time 262880540 ps
CPU time 3.62 seconds
Started Jun 13 02:16:02 PM PDT 24
Finished Jun 13 02:16:07 PM PDT 24
Peak memory 205436 kb
Host smart-eeb57c18-aa7e-4270-9f7c-0bd61e13bf55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479365216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1479365216
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1357369955
Short name T344
Test name
Test status
Simulation time 219769252 ps
CPU time 3.03 seconds
Started Jun 13 02:16:02 PM PDT 24
Finished Jun 13 02:16:07 PM PDT 24
Peak memory 213736 kb
Host smart-bb9009b0-a1b3-4dbf-bd4b-9e943beaeb23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357369955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1357369955
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3114195589
Short name T319
Test name
Test status
Simulation time 1868536837 ps
CPU time 6.48 seconds
Started Jun 13 02:16:03 PM PDT 24
Finished Jun 13 02:16:11 PM PDT 24
Peak memory 221840 kb
Host smart-160535ad-2f96-42f8-9e3e-8e06aaef0b8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114195589 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3114195589
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1640901362
Short name T95
Test name
Test status
Simulation time 103354129 ps
CPU time 1.54 seconds
Started Jun 13 02:16:07 PM PDT 24
Finished Jun 13 02:16:10 PM PDT 24
Peak memory 213672 kb
Host smart-49367033-7e12-4c8a-867c-41a96ea9ea1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640901362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1640901362
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1417497554
Short name T340
Test name
Test status
Simulation time 6691881008 ps
CPU time 6.79 seconds
Started Jun 13 02:16:11 PM PDT 24
Finished Jun 13 02:16:19 PM PDT 24
Peak memory 205528 kb
Host smart-35d25212-f38e-480d-b01c-8ebbe69cdb1b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417497554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.1417497554
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3211158865
Short name T292
Test name
Test status
Simulation time 2947237354 ps
CPU time 8.2 seconds
Started Jun 13 02:16:05 PM PDT 24
Finished Jun 13 02:16:14 PM PDT 24
Peak memory 205464 kb
Host smart-770d31d1-ce7c-4849-9907-bbd1e58d005a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211158865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3211158865
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1175669431
Short name T387
Test name
Test status
Simulation time 130309721 ps
CPU time 0.99 seconds
Started Jun 13 02:16:03 PM PDT 24
Finished Jun 13 02:16:06 PM PDT 24
Peak memory 205188 kb
Host smart-f84f9e14-46f2-468d-9997-3942a5d6cd9d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175669431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1175669431
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3381058312
Short name T362
Test name
Test status
Simulation time 411613648 ps
CPU time 7.23 seconds
Started Jun 13 02:16:10 PM PDT 24
Finished Jun 13 02:16:19 PM PDT 24
Peak memory 205468 kb
Host smart-ebf984ba-923d-4ff9-af86-1cdab4957410
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381058312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3381058312
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.908520711
Short name T118
Test name
Test status
Simulation time 204439203 ps
CPU time 2.61 seconds
Started Jun 13 02:16:11 PM PDT 24
Finished Jun 13 02:16:15 PM PDT 24
Peak memory 213820 kb
Host smart-4ec1dc3a-72fc-4b91-ac19-974646a4adb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908520711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.908520711
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3434559289
Short name T126
Test name
Test status
Simulation time 3651228137 ps
CPU time 24.26 seconds
Started Jun 13 02:16:14 PM PDT 24
Finished Jun 13 02:16:40 PM PDT 24
Peak memory 213812 kb
Host smart-1a499a02-2206-4676-93fd-31eba0220c37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434559289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
434559289
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2287019124
Short name T401
Test name
Test status
Simulation time 3549788058 ps
CPU time 9.58 seconds
Started Jun 13 02:16:10 PM PDT 24
Finished Jun 13 02:16:21 PM PDT 24
Peak memory 220032 kb
Host smart-f699de48-e51d-43e7-a3c3-b8567199e281
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287019124 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2287019124
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3238149316
Short name T85
Test name
Test status
Simulation time 97091104 ps
CPU time 2.44 seconds
Started Jun 13 02:16:05 PM PDT 24
Finished Jun 13 02:16:09 PM PDT 24
Peak memory 213672 kb
Host smart-5204d9c2-7884-4046-983b-8c77f5b868e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238149316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3238149316
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1576227007
Short name T279
Test name
Test status
Simulation time 41486136436 ps
CPU time 9.5 seconds
Started Jun 13 02:16:10 PM PDT 24
Finished Jun 13 02:16:21 PM PDT 24
Peak memory 205532 kb
Host smart-235b2291-3661-4586-842e-44f493b7714a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576227007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.1576227007
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2247496116
Short name T303
Test name
Test status
Simulation time 14522216388 ps
CPU time 23.44 seconds
Started Jun 13 02:16:08 PM PDT 24
Finished Jun 13 02:16:33 PM PDT 24
Peak memory 205476 kb
Host smart-c8b355a2-02e8-46fd-b51d-8a85035a5906
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247496116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2247496116
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.866049358
Short name T280
Test name
Test status
Simulation time 272140814 ps
CPU time 0.92 seconds
Started Jun 13 02:16:07 PM PDT 24
Finished Jun 13 02:16:09 PM PDT 24
Peak memory 205208 kb
Host smart-3145fe4d-6e2c-4c62-8f6b-a5b3964e665f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866049358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.866049358
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1198989770
Short name T388
Test name
Test status
Simulation time 371968904 ps
CPU time 6.73 seconds
Started Jun 13 02:16:07 PM PDT 24
Finished Jun 13 02:16:15 PM PDT 24
Peak memory 205468 kb
Host smart-45e8920b-827b-4b28-9837-1e47dad31272
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198989770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1198989770
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1228624586
Short name T298
Test name
Test status
Simulation time 220614448 ps
CPU time 2.64 seconds
Started Jun 13 02:16:10 PM PDT 24
Finished Jun 13 02:16:13 PM PDT 24
Peak memory 216144 kb
Host smart-0f70913b-6e72-4936-b4c5-4a2f2900a22a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228624586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1228624586
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3445686182
Short name T378
Test name
Test status
Simulation time 19412236996 ps
CPU time 21.28 seconds
Started Jun 13 02:16:05 PM PDT 24
Finished Jun 13 02:16:28 PM PDT 24
Peak memory 213780 kb
Host smart-1e9e28fb-b600-4661-9c90-92a5d1070fe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445686182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
445686182
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.703307386
Short name T316
Test name
Test status
Simulation time 1010927585 ps
CPU time 3.73 seconds
Started Jun 13 02:16:13 PM PDT 24
Finished Jun 13 02:16:19 PM PDT 24
Peak memory 218380 kb
Host smart-af5939f0-f8ba-486f-9c5f-ee67e95b5898
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703307386 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.703307386
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1676596562
Short name T106
Test name
Test status
Simulation time 191301616 ps
CPU time 1.52 seconds
Started Jun 13 02:16:15 PM PDT 24
Finished Jun 13 02:16:18 PM PDT 24
Peak memory 213692 kb
Host smart-a0c6291c-ae78-4638-b352-38a656faf190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676596562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1676596562
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2272561959
Short name T331
Test name
Test status
Simulation time 30688455884 ps
CPU time 74.04 seconds
Started Jun 13 02:16:15 PM PDT 24
Finished Jun 13 02:17:30 PM PDT 24
Peak memory 205528 kb
Host smart-e8578316-2e15-4d66-ac5f-f9866776fc42
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272561959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.2272561959
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2724505703
Short name T385
Test name
Test status
Simulation time 9349141553 ps
CPU time 25.7 seconds
Started Jun 13 02:16:22 PM PDT 24
Finished Jun 13 02:16:52 PM PDT 24
Peak memory 205552 kb
Host smart-fd16d68d-92eb-4399-8b69-a5f4d6853c95
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724505703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2724505703
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4142989067
Short name T286
Test name
Test status
Simulation time 285795974 ps
CPU time 0.91 seconds
Started Jun 13 02:16:14 PM PDT 24
Finished Jun 13 02:16:16 PM PDT 24
Peak memory 205192 kb
Host smart-785965e3-b8b0-4870-9708-477cc414c192
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142989067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
4142989067
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1230919700
Short name T369
Test name
Test status
Simulation time 217048344 ps
CPU time 4.07 seconds
Started Jun 13 02:16:12 PM PDT 24
Finished Jun 13 02:16:18 PM PDT 24
Peak memory 205520 kb
Host smart-c654bd76-daa8-40c0-9d66-4f01fd37b0d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230919700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1230919700
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.745797637
Short name T87
Test name
Test status
Simulation time 1171289077 ps
CPU time 5.05 seconds
Started Jun 13 02:16:12 PM PDT 24
Finished Jun 13 02:16:18 PM PDT 24
Peak memory 213720 kb
Host smart-bad40d9f-080e-445e-8a4a-47981260c9ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745797637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.745797637
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2974130682
Short name T75
Test name
Test status
Simulation time 5316242364 ps
CPU time 10.02 seconds
Started Jun 13 02:16:12 PM PDT 24
Finished Jun 13 02:16:23 PM PDT 24
Peak memory 213776 kb
Host smart-91569058-55c2-4b52-8639-2a0b32a5a906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974130682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
974130682
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2452376723
Short name T350
Test name
Test status
Simulation time 201679145 ps
CPU time 4.51 seconds
Started Jun 13 02:16:12 PM PDT 24
Finished Jun 13 02:16:18 PM PDT 24
Peak memory 221148 kb
Host smart-99432d0f-265e-4c23-80f1-6aa19f745aaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452376723 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2452376723
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2386503650
Short name T406
Test name
Test status
Simulation time 181534417 ps
CPU time 2.46 seconds
Started Jun 13 02:16:25 PM PDT 24
Finished Jun 13 02:16:32 PM PDT 24
Peak memory 213700 kb
Host smart-fd007203-8ee8-4bcb-af19-35b8929337f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386503650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2386503650
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2153827518
Short name T276
Test name
Test status
Simulation time 11628516560 ps
CPU time 16.27 seconds
Started Jun 13 02:16:12 PM PDT 24
Finished Jun 13 02:16:30 PM PDT 24
Peak memory 205436 kb
Host smart-ff178af3-ece4-4af3-81de-28e56221e69c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153827518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.2153827518
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3659805521
Short name T274
Test name
Test status
Simulation time 2713636943 ps
CPU time 7.32 seconds
Started Jun 13 02:16:12 PM PDT 24
Finished Jun 13 02:16:22 PM PDT 24
Peak memory 205536 kb
Host smart-4c5a07e2-3fc2-44f9-9a2b-d8cb03b70e62
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659805521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3659805521
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1017093722
Short name T323
Test name
Test status
Simulation time 136815644 ps
CPU time 0.71 seconds
Started Jun 13 02:16:14 PM PDT 24
Finished Jun 13 02:16:16 PM PDT 24
Peak memory 205200 kb
Host smart-3ed4725d-d5c0-4f15-82dc-a693b9669d30
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017093722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1017093722
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3172355814
Short name T381
Test name
Test status
Simulation time 178024725 ps
CPU time 2.87 seconds
Started Jun 13 02:16:11 PM PDT 24
Finished Jun 13 02:16:16 PM PDT 24
Peak memory 213700 kb
Host smart-6bf40f40-11fb-479e-b0f6-9414301d03c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172355814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3172355814
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1553472230
Short name T127
Test name
Test status
Simulation time 4724685584 ps
CPU time 10.07 seconds
Started Jun 13 02:16:15 PM PDT 24
Finished Jun 13 02:16:26 PM PDT 24
Peak memory 213792 kb
Host smart-ac7e35ad-594b-4bc4-a83a-3c9d2aee92d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553472230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
553472230
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3834805962
Short name T405
Test name
Test status
Simulation time 7246854828 ps
CPU time 7.38 seconds
Started Jun 13 02:16:10 PM PDT 24
Finished Jun 13 02:16:19 PM PDT 24
Peak memory 219888 kb
Host smart-108f3d7b-f284-49bc-8b6b-792fb0ef468e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834805962 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3834805962
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2655793855
Short name T368
Test name
Test status
Simulation time 55464149 ps
CPU time 1.47 seconds
Started Jun 13 02:16:23 PM PDT 24
Finished Jun 13 02:16:29 PM PDT 24
Peak memory 213700 kb
Host smart-382a1a00-72d4-4a12-aa24-1e4e80d3080a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655793855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2655793855
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3995777871
Short name T377
Test name
Test status
Simulation time 10890589122 ps
CPU time 4.78 seconds
Started Jun 13 02:16:13 PM PDT 24
Finished Jun 13 02:16:20 PM PDT 24
Peak memory 205516 kb
Host smart-d22b9a1e-80c9-48d3-ab1d-5b3d6939abe0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995777871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.3995777871
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1824326992
Short name T352
Test name
Test status
Simulation time 3169230888 ps
CPU time 3.25 seconds
Started Jun 13 02:16:21 PM PDT 24
Finished Jun 13 02:16:27 PM PDT 24
Peak memory 205584 kb
Host smart-0a84851d-cf4d-44ea-8a86-8fc085ee4c73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824326992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1824326992
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2228558293
Short name T396
Test name
Test status
Simulation time 618970422 ps
CPU time 1.38 seconds
Started Jun 13 02:16:12 PM PDT 24
Finished Jun 13 02:16:16 PM PDT 24
Peak memory 205216 kb
Host smart-1604391b-bacb-410b-a9ac-a7405fe41278
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228558293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2228558293
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2934791332
Short name T386
Test name
Test status
Simulation time 207600553 ps
CPU time 3.87 seconds
Started Jun 13 02:16:13 PM PDT 24
Finished Jun 13 02:16:19 PM PDT 24
Peak memory 205464 kb
Host smart-9ebb68ab-459f-4c20-8b56-db30f6628267
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934791332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.2934791332
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3838607289
Short name T313
Test name
Test status
Simulation time 97357936 ps
CPU time 4.98 seconds
Started Jun 13 02:16:12 PM PDT 24
Finished Jun 13 02:16:19 PM PDT 24
Peak memory 213704 kb
Host smart-5078ecb4-7b17-4c20-8c85-2a29105ed666
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838607289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3838607289
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4267363829
Short name T361
Test name
Test status
Simulation time 1507718685 ps
CPU time 5.69 seconds
Started Jun 13 02:16:18 PM PDT 24
Finished Jun 13 02:16:27 PM PDT 24
Peak memory 219608 kb
Host smart-f4276a04-c103-47eb-abbb-7a8912be2ae0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267363829 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.4267363829
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4260842336
Short name T392
Test name
Test status
Simulation time 62214821 ps
CPU time 2.14 seconds
Started Jun 13 02:16:17 PM PDT 24
Finished Jun 13 02:16:23 PM PDT 24
Peak memory 213644 kb
Host smart-1ba4e747-35be-4afc-9056-51d32970572b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260842336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.4260842336
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3361156513
Short name T268
Test name
Test status
Simulation time 11150744363 ps
CPU time 15.77 seconds
Started Jun 13 02:16:12 PM PDT 24
Finished Jun 13 02:16:30 PM PDT 24
Peak memory 205512 kb
Host smart-ae2a2360-2770-43f4-93ef-2c577539ab2f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361156513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.3361156513
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.61894686
Short name T301
Test name
Test status
Simulation time 7333705228 ps
CPU time 10.17 seconds
Started Jun 13 02:16:15 PM PDT 24
Finished Jun 13 02:16:26 PM PDT 24
Peak memory 205508 kb
Host smart-8dcaa694-5009-445a-8015-5ba6972a5019
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61894686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.61894686
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.790777784
Short name T335
Test name
Test status
Simulation time 386711801 ps
CPU time 0.77 seconds
Started Jun 13 02:16:14 PM PDT 24
Finished Jun 13 02:16:17 PM PDT 24
Peak memory 205180 kb
Host smart-03d38c29-eaab-411b-81d3-938bdfda2fd3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790777784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.790777784
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3786324360
Short name T103
Test name
Test status
Simulation time 620075931 ps
CPU time 8 seconds
Started Jun 13 02:16:19 PM PDT 24
Finished Jun 13 02:16:30 PM PDT 24
Peak memory 205476 kb
Host smart-580f061c-6464-4187-b03f-c1ba9e952b2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786324360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3786324360
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2806577785
Short name T171
Test name
Test status
Simulation time 112167316 ps
CPU time 5.23 seconds
Started Jun 13 02:16:20 PM PDT 24
Finished Jun 13 02:16:28 PM PDT 24
Peak memory 213704 kb
Host smart-94b2ee1a-969b-4326-8cb2-8b3b640de43b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806577785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2806577785
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3301960597
Short name T365
Test name
Test status
Simulation time 2063012008 ps
CPU time 12.15 seconds
Started Jun 13 02:16:17 PM PDT 24
Finished Jun 13 02:16:30 PM PDT 24
Peak memory 213660 kb
Host smart-697d9e9a-3acf-47c7-9b4a-8e0c7184f943
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301960597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
301960597
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2362953552
Short name T311
Test name
Test status
Simulation time 136665830 ps
CPU time 2.57 seconds
Started Jun 13 02:16:18 PM PDT 24
Finished Jun 13 02:16:24 PM PDT 24
Peak memory 218680 kb
Host smart-a220a50e-2be6-4ccf-9118-2417968ca4f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362953552 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2362953552
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.87907300
Short name T342
Test name
Test status
Simulation time 189926455 ps
CPU time 2.66 seconds
Started Jun 13 02:16:17 PM PDT 24
Finished Jun 13 02:16:24 PM PDT 24
Peak memory 213656 kb
Host smart-dc182726-6ccf-4a8c-b890-83ae9634220d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87907300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.87907300
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3011820618
Short name T282
Test name
Test status
Simulation time 8691566500 ps
CPU time 5.46 seconds
Started Jun 13 02:16:22 PM PDT 24
Finished Jun 13 02:16:31 PM PDT 24
Peak memory 205552 kb
Host smart-73a29e35-c06a-4ea3-a23d-2aed7cb72ed6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011820618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.3011820618
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2011726312
Short name T269
Test name
Test status
Simulation time 15559365973 ps
CPU time 40.66 seconds
Started Jun 13 02:16:18 PM PDT 24
Finished Jun 13 02:17:02 PM PDT 24
Peak memory 205508 kb
Host smart-307fbd5c-5e75-43bd-9347-065b3a548df6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011726312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2011726312
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.942173383
Short name T320
Test name
Test status
Simulation time 317354457 ps
CPU time 0.92 seconds
Started Jun 13 02:16:18 PM PDT 24
Finished Jun 13 02:16:22 PM PDT 24
Peak memory 205200 kb
Host smart-9a8c4677-b3f4-44d1-b3b7-c5319f3e3327
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942173383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.942173383
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2210477336
Short name T84
Test name
Test status
Simulation time 932224980 ps
CPU time 4.23 seconds
Started Jun 13 02:16:20 PM PDT 24
Finished Jun 13 02:16:27 PM PDT 24
Peak memory 205524 kb
Host smart-9255d657-6f50-47cb-8a97-54a3fab71373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210477336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2210477336
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.857624553
Short name T376
Test name
Test status
Simulation time 262221266 ps
CPU time 3.28 seconds
Started Jun 13 02:16:18 PM PDT 24
Finished Jun 13 02:16:25 PM PDT 24
Peak memory 213720 kb
Host smart-7e3e10be-f9d7-4aa8-a53f-83533539cf2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857624553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.857624553
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4277018862
Short name T65
Test name
Test status
Simulation time 3233356155 ps
CPU time 17.19 seconds
Started Jun 13 02:16:20 PM PDT 24
Finished Jun 13 02:16:40 PM PDT 24
Peak memory 213776 kb
Host smart-d87881d2-e168-4560-b9f5-8bb803e130a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277018862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4
277018862
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3334711388
Short name T299
Test name
Test status
Simulation time 1295807631 ps
CPU time 2.7 seconds
Started Jun 13 02:16:20 PM PDT 24
Finished Jun 13 02:16:26 PM PDT 24
Peak memory 221824 kb
Host smart-ffc361c2-c04b-4ae1-8493-bc217da4265c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334711388 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3334711388
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.480450193
Short name T108
Test name
Test status
Simulation time 116700810 ps
CPU time 1.54 seconds
Started Jun 13 02:16:20 PM PDT 24
Finished Jun 13 02:16:25 PM PDT 24
Peak memory 213652 kb
Host smart-46299b5d-3bc4-4800-a0c7-04307fce04b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480450193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.480450193
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2495544429
Short name T265
Test name
Test status
Simulation time 7906427701 ps
CPU time 20.74 seconds
Started Jun 13 02:16:19 PM PDT 24
Finished Jun 13 02:16:43 PM PDT 24
Peak memory 205508 kb
Host smart-2b21a9a8-a309-48aa-9092-de34ca4754c4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495544429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2495544429
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.163555582
Short name T393
Test name
Test status
Simulation time 14060089164 ps
CPU time 8.36 seconds
Started Jun 13 02:16:23 PM PDT 24
Finished Jun 13 02:16:36 PM PDT 24
Peak memory 205500 kb
Host smart-5ec765ff-10f8-48c5-9a85-740d1c45efe9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163555582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.163555582
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3767874803
Short name T275
Test name
Test status
Simulation time 121056588 ps
CPU time 0.74 seconds
Started Jun 13 02:16:22 PM PDT 24
Finished Jun 13 02:16:26 PM PDT 24
Peak memory 205212 kb
Host smart-cb6c52ba-6d8a-44b9-8a05-9370f8da592c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767874803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3767874803
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1524148685
Short name T113
Test name
Test status
Simulation time 161553874 ps
CPU time 3.79 seconds
Started Jun 13 02:16:25 PM PDT 24
Finished Jun 13 02:16:33 PM PDT 24
Peak memory 205536 kb
Host smart-7c90fcad-eb58-4348-be7c-ac93fb5d474e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524148685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1524148685
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3565088307
Short name T73
Test name
Test status
Simulation time 112232937 ps
CPU time 2.56 seconds
Started Jun 13 02:16:20 PM PDT 24
Finished Jun 13 02:16:26 PM PDT 24
Peak memory 213736 kb
Host smart-f9df882d-1244-4e57-b801-8e2e3837e471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565088307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3565088307
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4246089390
Short name T128
Test name
Test status
Simulation time 2114289923 ps
CPU time 23.87 seconds
Started Jun 13 02:16:18 PM PDT 24
Finished Jun 13 02:16:45 PM PDT 24
Peak memory 213684 kb
Host smart-43d9d880-3ada-48c9-8326-61a3240dea90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246089390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4
246089390
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3536537926
Short name T337
Test name
Test status
Simulation time 5353237964 ps
CPU time 29.25 seconds
Started Jun 13 02:15:29 PM PDT 24
Finished Jun 13 02:15:59 PM PDT 24
Peak memory 213800 kb
Host smart-7381376c-305e-49a8-a129-ac5267dfcbf6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536537926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3536537926
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1276546504
Short name T297
Test name
Test status
Simulation time 1536754276 ps
CPU time 60.45 seconds
Started Jun 13 02:15:31 PM PDT 24
Finished Jun 13 02:16:33 PM PDT 24
Peak memory 205464 kb
Host smart-a44d8c88-c2ff-43f0-b5be-6e0dfb89dd14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276546504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1276546504
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2899156266
Short name T99
Test name
Test status
Simulation time 154196885 ps
CPU time 1.52 seconds
Started Jun 13 02:15:33 PM PDT 24
Finished Jun 13 02:15:36 PM PDT 24
Peak memory 213692 kb
Host smart-3f15ccb1-5b88-4da7-b181-4c987359cabe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899156266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2899156266
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.379501478
Short name T64
Test name
Test status
Simulation time 184749885 ps
CPU time 2.21 seconds
Started Jun 13 02:15:34 PM PDT 24
Finished Jun 13 02:15:37 PM PDT 24
Peak memory 215768 kb
Host smart-dbff23b2-1f15-4a10-bcd4-597d58eabc79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379501478 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.379501478
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.4059264844
Short name T92
Test name
Test status
Simulation time 672414283 ps
CPU time 1.73 seconds
Started Jun 13 02:15:33 PM PDT 24
Finished Jun 13 02:15:36 PM PDT 24
Peak memory 213704 kb
Host smart-24c7f4bb-bcc7-465e-b17e-39afdc1bac90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059264844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.4059264844
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1949914667
Short name T291
Test name
Test status
Simulation time 16492396818 ps
CPU time 41.93 seconds
Started Jun 13 02:15:33 PM PDT 24
Finished Jun 13 02:16:17 PM PDT 24
Peak memory 205468 kb
Host smart-6ca54bfe-1a6f-44c2-85c3-f5ece24761e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949914667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1949914667
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.832686656
Short name T91
Test name
Test status
Simulation time 9847739187 ps
CPU time 23.78 seconds
Started Jun 13 02:15:31 PM PDT 24
Finished Jun 13 02:15:57 PM PDT 24
Peak memory 205580 kb
Host smart-6d1d1442-ba5d-4f01-ad9a-716dc68d9a37
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832686656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.832686656
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.924868461
Short name T295
Test name
Test status
Simulation time 1117219473 ps
CPU time 4.06 seconds
Started Jun 13 02:15:34 PM PDT 24
Finished Jun 13 02:15:39 PM PDT 24
Peak memory 205440 kb
Host smart-bb307b02-8017-4760-b268-0a79f06c4fd1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924868461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.924868461
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3781327167
Short name T341
Test name
Test status
Simulation time 2114344498 ps
CPU time 1.8 seconds
Started Jun 13 02:15:30 PM PDT 24
Finished Jun 13 02:15:32 PM PDT 24
Peak memory 205168 kb
Host smart-fc7ac746-4905-437a-a1ac-5832c5839248
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781327167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3781327167
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.177330650
Short name T278
Test name
Test status
Simulation time 16379692979 ps
CPU time 36.42 seconds
Started Jun 13 02:15:31 PM PDT 24
Finished Jun 13 02:16:08 PM PDT 24
Peak memory 205704 kb
Host smart-6d8f11cc-6ae1-4b16-ad7f-87b1d2cd26e3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177330650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.177330650
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1058063231
Short name T62
Test name
Test status
Simulation time 326755600 ps
CPU time 1.25 seconds
Started Jun 13 02:15:36 PM PDT 24
Finished Jun 13 02:15:38 PM PDT 24
Peak memory 205200 kb
Host smart-19772730-e0d0-4f57-908e-962d1a705938
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058063231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1058063231
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2834081511
Short name T306
Test name
Test status
Simulation time 141900393 ps
CPU time 0.74 seconds
Started Jun 13 02:15:31 PM PDT 24
Finished Jun 13 02:15:33 PM PDT 24
Peak memory 205180 kb
Host smart-1e29a4c1-3466-4a0f-a55f-44d903eb55d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834081511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
834081511
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.62851976
Short name T334
Test name
Test status
Simulation time 108667506 ps
CPU time 0.69 seconds
Started Jun 13 02:15:35 PM PDT 24
Finished Jun 13 02:15:37 PM PDT 24
Peak memory 205136 kb
Host smart-c590d5a8-3ebd-491e-a439-be41616c4202
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62851976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_parti
al_access.62851976
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1662709304
Short name T293
Test name
Test status
Simulation time 163462105 ps
CPU time 0.7 seconds
Started Jun 13 02:15:34 PM PDT 24
Finished Jun 13 02:15:36 PM PDT 24
Peak memory 205208 kb
Host smart-bd7deace-b3dd-4b46-b791-ec9f49cfcff8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662709304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1662709304
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3741301091
Short name T80
Test name
Test status
Simulation time 347106774 ps
CPU time 3.69 seconds
Started Jun 13 02:15:34 PM PDT 24
Finished Jun 13 02:15:40 PM PDT 24
Peak memory 205464 kb
Host smart-3bea77cb-7021-49ee-95cb-0881d4b06db9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741301091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3741301091
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.714248354
Short name T348
Test name
Test status
Simulation time 27884566653 ps
CPU time 22.46 seconds
Started Jun 13 02:15:36 PM PDT 24
Finished Jun 13 02:16:00 PM PDT 24
Peak memory 220816 kb
Host smart-e13dff63-82ce-4264-9b29-da88990842b4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714248354 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.714248354
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1104489906
Short name T307
Test name
Test status
Simulation time 325047830 ps
CPU time 4.87 seconds
Started Jun 13 02:15:40 PM PDT 24
Finished Jun 13 02:15:46 PM PDT 24
Peak memory 213704 kb
Host smart-a87dfe99-506b-42e7-b9c4-d072876b6e2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104489906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1104489906
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2801082985
Short name T104
Test name
Test status
Simulation time 2270004945 ps
CPU time 66.75 seconds
Started Jun 13 02:15:35 PM PDT 24
Finished Jun 13 02:16:43 PM PDT 24
Peak memory 213828 kb
Host smart-44f2d172-2efe-4e97-aba4-71edfc8b1c99
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801082985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2801082985
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2514632915
Short name T110
Test name
Test status
Simulation time 5749571732 ps
CPU time 34.16 seconds
Started Jun 13 02:15:39 PM PDT 24
Finished Jun 13 02:16:14 PM PDT 24
Peak memory 213768 kb
Host smart-9732f515-33ab-4707-bb8f-9fb2bb99c082
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514632915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2514632915
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.467041113
Short name T100
Test name
Test status
Simulation time 620562660 ps
CPU time 2.42 seconds
Started Jun 13 02:15:39 PM PDT 24
Finished Jun 13 02:15:43 PM PDT 24
Peak memory 213684 kb
Host smart-a40d94f9-f769-464c-a2ab-410ffbe0dd5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467041113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.467041113
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3305546975
Short name T359
Test name
Test status
Simulation time 2038521979 ps
CPU time 4.16 seconds
Started Jun 13 02:15:42 PM PDT 24
Finished Jun 13 02:15:48 PM PDT 24
Peak memory 219440 kb
Host smart-51bfcb18-841d-4b71-a6fa-1b7bc05980b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305546975 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3305546975
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.292150503
Short name T111
Test name
Test status
Simulation time 101490897 ps
CPU time 1.6 seconds
Started Jun 13 02:15:40 PM PDT 24
Finished Jun 13 02:15:43 PM PDT 24
Peak memory 213720 kb
Host smart-4b93bd52-614b-4f14-ae5c-4603c3ee935b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292150503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.292150503
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.217194800
Short name T273
Test name
Test status
Simulation time 63549692429 ps
CPU time 40.56 seconds
Started Jun 13 02:15:44 PM PDT 24
Finished Jun 13 02:16:26 PM PDT 24
Peak memory 205556 kb
Host smart-22e30010-c0a2-4882-8a9c-83dc25b1a025
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217194800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.217194800
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2159550033
Short name T264
Test name
Test status
Simulation time 34143486469 ps
CPU time 46.12 seconds
Started Jun 13 02:15:41 PM PDT 24
Finished Jun 13 02:16:28 PM PDT 24
Peak memory 205516 kb
Host smart-90cb7069-f8a2-4308-82ab-195cb44db635
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159550033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.2159550033
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4293884884
Short name T397
Test name
Test status
Simulation time 2302351951 ps
CPU time 2.29 seconds
Started Jun 13 02:15:44 PM PDT 24
Finished Jun 13 02:15:47 PM PDT 24
Peak memory 205592 kb
Host smart-b64f5efb-5b07-4c85-a0df-1b230840ee7c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293884884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.4293884884
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3591564224
Short name T270
Test name
Test status
Simulation time 1046594550 ps
CPU time 2.68 seconds
Started Jun 13 02:15:45 PM PDT 24
Finished Jun 13 02:15:49 PM PDT 24
Peak memory 205412 kb
Host smart-ce8bd9a6-7794-4793-a7d4-eade2de50492
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591564224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
591564224
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4030826785
Short name T333
Test name
Test status
Simulation time 546752800 ps
CPU time 0.95 seconds
Started Jun 13 02:15:36 PM PDT 24
Finished Jun 13 02:15:38 PM PDT 24
Peak memory 205192 kb
Host smart-874d4fac-cb68-4d1d-9d0e-7c5919522d88
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030826785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.4030826785
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2813608591
Short name T318
Test name
Test status
Simulation time 17567265575 ps
CPU time 21.85 seconds
Started Jun 13 02:15:34 PM PDT 24
Finished Jun 13 02:15:57 PM PDT 24
Peak memory 205524 kb
Host smart-51b3aba3-e0c6-4b6b-82d1-4eda0fce694f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813608591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2813608591
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1000802018
Short name T324
Test name
Test status
Simulation time 244057365 ps
CPU time 0.9 seconds
Started Jun 13 02:15:35 PM PDT 24
Finished Jun 13 02:15:37 PM PDT 24
Peak memory 205268 kb
Host smart-d63aee1f-c539-4724-b0e4-285ac11f9ffc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000802018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1000802018
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2457976625
Short name T317
Test name
Test status
Simulation time 1514563890 ps
CPU time 1.49 seconds
Started Jun 13 02:15:36 PM PDT 24
Finished Jun 13 02:15:38 PM PDT 24
Peak memory 205208 kb
Host smart-03806bba-a75e-419d-a6ec-ecd6023a3439
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457976625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
457976625
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2481689817
Short name T327
Test name
Test status
Simulation time 153935151 ps
CPU time 1.03 seconds
Started Jun 13 02:15:41 PM PDT 24
Finished Jun 13 02:15:44 PM PDT 24
Peak memory 205140 kb
Host smart-c57764ab-26b9-484a-9f9d-741130e081cb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481689817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2481689817
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1584097304
Short name T349
Test name
Test status
Simulation time 95837271 ps
CPU time 0.88 seconds
Started Jun 13 02:15:42 PM PDT 24
Finished Jun 13 02:15:44 PM PDT 24
Peak memory 205200 kb
Host smart-d5fd4c47-7d42-4afc-80b0-3bde177fad5d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584097304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1584097304
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2981889060
Short name T82
Test name
Test status
Simulation time 694422099 ps
CPU time 3.48 seconds
Started Jun 13 02:15:42 PM PDT 24
Finished Jun 13 02:15:47 PM PDT 24
Peak memory 205440 kb
Host smart-9c97021c-78e4-4fd3-8397-89b7a65f3690
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981889060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2981889060
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3098600044
Short name T338
Test name
Test status
Simulation time 63536128 ps
CPU time 2.88 seconds
Started Jun 13 02:15:44 PM PDT 24
Finished Jun 13 02:15:48 PM PDT 24
Peak memory 213752 kb
Host smart-6106b2ce-6971-4263-a17f-a4722f9a695a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098600044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3098600044
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2550390331
Short name T312
Test name
Test status
Simulation time 7207465650 ps
CPU time 31.08 seconds
Started Jun 13 02:15:39 PM PDT 24
Finished Jun 13 02:16:11 PM PDT 24
Peak memory 213756 kb
Host smart-a882770c-068d-434c-b52b-c9edcd72eeba
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550390331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2550390331
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3709323393
Short name T309
Test name
Test status
Simulation time 31911547751 ps
CPU time 39.47 seconds
Started Jun 13 02:15:47 PM PDT 24
Finished Jun 13 02:16:28 PM PDT 24
Peak memory 213816 kb
Host smart-a9535383-b1d3-4239-b51b-cb43370908a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709323393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3709323393
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.660199007
Short name T94
Test name
Test status
Simulation time 156985832 ps
CPU time 2.31 seconds
Started Jun 13 02:15:47 PM PDT 24
Finished Jun 13 02:15:50 PM PDT 24
Peak memory 213680 kb
Host smart-871052bf-7b10-46b0-8f60-614d53aeff74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660199007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.660199007
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3362186784
Short name T63
Test name
Test status
Simulation time 372345475 ps
CPU time 2.47 seconds
Started Jun 13 02:15:45 PM PDT 24
Finished Jun 13 02:15:49 PM PDT 24
Peak memory 217796 kb
Host smart-4e985c92-252d-4eb2-9677-83054b370fcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362186784 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3362186784
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.730659048
Short name T78
Test name
Test status
Simulation time 123836044 ps
CPU time 1.57 seconds
Started Jun 13 02:15:46 PM PDT 24
Finished Jun 13 02:15:49 PM PDT 24
Peak memory 213724 kb
Host smart-30f9576a-a60e-4faa-b40a-2be890477364
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730659048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.730659048
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1231176967
Short name T314
Test name
Test status
Simulation time 14363903157 ps
CPU time 38.3 seconds
Started Jun 13 02:15:44 PM PDT 24
Finished Jun 13 02:16:24 PM PDT 24
Peak memory 205492 kb
Host smart-f9f859bb-badd-4a2f-b3be-7bd1cf39049e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231176967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.1231176967
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.697900419
Short name T266
Test name
Test status
Simulation time 7591694494 ps
CPU time 19.2 seconds
Started Jun 13 02:15:43 PM PDT 24
Finished Jun 13 02:16:03 PM PDT 24
Peak memory 205620 kb
Host smart-bfc3f6f9-942c-403b-88c0-f4f604ae5cc4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697900419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.697900419
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1928890383
Short name T404
Test name
Test status
Simulation time 8175132191 ps
CPU time 2.82 seconds
Started Jun 13 02:15:41 PM PDT 24
Finished Jun 13 02:15:44 PM PDT 24
Peak memory 205536 kb
Host smart-d82b4193-47b0-41f1-966b-0efe92306ef3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928890383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
928890383
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3590863289
Short name T390
Test name
Test status
Simulation time 1426754055 ps
CPU time 1.28 seconds
Started Jun 13 02:15:42 PM PDT 24
Finished Jun 13 02:15:45 PM PDT 24
Peak memory 205196 kb
Host smart-7539b3c1-c671-4175-88d9-5dc33115b528
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590863289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3590863289
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.565973606
Short name T360
Test name
Test status
Simulation time 10394517753 ps
CPU time 29.98 seconds
Started Jun 13 02:15:42 PM PDT 24
Finished Jun 13 02:16:13 PM PDT 24
Peak memory 205532 kb
Host smart-c56c4bc4-05ae-4dda-96ac-42e9d0716531
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565973606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.565973606
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.434481565
Short name T61
Test name
Test status
Simulation time 1162956494 ps
CPU time 0.89 seconds
Started Jun 13 02:15:43 PM PDT 24
Finished Jun 13 02:15:45 PM PDT 24
Peak memory 205272 kb
Host smart-4e514ddf-4ccd-40bf-8f1b-01c003cef498
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434481565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.434481565
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3679224585
Short name T290
Test name
Test status
Simulation time 858925843 ps
CPU time 3.22 seconds
Started Jun 13 02:15:39 PM PDT 24
Finished Jun 13 02:15:44 PM PDT 24
Peak memory 205216 kb
Host smart-cb5d8212-4ea4-4386-8657-4bfa3563ff80
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679224585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
679224585
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3196759538
Short name T310
Test name
Test status
Simulation time 170177433 ps
CPU time 0.72 seconds
Started Jun 13 02:15:46 PM PDT 24
Finished Jun 13 02:15:48 PM PDT 24
Peak memory 205136 kb
Host smart-13a46754-3845-4387-8e7c-78e92a78ec77
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196759538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3196759538
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2453460546
Short name T382
Test name
Test status
Simulation time 92242327 ps
CPU time 0.69 seconds
Started Jun 13 02:15:45 PM PDT 24
Finished Jun 13 02:15:47 PM PDT 24
Peak memory 205228 kb
Host smart-5bee599d-a9ef-4d6f-a9bf-34d8bcf7e7b9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453460546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2453460546
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3383681897
Short name T102
Test name
Test status
Simulation time 355641976 ps
CPU time 4.45 seconds
Started Jun 13 02:15:45 PM PDT 24
Finished Jun 13 02:15:51 PM PDT 24
Peak memory 205528 kb
Host smart-8d1551c7-6d91-4d51-8040-53111b227eaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383681897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3383681897
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2606829734
Short name T122
Test name
Test status
Simulation time 15893814887 ps
CPU time 33.58 seconds
Started Jun 13 02:15:45 PM PDT 24
Finished Jun 13 02:16:20 PM PDT 24
Peak memory 220220 kb
Host smart-86fba026-f3c9-4f34-a619-544f1945434d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606829734 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2606829734
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2815335987
Short name T88
Test name
Test status
Simulation time 360663793 ps
CPU time 6.44 seconds
Started Jun 13 02:15:48 PM PDT 24
Finished Jun 13 02:15:56 PM PDT 24
Peak memory 213788 kb
Host smart-017c847e-0e2f-4687-9daf-60efa97bfa4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815335987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2815335987
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2467957725
Short name T72
Test name
Test status
Simulation time 7582888197 ps
CPU time 28.93 seconds
Started Jun 13 02:15:48 PM PDT 24
Finished Jun 13 02:16:18 PM PDT 24
Peak memory 213832 kb
Host smart-d7077a6e-1af5-4c90-92c9-484c71605a0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467957725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2467957725
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.865955146
Short name T339
Test name
Test status
Simulation time 598384435 ps
CPU time 2.72 seconds
Started Jun 13 02:15:46 PM PDT 24
Finished Jun 13 02:15:50 PM PDT 24
Peak memory 217372 kb
Host smart-4ae8a4f3-ca54-4ca4-b46b-b858fb13ab6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865955146 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.865955146
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.208641315
Short name T83
Test name
Test status
Simulation time 203624050 ps
CPU time 1.59 seconds
Started Jun 13 02:15:48 PM PDT 24
Finished Jun 13 02:15:51 PM PDT 24
Peak memory 213672 kb
Host smart-97425745-aaef-4097-83a4-089e94e1332a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208641315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.208641315
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3213513983
Short name T336
Test name
Test status
Simulation time 58836035898 ps
CPU time 165.84 seconds
Started Jun 13 02:15:46 PM PDT 24
Finished Jun 13 02:18:34 PM PDT 24
Peak memory 205500 kb
Host smart-3747d076-f0a8-4e41-b4c0-c19e5284529f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213513983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3213513983
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1485641847
Short name T373
Test name
Test status
Simulation time 4210963553 ps
CPU time 3.71 seconds
Started Jun 13 02:15:47 PM PDT 24
Finished Jun 13 02:15:52 PM PDT 24
Peak memory 205508 kb
Host smart-15d41338-f80a-416e-8026-4982e981ad73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485641847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
485641847
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.677845271
Short name T289
Test name
Test status
Simulation time 675734418 ps
CPU time 1.1 seconds
Started Jun 13 02:15:48 PM PDT 24
Finished Jun 13 02:15:50 PM PDT 24
Peak memory 205204 kb
Host smart-7bced008-85b6-4952-98a5-5fb5e1460af6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677845271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.677845271
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3085864525
Short name T114
Test name
Test status
Simulation time 776602961 ps
CPU time 7.46 seconds
Started Jun 13 02:15:46 PM PDT 24
Finished Jun 13 02:15:55 PM PDT 24
Peak memory 205528 kb
Host smart-edd1aa69-f2a2-4aff-9b30-b5dfa1ea606f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085864525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3085864525
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2622096779
Short name T370
Test name
Test status
Simulation time 26977596549 ps
CPU time 80.09 seconds
Started Jun 13 02:15:46 PM PDT 24
Finished Jun 13 02:17:08 PM PDT 24
Peak memory 221920 kb
Host smart-4278612e-1b54-4460-9f11-1c6a44aad843
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622096779 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2622096779
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2660358764
Short name T354
Test name
Test status
Simulation time 365346374 ps
CPU time 4.24 seconds
Started Jun 13 02:15:47 PM PDT 24
Finished Jun 13 02:15:53 PM PDT 24
Peak memory 213628 kb
Host smart-f1780c69-e04c-4d5e-81a1-291de9837e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660358764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2660358764
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4034337208
Short name T131
Test name
Test status
Simulation time 1233176659 ps
CPU time 8.74 seconds
Started Jun 13 02:15:47 PM PDT 24
Finished Jun 13 02:15:57 PM PDT 24
Peak memory 213612 kb
Host smart-634d341d-79c3-45ca-975d-f20d00b6a1fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034337208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.4034337208
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2605555896
Short name T351
Test name
Test status
Simulation time 220244781 ps
CPU time 2.75 seconds
Started Jun 13 02:15:52 PM PDT 24
Finished Jun 13 02:15:55 PM PDT 24
Peak memory 217824 kb
Host smart-05b89300-f1a2-4557-8369-b00ff5e6656d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605555896 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2605555896
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.356427653
Short name T343
Test name
Test status
Simulation time 223494131 ps
CPU time 2.35 seconds
Started Jun 13 02:15:53 PM PDT 24
Finished Jun 13 02:15:56 PM PDT 24
Peak memory 213696 kb
Host smart-0e796640-fcdf-471f-8db7-f6d9d9946ccf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356427653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.356427653
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3025820149
Short name T284
Test name
Test status
Simulation time 27927440667 ps
CPU time 74.85 seconds
Started Jun 13 02:15:46 PM PDT 24
Finished Jun 13 02:17:03 PM PDT 24
Peak memory 205492 kb
Host smart-700b3386-4b57-42d7-bcf6-f380b70622df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025820149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.3025820149
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.233362890
Short name T288
Test name
Test status
Simulation time 11544146512 ps
CPU time 13.73 seconds
Started Jun 13 02:15:49 PM PDT 24
Finished Jun 13 02:16:03 PM PDT 24
Peak memory 205532 kb
Host smart-f8853c64-619d-4a9a-97d1-f1ab72c50a1d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233362890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.233362890
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.14548081
Short name T315
Test name
Test status
Simulation time 216458185 ps
CPU time 1.27 seconds
Started Jun 13 02:15:46 PM PDT 24
Finished Jun 13 02:15:49 PM PDT 24
Peak memory 205184 kb
Host smart-dc775ab0-e07a-4d58-8955-b6218de4daa1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14548081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.14548081
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1320778105
Short name T97
Test name
Test status
Simulation time 152827491 ps
CPU time 6.62 seconds
Started Jun 13 02:15:56 PM PDT 24
Finished Jun 13 02:16:03 PM PDT 24
Peak memory 205468 kb
Host smart-bbf87437-7245-4fb1-9fb5-1395ca336f75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320778105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1320778105
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.862634319
Short name T121
Test name
Test status
Simulation time 97561269127 ps
CPU time 59.94 seconds
Started Jun 13 02:15:45 PM PDT 24
Finished Jun 13 02:16:46 PM PDT 24
Peak memory 230272 kb
Host smart-4072fd0b-7a03-4e8b-a75d-6a2ef44adf08
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862634319 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.862634319
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2000703352
Short name T363
Test name
Test status
Simulation time 138796487 ps
CPU time 3.92 seconds
Started Jun 13 02:15:56 PM PDT 24
Finished Jun 13 02:16:00 PM PDT 24
Peak memory 213716 kb
Host smart-c600a2c7-f864-4de9-a542-e4be41408443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000703352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2000703352
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2005032010
Short name T132
Test name
Test status
Simulation time 999272752 ps
CPU time 8.69 seconds
Started Jun 13 02:15:52 PM PDT 24
Finished Jun 13 02:16:02 PM PDT 24
Peak memory 213740 kb
Host smart-6cf71bcf-535d-429e-8d27-85732bc86b0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005032010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2005032010
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2272085656
Short name T308
Test name
Test status
Simulation time 809931657 ps
CPU time 2.28 seconds
Started Jun 13 02:16:03 PM PDT 24
Finished Jun 13 02:16:07 PM PDT 24
Peak memory 218384 kb
Host smart-962a9d02-6750-4d48-925b-59e381516364
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272085656 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2272085656
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.224205633
Short name T115
Test name
Test status
Simulation time 121612183 ps
CPU time 2.32 seconds
Started Jun 13 02:15:54 PM PDT 24
Finished Jun 13 02:15:57 PM PDT 24
Peak memory 213724 kb
Host smart-608ebdd5-f9d6-4268-bc89-df12de1c40a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224205633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.224205633
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.74508236
Short name T271
Test name
Test status
Simulation time 17510393187 ps
CPU time 24.66 seconds
Started Jun 13 02:15:54 PM PDT 24
Finished Jun 13 02:16:20 PM PDT 24
Peak memory 205496 kb
Host smart-899009d6-71e1-4ee5-a026-d3a933dd51bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74508236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv
_dm_jtag_dmi_csr_bit_bash.74508236
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.962096030
Short name T399
Test name
Test status
Simulation time 1618213551 ps
CPU time 2.1 seconds
Started Jun 13 02:15:54 PM PDT 24
Finished Jun 13 02:15:56 PM PDT 24
Peak memory 205460 kb
Host smart-9fed1176-5a83-43e6-b33c-97a3ca72281e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962096030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.962096030
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3980502984
Short name T345
Test name
Test status
Simulation time 121328426 ps
CPU time 0.76 seconds
Started Jun 13 02:15:52 PM PDT 24
Finished Jun 13 02:15:54 PM PDT 24
Peak memory 205224 kb
Host smart-dead1881-98f4-490e-b039-d141ae47361e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980502984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
980502984
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1065043568
Short name T379
Test name
Test status
Simulation time 342752353 ps
CPU time 3.71 seconds
Started Jun 13 02:16:01 PM PDT 24
Finished Jun 13 02:16:06 PM PDT 24
Peak memory 205444 kb
Host smart-616c20c0-667a-4d77-b832-34bc52fc52d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065043568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1065043568
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3021524708
Short name T391
Test name
Test status
Simulation time 18563815117 ps
CPU time 56.81 seconds
Started Jun 13 02:15:52 PM PDT 24
Finished Jun 13 02:16:50 PM PDT 24
Peak memory 221704 kb
Host smart-0a6ee216-45cf-477d-ac5f-e47092cd0c89
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021524708 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3021524708
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4217507751
Short name T332
Test name
Test status
Simulation time 77071611 ps
CPU time 2.32 seconds
Started Jun 13 02:15:52 PM PDT 24
Finished Jun 13 02:15:55 PM PDT 24
Peak memory 213720 kb
Host smart-73bd2ec1-7bae-4042-b267-751699b9f109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217507751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4217507751
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.48370795
Short name T325
Test name
Test status
Simulation time 2596911198 ps
CPU time 10.15 seconds
Started Jun 13 02:15:51 PM PDT 24
Finished Jun 13 02:16:02 PM PDT 24
Peak memory 213720 kb
Host smart-4ee919f9-d5a6-4c8b-bf04-9204b9bdea60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48370795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.48370795
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.362176303
Short name T51
Test name
Test status
Simulation time 541365493 ps
CPU time 2.68 seconds
Started Jun 13 02:16:05 PM PDT 24
Finished Jun 13 02:16:09 PM PDT 24
Peak memory 221920 kb
Host smart-246d6848-2209-41ed-80db-847de6b7e319
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362176303 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.362176303
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.38792461
Short name T107
Test name
Test status
Simulation time 121760007 ps
CPU time 1.51 seconds
Started Jun 13 02:16:02 PM PDT 24
Finished Jun 13 02:16:05 PM PDT 24
Peak memory 213680 kb
Host smart-46590a69-edf5-459e-928e-8cae8782a269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38792461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.38792461
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2105323128
Short name T355
Test name
Test status
Simulation time 98923032 ps
CPU time 0.78 seconds
Started Jun 13 02:15:59 PM PDT 24
Finished Jun 13 02:16:01 PM PDT 24
Peak memory 205212 kb
Host smart-fbb48f5b-306e-4b0c-ae84-07cd27ce64bf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105323128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.2105323128
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4182950643
Short name T372
Test name
Test status
Simulation time 1377250827 ps
CPU time 3.99 seconds
Started Jun 13 02:15:58 PM PDT 24
Finished Jun 13 02:16:04 PM PDT 24
Peak memory 205412 kb
Host smart-72de1a2a-f073-465b-a65c-f5d524796656
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182950643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.4
182950643
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1938951862
Short name T285
Test name
Test status
Simulation time 286867086 ps
CPU time 0.85 seconds
Started Jun 13 02:16:01 PM PDT 24
Finished Jun 13 02:16:03 PM PDT 24
Peak memory 205216 kb
Host smart-3cc60ccf-48f8-4d5f-827d-40870a5ea697
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938951862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1
938951862
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3341655422
Short name T366
Test name
Test status
Simulation time 3131120403 ps
CPU time 8.54 seconds
Started Jun 13 02:16:03 PM PDT 24
Finished Jun 13 02:16:13 PM PDT 24
Peak memory 205592 kb
Host smart-c586d09c-803b-4a10-9b72-9d5632b2fab3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341655422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.3341655422
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1967620221
Short name T371
Test name
Test status
Simulation time 1000584691 ps
CPU time 5.56 seconds
Started Jun 13 02:16:01 PM PDT 24
Finished Jun 13 02:16:08 PM PDT 24
Peak memory 213736 kb
Host smart-cbea6a1c-daf0-4715-8222-20a631a550cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967620221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1967620221
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3643514711
Short name T125
Test name
Test status
Simulation time 4178115519 ps
CPU time 16.83 seconds
Started Jun 13 02:16:01 PM PDT 24
Finished Jun 13 02:16:19 PM PDT 24
Peak memory 213788 kb
Host smart-bfbb9294-fb71-4c81-86c5-ab44fe4edc30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643514711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3643514711
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.725935056
Short name T395
Test name
Test status
Simulation time 3389256026 ps
CPU time 5.99 seconds
Started Jun 13 02:16:08 PM PDT 24
Finished Jun 13 02:16:15 PM PDT 24
Peak memory 220408 kb
Host smart-437dfe5f-ddca-4ca3-a4cd-e6b6a4b48cc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725935056 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.725935056
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1912953385
Short name T105
Test name
Test status
Simulation time 123469378 ps
CPU time 1.56 seconds
Started Jun 13 02:15:59 PM PDT 24
Finished Jun 13 02:16:02 PM PDT 24
Peak memory 213656 kb
Host smart-fe58dd82-b153-4db2-a14d-6f214c6d58e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912953385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1912953385
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.764543659
Short name T296
Test name
Test status
Simulation time 4843146623 ps
CPU time 12.37 seconds
Started Jun 13 02:16:01 PM PDT 24
Finished Jun 13 02:16:14 PM PDT 24
Peak memory 205420 kb
Host smart-259cced0-81fd-41d2-b60c-dfc59739380f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764543659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r
v_dm_jtag_dmi_csr_bit_bash.764543659
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2985313081
Short name T357
Test name
Test status
Simulation time 2336149098 ps
CPU time 4.84 seconds
Started Jun 13 02:16:05 PM PDT 24
Finished Jun 13 02:16:11 PM PDT 24
Peak memory 205444 kb
Host smart-5151cdaa-101f-4201-8a59-b08cf661c486
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985313081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
985313081
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2968057312
Short name T394
Test name
Test status
Simulation time 580066934 ps
CPU time 1.2 seconds
Started Jun 13 02:15:59 PM PDT 24
Finished Jun 13 02:16:02 PM PDT 24
Peak memory 205200 kb
Host smart-2d616780-4b75-4e00-8016-2977c40e3a00
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968057312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
968057312
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2666418614
Short name T407
Test name
Test status
Simulation time 768535071 ps
CPU time 7.25 seconds
Started Jun 13 02:16:00 PM PDT 24
Finished Jun 13 02:16:08 PM PDT 24
Peak memory 205468 kb
Host smart-a8e4a171-9570-43f7-8b05-cbf994f2d5af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666418614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2666418614
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3212898595
Short name T367
Test name
Test status
Simulation time 42603532484 ps
CPU time 118.3 seconds
Started Jun 13 02:16:00 PM PDT 24
Finished Jun 13 02:18:00 PM PDT 24
Peak memory 221976 kb
Host smart-ed76969c-f3b8-4ad8-9bc7-8fdef9345ebd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212898595 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3212898595
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2436245617
Short name T384
Test name
Test status
Simulation time 122974835 ps
CPU time 3.29 seconds
Started Jun 13 02:15:59 PM PDT 24
Finished Jun 13 02:16:04 PM PDT 24
Peak memory 213640 kb
Host smart-39f35aed-e09e-4e32-8f30-758bb724854b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436245617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2436245617
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1519047938
Short name T74
Test name
Test status
Simulation time 2927415131 ps
CPU time 17.04 seconds
Started Jun 13 02:16:02 PM PDT 24
Finished Jun 13 02:16:21 PM PDT 24
Peak memory 213780 kb
Host smart-d66266f7-8249-475d-95b4-64036d22c63b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519047938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1519047938
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3281138448
Short name T175
Test name
Test status
Simulation time 122019146 ps
CPU time 0.72 seconds
Started Jun 13 02:47:14 PM PDT 24
Finished Jun 13 02:47:18 PM PDT 24
Peak memory 205116 kb
Host smart-3a759210-f91f-4e1f-80da-391d1cebff49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281138448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3281138448
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.199748095
Short name T207
Test name
Test status
Simulation time 13329132747 ps
CPU time 11.55 seconds
Started Jun 13 02:47:04 PM PDT 24
Finished Jun 13 02:47:22 PM PDT 24
Peak memory 213760 kb
Host smart-a23d9969-a9c2-4162-a344-79d8509a8bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199748095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.199748095
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.281183557
Short name T194
Test name
Test status
Simulation time 2743986842 ps
CPU time 6.53 seconds
Started Jun 13 02:46:58 PM PDT 24
Finished Jun 13 02:47:11 PM PDT 24
Peak memory 205580 kb
Host smart-9e87dd33-5bcb-410c-8023-a53d45782575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281183557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.281183557
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2504155870
Short name T12
Test name
Test status
Simulation time 9130935077 ps
CPU time 17.28 seconds
Started Jun 13 02:47:01 PM PDT 24
Finished Jun 13 02:47:25 PM PDT 24
Peak memory 205340 kb
Host smart-e257de8f-932e-4c4c-b2fa-8ad99b59425c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504155870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2504155870
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1744523435
Short name T69
Test name
Test status
Simulation time 3173887220 ps
CPU time 10.05 seconds
Started Jun 13 02:47:04 PM PDT 24
Finished Jun 13 02:47:21 PM PDT 24
Peak memory 205384 kb
Host smart-38787d19-6961-4fc8-9d2f-2ef707e1da68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744523435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1744523435
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2365736340
Short name T137
Test name
Test status
Simulation time 202193653 ps
CPU time 0.81 seconds
Started Jun 13 02:46:55 PM PDT 24
Finished Jun 13 02:47:03 PM PDT 24
Peak memory 205132 kb
Host smart-f6a2ecbd-9d2c-47ff-b52a-53657c9a494d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365736340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2365736340
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.431710946
Short name T28
Test name
Test status
Simulation time 2068640340 ps
CPU time 6.49 seconds
Started Jun 13 02:46:53 PM PDT 24
Finished Jun 13 02:47:07 PM PDT 24
Peak memory 205536 kb
Host smart-e67b5960-322b-427f-a6f2-fe0c36f5f33f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431710946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.431710946
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1931685280
Short name T76
Test name
Test status
Simulation time 413159321 ps
CPU time 1.21 seconds
Started Jun 13 02:47:15 PM PDT 24
Finished Jun 13 02:47:20 PM PDT 24
Peak memory 205096 kb
Host smart-ab178327-6875-438d-923b-67df8e6a4f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931685280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1931685280
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2660509205
Short name T244
Test name
Test status
Simulation time 814831878 ps
CPU time 1.72 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:40 PM PDT 24
Peak memory 205044 kb
Host smart-2e4325ee-7aec-4226-a2aa-a1b7fc2b27cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660509205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2660509205
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1607400235
Short name T249
Test name
Test status
Simulation time 835912798 ps
CPU time 1.86 seconds
Started Jun 13 02:47:05 PM PDT 24
Finished Jun 13 02:47:13 PM PDT 24
Peak memory 204984 kb
Host smart-4350bd87-591a-4b4c-bec6-375cd684b003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607400235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1607400235
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1542793425
Short name T230
Test name
Test status
Simulation time 597152188 ps
CPU time 1.17 seconds
Started Jun 13 02:47:02 PM PDT 24
Finished Jun 13 02:47:10 PM PDT 24
Peak memory 204996 kb
Host smart-3e352285-a479-458d-b33a-6e3eca8af147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542793425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1542793425
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2895337676
Short name T256
Test name
Test status
Simulation time 363422471 ps
CPU time 1.14 seconds
Started Jun 13 02:47:29 PM PDT 24
Finished Jun 13 02:47:40 PM PDT 24
Peak memory 205044 kb
Host smart-e494c73d-d1f5-4df5-96ca-cce67c351e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895337676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2895337676
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2102574136
Short name T141
Test name
Test status
Simulation time 340810365 ps
CPU time 0.9 seconds
Started Jun 13 02:46:59 PM PDT 24
Finished Jun 13 02:47:07 PM PDT 24
Peak memory 205168 kb
Host smart-94c64dce-9e45-4e4b-9cd3-dfa5b110dfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102574136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2102574136
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1384560141
Short name T8
Test name
Test status
Simulation time 1941872742 ps
CPU time 3.01 seconds
Started Jun 13 02:47:05 PM PDT 24
Finished Jun 13 02:47:15 PM PDT 24
Peak memory 205136 kb
Host smart-6299df8e-8b43-4ac8-924a-ed0837d6263c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384560141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1384560141
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3075895005
Short name T18
Test name
Test status
Simulation time 4437471142 ps
CPU time 11.88 seconds
Started Jun 13 02:47:08 PM PDT 24
Finished Jun 13 02:47:26 PM PDT 24
Peak memory 205352 kb
Host smart-5c6dc7e8-df99-4ada-b504-b8453c412fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075895005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3075895005
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1257317584
Short name T187
Test name
Test status
Simulation time 3009199399 ps
CPU time 2.69 seconds
Started Jun 13 02:46:52 PM PDT 24
Finished Jun 13 02:47:03 PM PDT 24
Peak memory 205588 kb
Host smart-9a501eca-4ea8-4fec-906b-a348c144eb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257317584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1257317584
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.446803393
Short name T57
Test name
Test status
Simulation time 639407668 ps
CPU time 1.25 seconds
Started Jun 13 02:47:02 PM PDT 24
Finished Jun 13 02:47:10 PM PDT 24
Peak memory 236620 kb
Host smart-c354f6e9-92bb-4201-a7f2-c595223fea9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446803393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.446803393
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2995200565
Short name T233
Test name
Test status
Simulation time 481073243 ps
CPU time 1.39 seconds
Started Jun 13 02:47:09 PM PDT 24
Finished Jun 13 02:47:17 PM PDT 24
Peak memory 204996 kb
Host smart-7f1d45a2-5525-4acb-89a5-e9ae0f629f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995200565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2995200565
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2195196103
Short name T23
Test name
Test status
Simulation time 12502478242 ps
CPU time 27.27 seconds
Started Jun 13 02:47:00 PM PDT 24
Finished Jun 13 02:47:35 PM PDT 24
Peak memory 205360 kb
Host smart-8632b20e-70bb-4223-b961-86e2150e6d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195196103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2195196103
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3693418368
Short name T41
Test name
Test status
Simulation time 283508993 ps
CPU time 1.46 seconds
Started Jun 13 02:47:24 PM PDT 24
Finished Jun 13 02:47:29 PM PDT 24
Peak memory 205172 kb
Host smart-2dc8710c-4f1c-44ee-91b9-759cb59c6916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693418368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3693418368
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.693143004
Short name T164
Test name
Test status
Simulation time 45101901 ps
CPU time 0.8 seconds
Started Jun 13 02:47:05 PM PDT 24
Finished Jun 13 02:47:12 PM PDT 24
Peak memory 205080 kb
Host smart-2b2c0037-4a2e-459d-8675-56affb9463d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693143004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.693143004
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2333957719
Short name T222
Test name
Test status
Simulation time 3871250028 ps
CPU time 2.91 seconds
Started Jun 13 02:47:04 PM PDT 24
Finished Jun 13 02:47:13 PM PDT 24
Peak memory 205508 kb
Host smart-9ae0441b-6863-4d29-879d-79da06277ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333957719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2333957719
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3394177340
Short name T218
Test name
Test status
Simulation time 32708941348 ps
CPU time 24 seconds
Started Jun 13 02:46:58 PM PDT 24
Finished Jun 13 02:47:29 PM PDT 24
Peak memory 205380 kb
Host smart-45cb34b8-c0c8-44b7-9c33-4f39d141f5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394177340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3394177340
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2936109035
Short name T5
Test name
Test status
Simulation time 3958234521 ps
CPU time 11.07 seconds
Started Jun 13 02:47:19 PM PDT 24
Finished Jun 13 02:47:33 PM PDT 24
Peak memory 205364 kb
Host smart-2cf6db9f-4a62-49f4-9cd3-fc3f32c13cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936109035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2936109035
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1790228984
Short name T30
Test name
Test status
Simulation time 2288470192 ps
CPU time 3.42 seconds
Started Jun 13 02:47:09 PM PDT 24
Finished Jun 13 02:47:23 PM PDT 24
Peak memory 205056 kb
Host smart-a643beac-648a-489d-b0c1-1b6eb0e664e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790228984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1790228984
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3775908881
Short name T7
Test name
Test status
Simulation time 12942556087 ps
CPU time 22.39 seconds
Started Jun 13 02:47:09 PM PDT 24
Finished Jun 13 02:47:37 PM PDT 24
Peak memory 205444 kb
Host smart-2bfe3e22-7ea7-4631-9366-cd2262d20b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775908881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3775908881
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1092120358
Short name T257
Test name
Test status
Simulation time 291465471 ps
CPU time 1.11 seconds
Started Jun 13 02:47:15 PM PDT 24
Finished Jun 13 02:47:20 PM PDT 24
Peak memory 205160 kb
Host smart-dfafdf17-619a-4bdf-9eb3-bb241153d451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092120358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1092120358
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3821324923
Short name T253
Test name
Test status
Simulation time 2133931649 ps
CPU time 2.06 seconds
Started Jun 13 02:47:03 PM PDT 24
Finished Jun 13 02:47:12 PM PDT 24
Peak memory 205496 kb
Host smart-6e6cc9c1-9391-496f-b63f-fdb2d18e1c2d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821324923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3821324923
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.802894456
Short name T32
Test name
Test status
Simulation time 2454983573 ps
CPU time 3 seconds
Started Jun 13 02:47:01 PM PDT 24
Finished Jun 13 02:47:12 PM PDT 24
Peak memory 205180 kb
Host smart-a9a6fc09-bb9f-466f-935e-dbcec5608ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802894456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.802894456
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.4056055298
Short name T245
Test name
Test status
Simulation time 206201588 ps
CPU time 0.95 seconds
Started Jun 13 02:47:21 PM PDT 24
Finished Jun 13 02:47:24 PM PDT 24
Peak memory 204988 kb
Host smart-cee57ee3-fa3b-40b8-aaf1-2ba94e46fc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056055298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.4056055298
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2375987705
Short name T210
Test name
Test status
Simulation time 1786354781 ps
CPU time 3.47 seconds
Started Jun 13 02:47:04 PM PDT 24
Finished Jun 13 02:47:14 PM PDT 24
Peak memory 204996 kb
Host smart-90754779-c3fc-4286-b8a0-c2d85a4bc470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375987705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2375987705
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2528945752
Short name T221
Test name
Test status
Simulation time 2701477461 ps
CPU time 7.31 seconds
Started Jun 13 02:47:14 PM PDT 24
Finished Jun 13 02:47:25 PM PDT 24
Peak memory 205048 kb
Host smart-fd94ab6a-c434-47e6-ac40-f50f8b94d95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528945752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2528945752
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3612375480
Short name T10
Test name
Test status
Simulation time 1367919332 ps
CPU time 1.58 seconds
Started Jun 13 02:47:04 PM PDT 24
Finished Jun 13 02:47:13 PM PDT 24
Peak memory 204996 kb
Host smart-76f42f4a-522a-40ad-8b74-c01aec49bc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612375480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3612375480
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2186245898
Short name T213
Test name
Test status
Simulation time 100733427 ps
CPU time 0.97 seconds
Started Jun 13 02:47:13 PM PDT 24
Finished Jun 13 02:47:18 PM PDT 24
Peak memory 205008 kb
Host smart-f9b4e592-19f8-42dd-a7cc-583d1a6a139c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186245898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2186245898
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.40174653
Short name T199
Test name
Test status
Simulation time 306892074 ps
CPU time 1.46 seconds
Started Jun 13 02:47:02 PM PDT 24
Finished Jun 13 02:47:10 PM PDT 24
Peak memory 205084 kb
Host smart-629fa4d5-81cc-404e-9031-1b7bb46f6c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40174653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.40174653
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2589252650
Short name T138
Test name
Test status
Simulation time 4209743707 ps
CPU time 12.11 seconds
Started Jun 13 02:47:09 PM PDT 24
Finished Jun 13 02:47:27 PM PDT 24
Peak memory 205440 kb
Host smart-a86a79de-c9f8-4544-b577-eb97176e76ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589252650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2589252650
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2418973541
Short name T142
Test name
Test status
Simulation time 2683746313 ps
CPU time 7.82 seconds
Started Jun 13 02:47:03 PM PDT 24
Finished Jun 13 02:47:18 PM PDT 24
Peak memory 205356 kb
Host smart-2ecfcbd8-9b61-4d54-8ff7-1466efb34093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418973541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2418973541
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.356701174
Short name T36
Test name
Test status
Simulation time 2393159843 ps
CPU time 4.02 seconds
Started Jun 13 02:47:14 PM PDT 24
Finished Jun 13 02:47:22 PM PDT 24
Peak memory 205388 kb
Host smart-98583036-893c-4eff-be0f-3a9241465b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356701174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.356701174
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.451688036
Short name T39
Test name
Test status
Simulation time 1053934947 ps
CPU time 3.26 seconds
Started Jun 13 02:47:14 PM PDT 24
Finished Jun 13 02:47:22 PM PDT 24
Peak memory 205124 kb
Host smart-ab3538ea-6d8b-4242-9aa0-8950b355d1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451688036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.451688036
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.710332152
Short name T4
Test name
Test status
Simulation time 54882033 ps
CPU time 0.81 seconds
Started Jun 13 02:47:05 PM PDT 24
Finished Jun 13 02:47:12 PM PDT 24
Peak memory 213320 kb
Host smart-6efaa8dc-e93e-41d2-8c08-9a0116899e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710332152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.710332152
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3095878574
Short name T206
Test name
Test status
Simulation time 10069567504 ps
CPU time 7.85 seconds
Started Jun 13 02:47:16 PM PDT 24
Finished Jun 13 02:47:27 PM PDT 24
Peak memory 205556 kb
Host smart-d70ca51e-83e2-4b49-9988-a4d55f88b791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095878574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3095878574
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3039656831
Short name T22
Test name
Test status
Simulation time 1341725660 ps
CPU time 1.97 seconds
Started Jun 13 02:47:02 PM PDT 24
Finished Jun 13 02:47:11 PM PDT 24
Peak memory 204996 kb
Host smart-32d885e6-4c83-4c26-8eb8-ca9720f8145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039656831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3039656831
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1064557988
Short name T26
Test name
Test status
Simulation time 105340552 ps
CPU time 0.72 seconds
Started Jun 13 02:47:25 PM PDT 24
Finished Jun 13 02:47:29 PM PDT 24
Peak memory 205144 kb
Host smart-3d428733-53dd-486b-a42b-e10e7d6688c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064557988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1064557988
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2744884250
Short name T192
Test name
Test status
Simulation time 1886602966 ps
CPU time 6.69 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:43 PM PDT 24
Peak memory 205492 kb
Host smart-f1f836ed-7a64-4d0c-b078-b31d3c38a2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744884250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2744884250
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3072177502
Short name T235
Test name
Test status
Simulation time 1150824755 ps
CPU time 4.04 seconds
Started Jun 13 02:47:23 PM PDT 24
Finished Jun 13 02:47:30 PM PDT 24
Peak memory 205504 kb
Host smart-39aca81b-a351-44b3-b508-bdbf3771b928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072177502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3072177502
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3795233253
Short name T183
Test name
Test status
Simulation time 3026331844 ps
CPU time 4.03 seconds
Started Jun 13 02:47:17 PM PDT 24
Finished Jun 13 02:47:24 PM PDT 24
Peak memory 205552 kb
Host smart-38a5aedb-cd38-4ff9-98f5-83befd9cb7dc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795233253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3795233253
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.2657529508
Short name T54
Test name
Test status
Simulation time 2181947675 ps
CPU time 6.55 seconds
Started Jun 13 02:47:31 PM PDT 24
Finished Jun 13 02:47:49 PM PDT 24
Peak memory 205544 kb
Host smart-1d6346a8-49ab-4246-98ab-468b42a1825c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657529508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2657529508
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2591295248
Short name T166
Test name
Test status
Simulation time 89267623 ps
CPU time 0.77 seconds
Started Jun 13 02:47:27 PM PDT 24
Finished Jun 13 02:47:37 PM PDT 24
Peak memory 205148 kb
Host smart-b2c881ae-9e64-4207-a158-314bca38b77f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591295248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2591295248
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3375945198
Short name T254
Test name
Test status
Simulation time 11609923624 ps
CPU time 9.83 seconds
Started Jun 13 02:47:23 PM PDT 24
Finished Jun 13 02:47:37 PM PDT 24
Peak memory 213828 kb
Host smart-76bfdf87-9dba-4c9f-b486-864e960d44f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375945198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3375945198
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3591461229
Short name T260
Test name
Test status
Simulation time 3749832314 ps
CPU time 12.08 seconds
Started Jun 13 02:47:37 PM PDT 24
Finished Jun 13 02:48:00 PM PDT 24
Peak memory 205444 kb
Host smart-f305b27b-4b7a-493f-8f62-9666861616cf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591461229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3591461229
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3127194312
Short name T211
Test name
Test status
Simulation time 2508205590 ps
CPU time 2.6 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:38 PM PDT 24
Peak memory 205540 kb
Host smart-7864c85d-58fb-4752-aed0-9b168c966827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127194312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3127194312
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2323348904
Short name T58
Test name
Test status
Simulation time 43037754 ps
CPU time 0.78 seconds
Started Jun 13 02:47:22 PM PDT 24
Finished Jun 13 02:47:25 PM PDT 24
Peak memory 205132 kb
Host smart-444e8308-6446-4cfc-b81b-d7e6bc80745f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323348904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2323348904
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.540571248
Short name T212
Test name
Test status
Simulation time 29415985806 ps
CPU time 36.48 seconds
Started Jun 13 02:47:26 PM PDT 24
Finished Jun 13 02:48:08 PM PDT 24
Peak memory 214000 kb
Host smart-e6824305-c642-41d8-b47f-49a68bdac938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540571248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.540571248
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.884715248
Short name T197
Test name
Test status
Simulation time 1166526082 ps
CPU time 3.29 seconds
Started Jun 13 02:47:33 PM PDT 24
Finished Jun 13 02:47:49 PM PDT 24
Peak memory 205568 kb
Host smart-b9fecc8c-7fe4-468a-b824-97bad108c7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884715248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.884715248
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2176906093
Short name T259
Test name
Test status
Simulation time 3177949316 ps
CPU time 10.03 seconds
Started Jun 13 02:47:24 PM PDT 24
Finished Jun 13 02:47:38 PM PDT 24
Peak memory 205708 kb
Host smart-a95df27d-4502-48bf-b274-f09fb4365b57
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2176906093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2176906093
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.1084207829
Short name T196
Test name
Test status
Simulation time 6568621422 ps
CPU time 18.05 seconds
Started Jun 13 02:47:26 PM PDT 24
Finished Jun 13 02:47:48 PM PDT 24
Peak memory 205592 kb
Host smart-100d840e-c5f5-47ff-94d8-ab7239c0ce67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084207829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1084207829
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1282200635
Short name T156
Test name
Test status
Simulation time 98653385 ps
CPU time 0.85 seconds
Started Jun 13 02:47:26 PM PDT 24
Finished Jun 13 02:47:32 PM PDT 24
Peak memory 205148 kb
Host smart-769b425e-a195-49c4-8a63-13ba1b523045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282200635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1282200635
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.4050017596
Short name T205
Test name
Test status
Simulation time 143591212684 ps
CPU time 385.92 seconds
Started Jun 13 02:47:29 PM PDT 24
Finished Jun 13 02:54:06 PM PDT 24
Peak memory 221888 kb
Host smart-aaf180c1-850c-48dd-8fcf-454ea5b785da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050017596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.4050017596
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.924294571
Short name T242
Test name
Test status
Simulation time 7896730908 ps
CPU time 6.26 seconds
Started Jun 13 02:47:30 PM PDT 24
Finished Jun 13 02:47:47 PM PDT 24
Peak memory 213736 kb
Host smart-243523f4-1958-4be1-b5ef-58056a08f543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924294571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.924294571
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.929912771
Short name T231
Test name
Test status
Simulation time 6254458194 ps
CPU time 6.02 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:42 PM PDT 24
Peak memory 205528 kb
Host smart-c444c19d-09ab-4375-8f3b-09758e5e88c5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929912771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.929912771
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1415061557
Short name T228
Test name
Test status
Simulation time 15398505260 ps
CPU time 44.42 seconds
Started Jun 13 02:47:25 PM PDT 24
Finished Jun 13 02:48:13 PM PDT 24
Peak memory 205484 kb
Host smart-cd52d3ab-9eb0-40ad-8d79-eeeced9c2308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415061557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1415061557
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.875273287
Short name T209
Test name
Test status
Simulation time 8222121825 ps
CPU time 9.52 seconds
Started Jun 13 02:47:26 PM PDT 24
Finished Jun 13 02:47:40 PM PDT 24
Peak memory 213644 kb
Host smart-442c3d64-78fd-41ad-9c5c-d118a782604e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875273287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.875273287
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2610015645
Short name T234
Test name
Test status
Simulation time 817393231 ps
CPU time 1.81 seconds
Started Jun 13 02:47:34 PM PDT 24
Finished Jun 13 02:47:48 PM PDT 24
Peak memory 205464 kb
Host smart-470e5568-de07-4824-b59c-a6df60439923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610015645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2610015645
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.218459830
Short name T203
Test name
Test status
Simulation time 1123783529 ps
CPU time 2.26 seconds
Started Jun 13 02:47:23 PM PDT 24
Finished Jun 13 02:47:28 PM PDT 24
Peak memory 205488 kb
Host smart-d1d2d963-b3e2-4b24-9495-cd070f34f50b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=218459830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.218459830
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1566839890
Short name T193
Test name
Test status
Simulation time 12560051328 ps
CPU time 6.74 seconds
Started Jun 13 02:47:23 PM PDT 24
Finished Jun 13 02:47:33 PM PDT 24
Peak memory 205516 kb
Host smart-12eda0fb-8a55-48d4-8f6d-4bf2b1186a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566839890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1566839890
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1772652228
Short name T117
Test name
Test status
Simulation time 106169952 ps
CPU time 0.8 seconds
Started Jun 13 02:47:36 PM PDT 24
Finished Jun 13 02:47:48 PM PDT 24
Peak memory 205132 kb
Host smart-8f623693-1448-4830-b928-8b2886e3a416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772652228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1772652228
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3652790940
Short name T237
Test name
Test status
Simulation time 3630158448 ps
CPU time 1.51 seconds
Started Jun 13 02:47:25 PM PDT 24
Finished Jun 13 02:47:31 PM PDT 24
Peak memory 205608 kb
Host smart-b3dc91c0-8354-4768-816a-94012a59d47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652790940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3652790940
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.629094414
Short name T179
Test name
Test status
Simulation time 1072368024 ps
CPU time 1.38 seconds
Started Jun 13 02:47:22 PM PDT 24
Finished Jun 13 02:47:26 PM PDT 24
Peak memory 205524 kb
Host smart-f91079b4-13f6-419e-90a6-05ad87c621a6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=629094414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.629094414
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2613271560
Short name T258
Test name
Test status
Simulation time 2393321138 ps
CPU time 2.8 seconds
Started Jun 13 02:47:33 PM PDT 24
Finished Jun 13 02:47:49 PM PDT 24
Peak memory 205512 kb
Host smart-f4adca0d-ba3b-44ca-9638-7b3e692126ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613271560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2613271560
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.273931909
Short name T160
Test name
Test status
Simulation time 49295383 ps
CPU time 0.71 seconds
Started Jun 13 02:47:27 PM PDT 24
Finished Jun 13 02:47:33 PM PDT 24
Peak memory 205148 kb
Host smart-984139bf-49b7-44fb-852f-056378500b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273931909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.273931909
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2457897699
Short name T21
Test name
Test status
Simulation time 34680609948 ps
CPU time 83.69 seconds
Started Jun 13 02:47:27 PM PDT 24
Finished Jun 13 02:48:57 PM PDT 24
Peak memory 213776 kb
Host smart-7c55f7a6-f463-42b5-ab6b-c16d7b60c2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457897699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2457897699
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1875592414
Short name T223
Test name
Test status
Simulation time 6463434673 ps
CPU time 18.7 seconds
Started Jun 13 02:47:27 PM PDT 24
Finished Jun 13 02:47:54 PM PDT 24
Peak memory 215172 kb
Host smart-06e7c3a3-b014-428a-89fa-b081895577b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875592414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1875592414
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2696709489
Short name T241
Test name
Test status
Simulation time 5193177265 ps
CPU time 2.74 seconds
Started Jun 13 02:47:38 PM PDT 24
Finished Jun 13 02:48:00 PM PDT 24
Peak memory 205588 kb
Host smart-7a24c167-87a7-4fb9-a7a9-42515854a677
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2696709489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2696709489
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1109948304
Short name T89
Test name
Test status
Simulation time 2389850506 ps
CPU time 7.36 seconds
Started Jun 13 02:47:34 PM PDT 24
Finished Jun 13 02:47:54 PM PDT 24
Peak memory 205556 kb
Host smart-19d41f30-c830-4a05-b118-13d926ca3e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109948304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1109948304
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.3341810297
Short name T34
Test name
Test status
Simulation time 19678752545 ps
CPU time 53.42 seconds
Started Jun 13 02:47:22 PM PDT 24
Finished Jun 13 02:48:18 PM PDT 24
Peak memory 213564 kb
Host smart-16e870e2-dae5-4f3c-b0c9-110594d49f13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341810297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3341810297
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.443837744
Short name T151
Test name
Test status
Simulation time 59365564 ps
CPU time 0.81 seconds
Started Jun 13 02:47:24 PM PDT 24
Finished Jun 13 02:47:29 PM PDT 24
Peak memory 205108 kb
Host smart-c7813129-77ae-4ac5-8a7d-07e90f864740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443837744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.443837744
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3057018390
Short name T14
Test name
Test status
Simulation time 2717026599 ps
CPU time 7.77 seconds
Started Jun 13 02:47:29 PM PDT 24
Finished Jun 13 02:47:48 PM PDT 24
Peak memory 205520 kb
Host smart-446bd1df-6606-4eae-a93a-a9544fb97990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057018390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3057018390
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2754569990
Short name T216
Test name
Test status
Simulation time 1694122413 ps
CPU time 3.31 seconds
Started Jun 13 02:47:17 PM PDT 24
Finished Jun 13 02:47:23 PM PDT 24
Peak memory 205484 kb
Host smart-96aede4b-a5d6-41c2-8d4c-5d458e23d2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754569990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2754569990
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.841173505
Short name T240
Test name
Test status
Simulation time 4989577546 ps
CPU time 13.75 seconds
Started Jun 13 02:47:32 PM PDT 24
Finished Jun 13 02:47:58 PM PDT 24
Peak memory 205560 kb
Host smart-4a2114dc-f60a-445d-831c-bad91814427c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841173505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.841173505
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.4249726678
Short name T238
Test name
Test status
Simulation time 7188235700 ps
CPU time 9.96 seconds
Started Jun 13 02:47:20 PM PDT 24
Finished Jun 13 02:47:33 PM PDT 24
Peak memory 205540 kb
Host smart-0dd51ee1-5b82-4299-9670-b64315a84159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249726678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.4249726678
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3745734333
Short name T27
Test name
Test status
Simulation time 66319354 ps
CPU time 0.75 seconds
Started Jun 13 02:47:40 PM PDT 24
Finished Jun 13 02:47:53 PM PDT 24
Peak memory 205116 kb
Host smart-6a41b2c6-daaa-4599-ba9c-360edef1eff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745734333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3745734333
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3841893596
Short name T243
Test name
Test status
Simulation time 1592037967 ps
CPU time 2.33 seconds
Started Jun 13 02:47:25 PM PDT 24
Finished Jun 13 02:47:32 PM PDT 24
Peak memory 205488 kb
Host smart-fb8c362b-dfda-434d-afa7-6ac0f2c01f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841893596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3841893596
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1325371044
Short name T16
Test name
Test status
Simulation time 6313992740 ps
CPU time 16.31 seconds
Started Jun 13 02:47:30 PM PDT 24
Finished Jun 13 02:47:57 PM PDT 24
Peak memory 205556 kb
Host smart-f7b092e0-d3e1-4e1d-8b19-d2321e36dfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325371044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1325371044
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2901061410
Short name T188
Test name
Test status
Simulation time 3279193773 ps
CPU time 3.47 seconds
Started Jun 13 02:47:37 PM PDT 24
Finished Jun 13 02:47:52 PM PDT 24
Peak memory 205524 kb
Host smart-39b9c8fc-90a5-4762-a4d3-1fdd9daea2c0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901061410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2901061410
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.2948053914
Short name T247
Test name
Test status
Simulation time 1051017090 ps
CPU time 3.5 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:40 PM PDT 24
Peak memory 205468 kb
Host smart-3c503b6c-7eac-454f-bd9d-05cd93f8e873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948053914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2948053914
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.487834556
Short name T25
Test name
Test status
Simulation time 43300517 ps
CPU time 0.7 seconds
Started Jun 13 02:47:26 PM PDT 24
Finished Jun 13 02:47:32 PM PDT 24
Peak memory 205148 kb
Host smart-540b264d-83d2-405e-8bb8-5a96c3423332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487834556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.487834556
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2409531624
Short name T248
Test name
Test status
Simulation time 41824644859 ps
CPU time 56.92 seconds
Started Jun 13 02:47:35 PM PDT 24
Finished Jun 13 02:48:43 PM PDT 24
Peak memory 213784 kb
Host smart-3cccf513-c622-477b-96a5-0b54874740e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409531624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2409531624
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3009953113
Short name T191
Test name
Test status
Simulation time 1604734284 ps
CPU time 5.18 seconds
Started Jun 13 02:47:32 PM PDT 24
Finished Jun 13 02:47:49 PM PDT 24
Peak memory 205440 kb
Host smart-48a8f127-1f08-45af-93fd-cd3a3976139f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009953113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3009953113
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.922140330
Short name T214
Test name
Test status
Simulation time 8128260641 ps
CPU time 9.45 seconds
Started Jun 13 02:47:26 PM PDT 24
Finished Jun 13 02:47:41 PM PDT 24
Peak memory 205532 kb
Host smart-777cd10f-32eb-4d75-a9e0-68df0640aeed
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=922140330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.922140330
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3358898500
Short name T15
Test name
Test status
Simulation time 5226881049 ps
CPU time 8.25 seconds
Started Jun 13 02:47:33 PM PDT 24
Finished Jun 13 02:47:54 PM PDT 24
Peak memory 205508 kb
Host smart-8bdb7cea-ab81-402b-a2e4-c6777bfad01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358898500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3358898500
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.795382697
Short name T176
Test name
Test status
Simulation time 137295458 ps
CPU time 0.73 seconds
Started Jun 13 02:47:08 PM PDT 24
Finished Jun 13 02:47:15 PM PDT 24
Peak memory 205188 kb
Host smart-130fd234-8f7d-4225-9f0e-d33bb7a147bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795382697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.795382697
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3628543200
Short name T225
Test name
Test status
Simulation time 40993946607 ps
CPU time 61.87 seconds
Started Jun 13 02:47:13 PM PDT 24
Finished Jun 13 02:48:19 PM PDT 24
Peak memory 213788 kb
Host smart-a9bde202-3993-434b-bd0f-f39c1026f7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628543200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3628543200
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.268908705
Short name T224
Test name
Test status
Simulation time 3974252231 ps
CPU time 4.03 seconds
Started Jun 13 02:47:03 PM PDT 24
Finished Jun 13 02:47:14 PM PDT 24
Peak memory 205600 kb
Host smart-030c4c32-ae70-404a-96e7-f491b5c48dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268908705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.268908705
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3682011542
Short name T182
Test name
Test status
Simulation time 2188375872 ps
CPU time 7.28 seconds
Started Jun 13 02:47:12 PM PDT 24
Finished Jun 13 02:47:24 PM PDT 24
Peak memory 205604 kb
Host smart-7612b1af-0617-4d96-ac27-e8913d873825
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3682011542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3682011542
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.583438806
Short name T217
Test name
Test status
Simulation time 266647853 ps
CPU time 1.27 seconds
Started Jun 13 02:47:06 PM PDT 24
Finished Jun 13 02:47:13 PM PDT 24
Peak memory 205032 kb
Host smart-0dc152d6-1271-4550-8177-0717cd777a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583438806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.583438806
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.198407666
Short name T190
Test name
Test status
Simulation time 12073443664 ps
CPU time 16.21 seconds
Started Jun 13 02:47:14 PM PDT 24
Finished Jun 13 02:47:34 PM PDT 24
Peak memory 205632 kb
Host smart-2c5a035c-c41a-472b-b065-597646ddc65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198407666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.198407666
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.891483087
Short name T56
Test name
Test status
Simulation time 777146389 ps
CPU time 2.02 seconds
Started Jun 13 02:47:08 PM PDT 24
Finished Jun 13 02:47:17 PM PDT 24
Peak memory 237348 kb
Host smart-f28b61b5-dca2-4814-9ab2-81871d9088f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891483087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.891483087
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.3208537184
Short name T6
Test name
Test status
Simulation time 9309247952 ps
CPU time 7.24 seconds
Started Jun 13 02:47:17 PM PDT 24
Finished Jun 13 02:47:28 PM PDT 24
Peak memory 205440 kb
Host smart-e052eb83-c639-4be0-b3de-18025d6443f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208537184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3208537184
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.4145343224
Short name T163
Test name
Test status
Simulation time 118354960 ps
CPU time 0.87 seconds
Started Jun 13 02:47:29 PM PDT 24
Finished Jun 13 02:47:41 PM PDT 24
Peak memory 205116 kb
Host smart-2a88ae8d-f3e5-4f29-8e66-f8097dbdd2a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145343224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.4145343224
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.828111119
Short name T169
Test name
Test status
Simulation time 68475841 ps
CPU time 0.71 seconds
Started Jun 13 02:47:26 PM PDT 24
Finished Jun 13 02:47:33 PM PDT 24
Peak memory 205128 kb
Host smart-c9b9feab-eb58-4fc9-b933-bd69ae269ab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828111119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.828111119
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3728171112
Short name T262
Test name
Test status
Simulation time 57194341 ps
CPU time 0.8 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:39 PM PDT 24
Peak memory 205132 kb
Host smart-a4fcc7bf-e38b-4ce5-a5a2-abcb3d94548f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728171112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3728171112
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.4226709342
Short name T134
Test name
Test status
Simulation time 14568797629 ps
CPU time 4.23 seconds
Started Jun 13 02:47:29 PM PDT 24
Finished Jun 13 02:47:44 PM PDT 24
Peak memory 205388 kb
Host smart-4644484e-c3b4-4a27-9789-c415cae894d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226709342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.4226709342
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3034582975
Short name T168
Test name
Test status
Simulation time 164221147 ps
CPU time 0.73 seconds
Started Jun 13 02:47:33 PM PDT 24
Finished Jun 13 02:47:45 PM PDT 24
Peak memory 205132 kb
Host smart-e424453d-7877-4910-9c90-36822670429e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034582975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3034582975
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.1481864092
Short name T48
Test name
Test status
Simulation time 24776743684 ps
CPU time 21.9 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:59 PM PDT 24
Peak memory 205444 kb
Host smart-d7592b2b-3403-459c-88e5-40553256b98b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481864092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1481864092
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1215910970
Short name T153
Test name
Test status
Simulation time 65666059 ps
CPU time 0.75 seconds
Started Jun 13 02:47:31 PM PDT 24
Finished Jun 13 02:47:43 PM PDT 24
Peak memory 205120 kb
Host smart-8c7edca3-2094-4d60-94a0-e00563c7a730
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215910970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1215910970
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2724348671
Short name T165
Test name
Test status
Simulation time 114973060 ps
CPU time 0.76 seconds
Started Jun 13 02:47:30 PM PDT 24
Finished Jun 13 02:47:43 PM PDT 24
Peak memory 205144 kb
Host smart-f4c3d88e-3b1b-4300-ac01-bb270e3afc2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724348671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2724348671
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.1015075000
Short name T20
Test name
Test status
Simulation time 46051889824 ps
CPU time 38.59 seconds
Started Jun 13 02:47:46 PM PDT 24
Finished Jun 13 02:48:38 PM PDT 24
Peak memory 205412 kb
Host smart-3d0e3abc-960d-42c9-aa3b-b78c3db88b35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015075000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1015075000
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2331268984
Short name T120
Test name
Test status
Simulation time 62620126 ps
CPU time 0.83 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:37 PM PDT 24
Peak memory 205136 kb
Host smart-4f6fd334-88dd-4fc6-86c1-82bd33c6059d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331268984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2331268984
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.530166621
Short name T250
Test name
Test status
Simulation time 92666317 ps
CPU time 0.79 seconds
Started Jun 13 02:47:37 PM PDT 24
Finished Jun 13 02:47:50 PM PDT 24
Peak memory 205108 kb
Host smart-3e437685-b295-41aa-b6a7-85740b4d2ca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530166621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.530166621
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.4214290028
Short name T172
Test name
Test status
Simulation time 53199146 ps
CPU time 0.79 seconds
Started Jun 13 02:47:46 PM PDT 24
Finished Jun 13 02:48:01 PM PDT 24
Peak memory 205076 kb
Host smart-28757690-6fff-4f76-beef-56d9faf88741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214290028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.4214290028
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.81920531
Short name T145
Test name
Test status
Simulation time 54318799 ps
CPU time 0.75 seconds
Started Jun 13 02:47:24 PM PDT 24
Finished Jun 13 02:47:29 PM PDT 24
Peak memory 205136 kb
Host smart-9c75d9d4-acd8-4c0d-9389-21a608e75279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81920531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.81920531
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.802755467
Short name T252
Test name
Test status
Simulation time 7602198756 ps
CPU time 6.96 seconds
Started Jun 13 02:47:17 PM PDT 24
Finished Jun 13 02:47:28 PM PDT 24
Peak memory 205540 kb
Host smart-cecfe360-ec1c-43aa-ba2f-1a1aa3e37c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802755467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.802755467
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.4183487543
Short name T232
Test name
Test status
Simulation time 4117674517 ps
CPU time 6.29 seconds
Started Jun 13 02:47:21 PM PDT 24
Finished Jun 13 02:47:30 PM PDT 24
Peak memory 205560 kb
Host smart-5da3642c-690c-4e42-ad48-74ef129040c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183487543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.4183487543
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.418519663
Short name T220
Test name
Test status
Simulation time 4813256060 ps
CPU time 7.07 seconds
Started Jun 13 02:47:16 PM PDT 24
Finished Jun 13 02:47:27 PM PDT 24
Peak memory 205524 kb
Host smart-d943a64b-9acf-4c8b-8cfd-6da23e1101f7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=418519663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.418519663
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3764087383
Short name T236
Test name
Test status
Simulation time 338542657 ps
CPU time 1.11 seconds
Started Jun 13 02:47:14 PM PDT 24
Finished Jun 13 02:47:19 PM PDT 24
Peak memory 205020 kb
Host smart-ea05c1aa-f580-4091-85fa-7968efe3cd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764087383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3764087383
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1980943638
Short name T180
Test name
Test status
Simulation time 4232478722 ps
CPU time 4.23 seconds
Started Jun 13 02:47:16 PM PDT 24
Finished Jun 13 02:47:24 PM PDT 24
Peak memory 205588 kb
Host smart-bbe93b30-c587-43fb-836f-f35a3ace0ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980943638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1980943638
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.80984043
Short name T43
Test name
Test status
Simulation time 364409111 ps
CPU time 2 seconds
Started Jun 13 02:47:05 PM PDT 24
Finished Jun 13 02:47:14 PM PDT 24
Peak memory 237296 kb
Host smart-04cbd3bb-989d-432b-bfd6-83b4e67c0619
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80984043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.80984043
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2269540499
Short name T148
Test name
Test status
Simulation time 164314680 ps
CPU time 0.9 seconds
Started Jun 13 02:47:32 PM PDT 24
Finished Jun 13 02:47:45 PM PDT 24
Peak memory 205136 kb
Host smart-7c77b714-804c-4845-bf40-77bedf39c9a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269540499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2269540499
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.161588310
Short name T139
Test name
Test status
Simulation time 5654998068 ps
CPU time 17.52 seconds
Started Jun 13 02:47:34 PM PDT 24
Finished Jun 13 02:48:04 PM PDT 24
Peak memory 205572 kb
Host smart-1a4df995-ba3c-4d20-a482-25cb053a909d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161588310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.161588310
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.861999037
Short name T154
Test name
Test status
Simulation time 53523073 ps
CPU time 0.8 seconds
Started Jun 13 02:47:26 PM PDT 24
Finished Jun 13 02:47:31 PM PDT 24
Peak memory 205120 kb
Host smart-8c9d9ebb-0231-446e-b298-4cda9bdbc85b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861999037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.861999037
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2498353163
Short name T174
Test name
Test status
Simulation time 38112396 ps
CPU time 0.78 seconds
Started Jun 13 02:47:36 PM PDT 24
Finished Jun 13 02:47:49 PM PDT 24
Peak memory 205144 kb
Host smart-3d8794b4-cdf6-460c-b319-d26ed6f292b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498353163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2498353163
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.1135964177
Short name T136
Test name
Test status
Simulation time 6390583423 ps
CPU time 8.39 seconds
Started Jun 13 02:47:47 PM PDT 24
Finished Jun 13 02:48:09 PM PDT 24
Peak memory 205432 kb
Host smart-78ef5636-7d81-4671-8a61-f9548a9cb3dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135964177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1135964177
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.661134569
Short name T66
Test name
Test status
Simulation time 109713608 ps
CPU time 0.75 seconds
Started Jun 13 02:47:39 PM PDT 24
Finished Jun 13 02:47:52 PM PDT 24
Peak memory 205116 kb
Host smart-a0b65419-3c40-43e4-a80b-4ce3f165af37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661134569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.661134569
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2438680262
Short name T239
Test name
Test status
Simulation time 104778355 ps
CPU time 0.81 seconds
Started Jun 13 02:47:30 PM PDT 24
Finished Jun 13 02:47:42 PM PDT 24
Peak memory 205136 kb
Host smart-20e2a041-81de-4796-9666-29d8a2720e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438680262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2438680262
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.85236499
Short name T147
Test name
Test status
Simulation time 76673241 ps
CPU time 0.85 seconds
Started Jun 13 02:47:41 PM PDT 24
Finished Jun 13 02:47:54 PM PDT 24
Peak memory 205116 kb
Host smart-b70297ae-e5b5-47bd-b100-cd677717d40a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85236499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.85236499
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3236227553
Short name T173
Test name
Test status
Simulation time 124424525 ps
CPU time 0.91 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:37 PM PDT 24
Peak memory 205092 kb
Host smart-c80fbac1-bd22-46fb-9f96-bd0ebc9dc8c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236227553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3236227553
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.4129592189
Short name T116
Test name
Test status
Simulation time 101215902 ps
CPU time 0.81 seconds
Started Jun 13 02:47:40 PM PDT 24
Finished Jun 13 02:47:53 PM PDT 24
Peak memory 205148 kb
Host smart-a02237bf-20f9-4894-8f0d-2c291ef1dc9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129592189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.4129592189
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.1626408311
Short name T135
Test name
Test status
Simulation time 19193640309 ps
CPU time 51.81 seconds
Started Jun 13 02:47:33 PM PDT 24
Finished Jun 13 02:48:37 PM PDT 24
Peak memory 205396 kb
Host smart-d772e26c-e777-4325-a47a-bb118549cc3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626408311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1626408311
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.414963178
Short name T167
Test name
Test status
Simulation time 169887063 ps
CPU time 0.77 seconds
Started Jun 13 02:47:42 PM PDT 24
Finished Jun 13 02:47:56 PM PDT 24
Peak memory 205132 kb
Host smart-c81aeb97-2db9-4ddd-b05d-27644d68d43a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414963178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.414963178
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.378253890
Short name T144
Test name
Test status
Simulation time 55465744 ps
CPU time 0.75 seconds
Started Jun 13 02:47:40 PM PDT 24
Finished Jun 13 02:47:53 PM PDT 24
Peak memory 205080 kb
Host smart-8b735dd8-379d-4942-bccb-3bae1dc181a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378253890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.378253890
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2953248610
Short name T201
Test name
Test status
Simulation time 62355751 ps
CPU time 0.78 seconds
Started Jun 13 02:47:32 PM PDT 24
Finished Jun 13 02:47:45 PM PDT 24
Peak memory 204980 kb
Host smart-76e292d5-e1b1-4a68-8b2e-dd628ce2b085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953248610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2953248610
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.634396240
Short name T202
Test name
Test status
Simulation time 5217462782 ps
CPU time 10.09 seconds
Started Jun 13 02:47:26 PM PDT 24
Finished Jun 13 02:47:52 PM PDT 24
Peak memory 205536 kb
Host smart-2200505a-5150-4b42-80e3-eeb0212a0692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634396240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.634396240
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2130740246
Short name T189
Test name
Test status
Simulation time 5530204507 ps
CPU time 4.86 seconds
Started Jun 13 02:47:18 PM PDT 24
Finished Jun 13 02:47:26 PM PDT 24
Peak memory 205520 kb
Host smart-28a54e06-5a49-4c7a-b876-92c488e370e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130740246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2130740246
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2386224971
Short name T246
Test name
Test status
Simulation time 2964506269 ps
CPU time 4.92 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:42 PM PDT 24
Peak memory 205592 kb
Host smart-f80f88b0-7c1e-45ee-a1b1-08d072c64889
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2386224971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2386224971
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2497142725
Short name T9
Test name
Test status
Simulation time 367170523 ps
CPU time 0.9 seconds
Started Jun 13 02:47:24 PM PDT 24
Finished Jun 13 02:47:29 PM PDT 24
Peak memory 205028 kb
Host smart-8e5a4709-a2d4-4c2a-859d-8b9f67b41e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497142725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2497142725
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1421738639
Short name T227
Test name
Test status
Simulation time 5108433057 ps
CPU time 8.01 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:44 PM PDT 24
Peak memory 205588 kb
Host smart-ea9f29b0-4943-4a86-8a9c-82a777bbb124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421738639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1421738639
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2943206089
Short name T44
Test name
Test status
Simulation time 1218767794 ps
CPU time 1.24 seconds
Started Jun 13 02:47:30 PM PDT 24
Finished Jun 13 02:47:43 PM PDT 24
Peak memory 236688 kb
Host smart-5f019454-4b75-477c-b3ee-4f36fd4dfa93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943206089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2943206089
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2273144089
Short name T157
Test name
Test status
Simulation time 60622855 ps
CPU time 0.81 seconds
Started Jun 13 02:47:41 PM PDT 24
Finished Jun 13 02:47:55 PM PDT 24
Peak memory 205120 kb
Host smart-cd469c91-215a-49e3-a689-37a109917d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273144089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2273144089
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.1290808864
Short name T251
Test name
Test status
Simulation time 7103051759 ps
CPU time 17.16 seconds
Started Jun 13 02:47:30 PM PDT 24
Finished Jun 13 02:47:58 PM PDT 24
Peak memory 205368 kb
Host smart-2b9ea119-11e1-4550-86a9-7c11bad22643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290808864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1290808864
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.147630595
Short name T149
Test name
Test status
Simulation time 51408185 ps
CPU time 0.72 seconds
Started Jun 13 02:47:41 PM PDT 24
Finished Jun 13 02:47:54 PM PDT 24
Peak memory 205144 kb
Host smart-5c8c910b-6192-47df-ab87-3eb014734762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147630595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.147630595
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1748959709
Short name T146
Test name
Test status
Simulation time 103503866 ps
CPU time 0.7 seconds
Started Jun 13 02:47:29 PM PDT 24
Finished Jun 13 02:47:40 PM PDT 24
Peak memory 205040 kb
Host smart-6ab031bb-04c9-41b3-8e1e-7760167fb736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748959709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1748959709
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.1853965482
Short name T140
Test name
Test status
Simulation time 15163258191 ps
CPU time 22.95 seconds
Started Jun 13 02:47:38 PM PDT 24
Finished Jun 13 02:48:13 PM PDT 24
Peak memory 205372 kb
Host smart-eb57abaa-54f7-4dc0-a313-ff868343f90e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853965482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1853965482
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.4019463468
Short name T162
Test name
Test status
Simulation time 43162077 ps
CPU time 0.79 seconds
Started Jun 13 02:47:42 PM PDT 24
Finished Jun 13 02:47:55 PM PDT 24
Peak memory 205112 kb
Host smart-7baae8eb-6487-45c6-8a8b-dde2962fc490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019463468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.4019463468
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1690472722
Short name T159
Test name
Test status
Simulation time 168917424 ps
CPU time 0.81 seconds
Started Jun 13 02:47:33 PM PDT 24
Finished Jun 13 02:47:46 PM PDT 24
Peak memory 205132 kb
Host smart-edafc8c4-bbe9-4ad1-80a1-89cffe3d884b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690472722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1690472722
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2978405646
Short name T152
Test name
Test status
Simulation time 55759758 ps
CPU time 0.7 seconds
Started Jun 13 02:47:44 PM PDT 24
Finished Jun 13 02:47:58 PM PDT 24
Peak memory 205080 kb
Host smart-44fb6000-2d4e-4f08-be4b-5c7895d312b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978405646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2978405646
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1600578823
Short name T150
Test name
Test status
Simulation time 68738237 ps
CPU time 0.72 seconds
Started Jun 13 02:47:34 PM PDT 24
Finished Jun 13 02:47:47 PM PDT 24
Peak memory 205076 kb
Host smart-34d6f6be-a26d-4352-aef7-395e50925be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600578823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1600578823
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.512273502
Short name T37
Test name
Test status
Simulation time 9039428402 ps
CPU time 24.9 seconds
Started Jun 13 02:47:35 PM PDT 24
Finished Jun 13 02:48:11 PM PDT 24
Peak memory 205360 kb
Host smart-d2b7d8fe-5068-455c-b37a-403b40bdfb68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512273502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.512273502
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2761706938
Short name T67
Test name
Test status
Simulation time 29835204 ps
CPU time 0.72 seconds
Started Jun 13 02:47:46 PM PDT 24
Finished Jun 13 02:48:01 PM PDT 24
Peak memory 205132 kb
Host smart-8570ef54-7124-45a5-81b7-98431a43f520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761706938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2761706938
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1151165075
Short name T170
Test name
Test status
Simulation time 152440179 ps
CPU time 0.91 seconds
Started Jun 13 02:47:43 PM PDT 24
Finished Jun 13 02:47:57 PM PDT 24
Peak memory 205108 kb
Host smart-c5e5742f-a06e-4d3b-ae67-549ac30be632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151165075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1151165075
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.732156276
Short name T155
Test name
Test status
Simulation time 78951308 ps
CPU time 0.68 seconds
Started Jun 13 02:47:34 PM PDT 24
Finished Jun 13 02:47:47 PM PDT 24
Peak memory 205124 kb
Host smart-8a6d7113-b1d2-42df-9007-3d3994769e12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732156276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.732156276
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.813638577
Short name T158
Test name
Test status
Simulation time 214525060 ps
CPU time 0.76 seconds
Started Jun 13 02:47:15 PM PDT 24
Finished Jun 13 02:47:20 PM PDT 24
Peak memory 205096 kb
Host smart-1ea906c0-d959-4b3b-a224-2f007eaea939
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813638577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.813638577
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2104857885
Short name T261
Test name
Test status
Simulation time 4373648712 ps
CPU time 6.55 seconds
Started Jun 13 02:47:24 PM PDT 24
Finished Jun 13 02:47:34 PM PDT 24
Peak memory 205540 kb
Host smart-3cf7a57c-1672-43b2-8bbe-de620e3d747e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104857885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2104857885
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2653733609
Short name T59
Test name
Test status
Simulation time 10711713402 ps
CPU time 15.21 seconds
Started Jun 13 02:47:25 PM PDT 24
Finished Jun 13 02:47:45 PM PDT 24
Peak memory 213708 kb
Host smart-ca8b651b-1156-46ca-96e9-4daddd52e30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653733609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2653733609
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1090362151
Short name T177
Test name
Test status
Simulation time 2084221503 ps
CPU time 3.81 seconds
Started Jun 13 02:47:24 PM PDT 24
Finished Jun 13 02:47:32 PM PDT 24
Peak memory 205496 kb
Host smart-3fd85dc5-d23e-4432-84c5-6732e7ec0b62
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090362151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1090362151
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1559660779
Short name T184
Test name
Test status
Simulation time 3683136479 ps
CPU time 9.22 seconds
Started Jun 13 02:47:22 PM PDT 24
Finished Jun 13 02:47:33 PM PDT 24
Peak memory 205540 kb
Host smart-4a4fe318-5161-4452-8944-7a04a32116d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559660779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1559660779
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.94106052
Short name T68
Test name
Test status
Simulation time 46031346 ps
CPU time 0.8 seconds
Started Jun 13 02:47:16 PM PDT 24
Finished Jun 13 02:47:20 PM PDT 24
Peak memory 205088 kb
Host smart-8a5d3571-9e1c-41ca-9f3e-c861d589caaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94106052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.94106052
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.130499688
Short name T204
Test name
Test status
Simulation time 5182536764 ps
CPU time 13.9 seconds
Started Jun 13 02:47:31 PM PDT 24
Finished Jun 13 02:47:56 PM PDT 24
Peak memory 205552 kb
Host smart-796c7a8d-80ef-442e-8ca4-d133050dc811
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130499688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.130499688
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2679588634
Short name T208
Test name
Test status
Simulation time 6132890679 ps
CPU time 13.92 seconds
Started Jun 13 02:47:12 PM PDT 24
Finished Jun 13 02:47:31 PM PDT 24
Peak memory 205544 kb
Host smart-9a16275b-27ce-4829-8200-9299919627a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679588634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2679588634
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.490118370
Short name T13
Test name
Test status
Simulation time 47314834307 ps
CPU time 65.08 seconds
Started Jun 13 02:47:20 PM PDT 24
Finished Jun 13 02:48:28 PM PDT 24
Peak memory 205360 kb
Host smart-908ca7c8-1b50-42be-8973-a74615b96247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490118370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.490118370
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2438895369
Short name T24
Test name
Test status
Simulation time 151560321 ps
CPU time 0.78 seconds
Started Jun 13 02:47:23 PM PDT 24
Finished Jun 13 02:47:27 PM PDT 24
Peak memory 205112 kb
Host smart-26174566-b62d-4cc3-a994-2470e1efb5e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438895369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2438895369
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.2934388095
Short name T185
Test name
Test status
Simulation time 33733346099 ps
CPU time 21.88 seconds
Started Jun 13 02:47:18 PM PDT 24
Finished Jun 13 02:47:43 PM PDT 24
Peak memory 213788 kb
Host smart-5538774c-c64a-47e1-8c1d-818ac3281124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934388095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2934388095
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1981001233
Short name T198
Test name
Test status
Simulation time 8324569669 ps
CPU time 21.85 seconds
Started Jun 13 02:47:04 PM PDT 24
Finished Jun 13 02:47:33 PM PDT 24
Peak memory 205588 kb
Host smart-0609b20c-ab9f-4fe9-848a-3eb48610d483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981001233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1981001233
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2470589891
Short name T186
Test name
Test status
Simulation time 660804088 ps
CPU time 1.34 seconds
Started Jun 13 02:47:16 PM PDT 24
Finished Jun 13 02:47:21 PM PDT 24
Peak memory 205508 kb
Host smart-9537919e-2837-44a6-b80d-b8a051d4e251
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2470589891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2470589891
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.712753621
Short name T178
Test name
Test status
Simulation time 6010586196 ps
CPU time 5.54 seconds
Started Jun 13 02:47:18 PM PDT 24
Finished Jun 13 02:47:26 PM PDT 24
Peak memory 205544 kb
Host smart-47e35864-7151-430f-898c-537de2dca6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712753621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.712753621
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1530114517
Short name T161
Test name
Test status
Simulation time 48830586 ps
CPU time 0.8 seconds
Started Jun 13 02:47:29 PM PDT 24
Finished Jun 13 02:47:41 PM PDT 24
Peak memory 205096 kb
Host smart-63934c43-b55c-46cf-98b0-c5d6dd02a72b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530114517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1530114517
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3578217264
Short name T55
Test name
Test status
Simulation time 25129797209 ps
CPU time 19.01 seconds
Started Jun 13 02:47:23 PM PDT 24
Finished Jun 13 02:47:45 PM PDT 24
Peak memory 213748 kb
Host smart-2b54a8d0-6294-43f0-9a27-9255674f072f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578217264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3578217264
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2246136254
Short name T215
Test name
Test status
Simulation time 2628601737 ps
CPU time 7.73 seconds
Started Jun 13 02:47:19 PM PDT 24
Finished Jun 13 02:47:29 PM PDT 24
Peak memory 205532 kb
Host smart-94b767c4-6bb5-47cf-ad5f-4a2b4a264699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246136254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2246136254
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.632634216
Short name T255
Test name
Test status
Simulation time 6995546238 ps
CPU time 10.57 seconds
Started Jun 13 02:47:04 PM PDT 24
Finished Jun 13 02:47:21 PM PDT 24
Peak memory 205596 kb
Host smart-593584da-a26a-40e4-ae1a-23fe7b9980d9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=632634216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.632634216
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.689388644
Short name T195
Test name
Test status
Simulation time 4073676580 ps
CPU time 2.14 seconds
Started Jun 13 02:47:23 PM PDT 24
Finished Jun 13 02:47:29 PM PDT 24
Peak memory 205540 kb
Host smart-e9565530-3f3d-469c-a5d7-7c3f1b58083b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689388644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.689388644
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.4163668186
Short name T143
Test name
Test status
Simulation time 48578566 ps
CPU time 0.72 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:38 PM PDT 24
Peak memory 205156 kb
Host smart-7e64eea2-acc1-49c1-8512-9e25f0599272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163668186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.4163668186
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.23477611
Short name T229
Test name
Test status
Simulation time 26589066815 ps
CPU time 63.25 seconds
Started Jun 13 02:47:08 PM PDT 24
Finished Jun 13 02:48:17 PM PDT 24
Peak memory 213788 kb
Host smart-16e59068-7b0c-449d-b1ea-a875bb16f189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23477611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.23477611
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3415723947
Short name T226
Test name
Test status
Simulation time 2213277945 ps
CPU time 3.05 seconds
Started Jun 13 02:47:21 PM PDT 24
Finished Jun 13 02:47:27 PM PDT 24
Peak memory 205584 kb
Host smart-cea66873-823b-4ab1-8ea2-154dee8cf476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415723947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3415723947
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3171483181
Short name T219
Test name
Test status
Simulation time 2681343163 ps
CPU time 3.22 seconds
Started Jun 13 02:47:28 PM PDT 24
Finished Jun 13 02:47:40 PM PDT 24
Peak memory 205600 kb
Host smart-b24670f4-031a-4b77-8082-c248513ac197
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3171483181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3171483181
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1192647988
Short name T200
Test name
Test status
Simulation time 4470859804 ps
CPU time 4 seconds
Started Jun 13 02:47:21 PM PDT 24
Finished Jun 13 02:47:28 PM PDT 24
Peak memory 205524 kb
Host smart-db40665e-f025-4c8b-8a8f-59359af0d120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192647988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1192647988
Directory /workspace/9.rv_dm_sba_tl_access/latest
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