Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.53 94.56 78.90 88.43 73.08 84.50 98.42 38.82


Total test records in report: 416
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T101 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.362632965 Jun 21 06:24:41 PM PDT 24 Jun 21 06:24:51 PM PDT 24 98407380 ps
T117 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2265751804 Jun 21 06:24:51 PM PDT 24 Jun 21 06:25:07 PM PDT 24 871009518 ps
T279 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.569070725 Jun 21 06:24:42 PM PDT 24 Jun 21 06:24:51 PM PDT 24 1130011446 ps
T280 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1890292066 Jun 21 06:24:52 PM PDT 24 Jun 21 06:25:10 PM PDT 24 9906756943 ps
T102 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.4089770379 Jun 21 06:25:13 PM PDT 24 Jun 21 06:25:18 PM PDT 24 314381634 ps
T281 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3388080897 Jun 21 06:24:42 PM PDT 24 Jun 21 06:24:51 PM PDT 24 118758106 ps
T282 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2391127410 Jun 21 06:24:44 PM PDT 24 Jun 21 06:25:50 PM PDT 24 38650578334 ps
T283 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2826474984 Jun 21 06:25:12 PM PDT 24 Jun 21 06:25:19 PM PDT 24 325737435 ps
T284 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2534279866 Jun 21 06:24:44 PM PDT 24 Jun 21 06:24:54 PM PDT 24 156132660 ps
T67 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2542132860 Jun 21 06:24:50 PM PDT 24 Jun 21 06:27:57 PM PDT 24 71212109207 ps
T113 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3493486103 Jun 21 06:24:47 PM PDT 24 Jun 21 06:25:01 PM PDT 24 671103402 ps
T285 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2519023545 Jun 21 06:25:05 PM PDT 24 Jun 21 06:25:14 PM PDT 24 1295952811 ps
T286 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3218427860 Jun 21 06:24:46 PM PDT 24 Jun 21 06:29:40 PM PDT 24 120879131279 ps
T118 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.913734261 Jun 21 06:24:51 PM PDT 24 Jun 21 06:25:02 PM PDT 24 1017408667 ps
T106 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4024607392 Jun 21 06:24:39 PM PDT 24 Jun 21 06:25:39 PM PDT 24 1603428191 ps
T103 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1996724099 Jun 21 06:24:45 PM PDT 24 Jun 21 06:26:03 PM PDT 24 3470286196 ps
T287 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3997717311 Jun 21 06:24:56 PM PDT 24 Jun 21 06:25:13 PM PDT 24 41764273358 ps
T288 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.406962303 Jun 21 06:24:51 PM PDT 24 Jun 21 06:24:58 PM PDT 24 2329739844 ps
T114 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4061581063 Jun 21 06:25:08 PM PDT 24 Jun 21 06:25:13 PM PDT 24 291325627 ps
T289 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2943277951 Jun 21 06:24:38 PM PDT 24 Jun 21 06:24:45 PM PDT 24 145753504 ps
T290 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1103438356 Jun 21 06:24:58 PM PDT 24 Jun 21 06:25:10 PM PDT 24 2006580426 ps
T291 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1133043113 Jun 21 06:24:52 PM PDT 24 Jun 21 06:25:17 PM PDT 24 15687269334 ps
T292 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.936783864 Jun 21 06:24:53 PM PDT 24 Jun 21 06:25:00 PM PDT 24 184775286 ps
T293 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1154370969 Jun 21 06:24:57 PM PDT 24 Jun 21 06:25:09 PM PDT 24 3635597765 ps
T132 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2746334124 Jun 21 06:25:10 PM PDT 24 Jun 21 06:25:34 PM PDT 24 5639573639 ps
T294 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4240848991 Jun 21 06:24:57 PM PDT 24 Jun 21 06:25:01 PM PDT 24 296393307 ps
T295 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3817433785 Jun 21 06:25:01 PM PDT 24 Jun 21 06:25:30 PM PDT 24 24879363222 ps
T296 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2546362315 Jun 21 06:25:04 PM PDT 24 Jun 21 06:25:08 PM PDT 24 310918253 ps
T297 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.361025732 Jun 21 06:24:39 PM PDT 24 Jun 21 06:24:53 PM PDT 24 3805220099 ps
T298 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3547704752 Jun 21 06:24:39 PM PDT 24 Jun 21 06:24:47 PM PDT 24 169915219 ps
T299 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3572664290 Jun 21 06:24:52 PM PDT 24 Jun 21 06:25:00 PM PDT 24 151949871 ps
T300 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4057352698 Jun 21 06:24:36 PM PDT 24 Jun 21 06:24:41 PM PDT 24 456235238 ps
T121 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.867883257 Jun 21 06:24:39 PM PDT 24 Jun 21 06:25:47 PM PDT 24 88719840830 ps
T301 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3610175510 Jun 21 06:24:45 PM PDT 24 Jun 21 06:25:58 PM PDT 24 1476264592 ps
T302 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2901253621 Jun 21 06:25:05 PM PDT 24 Jun 21 06:25:09 PM PDT 24 104907001 ps
T303 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4193553197 Jun 21 06:24:43 PM PDT 24 Jun 21 06:24:53 PM PDT 24 881118717 ps
T304 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.367034734 Jun 21 06:25:02 PM PDT 24 Jun 21 06:25:09 PM PDT 24 2654952468 ps
T124 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3275505619 Jun 21 06:25:12 PM PDT 24 Jun 21 06:25:24 PM PDT 24 1005057420 ps
T107 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4085004564 Jun 21 06:24:59 PM PDT 24 Jun 21 06:25:03 PM PDT 24 128805198 ps
T305 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2415372037 Jun 21 06:24:44 PM PDT 24 Jun 21 06:24:54 PM PDT 24 386392645 ps
T306 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2142175676 Jun 21 06:24:37 PM PDT 24 Jun 21 06:24:48 PM PDT 24 1644980792 ps
T307 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.857644763 Jun 21 06:25:13 PM PDT 24 Jun 21 06:25:16 PM PDT 24 177675487 ps
T308 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2578901257 Jun 21 06:24:46 PM PDT 24 Jun 21 06:24:54 PM PDT 24 82549100 ps
T125 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2071463517 Jun 21 06:25:05 PM PDT 24 Jun 21 06:25:24 PM PDT 24 2441335546 ps
T309 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1390712704 Jun 21 06:24:46 PM PDT 24 Jun 21 06:24:59 PM PDT 24 1703208321 ps
T310 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3034734786 Jun 21 06:24:58 PM PDT 24 Jun 21 06:25:04 PM PDT 24 608910848 ps
T311 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2636507696 Jun 21 06:24:48 PM PDT 24 Jun 21 06:24:57 PM PDT 24 535858244 ps
T108 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.517825093 Jun 21 06:24:53 PM PDT 24 Jun 21 06:25:00 PM PDT 24 759204019 ps
T312 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.146116117 Jun 21 06:24:38 PM PDT 24 Jun 21 06:24:44 PM PDT 24 95148780 ps
T313 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.673835201 Jun 21 06:24:44 PM PDT 24 Jun 21 06:24:52 PM PDT 24 134979281 ps
T314 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4242253940 Jun 21 06:25:12 PM PDT 24 Jun 21 06:25:14 PM PDT 24 470948053 ps
T128 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2139174961 Jun 21 06:24:59 PM PDT 24 Jun 21 06:25:15 PM PDT 24 1411551839 ps
T109 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3867359629 Jun 21 06:25:07 PM PDT 24 Jun 21 06:25:10 PM PDT 24 102150957 ps
T110 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3803345472 Jun 21 06:24:36 PM PDT 24 Jun 21 06:25:37 PM PDT 24 15625240227 ps
T315 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1513132491 Jun 21 06:24:41 PM PDT 24 Jun 21 06:24:51 PM PDT 24 112250288 ps
T316 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3620111211 Jun 21 06:25:04 PM PDT 24 Jun 21 06:25:13 PM PDT 24 2191242854 ps
T129 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4084066993 Jun 21 06:24:55 PM PDT 24 Jun 21 06:25:11 PM PDT 24 1510047303 ps
T104 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1364765605 Jun 21 06:24:50 PM PDT 24 Jun 21 06:24:58 PM PDT 24 333535554 ps
T317 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1272530 Jun 21 06:24:58 PM PDT 24 Jun 21 06:25:02 PM PDT 24 615000326 ps
T318 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.4222803927 Jun 21 06:24:40 PM PDT 24 Jun 21 06:24:52 PM PDT 24 683219115 ps
T319 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1603780595 Jun 21 06:24:44 PM PDT 24 Jun 21 06:29:28 PM PDT 24 108612886293 ps
T320 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1978812658 Jun 21 06:24:51 PM PDT 24 Jun 21 06:26:21 PM PDT 24 63907281043 ps
T127 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1567994616 Jun 21 06:24:50 PM PDT 24 Jun 21 06:25:14 PM PDT 24 3030826444 ps
T321 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1176702286 Jun 21 06:24:51 PM PDT 24 Jun 21 06:24:59 PM PDT 24 461254794 ps
T322 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.26101445 Jun 21 06:24:44 PM PDT 24 Jun 21 06:24:54 PM PDT 24 68885014 ps
T323 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3646848832 Jun 21 06:24:58 PM PDT 24 Jun 21 06:25:04 PM PDT 24 3597438688 ps
T324 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3031034191 Jun 21 06:25:11 PM PDT 24 Jun 21 06:25:14 PM PDT 24 891488483 ps
T325 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.147204560 Jun 21 06:24:44 PM PDT 24 Jun 21 06:24:52 PM PDT 24 792386735 ps
T326 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2855495465 Jun 21 06:24:56 PM PDT 24 Jun 21 06:25:07 PM PDT 24 817316673 ps
T327 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2737360507 Jun 21 06:24:45 PM PDT 24 Jun 21 06:24:56 PM PDT 24 233563246 ps
T328 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1552742381 Jun 21 06:25:04 PM PDT 24 Jun 21 06:25:17 PM PDT 24 2480674107 ps
T329 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3751631710 Jun 21 06:25:05 PM PDT 24 Jun 21 06:25:08 PM PDT 24 333884334 ps
T330 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2740933520 Jun 21 06:24:49 PM PDT 24 Jun 21 06:24:58 PM PDT 24 151350717 ps
T331 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.166627440 Jun 21 06:24:57 PM PDT 24 Jun 21 06:25:03 PM PDT 24 517433849 ps
T332 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1750581893 Jun 21 06:24:46 PM PDT 24 Jun 21 06:24:55 PM PDT 24 259888307 ps
T333 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1143604271 Jun 21 06:24:53 PM PDT 24 Jun 21 06:25:05 PM PDT 24 2262442752 ps
T334 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3175471046 Jun 21 06:25:03 PM PDT 24 Jun 21 06:25:06 PM PDT 24 508199761 ps
T335 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1110156728 Jun 21 06:25:05 PM PDT 24 Jun 21 06:25:08 PM PDT 24 136169329 ps
T336 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4094051785 Jun 21 06:25:03 PM PDT 24 Jun 21 06:25:09 PM PDT 24 3473895094 ps
T337 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3029397752 Jun 21 06:25:11 PM PDT 24 Jun 21 06:25:22 PM PDT 24 3131597715 ps
T338 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2108903380 Jun 21 06:24:51 PM PDT 24 Jun 21 06:24:59 PM PDT 24 422247606 ps
T339 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3214179680 Jun 21 06:25:16 PM PDT 24 Jun 21 06:25:20 PM PDT 24 1105551546 ps
T340 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1301807657 Jun 21 06:25:01 PM PDT 24 Jun 21 06:25:22 PM PDT 24 7083002365 ps
T341 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.794273960 Jun 21 06:24:44 PM PDT 24 Jun 21 06:26:07 PM PDT 24 14301764196 ps
T342 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.670050725 Jun 21 06:24:52 PM PDT 24 Jun 21 06:25:00 PM PDT 24 84899374 ps
T95 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2857529662 Jun 21 06:24:37 PM PDT 24 Jun 21 06:24:49 PM PDT 24 8212545981 ps
T343 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3253908248 Jun 21 06:25:02 PM PDT 24 Jun 21 06:25:07 PM PDT 24 508412563 ps
T344 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1933558323 Jun 21 06:24:52 PM PDT 24 Jun 21 06:24:59 PM PDT 24 172659734 ps
T345 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4221513765 Jun 21 06:24:45 PM PDT 24 Jun 21 06:24:52 PM PDT 24 53700233 ps
T346 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.992324807 Jun 21 06:25:00 PM PDT 24 Jun 21 06:25:07 PM PDT 24 420744590 ps
T347 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2857619268 Jun 21 06:25:00 PM PDT 24 Jun 21 06:25:07 PM PDT 24 1255636699 ps
T348 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2552762793 Jun 21 06:25:12 PM PDT 24 Jun 21 06:25:25 PM PDT 24 1620101941 ps
T349 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.4246089055 Jun 21 06:25:10 PM PDT 24 Jun 21 06:25:14 PM PDT 24 2148030603 ps
T350 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.684984711 Jun 21 06:24:46 PM PDT 24 Jun 21 06:25:13 PM PDT 24 8063545374 ps
T351 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.140015405 Jun 21 06:24:44 PM PDT 24 Jun 21 06:26:11 PM PDT 24 91282425535 ps
T352 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1105499962 Jun 21 06:25:11 PM PDT 24 Jun 21 06:25:15 PM PDT 24 2740636433 ps
T122 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.4230297501 Jun 21 06:25:03 PM PDT 24 Jun 21 06:25:09 PM PDT 24 921688944 ps
T353 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1666820240 Jun 21 06:24:59 PM PDT 24 Jun 21 06:25:15 PM PDT 24 8407311445 ps
T354 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.208396778 Jun 21 06:24:45 PM PDT 24 Jun 21 06:25:30 PM PDT 24 6420341341 ps
T355 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1966158435 Jun 21 06:24:51 PM PDT 24 Jun 21 06:25:03 PM PDT 24 895071148 ps
T96 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3134647140 Jun 21 06:24:45 PM PDT 24 Jun 21 06:25:17 PM PDT 24 9608953230 ps
T356 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1315221159 Jun 21 06:24:38 PM PDT 24 Jun 21 06:24:52 PM PDT 24 487751597 ps
T357 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1334781969 Jun 21 06:25:10 PM PDT 24 Jun 21 06:25:46 PM PDT 24 12552421672 ps
T358 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1807889248 Jun 21 06:24:47 PM PDT 24 Jun 21 06:25:37 PM PDT 24 16398425400 ps
T359 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1051924396 Jun 21 06:24:51 PM PDT 24 Jun 21 06:24:58 PM PDT 24 125764907 ps
T360 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2036138273 Jun 21 06:24:50 PM PDT 24 Jun 21 06:25:15 PM PDT 24 11391136353 ps
T361 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2054954680 Jun 21 06:25:00 PM PDT 24 Jun 21 06:25:14 PM PDT 24 7200475388 ps
T362 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1448194380 Jun 21 06:24:45 PM PDT 24 Jun 21 06:24:53 PM PDT 24 106108952 ps
T363 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1268185447 Jun 21 06:24:52 PM PDT 24 Jun 21 06:24:58 PM PDT 24 243280788 ps
T364 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1357425763 Jun 21 06:25:00 PM PDT 24 Jun 21 06:25:04 PM PDT 24 1106244419 ps
T365 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3315968035 Jun 21 06:24:48 PM PDT 24 Jun 21 06:24:55 PM PDT 24 68904074 ps
T366 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.178573523 Jun 21 06:24:41 PM PDT 24 Jun 21 06:25:06 PM PDT 24 8789189606 ps
T367 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4200153827 Jun 21 06:24:50 PM PDT 24 Jun 21 06:25:00 PM PDT 24 4344911881 ps
T368 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3538472486 Jun 21 06:24:59 PM PDT 24 Jun 21 06:29:45 PM PDT 24 113459364575 ps
T369 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3575289474 Jun 21 06:24:53 PM PDT 24 Jun 21 06:24:59 PM PDT 24 66819850 ps
T370 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4257694042 Jun 21 06:24:44 PM PDT 24 Jun 21 06:24:52 PM PDT 24 360449122 ps
T371 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.383253436 Jun 21 06:24:39 PM PDT 24 Jun 21 06:24:48 PM PDT 24 175701596 ps
T105 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3209365709 Jun 21 06:24:59 PM PDT 24 Jun 21 06:25:05 PM PDT 24 95472727 ps
T372 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1876555045 Jun 21 06:24:58 PM PDT 24 Jun 21 06:25:04 PM PDT 24 109307701 ps
T373 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.624615879 Jun 21 06:24:46 PM PDT 24 Jun 21 06:25:04 PM PDT 24 1967533448 ps
T374 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.4060826130 Jun 21 06:25:02 PM PDT 24 Jun 21 06:25:07 PM PDT 24 56204025 ps
T375 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2610883484 Jun 21 06:25:11 PM PDT 24 Jun 21 06:28:57 PM PDT 24 77921370199 ps
T376 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2007670774 Jun 21 06:25:05 PM PDT 24 Jun 21 06:25:07 PM PDT 24 1735970920 ps
T377 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3348252174 Jun 21 06:24:58 PM PDT 24 Jun 21 06:25:02 PM PDT 24 193199706 ps
T378 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1203031837 Jun 21 06:24:48 PM PDT 24 Jun 21 06:25:22 PM PDT 24 36769355530 ps
T379 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4249079351 Jun 21 06:24:50 PM PDT 24 Jun 21 06:25:19 PM PDT 24 35012070444 ps
T380 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2630842212 Jun 21 06:24:43 PM PDT 24 Jun 21 06:26:28 PM PDT 24 32986742924 ps
T381 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3649061191 Jun 21 06:24:59 PM PDT 24 Jun 21 06:25:04 PM PDT 24 419921096 ps
T382 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2586707160 Jun 21 06:24:52 PM PDT 24 Jun 21 06:25:02 PM PDT 24 1972138434 ps
T383 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2908494089 Jun 21 06:25:04 PM PDT 24 Jun 21 06:25:14 PM PDT 24 4384012590 ps
T384 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2451796629 Jun 21 06:24:52 PM PDT 24 Jun 21 06:24:58 PM PDT 24 158608519 ps
T385 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2849719703 Jun 21 06:24:39 PM PDT 24 Jun 21 06:27:33 PM PDT 24 61805953060 ps
T386 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1377750150 Jun 21 06:24:45 PM PDT 24 Jun 21 06:24:54 PM PDT 24 370273716 ps
T387 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.74046055 Jun 21 06:25:09 PM PDT 24 Jun 21 06:25:15 PM PDT 24 3130089487 ps
T388 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3277340011 Jun 21 06:24:54 PM PDT 24 Jun 21 06:25:08 PM PDT 24 2326983467 ps
T389 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.893313074 Jun 21 06:25:10 PM PDT 24 Jun 21 06:25:20 PM PDT 24 7223532432 ps
T390 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1799850959 Jun 21 06:25:04 PM PDT 24 Jun 21 06:25:06 PM PDT 24 267069472 ps
T391 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2654046111 Jun 21 06:24:57 PM PDT 24 Jun 21 06:25:03 PM PDT 24 95047182 ps
T392 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1920536442 Jun 21 06:24:39 PM PDT 24 Jun 21 06:26:34 PM PDT 24 60785380279 ps
T393 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2158534990 Jun 21 06:25:08 PM PDT 24 Jun 21 06:25:11 PM PDT 24 756843110 ps
T394 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3699028853 Jun 21 06:24:59 PM PDT 24 Jun 21 06:25:04 PM PDT 24 204573624 ps
T395 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.668081282 Jun 21 06:24:46 PM PDT 24 Jun 21 06:24:56 PM PDT 24 947692654 ps
T396 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3831437912 Jun 21 06:25:04 PM PDT 24 Jun 21 06:25:14 PM PDT 24 3661296600 ps
T397 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.4150176521 Jun 21 06:25:13 PM PDT 24 Jun 21 06:25:19 PM PDT 24 376007634 ps
T398 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.898090841 Jun 21 06:25:11 PM PDT 24 Jun 21 06:25:19 PM PDT 24 2214261718 ps
T399 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.129334513 Jun 21 06:24:50 PM PDT 24 Jun 21 06:25:08 PM PDT 24 8489784840 ps
T400 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1623136016 Jun 21 06:25:04 PM PDT 24 Jun 21 06:25:09 PM PDT 24 346467125 ps
T401 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2901130987 Jun 21 06:24:40 PM PDT 24 Jun 21 06:24:53 PM PDT 24 6518060785 ps
T402 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2935362628 Jun 21 06:24:50 PM PDT 24 Jun 21 06:25:50 PM PDT 24 60070338284 ps
T403 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.220040231 Jun 21 06:25:04 PM PDT 24 Jun 21 06:25:10 PM PDT 24 270546499 ps
T130 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1897884183 Jun 21 06:25:12 PM PDT 24 Jun 21 06:25:37 PM PDT 24 6308522128 ps
T404 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3605558383 Jun 21 06:25:11 PM PDT 24 Jun 21 06:25:14 PM PDT 24 347572168 ps
T405 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3876626773 Jun 21 06:24:37 PM PDT 24 Jun 21 06:24:44 PM PDT 24 5420712861 ps
T97 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1003874682 Jun 21 06:24:46 PM PDT 24 Jun 21 06:25:08 PM PDT 24 25008887727 ps
T406 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1680496170 Jun 21 06:24:50 PM PDT 24 Jun 21 06:25:02 PM PDT 24 108770564 ps
T407 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3660256513 Jun 21 06:25:04 PM PDT 24 Jun 21 06:25:12 PM PDT 24 602122597 ps
T408 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1620529741 Jun 21 06:24:46 PM PDT 24 Jun 21 06:24:58 PM PDT 24 2962153700 ps
T409 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2026957635 Jun 21 06:24:49 PM PDT 24 Jun 21 06:24:56 PM PDT 24 381911449 ps
T410 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.577209069 Jun 21 06:24:59 PM PDT 24 Jun 21 06:25:09 PM PDT 24 2946508431 ps
T411 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.765397850 Jun 21 06:24:51 PM PDT 24 Jun 21 06:25:32 PM PDT 24 34222445175 ps
T98 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2397959001 Jun 21 06:24:47 PM PDT 24 Jun 21 06:25:02 PM PDT 24 15603739197 ps
T412 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2022370744 Jun 21 06:24:40 PM PDT 24 Jun 21 06:24:58 PM PDT 24 6847546781 ps
T413 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2979608557 Jun 21 06:24:49 PM PDT 24 Jun 21 06:25:08 PM PDT 24 22110258605 ps
T414 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3049403962 Jun 21 06:24:38 PM PDT 24 Jun 21 06:24:46 PM PDT 24 303834182 ps
T415 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3207987016 Jun 21 06:24:59 PM PDT 24 Jun 21 06:25:23 PM PDT 24 3677718930 ps
T416 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2453816997 Jun 21 06:25:08 PM PDT 24 Jun 21 06:25:10 PM PDT 24 1344178095 ps

Test location /workspace/coverage/default/46.rv_dm_stress_all.670648418
Short name T1
Test name
Test status
Simulation time 11675283332 ps
CPU time 17.57 seconds
Started Jun 21 06:00:21 PM PDT 24
Finished Jun 21 06:00:40 PM PDT 24
Peak memory 205004 kb
Host smart-52afa4cd-16d7-4cbd-ba0e-6c9165511e73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670648418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.670648418
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.988305824
Short name T11
Test name
Test status
Simulation time 23923103657 ps
CPU time 20.68 seconds
Started Jun 21 05:59:53 PM PDT 24
Finished Jun 21 06:00:14 PM PDT 24
Peak memory 213448 kb
Host smart-15b6d2de-d4c4-4fa9-a3d0-5922d69ae276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988305824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.988305824
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2421262705
Short name T44
Test name
Test status
Simulation time 78308052645 ps
CPU time 35.33 seconds
Started Jun 21 06:24:46 PM PDT 24
Finished Jun 21 06:25:29 PM PDT 24
Peak memory 223984 kb
Host smart-905e4da5-d445-4791-b310-ec5b9581f2a1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421262705 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2421262705
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3885135527
Short name T73
Test name
Test status
Simulation time 136501893 ps
CPU time 0.86 seconds
Started Jun 21 06:00:23 PM PDT 24
Finished Jun 21 06:00:27 PM PDT 24
Peak memory 204804 kb
Host smart-43a2e67e-6654-410c-aae3-5c27d7de7016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885135527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3885135527
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.65068190
Short name T5
Test name
Test status
Simulation time 32396586196 ps
CPU time 37.12 seconds
Started Jun 21 06:00:23 PM PDT 24
Finished Jun 21 06:01:03 PM PDT 24
Peak memory 205108 kb
Host smart-ff5fcc58-18e8-4848-90a0-4ac63b4a3b3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65068190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.65068190
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3770095206
Short name T50
Test name
Test status
Simulation time 3998678351 ps
CPU time 21.35 seconds
Started Jun 21 06:24:40 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 213828 kb
Host smart-796cd50a-9d84-49a3-8f2b-f43cad817500
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770095206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3770095206
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3864056390
Short name T66
Test name
Test status
Simulation time 47506736192 ps
CPU time 143.25 seconds
Started Jun 21 06:24:53 PM PDT 24
Finished Jun 21 06:27:21 PM PDT 24
Peak memory 221744 kb
Host smart-173337e2-8744-4db1-83c3-3d30ab19c811
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864056390 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3864056390
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3980443136
Short name T84
Test name
Test status
Simulation time 141655951 ps
CPU time 1.65 seconds
Started Jun 21 06:25:04 PM PDT 24
Finished Jun 21 06:25:07 PM PDT 24
Peak memory 213684 kb
Host smart-b496f1d7-cbbc-47f2-a91f-e36943aca623
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980443136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3980443136
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.2719486231
Short name T17
Test name
Test status
Simulation time 13390258444 ps
CPU time 9.51 seconds
Started Jun 21 06:00:23 PM PDT 24
Finished Jun 21 06:00:35 PM PDT 24
Peak memory 204952 kb
Host smart-7ebf1f97-a80a-4da5-8fa2-5278b8137b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719486231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2719486231
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1092009043
Short name T224
Test name
Test status
Simulation time 95836729926 ps
CPU time 265.96 seconds
Started Jun 21 06:00:09 PM PDT 24
Finished Jun 21 06:04:36 PM PDT 24
Peak memory 213340 kb
Host smart-9a207c51-b52a-4fb3-955d-d2354f32a5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092009043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1092009043
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1359493325
Short name T42
Test name
Test status
Simulation time 269643485 ps
CPU time 1.4 seconds
Started Jun 21 05:59:39 PM PDT 24
Finished Jun 21 05:59:41 PM PDT 24
Peak memory 229284 kb
Host smart-e1734b1b-80f3-43fa-acb4-485e0b8b24d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359493325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1359493325
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2981009462
Short name T28
Test name
Test status
Simulation time 63164639 ps
CPU time 0.84 seconds
Started Jun 21 05:59:47 PM PDT 24
Finished Jun 21 05:59:49 PM PDT 24
Peak memory 212972 kb
Host smart-05f58759-fb0e-4067-91ff-4f855dbe6515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981009462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2981009462
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.2312385389
Short name T38
Test name
Test status
Simulation time 217724752 ps
CPU time 0.84 seconds
Started Jun 21 05:59:39 PM PDT 24
Finished Jun 21 05:59:40 PM PDT 24
Peak memory 204660 kb
Host smart-99dd5905-409d-4aed-9384-3cdfb0d94686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312385389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2312385389
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.304033770
Short name T23
Test name
Test status
Simulation time 9178446864 ps
CPU time 13.42 seconds
Started Jun 21 06:00:06 PM PDT 24
Finished Jun 21 06:00:21 PM PDT 24
Peak memory 205104 kb
Host smart-38d24356-a1d7-4a86-894c-c479b89610d1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=304033770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.304033770
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2249774801
Short name T10
Test name
Test status
Simulation time 3796816940 ps
CPU time 2.06 seconds
Started Jun 21 05:59:33 PM PDT 24
Finished Jun 21 05:59:36 PM PDT 24
Peak memory 204788 kb
Host smart-b91df8bd-5f1b-43f4-a8ff-3429ad7a0c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249774801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2249774801
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2746334124
Short name T132
Test name
Test status
Simulation time 5639573639 ps
CPU time 23.32 seconds
Started Jun 21 06:25:10 PM PDT 24
Finished Jun 21 06:25:34 PM PDT 24
Peak memory 213808 kb
Host smart-1f34207e-84ed-4514-8ab1-0f8cddeb2d95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746334124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
746334124
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2721541033
Short name T29
Test name
Test status
Simulation time 21523906005 ps
CPU time 54.56 seconds
Started Jun 21 06:00:19 PM PDT 24
Finished Jun 21 06:01:15 PM PDT 24
Peak memory 213200 kb
Host smart-efbd3ce4-1ec0-473c-9d9b-30c91090f0de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721541033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2721541033
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.3339215519
Short name T36
Test name
Test status
Simulation time 937725134 ps
CPU time 1.08 seconds
Started Jun 21 05:59:38 PM PDT 24
Finished Jun 21 05:59:40 PM PDT 24
Peak memory 204740 kb
Host smart-aa4bfac2-64ee-42af-ba7f-aa79bd25df8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339215519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.3339215519
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4061581063
Short name T114
Test name
Test status
Simulation time 291325627 ps
CPU time 4.42 seconds
Started Jun 21 06:25:08 PM PDT 24
Finished Jun 21 06:25:13 PM PDT 24
Peak memory 205464 kb
Host smart-dd1157ca-2bfd-4122-ae74-c85583712673
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061581063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.4061581063
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.361025732
Short name T297
Test name
Test status
Simulation time 3805220099 ps
CPU time 6.77 seconds
Started Jun 21 06:24:39 PM PDT 24
Finished Jun 21 06:24:53 PM PDT 24
Peak memory 205452 kb
Host smart-e904e2d5-f8e3-49b5-8338-1d4086849865
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361025732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.361025732
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2857529662
Short name T95
Test name
Test status
Simulation time 8212545981 ps
CPU time 6.43 seconds
Started Jun 21 06:24:37 PM PDT 24
Finished Jun 21 06:24:49 PM PDT 24
Peak memory 205528 kb
Host smart-8f101242-9d6d-47c4-8ab6-5691ab05262f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857529662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2857529662
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1285521379
Short name T126
Test name
Test status
Simulation time 6710110178 ps
CPU time 19.42 seconds
Started Jun 21 06:24:44 PM PDT 24
Finished Jun 21 06:25:11 PM PDT 24
Peak memory 213828 kb
Host smart-5be7ff1f-17a3-4f20-ba77-a3d1413d50b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285521379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1285521379
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2139174961
Short name T128
Test name
Test status
Simulation time 1411551839 ps
CPU time 12.44 seconds
Started Jun 21 06:24:59 PM PDT 24
Finished Jun 21 06:25:15 PM PDT 24
Peak memory 213668 kb
Host smart-4e3f4220-691a-4ced-a789-aacaf88796c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139174961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
139174961
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3614397644
Short name T201
Test name
Test status
Simulation time 2137546059 ps
CPU time 2.84 seconds
Started Jun 21 05:59:32 PM PDT 24
Finished Jun 21 05:59:36 PM PDT 24
Peak memory 205060 kb
Host smart-930487bd-8146-47ef-aff0-af5c5739ff45
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3614397644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3614397644
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.400787400
Short name T25
Test name
Test status
Simulation time 538977654 ps
CPU time 1.22 seconds
Started Jun 21 05:59:32 PM PDT 24
Finished Jun 21 05:59:34 PM PDT 24
Peak memory 204608 kb
Host smart-4effb129-5a72-4c06-beac-bebb255a6152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400787400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.400787400
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3109305377
Short name T31
Test name
Test status
Simulation time 1341353693 ps
CPU time 1.63 seconds
Started Jun 21 05:59:40 PM PDT 24
Finished Jun 21 05:59:43 PM PDT 24
Peak memory 204696 kb
Host smart-3e040fd1-c6d2-4e4d-9ff6-65d137484239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109305377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3109305377
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1437230835
Short name T53
Test name
Test status
Simulation time 88435381 ps
CPU time 1.56 seconds
Started Jun 21 06:25:06 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 213660 kb
Host smart-daf14d11-a5ac-4287-9cf6-449ed868056b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437230835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1437230835
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1567994616
Short name T127
Test name
Test status
Simulation time 3030826444 ps
CPU time 18.57 seconds
Started Jun 21 06:24:50 PM PDT 24
Finished Jun 21 06:25:14 PM PDT 24
Peak memory 213852 kb
Host smart-7dba0ae1-12da-460f-839a-7d3ad8ac5200
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567994616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1567994616
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.362632965
Short name T101
Test name
Test status
Simulation time 98407380 ps
CPU time 2.43 seconds
Started Jun 21 06:24:41 PM PDT 24
Finished Jun 21 06:24:51 PM PDT 24
Peak memory 213584 kb
Host smart-888fb4c3-1b58-4dec-8301-5a0afcaf647f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362632965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.362632965
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.794273960
Short name T341
Test name
Test status
Simulation time 14301764196 ps
CPU time 75.69 seconds
Started Jun 21 06:24:44 PM PDT 24
Finished Jun 21 06:26:07 PM PDT 24
Peak memory 205636 kb
Host smart-9348c7d8-8cfe-4c56-aeb1-54e16c9cec68
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794273960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.794273960
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3803345472
Short name T110
Test name
Test status
Simulation time 15625240227 ps
CPU time 57.85 seconds
Started Jun 21 06:24:36 PM PDT 24
Finished Jun 21 06:25:37 PM PDT 24
Peak memory 213888 kb
Host smart-3cc19838-c23b-4331-b7e0-875108c1e21b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803345472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3803345472
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1513132491
Short name T315
Test name
Test status
Simulation time 112250288 ps
CPU time 1.68 seconds
Started Jun 21 06:24:41 PM PDT 24
Finished Jun 21 06:24:51 PM PDT 24
Peak memory 213632 kb
Host smart-c9d5c0bd-cc01-4c9f-8b0d-96c9795f8dd7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513132491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1513132491
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2771341623
Short name T273
Test name
Test status
Simulation time 779341463 ps
CPU time 2.63 seconds
Started Jun 21 06:24:42 PM PDT 24
Finished Jun 21 06:24:52 PM PDT 24
Peak memory 221964 kb
Host smart-7524108c-4116-47d6-816c-7bb92250bbf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771341623 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2771341623
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1920536442
Short name T392
Test name
Test status
Simulation time 60785380279 ps
CPU time 107.8 seconds
Started Jun 21 06:24:39 PM PDT 24
Finished Jun 21 06:26:34 PM PDT 24
Peak memory 205436 kb
Host smart-6a7eae6f-71de-482f-8691-1f9676ea9b18
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920536442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1920536442
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2849719703
Short name T385
Test name
Test status
Simulation time 61805953060 ps
CPU time 167.53 seconds
Started Jun 21 06:24:39 PM PDT 24
Finished Jun 21 06:27:33 PM PDT 24
Peak memory 205456 kb
Host smart-7f42e588-23ca-4519-ae2b-e4787108f33f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849719703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.2849719703
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2901130987
Short name T401
Test name
Test status
Simulation time 6518060785 ps
CPU time 5.48 seconds
Started Jun 21 06:24:40 PM PDT 24
Finished Jun 21 06:24:53 PM PDT 24
Peak memory 205520 kb
Host smart-1845ec2c-497b-4a3f-a490-0507b79f9087
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901130987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2901130987
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3876626773
Short name T405
Test name
Test status
Simulation time 5420712861 ps
CPU time 2.05 seconds
Started Jun 21 06:24:37 PM PDT 24
Finished Jun 21 06:24:44 PM PDT 24
Peak memory 205452 kb
Host smart-74441506-d2de-4450-8621-13af3fe90230
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876626773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
876626773
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4193553197
Short name T303
Test name
Test status
Simulation time 881118717 ps
CPU time 2.77 seconds
Started Jun 21 06:24:43 PM PDT 24
Finished Jun 21 06:24:53 PM PDT 24
Peak memory 205148 kb
Host smart-c74387e0-06bd-4191-a0ab-942b7969dcca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193553197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.4193553197
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3547704752
Short name T298
Test name
Test status
Simulation time 169915219 ps
CPU time 1.1 seconds
Started Jun 21 06:24:39 PM PDT 24
Finished Jun 21 06:24:47 PM PDT 24
Peak memory 205188 kb
Host smart-7f0f4ac7-42f2-491b-a3ee-e267e6f0ae4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547704752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3547704752
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4057352698
Short name T300
Test name
Test status
Simulation time 456235238 ps
CPU time 1.36 seconds
Started Jun 21 06:24:36 PM PDT 24
Finished Jun 21 06:24:41 PM PDT 24
Peak memory 205252 kb
Host smart-6ec04775-f128-4105-b71a-fea470ec1328
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057352698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.4
057352698
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1400108399
Short name T267
Test name
Test status
Simulation time 55133264 ps
CPU time 0.66 seconds
Started Jun 21 06:24:45 PM PDT 24
Finished Jun 21 06:24:53 PM PDT 24
Peak memory 205116 kb
Host smart-2089c7bf-a426-49f1-b45d-f99b64a1c67d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400108399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1400108399
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1234441545
Short name T277
Test name
Test status
Simulation time 45162106 ps
CPU time 0.7 seconds
Started Jun 21 06:24:37 PM PDT 24
Finished Jun 21 06:24:43 PM PDT 24
Peak memory 205152 kb
Host smart-e0b44e01-be7e-435f-9ce7-47884a933f76
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234441545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1234441545
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1125321848
Short name T112
Test name
Test status
Simulation time 441204018 ps
CPU time 6.2 seconds
Started Jun 21 06:24:41 PM PDT 24
Finished Jun 21 06:24:55 PM PDT 24
Peak memory 205476 kb
Host smart-365d8fe7-aaab-44d0-be18-b3c2c2dde4d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125321848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1125321848
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2630842212
Short name T380
Test name
Test status
Simulation time 32986742924 ps
CPU time 97.52 seconds
Started Jun 21 06:24:43 PM PDT 24
Finished Jun 21 06:26:28 PM PDT 24
Peak memory 222012 kb
Host smart-94f38185-5165-4dac-8fe2-e5c32093e4db
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630842212 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.2630842212
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2142175676
Short name T306
Test name
Test status
Simulation time 1644980792 ps
CPU time 6.51 seconds
Started Jun 21 06:24:37 PM PDT 24
Finished Jun 21 06:24:48 PM PDT 24
Peak memory 213724 kb
Host smart-af60b5d3-1da3-4563-9225-47ecea0a5e0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142175676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2142175676
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1996724099
Short name T103
Test name
Test status
Simulation time 3470286196 ps
CPU time 70.86 seconds
Started Jun 21 06:24:45 PM PDT 24
Finished Jun 21 06:26:03 PM PDT 24
Peak memory 205684 kb
Host smart-7948f477-684e-445a-86fc-b5b06187743d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996724099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1996724099
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4024607392
Short name T106
Test name
Test status
Simulation time 1603428191 ps
CPU time 53.06 seconds
Started Jun 21 06:24:39 PM PDT 24
Finished Jun 21 06:25:39 PM PDT 24
Peak memory 205412 kb
Host smart-fc6975e8-2040-415d-aa82-cc877b5edde1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024607392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4024607392
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.569070725
Short name T279
Test name
Test status
Simulation time 1130011446 ps
CPU time 1.61 seconds
Started Jun 21 06:24:42 PM PDT 24
Finished Jun 21 06:24:51 PM PDT 24
Peak memory 213680 kb
Host smart-2fca00ec-f935-421b-9200-774002c754fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569070725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.569070725
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1564217322
Short name T116
Test name
Test status
Simulation time 6419468435 ps
CPU time 9.12 seconds
Started Jun 21 06:24:45 PM PDT 24
Finished Jun 21 06:25:01 PM PDT 24
Peak memory 220820 kb
Host smart-197cf32b-dd30-4a38-ba0b-a7650c4b7f34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564217322 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1564217322
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3049403962
Short name T414
Test name
Test status
Simulation time 303834182 ps
CPU time 2.37 seconds
Started Jun 21 06:24:38 PM PDT 24
Finished Jun 21 06:24:46 PM PDT 24
Peak memory 213648 kb
Host smart-40a4d78d-d732-4230-81a7-a4b0f3f443ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049403962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3049403962
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1141866805
Short name T262
Test name
Test status
Simulation time 66628285306 ps
CPU time 94.85 seconds
Started Jun 21 06:24:38 PM PDT 24
Finished Jun 21 06:26:20 PM PDT 24
Peak memory 205396 kb
Host smart-a07dde8b-b450-4b85-9a74-babf39304713
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141866805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1141866805
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2391127410
Short name T282
Test name
Test status
Simulation time 38650578334 ps
CPU time 58.89 seconds
Started Jun 21 06:24:44 PM PDT 24
Finished Jun 21 06:25:50 PM PDT 24
Peak memory 205484 kb
Host smart-2a0dd752-77bc-438e-9e7e-4cf1ed57d8d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391127410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.2391127410
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.178573523
Short name T366
Test name
Test status
Simulation time 8789189606 ps
CPU time 17.24 seconds
Started Jun 21 06:24:41 PM PDT 24
Finished Jun 21 06:25:06 PM PDT 24
Peak memory 205396 kb
Host smart-002bcdf8-ec18-433e-abe0-964ac5f20fe7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178573523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.178573523
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2534670391
Short name T275
Test name
Test status
Simulation time 1221235281 ps
CPU time 1.21 seconds
Started Jun 21 06:24:37 PM PDT 24
Finished Jun 21 06:24:41 PM PDT 24
Peak memory 205156 kb
Host smart-976b688f-216c-4ed1-8605-7bd93a643104
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534670391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2534670391
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2022370744
Short name T412
Test name
Test status
Simulation time 6847546781 ps
CPU time 10.31 seconds
Started Jun 21 06:24:40 PM PDT 24
Finished Jun 21 06:24:58 PM PDT 24
Peak memory 205456 kb
Host smart-6cb8d7e2-7aa2-4906-bffc-157140da6494
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022370744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2022370744
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.97328643
Short name T266
Test name
Test status
Simulation time 785013200 ps
CPU time 1.12 seconds
Started Jun 21 06:24:42 PM PDT 24
Finished Jun 21 06:24:51 PM PDT 24
Peak memory 205208 kb
Host smart-630f69f5-889d-40de-b575-e876d8d0078f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97328643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_
hw_reset.97328643
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.383253436
Short name T371
Test name
Test status
Simulation time 175701596 ps
CPU time 0.9 seconds
Started Jun 21 06:24:39 PM PDT 24
Finished Jun 21 06:24:48 PM PDT 24
Peak memory 205152 kb
Host smart-08b14a15-aeeb-4d50-aef0-f5dd066e55b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383253436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.383253436
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3388080897
Short name T281
Test name
Test status
Simulation time 118758106 ps
CPU time 0.89 seconds
Started Jun 21 06:24:42 PM PDT 24
Finished Jun 21 06:24:51 PM PDT 24
Peak memory 205028 kb
Host smart-134472dd-6c17-4db7-bb65-cc121d84450a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388080897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3388080897
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.146116117
Short name T312
Test name
Test status
Simulation time 95148780 ps
CPU time 0.71 seconds
Started Jun 21 06:24:38 PM PDT 24
Finished Jun 21 06:24:44 PM PDT 24
Peak memory 205152 kb
Host smart-d91ee686-f11d-473e-8737-0c7155741e3e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146116117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.146116117
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1315221159
Short name T356
Test name
Test status
Simulation time 487751597 ps
CPU time 6.83 seconds
Started Jun 21 06:24:38 PM PDT 24
Finished Jun 21 06:24:52 PM PDT 24
Peak memory 205564 kb
Host smart-f210ceb6-2327-42db-9cd9-0bad167196b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315221159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1315221159
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.867883257
Short name T121
Test name
Test status
Simulation time 88719840830 ps
CPU time 60.81 seconds
Started Jun 21 06:24:39 PM PDT 24
Finished Jun 21 06:25:47 PM PDT 24
Peak memory 221764 kb
Host smart-65621351-ac75-4252-aac2-e89c7ac3aa2b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867883257 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.867883257
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.4222803927
Short name T318
Test name
Test status
Simulation time 683219115 ps
CPU time 4.74 seconds
Started Jun 21 06:24:40 PM PDT 24
Finished Jun 21 06:24:52 PM PDT 24
Peak memory 213744 kb
Host smart-0200450a-4e5f-476b-9fea-6674ddae72ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222803927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.4222803927
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3034734786
Short name T310
Test name
Test status
Simulation time 608910848 ps
CPU time 3.41 seconds
Started Jun 21 06:24:58 PM PDT 24
Finished Jun 21 06:25:04 PM PDT 24
Peak memory 218412 kb
Host smart-d7ec12f5-87a7-4a14-a0bd-a0e491359cfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034734786 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3034734786
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4085004564
Short name T107
Test name
Test status
Simulation time 128805198 ps
CPU time 1.48 seconds
Started Jun 21 06:24:59 PM PDT 24
Finished Jun 21 06:25:03 PM PDT 24
Peak memory 213664 kb
Host smart-aa10c7e2-eed9-4592-8d96-0200d32579dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085004564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.4085004564
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3794934213
Short name T278
Test name
Test status
Simulation time 15050180838 ps
CPU time 10.18 seconds
Started Jun 21 06:24:58 PM PDT 24
Finished Jun 21 06:25:11 PM PDT 24
Peak memory 205540 kb
Host smart-cb8753a3-888b-4f38-9043-11c7f4e956a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794934213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.3794934213
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3646848832
Short name T323
Test name
Test status
Simulation time 3597438688 ps
CPU time 2.25 seconds
Started Jun 21 06:24:58 PM PDT 24
Finished Jun 21 06:25:04 PM PDT 24
Peak memory 205452 kb
Host smart-262afc6e-c84a-4974-a6ec-53534131761c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646848832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3646848832
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3348252174
Short name T377
Test name
Test status
Simulation time 193199706 ps
CPU time 0.85 seconds
Started Jun 21 06:24:58 PM PDT 24
Finished Jun 21 06:25:02 PM PDT 24
Peak memory 205088 kb
Host smart-39fcd299-cd39-42aa-b924-1875981397dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348252174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3348252174
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3209365709
Short name T105
Test name
Test status
Simulation time 95472727 ps
CPU time 3.67 seconds
Started Jun 21 06:24:59 PM PDT 24
Finished Jun 21 06:25:05 PM PDT 24
Peak memory 205544 kb
Host smart-b19ff80c-c632-41c3-a774-9fbc1bf7710b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209365709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3209365709
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3253908248
Short name T343
Test name
Test status
Simulation time 508412563 ps
CPU time 2.99 seconds
Started Jun 21 06:25:02 PM PDT 24
Finished Jun 21 06:25:07 PM PDT 24
Peak memory 213728 kb
Host smart-ae6439e5-da3f-4181-9faa-d14df4b24ae7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253908248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3253908248
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3207987016
Short name T415
Test name
Test status
Simulation time 3677718930 ps
CPU time 20.71 seconds
Started Jun 21 06:24:59 PM PDT 24
Finished Jun 21 06:25:23 PM PDT 24
Peak memory 213732 kb
Host smart-e00a12eb-5f69-44f5-b889-deb10b61706c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207987016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
207987016
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.577209069
Short name T410
Test name
Test status
Simulation time 2946508431 ps
CPU time 6.71 seconds
Started Jun 21 06:24:59 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 213916 kb
Host smart-588e5697-bb61-4666-b8ef-73160528f8cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577209069 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.577209069
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3649061191
Short name T381
Test name
Test status
Simulation time 419921096 ps
CPU time 1.61 seconds
Started Jun 21 06:24:59 PM PDT 24
Finished Jun 21 06:25:04 PM PDT 24
Peak memory 213660 kb
Host smart-f147269a-999f-4043-842a-93fca697a751
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649061191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3649061191
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2054954680
Short name T361
Test name
Test status
Simulation time 7200475388 ps
CPU time 11.01 seconds
Started Jun 21 06:25:00 PM PDT 24
Finished Jun 21 06:25:14 PM PDT 24
Peak memory 205452 kb
Host smart-a0ed8598-ebf5-4342-a514-534821d619f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054954680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.2054954680
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2857619268
Short name T347
Test name
Test status
Simulation time 1255636699 ps
CPU time 4.24 seconds
Started Jun 21 06:25:00 PM PDT 24
Finished Jun 21 06:25:07 PM PDT 24
Peak memory 205340 kb
Host smart-4ba7d40b-3272-4421-97f5-5c4ed1f50f47
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857619268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2857619268
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2290945894
Short name T70
Test name
Test status
Simulation time 332045575 ps
CPU time 1.45 seconds
Started Jun 21 06:24:58 PM PDT 24
Finished Jun 21 06:25:03 PM PDT 24
Peak memory 205152 kb
Host smart-11fd0ebb-2239-4182-ac6e-8210e581ab5a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290945894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2290945894
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.992324807
Short name T346
Test name
Test status
Simulation time 420744590 ps
CPU time 4.08 seconds
Started Jun 21 06:25:00 PM PDT 24
Finished Jun 21 06:25:07 PM PDT 24
Peak memory 205464 kb
Host smart-fa9ec8dd-e5d5-4b9d-a8c6-3b8e6e666e48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992324807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.992324807
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1726289790
Short name T269
Test name
Test status
Simulation time 86514616 ps
CPU time 3.15 seconds
Started Jun 21 06:25:01 PM PDT 24
Finished Jun 21 06:25:06 PM PDT 24
Peak memory 213632 kb
Host smart-1576bac8-b9e8-46be-a8c6-c22aa9e31b0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726289790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1726289790
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2654046111
Short name T391
Test name
Test status
Simulation time 95047182 ps
CPU time 2.41 seconds
Started Jun 21 06:24:57 PM PDT 24
Finished Jun 21 06:25:03 PM PDT 24
Peak memory 213796 kb
Host smart-b18b9d4a-907f-4f5f-bf38-d0342dd1e1bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654046111 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2654046111
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3699028853
Short name T394
Test name
Test status
Simulation time 204573624 ps
CPU time 1.54 seconds
Started Jun 21 06:24:59 PM PDT 24
Finished Jun 21 06:25:04 PM PDT 24
Peak memory 213680 kb
Host smart-2daf3f22-657f-47ae-adf4-4a0bf08321df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699028853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3699028853
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3158549225
Short name T264
Test name
Test status
Simulation time 5760918025 ps
CPU time 6.11 seconds
Started Jun 21 06:24:58 PM PDT 24
Finished Jun 21 06:25:08 PM PDT 24
Peak memory 205624 kb
Host smart-49510c7a-a860-4301-ae65-4be725ada420
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158549225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3158549225
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1338291319
Short name T263
Test name
Test status
Simulation time 4022197464 ps
CPU time 3.86 seconds
Started Jun 21 06:25:02 PM PDT 24
Finished Jun 21 06:25:07 PM PDT 24
Peak memory 205504 kb
Host smart-a97ea15e-43b9-4d17-8cd0-af5ea73f875f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338291319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1338291319
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.166627440
Short name T331
Test name
Test status
Simulation time 517433849 ps
CPU time 1.67 seconds
Started Jun 21 06:24:57 PM PDT 24
Finished Jun 21 06:25:03 PM PDT 24
Peak memory 205160 kb
Host smart-504fe558-9758-4c77-a5e8-5a0105c3eab0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166627440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.166627440
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.782597614
Short name T111
Test name
Test status
Simulation time 2297588210 ps
CPU time 8.49 seconds
Started Jun 21 06:24:57 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 205604 kb
Host smart-ffdb668c-75b6-4a90-9d12-99054fce53ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782597614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.782597614
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2705548777
Short name T81
Test name
Test status
Simulation time 335753143 ps
CPU time 4.05 seconds
Started Jun 21 06:24:56 PM PDT 24
Finished Jun 21 06:25:04 PM PDT 24
Peak memory 216320 kb
Host smart-e75fd7c8-df83-4790-80d7-e6588cd60221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705548777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2705548777
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.754776567
Short name T90
Test name
Test status
Simulation time 1898082897 ps
CPU time 15.9 seconds
Started Jun 21 06:25:01 PM PDT 24
Finished Jun 21 06:25:19 PM PDT 24
Peak memory 213672 kb
Host smart-46b3d109-58b5-4fcc-bb32-6f75382e11aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754776567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.754776567
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1623136016
Short name T400
Test name
Test status
Simulation time 346467125 ps
CPU time 3.5 seconds
Started Jun 21 06:25:04 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 216788 kb
Host smart-325bfd3d-ef9a-4f8f-adb1-39ff7ae905b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623136016 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1623136016
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1110156728
Short name T335
Test name
Test status
Simulation time 136169329 ps
CPU time 1.69 seconds
Started Jun 21 06:25:05 PM PDT 24
Finished Jun 21 06:25:08 PM PDT 24
Peak memory 213680 kb
Host smart-93f72637-c878-4579-970f-9c52f1919d53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110156728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1110156728
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3817433785
Short name T295
Test name
Test status
Simulation time 24879363222 ps
CPU time 26.23 seconds
Started Jun 21 06:25:01 PM PDT 24
Finished Jun 21 06:25:30 PM PDT 24
Peak memory 205456 kb
Host smart-d9a81aab-c678-4b78-9f9f-eeb9b6722795
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817433785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.3817433785
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1666820240
Short name T353
Test name
Test status
Simulation time 8407311445 ps
CPU time 12.77 seconds
Started Jun 21 06:24:59 PM PDT 24
Finished Jun 21 06:25:15 PM PDT 24
Peak memory 205452 kb
Host smart-23006a2d-c587-419e-86ef-81a0bc11bf3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666820240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1666820240
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3727520598
Short name T68
Test name
Test status
Simulation time 106649458 ps
CPU time 0.81 seconds
Started Jun 21 06:24:59 PM PDT 24
Finished Jun 21 06:25:03 PM PDT 24
Peak memory 205132 kb
Host smart-07f6233e-0950-4913-9759-6e7cfa6bf954
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727520598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3727520598
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1326659570
Short name T89
Test name
Test status
Simulation time 177221639 ps
CPU time 6.47 seconds
Started Jun 21 06:25:05 PM PDT 24
Finished Jun 21 06:25:13 PM PDT 24
Peak memory 205464 kb
Host smart-f08438ee-0dc3-421b-bf87-b427c89a38fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326659570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1326659570
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2826474984
Short name T283
Test name
Test status
Simulation time 325737435 ps
CPU time 6.01 seconds
Started Jun 21 06:25:12 PM PDT 24
Finished Jun 21 06:25:19 PM PDT 24
Peak memory 213700 kb
Host smart-dd5ff93d-2f00-49b2-935b-5d194121ceb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826474984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2826474984
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1552742381
Short name T328
Test name
Test status
Simulation time 2480674107 ps
CPU time 11.34 seconds
Started Jun 21 06:25:04 PM PDT 24
Finished Jun 21 06:25:17 PM PDT 24
Peak memory 221904 kb
Host smart-3b549581-1c7f-4da1-9e5c-b4ce33bee165
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552742381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
552742381
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2546362315
Short name T296
Test name
Test status
Simulation time 310918253 ps
CPU time 2.45 seconds
Started Jun 21 06:25:04 PM PDT 24
Finished Jun 21 06:25:08 PM PDT 24
Peak memory 217264 kb
Host smart-04226e4e-30c1-4bb6-9391-530bcc47489e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546362315 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2546362315
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4094051785
Short name T336
Test name
Test status
Simulation time 3473895094 ps
CPU time 4.03 seconds
Started Jun 21 06:25:03 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 205420 kb
Host smart-2a4c0133-bb3b-4e11-bbfd-87ed01effbd7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094051785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.4094051785
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2007670774
Short name T376
Test name
Test status
Simulation time 1735970920 ps
CPU time 1.49 seconds
Started Jun 21 06:25:05 PM PDT 24
Finished Jun 21 06:25:07 PM PDT 24
Peak memory 205384 kb
Host smart-2bddc298-ae58-43f0-9682-de147f2359b4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007670774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2007670774
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3175471046
Short name T334
Test name
Test status
Simulation time 508199761 ps
CPU time 1.23 seconds
Started Jun 21 06:25:03 PM PDT 24
Finished Jun 21 06:25:06 PM PDT 24
Peak memory 205132 kb
Host smart-00685bf1-2660-467d-83b2-2955ba8154da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175471046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
3175471046
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3660256513
Short name T407
Test name
Test status
Simulation time 602122597 ps
CPU time 6.51 seconds
Started Jun 21 06:25:04 PM PDT 24
Finished Jun 21 06:25:12 PM PDT 24
Peak memory 205524 kb
Host smart-f4d92e8e-08bb-44b5-a46e-0f96b3655c10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660256513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3660256513
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3642046564
Short name T270
Test name
Test status
Simulation time 503281685 ps
CPU time 4.18 seconds
Started Jun 21 06:25:05 PM PDT 24
Finished Jun 21 06:25:10 PM PDT 24
Peak memory 213732 kb
Host smart-d23f11db-9ff1-43f8-b876-7a096e6e1640
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642046564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3642046564
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1897884183
Short name T130
Test name
Test status
Simulation time 6308522128 ps
CPU time 23.04 seconds
Started Jun 21 06:25:12 PM PDT 24
Finished Jun 21 06:25:37 PM PDT 24
Peak memory 213692 kb
Host smart-dfd96154-e0a1-4718-9bcb-5bc2037c3592
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897884183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
897884183
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3831437912
Short name T396
Test name
Test status
Simulation time 3661296600 ps
CPU time 7.98 seconds
Started Jun 21 06:25:04 PM PDT 24
Finished Jun 21 06:25:14 PM PDT 24
Peak memory 218308 kb
Host smart-11d177dd-d02c-494b-98ce-4ad228ff5c7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831437912 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3831437912
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.4246089055
Short name T349
Test name
Test status
Simulation time 2148030603 ps
CPU time 2.85 seconds
Started Jun 21 06:25:10 PM PDT 24
Finished Jun 21 06:25:14 PM PDT 24
Peak memory 205456 kb
Host smart-1f4a0235-ddbb-4444-bcd2-5c2d3c6ae0f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246089055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.4246089055
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.74046055
Short name T387
Test name
Test status
Simulation time 3130089487 ps
CPU time 4.75 seconds
Started Jun 21 06:25:09 PM PDT 24
Finished Jun 21 06:25:15 PM PDT 24
Peak memory 205456 kb
Host smart-45b79299-fb75-4243-9654-761f84d04047
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74046055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.74046055
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2453816997
Short name T416
Test name
Test status
Simulation time 1344178095 ps
CPU time 1.58 seconds
Started Jun 21 06:25:08 PM PDT 24
Finished Jun 21 06:25:10 PM PDT 24
Peak memory 205152 kb
Host smart-862f200a-84c3-4a7f-a503-a418010606e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453816997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2453816997
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4128530307
Short name T88
Test name
Test status
Simulation time 809389617 ps
CPU time 4.15 seconds
Started Jun 21 06:25:03 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 205524 kb
Host smart-899f7239-2c2e-4767-b793-7a9847dbf98c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128530307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.4128530307
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2519023545
Short name T285
Test name
Test status
Simulation time 1295952811 ps
CPU time 6.75 seconds
Started Jun 21 06:25:05 PM PDT 24
Finished Jun 21 06:25:14 PM PDT 24
Peak memory 213696 kb
Host smart-cbc9f219-e182-4f7a-afc3-c5ebd025ff28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519023545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2519023545
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2908494089
Short name T383
Test name
Test status
Simulation time 4384012590 ps
CPU time 8.74 seconds
Started Jun 21 06:25:04 PM PDT 24
Finished Jun 21 06:25:14 PM PDT 24
Peak memory 213808 kb
Host smart-b3c28e3e-a99d-4a4a-9d6d-1d5294cc17c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908494089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
908494089
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1697738557
Short name T272
Test name
Test status
Simulation time 4327243981 ps
CPU time 2.53 seconds
Started Jun 21 06:25:04 PM PDT 24
Finished Jun 21 06:25:08 PM PDT 24
Peak memory 219496 kb
Host smart-9e1e36b6-09ad-46d1-8e0e-0ef120a4e844
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697738557 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1697738557
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3867359629
Short name T109
Test name
Test status
Simulation time 102150957 ps
CPU time 2.46 seconds
Started Jun 21 06:25:07 PM PDT 24
Finished Jun 21 06:25:10 PM PDT 24
Peak memory 213652 kb
Host smart-317e1044-5550-40e3-b906-be04fd654626
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867359629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3867359629
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1334781969
Short name T357
Test name
Test status
Simulation time 12552421672 ps
CPU time 34.93 seconds
Started Jun 21 06:25:10 PM PDT 24
Finished Jun 21 06:25:46 PM PDT 24
Peak memory 205440 kb
Host smart-af0a3e78-c061-42bd-9e68-f26b3ce21e8a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334781969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.1334781969
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3253679421
Short name T268
Test name
Test status
Simulation time 2946676599 ps
CPU time 1.84 seconds
Started Jun 21 06:25:05 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 205472 kb
Host smart-4d238aae-8a9f-443e-9c02-08f6cac30a4b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253679421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3253679421
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3031034191
Short name T324
Test name
Test status
Simulation time 891488483 ps
CPU time 1.81 seconds
Started Jun 21 06:25:11 PM PDT 24
Finished Jun 21 06:25:14 PM PDT 24
Peak memory 205120 kb
Host smart-218fb9ad-6f5e-4097-849d-2695cc6f7712
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031034191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3031034191
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.220040231
Short name T403
Test name
Test status
Simulation time 270546499 ps
CPU time 4.3 seconds
Started Jun 21 06:25:04 PM PDT 24
Finished Jun 21 06:25:10 PM PDT 24
Peak memory 205420 kb
Host smart-69447e2c-9e31-4ce8-b243-6d305724ff87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220040231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.220040231
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3751631710
Short name T329
Test name
Test status
Simulation time 333884334 ps
CPU time 2.39 seconds
Started Jun 21 06:25:05 PM PDT 24
Finished Jun 21 06:25:08 PM PDT 24
Peak memory 213752 kb
Host smart-622d7964-3dd9-4d0a-91f9-5883fe3f0549
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751631710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3751631710
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2071463517
Short name T125
Test name
Test status
Simulation time 2441335546 ps
CPU time 17.93 seconds
Started Jun 21 06:25:05 PM PDT 24
Finished Jun 21 06:25:24 PM PDT 24
Peak memory 213788 kb
Host smart-cd992c4e-5c65-4835-b0b7-9ff52be45085
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071463517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
071463517
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2158534990
Short name T393
Test name
Test status
Simulation time 756843110 ps
CPU time 2.96 seconds
Started Jun 21 06:25:08 PM PDT 24
Finished Jun 21 06:25:11 PM PDT 24
Peak memory 213732 kb
Host smart-081f7034-7419-44be-ac30-7185c22e77c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158534990 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2158534990
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2901253621
Short name T302
Test name
Test status
Simulation time 104907001 ps
CPU time 2.33 seconds
Started Jun 21 06:25:05 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 213696 kb
Host smart-fbe5f11d-60d3-42b5-918d-215ab30d01c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901253621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2901253621
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.367034734
Short name T304
Test name
Test status
Simulation time 2654952468 ps
CPU time 4.4 seconds
Started Jun 21 06:25:02 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 205452 kb
Host smart-4ae5cf34-0b3e-4533-97df-e1e0f28d8b3f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367034734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.367034734
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3620111211
Short name T316
Test name
Test status
Simulation time 2191242854 ps
CPU time 7.52 seconds
Started Jun 21 06:25:04 PM PDT 24
Finished Jun 21 06:25:13 PM PDT 24
Peak memory 205452 kb
Host smart-6c2892d2-a3f5-481a-a712-fca99ce23059
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620111211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3620111211
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.5803103
Short name T271
Test name
Test status
Simulation time 1079781519 ps
CPU time 1.38 seconds
Started Jun 21 06:25:06 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 205144 kb
Host smart-17bc535b-b51f-40e7-a685-705e01c8582b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5803103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.5803103
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.4060826130
Short name T374
Test name
Test status
Simulation time 56204025 ps
CPU time 2.6 seconds
Started Jun 21 06:25:02 PM PDT 24
Finished Jun 21 06:25:07 PM PDT 24
Peak memory 213688 kb
Host smart-80d2a3a3-64a5-47e7-89e2-c9d471dac69d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060826130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.4060826130
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3275505619
Short name T124
Test name
Test status
Simulation time 1005057420 ps
CPU time 10.21 seconds
Started Jun 21 06:25:12 PM PDT 24
Finished Jun 21 06:25:24 PM PDT 24
Peak memory 213580 kb
Host smart-c5e7edbf-4bed-4cc7-9f46-e342e73db7f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275505619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
275505619
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.898090841
Short name T398
Test name
Test status
Simulation time 2214261718 ps
CPU time 6.71 seconds
Started Jun 21 06:25:11 PM PDT 24
Finished Jun 21 06:25:19 PM PDT 24
Peak memory 221968 kb
Host smart-eaad9893-27e2-420e-a8c1-bbc26457a423
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898090841 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.898090841
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3605558383
Short name T404
Test name
Test status
Simulation time 347572168 ps
CPU time 2.3 seconds
Started Jun 21 06:25:11 PM PDT 24
Finished Jun 21 06:25:14 PM PDT 24
Peak memory 213784 kb
Host smart-e754a87a-3418-4a9e-8e91-07d4644a4229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605558383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3605558383
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3597621529
Short name T261
Test name
Test status
Simulation time 34097712424 ps
CPU time 43.96 seconds
Started Jun 21 06:25:11 PM PDT 24
Finished Jun 21 06:25:56 PM PDT 24
Peak memory 205448 kb
Host smart-8d8c7dc3-2ab5-4683-b4e9-4f5fa823fd83
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597621529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.3597621529
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1105499962
Short name T352
Test name
Test status
Simulation time 2740636433 ps
CPU time 3.33 seconds
Started Jun 21 06:25:11 PM PDT 24
Finished Jun 21 06:25:15 PM PDT 24
Peak memory 205420 kb
Host smart-eb0b17c8-e90c-48ed-82b0-2472e1cc6257
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105499962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1105499962
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1799850959
Short name T390
Test name
Test status
Simulation time 267069472 ps
CPU time 0.77 seconds
Started Jun 21 06:25:04 PM PDT 24
Finished Jun 21 06:25:06 PM PDT 24
Peak memory 205148 kb
Host smart-ef4e51c2-b51e-478a-a0d4-8344a907d009
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799850959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1799850959
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.4089770379
Short name T102
Test name
Test status
Simulation time 314381634 ps
CPU time 3.82 seconds
Started Jun 21 06:25:13 PM PDT 24
Finished Jun 21 06:25:18 PM PDT 24
Peak memory 205460 kb
Host smart-520ff46f-d4e6-495e-8d2d-975f09412212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089770379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.4089770379
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1776453110
Short name T71
Test name
Test status
Simulation time 563940097 ps
CPU time 3.31 seconds
Started Jun 21 06:25:10 PM PDT 24
Finished Jun 21 06:25:14 PM PDT 24
Peak memory 213732 kb
Host smart-be10996c-8163-43d3-81c0-2a1a9fa682cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776453110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1776453110
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3214179680
Short name T339
Test name
Test status
Simulation time 1105551546 ps
CPU time 3.69 seconds
Started Jun 21 06:25:16 PM PDT 24
Finished Jun 21 06:25:20 PM PDT 24
Peak memory 221888 kb
Host smart-c639b7d8-e06e-4655-9799-9151aa4128d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214179680 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3214179680
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.857644763
Short name T307
Test name
Test status
Simulation time 177675487 ps
CPU time 2.3 seconds
Started Jun 21 06:25:13 PM PDT 24
Finished Jun 21 06:25:16 PM PDT 24
Peak memory 213604 kb
Host smart-1a71f053-b43c-40dc-ae2c-47c0fbf06a11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857644763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.857644763
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2610883484
Short name T375
Test name
Test status
Simulation time 77921370199 ps
CPU time 225.31 seconds
Started Jun 21 06:25:11 PM PDT 24
Finished Jun 21 06:28:57 PM PDT 24
Peak memory 205460 kb
Host smart-0d8bbcdd-05c8-494c-9ed5-4192dd768f4f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610883484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2610883484
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3029397752
Short name T337
Test name
Test status
Simulation time 3131597715 ps
CPU time 9.77 seconds
Started Jun 21 06:25:11 PM PDT 24
Finished Jun 21 06:25:22 PM PDT 24
Peak memory 205452 kb
Host smart-25c1b6b3-53c7-40f1-8a38-13780025ff13
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029397752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3029397752
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4242253940
Short name T314
Test name
Test status
Simulation time 470948053 ps
CPU time 1 seconds
Started Jun 21 06:25:12 PM PDT 24
Finished Jun 21 06:25:14 PM PDT 24
Peak memory 205152 kb
Host smart-a16aaaeb-7a7f-46e5-8fa8-25c8887dd774
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242253940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
4242253940
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.893313074
Short name T389
Test name
Test status
Simulation time 7223532432 ps
CPU time 8.04 seconds
Started Jun 21 06:25:10 PM PDT 24
Finished Jun 21 06:25:20 PM PDT 24
Peak memory 205576 kb
Host smart-356fc21a-ff16-477d-b126-87a0af62f774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893313074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.893313074
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.4150176521
Short name T397
Test name
Test status
Simulation time 376007634 ps
CPU time 5.68 seconds
Started Jun 21 06:25:13 PM PDT 24
Finished Jun 21 06:25:19 PM PDT 24
Peak memory 213796 kb
Host smart-2d18c99a-6103-47d5-ae3d-b2d99da3024b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150176521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.4150176521
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2552762793
Short name T348
Test name
Test status
Simulation time 1620101941 ps
CPU time 11.4 seconds
Started Jun 21 06:25:12 PM PDT 24
Finished Jun 21 06:25:25 PM PDT 24
Peak memory 213636 kb
Host smart-5bf40676-1ad0-4632-959f-74319d5a28ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552762793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
552762793
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2597976684
Short name T87
Test name
Test status
Simulation time 1192923275 ps
CPU time 63.3 seconds
Started Jun 21 06:24:38 PM PDT 24
Finished Jun 21 06:25:47 PM PDT 24
Peak memory 213696 kb
Host smart-019f0e86-9d6c-4f1a-927b-b94c8977d3ad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597976684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2597976684
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.208396778
Short name T354
Test name
Test status
Simulation time 6420341341 ps
CPU time 37.94 seconds
Started Jun 21 06:24:45 PM PDT 24
Finished Jun 21 06:25:30 PM PDT 24
Peak memory 213776 kb
Host smart-74adb2c1-a11c-40d2-9db1-94f737f2637c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208396778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.208396778
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2415372037
Short name T305
Test name
Test status
Simulation time 386392645 ps
CPU time 2.61 seconds
Started Jun 21 06:24:44 PM PDT 24
Finished Jun 21 06:24:54 PM PDT 24
Peak memory 213792 kb
Host smart-8c794612-da02-4382-86ed-69793ad5b351
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415372037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2415372037
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.26101445
Short name T322
Test name
Test status
Simulation time 68885014 ps
CPU time 2.8 seconds
Started Jun 21 06:24:44 PM PDT 24
Finished Jun 21 06:24:54 PM PDT 24
Peak memory 213744 kb
Host smart-28e4ab1b-b724-4241-9fba-690a4bc0618f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26101445 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.26101445
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1750581893
Short name T332
Test name
Test status
Simulation time 259888307 ps
CPU time 1.59 seconds
Started Jun 21 06:24:46 PM PDT 24
Finished Jun 21 06:24:55 PM PDT 24
Peak memory 213680 kb
Host smart-79f42b5d-6a48-4320-a9cd-f954a54d2a6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750581893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1750581893
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.4249079351
Short name T379
Test name
Test status
Simulation time 35012070444 ps
CPU time 22.34 seconds
Started Jun 21 06:24:50 PM PDT 24
Finished Jun 21 06:25:19 PM PDT 24
Peak memory 205396 kb
Host smart-9d82b40c-eb1a-412d-969a-dad63d028cb0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249079351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.4249079351
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1603780595
Short name T319
Test name
Test status
Simulation time 108612886293 ps
CPU time 276.87 seconds
Started Jun 21 06:24:44 PM PDT 24
Finished Jun 21 06:29:28 PM PDT 24
Peak memory 205456 kb
Host smart-b6c6ec1e-cd15-4471-813e-0cad01bba0f7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603780595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1603780595
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3134647140
Short name T96
Test name
Test status
Simulation time 9608953230 ps
CPU time 24.03 seconds
Started Jun 21 06:24:45 PM PDT 24
Finished Jun 21 06:25:17 PM PDT 24
Peak memory 205580 kb
Host smart-55954fe2-c5f4-49bf-8699-d7fbce97807c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134647140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3134647140
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1620529741
Short name T408
Test name
Test status
Simulation time 2962153700 ps
CPU time 4.63 seconds
Started Jun 21 06:24:46 PM PDT 24
Finished Jun 21 06:24:58 PM PDT 24
Peak memory 205472 kb
Host smart-7a175b57-ea36-4a86-a5a0-aa03b90aff3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620529741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
620529741
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2995592921
Short name T69
Test name
Test status
Simulation time 727837655 ps
CPU time 2.75 seconds
Started Jun 21 06:24:43 PM PDT 24
Finished Jun 21 06:24:53 PM PDT 24
Peak memory 205156 kb
Host smart-c54079b3-7e33-4f70-94c8-92b32711df03
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995592921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2995592921
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1807889248
Short name T358
Test name
Test status
Simulation time 16398425400 ps
CPU time 43.36 seconds
Started Jun 21 06:24:47 PM PDT 24
Finished Jun 21 06:25:37 PM PDT 24
Peak memory 205564 kb
Host smart-bad0798b-fb2f-43da-a683-3cc11abd105c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807889248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1807889248
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2943277951
Short name T289
Test name
Test status
Simulation time 145753504 ps
CPU time 0.82 seconds
Started Jun 21 06:24:38 PM PDT 24
Finished Jun 21 06:24:45 PM PDT 24
Peak memory 205180 kb
Host smart-2982fd0d-ef78-455e-99d9-579b2bbae9b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943277951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2943277951
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1282192855
Short name T265
Test name
Test status
Simulation time 1122196559 ps
CPU time 1.47 seconds
Started Jun 21 06:24:44 PM PDT 24
Finished Jun 21 06:24:52 PM PDT 24
Peak memory 205176 kb
Host smart-84bb345e-4897-4b78-b766-13104a8c746b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282192855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
282192855
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1051924396
Short name T359
Test name
Test status
Simulation time 125764907 ps
CPU time 0.95 seconds
Started Jun 21 06:24:51 PM PDT 24
Finished Jun 21 06:24:58 PM PDT 24
Peak memory 205024 kb
Host smart-eebe6865-9d7f-4fc6-88e3-35d028ea5b4a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051924396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1051924396
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4221513765
Short name T345
Test name
Test status
Simulation time 53700233 ps
CPU time 0.77 seconds
Started Jun 21 06:24:45 PM PDT 24
Finished Jun 21 06:24:52 PM PDT 24
Peak memory 205152 kb
Host smart-a83b9a61-5891-423a-ad11-a7fbf9a15073
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221513765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.4221513765
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2737360507
Short name T327
Test name
Test status
Simulation time 233563246 ps
CPU time 4.04 seconds
Started Jun 21 06:24:45 PM PDT 24
Finished Jun 21 06:24:56 PM PDT 24
Peak memory 205484 kb
Host smart-81d3007a-9f0d-476f-b7f2-8018a77dfde7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737360507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2737360507
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2636507696
Short name T311
Test name
Test status
Simulation time 535858244 ps
CPU time 2.65 seconds
Started Jun 21 06:24:48 PM PDT 24
Finished Jun 21 06:24:57 PM PDT 24
Peak memory 213752 kb
Host smart-881ef0e2-fa08-447d-8dd4-516c56dff975
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636507696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2636507696
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.930504915
Short name T131
Test name
Test status
Simulation time 2498413901 ps
CPU time 15.39 seconds
Started Jun 21 06:24:50 PM PDT 24
Finished Jun 21 06:25:12 PM PDT 24
Peak memory 213772 kb
Host smart-853410b5-d400-4979-a9e4-b481557e75de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930504915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.930504915
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3610175510
Short name T301
Test name
Test status
Simulation time 1476264592 ps
CPU time 66.02 seconds
Started Jun 21 06:24:45 PM PDT 24
Finished Jun 21 06:25:58 PM PDT 24
Peak memory 205488 kb
Host smart-1f8da561-8d74-4383-bc90-cb49c5652927
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610175510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3610175510
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.140015405
Short name T351
Test name
Test status
Simulation time 91282425535 ps
CPU time 79.62 seconds
Started Jun 21 06:24:44 PM PDT 24
Finished Jun 21 06:26:11 PM PDT 24
Peak memory 213804 kb
Host smart-01e29ac1-7c61-4e56-ab50-8cc2a700acea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140015405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.140015405
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1377750150
Short name T386
Test name
Test status
Simulation time 370273716 ps
CPU time 1.74 seconds
Started Jun 21 06:24:45 PM PDT 24
Finished Jun 21 06:24:54 PM PDT 24
Peak memory 213716 kb
Host smart-95c9a2e3-5a74-4d5e-95f0-bcf39e183869
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377750150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1377750150
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2534279866
Short name T284
Test name
Test status
Simulation time 156132660 ps
CPU time 2.7 seconds
Started Jun 21 06:24:44 PM PDT 24
Finished Jun 21 06:24:54 PM PDT 24
Peak memory 219780 kb
Host smart-ef364a7f-4e39-4b5a-9cb5-facd369e9dcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534279866 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2534279866
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2740933520
Short name T330
Test name
Test status
Simulation time 151350717 ps
CPU time 2.09 seconds
Started Jun 21 06:24:49 PM PDT 24
Finished Jun 21 06:24:58 PM PDT 24
Peak memory 213484 kb
Host smart-f66f6dcb-07bf-446f-a10a-82cc54c69d8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740933520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2740933520
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3218427860
Short name T286
Test name
Test status
Simulation time 120879131279 ps
CPU time 286.77 seconds
Started Jun 21 06:24:46 PM PDT 24
Finished Jun 21 06:29:40 PM PDT 24
Peak memory 205400 kb
Host smart-b1491761-af36-4595-96e0-ee1b067f1514
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218427860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3218427860
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1203031837
Short name T378
Test name
Test status
Simulation time 36769355530 ps
CPU time 27.2 seconds
Started Jun 21 06:24:48 PM PDT 24
Finished Jun 21 06:25:22 PM PDT 24
Peak memory 205456 kb
Host smart-d1149a1e-2f7e-46be-8b23-8544a7e22f52
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203031837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.1203031837
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2397959001
Short name T98
Test name
Test status
Simulation time 15603739197 ps
CPU time 7.75 seconds
Started Jun 21 06:24:47 PM PDT 24
Finished Jun 21 06:25:02 PM PDT 24
Peak memory 205584 kb
Host smart-eba23bb2-f9ee-4745-9501-16d218f62652
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397959001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2397959001
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3059761409
Short name T276
Test name
Test status
Simulation time 4614638897 ps
CPU time 7.58 seconds
Started Jun 21 06:24:45 PM PDT 24
Finished Jun 21 06:25:00 PM PDT 24
Peak memory 205436 kb
Host smart-c63fc390-8cb5-41d5-af6e-b9f4041d13f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059761409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
059761409
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.147204560
Short name T325
Test name
Test status
Simulation time 792386735 ps
CPU time 1.22 seconds
Started Jun 21 06:24:44 PM PDT 24
Finished Jun 21 06:24:52 PM PDT 24
Peak memory 205152 kb
Host smart-f9266b2a-9ba5-478f-90d9-0354ba143da4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147204560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.147204560
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2979608557
Short name T413
Test name
Test status
Simulation time 22110258605 ps
CPU time 12.19 seconds
Started Jun 21 06:24:49 PM PDT 24
Finished Jun 21 06:25:08 PM PDT 24
Peak memory 205360 kb
Host smart-22e525da-745e-4f5d-b884-da26e9c9c46b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979608557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2979608557
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.668081282
Short name T395
Test name
Test status
Simulation time 947692654 ps
CPU time 3.13 seconds
Started Jun 21 06:24:46 PM PDT 24
Finished Jun 21 06:24:56 PM PDT 24
Peak memory 205152 kb
Host smart-3ea0c10f-7800-4642-b1b4-4183263e7572
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668081282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.668081282
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1448194380
Short name T362
Test name
Test status
Simulation time 106108952 ps
CPU time 0.8 seconds
Started Jun 21 06:24:45 PM PDT 24
Finished Jun 21 06:24:53 PM PDT 24
Peak memory 205132 kb
Host smart-149c94ec-9737-4efb-8f95-0acb6ab55871
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448194380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
448194380
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3315968035
Short name T365
Test name
Test status
Simulation time 68904074 ps
CPU time 0.71 seconds
Started Jun 21 06:24:48 PM PDT 24
Finished Jun 21 06:24:55 PM PDT 24
Peak memory 205224 kb
Host smart-c57c0cc0-798c-4536-9861-2835d397d70a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315968035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3315968035
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2578901257
Short name T308
Test name
Test status
Simulation time 82549100 ps
CPU time 0.77 seconds
Started Jun 21 06:24:46 PM PDT 24
Finished Jun 21 06:24:54 PM PDT 24
Peak memory 205152 kb
Host smart-59453d4f-23a1-468b-a049-2af7afdf2c3e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578901257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2578901257
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3493486103
Short name T113
Test name
Test status
Simulation time 671103402 ps
CPU time 6.61 seconds
Started Jun 21 06:24:47 PM PDT 24
Finished Jun 21 06:25:01 PM PDT 24
Peak memory 205464 kb
Host smart-4ca65d3e-09c7-46e8-a918-f1f16a36db6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493486103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3493486103
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.107819794
Short name T52
Test name
Test status
Simulation time 87747836 ps
CPU time 2.61 seconds
Started Jun 21 06:24:42 PM PDT 24
Finished Jun 21 06:24:53 PM PDT 24
Peak memory 213728 kb
Host smart-67e35191-7b24-445f-b88c-f0108a86260a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107819794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.107819794
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.624615879
Short name T373
Test name
Test status
Simulation time 1967533448 ps
CPU time 10.3 seconds
Started Jun 21 06:24:46 PM PDT 24
Finished Jun 21 06:25:04 PM PDT 24
Peak memory 213688 kb
Host smart-2ebeb5b1-b91e-41a6-a861-9b497d381694
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624615879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.624615879
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.313214241
Short name T55
Test name
Test status
Simulation time 1353329244 ps
CPU time 26.33 seconds
Started Jun 21 06:24:44 PM PDT 24
Finished Jun 21 06:25:17 PM PDT 24
Peak memory 205516 kb
Host smart-5b61d166-9d15-49b7-be31-84bd5037ad45
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313214241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.313214241
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2623647106
Short name T83
Test name
Test status
Simulation time 17588620819 ps
CPU time 56.37 seconds
Started Jun 21 06:24:53 PM PDT 24
Finished Jun 21 06:25:54 PM PDT 24
Peak memory 205576 kb
Host smart-9f27aed7-1473-4d1a-a695-bf01be5928a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623647106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2623647106
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1364765605
Short name T104
Test name
Test status
Simulation time 333535554 ps
CPU time 1.66 seconds
Started Jun 21 06:24:50 PM PDT 24
Finished Jun 21 06:24:58 PM PDT 24
Peak memory 213700 kb
Host smart-6aca5175-e84e-4e22-bba6-bbe278a9c4a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364765605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1364765605
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1176702286
Short name T321
Test name
Test status
Simulation time 461254794 ps
CPU time 2.16 seconds
Started Jun 21 06:24:51 PM PDT 24
Finished Jun 21 06:24:59 PM PDT 24
Peak memory 215608 kb
Host smart-f3405ea2-5030-4227-9343-65d21f577540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176702286 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1176702286
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.936783864
Short name T292
Test name
Test status
Simulation time 184775286 ps
CPU time 1.61 seconds
Started Jun 21 06:24:53 PM PDT 24
Finished Jun 21 06:25:00 PM PDT 24
Peak memory 213688 kb
Host smart-96ce5a3c-a1be-4dcb-8296-53c21dd7b562
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936783864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.936783864
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2935362628
Short name T402
Test name
Test status
Simulation time 60070338284 ps
CPU time 53.85 seconds
Started Jun 21 06:24:50 PM PDT 24
Finished Jun 21 06:25:50 PM PDT 24
Peak memory 205444 kb
Host smart-c14293f5-ddd7-4290-a056-ab4e75edb763
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935362628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2935362628
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3575289474
Short name T369
Test name
Test status
Simulation time 66819850 ps
CPU time 0.68 seconds
Started Jun 21 06:24:53 PM PDT 24
Finished Jun 21 06:24:59 PM PDT 24
Peak memory 205168 kb
Host smart-27f9c7c3-7a46-4593-a63b-391d8d0d88c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575289474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.3575289474
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1003874682
Short name T97
Test name
Test status
Simulation time 25008887727 ps
CPU time 14.55 seconds
Started Jun 21 06:24:46 PM PDT 24
Finished Jun 21 06:25:08 PM PDT 24
Peak memory 205632 kb
Host smart-708dbb52-7156-4e50-8bb1-eb341dfab0ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003874682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1003874682
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1390712704
Short name T309
Test name
Test status
Simulation time 1703208321 ps
CPU time 5.72 seconds
Started Jun 21 06:24:46 PM PDT 24
Finished Jun 21 06:24:59 PM PDT 24
Peak memory 205420 kb
Host smart-67f7a5fc-ce2c-462b-8133-4ad838702e3e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390712704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
390712704
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4257694042
Short name T370
Test name
Test status
Simulation time 360449122 ps
CPU time 0.91 seconds
Started Jun 21 06:24:44 PM PDT 24
Finished Jun 21 06:24:52 PM PDT 24
Peak memory 205152 kb
Host smart-21b8a9bd-a78a-479e-ad10-beedfc944b8f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257694042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.4257694042
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.684984711
Short name T350
Test name
Test status
Simulation time 8063545374 ps
CPU time 19.42 seconds
Started Jun 21 06:24:46 PM PDT 24
Finished Jun 21 06:25:13 PM PDT 24
Peak memory 205456 kb
Host smart-43b27fc2-d503-46a5-9190-a881af3ebe5d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684984711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.684984711
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1268185447
Short name T363
Test name
Test status
Simulation time 243280788 ps
CPU time 1.28 seconds
Started Jun 21 06:24:52 PM PDT 24
Finished Jun 21 06:24:58 PM PDT 24
Peak memory 205148 kb
Host smart-901ef639-b4bc-419f-b247-583603586c16
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268185447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1268185447
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.673835201
Short name T313
Test name
Test status
Simulation time 134979281 ps
CPU time 0.92 seconds
Started Jun 21 06:24:44 PM PDT 24
Finished Jun 21 06:24:52 PM PDT 24
Peak memory 205136 kb
Host smart-adb17dd2-038e-42ca-b3de-6d5212db325f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673835201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.673835201
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2451796629
Short name T384
Test name
Test status
Simulation time 158608519 ps
CPU time 0.74 seconds
Started Jun 21 06:24:52 PM PDT 24
Finished Jun 21 06:24:58 PM PDT 24
Peak memory 205092 kb
Host smart-b40d4913-8f65-4aa7-8502-acc53a230f7a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451796629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2451796629
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1448399627
Short name T260
Test name
Test status
Simulation time 66292346 ps
CPU time 0.73 seconds
Started Jun 21 06:25:00 PM PDT 24
Finished Jun 21 06:25:03 PM PDT 24
Peak memory 205156 kb
Host smart-6c9826f8-45f8-4a2a-b865-c7ca785c2eab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448399627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1448399627
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.17087821
Short name T100
Test name
Test status
Simulation time 10824767248 ps
CPU time 10.7 seconds
Started Jun 21 06:24:54 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 205616 kb
Host smart-ce0b3e13-59b9-4c9d-a478-ac4ca7e47982
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17087821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_cs
r_outstanding.17087821
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.765397850
Short name T411
Test name
Test status
Simulation time 34222445175 ps
CPU time 34.79 seconds
Started Jun 21 06:24:51 PM PDT 24
Finished Jun 21 06:25:32 PM PDT 24
Peak memory 222092 kb
Host smart-0bc06ea1-90df-4ad8-b6be-deed210a0968
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765397850 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.765397850
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1680496170
Short name T406
Test name
Test status
Simulation time 108770564 ps
CPU time 4.96 seconds
Started Jun 21 06:24:50 PM PDT 24
Finished Jun 21 06:25:02 PM PDT 24
Peak memory 213792 kb
Host smart-24becad7-1491-4254-8900-a0390e48f895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680496170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1680496170
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2265751804
Short name T117
Test name
Test status
Simulation time 871009518 ps
CPU time 10.18 seconds
Started Jun 21 06:24:51 PM PDT 24
Finished Jun 21 06:25:07 PM PDT 24
Peak memory 213688 kb
Host smart-d97bf602-0d37-446d-a75e-00f1def6f648
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265751804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2265751804
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2586707160
Short name T382
Test name
Test status
Simulation time 1972138434 ps
CPU time 4.59 seconds
Started Jun 21 06:24:52 PM PDT 24
Finished Jun 21 06:25:02 PM PDT 24
Peak memory 220812 kb
Host smart-32ec0029-c312-4410-90a2-3a9f3e4dd459
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586707160 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2586707160
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.517825093
Short name T108
Test name
Test status
Simulation time 759204019 ps
CPU time 2.49 seconds
Started Jun 21 06:24:53 PM PDT 24
Finished Jun 21 06:25:00 PM PDT 24
Peak memory 213348 kb
Host smart-95e0eda2-c8b2-4bfd-8bb4-23e4d4cec150
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517825093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.517825093
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3538472486
Short name T368
Test name
Test status
Simulation time 113459364575 ps
CPU time 282.81 seconds
Started Jun 21 06:24:59 PM PDT 24
Finished Jun 21 06:29:45 PM PDT 24
Peak memory 205460 kb
Host smart-94f22003-09c1-4fa2-ad82-089ecde4da3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538472486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3538472486
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4200153827
Short name T367
Test name
Test status
Simulation time 4344911881 ps
CPU time 3.62 seconds
Started Jun 21 06:24:50 PM PDT 24
Finished Jun 21 06:25:00 PM PDT 24
Peak memory 205452 kb
Host smart-968276fd-734e-4655-9439-c68d881c6117
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200153827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.4
200153827
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4240848991
Short name T294
Test name
Test status
Simulation time 296393307 ps
CPU time 0.86 seconds
Started Jun 21 06:24:57 PM PDT 24
Finished Jun 21 06:25:01 PM PDT 24
Peak memory 205092 kb
Host smart-1190edb6-9c9a-4384-bf54-91e42c1849f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240848991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.4
240848991
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1966158435
Short name T355
Test name
Test status
Simulation time 895071148 ps
CPU time 6.51 seconds
Started Jun 21 06:24:51 PM PDT 24
Finished Jun 21 06:25:03 PM PDT 24
Peak memory 205380 kb
Host smart-aa928c8f-4da1-4679-9342-54d27deab6ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966158435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1966158435
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.66590218
Short name T274
Test name
Test status
Simulation time 50555156503 ps
CPU time 44.12 seconds
Started Jun 21 06:24:55 PM PDT 24
Finished Jun 21 06:25:43 PM PDT 24
Peak memory 222084 kb
Host smart-5185d0fb-248f-4f96-a48c-4c9fa167548e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66590218 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.66590218
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2108903380
Short name T338
Test name
Test status
Simulation time 422247606 ps
CPU time 2.71 seconds
Started Jun 21 06:24:51 PM PDT 24
Finished Jun 21 06:24:59 PM PDT 24
Peak memory 213764 kb
Host smart-de3c5484-db59-44b7-870d-caaa63915db0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108903380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2108903380
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.361230603
Short name T51
Test name
Test status
Simulation time 1304089797 ps
CPU time 3.15 seconds
Started Jun 21 06:24:54 PM PDT 24
Finished Jun 21 06:25:02 PM PDT 24
Peak memory 213720 kb
Host smart-6a8d4423-c97e-47be-85ce-eb1069daadbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361230603 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.361230603
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.936691358
Short name T99
Test name
Test status
Simulation time 93503152 ps
CPU time 2.31 seconds
Started Jun 21 06:24:54 PM PDT 24
Finished Jun 21 06:25:00 PM PDT 24
Peak memory 213380 kb
Host smart-85f00685-044b-491a-a541-60721fc67cd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936691358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.936691358
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1978812658
Short name T320
Test name
Test status
Simulation time 63907281043 ps
CPU time 84.33 seconds
Started Jun 21 06:24:51 PM PDT 24
Finished Jun 21 06:26:21 PM PDT 24
Peak memory 205460 kb
Host smart-604075de-8f42-4343-ab72-e87056858c56
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978812658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.1978812658
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.406962303
Short name T288
Test name
Test status
Simulation time 2329739844 ps
CPU time 1.68 seconds
Started Jun 21 06:24:51 PM PDT 24
Finished Jun 21 06:24:58 PM PDT 24
Peak memory 205468 kb
Host smart-c6b525cc-f639-40fb-949e-c000d194e5d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406962303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.406962303
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1933558323
Short name T344
Test name
Test status
Simulation time 172659734 ps
CPU time 1.12 seconds
Started Jun 21 06:24:52 PM PDT 24
Finished Jun 21 06:24:59 PM PDT 24
Peak memory 204948 kb
Host smart-8340d64f-f36d-493e-b32c-797e1a0e218a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933558323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
933558323
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1981230333
Short name T86
Test name
Test status
Simulation time 716432460 ps
CPU time 8.62 seconds
Started Jun 21 06:24:53 PM PDT 24
Finished Jun 21 06:25:07 PM PDT 24
Peak memory 205112 kb
Host smart-9d7ee8ee-99c3-48ff-a09d-6505de2f4e46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981230333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1981230333
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2542132860
Short name T67
Test name
Test status
Simulation time 71212109207 ps
CPU time 180.94 seconds
Started Jun 21 06:24:50 PM PDT 24
Finished Jun 21 06:27:57 PM PDT 24
Peak memory 224596 kb
Host smart-aace8ee1-afd1-40c4-b70a-7611ebbf5ed5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542132860 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.2542132860
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.670050725
Short name T342
Test name
Test status
Simulation time 84899374 ps
CPU time 2.52 seconds
Started Jun 21 06:24:52 PM PDT 24
Finished Jun 21 06:25:00 PM PDT 24
Peak memory 221960 kb
Host smart-d6776699-defd-4746-8544-4f6c64e58510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670050725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.670050725
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3277340011
Short name T388
Test name
Test status
Simulation time 2326983467 ps
CPU time 9.16 seconds
Started Jun 21 06:24:54 PM PDT 24
Finished Jun 21 06:25:08 PM PDT 24
Peak memory 213828 kb
Host smart-ed55eba6-04e1-41a5-b3b5-d8eb6f27101f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277340011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3277340011
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1806601015
Short name T78
Test name
Test status
Simulation time 611613663 ps
CPU time 2.09 seconds
Started Jun 21 06:24:53 PM PDT 24
Finished Jun 21 06:25:00 PM PDT 24
Peak memory 213780 kb
Host smart-8dcbb5d2-81ee-4ccd-b400-e0a4d29f0315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806601015 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1806601015
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2891499308
Short name T54
Test name
Test status
Simulation time 205302863 ps
CPU time 1.54 seconds
Started Jun 21 06:24:53 PM PDT 24
Finished Jun 21 06:25:00 PM PDT 24
Peak memory 213680 kb
Host smart-c11a6de2-c34a-4e26-ac05-9054bccec5ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891499308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2891499308
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2036138273
Short name T360
Test name
Test status
Simulation time 11391136353 ps
CPU time 19.02 seconds
Started Jun 21 06:24:50 PM PDT 24
Finished Jun 21 06:25:15 PM PDT 24
Peak memory 205464 kb
Host smart-118ab6c7-023e-4cb4-935e-c56c562db683
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036138273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2036138273
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1133043113
Short name T291
Test name
Test status
Simulation time 15687269334 ps
CPU time 19.8 seconds
Started Jun 21 06:24:52 PM PDT 24
Finished Jun 21 06:25:17 PM PDT 24
Peak memory 205460 kb
Host smart-a44721e0-4282-40f5-bf16-df80f4c991c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133043113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
133043113
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2026957635
Short name T409
Test name
Test status
Simulation time 381911449 ps
CPU time 0.89 seconds
Started Jun 21 06:24:49 PM PDT 24
Finished Jun 21 06:24:56 PM PDT 24
Peak memory 205152 kb
Host smart-2c251dd3-61db-4b55-acb2-fb7647eaedac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026957635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
026957635
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3627945072
Short name T85
Test name
Test status
Simulation time 869462639 ps
CPU time 4.24 seconds
Started Jun 21 06:24:58 PM PDT 24
Finished Jun 21 06:25:05 PM PDT 24
Peak memory 205404 kb
Host smart-d176ca47-859b-48fe-a7fe-cf83e23b342f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627945072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3627945072
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.482354567
Short name T45
Test name
Test status
Simulation time 62523146621 ps
CPU time 94.04 seconds
Started Jun 21 06:24:53 PM PDT 24
Finished Jun 21 06:26:32 PM PDT 24
Peak memory 230192 kb
Host smart-ed3db0c7-94cc-48d8-b8cc-1f92d6f6493c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482354567 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.482354567
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1143604271
Short name T333
Test name
Test status
Simulation time 2262442752 ps
CPU time 7.06 seconds
Started Jun 21 06:24:53 PM PDT 24
Finished Jun 21 06:25:05 PM PDT 24
Peak memory 213812 kb
Host smart-a3655f8a-65fa-4781-bec3-bcd9025093b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143604271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1143604271
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3656131376
Short name T123
Test name
Test status
Simulation time 2821758308 ps
CPU time 11.9 seconds
Started Jun 21 06:24:52 PM PDT 24
Finished Jun 21 06:25:10 PM PDT 24
Peak memory 213660 kb
Host smart-649da36c-d40d-45b1-85b0-51c438011976
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656131376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3656131376
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2811705951
Short name T79
Test name
Test status
Simulation time 3082300793 ps
CPU time 6.23 seconds
Started Jun 21 06:24:57 PM PDT 24
Finished Jun 21 06:25:07 PM PDT 24
Peak memory 213964 kb
Host smart-194f2340-b075-4ea8-90a0-27d50a92b4b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811705951 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2811705951
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3572664290
Short name T299
Test name
Test status
Simulation time 151949871 ps
CPU time 2.45 seconds
Started Jun 21 06:24:52 PM PDT 24
Finished Jun 21 06:25:00 PM PDT 24
Peak memory 213724 kb
Host smart-5feff942-4945-44b8-be00-3c99eb737018
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572664290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3572664290
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1890292066
Short name T280
Test name
Test status
Simulation time 9906756943 ps
CPU time 12.54 seconds
Started Jun 21 06:24:52 PM PDT 24
Finished Jun 21 06:25:10 PM PDT 24
Peak memory 205456 kb
Host smart-4702e6f3-0c56-4e64-8611-b0592eec824b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890292066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.1890292066
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.129334513
Short name T399
Test name
Test status
Simulation time 8489784840 ps
CPU time 11.48 seconds
Started Jun 21 06:24:50 PM PDT 24
Finished Jun 21 06:25:08 PM PDT 24
Peak memory 205396 kb
Host smart-183d82fb-761d-4e0a-9661-b6d705ad4185
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129334513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.129334513
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1357425763
Short name T364
Test name
Test status
Simulation time 1106244419 ps
CPU time 1.39 seconds
Started Jun 21 06:25:00 PM PDT 24
Finished Jun 21 06:25:04 PM PDT 24
Peak memory 205152 kb
Host smart-aba05325-3acb-4a18-8d70-933374f4301e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357425763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1
357425763
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1103438356
Short name T290
Test name
Test status
Simulation time 2006580426 ps
CPU time 8.51 seconds
Started Jun 21 06:24:58 PM PDT 24
Finished Jun 21 06:25:10 PM PDT 24
Peak memory 205500 kb
Host smart-c16c7678-eef2-4397-b95d-6a4863a02fb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103438356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1103438356
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.913734261
Short name T118
Test name
Test status
Simulation time 1017408667 ps
CPU time 5.29 seconds
Started Jun 21 06:24:51 PM PDT 24
Finished Jun 21 06:25:02 PM PDT 24
Peak memory 213724 kb
Host smart-a55639f4-7ab8-40ad-8d7f-72d94d644661
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913734261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.913734261
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4084066993
Short name T129
Test name
Test status
Simulation time 1510047303 ps
CPU time 11.84 seconds
Started Jun 21 06:24:55 PM PDT 24
Finished Jun 21 06:25:11 PM PDT 24
Peak memory 213676 kb
Host smart-0f259d40-d217-4036-b1f9-01eef8ae7d74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084066993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.4084066993
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1154370969
Short name T293
Test name
Test status
Simulation time 3635597765 ps
CPU time 7.67 seconds
Started Jun 21 06:24:57 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 221956 kb
Host smart-6e1f1e18-d128-4ab0-b834-fec5431d793d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154370969 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1154370969
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1876555045
Short name T372
Test name
Test status
Simulation time 109307701 ps
CPU time 2.23 seconds
Started Jun 21 06:24:58 PM PDT 24
Finished Jun 21 06:25:04 PM PDT 24
Peak memory 213620 kb
Host smart-7f702c6f-d0ad-420a-9492-6af952a9e9ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876555045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1876555045
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3997717311
Short name T287
Test name
Test status
Simulation time 41764273358 ps
CPU time 13.65 seconds
Started Jun 21 06:24:56 PM PDT 24
Finished Jun 21 06:25:13 PM PDT 24
Peak memory 205452 kb
Host smart-af0aac3d-d930-4ffa-9716-eee92009002c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997717311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3997717311
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1301807657
Short name T340
Test name
Test status
Simulation time 7083002365 ps
CPU time 19.07 seconds
Started Jun 21 06:25:01 PM PDT 24
Finished Jun 21 06:25:22 PM PDT 24
Peak memory 205392 kb
Host smart-bba41787-53e9-4ad4-b262-58494e6eae76
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301807657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
301807657
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1272530
Short name T317
Test name
Test status
Simulation time 615000326 ps
CPU time 1.45 seconds
Started Jun 21 06:24:58 PM PDT 24
Finished Jun 21 06:25:02 PM PDT 24
Peak memory 205084 kb
Host smart-3a8d6550-28e4-419f-88ba-008de1487df5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1272530
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2855495465
Short name T326
Test name
Test status
Simulation time 817316673 ps
CPU time 6.76 seconds
Started Jun 21 06:24:56 PM PDT 24
Finished Jun 21 06:25:07 PM PDT 24
Peak memory 205456 kb
Host smart-64ce0381-f873-4d99-a742-8dae0c0b266d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855495465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2855495465
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.4230297501
Short name T122
Test name
Test status
Simulation time 921688944 ps
CPU time 5.24 seconds
Started Jun 21 06:25:03 PM PDT 24
Finished Jun 21 06:25:09 PM PDT 24
Peak memory 216240 kb
Host smart-9ea0db54-23dd-47ee-8ffe-382b51493fe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230297501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.4230297501
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1685393399
Short name T80
Test name
Test status
Simulation time 4138854700 ps
CPU time 10.06 seconds
Started Jun 21 06:25:02 PM PDT 24
Finished Jun 21 06:25:14 PM PDT 24
Peak memory 213804 kb
Host smart-8073d718-a1a0-4270-9375-077c52754b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685393399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1685393399
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3988369369
Short name T153
Test name
Test status
Simulation time 220567575 ps
CPU time 0.83 seconds
Started Jun 21 05:59:41 PM PDT 24
Finished Jun 21 05:59:43 PM PDT 24
Peak memory 204780 kb
Host smart-6e75328f-4fa6-4045-9da3-75b488a0457c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988369369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3988369369
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.296224620
Short name T191
Test name
Test status
Simulation time 4105007831 ps
CPU time 4.27 seconds
Started Jun 21 05:59:32 PM PDT 24
Finished Jun 21 05:59:36 PM PDT 24
Peak memory 205120 kb
Host smart-84a944dc-d6a7-42bc-ab8e-ad9c39feb9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296224620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.296224620
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1857379659
Short name T218
Test name
Test status
Simulation time 3045744874 ps
CPU time 5.49 seconds
Started Jun 21 05:59:35 PM PDT 24
Finished Jun 21 05:59:41 PM PDT 24
Peak memory 205112 kb
Host smart-f666278b-b79d-489c-8136-da683429a5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857379659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1857379659
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.2650064121
Short name T137
Test name
Test status
Simulation time 4788333506 ps
CPU time 12.79 seconds
Started Jun 21 05:59:37 PM PDT 24
Finished Jun 21 05:59:50 PM PDT 24
Peak memory 205000 kb
Host smart-797d1168-4aa0-43e8-9714-6e51f59d74be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650064121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.2650064121
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1635256237
Short name T143
Test name
Test status
Simulation time 4196651979 ps
CPU time 6.8 seconds
Started Jun 21 05:59:30 PM PDT 24
Finished Jun 21 05:59:38 PM PDT 24
Peak memory 205004 kb
Host smart-f7326d48-1758-4f25-903e-b714d927b6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635256237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1635256237
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1102067198
Short name T145
Test name
Test status
Simulation time 114340784 ps
CPU time 0.98 seconds
Started Jun 21 05:59:33 PM PDT 24
Finished Jun 21 05:59:35 PM PDT 24
Peak memory 204712 kb
Host smart-8dbf8ebc-db1e-4910-a6c1-197ae4a4a7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102067198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1102067198
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1796149597
Short name T62
Test name
Test status
Simulation time 2745415981 ps
CPU time 3.61 seconds
Started Jun 21 05:59:42 PM PDT 24
Finished Jun 21 05:59:47 PM PDT 24
Peak memory 204792 kb
Host smart-47c1da30-15c1-46e4-bd6f-33c2ca9b10b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796149597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1796149597
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2263136508
Short name T222
Test name
Test status
Simulation time 379678156 ps
CPU time 1.33 seconds
Started Jun 21 05:59:32 PM PDT 24
Finished Jun 21 05:59:33 PM PDT 24
Peak memory 204584 kb
Host smart-59d60f1d-9728-44b2-a7d2-1d6df460f9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263136508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2263136508
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3936794687
Short name T198
Test name
Test status
Simulation time 687802801 ps
CPU time 1.83 seconds
Started Jun 21 05:59:38 PM PDT 24
Finished Jun 21 05:59:41 PM PDT 24
Peak memory 204588 kb
Host smart-49434690-942d-4fd6-a515-df4decfe6330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936794687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3936794687
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3090335584
Short name T211
Test name
Test status
Simulation time 1360096925 ps
CPU time 1.84 seconds
Started Jun 21 05:59:37 PM PDT 24
Finished Jun 21 05:59:40 PM PDT 24
Peak memory 204592 kb
Host smart-9e18af16-a91b-4f99-864f-50d7870a843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090335584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3090335584
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3309712941
Short name T188
Test name
Test status
Simulation time 5039629800 ps
CPU time 4.15 seconds
Started Jun 21 05:59:38 PM PDT 24
Finished Jun 21 05:59:43 PM PDT 24
Peak memory 204844 kb
Host smart-f536fc9c-6523-424b-b090-ddd7eee16c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309712941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3309712941
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1245675361
Short name T180
Test name
Test status
Simulation time 151370014 ps
CPU time 0.81 seconds
Started Jun 21 05:59:40 PM PDT 24
Finished Jun 21 05:59:42 PM PDT 24
Peak memory 204548 kb
Host smart-47b568ce-fcbd-4339-a514-4e076702e397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245675361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1245675361
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.86727661
Short name T144
Test name
Test status
Simulation time 104044523 ps
CPU time 0.73 seconds
Started Jun 21 05:59:37 PM PDT 24
Finished Jun 21 05:59:38 PM PDT 24
Peak memory 204720 kb
Host smart-352611bb-8473-41f0-acae-db44aab47893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86727661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.86727661
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2783550771
Short name T259
Test name
Test status
Simulation time 425938837 ps
CPU time 1.19 seconds
Started Jun 21 05:59:37 PM PDT 24
Finished Jun 21 05:59:39 PM PDT 24
Peak memory 204740 kb
Host smart-6ad3e575-006c-4e06-98b9-61d0555d9b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783550771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2783550771
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.436751717
Short name T56
Test name
Test status
Simulation time 1437688988 ps
CPU time 1.73 seconds
Started Jun 21 05:59:37 PM PDT 24
Finished Jun 21 05:59:40 PM PDT 24
Peak memory 204712 kb
Host smart-6f6ccc0d-8006-47ef-be27-49a94a312ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436751717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.436751717
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.849538911
Short name T27
Test name
Test status
Simulation time 67072714 ps
CPU time 0.95 seconds
Started Jun 21 05:59:39 PM PDT 24
Finished Jun 21 05:59:41 PM PDT 24
Peak memory 213008 kb
Host smart-daeb4795-e501-493b-a99b-3fdd053b553f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849538911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.849538911
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1705003450
Short name T181
Test name
Test status
Simulation time 1049977321 ps
CPU time 3.19 seconds
Started Jun 21 05:59:32 PM PDT 24
Finished Jun 21 05:59:36 PM PDT 24
Peak memory 205044 kb
Host smart-ba1bdc59-c872-484e-8799-ee9ae6e705c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705003450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1705003450
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1912435778
Short name T173
Test name
Test status
Simulation time 2302545000 ps
CPU time 6.42 seconds
Started Jun 21 05:59:32 PM PDT 24
Finished Jun 21 05:59:39 PM PDT 24
Peak memory 204676 kb
Host smart-9733c48e-887c-4e38-ad33-00dbb1bd4ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912435778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1912435778
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2703360914
Short name T46
Test name
Test status
Simulation time 18411879858 ps
CPU time 51.03 seconds
Started Jun 21 05:59:38 PM PDT 24
Finished Jun 21 06:00:30 PM PDT 24
Peak memory 213204 kb
Host smart-65cad258-f44b-40f0-a0f1-075f403b00be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703360914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2703360914
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.144222756
Short name T43
Test name
Test status
Simulation time 6861369916 ps
CPU time 19.36 seconds
Started Jun 21 05:59:32 PM PDT 24
Finished Jun 21 05:59:52 PM PDT 24
Peak memory 205004 kb
Host smart-96fb22ee-e9b7-451b-af3a-8d5bf75aaa24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144222756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.144222756
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3630935838
Short name T39
Test name
Test status
Simulation time 706301608 ps
CPU time 0.86 seconds
Started Jun 21 05:59:47 PM PDT 24
Finished Jun 21 05:59:49 PM PDT 24
Peak memory 204836 kb
Host smart-1f67497e-1ba7-4b7a-9a6c-a0b48f75ecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630935838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3630935838
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2260515572
Short name T194
Test name
Test status
Simulation time 30408366 ps
CPU time 0.76 seconds
Started Jun 21 05:59:46 PM PDT 24
Finished Jun 21 05:59:47 PM PDT 24
Peak memory 204736 kb
Host smart-08d09e52-f3d4-44b6-9f9b-10481c1e75f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260515572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2260515572
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1722449282
Short name T239
Test name
Test status
Simulation time 18676911938 ps
CPU time 44.23 seconds
Started Jun 21 05:59:41 PM PDT 24
Finished Jun 21 06:00:26 PM PDT 24
Peak memory 213364 kb
Host smart-75863519-d81f-460e-9184-e0582eb1b821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722449282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1722449282
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.419027712
Short name T48
Test name
Test status
Simulation time 7447012720 ps
CPU time 20 seconds
Started Jun 21 05:59:40 PM PDT 24
Finished Jun 21 06:00:01 PM PDT 24
Peak memory 213360 kb
Host smart-23ed677a-6544-4b69-baf6-bbdabaf238fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419027712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.419027712
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.394273183
Short name T4
Test name
Test status
Simulation time 16243083190 ps
CPU time 23.26 seconds
Started Jun 21 05:59:39 PM PDT 24
Finished Jun 21 06:00:03 PM PDT 24
Peak memory 204996 kb
Host smart-652a805e-4eb5-41fd-aba6-1944d5b9c959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394273183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.394273183
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1151660740
Short name T34
Test name
Test status
Simulation time 149412417 ps
CPU time 0.77 seconds
Started Jun 21 05:59:39 PM PDT 24
Finished Jun 21 05:59:41 PM PDT 24
Peak memory 204728 kb
Host smart-5c90523c-8ae0-4af4-a34f-d91e43594d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151660740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1151660740
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.4052287044
Short name T24
Test name
Test status
Simulation time 486112842 ps
CPU time 2.05 seconds
Started Jun 21 05:59:38 PM PDT 24
Finished Jun 21 05:59:41 PM PDT 24
Peak memory 204560 kb
Host smart-24644626-f4bf-4d03-b2ad-c20b8d894d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052287044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.4052287044
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1311290808
Short name T136
Test name
Test status
Simulation time 8697475552 ps
CPU time 3.23 seconds
Started Jun 21 05:59:39 PM PDT 24
Finished Jun 21 05:59:44 PM PDT 24
Peak memory 204948 kb
Host smart-515bd8e4-411e-455f-a936-7df150a6d7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311290808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1311290808
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1182597238
Short name T202
Test name
Test status
Simulation time 239518303 ps
CPU time 1.06 seconds
Started Jun 21 05:59:40 PM PDT 24
Finished Jun 21 05:59:42 PM PDT 24
Peak memory 204836 kb
Host smart-781811ac-e1be-4c71-b289-a979b7a07310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182597238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1182597238
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.4121570319
Short name T179
Test name
Test status
Simulation time 2251815722 ps
CPU time 6.9 seconds
Started Jun 21 05:59:39 PM PDT 24
Finished Jun 21 05:59:47 PM PDT 24
Peak memory 205108 kb
Host smart-3ec67da6-395e-400b-852a-37031c73adf4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121570319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.4121570319
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.4015253043
Short name T30
Test name
Test status
Simulation time 909961914 ps
CPU time 1.28 seconds
Started Jun 21 05:59:42 PM PDT 24
Finished Jun 21 05:59:44 PM PDT 24
Peak memory 204736 kb
Host smart-2b963b01-3049-42ee-9b3f-73ad9eda1706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015253043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.4015253043
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.123510469
Short name T206
Test name
Test status
Simulation time 220558843 ps
CPU time 0.95 seconds
Started Jun 21 05:59:38 PM PDT 24
Finished Jun 21 05:59:40 PM PDT 24
Peak memory 204580 kb
Host smart-aee42cdb-d8ca-4442-b7b5-f4629d449939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123510469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.123510469
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.887735866
Short name T59
Test name
Test status
Simulation time 842132961 ps
CPU time 2.04 seconds
Started Jun 21 05:59:48 PM PDT 24
Finished Jun 21 05:59:51 PM PDT 24
Peak memory 204580 kb
Host smart-fb385860-5d12-45d1-9be3-d1bc104d34ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887735866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.887735866
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3969521534
Short name T251
Test name
Test status
Simulation time 1988717963 ps
CPU time 3.53 seconds
Started Jun 21 05:59:47 PM PDT 24
Finished Jun 21 05:59:52 PM PDT 24
Peak memory 204588 kb
Host smart-6a38cdf9-d031-4acc-86c1-1f8ad2331f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969521534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3969521534
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1048319750
Short name T47
Test name
Test status
Simulation time 993804349 ps
CPU time 1.09 seconds
Started Jun 21 05:59:47 PM PDT 24
Finished Jun 21 05:59:49 PM PDT 24
Peak memory 204608 kb
Host smart-ead16f5e-9173-4d17-9244-720c3669cd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048319750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1048319750
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.241955788
Short name T184
Test name
Test status
Simulation time 304513773 ps
CPU time 1.41 seconds
Started Jun 21 05:59:45 PM PDT 24
Finished Jun 21 05:59:47 PM PDT 24
Peak memory 204560 kb
Host smart-01c93da7-642d-41b6-b93d-4376019807b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241955788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.241955788
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3030255304
Short name T135
Test name
Test status
Simulation time 1776733795 ps
CPU time 5.55 seconds
Started Jun 21 05:59:38 PM PDT 24
Finished Jun 21 05:59:44 PM PDT 24
Peak memory 204708 kb
Host smart-2ee7660a-17b1-4ba6-9aa8-d173bccebf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030255304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3030255304
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1132178619
Short name T142
Test name
Test status
Simulation time 212102435 ps
CPU time 0.82 seconds
Started Jun 21 05:59:42 PM PDT 24
Finished Jun 21 05:59:43 PM PDT 24
Peak memory 204756 kb
Host smart-fba2f1da-ddf6-4bfb-9e3b-0afb8810f3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132178619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1132178619
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2920950853
Short name T139
Test name
Test status
Simulation time 2977343319 ps
CPU time 9.07 seconds
Started Jun 21 05:59:48 PM PDT 24
Finished Jun 21 05:59:58 PM PDT 24
Peak memory 205028 kb
Host smart-e6d56e57-39f8-4a9e-84a9-8cb73ce4b2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920950853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2920950853
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3940519172
Short name T32
Test name
Test status
Simulation time 420830271 ps
CPU time 1.19 seconds
Started Jun 21 05:59:48 PM PDT 24
Finished Jun 21 05:59:50 PM PDT 24
Peak memory 204708 kb
Host smart-9803d0e1-79eb-48bc-b1a8-ff0ae866b530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940519172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3940519172
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1260586506
Short name T37
Test name
Test status
Simulation time 1166449947 ps
CPU time 3.72 seconds
Started Jun 21 05:59:46 PM PDT 24
Finished Jun 21 05:59:50 PM PDT 24
Peak memory 204736 kb
Host smart-e4b31960-e4a5-4026-8352-a43de40715df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260586506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1260586506
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1806224828
Short name T235
Test name
Test status
Simulation time 1093274742 ps
CPU time 2.33 seconds
Started Jun 21 05:59:37 PM PDT 24
Finished Jun 21 05:59:40 PM PDT 24
Peak memory 205124 kb
Host smart-1415dc4a-f32f-4ce6-a843-f581acf7bdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806224828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1806224828
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.183784155
Short name T40
Test name
Test status
Simulation time 811815504 ps
CPU time 3.29 seconds
Started Jun 21 05:59:46 PM PDT 24
Finished Jun 21 05:59:51 PM PDT 24
Peak memory 229220 kb
Host smart-1e87b2d7-b604-4130-8517-87bda5362737
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183784155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.183784155
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2802719606
Short name T233
Test name
Test status
Simulation time 1001615225 ps
CPU time 3.38 seconds
Started Jun 21 05:59:41 PM PDT 24
Finished Jun 21 05:59:45 PM PDT 24
Peak memory 204616 kb
Host smart-9b054690-6e68-453e-a218-ee3c202aee19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802719606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2802719606
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.3367888179
Short name T14
Test name
Test status
Simulation time 27218008198 ps
CPU time 73.17 seconds
Started Jun 21 05:59:48 PM PDT 24
Finished Jun 21 06:01:02 PM PDT 24
Peak memory 213168 kb
Host smart-ff62f761-1a2e-4cc4-824f-1fe91b106153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367888179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3367888179
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2131511917
Short name T169
Test name
Test status
Simulation time 37409596 ps
CPU time 0.77 seconds
Started Jun 21 06:00:04 PM PDT 24
Finished Jun 21 06:00:06 PM PDT 24
Peak memory 204820 kb
Host smart-6de3e231-fb0e-4d5c-8bfc-3f8ca4cbaef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131511917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2131511917
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3225945052
Short name T200
Test name
Test status
Simulation time 5202871704 ps
CPU time 9.36 seconds
Started Jun 21 06:00:03 PM PDT 24
Finished Jun 21 06:00:14 PM PDT 24
Peak memory 214912 kb
Host smart-9cbb065e-c616-403a-bcd4-d09e7b4cd9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225945052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3225945052
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.963364406
Short name T189
Test name
Test status
Simulation time 11073156963 ps
CPU time 8.09 seconds
Started Jun 21 06:00:02 PM PDT 24
Finished Jun 21 06:00:12 PM PDT 24
Peak memory 213276 kb
Host smart-31bc1780-74e2-4498-89b7-7ec913338330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963364406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.963364406
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2979589440
Short name T208
Test name
Test status
Simulation time 3514171915 ps
CPU time 11.69 seconds
Started Jun 21 06:00:05 PM PDT 24
Finished Jun 21 06:00:18 PM PDT 24
Peak memory 205076 kb
Host smart-c874c60d-2d0f-49fe-b126-afbc605d7c37
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979589440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2979589440
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.716911053
Short name T246
Test name
Test status
Simulation time 6720052915 ps
CPU time 5.29 seconds
Started Jun 21 06:00:03 PM PDT 24
Finished Jun 21 06:00:10 PM PDT 24
Peak memory 205156 kb
Host smart-2412297d-d024-427c-9dac-5fa804f0cf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716911053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.716911053
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.237487976
Short name T26
Test name
Test status
Simulation time 20173022154 ps
CPU time 15.12 seconds
Started Jun 21 06:00:04 PM PDT 24
Finished Jun 21 06:00:21 PM PDT 24
Peak memory 204956 kb
Host smart-afae3c27-b93c-4569-bd0a-8a05ef417624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237487976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.237487976
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1847501121
Short name T158
Test name
Test status
Simulation time 62862448 ps
CPU time 0.79 seconds
Started Jun 21 06:00:06 PM PDT 24
Finished Jun 21 06:00:08 PM PDT 24
Peak memory 204768 kb
Host smart-09f27d79-3d3f-4dea-8073-e977534027ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847501121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1847501121
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2864526310
Short name T16
Test name
Test status
Simulation time 8057840096 ps
CPU time 11.49 seconds
Started Jun 21 06:00:06 PM PDT 24
Finished Jun 21 06:00:19 PM PDT 24
Peak memory 205160 kb
Host smart-896fc52a-cb27-48d9-af54-5809508a25d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864526310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2864526310
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2170084760
Short name T72
Test name
Test status
Simulation time 2211305403 ps
CPU time 6.95 seconds
Started Jun 21 06:00:03 PM PDT 24
Finished Jun 21 06:00:11 PM PDT 24
Peak memory 205136 kb
Host smart-575ff209-90a0-4b36-98e3-309fb7e70e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170084760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2170084760
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2138799733
Short name T175
Test name
Test status
Simulation time 16824593507 ps
CPU time 23.95 seconds
Started Jun 21 06:00:03 PM PDT 24
Finished Jun 21 06:00:29 PM PDT 24
Peak memory 213324 kb
Host smart-7d988115-8e5a-4bbe-a290-8b9ee32f88a9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138799733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2138799733
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1623887891
Short name T217
Test name
Test status
Simulation time 4104553107 ps
CPU time 10.76 seconds
Started Jun 21 06:00:02 PM PDT 24
Finished Jun 21 06:00:14 PM PDT 24
Peak memory 205112 kb
Host smart-2a7e1804-d82a-416c-bb84-bf3d608ba8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623887891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1623887891
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3796439376
Short name T160
Test name
Test status
Simulation time 46332121 ps
CPU time 0.73 seconds
Started Jun 21 06:00:04 PM PDT 24
Finished Jun 21 06:00:06 PM PDT 24
Peak memory 204788 kb
Host smart-41b99979-47d6-45a3-ac32-675a9b1b8536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796439376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3796439376
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2147109857
Short name T220
Test name
Test status
Simulation time 5816428550 ps
CPU time 9.81 seconds
Started Jun 21 06:00:05 PM PDT 24
Finished Jun 21 06:00:17 PM PDT 24
Peak memory 214684 kb
Host smart-77b742ed-9a89-4ff9-bc9c-363fd67a8dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147109857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2147109857
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2417404754
Short name T12
Test name
Test status
Simulation time 7915548852 ps
CPU time 20.51 seconds
Started Jun 21 06:00:03 PM PDT 24
Finished Jun 21 06:00:25 PM PDT 24
Peak memory 205128 kb
Host smart-de538881-eedf-4698-a053-8eeac5b91941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417404754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2417404754
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2489551843
Short name T254
Test name
Test status
Simulation time 2130352013 ps
CPU time 7.06 seconds
Started Jun 21 06:00:03 PM PDT 24
Finished Jun 21 06:00:11 PM PDT 24
Peak memory 205100 kb
Host smart-c2bd8046-ed0b-417f-92d1-a269e26df86e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489551843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2489551843
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.694493172
Short name T203
Test name
Test status
Simulation time 14371957164 ps
CPU time 29.42 seconds
Started Jun 21 06:00:04 PM PDT 24
Finished Jun 21 06:00:35 PM PDT 24
Peak memory 205264 kb
Host smart-ba780904-8c69-45a5-be07-f75e7864fa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694493172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.694493172
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3921106562
Short name T150
Test name
Test status
Simulation time 35793218 ps
CPU time 0.78 seconds
Started Jun 21 06:00:07 PM PDT 24
Finished Jun 21 06:00:09 PM PDT 24
Peak memory 204788 kb
Host smart-810f4ae9-7ec6-4c60-a295-6712f2755284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921106562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3921106562
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1513516304
Short name T227
Test name
Test status
Simulation time 36649690049 ps
CPU time 91.05 seconds
Started Jun 21 06:00:09 PM PDT 24
Finished Jun 21 06:01:41 PM PDT 24
Peak memory 213292 kb
Host smart-d3fdde20-7059-45b9-9934-00a73e9ec2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513516304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1513516304
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3474804073
Short name T247
Test name
Test status
Simulation time 5462277411 ps
CPU time 9.23 seconds
Started Jun 21 06:00:18 PM PDT 24
Finished Jun 21 06:00:29 PM PDT 24
Peak memory 205156 kb
Host smart-cf0e91a0-fa8e-41ee-ad7c-63747dce1c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474804073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3474804073
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3750158424
Short name T204
Test name
Test status
Simulation time 6044698253 ps
CPU time 9.51 seconds
Started Jun 21 06:00:08 PM PDT 24
Finished Jun 21 06:00:18 PM PDT 24
Peak memory 205092 kb
Host smart-7670d61e-b6d4-4ac1-98fa-28fedd951f75
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750158424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3750158424
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.768432878
Short name T258
Test name
Test status
Simulation time 12516798510 ps
CPU time 15.12 seconds
Started Jun 21 06:00:07 PM PDT 24
Finished Jun 21 06:00:23 PM PDT 24
Peak memory 205116 kb
Host smart-3ee5ead2-0bf4-4858-b2df-32e80d70b7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768432878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.768432878
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.4084397276
Short name T163
Test name
Test status
Simulation time 52710219 ps
CPU time 0.7 seconds
Started Jun 21 06:00:19 PM PDT 24
Finished Jun 21 06:00:21 PM PDT 24
Peak memory 204784 kb
Host smart-bc36f684-906b-4b62-803d-d7433e3678bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084397276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.4084397276
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.264221882
Short name T223
Test name
Test status
Simulation time 24804779340 ps
CPU time 75.16 seconds
Started Jun 21 06:00:18 PM PDT 24
Finished Jun 21 06:01:35 PM PDT 24
Peak memory 213376 kb
Host smart-2299f2fb-1697-4c3c-a3ed-86fdf62924c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264221882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.264221882
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3792368980
Short name T248
Test name
Test status
Simulation time 7121968585 ps
CPU time 6.85 seconds
Started Jun 21 06:00:07 PM PDT 24
Finished Jun 21 06:00:15 PM PDT 24
Peak memory 205164 kb
Host smart-1d6bf97d-194f-46a9-8c08-3311fa6d9b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792368980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3792368980
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2489355293
Short name T92
Test name
Test status
Simulation time 2885390922 ps
CPU time 8.6 seconds
Started Jun 21 06:00:07 PM PDT 24
Finished Jun 21 06:00:17 PM PDT 24
Peak memory 205020 kb
Host smart-215e21d2-0fc9-4d1a-a3eb-d0514d8f12d0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489355293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.2489355293
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.4071035777
Short name T230
Test name
Test status
Simulation time 7474019102 ps
CPU time 18.4 seconds
Started Jun 21 06:00:06 PM PDT 24
Finished Jun 21 06:00:26 PM PDT 24
Peak memory 205100 kb
Host smart-070f7d9b-dc8c-437a-bd5e-3fb958b021a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071035777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.4071035777
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.1327820321
Short name T138
Test name
Test status
Simulation time 10425345940 ps
CPU time 15.91 seconds
Started Jun 21 06:00:07 PM PDT 24
Finished Jun 21 06:00:24 PM PDT 24
Peak memory 204996 kb
Host smart-275f86e5-3738-4e07-ad2d-80590540d310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327820321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1327820321
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3247100926
Short name T115
Test name
Test status
Simulation time 153113807 ps
CPU time 0.85 seconds
Started Jun 21 06:00:07 PM PDT 24
Finished Jun 21 06:00:09 PM PDT 24
Peak memory 204788 kb
Host smart-2099dab8-b0a1-4134-8c7c-bebd7f3af633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247100926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3247100926
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3247224193
Short name T212
Test name
Test status
Simulation time 3570332098 ps
CPU time 11.22 seconds
Started Jun 21 06:00:11 PM PDT 24
Finished Jun 21 06:00:22 PM PDT 24
Peak memory 205184 kb
Host smart-a95b1821-5fb7-402d-8a93-bf22f0c335c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247224193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3247224193
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2610822884
Short name T229
Test name
Test status
Simulation time 2571134217 ps
CPU time 4.81 seconds
Started Jun 21 06:00:05 PM PDT 24
Finished Jun 21 06:00:12 PM PDT 24
Peak memory 205108 kb
Host smart-7a31781f-d1d5-43fd-808e-542def4483cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610822884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2610822884
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.4180081504
Short name T253
Test name
Test status
Simulation time 2909977713 ps
CPU time 2.67 seconds
Started Jun 21 06:00:19 PM PDT 24
Finished Jun 21 06:00:23 PM PDT 24
Peak memory 205160 kb
Host smart-d76ccf44-b9de-4b25-b341-07483f9992aa
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4180081504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.4180081504
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.204146398
Short name T64
Test name
Test status
Simulation time 2367036147 ps
CPU time 2.55 seconds
Started Jun 21 06:00:11 PM PDT 24
Finished Jun 21 06:00:15 PM PDT 24
Peak memory 205248 kb
Host smart-b8b9ef35-92d7-4ef7-9a7a-0cff12b09b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204146398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.204146398
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2741130383
Short name T171
Test name
Test status
Simulation time 105867277 ps
CPU time 0.86 seconds
Started Jun 21 06:00:10 PM PDT 24
Finished Jun 21 06:00:11 PM PDT 24
Peak memory 204652 kb
Host smart-1ae4a999-88f5-4dac-aea2-1d16338770ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741130383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2741130383
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.7482376
Short name T120
Test name
Test status
Simulation time 5293919030 ps
CPU time 2.8 seconds
Started Jun 21 06:00:18 PM PDT 24
Finished Jun 21 06:00:22 PM PDT 24
Peak memory 205120 kb
Host smart-368585da-21ab-44f9-8e21-4bd655366299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7482376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.7482376
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1542410487
Short name T193
Test name
Test status
Simulation time 5000912586 ps
CPU time 15.23 seconds
Started Jun 21 06:00:09 PM PDT 24
Finished Jun 21 06:00:25 PM PDT 24
Peak memory 205136 kb
Host smart-1cc926c8-cd41-4105-9913-9f1aef8c51f3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1542410487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1542410487
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.184212602
Short name T8
Test name
Test status
Simulation time 4225247803 ps
CPU time 11.73 seconds
Started Jun 21 06:00:10 PM PDT 24
Finished Jun 21 06:00:22 PM PDT 24
Peak memory 205048 kb
Host smart-6d9d5ede-1b30-4537-b40e-7f1bdd15af21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184212602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.184212602
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2720958614
Short name T61
Test name
Test status
Simulation time 10533242736 ps
CPU time 14.69 seconds
Started Jun 21 06:00:07 PM PDT 24
Finished Jun 21 06:00:23 PM PDT 24
Peak memory 204912 kb
Host smart-1fed61ef-e9db-4969-af92-083be4b6e44a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720958614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2720958614
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.843568765
Short name T166
Test name
Test status
Simulation time 66465920 ps
CPU time 0.71 seconds
Started Jun 21 06:00:18 PM PDT 24
Finished Jun 21 06:00:20 PM PDT 24
Peak memory 204780 kb
Host smart-bb7239e2-bba4-4687-9773-789d93565473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843568765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.843568765
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3171275292
Short name T214
Test name
Test status
Simulation time 11246571585 ps
CPU time 10.27 seconds
Started Jun 21 06:00:06 PM PDT 24
Finished Jun 21 06:00:18 PM PDT 24
Peak memory 216032 kb
Host smart-fb647422-9383-499c-9151-a893dcd24f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171275292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3171275292
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3853899928
Short name T252
Test name
Test status
Simulation time 1744853967 ps
CPU time 2.43 seconds
Started Jun 21 06:00:19 PM PDT 24
Finished Jun 21 06:00:23 PM PDT 24
Peak memory 205040 kb
Host smart-97b1b47d-3590-479f-92ee-fa06686cc61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853899928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3853899928
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3886390076
Short name T93
Test name
Test status
Simulation time 1680900800 ps
CPU time 5.41 seconds
Started Jun 21 06:00:10 PM PDT 24
Finished Jun 21 06:00:16 PM PDT 24
Peak memory 204980 kb
Host smart-52d89387-c03b-46d4-8861-c8969422dbb0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886390076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3886390076
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3624897306
Short name T236
Test name
Test status
Simulation time 1681022823 ps
CPU time 2.27 seconds
Started Jun 21 06:00:08 PM PDT 24
Finished Jun 21 06:00:12 PM PDT 24
Peak memory 204712 kb
Host smart-6db34bf9-def3-41da-9725-e746c9866334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624897306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3624897306
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.2654598869
Short name T238
Test name
Test status
Simulation time 11094803417 ps
CPU time 6.24 seconds
Started Jun 21 06:00:09 PM PDT 24
Finished Jun 21 06:00:16 PM PDT 24
Peak memory 205028 kb
Host smart-e8cee19a-4994-4ecf-a3b8-e6237a2589dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654598869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2654598869
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.179668671
Short name T154
Test name
Test status
Simulation time 117941157 ps
CPU time 0.95 seconds
Started Jun 21 06:00:08 PM PDT 24
Finished Jun 21 06:00:10 PM PDT 24
Peak memory 204460 kb
Host smart-6a8be868-6b05-4bfe-8e38-567e54c66f41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179668671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.179668671
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.868519333
Short name T185
Test name
Test status
Simulation time 15437870752 ps
CPU time 18.86 seconds
Started Jun 21 06:00:19 PM PDT 24
Finished Jun 21 06:00:39 PM PDT 24
Peak memory 216268 kb
Host smart-879e7010-8431-42ce-899f-dd7b60a10de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868519333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.868519333
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2934384379
Short name T205
Test name
Test status
Simulation time 6106990046 ps
CPU time 3.67 seconds
Started Jun 21 06:00:07 PM PDT 24
Finished Jun 21 06:00:12 PM PDT 24
Peak memory 213492 kb
Host smart-a34d9c89-7c0b-4c42-8210-28dd0d0644e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934384379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2934384379
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3135775030
Short name T178
Test name
Test status
Simulation time 2993841637 ps
CPU time 7.73 seconds
Started Jun 21 06:00:09 PM PDT 24
Finished Jun 21 06:00:18 PM PDT 24
Peak memory 205156 kb
Host smart-b9ae81df-affe-4f77-b4e8-280d356ce568
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135775030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.3135775030
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.783209286
Short name T174
Test name
Test status
Simulation time 8243135765 ps
CPU time 6.75 seconds
Started Jun 21 06:00:07 PM PDT 24
Finished Jun 21 06:00:15 PM PDT 24
Peak memory 205064 kb
Host smart-abcbc647-a7bf-4cb8-ac54-df52d6902a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783209286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.783209286
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.721562414
Short name T159
Test name
Test status
Simulation time 154113088 ps
CPU time 0.8 seconds
Started Jun 21 06:00:18 PM PDT 24
Finished Jun 21 06:00:20 PM PDT 24
Peak memory 204784 kb
Host smart-2003bb4d-fddd-4a5b-9476-76b87aefee9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721562414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.721562414
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.491845147
Short name T225
Test name
Test status
Simulation time 17833151779 ps
CPU time 23.79 seconds
Started Jun 21 06:00:13 PM PDT 24
Finished Jun 21 06:00:38 PM PDT 24
Peak memory 205196 kb
Host smart-16521644-9b55-4fb8-b1f3-bf801f852cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491845147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.491845147
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.695113871
Short name T209
Test name
Test status
Simulation time 781222882 ps
CPU time 1.13 seconds
Started Jun 21 06:00:09 PM PDT 24
Finished Jun 21 06:00:11 PM PDT 24
Peak memory 205064 kb
Host smart-0936d71e-1122-4478-8327-97ac1552b758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695113871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.695113871
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.283332720
Short name T9
Test name
Test status
Simulation time 8083826127 ps
CPU time 6.06 seconds
Started Jun 21 06:00:06 PM PDT 24
Finished Jun 21 06:00:13 PM PDT 24
Peak memory 205180 kb
Host smart-8f14df38-2b13-44fe-89fd-b6e982c2ab90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283332720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.283332720
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.626504029
Short name T164
Test name
Test status
Simulation time 66394631 ps
CPU time 0.79 seconds
Started Jun 21 05:59:48 PM PDT 24
Finished Jun 21 05:59:50 PM PDT 24
Peak memory 204732 kb
Host smart-432ecd54-b7fa-4c2f-abb9-f0c1228a6eaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626504029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.626504029
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1590819582
Short name T250
Test name
Test status
Simulation time 3062417810 ps
CPU time 8.59 seconds
Started Jun 21 05:59:46 PM PDT 24
Finished Jun 21 05:59:56 PM PDT 24
Peak memory 205136 kb
Host smart-63162a4f-de09-489c-9297-cf45ef016498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590819582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1590819582
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1695119561
Short name T213
Test name
Test status
Simulation time 2560790617 ps
CPU time 2.66 seconds
Started Jun 21 05:59:47 PM PDT 24
Finished Jun 21 05:59:51 PM PDT 24
Peak memory 205112 kb
Host smart-084fd8e0-d8f4-45dd-9dee-9d8e48492f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695119561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1695119561
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3207417157
Short name T219
Test name
Test status
Simulation time 1621349357 ps
CPU time 3.25 seconds
Started Jun 21 05:59:47 PM PDT 24
Finished Jun 21 05:59:51 PM PDT 24
Peak memory 205084 kb
Host smart-ffdf842d-7b04-4447-a26a-1a20bafadc1b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3207417157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3207417157
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.821655714
Short name T199
Test name
Test status
Simulation time 753647337 ps
CPU time 1.02 seconds
Started Jun 21 05:59:46 PM PDT 24
Finished Jun 21 05:59:48 PM PDT 24
Peak memory 204588 kb
Host smart-0a1e3814-fe59-4eb4-a73a-62b3e1c46e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821655714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.821655714
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3535528417
Short name T91
Test name
Test status
Simulation time 9550720962 ps
CPU time 3.04 seconds
Started Jun 21 05:59:48 PM PDT 24
Finished Jun 21 05:59:52 PM PDT 24
Peak memory 205120 kb
Host smart-e05b0ea2-b1c9-4c95-85c7-c0e47f4d8c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535528417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3535528417
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1946241341
Short name T58
Test name
Test status
Simulation time 381780661 ps
CPU time 1.84 seconds
Started Jun 21 05:59:46 PM PDT 24
Finished Jun 21 05:59:48 PM PDT 24
Peak memory 229184 kb
Host smart-6ef6f138-f667-4f44-847e-ba2a972350b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946241341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1946241341
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.3039935481
Short name T35
Test name
Test status
Simulation time 16083098061 ps
CPU time 13.18 seconds
Started Jun 21 05:59:47 PM PDT 24
Finished Jun 21 06:00:02 PM PDT 24
Peak memory 204948 kb
Host smart-2e0f09a1-e145-46af-83e0-9c8c82360aa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039935481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3039935481
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2531220999
Short name T172
Test name
Test status
Simulation time 63277958 ps
CPU time 0.7 seconds
Started Jun 21 06:00:16 PM PDT 24
Finished Jun 21 06:00:18 PM PDT 24
Peak memory 204780 kb
Host smart-8f42796a-23f6-4172-bca7-e75c103f4265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531220999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2531220999
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.4156608104
Short name T149
Test name
Test status
Simulation time 94835655 ps
CPU time 0.77 seconds
Started Jun 21 06:00:17 PM PDT 24
Finished Jun 21 06:00:19 PM PDT 24
Peak memory 204776 kb
Host smart-96a47566-1299-4cc4-a2c8-f206804be62e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156608104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.4156608104
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1965283485
Short name T162
Test name
Test status
Simulation time 90409651 ps
CPU time 0.9 seconds
Started Jun 21 06:00:12 PM PDT 24
Finished Jun 21 06:00:13 PM PDT 24
Peak memory 204784 kb
Host smart-02adb895-e827-44bc-b7a6-63f001343e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965283485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1965283485
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3009131967
Short name T216
Test name
Test status
Simulation time 51519748 ps
CPU time 0.85 seconds
Started Jun 21 06:00:16 PM PDT 24
Finished Jun 21 06:00:18 PM PDT 24
Peak memory 204788 kb
Host smart-322c0642-dbcd-4bc7-8ba4-6f786d7d0197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009131967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3009131967
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.810686141
Short name T74
Test name
Test status
Simulation time 117406805 ps
CPU time 0.73 seconds
Started Jun 21 06:00:15 PM PDT 24
Finished Jun 21 06:00:16 PM PDT 24
Peak memory 204636 kb
Host smart-ee2ca38e-0122-46e4-a76e-50e954eab965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810686141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.810686141
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.186228616
Short name T161
Test name
Test status
Simulation time 141284921 ps
CPU time 0.87 seconds
Started Jun 21 06:00:17 PM PDT 24
Finished Jun 21 06:00:20 PM PDT 24
Peak memory 204784 kb
Host smart-54f0428d-c637-4b85-8a8d-435b5a65850d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186228616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.186228616
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.417998379
Short name T7
Test name
Test status
Simulation time 64397586704 ps
CPU time 39.87 seconds
Started Jun 21 06:00:15 PM PDT 24
Finished Jun 21 06:00:55 PM PDT 24
Peak memory 213152 kb
Host smart-b73d0bdc-8f0e-4aa9-83a7-bb612e603285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417998379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.417998379
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1801175365
Short name T77
Test name
Test status
Simulation time 56757647 ps
CPU time 0.77 seconds
Started Jun 21 06:00:19 PM PDT 24
Finished Jun 21 06:00:21 PM PDT 24
Peak memory 204788 kb
Host smart-31d22908-8467-4c63-ac1d-241494848635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801175365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1801175365
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.2921470394
Short name T141
Test name
Test status
Simulation time 26230630374 ps
CPU time 33.09 seconds
Started Jun 21 06:00:12 PM PDT 24
Finished Jun 21 06:00:46 PM PDT 24
Peak memory 204952 kb
Host smart-5bfdd40b-96c6-4d29-a7f4-b6a8c6abda79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921470394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2921470394
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1557652953
Short name T20
Test name
Test status
Simulation time 200823841 ps
CPU time 0.77 seconds
Started Jun 21 06:00:16 PM PDT 24
Finished Jun 21 06:00:18 PM PDT 24
Peak memory 204784 kb
Host smart-5523ed9f-f84b-4d05-bd80-9480aaf40c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557652953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1557652953
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1315783868
Short name T187
Test name
Test status
Simulation time 64363247 ps
CPU time 0.73 seconds
Started Jun 21 06:00:15 PM PDT 24
Finished Jun 21 06:00:17 PM PDT 24
Peak memory 204804 kb
Host smart-1ada0d4b-7217-4cad-a4a9-0be80b1df15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315783868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1315783868
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1796054073
Short name T148
Test name
Test status
Simulation time 108397597 ps
CPU time 0.72 seconds
Started Jun 21 06:00:18 PM PDT 24
Finished Jun 21 06:00:21 PM PDT 24
Peak memory 204788 kb
Host smart-4adeed43-d8f7-4a1e-92af-79b08e5e70b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796054073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1796054073
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.986951114
Short name T19
Test name
Test status
Simulation time 155557359 ps
CPU time 0.82 seconds
Started Jun 21 05:59:53 PM PDT 24
Finished Jun 21 05:59:55 PM PDT 24
Peak memory 204724 kb
Host smart-171a40e6-90cb-464b-858b-d6b4451c90d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986951114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.986951114
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.111696380
Short name T15
Test name
Test status
Simulation time 34767026545 ps
CPU time 55.34 seconds
Started Jun 21 05:59:46 PM PDT 24
Finished Jun 21 06:00:42 PM PDT 24
Peak memory 213332 kb
Host smart-99ecee22-f554-49d3-ac9d-79602c240e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111696380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.111696380
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1692378755
Short name T241
Test name
Test status
Simulation time 10622877125 ps
CPU time 6.52 seconds
Started Jun 21 05:59:46 PM PDT 24
Finished Jun 21 05:59:53 PM PDT 24
Peak memory 205164 kb
Host smart-a96e30f1-6b37-4b03-9726-1f92ab58e320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692378755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1692378755
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1579853298
Short name T256
Test name
Test status
Simulation time 2477654397 ps
CPU time 7.87 seconds
Started Jun 21 05:59:48 PM PDT 24
Finished Jun 21 05:59:57 PM PDT 24
Peak memory 205124 kb
Host smart-acf5013e-e37d-431d-8d9b-b7f7d7b58d79
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1579853298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1579853298
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.511608915
Short name T6
Test name
Test status
Simulation time 235797452 ps
CPU time 0.84 seconds
Started Jun 21 05:59:46 PM PDT 24
Finished Jun 21 05:59:47 PM PDT 24
Peak memory 204580 kb
Host smart-8d1750ea-d610-4b96-88a0-784b719e2a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511608915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.511608915
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2395554645
Short name T196
Test name
Test status
Simulation time 1461665144 ps
CPU time 4.27 seconds
Started Jun 21 05:59:47 PM PDT 24
Finished Jun 21 05:59:52 PM PDT 24
Peak memory 205128 kb
Host smart-4940987d-3ae7-43f8-bb68-229ad7c6d6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395554645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2395554645
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1490668105
Short name T41
Test name
Test status
Simulation time 784423785 ps
CPU time 3.02 seconds
Started Jun 21 05:59:52 PM PDT 24
Finished Jun 21 05:59:55 PM PDT 24
Peak memory 237360 kb
Host smart-dc99606a-bbe0-47f9-8810-2578e5614183
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490668105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1490668105
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.388155043
Short name T134
Test name
Test status
Simulation time 19660725121 ps
CPU time 45.54 seconds
Started Jun 21 05:59:46 PM PDT 24
Finished Jun 21 06:00:32 PM PDT 24
Peak memory 204952 kb
Host smart-b71ea7dd-f56e-4033-9c62-bdf1c1d4d42d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388155043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.388155043
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.4043982469
Short name T170
Test name
Test status
Simulation time 78475954 ps
CPU time 0.73 seconds
Started Jun 21 06:00:18 PM PDT 24
Finished Jun 21 06:00:20 PM PDT 24
Peak memory 204776 kb
Host smart-f8388719-a6a9-4454-9c33-5918f67f0fee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043982469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.4043982469
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2744106531
Short name T151
Test name
Test status
Simulation time 37997301 ps
CPU time 0.79 seconds
Started Jun 21 06:00:13 PM PDT 24
Finished Jun 21 06:00:14 PM PDT 24
Peak memory 204788 kb
Host smart-8562b554-89b8-4011-a639-ae1bbfcdcc30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744106531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2744106531
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.4075282172
Short name T228
Test name
Test status
Simulation time 64216898 ps
CPU time 0.74 seconds
Started Jun 21 06:00:15 PM PDT 24
Finished Jun 21 06:00:17 PM PDT 24
Peak memory 204652 kb
Host smart-4a0452f1-ce86-46da-8cff-e5d535d8a354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075282172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.4075282172
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.902052774
Short name T157
Test name
Test status
Simulation time 144928222 ps
CPU time 0.79 seconds
Started Jun 21 06:00:19 PM PDT 24
Finished Jun 21 06:00:22 PM PDT 24
Peak memory 204784 kb
Host smart-776cb3c0-6aa1-4058-8297-c98c329071a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902052774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.902052774
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2861617681
Short name T168
Test name
Test status
Simulation time 122113440 ps
CPU time 0.76 seconds
Started Jun 21 06:00:17 PM PDT 24
Finished Jun 21 06:00:19 PM PDT 24
Peak memory 204820 kb
Host smart-981a45dc-a472-4a61-a120-256b9489f378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861617681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2861617681
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2568103772
Short name T63
Test name
Test status
Simulation time 81176191 ps
CPU time 0.94 seconds
Started Jun 21 06:00:17 PM PDT 24
Finished Jun 21 06:00:19 PM PDT 24
Peak memory 204820 kb
Host smart-affa60d8-8ce8-4292-aa1e-244153746bc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568103772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2568103772
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.188067987
Short name T147
Test name
Test status
Simulation time 198500700 ps
CPU time 0.76 seconds
Started Jun 21 06:00:18 PM PDT 24
Finished Jun 21 06:00:20 PM PDT 24
Peak memory 204772 kb
Host smart-8bddc7c3-7f84-4547-9674-4f48c2bd962e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188067987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.188067987
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.668442370
Short name T197
Test name
Test status
Simulation time 79779873 ps
CPU time 0.72 seconds
Started Jun 21 06:00:20 PM PDT 24
Finished Jun 21 06:00:22 PM PDT 24
Peak memory 204760 kb
Host smart-03850554-a3f4-4eb2-87bf-20ea3ff59a4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668442370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.668442370
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.918443937
Short name T156
Test name
Test status
Simulation time 65684017 ps
CPU time 0.8 seconds
Started Jun 21 06:00:23 PM PDT 24
Finished Jun 21 06:00:26 PM PDT 24
Peak memory 204720 kb
Host smart-d9606f23-f89a-4705-978f-262b08e02b60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918443937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.918443937
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.3344675661
Short name T75
Test name
Test status
Simulation time 75211529 ps
CPU time 0.91 seconds
Started Jun 21 06:00:23 PM PDT 24
Finished Jun 21 06:00:26 PM PDT 24
Peak memory 204788 kb
Host smart-c83ab3e7-e8e5-4dca-889a-b26950d1bbe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344675661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3344675661
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.953083684
Short name T242
Test name
Test status
Simulation time 28560178549 ps
CPU time 15.72 seconds
Started Jun 21 06:00:22 PM PDT 24
Finished Jun 21 06:00:40 PM PDT 24
Peak memory 204936 kb
Host smart-142666fd-fbbf-4277-8e5e-5342d5754b81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953083684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.953083684
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3927015953
Short name T190
Test name
Test status
Simulation time 45734091 ps
CPU time 0.78 seconds
Started Jun 21 05:59:54 PM PDT 24
Finished Jun 21 05:59:56 PM PDT 24
Peak memory 204784 kb
Host smart-41ab664d-f7a9-400a-9350-08ea9babb9b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927015953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3927015953
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.291455687
Short name T226
Test name
Test status
Simulation time 117545713367 ps
CPU time 274.95 seconds
Started Jun 21 05:59:54 PM PDT 24
Finished Jun 21 06:04:30 PM PDT 24
Peak memory 213320 kb
Host smart-c3ce2fa0-eb9a-4e4d-87bc-cf8909cf6aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291455687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.291455687
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.869852128
Short name T234
Test name
Test status
Simulation time 1968695339 ps
CPU time 3.86 seconds
Started Jun 21 05:59:53 PM PDT 24
Finished Jun 21 05:59:57 PM PDT 24
Peak memory 205064 kb
Host smart-e732ff7d-9f1e-4f73-9380-236e9ed8d9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869852128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.869852128
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2986441167
Short name T183
Test name
Test status
Simulation time 9025540429 ps
CPU time 9.78 seconds
Started Jun 21 05:59:52 PM PDT 24
Finished Jun 21 06:00:03 PM PDT 24
Peak memory 205108 kb
Host smart-d8933003-e666-442f-a55e-bd7c3206e152
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2986441167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2986441167
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2270763766
Short name T192
Test name
Test status
Simulation time 486372932 ps
CPU time 1.33 seconds
Started Jun 21 05:59:54 PM PDT 24
Finished Jun 21 05:59:56 PM PDT 24
Peak memory 204580 kb
Host smart-6a3cea01-056c-4558-8e50-b3201ff35a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270763766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2270763766
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1550572938
Short name T182
Test name
Test status
Simulation time 5027524465 ps
CPU time 8.75 seconds
Started Jun 21 05:59:55 PM PDT 24
Finished Jun 21 06:00:04 PM PDT 24
Peak memory 205068 kb
Host smart-2605c574-91a7-4dc9-94ec-b8845e1f51fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550572938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1550572938
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1541902572
Short name T57
Test name
Test status
Simulation time 580038269 ps
CPU time 2.55 seconds
Started Jun 21 06:00:00 PM PDT 24
Finished Jun 21 06:00:03 PM PDT 24
Peak memory 229248 kb
Host smart-54e00d44-0d07-47ea-896e-d36c39a066e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541902572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1541902572
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.727580162
Short name T21
Test name
Test status
Simulation time 122487051 ps
CPU time 1.05 seconds
Started Jun 21 06:00:20 PM PDT 24
Finished Jun 21 06:00:22 PM PDT 24
Peak memory 204776 kb
Host smart-8c5c4232-0728-4fff-8456-0f9066b525a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727580162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.727580162
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.2195863620
Short name T33
Test name
Test status
Simulation time 37196488164 ps
CPU time 84.95 seconds
Started Jun 21 06:00:22 PM PDT 24
Finished Jun 21 06:01:50 PM PDT 24
Peak memory 205060 kb
Host smart-b3b7e21d-f24e-4aa2-bbcf-10471993bb11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195863620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2195863620
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.918774642
Short name T177
Test name
Test status
Simulation time 81422001 ps
CPU time 0.78 seconds
Started Jun 21 06:00:21 PM PDT 24
Finished Jun 21 06:00:24 PM PDT 24
Peak memory 204780 kb
Host smart-9a3a5a29-7677-46be-90eb-f52c60e83a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918774642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.918774642
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.4294012396
Short name T207
Test name
Test status
Simulation time 116926803 ps
CPU time 0.86 seconds
Started Jun 21 06:00:21 PM PDT 24
Finished Jun 21 06:00:24 PM PDT 24
Peak memory 204788 kb
Host smart-d03b59a8-b43f-42f7-9284-825c9e80b294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294012396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.4294012396
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.2536018167
Short name T18
Test name
Test status
Simulation time 16670316226 ps
CPU time 42.14 seconds
Started Jun 21 06:00:22 PM PDT 24
Finished Jun 21 06:01:06 PM PDT 24
Peak memory 205024 kb
Host smart-ab1f2653-fc19-4db6-9197-c02781be3ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536018167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2536018167
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.4204596459
Short name T82
Test name
Test status
Simulation time 205946423 ps
CPU time 0.76 seconds
Started Jun 21 06:00:22 PM PDT 24
Finished Jun 21 06:00:26 PM PDT 24
Peak memory 204776 kb
Host smart-dc41afe3-18e4-4cdf-a4f0-537eafe3701d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204596459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.4204596459
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1684711664
Short name T22
Test name
Test status
Simulation time 185105391 ps
CPU time 0.89 seconds
Started Jun 21 06:00:22 PM PDT 24
Finished Jun 21 06:00:26 PM PDT 24
Peak memory 204776 kb
Host smart-912c1d5c-dcaa-4f03-b208-a93440722dd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684711664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1684711664
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.4208372973
Short name T232
Test name
Test status
Simulation time 59855489 ps
CPU time 0.78 seconds
Started Jun 21 06:00:23 PM PDT 24
Finished Jun 21 06:00:26 PM PDT 24
Peak memory 204788 kb
Host smart-a01ea4b7-22f3-4da7-a960-753dcb266e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208372973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.4208372973
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3867589186
Short name T167
Test name
Test status
Simulation time 56757559 ps
CPU time 0.9 seconds
Started Jun 21 06:00:22 PM PDT 24
Finished Jun 21 06:00:25 PM PDT 24
Peak memory 204776 kb
Host smart-59320539-01af-4ca4-a196-b398f351203a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867589186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3867589186
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3954312477
Short name T165
Test name
Test status
Simulation time 41147240 ps
CPU time 0.8 seconds
Started Jun 21 06:00:21 PM PDT 24
Finished Jun 21 06:00:24 PM PDT 24
Peak memory 204784 kb
Host smart-21e82fc8-356c-4ff7-ba3d-ca79b6bbb160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954312477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3954312477
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.2639311706
Short name T3
Test name
Test status
Simulation time 12206714211 ps
CPU time 34.42 seconds
Started Jun 21 06:00:22 PM PDT 24
Finished Jun 21 06:00:59 PM PDT 24
Peak memory 204920 kb
Host smart-18069a2d-3918-4437-8254-62541709040c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639311706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2639311706
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.1570192127
Short name T133
Test name
Test status
Simulation time 29404153405 ps
CPU time 25.59 seconds
Started Jun 21 06:00:22 PM PDT 24
Finished Jun 21 06:00:51 PM PDT 24
Peak memory 213160 kb
Host smart-ff4b3b17-78ec-4fb0-b36b-9ab7ab2cb62b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570192127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1570192127
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.185816743
Short name T76
Test name
Test status
Simulation time 154554923 ps
CPU time 0.79 seconds
Started Jun 21 06:00:20 PM PDT 24
Finished Jun 21 06:00:22 PM PDT 24
Peak memory 204784 kb
Host smart-68c6f6a7-a5ea-48ea-bf08-a73b94a1ef6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185816743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.185816743
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.4281960050
Short name T119
Test name
Test status
Simulation time 49484542 ps
CPU time 0.79 seconds
Started Jun 21 06:00:00 PM PDT 24
Finished Jun 21 06:00:01 PM PDT 24
Peak memory 204784 kb
Host smart-aead12e9-8756-4b38-b940-2f78fca1dd6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281960050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.4281960050
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1866635110
Short name T13
Test name
Test status
Simulation time 866959090 ps
CPU time 1.68 seconds
Started Jun 21 05:59:55 PM PDT 24
Finished Jun 21 05:59:57 PM PDT 24
Peak memory 205040 kb
Host smart-43728fdc-f2bb-4012-8695-2834c4b37376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866635110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1866635110
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3881337963
Short name T244
Test name
Test status
Simulation time 8630777927 ps
CPU time 23.72 seconds
Started Jun 21 05:59:55 PM PDT 24
Finished Jun 21 06:00:20 PM PDT 24
Peak memory 205144 kb
Host smart-4c240d69-05e6-448b-956b-16d15bd1c316
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3881337963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3881337963
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1795434136
Short name T210
Test name
Test status
Simulation time 1696511188 ps
CPU time 5.45 seconds
Started Jun 21 05:59:57 PM PDT 24
Finished Jun 21 06:00:03 PM PDT 24
Peak memory 205116 kb
Host smart-ad3f083d-d4aa-4070-b33b-3a8de15fe215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795434136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1795434136
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1266364099
Short name T152
Test name
Test status
Simulation time 33870502 ps
CPU time 0.8 seconds
Started Jun 21 05:59:53 PM PDT 24
Finished Jun 21 05:59:55 PM PDT 24
Peak memory 204776 kb
Host smart-e2862995-db84-45c9-9089-c038865ccf33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266364099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1266364099
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3642521857
Short name T221
Test name
Test status
Simulation time 32788508302 ps
CPU time 88.7 seconds
Started Jun 21 05:59:55 PM PDT 24
Finished Jun 21 06:01:24 PM PDT 24
Peak memory 213444 kb
Host smart-b0a0bffa-ac4b-4635-a550-28acb29540a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642521857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3642521857
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1035734378
Short name T186
Test name
Test status
Simulation time 2037277855 ps
CPU time 3.93 seconds
Started Jun 21 05:59:54 PM PDT 24
Finished Jun 21 05:59:59 PM PDT 24
Peak memory 205096 kb
Host smart-b65c1be2-e5fd-4b19-b534-86fc7ca71bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035734378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1035734378
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1374113185
Short name T176
Test name
Test status
Simulation time 5213870891 ps
CPU time 8.54 seconds
Started Jun 21 05:59:55 PM PDT 24
Finished Jun 21 06:00:05 PM PDT 24
Peak memory 205152 kb
Host smart-f6f39c5b-8572-4ee6-b21b-57ae8878d79f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374113185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1374113185
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.240843156
Short name T94
Test name
Test status
Simulation time 907416031 ps
CPU time 3.2 seconds
Started Jun 21 05:59:57 PM PDT 24
Finished Jun 21 06:00:01 PM PDT 24
Peak memory 205076 kb
Host smart-4d372e2c-2ce8-4bf6-815f-cb1456573c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240843156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.240843156
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3353229906
Short name T146
Test name
Test status
Simulation time 72479723 ps
CPU time 0.76 seconds
Started Jun 21 06:00:03 PM PDT 24
Finished Jun 21 06:00:06 PM PDT 24
Peak memory 204776 kb
Host smart-9a58690d-83bd-4185-b905-84d80aad2ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353229906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3353229906
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3345301384
Short name T215
Test name
Test status
Simulation time 6660593147 ps
CPU time 11.23 seconds
Started Jun 21 06:00:04 PM PDT 24
Finished Jun 21 06:00:17 PM PDT 24
Peak memory 213332 kb
Host smart-df1524d8-fad6-48e6-8549-11ac8291c471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345301384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3345301384
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.244464648
Short name T60
Test name
Test status
Simulation time 5305615715 ps
CPU time 4.44 seconds
Started Jun 21 06:00:06 PM PDT 24
Finished Jun 21 06:00:12 PM PDT 24
Peak memory 213320 kb
Host smart-cf9a2d9a-6663-424e-8272-66b1432d0ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244464648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.244464648
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2989757728
Short name T243
Test name
Test status
Simulation time 4192507854 ps
CPU time 3.13 seconds
Started Jun 21 05:59:55 PM PDT 24
Finished Jun 21 05:59:59 PM PDT 24
Peak memory 205260 kb
Host smart-b76bd930-3b5e-4ecf-b676-cfe8009b0045
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2989757728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2989757728
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3656783209
Short name T195
Test name
Test status
Simulation time 7525516689 ps
CPU time 8.36 seconds
Started Jun 21 05:59:53 PM PDT 24
Finished Jun 21 06:00:02 PM PDT 24
Peak memory 205152 kb
Host smart-f9c35e2a-503e-4b46-9ae2-06dc32cca5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656783209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3656783209
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.1424622420
Short name T140
Test name
Test status
Simulation time 21419552279 ps
CPU time 57.79 seconds
Started Jun 21 06:00:04 PM PDT 24
Finished Jun 21 06:01:04 PM PDT 24
Peak memory 205008 kb
Host smart-16dc57f3-7a51-41ed-be76-7accb17637b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424622420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1424622420
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2695883202
Short name T155
Test name
Test status
Simulation time 170109367 ps
CPU time 0.75 seconds
Started Jun 21 06:00:04 PM PDT 24
Finished Jun 21 06:00:07 PM PDT 24
Peak memory 204780 kb
Host smart-f63cd2b5-cce1-4a25-b692-9954d34efb2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695883202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2695883202
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1115897121
Short name T249
Test name
Test status
Simulation time 4329978455 ps
CPU time 4.4 seconds
Started Jun 21 06:00:05 PM PDT 24
Finished Jun 21 06:00:11 PM PDT 24
Peak memory 205272 kb
Host smart-ae871a67-94d4-4d07-856a-3d20b9805e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115897121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1115897121
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1785292745
Short name T257
Test name
Test status
Simulation time 4139844061 ps
CPU time 6 seconds
Started Jun 21 06:00:06 PM PDT 24
Finished Jun 21 06:00:13 PM PDT 24
Peak memory 205116 kb
Host smart-d9b957b0-3437-4252-ba2c-aae2c7ca6228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785292745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1785292745
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3249790444
Short name T237
Test name
Test status
Simulation time 1578533941 ps
CPU time 2.51 seconds
Started Jun 21 06:00:04 PM PDT 24
Finished Jun 21 06:00:08 PM PDT 24
Peak memory 205068 kb
Host smart-81395997-966b-4d2b-99e4-e7fff7f2cf07
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3249790444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3249790444
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.504113192
Short name T65
Test name
Test status
Simulation time 3010945818 ps
CPU time 6.41 seconds
Started Jun 21 06:00:02 PM PDT 24
Finished Jun 21 06:00:09 PM PDT 24
Peak memory 205152 kb
Host smart-b36f4268-a7db-47f8-b6c8-9d5967fd7f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504113192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.504113192
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3303166888
Short name T49
Test name
Test status
Simulation time 64128518 ps
CPU time 0.77 seconds
Started Jun 21 06:00:03 PM PDT 24
Finished Jun 21 06:00:06 PM PDT 24
Peak memory 204780 kb
Host smart-0f46498b-034c-4763-9435-9dc1a5f92cf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303166888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3303166888
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.609048956
Short name T231
Test name
Test status
Simulation time 4309334353 ps
CPU time 4.66 seconds
Started Jun 21 06:00:04 PM PDT 24
Finished Jun 21 06:00:10 PM PDT 24
Peak memory 213544 kb
Host smart-9e0bdf09-1111-40b1-a385-a8c211126f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609048956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.609048956
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1874695481
Short name T240
Test name
Test status
Simulation time 13271006147 ps
CPU time 20.53 seconds
Started Jun 21 06:00:04 PM PDT 24
Finished Jun 21 06:00:27 PM PDT 24
Peak memory 215732 kb
Host smart-55fca057-6fde-464f-81ff-8bf6a64d85a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874695481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1874695481
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2787007642
Short name T255
Test name
Test status
Simulation time 7167484256 ps
CPU time 6.22 seconds
Started Jun 21 06:00:05 PM PDT 24
Finished Jun 21 06:00:12 PM PDT 24
Peak memory 205116 kb
Host smart-355683bf-cd5c-4c9d-a195-cc8467c94117
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2787007642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2787007642
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2575287870
Short name T2
Test name
Test status
Simulation time 8998373429 ps
CPU time 15.1 seconds
Started Jun 21 06:00:04 PM PDT 24
Finished Jun 21 06:00:21 PM PDT 24
Peak memory 205120 kb
Host smart-3a999e7d-e4ff-485d-b025-772ea50809a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575287870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2575287870
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.1060157130
Short name T245
Test name
Test status
Simulation time 4375026292 ps
CPU time 13.2 seconds
Started Jun 21 06:00:03 PM PDT 24
Finished Jun 21 06:00:18 PM PDT 24
Peak memory 205020 kb
Host smart-d03d9d71-f02f-49ef-8dd2-f282f7bb8d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060157130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1060157130
Directory /workspace/9.rv_dm_stress_all/latest
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