Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
79.32 94.71 79.17 88.43 71.79 84.83 98.52 37.74


Total test records in report: 411
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T45 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1781208011 Jun 22 04:40:22 PM PDT 24 Jun 22 04:42:03 PM PDT 24 65914404824 ps
T282 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2857788747 Jun 22 04:40:18 PM PDT 24 Jun 22 04:40:20 PM PDT 24 526199714 ps
T101 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.105058460 Jun 22 04:40:20 PM PDT 24 Jun 22 04:40:23 PM PDT 24 139779268 ps
T283 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.729818800 Jun 22 04:40:11 PM PDT 24 Jun 22 04:40:33 PM PDT 24 2422043410 ps
T284 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1254245299 Jun 22 04:40:20 PM PDT 24 Jun 22 04:40:26 PM PDT 24 694471374 ps
T285 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3155955374 Jun 22 04:40:45 PM PDT 24 Jun 22 04:40:47 PM PDT 24 159661038 ps
T286 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1842273133 Jun 22 04:40:28 PM PDT 24 Jun 22 04:40:36 PM PDT 24 215295213 ps
T112 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2032847777 Jun 22 04:40:27 PM PDT 24 Jun 22 04:40:38 PM PDT 24 1928337793 ps
T287 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.397308183 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:31 PM PDT 24 139857934 ps
T288 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1438235432 Jun 22 04:40:31 PM PDT 24 Jun 22 04:40:40 PM PDT 24 2640062753 ps
T130 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.197787919 Jun 22 04:40:03 PM PDT 24 Jun 22 04:40:25 PM PDT 24 1775417927 ps
T107 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2504320765 Jun 22 04:40:17 PM PDT 24 Jun 22 04:40:20 PM PDT 24 367455448 ps
T289 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1237578420 Jun 22 04:40:10 PM PDT 24 Jun 22 04:40:11 PM PDT 24 45705938 ps
T290 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2343755411 Jun 22 04:40:19 PM PDT 24 Jun 22 04:40:22 PM PDT 24 861452213 ps
T291 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3039097417 Jun 22 04:40:21 PM PDT 24 Jun 22 04:42:43 PM PDT 24 48549987813 ps
T292 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.926702806 Jun 22 04:40:22 PM PDT 24 Jun 22 04:40:32 PM PDT 24 219029498 ps
T293 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3643436986 Jun 22 04:40:25 PM PDT 24 Jun 22 04:40:34 PM PDT 24 4620024219 ps
T97 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2392213750 Jun 22 04:40:14 PM PDT 24 Jun 22 04:40:20 PM PDT 24 2124437384 ps
T113 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2862879400 Jun 22 04:40:22 PM PDT 24 Jun 22 04:40:32 PM PDT 24 435424515 ps
T294 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.829027831 Jun 22 04:40:20 PM PDT 24 Jun 22 04:40:23 PM PDT 24 1955469515 ps
T295 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2029449893 Jun 22 04:40:03 PM PDT 24 Jun 22 04:41:29 PM PDT 24 98414765765 ps
T117 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2582499945 Jun 22 04:40:25 PM PDT 24 Jun 22 04:40:30 PM PDT 24 200369643 ps
T296 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3583842381 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:30 PM PDT 24 5639208977 ps
T297 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3939104080 Jun 22 04:40:21 PM PDT 24 Jun 22 04:40:26 PM PDT 24 169308473 ps
T102 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1043358457 Jun 22 04:40:28 PM PDT 24 Jun 22 04:40:34 PM PDT 24 106487527 ps
T298 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2133123515 Jun 22 04:40:26 PM PDT 24 Jun 22 04:40:31 PM PDT 24 577919915 ps
T299 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.502529271 Jun 22 04:40:28 PM PDT 24 Jun 22 04:40:33 PM PDT 24 459736677 ps
T300 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.40078646 Jun 22 04:40:30 PM PDT 24 Jun 22 04:40:36 PM PDT 24 203475562 ps
T301 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1090928868 Jun 22 04:40:40 PM PDT 24 Jun 22 04:40:42 PM PDT 24 268780854 ps
T302 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4293442276 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:34 PM PDT 24 2993816478 ps
T303 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.183144247 Jun 22 04:40:14 PM PDT 24 Jun 22 04:40:18 PM PDT 24 392329734 ps
T304 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3047776387 Jun 22 04:40:28 PM PDT 24 Jun 22 04:42:40 PM PDT 24 45410522561 ps
T305 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.953975976 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:41 PM PDT 24 19260475639 ps
T114 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3531697772 Jun 22 04:40:19 PM PDT 24 Jun 22 04:40:24 PM PDT 24 446172297 ps
T306 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2075474061 Jun 22 04:40:20 PM PDT 24 Jun 22 04:40:34 PM PDT 24 6234748266 ps
T307 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1360048786 Jun 22 04:40:17 PM PDT 24 Jun 22 04:40:21 PM PDT 24 788990919 ps
T308 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1014627874 Jun 22 04:40:14 PM PDT 24 Jun 22 04:40:34 PM PDT 24 2718429590 ps
T309 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.735557713 Jun 22 04:40:10 PM PDT 24 Jun 22 04:40:11 PM PDT 24 56119708 ps
T310 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.125722408 Jun 22 04:40:22 PM PDT 24 Jun 22 04:40:46 PM PDT 24 7338792614 ps
T311 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1884554668 Jun 22 04:40:19 PM PDT 24 Jun 22 04:40:51 PM PDT 24 12590807688 ps
T312 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4225127876 Jun 22 04:40:15 PM PDT 24 Jun 22 04:40:22 PM PDT 24 1977091191 ps
T108 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1810009698 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:29 PM PDT 24 100589246 ps
T313 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2239796763 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:31 PM PDT 24 98264018 ps
T314 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1527486239 Jun 22 04:40:20 PM PDT 24 Jun 22 04:40:29 PM PDT 24 2523575675 ps
T315 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.889884393 Jun 22 04:40:37 PM PDT 24 Jun 22 04:40:43 PM PDT 24 1044003914 ps
T316 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2583841663 Jun 22 04:40:23 PM PDT 24 Jun 22 04:40:29 PM PDT 24 1021751233 ps
T317 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1416616997 Jun 22 04:40:17 PM PDT 24 Jun 22 04:40:24 PM PDT 24 4102441466 ps
T318 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2673023672 Jun 22 04:40:25 PM PDT 24 Jun 22 04:40:31 PM PDT 24 292650789 ps
T319 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1390561115 Jun 22 04:39:58 PM PDT 24 Jun 22 04:40:32 PM PDT 24 4449684810 ps
T320 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3362831312 Jun 22 04:40:15 PM PDT 24 Jun 22 04:40:17 PM PDT 24 113232008 ps
T109 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1884435239 Jun 22 04:40:23 PM PDT 24 Jun 22 04:41:02 PM PDT 24 3692041530 ps
T321 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2431133220 Jun 22 04:40:27 PM PDT 24 Jun 22 04:40:51 PM PDT 24 7570893128 ps
T322 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1520952657 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:34 PM PDT 24 52993324 ps
T323 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3284147094 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:37 PM PDT 24 6696245378 ps
T324 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.616998155 Jun 22 04:41:22 PM PDT 24 Jun 22 04:41:27 PM PDT 24 161593212 ps
T110 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2873927176 Jun 22 04:40:35 PM PDT 24 Jun 22 04:40:37 PM PDT 24 203626198 ps
T111 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1555667959 Jun 22 04:40:08 PM PDT 24 Jun 22 04:40:10 PM PDT 24 308268237 ps
T325 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.28026919 Jun 22 04:40:11 PM PDT 24 Jun 22 04:44:02 PM PDT 24 85511669206 ps
T326 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3750333338 Jun 22 04:40:27 PM PDT 24 Jun 22 04:40:33 PM PDT 24 69036663 ps
T327 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4024690305 Jun 22 04:40:10 PM PDT 24 Jun 22 04:40:15 PM PDT 24 1334262296 ps
T328 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2114579514 Jun 22 04:40:08 PM PDT 24 Jun 22 04:40:09 PM PDT 24 66564050 ps
T329 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1921900106 Jun 22 04:40:19 PM PDT 24 Jun 22 04:40:22 PM PDT 24 437700099 ps
T134 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.637546906 Jun 22 04:40:17 PM PDT 24 Jun 22 04:40:51 PM PDT 24 33397662380 ps
T330 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3083771895 Jun 22 04:40:21 PM PDT 24 Jun 22 04:40:23 PM PDT 24 73764968 ps
T331 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4187153207 Jun 22 04:40:38 PM PDT 24 Jun 22 04:40:40 PM PDT 24 163993219 ps
T332 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3642377212 Jun 22 04:40:13 PM PDT 24 Jun 22 04:40:41 PM PDT 24 661234085 ps
T333 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3438311525 Jun 22 04:40:19 PM PDT 24 Jun 22 04:44:44 PM PDT 24 98965882928 ps
T334 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2112979667 Jun 22 04:40:25 PM PDT 24 Jun 22 04:40:31 PM PDT 24 162187986 ps
T335 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4269771384 Jun 22 04:40:29 PM PDT 24 Jun 22 04:40:35 PM PDT 24 634334034 ps
T336 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3671951736 Jun 22 04:40:06 PM PDT 24 Jun 22 04:40:14 PM PDT 24 3277246378 ps
T337 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1302187977 Jun 22 04:40:20 PM PDT 24 Jun 22 04:40:54 PM PDT 24 2529568194 ps
T338 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.971175968 Jun 22 04:40:35 PM PDT 24 Jun 22 04:40:39 PM PDT 24 954767784 ps
T339 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3618594802 Jun 22 04:40:39 PM PDT 24 Jun 22 04:41:24 PM PDT 24 15910672451 ps
T115 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3083441615 Jun 22 04:40:27 PM PDT 24 Jun 22 04:40:39 PM PDT 24 549975151 ps
T340 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.95576798 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:30 PM PDT 24 471157663 ps
T341 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1250287575 Jun 22 04:40:14 PM PDT 24 Jun 22 04:40:28 PM PDT 24 11434360709 ps
T342 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3900585588 Jun 22 04:40:22 PM PDT 24 Jun 22 04:40:25 PM PDT 24 39090824 ps
T127 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3627149009 Jun 22 04:40:26 PM PDT 24 Jun 22 04:40:50 PM PDT 24 2951534598 ps
T116 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2954895398 Jun 22 04:40:12 PM PDT 24 Jun 22 04:40:16 PM PDT 24 1600602610 ps
T343 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.529454827 Jun 22 04:40:26 PM PDT 24 Jun 22 04:40:36 PM PDT 24 3979266166 ps
T125 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4185126899 Jun 22 04:40:28 PM PDT 24 Jun 22 04:40:37 PM PDT 24 224064762 ps
T344 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1241721672 Jun 22 04:40:19 PM PDT 24 Jun 22 04:43:19 PM PDT 24 70670661615 ps
T98 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2939726047 Jun 22 04:40:21 PM PDT 24 Jun 22 04:40:31 PM PDT 24 8174540364 ps
T345 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3116035112 Jun 22 04:40:25 PM PDT 24 Jun 22 04:40:39 PM PDT 24 1090792325 ps
T346 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.654755820 Jun 22 04:40:23 PM PDT 24 Jun 22 04:40:26 PM PDT 24 94651399 ps
T347 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2040122010 Jun 22 04:40:21 PM PDT 24 Jun 22 04:40:27 PM PDT 24 753863111 ps
T348 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1003029529 Jun 22 04:40:17 PM PDT 24 Jun 22 04:42:27 PM PDT 24 53344726417 ps
T126 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3379409462 Jun 22 04:40:15 PM PDT 24 Jun 22 04:41:05 PM PDT 24 16787346548 ps
T349 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4274883958 Jun 22 04:40:23 PM PDT 24 Jun 22 04:40:30 PM PDT 24 2817840741 ps
T103 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2505470903 Jun 22 04:40:41 PM PDT 24 Jun 22 04:40:46 PM PDT 24 340642290 ps
T350 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.279919080 Jun 22 04:40:22 PM PDT 24 Jun 22 04:40:31 PM PDT 24 263837856 ps
T351 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3123765770 Jun 22 04:40:09 PM PDT 24 Jun 22 04:40:10 PM PDT 24 182456355 ps
T352 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.573029354 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:31 PM PDT 24 1024351131 ps
T104 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.15786233 Jun 22 04:40:21 PM PDT 24 Jun 22 04:40:25 PM PDT 24 339410579 ps
T105 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3056990238 Jun 22 04:40:25 PM PDT 24 Jun 22 04:40:32 PM PDT 24 134182466 ps
T353 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4036741692 Jun 22 04:40:25 PM PDT 24 Jun 22 04:40:33 PM PDT 24 3578912073 ps
T354 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.4203637879 Jun 22 04:40:05 PM PDT 24 Jun 22 04:40:16 PM PDT 24 3680344670 ps
T355 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2895863508 Jun 22 04:40:29 PM PDT 24 Jun 22 04:40:38 PM PDT 24 211568739 ps
T356 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3774145715 Jun 22 04:40:26 PM PDT 24 Jun 22 04:40:32 PM PDT 24 593097342 ps
T357 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1435042610 Jun 22 04:40:21 PM PDT 24 Jun 22 04:40:45 PM PDT 24 5477120186 ps
T358 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3550370024 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:31 PM PDT 24 245029972 ps
T359 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2248059648 Jun 22 04:40:27 PM PDT 24 Jun 22 04:40:38 PM PDT 24 13163119582 ps
T360 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4287940005 Jun 22 04:40:20 PM PDT 24 Jun 22 04:40:23 PM PDT 24 174597970 ps
T361 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3540978346 Jun 22 04:40:22 PM PDT 24 Jun 22 04:40:25 PM PDT 24 723728005 ps
T362 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2941338021 Jun 22 04:40:23 PM PDT 24 Jun 22 04:42:50 PM PDT 24 52327293170 ps
T128 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1142934920 Jun 22 04:40:20 PM PDT 24 Jun 22 04:40:30 PM PDT 24 2162621435 ps
T363 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2815707084 Jun 22 04:40:03 PM PDT 24 Jun 22 04:40:06 PM PDT 24 748742989 ps
T364 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3343539910 Jun 22 04:40:26 PM PDT 24 Jun 22 04:40:36 PM PDT 24 3949054354 ps
T365 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2407816047 Jun 22 04:40:24 PM PDT 24 Jun 22 04:41:27 PM PDT 24 22985940830 ps
T366 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2288950229 Jun 22 04:40:27 PM PDT 24 Jun 22 04:40:37 PM PDT 24 975390371 ps
T367 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.234389204 Jun 22 04:39:59 PM PDT 24 Jun 22 04:40:02 PM PDT 24 525717290 ps
T368 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3456345995 Jun 22 04:40:15 PM PDT 24 Jun 22 04:40:20 PM PDT 24 519591058 ps
T369 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3707266538 Jun 22 04:40:32 PM PDT 24 Jun 22 04:40:36 PM PDT 24 2167536044 ps
T129 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4215670765 Jun 22 04:40:44 PM PDT 24 Jun 22 04:40:55 PM PDT 24 1492168415 ps
T370 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.189526866 Jun 22 04:40:06 PM PDT 24 Jun 22 04:40:12 PM PDT 24 90248954 ps
T371 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1887159862 Jun 22 04:40:16 PM PDT 24 Jun 22 04:40:21 PM PDT 24 413522630 ps
T372 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2043620594 Jun 22 04:40:22 PM PDT 24 Jun 22 04:40:35 PM PDT 24 5678873965 ps
T373 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.539950876 Jun 22 04:40:27 PM PDT 24 Jun 22 04:41:27 PM PDT 24 27998217703 ps
T374 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2860460420 Jun 22 04:40:19 PM PDT 24 Jun 22 04:40:25 PM PDT 24 2218593040 ps
T375 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2908607043 Jun 22 04:40:33 PM PDT 24 Jun 22 04:40:36 PM PDT 24 386444751 ps
T376 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1310730207 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:28 PM PDT 24 653712454 ps
T377 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1530742330 Jun 22 04:40:28 PM PDT 24 Jun 22 04:41:17 PM PDT 24 37054531435 ps
T378 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.427970520 Jun 22 04:40:23 PM PDT 24 Jun 22 04:40:28 PM PDT 24 535908944 ps
T106 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.162984025 Jun 22 04:40:20 PM PDT 24 Jun 22 04:40:29 PM PDT 24 1018589804 ps
T379 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3949739716 Jun 22 04:40:25 PM PDT 24 Jun 22 04:40:59 PM PDT 24 48778049367 ps
T380 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4042063807 Jun 22 04:40:19 PM PDT 24 Jun 22 04:40:28 PM PDT 24 541386227 ps
T381 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3803287932 Jun 22 04:40:17 PM PDT 24 Jun 22 04:41:37 PM PDT 24 19474087487 ps
T382 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.321499771 Jun 22 04:40:27 PM PDT 24 Jun 22 04:40:47 PM PDT 24 13820907704 ps
T383 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3555797620 Jun 22 04:40:23 PM PDT 24 Jun 22 04:40:30 PM PDT 24 173506002 ps
T131 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4218131 Jun 22 04:40:05 PM PDT 24 Jun 22 04:40:27 PM PDT 24 3536522320 ps
T384 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.958013411 Jun 22 04:40:22 PM PDT 24 Jun 22 04:42:40 PM PDT 24 57239911693 ps
T385 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3764067587 Jun 22 04:40:12 PM PDT 24 Jun 22 04:40:13 PM PDT 24 188089975 ps
T386 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.721833831 Jun 22 04:40:20 PM PDT 24 Jun 22 04:40:25 PM PDT 24 301479822 ps
T387 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1029543420 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:29 PM PDT 24 1253068507 ps
T388 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1748506124 Jun 22 04:40:03 PM PDT 24 Jun 22 04:40:10 PM PDT 24 357468812 ps
T389 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2121818317 Jun 22 04:40:26 PM PDT 24 Jun 22 04:40:33 PM PDT 24 3156243132 ps
T390 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2365016928 Jun 22 04:40:25 PM PDT 24 Jun 22 04:40:33 PM PDT 24 856448617 ps
T391 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3370865144 Jun 22 04:40:23 PM PDT 24 Jun 22 04:40:27 PM PDT 24 974253281 ps
T135 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3022775765 Jun 22 04:40:20 PM PDT 24 Jun 22 04:40:57 PM PDT 24 42017018179 ps
T392 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3718938585 Jun 22 04:40:24 PM PDT 24 Jun 22 04:40:48 PM PDT 24 6795727550 ps
T393 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2375548310 Jun 22 04:40:13 PM PDT 24 Jun 22 04:40:15 PM PDT 24 288721063 ps
T394 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2426270061 Jun 22 04:40:26 PM PDT 24 Jun 22 04:41:28 PM PDT 24 68502143443 ps
T395 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3090035038 Jun 22 04:40:22 PM PDT 24 Jun 22 04:40:29 PM PDT 24 1114238595 ps
T396 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.4205368609 Jun 22 04:40:19 PM PDT 24 Jun 22 04:41:14 PM PDT 24 5639941433 ps
T397 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3913192369 Jun 22 04:40:23 PM PDT 24 Jun 22 04:40:36 PM PDT 24 12387657211 ps
T398 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4151498502 Jun 22 04:39:58 PM PDT 24 Jun 22 04:40:37 PM PDT 24 3839576791 ps
T399 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2990454905 Jun 22 04:40:20 PM PDT 24 Jun 22 04:40:24 PM PDT 24 121050368 ps
T132 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2420713324 Jun 22 04:40:14 PM PDT 24 Jun 22 04:40:32 PM PDT 24 1724060739 ps
T400 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.335955370 Jun 22 04:40:23 PM PDT 24 Jun 22 04:40:29 PM PDT 24 240316540 ps
T401 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3058217755 Jun 22 04:40:08 PM PDT 24 Jun 22 04:40:11 PM PDT 24 878936554 ps
T402 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.72618583 Jun 22 04:40:23 PM PDT 24 Jun 22 04:40:26 PM PDT 24 200165049 ps
T403 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.565670926 Jun 22 04:40:29 PM PDT 24 Jun 22 04:40:38 PM PDT 24 2467641070 ps
T133 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3032180544 Jun 22 04:40:23 PM PDT 24 Jun 22 04:40:45 PM PDT 24 4570413652 ps
T404 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2682916989 Jun 22 04:40:04 PM PDT 24 Jun 22 04:40:29 PM PDT 24 26734283594 ps
T405 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4062401980 Jun 22 04:40:26 PM PDT 24 Jun 22 04:40:31 PM PDT 24 182995119 ps
T406 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.509585607 Jun 22 04:40:21 PM PDT 24 Jun 22 04:40:31 PM PDT 24 1062783877 ps
T407 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1040497948 Jun 22 04:40:28 PM PDT 24 Jun 22 04:40:43 PM PDT 24 13098091970 ps
T408 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.496364519 Jun 22 04:40:13 PM PDT 24 Jun 22 04:40:16 PM PDT 24 193584419 ps
T409 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.285928090 Jun 22 04:40:20 PM PDT 24 Jun 22 04:40:41 PM PDT 24 33721662071 ps
T410 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1237774059 Jun 22 04:40:04 PM PDT 24 Jun 22 04:40:07 PM PDT 24 213223345 ps
T411 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2103765689 Jun 22 04:40:16 PM PDT 24 Jun 22 04:40:30 PM PDT 24 2997864158 ps

Test location /workspace/coverage/default/45.rv_dm_stress_all.4228217280
Short name T4
Test name
Test status
Simulation time 13732701466 ps
CPU time 6.54 seconds
Started Jun 22 04:49:17 PM PDT 24
Finished Jun 22 04:49:25 PM PDT 24
Peak memory 213188 kb
Host smart-daf92f37-dc4b-47eb-a588-cb41cf24a1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228217280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.4228217280
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2334684059
Short name T23
Test name
Test status
Simulation time 2939181678 ps
CPU time 7.46 seconds
Started Jun 22 04:48:58 PM PDT 24
Finished Jun 22 04:49:07 PM PDT 24
Peak memory 205140 kb
Host smart-e40f4226-1a0d-40ad-8c22-a7013814313f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334684059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2334684059
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3186316644
Short name T71
Test name
Test status
Simulation time 497697080 ps
CPU time 3 seconds
Started Jun 22 04:40:21 PM PDT 24
Finished Jun 22 04:40:25 PM PDT 24
Peak memory 217760 kb
Host smart-564fb798-5e9b-4676-97ff-835c8efb1b3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186316644 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3186316644
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2357491435
Short name T50
Test name
Test status
Simulation time 35224131 ps
CPU time 0.8 seconds
Started Jun 22 04:49:17 PM PDT 24
Finished Jun 22 04:49:19 PM PDT 24
Peak memory 204652 kb
Host smart-fac6d6e0-ccea-471e-bb68-a8976e26d592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357491435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2357491435
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1781208011
Short name T45
Test name
Test status
Simulation time 65914404824 ps
CPU time 97.73 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:42:03 PM PDT 24
Peak memory 222620 kb
Host smart-e626e362-31b1-4098-a9b1-6819ca53f958
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781208011 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1781208011
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.589993510
Short name T8
Test name
Test status
Simulation time 39775071508 ps
CPU time 59.11 seconds
Started Jun 22 04:49:07 PM PDT 24
Finished Jun 22 04:50:07 PM PDT 24
Peak memory 213128 kb
Host smart-2efc8e8e-c901-416e-af23-cd9d18b00327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589993510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.589993510
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.926754747
Short name T72
Test name
Test status
Simulation time 4051916850 ps
CPU time 19.47 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:49 PM PDT 24
Peak memory 213804 kb
Host smart-c5cfd585-4ca5-4321-a700-7cf3cf2a7450
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926754747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.926754747
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2099548624
Short name T178
Test name
Test status
Simulation time 32515563963 ps
CPU time 78.07 seconds
Started Jun 22 04:49:08 PM PDT 24
Finished Jun 22 04:50:27 PM PDT 24
Peak memory 213364 kb
Host smart-f0e060b1-2bfc-48bc-af90-96406edf9d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099548624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2099548624
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4008350856
Short name T82
Test name
Test status
Simulation time 239750206 ps
CPU time 3.88 seconds
Started Jun 22 04:40:07 PM PDT 24
Finished Jun 22 04:40:12 PM PDT 24
Peak memory 205340 kb
Host smart-3bb66558-b144-4bb7-950b-823a082cc28c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008350856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.4008350856
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.1940231872
Short name T20
Test name
Test status
Simulation time 10457038554 ps
CPU time 16.25 seconds
Started Jun 22 04:49:17 PM PDT 24
Finished Jun 22 04:49:35 PM PDT 24
Peak memory 205012 kb
Host smart-1d20309b-2adc-40b6-86e5-c20ca240712d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940231872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1940231872
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4191694852
Short name T88
Test name
Test status
Simulation time 132178576 ps
CPU time 2.36 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:32 PM PDT 24
Peak memory 213592 kb
Host smart-2bc46db5-320e-4e2a-86f8-10f7c0500569
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191694852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4191694852
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2914330453
Short name T42
Test name
Test status
Simulation time 200648346 ps
CPU time 1.59 seconds
Started Jun 22 04:48:54 PM PDT 24
Finished Jun 22 04:48:56 PM PDT 24
Peak memory 228288 kb
Host smart-ba9837c0-3b54-4c86-a412-adae9dd0f0ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914330453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2914330453
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.263989116
Short name T30
Test name
Test status
Simulation time 38400654186 ps
CPU time 14.66 seconds
Started Jun 22 04:48:57 PM PDT 24
Finished Jun 22 04:49:13 PM PDT 24
Peak memory 213116 kb
Host smart-cf8e9dc2-169e-4065-88f7-cce60f49284c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263989116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.263989116
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.228750100
Short name T76
Test name
Test status
Simulation time 4440797327 ps
CPU time 17.79 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:40:42 PM PDT 24
Peak memory 213712 kb
Host smart-b7311f56-0c73-44cb-9e2f-473ba30945f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228750100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.228750100
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.2361006004
Short name T37
Test name
Test status
Simulation time 203033244 ps
CPU time 0.82 seconds
Started Jun 22 04:48:49 PM PDT 24
Finished Jun 22 04:48:50 PM PDT 24
Peak memory 204692 kb
Host smart-81de0f58-11c4-4116-8a3c-eba41b81cac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361006004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2361006004
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1656674361
Short name T28
Test name
Test status
Simulation time 84093025 ps
CPU time 0.85 seconds
Started Jun 22 04:48:47 PM PDT 24
Finished Jun 22 04:48:49 PM PDT 24
Peak memory 212984 kb
Host smart-2b958d86-8f84-4a33-9f75-9f28ebd2703a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656674361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1656674361
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2974323826
Short name T33
Test name
Test status
Simulation time 1017974019 ps
CPU time 1.42 seconds
Started Jun 22 04:48:42 PM PDT 24
Finished Jun 22 04:48:44 PM PDT 24
Peak memory 204648 kb
Host smart-1bbaa792-0a01-4e44-b489-0b45dd7cc0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974323826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2974323826
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3426908258
Short name T43
Test name
Test status
Simulation time 43424041780 ps
CPU time 28.65 seconds
Started Jun 22 04:40:18 PM PDT 24
Finished Jun 22 04:40:48 PM PDT 24
Peak memory 222052 kb
Host smart-59b09159-29ca-494c-90eb-84c3f2e226fd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426908258 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3426908258
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2964412597
Short name T175
Test name
Test status
Simulation time 57990999571 ps
CPU time 78.34 seconds
Started Jun 22 04:49:09 PM PDT 24
Finished Jun 22 04:50:30 PM PDT 24
Peak memory 221436 kb
Host smart-44afc724-90cf-4a40-92f7-c4b098c46701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964412597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2964412597
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.25352611
Short name T36
Test name
Test status
Simulation time 175698258 ps
CPU time 0.84 seconds
Started Jun 22 04:48:57 PM PDT 24
Finished Jun 22 04:48:59 PM PDT 24
Peak memory 204696 kb
Host smart-7cf2dd30-5308-4313-ad3b-f83a848ea273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25352611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.25352611
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2068803395
Short name T67
Test name
Test status
Simulation time 125341174 ps
CPU time 1.05 seconds
Started Jun 22 04:49:10 PM PDT 24
Finished Jun 22 04:49:13 PM PDT 24
Peak memory 204776 kb
Host smart-5c948ead-822c-4a17-940c-f825abbba89d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068803395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2068803395
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3627149009
Short name T127
Test name
Test status
Simulation time 2951534598 ps
CPU time 20.44 seconds
Started Jun 22 04:40:26 PM PDT 24
Finished Jun 22 04:40:50 PM PDT 24
Peak memory 213748 kb
Host smart-70652532-022d-4149-843f-22d47cbb48b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627149009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
627149009
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3136946398
Short name T272
Test name
Test status
Simulation time 947490466 ps
CPU time 3.14 seconds
Started Jun 22 04:40:10 PM PDT 24
Finished Jun 22 04:40:13 PM PDT 24
Peak memory 205104 kb
Host smart-f0428091-7a57-4dcc-a491-f29f6cbf119e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136946398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3136946398
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.2072796157
Short name T11
Test name
Test status
Simulation time 18861543555 ps
CPU time 10.33 seconds
Started Jun 22 04:48:57 PM PDT 24
Finished Jun 22 04:49:08 PM PDT 24
Peak memory 204732 kb
Host smart-0ad20268-6931-492d-8099-074092225fa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072796157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.2072796157
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3579902015
Short name T95
Test name
Test status
Simulation time 7087719644 ps
CPU time 2.67 seconds
Started Jun 22 04:39:57 PM PDT 24
Finished Jun 22 04:40:06 PM PDT 24
Peak memory 205468 kb
Host smart-93b33c0c-9795-484d-8434-c51f767341aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579902015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3579902015
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1196096099
Short name T25
Test name
Test status
Simulation time 835261927 ps
CPU time 2.85 seconds
Started Jun 22 04:48:42 PM PDT 24
Finished Jun 22 04:48:45 PM PDT 24
Peak memory 204576 kb
Host smart-3c6b4409-231f-4bf4-bac1-efeb95b1023f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196096099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1196096099
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.333601861
Short name T5
Test name
Test status
Simulation time 1892663897 ps
CPU time 3.05 seconds
Started Jun 22 04:48:47 PM PDT 24
Finished Jun 22 04:48:51 PM PDT 24
Peak memory 204672 kb
Host smart-11892010-d9ac-49ef-8072-5a4b955afad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333601861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.333601861
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.699736919
Short name T90
Test name
Test status
Simulation time 30432429045 ps
CPU time 72.48 seconds
Started Jun 22 04:40:15 PM PDT 24
Finished Jun 22 04:41:28 PM PDT 24
Peak memory 213692 kb
Host smart-890affec-acf4-4c65-8093-ead64878df08
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699736919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.699736919
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3417093920
Short name T80
Test name
Test status
Simulation time 723516370 ps
CPU time 2.53 seconds
Started Jun 22 04:40:18 PM PDT 24
Finished Jun 22 04:40:21 PM PDT 24
Peak memory 218336 kb
Host smart-d10012ba-9da3-49df-a8c1-f1e6f689ecd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417093920 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3417093920
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4218131
Short name T131
Test name
Test status
Simulation time 3536522320 ps
CPU time 20.35 seconds
Started Jun 22 04:40:05 PM PDT 24
Finished Jun 22 04:40:27 PM PDT 24
Peak memory 213844 kb
Host smart-a831d8ba-8e21-4bfa-8068-1ffe313666f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.4218131
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3739124915
Short name T93
Test name
Test status
Simulation time 3640041409 ps
CPU time 18.72 seconds
Started Jun 22 04:40:32 PM PDT 24
Finished Jun 22 04:40:52 PM PDT 24
Peak memory 213776 kb
Host smart-6a48ae98-3dfd-40b4-b218-824c2e874b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739124915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
739124915
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1390561115
Short name T319
Test name
Test status
Simulation time 4449684810 ps
CPU time 31.66 seconds
Started Jun 22 04:39:58 PM PDT 24
Finished Jun 22 04:40:32 PM PDT 24
Peak memory 205576 kb
Host smart-d0fd4c76-7be6-4b1a-821b-08640615b8fc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390561115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1390561115
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4151498502
Short name T398
Test name
Test status
Simulation time 3839576791 ps
CPU time 36.96 seconds
Started Jun 22 04:39:58 PM PDT 24
Finished Jun 22 04:40:37 PM PDT 24
Peak memory 214016 kb
Host smart-2acc6e62-17fc-4fc9-bc68-ee111ae82b04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151498502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.4151498502
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1237774059
Short name T410
Test name
Test status
Simulation time 213223345 ps
CPU time 1.71 seconds
Started Jun 22 04:40:04 PM PDT 24
Finished Jun 22 04:40:07 PM PDT 24
Peak memory 213688 kb
Host smart-45539cd8-91ca-4a92-b515-5c9a49649fff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237774059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1237774059
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.189526866
Short name T370
Test name
Test status
Simulation time 90248954 ps
CPU time 4.29 seconds
Started Jun 22 04:40:06 PM PDT 24
Finished Jun 22 04:40:12 PM PDT 24
Peak memory 221916 kb
Host smart-b558d918-1c38-4c87-b7e4-79ba7dd2087c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189526866 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.189526866
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.496364519
Short name T408
Test name
Test status
Simulation time 193584419 ps
CPU time 2.55 seconds
Started Jun 22 04:40:13 PM PDT 24
Finished Jun 22 04:40:16 PM PDT 24
Peak memory 213556 kb
Host smart-2890cb99-354a-4cde-8e8f-6e2a66684b26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496364519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.496364519
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1003029529
Short name T348
Test name
Test status
Simulation time 53344726417 ps
CPU time 129.29 seconds
Started Jun 22 04:40:17 PM PDT 24
Finished Jun 22 04:42:27 PM PDT 24
Peak memory 205404 kb
Host smart-ceec4fba-b7fa-4e84-8dce-022459cef414
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003029529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1003029529
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2029449893
Short name T295
Test name
Test status
Simulation time 98414765765 ps
CPU time 84.26 seconds
Started Jun 22 04:40:03 PM PDT 24
Finished Jun 22 04:41:29 PM PDT 24
Peak memory 205264 kb
Host smart-0e86cf2e-a077-46dc-b86d-9a538ce92bd3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029449893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.2029449893
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.4203637879
Short name T354
Test name
Test status
Simulation time 3680344670 ps
CPU time 9.79 seconds
Started Jun 22 04:40:05 PM PDT 24
Finished Jun 22 04:40:16 PM PDT 24
Peak memory 205404 kb
Host smart-2da28414-1fe9-43f4-bf9f-4ed226baabf5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203637879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.4
203637879
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3058217755
Short name T401
Test name
Test status
Simulation time 878936554 ps
CPU time 2 seconds
Started Jun 22 04:40:08 PM PDT 24
Finished Jun 22 04:40:11 PM PDT 24
Peak memory 205016 kb
Host smart-f690b535-835e-41f5-af6c-682f2f6d8ebf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058217755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3058217755
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1250287575
Short name T341
Test name
Test status
Simulation time 11434360709 ps
CPU time 14 seconds
Started Jun 22 04:40:14 PM PDT 24
Finished Jun 22 04:40:28 PM PDT 24
Peak memory 205240 kb
Host smart-c14b12e2-868c-457f-aef2-064a4d7a1c9b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250287575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1250287575
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2815707084
Short name T363
Test name
Test status
Simulation time 748742989 ps
CPU time 1.37 seconds
Started Jun 22 04:40:03 PM PDT 24
Finished Jun 22 04:40:06 PM PDT 24
Peak memory 205120 kb
Host smart-065d6152-0907-4f9a-85ad-61f4dca6278b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815707084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2
815707084
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1237578420
Short name T289
Test name
Test status
Simulation time 45705938 ps
CPU time 0.78 seconds
Started Jun 22 04:40:10 PM PDT 24
Finished Jun 22 04:40:11 PM PDT 24
Peak memory 205056 kb
Host smart-f1334563-eda6-478c-a7df-93832cea54be
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237578420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1237578420
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.629333075
Short name T266
Test name
Test status
Simulation time 114238109 ps
CPU time 0.75 seconds
Started Jun 22 04:40:11 PM PDT 24
Finished Jun 22 04:40:12 PM PDT 24
Peak memory 204416 kb
Host smart-9e4a9610-150e-4f10-a0c3-a1cade4926c9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629333075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.629333075
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.285928090
Short name T409
Test name
Test status
Simulation time 33721662071 ps
CPU time 19.14 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:41 PM PDT 24
Peak memory 221116 kb
Host smart-23172cca-1a74-4865-b635-f3a4393c6409
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285928090 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.285928090
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1748506124
Short name T388
Test name
Test status
Simulation time 357468812 ps
CPU time 5.18 seconds
Started Jun 22 04:40:03 PM PDT 24
Finished Jun 22 04:40:10 PM PDT 24
Peak memory 213976 kb
Host smart-2f20593b-0481-4420-a050-a2cddb149333
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748506124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1748506124
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3803287932
Short name T381
Test name
Test status
Simulation time 19474087487 ps
CPU time 79.11 seconds
Started Jun 22 04:40:17 PM PDT 24
Finished Jun 22 04:41:37 PM PDT 24
Peak memory 205556 kb
Host smart-36e712a4-0bc2-42d1-ba10-ee4d059c2c5e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803287932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3803287932
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.95576798
Short name T340
Test name
Test status
Simulation time 471157663 ps
CPU time 2.46 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:30 PM PDT 24
Peak memory 213644 kb
Host smart-062b92fc-d318-4072-9409-0a156014afbf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95576798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.95576798
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1416616997
Short name T317
Test name
Test status
Simulation time 4102441466 ps
CPU time 5.93 seconds
Started Jun 22 04:40:17 PM PDT 24
Finished Jun 22 04:40:24 PM PDT 24
Peak memory 221948 kb
Host smart-363f9dc2-645e-43c2-927d-de0a095aec0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416616997 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1416616997
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.105058460
Short name T101
Test name
Test status
Simulation time 139779268 ps
CPU time 2.14 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:23 PM PDT 24
Peak memory 213556 kb
Host smart-1fc6ecae-d6a7-4a66-82e4-0068e349a95a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105058460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.105058460
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.28026919
Short name T325
Test name
Test status
Simulation time 85511669206 ps
CPU time 230.4 seconds
Started Jun 22 04:40:11 PM PDT 24
Finished Jun 22 04:44:02 PM PDT 24
Peak memory 204684 kb
Host smart-05789034-df8a-45cb-ab33-223c72f72281
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28026919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_
aliasing.28026919
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4225127876
Short name T312
Test name
Test status
Simulation time 1977091191 ps
CPU time 6.52 seconds
Started Jun 22 04:40:15 PM PDT 24
Finished Jun 22 04:40:22 PM PDT 24
Peak memory 205300 kb
Host smart-be9d4813-fad7-4f7f-9616-f1dee4e7382d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225127876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.4225127876
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2939726047
Short name T98
Test name
Test status
Simulation time 8174540364 ps
CPU time 8.28 seconds
Started Jun 22 04:40:21 PM PDT 24
Finished Jun 22 04:40:31 PM PDT 24
Peak memory 205552 kb
Host smart-e7bb456c-c2cc-43cc-b5a2-3709e491a830
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939726047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2939726047
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4024690305
Short name T327
Test name
Test status
Simulation time 1334262296 ps
CPU time 4.29 seconds
Started Jun 22 04:40:10 PM PDT 24
Finished Jun 22 04:40:15 PM PDT 24
Peak memory 205284 kb
Host smart-d279d5cc-3b9f-41d7-a048-6ec0804a8643
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024690305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.4
024690305
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1360048786
Short name T307
Test name
Test status
Simulation time 788990919 ps
CPU time 2.62 seconds
Started Jun 22 04:40:17 PM PDT 24
Finished Jun 22 04:40:21 PM PDT 24
Peak memory 205040 kb
Host smart-29af6109-68e5-4237-b67e-a91b52d39e33
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360048786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1360048786
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3671951736
Short name T336
Test name
Test status
Simulation time 3277246378 ps
CPU time 6.79 seconds
Started Jun 22 04:40:06 PM PDT 24
Finished Jun 22 04:40:14 PM PDT 24
Peak memory 205420 kb
Host smart-9e9025bf-6c76-4d75-ad2a-474992aa2055
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671951736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3671951736
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3571169946
Short name T62
Test name
Test status
Simulation time 287171852 ps
CPU time 0.97 seconds
Started Jun 22 04:40:08 PM PDT 24
Finished Jun 22 04:40:10 PM PDT 24
Peak memory 205156 kb
Host smart-3b61f674-4a2d-40dd-9bdf-c32d20f9656e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571169946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3571169946
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.234389204
Short name T367
Test name
Test status
Simulation time 525717290 ps
CPU time 0.98 seconds
Started Jun 22 04:39:59 PM PDT 24
Finished Jun 22 04:40:02 PM PDT 24
Peak memory 205120 kb
Host smart-9fa3fed2-6578-44a3-9e9f-e9991c69968c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234389204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.234389204
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3362831312
Short name T320
Test name
Test status
Simulation time 113232008 ps
CPU time 0.89 seconds
Started Jun 22 04:40:15 PM PDT 24
Finished Jun 22 04:40:17 PM PDT 24
Peak memory 205052 kb
Host smart-8dc3e290-58ec-4b99-9d31-ecb947445315
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362831312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3362831312
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.735557713
Short name T309
Test name
Test status
Simulation time 56119708 ps
CPU time 0.69 seconds
Started Jun 22 04:40:10 PM PDT 24
Finished Jun 22 04:40:11 PM PDT 24
Peak memory 204940 kb
Host smart-24261464-89a1-4ac6-8ea3-4cae7ea4cc6d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735557713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.735557713
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2954895398
Short name T116
Test name
Test status
Simulation time 1600602610 ps
CPU time 3.97 seconds
Started Jun 22 04:40:12 PM PDT 24
Finished Jun 22 04:40:16 PM PDT 24
Peak memory 205412 kb
Host smart-a49bf83d-aed4-4110-8dcb-c48a3568c490
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954895398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2954895398
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3379409462
Short name T126
Test name
Test status
Simulation time 16787346548 ps
CPU time 48.67 seconds
Started Jun 22 04:40:15 PM PDT 24
Finished Jun 22 04:41:05 PM PDT 24
Peak memory 221032 kb
Host smart-4a43780d-6a53-4a6f-9377-a4f28bf78abd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379409462 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3379409462
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.183144247
Short name T303
Test name
Test status
Simulation time 392329734 ps
CPU time 3.21 seconds
Started Jun 22 04:40:14 PM PDT 24
Finished Jun 22 04:40:18 PM PDT 24
Peak memory 213696 kb
Host smart-e5ca7385-a173-4653-a595-9baf5182a313
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183144247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.183144247
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.729818800
Short name T283
Test name
Test status
Simulation time 2422043410 ps
CPU time 21.39 seconds
Started Jun 22 04:40:11 PM PDT 24
Finished Jun 22 04:40:33 PM PDT 24
Peak memory 213684 kb
Host smart-af1888e3-f8d8-4c44-9b91-8ddae2206a29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729818800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.729818800
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.758617716
Short name T87
Test name
Test status
Simulation time 224535883 ps
CPU time 1.74 seconds
Started Jun 22 04:40:26 PM PDT 24
Finished Jun 22 04:40:32 PM PDT 24
Peak memory 213588 kb
Host smart-77a2b359-2762-4df0-90ca-e1b401e95131
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758617716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.758617716
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3047776387
Short name T304
Test name
Test status
Simulation time 45410522561 ps
CPU time 124.52 seconds
Started Jun 22 04:40:28 PM PDT 24
Finished Jun 22 04:42:40 PM PDT 24
Peak memory 205332 kb
Host smart-c9963afd-497d-4969-b4ac-ae8dd391475f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047776387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.3047776387
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.917311855
Short name T276
Test name
Test status
Simulation time 4492776151 ps
CPU time 7.04 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:33 PM PDT 24
Peak memory 205332 kb
Host smart-da5f4ed3-70a3-4737-bc92-dbb60e414cc5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917311855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.917311855
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3088140876
Short name T269
Test name
Test status
Simulation time 686670809 ps
CPU time 1.44 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:30 PM PDT 24
Peak memory 205028 kb
Host smart-e4067680-d487-40fd-9655-c577413c8fb6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088140876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3088140876
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2505470903
Short name T103
Test name
Test status
Simulation time 340642290 ps
CPU time 4.06 seconds
Started Jun 22 04:40:41 PM PDT 24
Finished Jun 22 04:40:46 PM PDT 24
Peak memory 205412 kb
Host smart-f95f3bd8-1c79-4fa3-9b3a-7e5ae28d2b53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505470903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2505470903
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2239796763
Short name T313
Test name
Test status
Simulation time 98264018 ps
CPU time 2.62 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:31 PM PDT 24
Peak memory 213696 kb
Host smart-9478c716-9cdb-4f89-be5a-a32d47207cc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239796763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2239796763
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3116035112
Short name T345
Test name
Test status
Simulation time 1090792325 ps
CPU time 10.8 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:39 PM PDT 24
Peak memory 213648 kb
Host smart-54f636b1-6012-481a-b3ca-3c4d9dc2dfd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116035112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
116035112
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4269771384
Short name T335
Test name
Test status
Simulation time 634334034 ps
CPU time 2.38 seconds
Started Jun 22 04:40:29 PM PDT 24
Finished Jun 22 04:40:35 PM PDT 24
Peak memory 213556 kb
Host smart-f44f003c-33aa-4d36-a268-a4077701c7c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269771384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4269771384
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1520952657
Short name T322
Test name
Test status
Simulation time 52993324 ps
CPU time 0.77 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:34 PM PDT 24
Peak memory 204948 kb
Host smart-2b6579ff-9efa-41bb-a3f1-3c5376d5cf4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520952657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1520952657
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3284147094
Short name T323
Test name
Test status
Simulation time 6696245378 ps
CPU time 10.15 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:37 PM PDT 24
Peak memory 205352 kb
Host smart-9e5a37e6-d2ff-4891-be37-58c41d14758a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284147094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3284147094
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3370865144
Short name T391
Test name
Test status
Simulation time 974253281 ps
CPU time 0.94 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:27 PM PDT 24
Peak memory 205036 kb
Host smart-52d513a2-53fc-429a-bc44-cccb38a48475
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370865144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3370865144
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3624425459
Short name T89
Test name
Test status
Simulation time 269568057 ps
CPU time 4.12 seconds
Started Jun 22 04:40:38 PM PDT 24
Finished Jun 22 04:40:43 PM PDT 24
Peak memory 205504 kb
Host smart-7891d360-2f76-4bb0-9cf2-d8dacb1f0027
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624425459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3624425459
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3939104080
Short name T297
Test name
Test status
Simulation time 169308473 ps
CPU time 2.79 seconds
Started Jun 22 04:40:21 PM PDT 24
Finished Jun 22 04:40:26 PM PDT 24
Peak memory 213636 kb
Host smart-b448716a-5fbb-4667-92e8-8ce3a3d63d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939104080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3939104080
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4036741692
Short name T353
Test name
Test status
Simulation time 3578912073 ps
CPU time 3.61 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:33 PM PDT 24
Peak memory 221804 kb
Host smart-a1be22b2-af35-4751-8459-f0c466b8e337
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036741692 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.4036741692
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4187153207
Short name T331
Test name
Test status
Simulation time 163993219 ps
CPU time 1.61 seconds
Started Jun 22 04:40:38 PM PDT 24
Finished Jun 22 04:40:40 PM PDT 24
Peak memory 213676 kb
Host smart-a8178681-8de3-4a01-baef-597f370a34ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187153207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.4187153207
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.4083800009
Short name T268
Test name
Test status
Simulation time 34389221777 ps
CPU time 68.65 seconds
Started Jun 22 04:40:27 PM PDT 24
Finished Jun 22 04:41:40 PM PDT 24
Peak memory 205356 kb
Host smart-34d4c08c-90a5-4d0e-8183-2c2edc37e66b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083800009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.4083800009
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3343539910
Short name T364
Test name
Test status
Simulation time 3949054354 ps
CPU time 6.03 seconds
Started Jun 22 04:40:26 PM PDT 24
Finished Jun 22 04:40:36 PM PDT 24
Peak memory 205348 kb
Host smart-9af11ee5-3e9c-441e-b591-9fc587ff96d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343539910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3343539910
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.4062401980
Short name T405
Test name
Test status
Simulation time 182995119 ps
CPU time 0.8 seconds
Started Jun 22 04:40:26 PM PDT 24
Finished Jun 22 04:40:31 PM PDT 24
Peak memory 205136 kb
Host smart-affe2ef9-07ce-4ae6-a512-04e3dd0e5bd4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062401980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
4062401980
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3083441615
Short name T115
Test name
Test status
Simulation time 549975151 ps
CPU time 7.73 seconds
Started Jun 22 04:40:27 PM PDT 24
Finished Jun 22 04:40:39 PM PDT 24
Peak memory 205376 kb
Host smart-ef4c2270-4b5e-4a99-bf64-961e39cc35b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083441615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3083441615
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2583841663
Short name T316
Test name
Test status
Simulation time 1021751233 ps
CPU time 4.59 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:29 PM PDT 24
Peak memory 213628 kb
Host smart-5438ea5c-e321-400b-8bdd-3ec802d869bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583841663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2583841663
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1854488524
Short name T92
Test name
Test status
Simulation time 780191707 ps
CPU time 10.23 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:39 PM PDT 24
Peak memory 213708 kb
Host smart-6b38612d-21ce-4e17-abc2-a5a74df2fcb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854488524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
854488524
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.889884393
Short name T315
Test name
Test status
Simulation time 1044003914 ps
CPU time 4.75 seconds
Started Jun 22 04:40:37 PM PDT 24
Finished Jun 22 04:40:43 PM PDT 24
Peak memory 219908 kb
Host smart-f36ae6d9-aa4f-4da4-a272-6be66243ee73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889884393 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.889884393
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2908607043
Short name T375
Test name
Test status
Simulation time 386444751 ps
CPU time 2.23 seconds
Started Jun 22 04:40:33 PM PDT 24
Finished Jun 22 04:40:36 PM PDT 24
Peak memory 213580 kb
Host smart-b904ebb3-0f46-4cfd-9265-55c75063535c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908607043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2908607043
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2124495340
Short name T275
Test name
Test status
Simulation time 12032813622 ps
CPU time 13.69 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:35 PM PDT 24
Peak memory 205428 kb
Host smart-6a5dbb6f-9818-47c3-b8d1-d5e4a1127231
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124495340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2124495340
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2164905293
Short name T274
Test name
Test status
Simulation time 1151030406 ps
CPU time 1.46 seconds
Started Jun 22 04:40:21 PM PDT 24
Finished Jun 22 04:40:24 PM PDT 24
Peak memory 205224 kb
Host smart-1e485b31-853a-48e8-9580-564ed6bc3590
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164905293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2164905293
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.654755820
Short name T346
Test name
Test status
Simulation time 94651399 ps
CPU time 0.78 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:26 PM PDT 24
Peak memory 205120 kb
Host smart-477ad251-d28c-4202-8ed5-45242b5e46d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654755820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.654755820
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.162984025
Short name T106
Test name
Test status
Simulation time 1018589804 ps
CPU time 7.3 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:29 PM PDT 24
Peak memory 205380 kb
Host smart-5827456c-9197-4e05-994e-2c6929a8b4cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162984025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.162984025
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2040122010
Short name T347
Test name
Test status
Simulation time 753863111 ps
CPU time 4.02 seconds
Started Jun 22 04:40:21 PM PDT 24
Finished Jun 22 04:40:27 PM PDT 24
Peak memory 216096 kb
Host smart-ceca04de-0de7-4a75-9b1e-aa98f224e0e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040122010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2040122010
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3032180544
Short name T133
Test name
Test status
Simulation time 4570413652 ps
CPU time 18.98 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:45 PM PDT 24
Peak memory 213696 kb
Host smart-28b9b64d-618f-4cdc-9ced-f09ac8d0a386
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032180544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
032180544
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4274883958
Short name T349
Test name
Test status
Simulation time 2817840741 ps
CPU time 4.76 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:30 PM PDT 24
Peak memory 217956 kb
Host smart-bd208ff5-bdbb-45a6-a711-792efcdcd49b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274883958 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4274883958
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3707266538
Short name T369
Test name
Test status
Simulation time 2167536044 ps
CPU time 2.64 seconds
Started Jun 22 04:40:32 PM PDT 24
Finished Jun 22 04:40:36 PM PDT 24
Peak memory 205364 kb
Host smart-217740c6-b18b-4468-9016-ecee4efcbcad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707266538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.3707266538
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2248059648
Short name T359
Test name
Test status
Simulation time 13163119582 ps
CPU time 6.76 seconds
Started Jun 22 04:40:27 PM PDT 24
Finished Jun 22 04:40:38 PM PDT 24
Peak memory 205348 kb
Host smart-077b620c-a59d-4bf1-9f14-e736a51632bf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248059648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2248059648
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3137629383
Short name T263
Test name
Test status
Simulation time 486466100 ps
CPU time 1.74 seconds
Started Jun 22 04:40:26 PM PDT 24
Finished Jun 22 04:40:32 PM PDT 24
Peak memory 205112 kb
Host smart-bcf4fe98-de64-4eff-84a5-9afaae0f5513
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137629383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
3137629383
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2862879400
Short name T113
Test name
Test status
Simulation time 435424515 ps
CPU time 7.34 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:40:32 PM PDT 24
Peak memory 205380 kb
Host smart-5ec853c1-f2ce-410b-9204-7f118f58efb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862879400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2862879400
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1254245299
Short name T284
Test name
Test status
Simulation time 694471374 ps
CPU time 4.27 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:26 PM PDT 24
Peak memory 213948 kb
Host smart-d0b6d378-8e40-4921-be13-30368b438c6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254245299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1254245299
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.280231271
Short name T75
Test name
Test status
Simulation time 2124298774 ps
CPU time 19.74 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:46 PM PDT 24
Peak memory 213580 kb
Host smart-04db156d-b670-48ff-9716-bfe94d82a1cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280231271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.280231271
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1438235432
Short name T288
Test name
Test status
Simulation time 2640062753 ps
CPU time 6.52 seconds
Started Jun 22 04:40:31 PM PDT 24
Finished Jun 22 04:40:40 PM PDT 24
Peak memory 221804 kb
Host smart-7e1c5d26-262c-4bb6-a982-5768213b88b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438235432 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1438235432
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2873927176
Short name T110
Test name
Test status
Simulation time 203626198 ps
CPU time 1.55 seconds
Started Jun 22 04:40:35 PM PDT 24
Finished Jun 22 04:40:37 PM PDT 24
Peak memory 213572 kb
Host smart-1a6a38e9-6c55-4e13-a1c7-47eef1e8f9e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873927176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2873927176
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.953975976
Short name T305
Test name
Test status
Simulation time 19260475639 ps
CPU time 14.53 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:41 PM PDT 24
Peak memory 205444 kb
Host smart-4abcdffe-9db1-423c-86d3-961e34868798
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953975976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rv_dm_jtag_dmi_csr_bit_bash.953975976
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3718938585
Short name T392
Test name
Test status
Simulation time 6795727550 ps
CPU time 18.05 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:48 PM PDT 24
Peak memory 205328 kb
Host smart-d78ba628-6902-4604-8e86-0693d9e72d9c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718938585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3718938585
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3090132054
Short name T280
Test name
Test status
Simulation time 240547729 ps
CPU time 1.41 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:27 PM PDT 24
Peak memory 205124 kb
Host smart-4c880aea-3b42-46d1-a55c-c3b0445b2916
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090132054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3090132054
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.427970520
Short name T378
Test name
Test status
Simulation time 535908944 ps
CPU time 3.49 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:28 PM PDT 24
Peak memory 205360 kb
Host smart-be4bc06b-3dd6-43ed-a7b3-798e590c9abe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427970520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_
csr_outstanding.427970520
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3555797620
Short name T383
Test name
Test status
Simulation time 173506002 ps
CPU time 4.66 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:30 PM PDT 24
Peak memory 213604 kb
Host smart-bc1f2049-ad14-41ee-b296-106d99317418
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555797620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3555797620
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.565670926
Short name T403
Test name
Test status
Simulation time 2467641070 ps
CPU time 5.49 seconds
Started Jun 22 04:40:29 PM PDT 24
Finished Jun 22 04:40:38 PM PDT 24
Peak memory 221860 kb
Host smart-885ce492-b1c3-40fe-90c5-03b9b6040a93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565670926 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.565670926
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2112979667
Short name T334
Test name
Test status
Simulation time 162187986 ps
CPU time 1.48 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:31 PM PDT 24
Peak memory 213656 kb
Host smart-f49fd472-1be1-4279-bfeb-a50418f6b3d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112979667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2112979667
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.321499771
Short name T382
Test name
Test status
Simulation time 13820907704 ps
CPU time 16.19 seconds
Started Jun 22 04:40:27 PM PDT 24
Finished Jun 22 04:40:47 PM PDT 24
Peak memory 205404 kb
Host smart-356e80e8-5733-48e9-8447-aaac62b9386c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321499771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
rv_dm_jtag_dmi_csr_bit_bash.321499771
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2121818317
Short name T389
Test name
Test status
Simulation time 3156243132 ps
CPU time 3.18 seconds
Started Jun 22 04:40:26 PM PDT 24
Finished Jun 22 04:40:33 PM PDT 24
Peak memory 205348 kb
Host smart-47f463f8-6c7a-491b-b2b7-55b1c41ad0f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121818317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2121818317
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.72618583
Short name T402
Test name
Test status
Simulation time 200165049 ps
CPU time 0.85 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:26 PM PDT 24
Peak memory 205124 kb
Host smart-53b440ec-ac82-49c1-969f-616e4fc8d446
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72618583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.72618583
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2365016928
Short name T390
Test name
Test status
Simulation time 856448617 ps
CPU time 4.29 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:33 PM PDT 24
Peak memory 205432 kb
Host smart-2c034309-adca-48e4-bb6e-af9a1bd76280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365016928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.2365016928
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1842273133
Short name T286
Test name
Test status
Simulation time 215295213 ps
CPU time 3.73 seconds
Started Jun 22 04:40:28 PM PDT 24
Finished Jun 22 04:40:36 PM PDT 24
Peak memory 213636 kb
Host smart-d7c2699a-0455-4b05-8540-b45827265a32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842273133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1842273133
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.335955370
Short name T400
Test name
Test status
Simulation time 240316540 ps
CPU time 3.66 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:29 PM PDT 24
Peak memory 218624 kb
Host smart-1ad90c0d-7c20-4d3c-9f19-1b62a73f2f8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335955370 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.335955370
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2673023672
Short name T318
Test name
Test status
Simulation time 292650789 ps
CPU time 1.52 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:31 PM PDT 24
Peak memory 213536 kb
Host smart-b1b2f9b6-6169-4ac8-a1cd-894842769d71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673023672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2673023672
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3618594802
Short name T339
Test name
Test status
Simulation time 15910672451 ps
CPU time 45.19 seconds
Started Jun 22 04:40:39 PM PDT 24
Finished Jun 22 04:41:24 PM PDT 24
Peak memory 205444 kb
Host smart-e8bb4d79-96bb-4452-90dc-9cdd0ad44654
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618594802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.3618594802
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.971175968
Short name T338
Test name
Test status
Simulation time 954767784 ps
CPU time 3.35 seconds
Started Jun 22 04:40:35 PM PDT 24
Finished Jun 22 04:40:39 PM PDT 24
Peak memory 205204 kb
Host smart-00d21ff1-8f9b-46b3-8dfc-36ea9ded0c64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971175968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.971175968
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.502529271
Short name T299
Test name
Test status
Simulation time 459736677 ps
CPU time 0.86 seconds
Started Jun 22 04:40:28 PM PDT 24
Finished Jun 22 04:40:33 PM PDT 24
Peak memory 205024 kb
Host smart-bcd4c2d8-876e-44fd-b577-64c94207b64a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502529271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.502529271
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1393652394
Short name T91
Test name
Test status
Simulation time 686612205 ps
CPU time 8.07 seconds
Started Jun 22 04:40:34 PM PDT 24
Finished Jun 22 04:40:43 PM PDT 24
Peak memory 205284 kb
Host smart-dc8d6137-4e37-438b-b89a-90ca490b309d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393652394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1393652394
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2990454905
Short name T399
Test name
Test status
Simulation time 121050368 ps
CPU time 2.42 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:24 PM PDT 24
Peak memory 213644 kb
Host smart-18f5031d-fca5-4b56-9a01-0d11fc2af500
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990454905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2990454905
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1186736082
Short name T53
Test name
Test status
Simulation time 2488997747 ps
CPU time 9.7 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:40:34 PM PDT 24
Peak memory 213684 kb
Host smart-8fd1e210-2aee-4a7e-ad9f-61842210b4b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186736082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
186736082
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.529454827
Short name T343
Test name
Test status
Simulation time 3979266166 ps
CPU time 5.27 seconds
Started Jun 22 04:40:26 PM PDT 24
Finished Jun 22 04:40:36 PM PDT 24
Peak memory 219380 kb
Host smart-22be893f-58e4-4bb4-bae3-b0bcc8db3591
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529454827 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.529454827
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1810009698
Short name T108
Test name
Test status
Simulation time 100589246 ps
CPU time 2.3 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:29 PM PDT 24
Peak memory 213552 kb
Host smart-a55f144b-f818-44f3-8da7-d65e5a6f1f39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810009698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1810009698
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.539950876
Short name T373
Test name
Test status
Simulation time 27998217703 ps
CPU time 55.92 seconds
Started Jun 22 04:40:27 PM PDT 24
Finished Jun 22 04:41:27 PM PDT 24
Peak memory 205460 kb
Host smart-215f9fbe-6b1d-40ee-ba02-fb8ebf0ff997
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539950876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rv_dm_jtag_dmi_csr_bit_bash.539950876
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2345489290
Short name T278
Test name
Test status
Simulation time 2774258332 ps
CPU time 3.05 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:29 PM PDT 24
Peak memory 205424 kb
Host smart-08e18cf2-e120-4773-921b-6a0a8b7d7465
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345489290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2345489290
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2133123515
Short name T298
Test name
Test status
Simulation time 577919915 ps
CPU time 1.05 seconds
Started Jun 22 04:40:26 PM PDT 24
Finished Jun 22 04:40:31 PM PDT 24
Peak memory 205116 kb
Host smart-1d6ddf39-c3c0-439a-9273-9ae06b0951c9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133123515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2133123515
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3056990238
Short name T105
Test name
Test status
Simulation time 134182466 ps
CPU time 3.68 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:32 PM PDT 24
Peak memory 205368 kb
Host smart-b91ce22d-4d41-4c39-9832-46b9f45920c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056990238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3056990238
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2895863508
Short name T355
Test name
Test status
Simulation time 211568739 ps
CPU time 5.33 seconds
Started Jun 22 04:40:29 PM PDT 24
Finished Jun 22 04:40:38 PM PDT 24
Peak memory 213664 kb
Host smart-7f4500d6-5dbb-46f8-8fd8-924d0ca372ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895863508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2895863508
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1754480481
Short name T94
Test name
Test status
Simulation time 215936175 ps
CPU time 2.36 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:24 PM PDT 24
Peak memory 216584 kb
Host smart-e76d07ab-5f79-43ad-8aa2-f6f213019c11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754480481 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1754480481
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2413894886
Short name T100
Test name
Test status
Simulation time 199944780 ps
CPU time 2.15 seconds
Started Jun 22 04:40:26 PM PDT 24
Finished Jun 22 04:40:33 PM PDT 24
Peak memory 213620 kb
Host smart-3d87fb06-9c69-4f37-bd24-94544a32003b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413894886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2413894886
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1530742330
Short name T377
Test name
Test status
Simulation time 37054531435 ps
CPU time 44.89 seconds
Started Jun 22 04:40:28 PM PDT 24
Finished Jun 22 04:41:17 PM PDT 24
Peak memory 205328 kb
Host smart-c6e8f84d-1ef4-4b7b-b29f-0ac2f4284d9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530742330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.1530742330
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.319284831
Short name T264
Test name
Test status
Simulation time 1349896920 ps
CPU time 1.13 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:29 PM PDT 24
Peak memory 205128 kb
Host smart-96d3543d-564e-40f0-9a55-c8a2d24bb2eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319284831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.319284831
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3155955374
Short name T285
Test name
Test status
Simulation time 159661038 ps
CPU time 0.78 seconds
Started Jun 22 04:40:45 PM PDT 24
Finished Jun 22 04:40:47 PM PDT 24
Peak memory 204968 kb
Host smart-79616f74-7e70-42dd-bf2b-14134632e3c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155955374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3155955374
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2032847777
Short name T112
Test name
Test status
Simulation time 1928337793 ps
CPU time 7.09 seconds
Started Jun 22 04:40:27 PM PDT 24
Finished Jun 22 04:40:38 PM PDT 24
Peak memory 205776 kb
Host smart-c8cbf1ae-948e-4efd-9b56-0d107570d4bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032847777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2032847777
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1887159862
Short name T371
Test name
Test status
Simulation time 413522630 ps
CPU time 4.05 seconds
Started Jun 22 04:40:16 PM PDT 24
Finished Jun 22 04:40:21 PM PDT 24
Peak memory 213620 kb
Host smart-3ab96c86-4c4d-40bd-96fa-041ee7459a7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887159862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1887159862
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4215670765
Short name T129
Test name
Test status
Simulation time 1492168415 ps
CPU time 10.5 seconds
Started Jun 22 04:40:44 PM PDT 24
Finished Jun 22 04:40:55 PM PDT 24
Peak memory 213576 kb
Host smart-873748dc-db67-4730-8443-c042e88e2a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215670765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4
215670765
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3642377212
Short name T332
Test name
Test status
Simulation time 661234085 ps
CPU time 27.06 seconds
Started Jun 22 04:40:13 PM PDT 24
Finished Jun 22 04:40:41 PM PDT 24
Peak memory 213632 kb
Host smart-bbb9f67f-e963-4f62-aa6b-0d9c7896a617
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642377212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3642377212
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1302187977
Short name T337
Test name
Test status
Simulation time 2529568194 ps
CPU time 31.91 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:54 PM PDT 24
Peak memory 205492 kb
Host smart-2ef27f08-f6ef-4d8e-990b-0cfda0bbb360
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302187977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1302187977
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1555667959
Short name T111
Test name
Test status
Simulation time 308268237 ps
CPU time 1.87 seconds
Started Jun 22 04:40:08 PM PDT 24
Finished Jun 22 04:40:10 PM PDT 24
Peak memory 213668 kb
Host smart-ed57a69f-381e-412d-8f20-bf90c31501f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555667959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1555667959
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.432307025
Short name T73
Test name
Test status
Simulation time 206912087 ps
CPU time 2.36 seconds
Started Jun 22 04:40:13 PM PDT 24
Finished Jun 22 04:40:16 PM PDT 24
Peak memory 221744 kb
Host smart-35b13b43-7358-4977-a845-07e5aaf71429
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432307025 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.432307025
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1921900106
Short name T329
Test name
Test status
Simulation time 437700099 ps
CPU time 2.37 seconds
Started Jun 22 04:40:19 PM PDT 24
Finished Jun 22 04:40:22 PM PDT 24
Peak memory 213680 kb
Host smart-1cf10865-19f8-47fa-9d5a-336121e208a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921900106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1921900106
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.958013411
Short name T384
Test name
Test status
Simulation time 57239911693 ps
CPU time 136.4 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:42:40 PM PDT 24
Peak memory 205384 kb
Host smart-1d742047-a5fc-4e71-a0b0-488da5472c5b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958013411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.958013411
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1435042610
Short name T357
Test name
Test status
Simulation time 5477120186 ps
CPU time 15.44 seconds
Started Jun 22 04:40:21 PM PDT 24
Finished Jun 22 04:40:45 PM PDT 24
Peak memory 205416 kb
Host smart-5e018693-e85c-4d12-af0f-0cb0795a48db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435042610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1435042610
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2392213750
Short name T97
Test name
Test status
Simulation time 2124437384 ps
CPU time 5.89 seconds
Started Jun 22 04:40:14 PM PDT 24
Finished Jun 22 04:40:20 PM PDT 24
Peak memory 205368 kb
Host smart-34d1190b-88a6-40a3-bf22-9d64d01adad9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392213750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2392213750
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1048969677
Short name T271
Test name
Test status
Simulation time 1287868901 ps
CPU time 3.66 seconds
Started Jun 22 04:40:13 PM PDT 24
Finished Jun 22 04:40:22 PM PDT 24
Peak memory 205200 kb
Host smart-c009270d-9d74-45c8-8331-2dfdc0b44053
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048969677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
048969677
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1871389959
Short name T281
Test name
Test status
Simulation time 1225472054 ps
CPU time 1.19 seconds
Started Jun 22 04:40:09 PM PDT 24
Finished Jun 22 04:40:10 PM PDT 24
Peak memory 205044 kb
Host smart-99346db9-b78c-478f-b376-a18e740ac094
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871389959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.1871389959
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.125722408
Short name T310
Test name
Test status
Simulation time 7338792614 ps
CPU time 22.1 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:40:46 PM PDT 24
Peak memory 205344 kb
Host smart-3fb21a38-28e1-4e0e-93a4-19311a5efb84
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125722408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.125722408
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.926702806
Short name T292
Test name
Test status
Simulation time 219029498 ps
CPU time 0.81 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:40:32 PM PDT 24
Peak memory 205120 kb
Host smart-448d0a83-4984-4968-9172-3dfbe195a203
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926702806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.926702806
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2343755411
Short name T290
Test name
Test status
Simulation time 861452213 ps
CPU time 1.28 seconds
Started Jun 22 04:40:19 PM PDT 24
Finished Jun 22 04:40:22 PM PDT 24
Peak memory 205120 kb
Host smart-65d8117e-8150-4480-af77-7afd0f76780f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343755411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
343755411
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3123765770
Short name T351
Test name
Test status
Simulation time 182456355 ps
CPU time 0.74 seconds
Started Jun 22 04:40:09 PM PDT 24
Finished Jun 22 04:40:10 PM PDT 24
Peak memory 204980 kb
Host smart-eae621fb-29cb-4bdd-b64c-034e07ec2093
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123765770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3123765770
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2114579514
Short name T328
Test name
Test status
Simulation time 66564050 ps
CPU time 0.67 seconds
Started Jun 22 04:40:08 PM PDT 24
Finished Jun 22 04:40:09 PM PDT 24
Peak memory 205124 kb
Host smart-ddb54035-dcc4-4eb9-ae04-3e370d667c1f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114579514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2114579514
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2107701392
Short name T84
Test name
Test status
Simulation time 1076537569 ps
CPU time 7.56 seconds
Started Jun 22 04:40:17 PM PDT 24
Finished Jun 22 04:40:25 PM PDT 24
Peak memory 205404 kb
Host smart-1cc82944-00dc-4b13-acce-ff3f11eac401
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107701392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2107701392
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.4077009615
Short name T44
Test name
Test status
Simulation time 21308508251 ps
CPU time 58.87 seconds
Started Jun 22 04:40:04 PM PDT 24
Finished Jun 22 04:41:05 PM PDT 24
Peak memory 221956 kb
Host smart-1dd163e1-dbbb-4ac4-bd78-dd8dd8b70e45
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077009615 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.4077009615
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.721833831
Short name T386
Test name
Test status
Simulation time 301479822 ps
CPU time 3.77 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:25 PM PDT 24
Peak memory 213632 kb
Host smart-bbd2e692-cfdd-4333-a001-53e53f846802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721833831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.721833831
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.197787919
Short name T130
Test name
Test status
Simulation time 1775417927 ps
CPU time 20.87 seconds
Started Jun 22 04:40:03 PM PDT 24
Finished Jun 22 04:40:25 PM PDT 24
Peak memory 213640 kb
Host smart-7ae0210f-198f-44f0-8db5-357d3fc41e88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197787919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.197787919
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3301688229
Short name T99
Test name
Test status
Simulation time 19572394938 ps
CPU time 34.71 seconds
Started Jun 22 04:40:09 PM PDT 24
Finished Jun 22 04:40:44 PM PDT 24
Peak memory 213732 kb
Host smart-91590d7f-f49a-4e15-9062-b8b1979eb47b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301688229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3301688229
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.4205368609
Short name T396
Test name
Test status
Simulation time 5639941433 ps
CPU time 53.87 seconds
Started Jun 22 04:40:19 PM PDT 24
Finished Jun 22 04:41:14 PM PDT 24
Peak memory 213752 kb
Host smart-7ba52d4b-749d-4279-bd76-3bedc7d46c29
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205368609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.4205368609
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.550816599
Short name T83
Test name
Test status
Simulation time 480404542 ps
CPU time 1.8 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:23 PM PDT 24
Peak memory 213600 kb
Host smart-9902e39b-3d93-427e-ab66-ab5793f7deb7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550816599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.550816599
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3009667454
Short name T51
Test name
Test status
Simulation time 1008298163 ps
CPU time 3.52 seconds
Started Jun 22 04:40:11 PM PDT 24
Finished Jun 22 04:40:15 PM PDT 24
Peak memory 218692 kb
Host smart-ac065f82-f9e2-4dd0-a317-a8d6e2e86829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009667454 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3009667454
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2504320765
Short name T107
Test name
Test status
Simulation time 367455448 ps
CPU time 2.29 seconds
Started Jun 22 04:40:17 PM PDT 24
Finished Jun 22 04:40:20 PM PDT 24
Peak memory 213576 kb
Host smart-444b5a37-7617-43f8-8155-93d6c32e501b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504320765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2504320765
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1241721672
Short name T344
Test name
Test status
Simulation time 70670661615 ps
CPU time 179.4 seconds
Started Jun 22 04:40:19 PM PDT 24
Finished Jun 22 04:43:19 PM PDT 24
Peak memory 205332 kb
Host smart-0d1f7235-48ea-4309-a3c1-0383f788a3f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241721672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1241721672
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2682916989
Short name T404
Test name
Test status
Simulation time 26734283594 ps
CPU time 23.11 seconds
Started Jun 22 04:40:04 PM PDT 24
Finished Jun 22 04:40:29 PM PDT 24
Peak memory 205424 kb
Host smart-fc273596-adea-4552-9e97-639dd8566696
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682916989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.2682916989
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.829027831
Short name T294
Test name
Test status
Simulation time 1955469515 ps
CPU time 1.57 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:23 PM PDT 24
Peak memory 205412 kb
Host smart-9adc86a2-6e1f-46ad-a18f-b6971e51b828
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829027831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.829027831
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3027566308
Short name T279
Test name
Test status
Simulation time 1365145922 ps
CPU time 3.2 seconds
Started Jun 22 04:40:17 PM PDT 24
Finished Jun 22 04:40:21 PM PDT 24
Peak memory 205212 kb
Host smart-8777274c-d427-4c2c-9773-edbe3e3f9cf5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027566308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
027566308
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2234088912
Short name T63
Test name
Test status
Simulation time 420317232 ps
CPU time 1.33 seconds
Started Jun 22 04:40:17 PM PDT 24
Finished Jun 22 04:40:19 PM PDT 24
Peak memory 205020 kb
Host smart-2a78c331-0a40-4024-a6d9-b9773c65b93c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234088912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2234088912
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3583842381
Short name T296
Test name
Test status
Simulation time 5639208977 ps
CPU time 2.99 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:30 PM PDT 24
Peak memory 205340 kb
Host smart-89d9a7af-33b0-445c-b3bf-e8d7a045be27
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583842381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3583842381
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3774145715
Short name T356
Test name
Test status
Simulation time 593097342 ps
CPU time 1.98 seconds
Started Jun 22 04:40:26 PM PDT 24
Finished Jun 22 04:40:32 PM PDT 24
Peak memory 205120 kb
Host smart-35b1ea69-2c28-4f72-953b-b14351780e32
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774145715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3774145715
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4287940005
Short name T360
Test name
Test status
Simulation time 174597970 ps
CPU time 1.13 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:23 PM PDT 24
Peak memory 205112 kb
Host smart-705a1848-ea6b-4d5f-939e-9f9c20d7d64f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287940005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.4
287940005
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1690237758
Short name T277
Test name
Test status
Simulation time 157152702 ps
CPU time 0.69 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:26 PM PDT 24
Peak memory 204988 kb
Host smart-e8b3fe85-a5ea-4a2a-b5c9-e9b1809af79c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690237758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1690237758
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3083387454
Short name T262
Test name
Test status
Simulation time 116147792 ps
CPU time 0.92 seconds
Started Jun 22 04:40:19 PM PDT 24
Finished Jun 22 04:40:21 PM PDT 24
Peak memory 205096 kb
Host smart-50dc244e-9fad-405c-be51-3a267807745a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083387454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3083387454
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.279919080
Short name T350
Test name
Test status
Simulation time 263837856 ps
CPU time 6.74 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:40:31 PM PDT 24
Peak memory 205356 kb
Host smart-db1cb857-7a2c-4569-9703-ec291370e29e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279919080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.279919080
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.616998155
Short name T324
Test name
Test status
Simulation time 161593212 ps
CPU time 2.83 seconds
Started Jun 22 04:41:22 PM PDT 24
Finished Jun 22 04:41:27 PM PDT 24
Peak memory 213712 kb
Host smart-1c176b23-044c-4ea9-910e-2efd1b71a8b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616998155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.616998155
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1014627874
Short name T308
Test name
Test status
Simulation time 2718429590 ps
CPU time 19.36 seconds
Started Jun 22 04:40:14 PM PDT 24
Finished Jun 22 04:40:34 PM PDT 24
Peak memory 213768 kb
Host smart-b9630423-87dc-4a48-a7f5-dca0abf666bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014627874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1014627874
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1884554668
Short name T311
Test name
Test status
Simulation time 12590807688 ps
CPU time 31.54 seconds
Started Jun 22 04:40:19 PM PDT 24
Finished Jun 22 04:40:51 PM PDT 24
Peak memory 213756 kb
Host smart-2d458ecc-ef33-4c70-a1a5-74c3cffca62d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884554668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1884554668
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1884435239
Short name T109
Test name
Test status
Simulation time 3692041530 ps
CPU time 36.2 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:41:02 PM PDT 24
Peak memory 205484 kb
Host smart-4e588868-0e87-4c33-ae4b-23c44e14f5a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884435239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1884435239
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2375548310
Short name T393
Test name
Test status
Simulation time 288721063 ps
CPU time 1.74 seconds
Started Jun 22 04:40:13 PM PDT 24
Finished Jun 22 04:40:15 PM PDT 24
Peak memory 213616 kb
Host smart-99f38e32-4dc7-40ab-bba4-bee50f98fd13
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375548310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2375548310
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2075474061
Short name T306
Test name
Test status
Simulation time 6234748266 ps
CPU time 12.36 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:34 PM PDT 24
Peak memory 219844 kb
Host smart-bc2d9cd5-f858-48b5-a05b-77e6d8b441fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075474061 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2075474061
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1090928868
Short name T301
Test name
Test status
Simulation time 268780854 ps
CPU time 1.55 seconds
Started Jun 22 04:40:40 PM PDT 24
Finished Jun 22 04:40:42 PM PDT 24
Peak memory 213956 kb
Host smart-57116533-7af7-4e23-9e0d-f04e81d3393d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090928868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1090928868
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1894324532
Short name T260
Test name
Test status
Simulation time 286008134656 ps
CPU time 114.15 seconds
Started Jun 22 04:40:21 PM PDT 24
Finished Jun 22 04:42:17 PM PDT 24
Peak memory 215284 kb
Host smart-9404562f-3b43-49f9-a830-1e82ac0af6cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894324532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1894324532
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3039097417
Short name T291
Test name
Test status
Simulation time 48549987813 ps
CPU time 140.12 seconds
Started Jun 22 04:40:21 PM PDT 24
Finished Jun 22 04:42:43 PM PDT 24
Peak memory 205332 kb
Host smart-5b9db377-fa0a-4959-9008-aeb811334ad9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039097417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.3039097417
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4228041857
Short name T96
Test name
Test status
Simulation time 25256877104 ps
CPU time 17.24 seconds
Started Jun 22 04:40:18 PM PDT 24
Finished Jun 22 04:40:36 PM PDT 24
Peak memory 205552 kb
Host smart-c5d8ce39-d868-4dd3-9932-9419e7d66e4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228041857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.4228041857
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1527486239
Short name T314
Test name
Test status
Simulation time 2523575675 ps
CPU time 7.48 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:29 PM PDT 24
Peak memory 205348 kb
Host smart-b9922b31-7fb6-49d5-8bf5-80d4b8f7f558
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527486239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
527486239
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1807303694
Short name T267
Test name
Test status
Simulation time 1123286855 ps
CPU time 1.54 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:23 PM PDT 24
Peak memory 205052 kb
Host smart-124e1d9c-d9f7-48aa-8d61-f8ce72aa82f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807303694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1807303694
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2407816047
Short name T365
Test name
Test status
Simulation time 22985940830 ps
CPU time 59.81 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:41:27 PM PDT 24
Peak memory 205420 kb
Host smart-5e7e1717-075f-4b4e-a4d9-77d1697b939c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407816047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2407816047
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2857788747
Short name T282
Test name
Test status
Simulation time 526199714 ps
CPU time 1.36 seconds
Started Jun 22 04:40:18 PM PDT 24
Finished Jun 22 04:40:20 PM PDT 24
Peak memory 205084 kb
Host smart-cdfbf3a4-4b2c-49a7-b4c7-7932fe34ee41
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857788747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2857788747
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3764067587
Short name T385
Test name
Test status
Simulation time 188089975 ps
CPU time 0.96 seconds
Started Jun 22 04:40:12 PM PDT 24
Finished Jun 22 04:40:13 PM PDT 24
Peak memory 205120 kb
Host smart-b6de4c70-c5d7-461e-83ee-c41b9deb0cc1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764067587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
764067587
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3900585588
Short name T342
Test name
Test status
Simulation time 39090824 ps
CPU time 0.74 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:40:25 PM PDT 24
Peak memory 205036 kb
Host smart-8fecf3c4-95cd-409e-b6d1-6c5a143bb553
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900585588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3900585588
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.511475739
Short name T265
Test name
Test status
Simulation time 32566489 ps
CPU time 0.74 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:31 PM PDT 24
Peak memory 205052 kb
Host smart-a17f51d5-ea5f-4c69-9da0-0dc358b99c8b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511475739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.511475739
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3945264411
Short name T86
Test name
Test status
Simulation time 589086175 ps
CPU time 4.37 seconds
Started Jun 22 04:40:21 PM PDT 24
Finished Jun 22 04:40:27 PM PDT 24
Peak memory 205436 kb
Host smart-e1cc99f5-da6e-4bd7-a649-4cadfb6fed37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945264411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3945264411
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.637546906
Short name T134
Test name
Test status
Simulation time 33397662380 ps
CPU time 33.41 seconds
Started Jun 22 04:40:17 PM PDT 24
Finished Jun 22 04:40:51 PM PDT 24
Peak memory 222036 kb
Host smart-434c0a23-f11c-4a52-a753-90c165d5c0a4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637546906 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.637546906
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2288950229
Short name T366
Test name
Test status
Simulation time 975390371 ps
CPU time 5.75 seconds
Started Jun 22 04:40:27 PM PDT 24
Finished Jun 22 04:40:37 PM PDT 24
Peak memory 213740 kb
Host smart-2b3140c2-b6a8-4e9e-a605-30c1a491a7bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288950229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2288950229
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2103765689
Short name T411
Test name
Test status
Simulation time 2997864158 ps
CPU time 13.44 seconds
Started Jun 22 04:40:16 PM PDT 24
Finished Jun 22 04:40:30 PM PDT 24
Peak memory 213724 kb
Host smart-640d9f08-c2a3-45b6-b8ca-31c9daacd61b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103765689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2103765689
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1978817459
Short name T52
Test name
Test status
Simulation time 331785376 ps
CPU time 5.33 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:34 PM PDT 24
Peak memory 221928 kb
Host smart-d65342b1-a2de-4aa2-ab3f-f10d9719238f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978817459 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1978817459
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2582499945
Short name T117
Test name
Test status
Simulation time 200369643 ps
CPU time 1.55 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:30 PM PDT 24
Peak memory 213620 kb
Host smart-3290e5ec-9c34-4980-a3ae-95ddf3b62b48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582499945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2582499945
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2552517460
Short name T270
Test name
Test status
Simulation time 31415789806 ps
CPU time 28.23 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:49 PM PDT 24
Peak memory 205344 kb
Host smart-1397189d-c625-433c-8dd9-09147d576526
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552517460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.2552517460
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4293442276
Short name T302
Test name
Test status
Simulation time 2993816478 ps
CPU time 5.34 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:34 PM PDT 24
Peak memory 205368 kb
Host smart-7f45f7a6-f4b3-4640-9f0e-cb98ae24b24e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293442276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.4
293442276
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1679023849
Short name T64
Test name
Test status
Simulation time 686313472 ps
CPU time 2.31 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:30 PM PDT 24
Peak memory 205020 kb
Host smart-f72a3743-da35-4f35-ba45-e71fdc8230ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679023849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
679023849
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2860460420
Short name T374
Test name
Test status
Simulation time 2218593040 ps
CPU time 4.15 seconds
Started Jun 22 04:40:19 PM PDT 24
Finished Jun 22 04:40:25 PM PDT 24
Peak memory 205772 kb
Host smart-ded5a426-a8de-4fd9-9c4a-97917500e490
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860460420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2860460420
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1511229664
Short name T77
Test name
Test status
Simulation time 82039732 ps
CPU time 3.98 seconds
Started Jun 22 04:40:19 PM PDT 24
Finished Jun 22 04:40:23 PM PDT 24
Peak memory 213620 kb
Host smart-b48a62d3-5da8-457d-9d55-03f69ea6df92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511229664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1511229664
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1154797250
Short name T65
Test name
Test status
Simulation time 3397760772 ps
CPU time 10.83 seconds
Started Jun 22 04:40:16 PM PDT 24
Finished Jun 22 04:40:28 PM PDT 24
Peak memory 213824 kb
Host smart-61a40895-03c4-4e83-ac6f-c84737d553d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154797250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1154797250
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3186618595
Short name T79
Test name
Test status
Simulation time 317308025 ps
CPU time 2.12 seconds
Started Jun 22 04:40:26 PM PDT 24
Finished Jun 22 04:40:32 PM PDT 24
Peak memory 215996 kb
Host smart-c826963d-def1-445e-93b1-abeb298f356b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186618595 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3186618595
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3750333338
Short name T326
Test name
Test status
Simulation time 69036663 ps
CPU time 1.49 seconds
Started Jun 22 04:40:27 PM PDT 24
Finished Jun 22 04:40:33 PM PDT 24
Peak memory 213608 kb
Host smart-08dd5e84-7810-4152-a354-e06b3d073969
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750333338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3750333338
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1040497948
Short name T407
Test name
Test status
Simulation time 13098091970 ps
CPU time 11.06 seconds
Started Jun 22 04:40:28 PM PDT 24
Finished Jun 22 04:40:43 PM PDT 24
Peak memory 205328 kb
Host smart-f0683e3d-90bb-4520-ba35-d4e78da60dce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040497948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.1040497948
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3913192369
Short name T397
Test name
Test status
Simulation time 12387657211 ps
CPU time 9.96 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:40:36 PM PDT 24
Peak memory 205388 kb
Host smart-a5f9d0fc-1173-45b7-99e9-5e91a21413d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913192369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
913192369
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1378276182
Short name T273
Test name
Test status
Simulation time 268491660 ps
CPU time 1.25 seconds
Started Jun 22 04:40:37 PM PDT 24
Finished Jun 22 04:40:39 PM PDT 24
Peak memory 205056 kb
Host smart-e8fa49a8-507a-4825-8356-1a086453fe87
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378276182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
378276182
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3531697772
Short name T114
Test name
Test status
Simulation time 446172297 ps
CPU time 3.72 seconds
Started Jun 22 04:40:19 PM PDT 24
Finished Jun 22 04:40:24 PM PDT 24
Peak memory 205380 kb
Host smart-c3bd4c95-63d4-47cb-b1a4-13cf9e886f32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531697772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3531697772
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3022775765
Short name T135
Test name
Test status
Simulation time 42017018179 ps
CPU time 34.95 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:57 PM PDT 24
Peak memory 221948 kb
Host smart-65e8bb81-a7d6-4110-ba56-80c5d2936319
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022775765 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3022775765
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3188947970
Short name T74
Test name
Test status
Simulation time 3675817948 ps
CPU time 5.4 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:40:33 PM PDT 24
Peak memory 213736 kb
Host smart-f97226c5-4abe-40b2-bc33-93cf37b99f8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188947970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3188947970
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3922791078
Short name T78
Test name
Test status
Simulation time 928404275 ps
CPU time 9.98 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:38 PM PDT 24
Peak memory 213564 kb
Host smart-d72411a7-e662-4c67-984e-1ade1737173d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922791078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3922791078
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.573029354
Short name T352
Test name
Test status
Simulation time 1024351131 ps
CPU time 2.54 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:31 PM PDT 24
Peak memory 221872 kb
Host smart-b62904f7-401e-452f-b083-e32abf24417e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573029354 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.573029354
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.15786233
Short name T104
Test name
Test status
Simulation time 339410579 ps
CPU time 2.18 seconds
Started Jun 22 04:40:21 PM PDT 24
Finished Jun 22 04:40:25 PM PDT 24
Peak memory 213608 kb
Host smart-4bccd957-5c5d-4831-b6ee-8f5650565d24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15786233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.15786233
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3438311525
Short name T333
Test name
Test status
Simulation time 98965882928 ps
CPU time 265.01 seconds
Started Jun 22 04:40:19 PM PDT 24
Finished Jun 22 04:44:44 PM PDT 24
Peak memory 205420 kb
Host smart-9eb13431-1f57-4629-9799-ded8ebf07abb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438311525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.3438311525
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2043620594
Short name T372
Test name
Test status
Simulation time 5678873965 ps
CPU time 11.09 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:40:35 PM PDT 24
Peak memory 205336 kb
Host smart-2bcfeeec-477c-4c2b-80e1-288ec3bd8e62
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043620594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
043620594
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3540978346
Short name T361
Test name
Test status
Simulation time 723728005 ps
CPU time 1.36 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:40:25 PM PDT 24
Peak memory 205348 kb
Host smart-d3c44b70-411a-4df9-8668-7cb44cd7c2bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540978346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
540978346
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3090035038
Short name T395
Test name
Test status
Simulation time 1114238595 ps
CPU time 4.05 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:40:29 PM PDT 24
Peak memory 205512 kb
Host smart-51b64c54-a2cf-4b7d-9b74-7f388ba11810
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090035038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3090035038
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2426270061
Short name T394
Test name
Test status
Simulation time 68502143443 ps
CPU time 58.17 seconds
Started Jun 22 04:40:26 PM PDT 24
Finished Jun 22 04:41:28 PM PDT 24
Peak memory 224160 kb
Host smart-6b1ec59e-7cf5-4aed-9741-e8e410f5d3c8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426270061 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2426270061
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4185126899
Short name T125
Test name
Test status
Simulation time 224064762 ps
CPU time 4.47 seconds
Started Jun 22 04:40:28 PM PDT 24
Finished Jun 22 04:40:37 PM PDT 24
Peak memory 213600 kb
Host smart-a649a519-9ba2-4c7f-aa73-18f814d2bd3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185126899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4185126899
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1142934920
Short name T128
Test name
Test status
Simulation time 2162621435 ps
CPU time 9.68 seconds
Started Jun 22 04:40:20 PM PDT 24
Finished Jun 22 04:40:30 PM PDT 24
Peak memory 214000 kb
Host smart-4f2c9b26-122e-4f90-9a7a-c54ea768b4fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142934920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1142934920
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3643436986
Short name T293
Test name
Test status
Simulation time 4620024219 ps
CPU time 5.22 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:34 PM PDT 24
Peak memory 220296 kb
Host smart-736e398f-6e01-4e0c-9671-f7a657c8a736
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643436986 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3643436986
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1043358457
Short name T102
Test name
Test status
Simulation time 106487527 ps
CPU time 1.69 seconds
Started Jun 22 04:40:28 PM PDT 24
Finished Jun 22 04:40:34 PM PDT 24
Peak memory 213536 kb
Host smart-21f1f4e0-6f23-43de-a0ab-49189bda1a9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043358457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1043358457
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3949739716
Short name T379
Test name
Test status
Simulation time 48778049367 ps
CPU time 29.97 seconds
Started Jun 22 04:40:25 PM PDT 24
Finished Jun 22 04:40:59 PM PDT 24
Peak memory 205424 kb
Host smart-6664e2f6-9084-4081-8c1f-c674663b8a01
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949739716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.3949739716
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2437244853
Short name T261
Test name
Test status
Simulation time 15505787030 ps
CPU time 12.85 seconds
Started Jun 22 04:40:22 PM PDT 24
Finished Jun 22 04:40:37 PM PDT 24
Peak memory 205356 kb
Host smart-b32d7066-8966-4bd5-bcbb-e14d16e65af6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437244853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2
437244853
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1310730207
Short name T376
Test name
Test status
Simulation time 653712454 ps
CPU time 1.24 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:28 PM PDT 24
Peak memory 205028 kb
Host smart-98e1cd61-a51b-4670-b8d2-c24995fd5ec3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310730207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1
310730207
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4042063807
Short name T380
Test name
Test status
Simulation time 541386227 ps
CPU time 7.46 seconds
Started Jun 22 04:40:19 PM PDT 24
Finished Jun 22 04:40:28 PM PDT 24
Peak memory 205404 kb
Host smart-6ac94378-d7d5-45ad-93a5-00ceaca7a287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042063807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.4042063807
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.397308183
Short name T287
Test name
Test status
Simulation time 139857934 ps
CPU time 3.4 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:31 PM PDT 24
Peak memory 216212 kb
Host smart-ad37f1ba-44c9-4960-a0bc-508a4371e3ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397308183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.397308183
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.509585607
Short name T406
Test name
Test status
Simulation time 1062783877 ps
CPU time 9.38 seconds
Started Jun 22 04:40:21 PM PDT 24
Finished Jun 22 04:40:31 PM PDT 24
Peak memory 213588 kb
Host smart-7b12fce1-0de7-4ac2-9eca-a70590531162
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509585607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.509585607
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3550370024
Short name T358
Test name
Test status
Simulation time 245029972 ps
CPU time 2.3 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:31 PM PDT 24
Peak memory 213592 kb
Host smart-3ca4ef8c-5ac7-4bf2-a276-dc682294e4a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550370024 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3550370024
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1084489505
Short name T85
Test name
Test status
Simulation time 285190068 ps
CPU time 1.53 seconds
Started Jun 22 04:40:26 PM PDT 24
Finished Jun 22 04:40:32 PM PDT 24
Peak memory 213604 kb
Host smart-2362bd87-de89-429b-bc22-105e3e41720c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084489505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1084489505
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3083771895
Short name T330
Test name
Test status
Simulation time 73764968 ps
CPU time 0.73 seconds
Started Jun 22 04:40:21 PM PDT 24
Finished Jun 22 04:40:23 PM PDT 24
Peak memory 205044 kb
Host smart-70febbc3-8b6b-4794-b46c-e07baf75b656
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083771895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3083771895
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2431133220
Short name T321
Test name
Test status
Simulation time 7570893128 ps
CPU time 19.66 seconds
Started Jun 22 04:40:27 PM PDT 24
Finished Jun 22 04:40:51 PM PDT 24
Peak memory 205376 kb
Host smart-5ccf5d3b-b48e-4cf7-a01e-c71fbe4ed385
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431133220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
431133220
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1029543420
Short name T387
Test name
Test status
Simulation time 1253068507 ps
CPU time 1.82 seconds
Started Jun 22 04:40:24 PM PDT 24
Finished Jun 22 04:40:29 PM PDT 24
Peak memory 205048 kb
Host smart-d2dc01b0-316f-47ef-9701-539902fea0dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029543420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
029543420
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3456345995
Short name T368
Test name
Test status
Simulation time 519591058 ps
CPU time 4.45 seconds
Started Jun 22 04:40:15 PM PDT 24
Finished Jun 22 04:40:20 PM PDT 24
Peak memory 205356 kb
Host smart-76b8b74c-e315-40d0-878f-ce71157f7038
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456345995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3456345995
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2941338021
Short name T362
Test name
Test status
Simulation time 52327293170 ps
CPU time 141.52 seconds
Started Jun 22 04:40:23 PM PDT 24
Finished Jun 22 04:42:50 PM PDT 24
Peak memory 222300 kb
Host smart-9d056ba6-5ac6-44dd-aed2-e4000ae6d3f1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941338021 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2941338021
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.40078646
Short name T300
Test name
Test status
Simulation time 203475562 ps
CPU time 2.82 seconds
Started Jun 22 04:40:30 PM PDT 24
Finished Jun 22 04:40:36 PM PDT 24
Peak memory 213676 kb
Host smart-3b410bcb-07a4-4581-a468-af4138ef88ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40078646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.40078646
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2420713324
Short name T132
Test name
Test status
Simulation time 1724060739 ps
CPU time 16.83 seconds
Started Jun 22 04:40:14 PM PDT 24
Finished Jun 22 04:40:32 PM PDT 24
Peak memory 213640 kb
Host smart-78b30fd3-fb38-46c8-ad06-d0b39d96b549
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420713324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2420713324
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2684662009
Short name T39
Test name
Test status
Simulation time 100770512 ps
CPU time 0.85 seconds
Started Jun 22 04:48:49 PM PDT 24
Finished Jun 22 04:48:50 PM PDT 24
Peak memory 204760 kb
Host smart-1660b827-28e4-4063-864a-22504b59affa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684662009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2684662009
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1967679478
Short name T238
Test name
Test status
Simulation time 6512195921 ps
CPU time 10.53 seconds
Started Jun 22 04:48:40 PM PDT 24
Finished Jun 22 04:48:53 PM PDT 24
Peak memory 213288 kb
Host smart-758bfedc-6af1-4c16-a024-d7676e0249ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967679478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1967679478
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.4277335725
Short name T12
Test name
Test status
Simulation time 10445434116 ps
CPU time 8.62 seconds
Started Jun 22 04:48:40 PM PDT 24
Finished Jun 22 04:48:50 PM PDT 24
Peak memory 205136 kb
Host smart-3435e357-38f9-4303-8025-455642633ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277335725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.4277335725
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1713012598
Short name T10
Test name
Test status
Simulation time 7623611644 ps
CPU time 5.73 seconds
Started Jun 22 04:48:40 PM PDT 24
Finished Jun 22 04:48:48 PM PDT 24
Peak memory 204972 kb
Host smart-3caf181c-5063-417b-aaf6-abfd08c4fa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713012598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1713012598
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1264468515
Short name T140
Test name
Test status
Simulation time 13155684497 ps
CPU time 10.6 seconds
Started Jun 22 04:48:37 PM PDT 24
Finished Jun 22 04:48:48 PM PDT 24
Peak memory 204896 kb
Host smart-152caaf2-c372-4cf7-a33f-c47c62a08348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264468515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1264468515
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.112750592
Short name T223
Test name
Test status
Simulation time 365567578 ps
CPU time 1.62 seconds
Started Jun 22 04:48:40 PM PDT 24
Finished Jun 22 04:48:43 PM PDT 24
Peak memory 204728 kb
Host smart-863de57c-1772-499a-8960-dfcd478b0f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112750592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.112750592
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3739910990
Short name T219
Test name
Test status
Simulation time 2501081123 ps
CPU time 4.57 seconds
Started Jun 22 04:48:40 PM PDT 24
Finished Jun 22 04:48:46 PM PDT 24
Peak memory 205052 kb
Host smart-b07dbcf8-9887-45fb-bc7d-e697444194a5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3739910990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3739910990
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3445311465
Short name T29
Test name
Test status
Simulation time 2867441028 ps
CPU time 2.65 seconds
Started Jun 22 04:48:39 PM PDT 24
Finished Jun 22 04:48:43 PM PDT 24
Peak memory 204784 kb
Host smart-a4da00fb-aa9f-43bb-8523-e96df1f04d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445311465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3445311465
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.113973431
Short name T185
Test name
Test status
Simulation time 405221883 ps
CPU time 1.16 seconds
Started Jun 22 04:48:39 PM PDT 24
Finished Jun 22 04:48:42 PM PDT 24
Peak memory 204600 kb
Host smart-38f459d6-02f8-4d50-bde8-af4e3af4330f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113973431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.113973431
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.594458241
Short name T236
Test name
Test status
Simulation time 993151983 ps
CPU time 2.03 seconds
Started Jun 22 04:48:40 PM PDT 24
Finished Jun 22 04:48:44 PM PDT 24
Peak memory 204496 kb
Host smart-1ce1bb9f-9635-475c-b3a7-4baaa49cdcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594458241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.594458241
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4024117618
Short name T227
Test name
Test status
Simulation time 3002765196 ps
CPU time 8.32 seconds
Started Jun 22 04:48:40 PM PDT 24
Finished Jun 22 04:48:50 PM PDT 24
Peak memory 204616 kb
Host smart-d8412218-2874-49e0-965b-ef34ce5474c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024117618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4024117618
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1186745899
Short name T214
Test name
Test status
Simulation time 368624310 ps
CPU time 1.44 seconds
Started Jun 22 04:48:43 PM PDT 24
Finished Jun 22 04:48:44 PM PDT 24
Peak memory 204592 kb
Host smart-e89be50b-d1ea-4380-87d8-cbdf18d88a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186745899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1186745899
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1539204785
Short name T190
Test name
Test status
Simulation time 242802923 ps
CPU time 1.28 seconds
Started Jun 22 04:48:44 PM PDT 24
Finished Jun 22 04:48:46 PM PDT 24
Peak memory 204576 kb
Host smart-c417137b-c757-413c-a518-300eaedd3b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539204785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1539204785
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3531286339
Short name T142
Test name
Test status
Simulation time 916370628 ps
CPU time 1.89 seconds
Started Jun 22 04:48:45 PM PDT 24
Finished Jun 22 04:48:48 PM PDT 24
Peak memory 204700 kb
Host smart-fc2115ad-2553-4652-9a97-c0efad01c495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531286339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3531286339
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2129025307
Short name T55
Test name
Test status
Simulation time 1376816143 ps
CPU time 1.43 seconds
Started Jun 22 04:48:42 PM PDT 24
Finished Jun 22 04:48:44 PM PDT 24
Peak memory 204724 kb
Host smart-9b3a0a30-6285-4ff7-8efd-1fb7789958c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129025307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2129025307
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1650362322
Short name T257
Test name
Test status
Simulation time 3202463698 ps
CPU time 3.43 seconds
Started Jun 22 04:48:38 PM PDT 24
Finished Jun 22 04:48:43 PM PDT 24
Peak memory 204944 kb
Host smart-06c4d6df-0da1-4e5a-b67a-2d281e8129d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650362322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1650362322
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2019844552
Short name T200
Test name
Test status
Simulation time 1855551540 ps
CPU time 3.59 seconds
Started Jun 22 04:48:39 PM PDT 24
Finished Jun 22 04:48:44 PM PDT 24
Peak memory 205028 kb
Host smart-af39c267-0a9e-4ba0-8e7c-f284383ea9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019844552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2019844552
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3189008073
Short name T40
Test name
Test status
Simulation time 1072605548 ps
CPU time 1.77 seconds
Started Jun 22 04:48:57 PM PDT 24
Finished Jun 22 04:49:00 PM PDT 24
Peak memory 229612 kb
Host smart-dff3900a-dae2-4721-8af7-0bfe9e717977
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189008073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3189008073
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2212695296
Short name T179
Test name
Test status
Simulation time 1540503950 ps
CPU time 2.21 seconds
Started Jun 22 04:48:38 PM PDT 24
Finished Jun 22 04:48:42 PM PDT 24
Peak memory 204824 kb
Host smart-de4f5fd5-501f-43e7-a8f4-c34963186ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212695296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2212695296
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.4041523976
Short name T34
Test name
Test status
Simulation time 7463169686 ps
CPU time 12.04 seconds
Started Jun 22 04:48:45 PM PDT 24
Finished Jun 22 04:48:58 PM PDT 24
Peak memory 204916 kb
Host smart-25e18f0e-ced8-44a2-a1c6-bfe25b535abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041523976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.4041523976
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1619462713
Short name T38
Test name
Test status
Simulation time 116745099 ps
CPU time 0.97 seconds
Started Jun 22 04:48:56 PM PDT 24
Finished Jun 22 04:48:58 PM PDT 24
Peak memory 204720 kb
Host smart-10b45e80-4327-41d5-9d22-28868ec4491b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619462713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1619462713
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2467898391
Short name T166
Test name
Test status
Simulation time 37936223 ps
CPU time 0.76 seconds
Started Jun 22 04:48:57 PM PDT 24
Finished Jun 22 04:48:59 PM PDT 24
Peak memory 204744 kb
Host smart-85221900-f9e1-48db-b69b-b29a5f76baa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467898391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2467898391
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.798615374
Short name T1
Test name
Test status
Simulation time 4465973603 ps
CPU time 13.26 seconds
Started Jun 22 04:48:46 PM PDT 24
Finished Jun 22 04:49:00 PM PDT 24
Peak memory 205180 kb
Host smart-df666746-5aea-4470-b9f6-0bb5c2ce8824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798615374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.798615374
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1589159193
Short name T232
Test name
Test status
Simulation time 3575135715 ps
CPU time 5.81 seconds
Started Jun 22 04:48:49 PM PDT 24
Finished Jun 22 04:48:55 PM PDT 24
Peak memory 205120 kb
Host smart-2607a461-a083-4120-879a-1e6eb93bcc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589159193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1589159193
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3380517577
Short name T138
Test name
Test status
Simulation time 23589118601 ps
CPU time 36.8 seconds
Started Jun 22 04:48:48 PM PDT 24
Finished Jun 22 04:49:26 PM PDT 24
Peak memory 205004 kb
Host smart-891ed428-ae9f-4bdc-b2a9-85c998664c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380517577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3380517577
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.334201702
Short name T7
Test name
Test status
Simulation time 993810109 ps
CPU time 1.22 seconds
Started Jun 22 04:48:47 PM PDT 24
Finished Jun 22 04:48:49 PM PDT 24
Peak memory 204596 kb
Host smart-c12a0953-3fec-45b1-8c06-0b5cde22bcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334201702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.334201702
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.4144021240
Short name T24
Test name
Test status
Simulation time 1273293274 ps
CPU time 3.98 seconds
Started Jun 22 04:48:46 PM PDT 24
Finished Jun 22 04:48:50 PM PDT 24
Peak memory 204572 kb
Host smart-c5db29e6-6af4-4196-811f-2f90e98a4868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144021240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.4144021240
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.316123206
Short name T3
Test name
Test status
Simulation time 9039781886 ps
CPU time 3.64 seconds
Started Jun 22 04:48:47 PM PDT 24
Finished Jun 22 04:48:51 PM PDT 24
Peak memory 204920 kb
Host smart-d876c368-3ab7-4805-b2ee-fde0a90f78eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316123206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.316123206
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.4279153227
Short name T143
Test name
Test status
Simulation time 126797004 ps
CPU time 0.72 seconds
Started Jun 22 04:48:48 PM PDT 24
Finished Jun 22 04:48:49 PM PDT 24
Peak memory 204680 kb
Host smart-7cf816b7-9c54-421a-b15c-43ed9bfcf003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279153227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.4279153227
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.4183086943
Short name T213
Test name
Test status
Simulation time 5234576755 ps
CPU time 14.59 seconds
Started Jun 22 04:48:55 PM PDT 24
Finished Jun 22 04:49:11 PM PDT 24
Peak memory 205108 kb
Host smart-7cf2fab4-b06f-4702-b0fe-1497c11244f9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4183086943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.4183086943
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2452557974
Short name T6
Test name
Test status
Simulation time 2179397754 ps
CPU time 2.26 seconds
Started Jun 22 04:48:48 PM PDT 24
Finished Jun 22 04:48:51 PM PDT 24
Peak memory 204784 kb
Host smart-2bb73ae8-39d5-47a8-9666-68733c3d2e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452557974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2452557974
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3720806850
Short name T176
Test name
Test status
Simulation time 156290742 ps
CPU time 0.7 seconds
Started Jun 22 04:48:46 PM PDT 24
Finished Jun 22 04:48:47 PM PDT 24
Peak memory 204576 kb
Host smart-7a97bc5b-2c97-4036-b106-687f0fc3bcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720806850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3720806850
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3433298201
Short name T201
Test name
Test status
Simulation time 1127901139 ps
CPU time 2.51 seconds
Started Jun 22 04:48:48 PM PDT 24
Finished Jun 22 04:48:51 PM PDT 24
Peak memory 204796 kb
Host smart-bd4d8729-0403-45bb-a184-ad774318b7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433298201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3433298201
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2782615209
Short name T253
Test name
Test status
Simulation time 2731765172 ps
CPU time 7.97 seconds
Started Jun 22 04:48:56 PM PDT 24
Finished Jun 22 04:49:05 PM PDT 24
Peak memory 204652 kb
Host smart-2717b9d1-e01f-4efa-bc92-81ad2c1a7532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782615209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2782615209
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3264290839
Short name T195
Test name
Test status
Simulation time 587961801 ps
CPU time 1.97 seconds
Started Jun 22 04:48:48 PM PDT 24
Finished Jun 22 04:48:51 PM PDT 24
Peak memory 204808 kb
Host smart-96ca3277-9a11-4d4c-a731-e9eb8024e2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264290839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3264290839
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1983881273
Short name T46
Test name
Test status
Simulation time 280116897 ps
CPU time 0.91 seconds
Started Jun 22 04:48:47 PM PDT 24
Finished Jun 22 04:48:48 PM PDT 24
Peak memory 204504 kb
Host smart-ea93380d-c81a-42a5-814d-fc2bdbd0b975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983881273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1983881273
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1814675656
Short name T136
Test name
Test status
Simulation time 772232588 ps
CPU time 1.27 seconds
Started Jun 22 04:48:56 PM PDT 24
Finished Jun 22 04:48:58 PM PDT 24
Peak memory 204720 kb
Host smart-b581a9f4-0c84-43c3-87a9-67a8f20e1c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814675656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1814675656
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2759862401
Short name T218
Test name
Test status
Simulation time 120345473 ps
CPU time 1.02 seconds
Started Jun 22 04:48:46 PM PDT 24
Finished Jun 22 04:48:47 PM PDT 24
Peak memory 204648 kb
Host smart-a4b13283-4113-4445-b9b7-9fe2b9b2de9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759862401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2759862401
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2809986441
Short name T15
Test name
Test status
Simulation time 543866027 ps
CPU time 1.42 seconds
Started Jun 22 04:48:48 PM PDT 24
Finished Jun 22 04:48:50 PM PDT 24
Peak memory 204752 kb
Host smart-e8d42eca-4a7d-4a69-8443-1ee986b8c558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809986441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2809986441
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1303693458
Short name T13
Test name
Test status
Simulation time 2900596348 ps
CPU time 2.48 seconds
Started Jun 22 04:48:48 PM PDT 24
Finished Jun 22 04:48:51 PM PDT 24
Peak memory 204764 kb
Host smart-6738a496-ff5b-4e60-88af-7920313517b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303693458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1303693458
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.27365070
Short name T35
Test name
Test status
Simulation time 176919869 ps
CPU time 1.15 seconds
Started Jun 22 04:48:48 PM PDT 24
Finished Jun 22 04:48:50 PM PDT 24
Peak memory 204692 kb
Host smart-577eda40-8924-4f03-a66f-2863aca6dbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27365070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.27365070
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2419104666
Short name T27
Test name
Test status
Simulation time 136498741 ps
CPU time 0.86 seconds
Started Jun 22 04:49:50 PM PDT 24
Finished Jun 22 04:49:52 PM PDT 24
Peak memory 212972 kb
Host smart-d4cbd9ac-3e8f-4e27-a763-6ac7c8001b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419104666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2419104666
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.501136981
Short name T197
Test name
Test status
Simulation time 1830505312 ps
CPU time 2.52 seconds
Started Jun 22 04:48:57 PM PDT 24
Finished Jun 22 04:49:00 PM PDT 24
Peak memory 204612 kb
Host smart-89ee977c-b49f-41d2-b0c1-77ef423b29c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501136981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.501136981
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.104683436
Short name T41
Test name
Test status
Simulation time 1355712401 ps
CPU time 1.34 seconds
Started Jun 22 04:48:57 PM PDT 24
Finished Jun 22 04:48:59 PM PDT 24
Peak memory 228068 kb
Host smart-9fec2e8e-d7f2-47e4-91b8-8b9555283713
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104683436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.104683436
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.493320021
Short name T171
Test name
Test status
Simulation time 3643727262 ps
CPU time 8.12 seconds
Started Jun 22 04:48:46 PM PDT 24
Finished Jun 22 04:48:55 PM PDT 24
Peak memory 204820 kb
Host smart-3e03d1b7-4d91-463d-b450-ac52a26a84cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493320021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.493320021
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1043894417
Short name T164
Test name
Test status
Simulation time 79238971 ps
CPU time 0.73 seconds
Started Jun 22 04:49:02 PM PDT 24
Finished Jun 22 04:49:04 PM PDT 24
Peak memory 204736 kb
Host smart-a9b47541-ef6f-4088-916b-e01dfeaa33fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043894417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1043894417
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1727204143
Short name T217
Test name
Test status
Simulation time 18445590054 ps
CPU time 51.76 seconds
Started Jun 22 04:49:03 PM PDT 24
Finished Jun 22 04:49:56 PM PDT 24
Peak memory 213200 kb
Host smart-df4f96fa-eedf-4557-878e-eb5fa49069f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727204143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1727204143
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1290553809
Short name T184
Test name
Test status
Simulation time 5242539422 ps
CPU time 4.89 seconds
Started Jun 22 04:49:03 PM PDT 24
Finished Jun 22 04:49:09 PM PDT 24
Peak memory 205096 kb
Host smart-fc15e604-e15d-4131-88a1-25ccad6675d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290553809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1290553809
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3327069889
Short name T256
Test name
Test status
Simulation time 5075392632 ps
CPU time 8.26 seconds
Started Jun 22 04:49:02 PM PDT 24
Finished Jun 22 04:49:12 PM PDT 24
Peak memory 205116 kb
Host smart-03b9132c-cc15-46e7-9b50-06d936f93517
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3327069889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3327069889
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3091070222
Short name T203
Test name
Test status
Simulation time 2922489283 ps
CPU time 3.23 seconds
Started Jun 22 04:49:14 PM PDT 24
Finished Jun 22 04:49:18 PM PDT 24
Peak memory 204788 kb
Host smart-c77942ac-2684-4833-810e-2cf159143658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091070222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3091070222
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.1724032018
Short name T31
Test name
Test status
Simulation time 14574544321 ps
CPU time 39.74 seconds
Started Jun 22 04:49:04 PM PDT 24
Finished Jun 22 04:49:45 PM PDT 24
Peak memory 213180 kb
Host smart-57c63a13-241e-46b1-bdcc-9aa9cad9e55e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724032018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1724032018
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1179390124
Short name T151
Test name
Test status
Simulation time 87550436 ps
CPU time 0.7 seconds
Started Jun 22 04:49:04 PM PDT 24
Finished Jun 22 04:49:05 PM PDT 24
Peak memory 204768 kb
Host smart-f29d2389-080d-4de5-b5f9-5ad81aa267f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179390124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1179390124
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.4277747148
Short name T193
Test name
Test status
Simulation time 26861636861 ps
CPU time 78.4 seconds
Started Jun 22 04:49:00 PM PDT 24
Finished Jun 22 04:50:20 PM PDT 24
Peak memory 205096 kb
Host smart-7b1665ed-8e8d-4386-8bd7-66ca1f1719ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277747148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.4277747148
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.236974202
Short name T212
Test name
Test status
Simulation time 6333416628 ps
CPU time 11.45 seconds
Started Jun 22 04:49:00 PM PDT 24
Finished Jun 22 04:49:12 PM PDT 24
Peak memory 213312 kb
Host smart-3a1f5749-24fc-49f8-86e6-f071d9a9f917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236974202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.236974202
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1955821139
Short name T228
Test name
Test status
Simulation time 3002863440 ps
CPU time 4.07 seconds
Started Jun 22 04:49:13 PM PDT 24
Finished Jun 22 04:49:19 PM PDT 24
Peak memory 204724 kb
Host smart-f0203255-fa4b-4f03-8efa-0cbbbd791424
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1955821139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1955821139
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2601326798
Short name T70
Test name
Test status
Simulation time 2462276050 ps
CPU time 3.26 seconds
Started Jun 22 04:49:14 PM PDT 24
Finished Jun 22 04:49:18 PM PDT 24
Peak memory 204744 kb
Host smart-f34f111a-ab80-4a90-936f-382075b604af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601326798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2601326798
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1499784557
Short name T165
Test name
Test status
Simulation time 70909363 ps
CPU time 0.8 seconds
Started Jun 22 04:49:03 PM PDT 24
Finished Jun 22 04:49:05 PM PDT 24
Peak memory 204656 kb
Host smart-aa22cfe1-774c-4611-b9a1-88fb5a518650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499784557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1499784557
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2625640169
Short name T18
Test name
Test status
Simulation time 18892516357 ps
CPU time 15.46 seconds
Started Jun 22 04:49:01 PM PDT 24
Finished Jun 22 04:49:17 PM PDT 24
Peak memory 213268 kb
Host smart-4fd7bb3b-8e83-403e-8ac7-cfbd07411258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625640169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2625640169
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.322282772
Short name T196
Test name
Test status
Simulation time 3459865011 ps
CPU time 3.41 seconds
Started Jun 22 04:49:14 PM PDT 24
Finished Jun 22 04:49:19 PM PDT 24
Peak memory 204784 kb
Host smart-bab08db4-dc83-4964-be6a-443a3c493747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322282772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.322282772
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.342511413
Short name T174
Test name
Test status
Simulation time 14312854565 ps
CPU time 22.5 seconds
Started Jun 22 04:49:02 PM PDT 24
Finished Jun 22 04:49:25 PM PDT 24
Peak memory 213292 kb
Host smart-5623f4ea-1223-4821-b93d-d57dbc682a37
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=342511413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.342511413
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3191389816
Short name T233
Test name
Test status
Simulation time 838646188 ps
CPU time 2.86 seconds
Started Jun 22 04:49:03 PM PDT 24
Finished Jun 22 04:49:07 PM PDT 24
Peak memory 205040 kb
Host smart-19321f22-5d96-4bc6-b5e9-2083c8afc6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191389816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3191389816
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3621067909
Short name T122
Test name
Test status
Simulation time 113236025 ps
CPU time 0.73 seconds
Started Jun 22 04:49:14 PM PDT 24
Finished Jun 22 04:49:16 PM PDT 24
Peak memory 204388 kb
Host smart-890d9c14-47a2-4a46-a362-28435d5d8d2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621067909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3621067909
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.4020839529
Short name T59
Test name
Test status
Simulation time 2101488867 ps
CPU time 3.94 seconds
Started Jun 22 04:48:58 PM PDT 24
Finished Jun 22 04:49:03 PM PDT 24
Peak memory 205036 kb
Host smart-ded99198-fbe5-4039-86cf-642838109cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020839529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.4020839529
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.4259212277
Short name T242
Test name
Test status
Simulation time 8351162343 ps
CPU time 2.77 seconds
Started Jun 22 04:49:03 PM PDT 24
Finished Jun 22 04:49:07 PM PDT 24
Peak memory 205092 kb
Host smart-4025004d-7230-483a-8693-13a7fb39f5ed
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259212277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.4259212277
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.4276871487
Short name T172
Test name
Test status
Simulation time 727964851 ps
CPU time 1.17 seconds
Started Jun 22 04:49:08 PM PDT 24
Finished Jun 22 04:49:10 PM PDT 24
Peak memory 205044 kb
Host smart-d7d8d532-03b9-48f7-bd01-7bc7626004f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276871487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.4276871487
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.1504544662
Short name T26
Test name
Test status
Simulation time 12862815922 ps
CPU time 23.17 seconds
Started Jun 22 04:49:14 PM PDT 24
Finished Jun 22 04:49:38 PM PDT 24
Peak memory 204588 kb
Host smart-42adb075-dcf5-4ebf-8ace-1733a786126a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504544662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1504544662
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.348956722
Short name T162
Test name
Test status
Simulation time 47600621 ps
CPU time 0.75 seconds
Started Jun 22 04:49:01 PM PDT 24
Finished Jun 22 04:49:03 PM PDT 24
Peak memory 204688 kb
Host smart-3c49b4e6-4a52-4692-a5eb-00d5f750a1dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348956722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.348956722
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1522743053
Short name T245
Test name
Test status
Simulation time 3470114983 ps
CPU time 1.59 seconds
Started Jun 22 04:49:02 PM PDT 24
Finished Jun 22 04:49:05 PM PDT 24
Peak memory 205132 kb
Host smart-0e80eba3-37d3-467d-bcdf-334d445d0ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522743053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1522743053
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2984535130
Short name T182
Test name
Test status
Simulation time 9895934269 ps
CPU time 29.73 seconds
Started Jun 22 04:49:00 PM PDT 24
Finished Jun 22 04:49:31 PM PDT 24
Peak memory 213304 kb
Host smart-a8219210-7c06-4792-92ae-98005cf01515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984535130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2984535130
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1340141686
Short name T188
Test name
Test status
Simulation time 2336510609 ps
CPU time 4.14 seconds
Started Jun 22 04:49:01 PM PDT 24
Finished Jun 22 04:49:07 PM PDT 24
Peak memory 205096 kb
Host smart-77664f11-4cdc-4ebc-aca4-7e33321aa57a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1340141686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1340141686
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2838758892
Short name T61
Test name
Test status
Simulation time 3171437517 ps
CPU time 10.2 seconds
Started Jun 22 04:49:01 PM PDT 24
Finished Jun 22 04:49:12 PM PDT 24
Peak memory 205096 kb
Host smart-7d32235f-44f7-4f74-89c3-8e0b0e7492dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838758892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2838758892
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1471968221
Short name T259
Test name
Test status
Simulation time 50931777 ps
CPU time 0.76 seconds
Started Jun 22 04:49:08 PM PDT 24
Finished Jun 22 04:49:10 PM PDT 24
Peak memory 204772 kb
Host smart-36abe1a0-73c9-4aaa-8e66-fe74fdf19691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471968221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1471968221
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3702701074
Short name T2
Test name
Test status
Simulation time 4112269844 ps
CPU time 6.22 seconds
Started Jun 22 04:49:01 PM PDT 24
Finished Jun 22 04:49:09 PM PDT 24
Peak memory 205100 kb
Host smart-2cacbfce-d766-4e1b-8116-574e59f4a4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702701074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3702701074
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3173425004
Short name T199
Test name
Test status
Simulation time 2461591838 ps
CPU time 2.03 seconds
Started Jun 22 04:49:01 PM PDT 24
Finished Jun 22 04:49:04 PM PDT 24
Peak memory 205140 kb
Host smart-09772757-3f2e-4bf5-a8bc-b594b12e97b0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3173425004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3173425004
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.3658664224
Short name T60
Test name
Test status
Simulation time 6765680360 ps
CPU time 4.57 seconds
Started Jun 22 04:49:03 PM PDT 24
Finished Jun 22 04:49:08 PM PDT 24
Peak memory 205064 kb
Host smart-378f5d9a-447c-4138-918c-7afbcdb67984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658664224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3658664224
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.502039813
Short name T139
Test name
Test status
Simulation time 14911963616 ps
CPU time 19.88 seconds
Started Jun 22 04:49:13 PM PDT 24
Finished Jun 22 04:49:34 PM PDT 24
Peak memory 204492 kb
Host smart-40950c46-ec05-4c84-aec0-eb4e115d53e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502039813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.502039813
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1726036238
Short name T155
Test name
Test status
Simulation time 77110681 ps
CPU time 0.77 seconds
Started Jun 22 04:49:08 PM PDT 24
Finished Jun 22 04:49:11 PM PDT 24
Peak memory 204700 kb
Host smart-647aeffa-d592-4fe9-a66b-993e2a580786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726036238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1726036238
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1623430808
Short name T177
Test name
Test status
Simulation time 3347299888 ps
CPU time 6.06 seconds
Started Jun 22 04:49:07 PM PDT 24
Finished Jun 22 04:49:14 PM PDT 24
Peak memory 205184 kb
Host smart-492ab4b3-209c-434d-ae31-2c2c0ebfff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623430808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1623430808
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3200487885
Short name T207
Test name
Test status
Simulation time 10604627020 ps
CPU time 5.51 seconds
Started Jun 22 04:49:10 PM PDT 24
Finished Jun 22 04:49:18 PM PDT 24
Peak memory 213324 kb
Host smart-2ffb80c4-f4b2-4116-9196-15897cec0bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200487885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3200487885
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.4063803400
Short name T258
Test name
Test status
Simulation time 2469829085 ps
CPU time 1.66 seconds
Started Jun 22 04:49:10 PM PDT 24
Finished Jun 22 04:49:14 PM PDT 24
Peak memory 205100 kb
Host smart-3c8a2e81-0660-4e65-8e3c-319a52a4dd7f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063803400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.4063803400
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.3081260949
Short name T191
Test name
Test status
Simulation time 12775409328 ps
CPU time 13.95 seconds
Started Jun 22 04:49:11 PM PDT 24
Finished Jun 22 04:49:27 PM PDT 24
Peak memory 205064 kb
Host smart-e7708ae8-5626-4ed6-b08e-8cc8dac08fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081260949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3081260949
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.905787924
Short name T141
Test name
Test status
Simulation time 3155380736 ps
CPU time 4.32 seconds
Started Jun 22 04:49:10 PM PDT 24
Finished Jun 22 04:49:17 PM PDT 24
Peak memory 204864 kb
Host smart-5c1d8e81-ce41-4f24-a454-ccc103ec5170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905787924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.905787924
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3802397899
Short name T247
Test name
Test status
Simulation time 7853544806 ps
CPU time 13.18 seconds
Started Jun 22 04:49:09 PM PDT 24
Finished Jun 22 04:49:24 PM PDT 24
Peak memory 213352 kb
Host smart-052b57a8-6dda-44f5-b3cf-a9609181556e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802397899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3802397899
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.4090369411
Short name T220
Test name
Test status
Simulation time 5760042839 ps
CPU time 5.17 seconds
Started Jun 22 04:49:10 PM PDT 24
Finished Jun 22 04:49:17 PM PDT 24
Peak memory 213560 kb
Host smart-1b61914a-cb68-4207-92f7-1a5f3d811e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090369411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.4090369411
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2995092886
Short name T173
Test name
Test status
Simulation time 3706708469 ps
CPU time 7 seconds
Started Jun 22 04:49:07 PM PDT 24
Finished Jun 22 04:49:15 PM PDT 24
Peak memory 205128 kb
Host smart-eef1c71b-3cbc-4883-8458-a7563b58274e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995092886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.2995092886
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3450773723
Short name T211
Test name
Test status
Simulation time 5928978832 ps
CPU time 7.35 seconds
Started Jun 22 04:49:14 PM PDT 24
Finished Jun 22 04:49:23 PM PDT 24
Peak memory 204740 kb
Host smart-11222400-9567-4345-9349-3f474dd98941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450773723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3450773723
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3482307183
Short name T244
Test name
Test status
Simulation time 38065852 ps
CPU time 0.78 seconds
Started Jun 22 04:49:12 PM PDT 24
Finished Jun 22 04:49:15 PM PDT 24
Peak memory 204772 kb
Host smart-e111171b-5866-4b71-8ecf-3926a1ada0c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482307183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3482307183
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3875297427
Short name T222
Test name
Test status
Simulation time 153326695586 ps
CPU time 339.91 seconds
Started Jun 22 04:49:08 PM PDT 24
Finished Jun 22 04:54:50 PM PDT 24
Peak memory 217800 kb
Host smart-02073c5e-d8a3-410c-b3c0-549c1b97d176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875297427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3875297427
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1536590639
Short name T189
Test name
Test status
Simulation time 1358338208 ps
CPU time 3.22 seconds
Started Jun 22 04:49:07 PM PDT 24
Finished Jun 22 04:49:11 PM PDT 24
Peak memory 205008 kb
Host smart-28c7a9d7-857c-4806-8ad2-b7e6c2e591c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536590639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1536590639
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3750926862
Short name T215
Test name
Test status
Simulation time 12062735872 ps
CPU time 35.34 seconds
Started Jun 22 04:49:11 PM PDT 24
Finished Jun 22 04:49:48 PM PDT 24
Peak memory 205096 kb
Host smart-ee12a2f2-8a95-44a1-8e0e-84164ed60948
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3750926862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.3750926862
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.749908222
Short name T237
Test name
Test status
Simulation time 1741877347 ps
CPU time 5.71 seconds
Started Jun 22 04:49:07 PM PDT 24
Finished Jun 22 04:49:14 PM PDT 24
Peak memory 205040 kb
Host smart-09c6fb91-0aad-4a1d-9e70-c9bbdab64616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749908222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.749908222
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1544525010
Short name T22
Test name
Test status
Simulation time 150161228 ps
CPU time 0.78 seconds
Started Jun 22 04:49:09 PM PDT 24
Finished Jun 22 04:49:11 PM PDT 24
Peak memory 204772 kb
Host smart-b2d4fd49-3ec7-4504-baa2-91e474d736b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544525010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1544525010
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3777920252
Short name T221
Test name
Test status
Simulation time 5418047057 ps
CPU time 5.8 seconds
Started Jun 22 04:49:09 PM PDT 24
Finished Jun 22 04:49:17 PM PDT 24
Peak memory 205124 kb
Host smart-53bcfba3-c4aa-4823-82ae-d777b77d3835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777920252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3777920252
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3147276864
Short name T255
Test name
Test status
Simulation time 5616989083 ps
CPU time 15.79 seconds
Started Jun 22 04:49:10 PM PDT 24
Finished Jun 22 04:49:28 PM PDT 24
Peak memory 205048 kb
Host smart-75a632e6-324a-4d0c-b6ec-d908b69ffe43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147276864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3147276864
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.4245409386
Short name T231
Test name
Test status
Simulation time 3404755985 ps
CPU time 3.63 seconds
Started Jun 22 04:49:12 PM PDT 24
Finished Jun 22 04:49:17 PM PDT 24
Peak memory 205148 kb
Host smart-ba282613-bf90-4412-941d-4ddc26b3188e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4245409386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.4245409386
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2271579050
Short name T246
Test name
Test status
Simulation time 13257580122 ps
CPU time 32.02 seconds
Started Jun 22 04:49:12 PM PDT 24
Finished Jun 22 04:49:45 PM PDT 24
Peak memory 205156 kb
Host smart-2f016d39-ebcf-4302-99dd-8fb5c2c6e01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271579050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2271579050
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2928988633
Short name T147
Test name
Test status
Simulation time 41229052 ps
CPU time 0.76 seconds
Started Jun 22 04:49:45 PM PDT 24
Finished Jun 22 04:49:48 PM PDT 24
Peak memory 204744 kb
Host smart-aa2a3f4d-0009-43af-9b50-ccb0705c3226
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928988633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2928988633
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1860951745
Short name T208
Test name
Test status
Simulation time 4923280308 ps
CPU time 4.42 seconds
Started Jun 22 04:48:57 PM PDT 24
Finished Jun 22 04:49:03 PM PDT 24
Peak memory 205092 kb
Host smart-dd5e0d8b-8780-4b53-aa41-1aafea7ce4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860951745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1860951745
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3531792437
Short name T186
Test name
Test status
Simulation time 4043868321 ps
CPU time 7.01 seconds
Started Jun 22 04:48:48 PM PDT 24
Finished Jun 22 04:48:56 PM PDT 24
Peak memory 205116 kb
Host smart-2904d212-6856-4ee5-944e-1c3b23ac6159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531792437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3531792437
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3341919770
Short name T235
Test name
Test status
Simulation time 3634097491 ps
CPU time 5.97 seconds
Started Jun 22 04:48:56 PM PDT 24
Finished Jun 22 04:49:02 PM PDT 24
Peak memory 205156 kb
Host smart-7f9c7262-8fa7-452e-bb0f-9f7b56adab1c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3341919770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3341919770
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1329336604
Short name T9
Test name
Test status
Simulation time 163135018 ps
CPU time 0.85 seconds
Started Jun 22 04:48:59 PM PDT 24
Finished Jun 22 04:49:00 PM PDT 24
Peak memory 204508 kb
Host smart-62832893-caca-47f3-b272-b7649e0e126c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329336604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1329336604
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.730182030
Short name T198
Test name
Test status
Simulation time 1411223985 ps
CPU time 1.84 seconds
Started Jun 22 04:48:48 PM PDT 24
Finished Jun 22 04:48:51 PM PDT 24
Peak memory 205080 kb
Host smart-23c3cf3d-4a44-4dbf-ac17-3e18c378ccfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730182030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.730182030
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.966228754
Short name T57
Test name
Test status
Simulation time 432165558 ps
CPU time 2.07 seconds
Started Jun 22 04:48:59 PM PDT 24
Finished Jun 22 04:49:02 PM PDT 24
Peak memory 228916 kb
Host smart-8d74a075-9ac7-492f-96ab-651d985fb019
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966228754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.966228754
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.4005098132
Short name T19
Test name
Test status
Simulation time 26399511909 ps
CPU time 37.59 seconds
Started Jun 22 04:48:56 PM PDT 24
Finished Jun 22 04:49:35 PM PDT 24
Peak memory 213160 kb
Host smart-70c6c738-faee-4473-afc5-ff7438224216
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005098132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.4005098132
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2289185608
Short name T149
Test name
Test status
Simulation time 137749133 ps
CPU time 0.86 seconds
Started Jun 22 04:49:12 PM PDT 24
Finished Jun 22 04:49:14 PM PDT 24
Peak memory 204704 kb
Host smart-01d81c54-559d-43cd-8258-1fc1804bd29e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289185608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2289185608
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2643007455
Short name T152
Test name
Test status
Simulation time 74426088 ps
CPU time 0.73 seconds
Started Jun 22 04:49:11 PM PDT 24
Finished Jun 22 04:49:13 PM PDT 24
Peak memory 204776 kb
Host smart-a78020b8-121a-48b9-a893-685b90f13e31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643007455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2643007455
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.4108475433
Short name T47
Test name
Test status
Simulation time 104384764 ps
CPU time 0.73 seconds
Started Jun 22 04:49:11 PM PDT 24
Finished Jun 22 04:49:13 PM PDT 24
Peak memory 204776 kb
Host smart-bda33ca1-0c8e-412f-bac4-fa3318922824
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108475433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.4108475433
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.2736916232
Short name T137
Test name
Test status
Simulation time 13472059078 ps
CPU time 18.76 seconds
Started Jun 22 04:49:09 PM PDT 24
Finished Jun 22 04:49:30 PM PDT 24
Peak memory 204920 kb
Host smart-11e68795-af22-432a-bc22-d00a529571f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736916232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2736916232
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2423917375
Short name T248
Test name
Test status
Simulation time 42849875 ps
CPU time 0.82 seconds
Started Jun 22 04:49:08 PM PDT 24
Finished Jun 22 04:49:10 PM PDT 24
Peak memory 204904 kb
Host smart-755c9cd6-caf8-4b78-b271-07e0b8a42182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423917375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2423917375
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.3656274061
Short name T251
Test name
Test status
Simulation time 14368559879 ps
CPU time 20.57 seconds
Started Jun 22 04:49:12 PM PDT 24
Finished Jun 22 04:49:34 PM PDT 24
Peak memory 204944 kb
Host smart-5c638735-5ae6-4287-a7e3-8b4f06ade699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656274061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3656274061
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.716763379
Short name T69
Test name
Test status
Simulation time 31133952 ps
CPU time 0.79 seconds
Started Jun 22 04:49:11 PM PDT 24
Finished Jun 22 04:49:14 PM PDT 24
Peak memory 204764 kb
Host smart-d5152bba-1a33-47ae-95f6-9d5d1eeec1ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716763379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.716763379
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3938056954
Short name T124
Test name
Test status
Simulation time 152504585 ps
CPU time 0.85 seconds
Started Jun 22 04:49:08 PM PDT 24
Finished Jun 22 04:49:11 PM PDT 24
Peak memory 204772 kb
Host smart-bdb9ed17-3609-444d-af3c-c5902dd26810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938056954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3938056954
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2958222346
Short name T202
Test name
Test status
Simulation time 41876029 ps
CPU time 0.82 seconds
Started Jun 22 04:49:11 PM PDT 24
Finished Jun 22 04:49:14 PM PDT 24
Peak memory 204700 kb
Host smart-bb598ccd-0d26-45b0-8557-8206f8b86556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958222346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2958222346
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2715488396
Short name T154
Test name
Test status
Simulation time 46531922 ps
CPU time 0.75 seconds
Started Jun 22 04:49:08 PM PDT 24
Finished Jun 22 04:49:10 PM PDT 24
Peak memory 204772 kb
Host smart-26a03bc4-31cf-42fa-9bd6-5cac6d48b8a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715488396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2715488396
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.670327887
Short name T81
Test name
Test status
Simulation time 40571826 ps
CPU time 0.77 seconds
Started Jun 22 04:49:08 PM PDT 24
Finished Jun 22 04:49:10 PM PDT 24
Peak memory 204684 kb
Host smart-32c83087-e15a-4791-bb9c-16f88b6cdaf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670327887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.670327887
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2135980326
Short name T169
Test name
Test status
Simulation time 38986080 ps
CPU time 0.71 seconds
Started Jun 22 04:49:09 PM PDT 24
Finished Jun 22 04:49:11 PM PDT 24
Peak memory 204776 kb
Host smart-9ffcf1c5-1f28-4d41-bb22-72450507a98c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135980326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2135980326
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.301195895
Short name T68
Test name
Test status
Simulation time 68757993 ps
CPU time 0.73 seconds
Started Jun 22 04:48:58 PM PDT 24
Finished Jun 22 04:49:00 PM PDT 24
Peak memory 204760 kb
Host smart-1eee6697-85db-45b9-9b37-ee51f97eaee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301195895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.301195895
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1111749280
Short name T206
Test name
Test status
Simulation time 37681135855 ps
CPU time 54.64 seconds
Started Jun 22 04:48:55 PM PDT 24
Finished Jun 22 04:49:50 PM PDT 24
Peak memory 213312 kb
Host smart-c3447d5e-beb8-47b1-8068-1bf45a81beb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111749280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1111749280
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2999361744
Short name T170
Test name
Test status
Simulation time 9241983854 ps
CPU time 20.19 seconds
Started Jun 22 04:48:57 PM PDT 24
Finished Jun 22 04:49:18 PM PDT 24
Peak memory 205140 kb
Host smart-ab42e199-81ae-4895-863f-a48755c079f8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999361744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2999361744
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2154828248
Short name T209
Test name
Test status
Simulation time 616977038 ps
CPU time 1.2 seconds
Started Jun 22 04:48:56 PM PDT 24
Finished Jun 22 04:48:58 PM PDT 24
Peak memory 204576 kb
Host smart-f8673e8f-0a4f-4520-9614-2c9e91f6dbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154828248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2154828248
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3632693834
Short name T48
Test name
Test status
Simulation time 1396207372 ps
CPU time 2.72 seconds
Started Jun 22 04:48:53 PM PDT 24
Finished Jun 22 04:48:56 PM PDT 24
Peak memory 205136 kb
Host smart-e6b4f6e0-a9e8-4a3c-af4c-a6ac62da500d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632693834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3632693834
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.565313814
Short name T150
Test name
Test status
Simulation time 101022458 ps
CPU time 0.75 seconds
Started Jun 22 04:49:17 PM PDT 24
Finished Jun 22 04:49:19 PM PDT 24
Peak memory 204776 kb
Host smart-29504722-2ea6-42c6-8735-5ad3f3518e8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565313814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.565313814
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1743305279
Short name T156
Test name
Test status
Simulation time 116835962 ps
CPU time 0.79 seconds
Started Jun 22 04:49:15 PM PDT 24
Finished Jun 22 04:49:17 PM PDT 24
Peak memory 204768 kb
Host smart-570879ef-0306-41f0-9253-fa3b4cd80542
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743305279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1743305279
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1356575401
Short name T158
Test name
Test status
Simulation time 79042252 ps
CPU time 0.85 seconds
Started Jun 22 04:49:17 PM PDT 24
Finished Jun 22 04:49:20 PM PDT 24
Peak memory 204640 kb
Host smart-2398b248-e116-4b86-a27a-7979b93b0a72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356575401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1356575401
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.981452808
Short name T21
Test name
Test status
Simulation time 96602477 ps
CPU time 0.83 seconds
Started Jun 22 04:49:17 PM PDT 24
Finished Jun 22 04:49:19 PM PDT 24
Peak memory 204764 kb
Host smart-7b54d293-05bc-4cc1-9108-54127c7254d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981452808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.981452808
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3444510275
Short name T146
Test name
Test status
Simulation time 85307753 ps
CPU time 0.7 seconds
Started Jun 22 04:49:21 PM PDT 24
Finished Jun 22 04:49:22 PM PDT 24
Peak memory 204804 kb
Host smart-411a19f5-800c-4f0c-85d2-0d0bf0d0fc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444510275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3444510275
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1518949483
Short name T119
Test name
Test status
Simulation time 55299273 ps
CPU time 0.71 seconds
Started Jun 22 04:49:16 PM PDT 24
Finished Jun 22 04:49:18 PM PDT 24
Peak memory 204752 kb
Host smart-5c3816fe-4dc6-4d97-b62e-a9d289d76c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518949483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1518949483
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3157822592
Short name T210
Test name
Test status
Simulation time 98883396 ps
CPU time 0.79 seconds
Started Jun 22 04:49:15 PM PDT 24
Finished Jun 22 04:49:16 PM PDT 24
Peak memory 204752 kb
Host smart-61eaf087-e698-4dc9-b4bb-fed02ea63933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157822592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3157822592
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2307415346
Short name T167
Test name
Test status
Simulation time 126020395 ps
CPU time 0.74 seconds
Started Jun 22 04:49:16 PM PDT 24
Finished Jun 22 04:49:18 PM PDT 24
Peak memory 204768 kb
Host smart-a574da15-77b8-4aa4-b3b2-81af2b330ac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307415346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2307415346
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1887922992
Short name T145
Test name
Test status
Simulation time 57251168 ps
CPU time 0.7 seconds
Started Jun 22 04:49:20 PM PDT 24
Finished Jun 22 04:49:21 PM PDT 24
Peak memory 204804 kb
Host smart-ccd0b9da-e5c1-4ff8-8e55-6d678fc66932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887922992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1887922992
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.605050708
Short name T54
Test name
Test status
Simulation time 103497649 ps
CPU time 0.76 seconds
Started Jun 22 04:49:17 PM PDT 24
Finished Jun 22 04:49:19 PM PDT 24
Peak memory 204720 kb
Host smart-f2da8e36-6a53-416c-95db-e62257692f4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605050708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.605050708
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1154596111
Short name T153
Test name
Test status
Simulation time 53579563 ps
CPU time 0.8 seconds
Started Jun 22 04:48:58 PM PDT 24
Finished Jun 22 04:49:00 PM PDT 24
Peak memory 204492 kb
Host smart-e3d1e8d0-5a8d-47ac-82f5-a59ac2a90e23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154596111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1154596111
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2596366304
Short name T224
Test name
Test status
Simulation time 115395420937 ps
CPU time 91.87 seconds
Started Jun 22 04:48:58 PM PDT 24
Finished Jun 22 04:50:31 PM PDT 24
Peak memory 213248 kb
Host smart-e9015419-3c69-4712-8a96-1285fa97ff71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596366304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2596366304
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1610307168
Short name T181
Test name
Test status
Simulation time 3023037282 ps
CPU time 4.69 seconds
Started Jun 22 04:48:58 PM PDT 24
Finished Jun 22 04:49:04 PM PDT 24
Peak memory 205152 kb
Host smart-f923f5a1-5e58-437b-9b5c-97b686def8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610307168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1610307168
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2897667763
Short name T49
Test name
Test status
Simulation time 1861370203 ps
CPU time 3.55 seconds
Started Jun 22 04:48:56 PM PDT 24
Finished Jun 22 04:49:01 PM PDT 24
Peak memory 205080 kb
Host smart-49658136-672d-4665-98fd-a40e75b127c8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897667763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2897667763
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3249109018
Short name T234
Test name
Test status
Simulation time 131820526 ps
CPU time 0.86 seconds
Started Jun 22 04:48:52 PM PDT 24
Finished Jun 22 04:48:54 PM PDT 24
Peak memory 204572 kb
Host smart-0ac3f40e-d82d-482b-8c2f-b9740fbd34dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249109018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3249109018
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2406623153
Short name T241
Test name
Test status
Simulation time 2730704319 ps
CPU time 8.51 seconds
Started Jun 22 04:49:00 PM PDT 24
Finished Jun 22 04:49:10 PM PDT 24
Peak memory 205120 kb
Host smart-90b735de-f6bd-4dde-9633-2d1fda10cb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406623153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2406623153
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3338448494
Short name T56
Test name
Test status
Simulation time 361839959 ps
CPU time 1.17 seconds
Started Jun 22 04:48:57 PM PDT 24
Finished Jun 22 04:48:59 PM PDT 24
Peak memory 229528 kb
Host smart-a3d3a8d3-0300-43cf-b733-b6b6fcd9a282
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338448494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3338448494
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.541750217
Short name T161
Test name
Test status
Simulation time 188059533 ps
CPU time 0.81 seconds
Started Jun 22 04:49:20 PM PDT 24
Finished Jun 22 04:49:22 PM PDT 24
Peak memory 204796 kb
Host smart-36bf901a-57ef-4c48-981e-1631ceeb7731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541750217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.541750217
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.831140132
Short name T144
Test name
Test status
Simulation time 126624252 ps
CPU time 0.83 seconds
Started Jun 22 04:49:15 PM PDT 24
Finished Jun 22 04:49:17 PM PDT 24
Peak memory 204760 kb
Host smart-f99b2871-c56c-4328-8eef-3caa981e89f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831140132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.831140132
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.4098880132
Short name T168
Test name
Test status
Simulation time 75719107 ps
CPU time 0.77 seconds
Started Jun 22 04:49:19 PM PDT 24
Finished Jun 22 04:49:20 PM PDT 24
Peak memory 204776 kb
Host smart-77c250b8-1390-477d-8cf1-2b34a8b1b133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098880132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.4098880132
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1922608905
Short name T121
Test name
Test status
Simulation time 155088990 ps
CPU time 0.92 seconds
Started Jun 22 04:49:17 PM PDT 24
Finished Jun 22 04:49:19 PM PDT 24
Peak memory 204772 kb
Host smart-04ce044d-36af-4f22-ad49-d34e8072abc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922608905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1922608905
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2310638873
Short name T157
Test name
Test status
Simulation time 70781733 ps
CPU time 0.78 seconds
Started Jun 22 04:49:18 PM PDT 24
Finished Jun 22 04:49:20 PM PDT 24
Peak memory 204752 kb
Host smart-25512b89-e2f5-454f-8419-3b470b51a926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310638873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2310638873
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.823847015
Short name T163
Test name
Test status
Simulation time 49046690 ps
CPU time 0.81 seconds
Started Jun 22 04:49:16 PM PDT 24
Finished Jun 22 04:49:17 PM PDT 24
Peak memory 204720 kb
Host smart-ffebdfa9-5c16-4f53-89b0-e055e0561c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823847015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.823847015
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2487585143
Short name T205
Test name
Test status
Simulation time 37666800 ps
CPU time 0.78 seconds
Started Jun 22 04:49:15 PM PDT 24
Finished Jun 22 04:49:17 PM PDT 24
Peak memory 204704 kb
Host smart-b5d9e8c2-9e94-4c2e-8ccb-db626e657e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487585143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2487585143
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.2768020597
Short name T16
Test name
Test status
Simulation time 9894275220 ps
CPU time 15.29 seconds
Started Jun 22 04:49:22 PM PDT 24
Finished Jun 22 04:49:38 PM PDT 24
Peak memory 204940 kb
Host smart-92544b47-0b97-4fb6-9374-75d72d9537c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768020597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2768020597
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3875411197
Short name T66
Test name
Test status
Simulation time 60306050 ps
CPU time 0.74 seconds
Started Jun 22 04:49:22 PM PDT 24
Finished Jun 22 04:49:23 PM PDT 24
Peak memory 204768 kb
Host smart-df8b0e70-a46f-41f0-a1c8-c74f693e6a46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875411197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3875411197
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.289954912
Short name T243
Test name
Test status
Simulation time 149401123 ps
CPU time 0.7 seconds
Started Jun 22 04:49:21 PM PDT 24
Finished Jun 22 04:49:22 PM PDT 24
Peak memory 204764 kb
Host smart-e637dda3-5c94-4beb-96ab-d2a40f351327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289954912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.289954912
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3034624808
Short name T160
Test name
Test status
Simulation time 224622425 ps
CPU time 0.75 seconds
Started Jun 22 04:48:53 PM PDT 24
Finished Jun 22 04:48:54 PM PDT 24
Peak memory 204688 kb
Host smart-8f82e401-f99a-4874-98ab-e6bc5f018348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034624808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3034624808
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3958694091
Short name T123
Test name
Test status
Simulation time 57137802072 ps
CPU time 72.81 seconds
Started Jun 22 04:48:52 PM PDT 24
Finished Jun 22 04:50:05 PM PDT 24
Peak memory 213244 kb
Host smart-0efed444-d5b8-48f7-a01e-b00acbe124fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958694091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3958694091
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2913693001
Short name T187
Test name
Test status
Simulation time 13764889692 ps
CPU time 21.67 seconds
Started Jun 22 04:48:58 PM PDT 24
Finished Jun 22 04:49:21 PM PDT 24
Peak memory 215380 kb
Host smart-a53c01b0-a948-4dc7-9c84-0d2dbf5253b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913693001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2913693001
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.4006054469
Short name T229
Test name
Test status
Simulation time 1777352565 ps
CPU time 5.58 seconds
Started Jun 22 04:48:57 PM PDT 24
Finished Jun 22 04:49:03 PM PDT 24
Peak memory 204960 kb
Host smart-a1913ee3-26e6-40a8-b78b-c3164970b210
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006054469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.4006054469
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1844610720
Short name T216
Test name
Test status
Simulation time 2108128696 ps
CPU time 6.35 seconds
Started Jun 22 04:48:58 PM PDT 24
Finished Jun 22 04:49:05 PM PDT 24
Peak memory 204788 kb
Host smart-28d8fd52-88b5-45a4-ad96-fe79c6fa8b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844610720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1844610720
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.2855187761
Short name T14
Test name
Test status
Simulation time 3118060955 ps
CPU time 9.33 seconds
Started Jun 22 04:48:55 PM PDT 24
Finished Jun 22 04:49:04 PM PDT 24
Peak memory 204936 kb
Host smart-f4bb1b25-4de7-4e2a-b875-7d1cbe23b927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855187761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2855187761
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3850841804
Short name T159
Test name
Test status
Simulation time 62570913 ps
CPU time 0.83 seconds
Started Jun 22 04:48:59 PM PDT 24
Finished Jun 22 04:49:00 PM PDT 24
Peak memory 204688 kb
Host smart-06089a9a-624e-452d-86aa-61324a49beb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850841804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3850841804
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1208786344
Short name T204
Test name
Test status
Simulation time 24509891877 ps
CPU time 23.42 seconds
Started Jun 22 04:48:51 PM PDT 24
Finished Jun 22 04:49:15 PM PDT 24
Peak memory 213568 kb
Host smart-a45bb972-b9ea-496f-956b-3d5897a713b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208786344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1208786344
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2143644670
Short name T226
Test name
Test status
Simulation time 2148978881 ps
CPU time 2.51 seconds
Started Jun 22 04:49:00 PM PDT 24
Finished Jun 22 04:49:03 PM PDT 24
Peak memory 205080 kb
Host smart-5617a79b-614e-4907-8116-2fa3a17ad5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143644670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2143644670
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2945992344
Short name T58
Test name
Test status
Simulation time 3509553932 ps
CPU time 10.57 seconds
Started Jun 22 04:48:56 PM PDT 24
Finished Jun 22 04:49:07 PM PDT 24
Peak memory 205092 kb
Host smart-6fce80d8-73ea-4882-8a74-410cbb5804e2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2945992344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2945992344
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3219768153
Short name T183
Test name
Test status
Simulation time 2003385085 ps
CPU time 1.85 seconds
Started Jun 22 04:48:58 PM PDT 24
Finished Jun 22 04:49:01 PM PDT 24
Peak memory 205032 kb
Host smart-296e3b94-b214-416f-bf5e-6adf8a8125ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219768153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3219768153
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3027362997
Short name T118
Test name
Test status
Simulation time 167237009 ps
CPU time 1.1 seconds
Started Jun 22 04:49:03 PM PDT 24
Finished Jun 22 04:49:05 PM PDT 24
Peak memory 204652 kb
Host smart-b61e2058-9deb-4d4f-a2ac-5e911709be05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027362997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3027362997
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.878589217
Short name T192
Test name
Test status
Simulation time 30811513067 ps
CPU time 52.49 seconds
Started Jun 22 04:48:56 PM PDT 24
Finished Jun 22 04:49:49 PM PDT 24
Peak memory 213304 kb
Host smart-3e7cd87e-8056-4b77-adaf-c3f9d8fbad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878589217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.878589217
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3677507927
Short name T249
Test name
Test status
Simulation time 7008197803 ps
CPU time 18.19 seconds
Started Jun 22 04:49:01 PM PDT 24
Finished Jun 22 04:49:20 PM PDT 24
Peak memory 205032 kb
Host smart-55d1d7fa-4186-488a-b22b-df15e6ab8700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677507927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3677507927
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3719940064
Short name T180
Test name
Test status
Simulation time 664655555 ps
CPU time 1.92 seconds
Started Jun 22 04:48:56 PM PDT 24
Finished Jun 22 04:48:59 PM PDT 24
Peak memory 204924 kb
Host smart-9342e828-d746-4271-95b4-88050dcbebaa
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3719940064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3719940064
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2003882966
Short name T230
Test name
Test status
Simulation time 2016481172 ps
CPU time 6.19 seconds
Started Jun 22 04:48:56 PM PDT 24
Finished Jun 22 04:49:03 PM PDT 24
Peak memory 204952 kb
Host smart-4f4a4624-c823-45b1-a171-a2bb192bbf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003882966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2003882966
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.304250316
Short name T32
Test name
Test status
Simulation time 17119162362 ps
CPU time 7.21 seconds
Started Jun 22 04:50:00 PM PDT 24
Finished Jun 22 04:50:09 PM PDT 24
Peak memory 204940 kb
Host smart-8e3b6747-7d0d-42b3-8193-91e2eda5bcea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304250316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.304250316
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3002287950
Short name T148
Test name
Test status
Simulation time 81605394 ps
CPU time 0.8 seconds
Started Jun 22 04:49:00 PM PDT 24
Finished Jun 22 04:49:03 PM PDT 24
Peak memory 204696 kb
Host smart-a1179340-1739-4efb-a128-266a90623b3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002287950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3002287950
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.980498345
Short name T17
Test name
Test status
Simulation time 9521957688 ps
CPU time 14.78 seconds
Started Jun 22 04:49:00 PM PDT 24
Finished Jun 22 04:49:15 PM PDT 24
Peak memory 213308 kb
Host smart-db791fd0-07ee-4d1d-b39a-af06809ccbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980498345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.980498345
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3552465064
Short name T239
Test name
Test status
Simulation time 867432293 ps
CPU time 1.99 seconds
Started Jun 22 04:49:02 PM PDT 24
Finished Jun 22 04:49:05 PM PDT 24
Peak memory 204988 kb
Host smart-5ec3222b-2e2e-454b-b910-c329d2d994e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552465064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3552465064
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.654551254
Short name T194
Test name
Test status
Simulation time 7602782099 ps
CPU time 6.12 seconds
Started Jun 22 04:49:03 PM PDT 24
Finished Jun 22 04:49:10 PM PDT 24
Peak memory 205092 kb
Host smart-f37534d7-62a8-4537-92a1-a36e480b2f5a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=654551254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.654551254
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3149780619
Short name T225
Test name
Test status
Simulation time 1683050961 ps
CPU time 5.39 seconds
Started Jun 22 04:49:01 PM PDT 24
Finished Jun 22 04:49:08 PM PDT 24
Peak memory 204996 kb
Host smart-042e33c5-4f5a-4b7c-b254-64e7e3e6003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149780619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3149780619
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3928795945
Short name T120
Test name
Test status
Simulation time 38381852 ps
CPU time 0.73 seconds
Started Jun 22 04:49:03 PM PDT 24
Finished Jun 22 04:49:05 PM PDT 24
Peak memory 204772 kb
Host smart-02332b5b-f0ee-49c7-b15b-b4e979b37c63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928795945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3928795945
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.2868640386
Short name T250
Test name
Test status
Simulation time 16482367974 ps
CPU time 17.69 seconds
Started Jun 22 04:49:00 PM PDT 24
Finished Jun 22 04:49:19 PM PDT 24
Peak memory 213260 kb
Host smart-85ca31d9-0680-46a5-94f0-6f47be8a5ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868640386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2868640386
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3628248080
Short name T254
Test name
Test status
Simulation time 5350920020 ps
CPU time 15.38 seconds
Started Jun 22 04:49:08 PM PDT 24
Finished Jun 22 04:49:25 PM PDT 24
Peak memory 213384 kb
Host smart-209741ed-38bb-4c47-9d97-35fa97cdf71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628248080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3628248080
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2065137817
Short name T240
Test name
Test status
Simulation time 1607568902 ps
CPU time 2.1 seconds
Started Jun 22 04:49:13 PM PDT 24
Finished Jun 22 04:49:17 PM PDT 24
Peak memory 204660 kb
Host smart-ec184521-0b61-4a0f-81a0-580daa62d0b0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065137817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2065137817
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1884177352
Short name T252
Test name
Test status
Simulation time 2880657944 ps
CPU time 7.61 seconds
Started Jun 22 04:49:00 PM PDT 24
Finished Jun 22 04:49:09 PM PDT 24
Peak memory 205072 kb
Host smart-f9d3f2c1-1a73-4bb9-a4a3-7f3e99affcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884177352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1884177352
Directory /workspace/9.rv_dm_sba_tl_access/latest
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