Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
78.00 94.81 78.48 88.43 62.82 84.33 98.42 38.72


Total test records in report: 406
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T115 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2380206495 Jun 24 05:55:00 PM PDT 24 Jun 24 05:55:08 PM PDT 24 514902893 ps
T97 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2898336150 Jun 24 05:55:03 PM PDT 24 Jun 24 05:55:08 PM PDT 24 154520111 ps
T274 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.804273584 Jun 24 05:54:30 PM PDT 24 Jun 24 05:54:33 PM PDT 24 134478106 ps
T275 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2531573606 Jun 24 05:55:01 PM PDT 24 Jun 24 05:55:06 PM PDT 24 2963194714 ps
T89 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2331761462 Jun 24 05:54:31 PM PDT 24 Jun 24 05:54:45 PM PDT 24 7665776699 ps
T276 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1202165698 Jun 24 05:54:55 PM PDT 24 Jun 24 05:55:13 PM PDT 24 27946112173 ps
T277 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2766442690 Jun 24 05:54:32 PM PDT 24 Jun 24 05:54:44 PM PDT 24 4265319777 ps
T98 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3216222785 Jun 24 05:54:44 PM PDT 24 Jun 24 05:54:54 PM PDT 24 417884119 ps
T278 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1499891826 Jun 24 05:55:02 PM PDT 24 Jun 24 05:55:06 PM PDT 24 500581637 ps
T279 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.442053546 Jun 24 05:54:32 PM PDT 24 Jun 24 05:54:36 PM PDT 24 159239831 ps
T121 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2460133747 Jun 24 05:55:01 PM PDT 24 Jun 24 05:55:25 PM PDT 24 5652565788 ps
T102 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2038190336 Jun 24 05:54:38 PM PDT 24 Jun 24 05:55:05 PM PDT 24 3053206247 ps
T280 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3072038376 Jun 24 05:54:51 PM PDT 24 Jun 24 05:54:53 PM PDT 24 143370294 ps
T281 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2770798688 Jun 24 05:54:44 PM PDT 24 Jun 24 05:54:53 PM PDT 24 8288307652 ps
T282 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.222294915 Jun 24 05:54:33 PM PDT 24 Jun 24 05:54:46 PM PDT 24 3024140725 ps
T283 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3947629142 Jun 24 05:54:24 PM PDT 24 Jun 24 05:56:02 PM PDT 24 35203552085 ps
T284 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2264423485 Jun 24 05:54:43 PM PDT 24 Jun 24 05:54:50 PM PDT 24 328250144 ps
T285 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4038979924 Jun 24 05:54:41 PM PDT 24 Jun 24 05:54:50 PM PDT 24 6954782582 ps
T286 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1530598692 Jun 24 05:55:03 PM PDT 24 Jun 24 05:55:07 PM PDT 24 232472726 ps
T287 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.200044787 Jun 24 05:54:24 PM PDT 24 Jun 24 05:54:30 PM PDT 24 1973961426 ps
T288 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.937319384 Jun 24 05:54:43 PM PDT 24 Jun 24 05:54:59 PM PDT 24 11227113831 ps
T289 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3457840611 Jun 24 05:54:51 PM PDT 24 Jun 24 05:55:45 PM PDT 24 64613976837 ps
T290 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3353932991 Jun 24 05:55:01 PM PDT 24 Jun 24 05:55:06 PM PDT 24 62106756 ps
T291 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1146635193 Jun 24 05:54:44 PM PDT 24 Jun 24 05:55:13 PM PDT 24 593549731 ps
T292 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2544869454 Jun 24 05:55:04 PM PDT 24 Jun 24 05:55:17 PM PDT 24 7332996725 ps
T293 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3918150973 Jun 24 05:54:59 PM PDT 24 Jun 24 05:55:01 PM PDT 24 1260436634 ps
T103 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1379069956 Jun 24 05:54:57 PM PDT 24 Jun 24 05:55:00 PM PDT 24 426727446 ps
T294 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.970985639 Jun 24 05:55:00 PM PDT 24 Jun 24 05:55:04 PM PDT 24 2373497680 ps
T295 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1773569352 Jun 24 05:54:30 PM PDT 24 Jun 24 05:54:32 PM PDT 24 114684835 ps
T296 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2048913988 Jun 24 05:54:57 PM PDT 24 Jun 24 05:55:01 PM PDT 24 144020927 ps
T297 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4085183922 Jun 24 05:54:44 PM PDT 24 Jun 24 05:55:26 PM PDT 24 14608120035 ps
T116 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3216674347 Jun 24 05:55:00 PM PDT 24 Jun 24 05:55:11 PM PDT 24 2562769881 ps
T298 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3612329081 Jun 24 05:54:24 PM PDT 24 Jun 24 05:54:27 PM PDT 24 97025650 ps
T299 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2305786819 Jun 24 05:54:35 PM PDT 24 Jun 24 05:54:38 PM PDT 24 165430298 ps
T300 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2625462104 Jun 24 05:54:27 PM PDT 24 Jun 24 05:54:30 PM PDT 24 32548173 ps
T301 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.180104614 Jun 24 05:54:52 PM PDT 24 Jun 24 05:54:55 PM PDT 24 100235782 ps
T302 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2458037225 Jun 24 05:54:56 PM PDT 24 Jun 24 05:55:01 PM PDT 24 3581855857 ps
T303 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4220043269 Jun 24 05:54:32 PM PDT 24 Jun 24 05:54:36 PM PDT 24 117593697 ps
T304 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1532364877 Jun 24 05:54:45 PM PDT 24 Jun 24 05:54:49 PM PDT 24 1938354531 ps
T305 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.627886008 Jun 24 05:54:30 PM PDT 24 Jun 24 05:54:32 PM PDT 24 626898238 ps
T306 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4110147244 Jun 24 05:54:33 PM PDT 24 Jun 24 05:54:51 PM PDT 24 5519872290 ps
T117 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2287817544 Jun 24 05:54:49 PM PDT 24 Jun 24 05:54:52 PM PDT 24 232573602 ps
T104 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3808787619 Jun 24 05:54:42 PM PDT 24 Jun 24 05:54:45 PM PDT 24 90360757 ps
T99 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2389331600 Jun 24 05:54:30 PM PDT 24 Jun 24 05:54:36 PM PDT 24 826908202 ps
T105 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.830488024 Jun 24 05:54:33 PM PDT 24 Jun 24 05:54:39 PM PDT 24 128013130 ps
T307 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3352530770 Jun 24 05:54:49 PM PDT 24 Jun 24 05:54:54 PM PDT 24 1344648891 ps
T308 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.408003520 Jun 24 05:54:43 PM PDT 24 Jun 24 05:54:54 PM PDT 24 3589262508 ps
T309 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2650425527 Jun 24 05:54:24 PM PDT 24 Jun 24 05:54:30 PM PDT 24 224178384 ps
T310 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1672504127 Jun 24 05:55:00 PM PDT 24 Jun 24 05:55:03 PM PDT 24 480762909 ps
T311 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1313448742 Jun 24 05:54:35 PM PDT 24 Jun 24 05:54:38 PM PDT 24 902356655 ps
T312 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1705397114 Jun 24 05:54:37 PM PDT 24 Jun 24 05:54:40 PM PDT 24 287696072 ps
T119 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3710511890 Jun 24 05:54:45 PM PDT 24 Jun 24 05:54:56 PM PDT 24 2846454185 ps
T313 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3340553247 Jun 24 05:54:32 PM PDT 24 Jun 24 05:56:41 PM PDT 24 50643945254 ps
T314 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3587277329 Jun 24 05:54:35 PM PDT 24 Jun 24 05:54:40 PM PDT 24 178324087 ps
T315 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1095112488 Jun 24 05:55:00 PM PDT 24 Jun 24 05:55:04 PM PDT 24 431902245 ps
T316 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1963754834 Jun 24 05:54:34 PM PDT 24 Jun 24 05:55:55 PM PDT 24 84560396732 ps
T317 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1467547444 Jun 24 05:55:02 PM PDT 24 Jun 24 05:55:06 PM PDT 24 4623158673 ps
T318 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.544980045 Jun 24 05:54:44 PM PDT 24 Jun 24 05:54:50 PM PDT 24 91908473 ps
T319 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.319370132 Jun 24 05:54:50 PM PDT 24 Jun 24 05:55:00 PM PDT 24 4563458202 ps
T320 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1060456157 Jun 24 05:54:44 PM PDT 24 Jun 24 05:54:47 PM PDT 24 186893566 ps
T321 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3145068840 Jun 24 05:54:55 PM PDT 24 Jun 24 05:55:07 PM PDT 24 5034004800 ps
T322 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.42193182 Jun 24 05:54:59 PM PDT 24 Jun 24 05:55:03 PM PDT 24 140219453 ps
T323 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3466348122 Jun 24 05:54:44 PM PDT 24 Jun 24 05:55:15 PM PDT 24 30203448520 ps
T125 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3731265118 Jun 24 05:55:02 PM PDT 24 Jun 24 05:55:16 PM PDT 24 2957283717 ps
T324 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2316964456 Jun 24 05:55:00 PM PDT 24 Jun 24 05:55:05 PM PDT 24 394298856 ps
T100 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1470065765 Jun 24 05:55:02 PM PDT 24 Jun 24 05:55:13 PM PDT 24 1889303684 ps
T325 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3562851999 Jun 24 05:54:44 PM PDT 24 Jun 24 05:54:55 PM PDT 24 1950753949 ps
T326 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3114025961 Jun 24 05:55:01 PM PDT 24 Jun 24 05:57:25 PM PDT 24 51782601143 ps
T327 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3374903363 Jun 24 05:54:24 PM PDT 24 Jun 24 05:54:28 PM PDT 24 1687362024 ps
T328 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.933795374 Jun 24 05:54:51 PM PDT 24 Jun 24 05:54:53 PM PDT 24 247514450 ps
T329 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.748409437 Jun 24 05:54:31 PM PDT 24 Jun 24 05:54:36 PM PDT 24 321444830 ps
T330 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.527059988 Jun 24 05:54:33 PM PDT 24 Jun 24 05:54:36 PM PDT 24 134669525 ps
T331 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2818249290 Jun 24 05:54:43 PM PDT 24 Jun 24 05:54:46 PM PDT 24 137731468 ps
T332 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.385467718 Jun 24 05:54:33 PM PDT 24 Jun 24 05:55:35 PM PDT 24 22343185746 ps
T333 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3690029828 Jun 24 05:55:02 PM PDT 24 Jun 24 05:55:11 PM PDT 24 328844826 ps
T106 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.51837267 Jun 24 05:54:34 PM PDT 24 Jun 24 05:55:30 PM PDT 24 2881951125 ps
T334 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.298574424 Jun 24 05:54:26 PM PDT 24 Jun 24 05:54:47 PM PDT 24 32682178671 ps
T124 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1960393071 Jun 24 05:54:55 PM PDT 24 Jun 24 05:55:10 PM PDT 24 2490855585 ps
T335 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2304589819 Jun 24 05:54:52 PM PDT 24 Jun 24 05:54:59 PM PDT 24 1124473199 ps
T107 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3988619659 Jun 24 05:54:48 PM PDT 24 Jun 24 05:54:51 PM PDT 24 148457090 ps
T336 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4006647612 Jun 24 05:54:53 PM PDT 24 Jun 24 05:54:56 PM PDT 24 199079117 ps
T90 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.627278834 Jun 24 05:54:36 PM PDT 24 Jun 24 05:54:42 PM PDT 24 1669134125 ps
T337 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1435833956 Jun 24 05:54:56 PM PDT 24 Jun 24 05:55:00 PM PDT 24 183999320 ps
T338 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2309777810 Jun 24 05:55:00 PM PDT 24 Jun 24 05:55:12 PM PDT 24 2233759480 ps
T339 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4077951646 Jun 24 05:55:00 PM PDT 24 Jun 24 05:55:07 PM PDT 24 1936997219 ps
T340 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4042895283 Jun 24 05:55:02 PM PDT 24 Jun 24 05:55:50 PM PDT 24 18679604590 ps
T341 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1126276777 Jun 24 05:55:00 PM PDT 24 Jun 24 05:55:05 PM PDT 24 1151246251 ps
T342 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.764401995 Jun 24 05:54:32 PM PDT 24 Jun 24 05:54:42 PM PDT 24 12395667094 ps
T343 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4163075958 Jun 24 05:54:30 PM PDT 24 Jun 24 05:54:32 PM PDT 24 201815302 ps
T344 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1630194397 Jun 24 05:54:51 PM PDT 24 Jun 24 05:54:59 PM PDT 24 359038479 ps
T345 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.946266332 Jun 24 05:55:03 PM PDT 24 Jun 24 05:55:14 PM PDT 24 964128682 ps
T346 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4287874515 Jun 24 05:54:54 PM PDT 24 Jun 24 05:55:12 PM PDT 24 11500649772 ps
T347 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3280757417 Jun 24 05:54:34 PM PDT 24 Jun 24 05:54:43 PM PDT 24 12227500914 ps
T348 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3551116152 Jun 24 05:54:59 PM PDT 24 Jun 24 05:55:02 PM PDT 24 182676787 ps
T349 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3474658709 Jun 24 05:54:44 PM PDT 24 Jun 24 05:54:47 PM PDT 24 79846422 ps
T350 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3171495278 Jun 24 05:54:49 PM PDT 24 Jun 24 05:55:37 PM PDT 24 37686207197 ps
T351 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.866417672 Jun 24 05:54:42 PM PDT 24 Jun 24 05:54:48 PM PDT 24 195937222 ps
T91 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2916304549 Jun 24 05:54:42 PM PDT 24 Jun 24 05:54:55 PM PDT 24 3979758305 ps
T352 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3690074335 Jun 24 05:54:44 PM PDT 24 Jun 24 05:54:58 PM PDT 24 15151338031 ps
T353 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1143611759 Jun 24 05:54:41 PM PDT 24 Jun 24 05:54:43 PM PDT 24 166364885 ps
T354 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3403923436 Jun 24 05:54:53 PM PDT 24 Jun 24 05:54:55 PM PDT 24 355127101 ps
T355 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3999772283 Jun 24 05:54:59 PM PDT 24 Jun 24 05:55:08 PM PDT 24 2817045382 ps
T356 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2604553555 Jun 24 05:54:37 PM PDT 24 Jun 24 05:54:39 PM PDT 24 76284363 ps
T357 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.714648613 Jun 24 05:54:32 PM PDT 24 Jun 24 06:03:15 PM PDT 24 200962826957 ps
T108 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4194202322 Jun 24 05:54:45 PM PDT 24 Jun 24 05:54:48 PM PDT 24 83569542 ps
T358 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1032627299 Jun 24 05:54:57 PM PDT 24 Jun 24 05:54:59 PM PDT 24 436886465 ps
T359 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2885497850 Jun 24 05:54:31 PM PDT 24 Jun 24 05:54:35 PM PDT 24 178164394 ps
T360 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.42404943 Jun 24 05:54:51 PM PDT 24 Jun 24 05:54:53 PM PDT 24 97238784 ps
T361 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3172590345 Jun 24 05:54:51 PM PDT 24 Jun 24 05:54:55 PM PDT 24 284718327 ps
T362 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4272822737 Jun 24 05:54:44 PM PDT 24 Jun 24 05:54:47 PM PDT 24 229427948 ps
T363 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4098191114 Jun 24 05:54:30 PM PDT 24 Jun 24 05:54:36 PM PDT 24 1219694127 ps
T364 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3393233434 Jun 24 05:54:32 PM PDT 24 Jun 24 05:54:36 PM PDT 24 129822925 ps
T122 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2159746660 Jun 24 05:54:52 PM PDT 24 Jun 24 05:55:22 PM PDT 24 5623763641 ps
T365 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.787950268 Jun 24 05:54:41 PM PDT 24 Jun 24 05:54:47 PM PDT 24 3310009738 ps
T366 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2869796874 Jun 24 05:54:56 PM PDT 24 Jun 24 05:55:05 PM PDT 24 8899603983 ps
T367 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2602087210 Jun 24 05:54:34 PM PDT 24 Jun 24 05:55:51 PM PDT 24 4094824053 ps
T368 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3584918548 Jun 24 05:55:03 PM PDT 24 Jun 24 05:55:10 PM PDT 24 331022675 ps
T369 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2413455556 Jun 24 05:54:44 PM PDT 24 Jun 24 05:54:47 PM PDT 24 82781432 ps
T370 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3285030653 Jun 24 05:54:50 PM PDT 24 Jun 24 05:55:00 PM PDT 24 3225031008 ps
T371 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3637767589 Jun 24 05:54:44 PM PDT 24 Jun 24 05:54:48 PM PDT 24 207002137 ps
T372 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4202865754 Jun 24 05:54:45 PM PDT 24 Jun 24 05:54:49 PM PDT 24 135762259 ps
T373 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2424590993 Jun 24 05:54:44 PM PDT 24 Jun 24 05:54:47 PM PDT 24 609570577 ps
T374 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1906879105 Jun 24 05:54:37 PM PDT 24 Jun 24 05:54:45 PM PDT 24 589770164 ps
T375 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3284531774 Jun 24 05:55:00 PM PDT 24 Jun 24 05:55:07 PM PDT 24 193314304 ps
T376 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3172577796 Jun 24 05:54:45 PM PDT 24 Jun 24 05:54:49 PM PDT 24 1829451672 ps
T377 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.389034142 Jun 24 05:54:33 PM PDT 24 Jun 24 05:55:39 PM PDT 24 4951038239 ps
T378 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.493390299 Jun 24 05:55:01 PM PDT 24 Jun 24 05:55:07 PM PDT 24 1100606871 ps
T123 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2769947561 Jun 24 05:54:26 PM PDT 24 Jun 24 05:54:47 PM PDT 24 2837737724 ps
T379 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.581450287 Jun 24 05:54:34 PM PDT 24 Jun 24 05:54:40 PM PDT 24 1744747183 ps
T380 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2922901375 Jun 24 05:55:00 PM PDT 24 Jun 24 05:55:12 PM PDT 24 1968431312 ps
T381 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2240787701 Jun 24 05:54:51 PM PDT 24 Jun 24 05:54:52 PM PDT 24 76342635 ps
T382 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2226020455 Jun 24 05:54:34 PM PDT 24 Jun 24 05:54:38 PM PDT 24 1748380961 ps
T383 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1462700302 Jun 24 05:55:03 PM PDT 24 Jun 24 05:55:07 PM PDT 24 224025155 ps
T384 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1600557950 Jun 24 05:54:42 PM PDT 24 Jun 24 05:54:53 PM PDT 24 18169108780 ps
T385 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1254554978 Jun 24 05:55:01 PM PDT 24 Jun 24 05:55:07 PM PDT 24 119462090 ps
T386 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.108074334 Jun 24 05:54:56 PM PDT 24 Jun 24 05:54:58 PM PDT 24 2972795912 ps
T387 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1410189545 Jun 24 05:54:32 PM PDT 24 Jun 24 05:54:36 PM PDT 24 262704603 ps
T388 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2215798205 Jun 24 05:54:41 PM PDT 24 Jun 24 05:54:43 PM PDT 24 213088494 ps
T389 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.564855709 Jun 24 05:54:41 PM PDT 24 Jun 24 05:54:51 PM PDT 24 4960984733 ps
T390 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2487672469 Jun 24 05:54:50 PM PDT 24 Jun 24 05:54:59 PM PDT 24 853228631 ps
T391 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3549231332 Jun 24 05:54:56 PM PDT 24 Jun 24 05:55:00 PM PDT 24 410484276 ps
T392 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1645181703 Jun 24 05:54:33 PM PDT 24 Jun 24 05:54:47 PM PDT 24 1590754521 ps
T393 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4278331 Jun 24 05:55:04 PM PDT 24 Jun 24 05:55:16 PM PDT 24 5472661930 ps
T394 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1748580828 Jun 24 05:54:33 PM PDT 24 Jun 24 05:54:38 PM PDT 24 242062978 ps
T395 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2051753436 Jun 24 05:55:00 PM PDT 24 Jun 24 05:55:19 PM PDT 24 1180632518 ps
T396 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1877913720 Jun 24 05:54:59 PM PDT 24 Jun 24 05:55:01 PM PDT 24 176736658 ps
T397 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.4127418169 Jun 24 05:54:32 PM PDT 24 Jun 24 05:54:39 PM PDT 24 2830213482 ps
T398 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.739293842 Jun 24 05:54:25 PM PDT 24 Jun 24 05:54:28 PM PDT 24 157588174 ps
T399 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1612887530 Jun 24 05:54:41 PM PDT 24 Jun 24 05:56:00 PM PDT 24 15629076034 ps
T400 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2632841877 Jun 24 05:55:01 PM PDT 24 Jun 24 05:55:09 PM PDT 24 1983742883 ps
T401 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.614396915 Jun 24 05:54:34 PM PDT 24 Jun 24 05:54:38 PM PDT 24 184365265 ps
T402 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.589873049 Jun 24 05:54:40 PM PDT 24 Jun 24 05:54:54 PM PDT 24 17932321076 ps
T403 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1006597490 Jun 24 05:54:39 PM PDT 24 Jun 24 05:55:46 PM PDT 24 5133992813 ps
T404 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3334939432 Jun 24 05:54:24 PM PDT 24 Jun 24 05:55:30 PM PDT 24 2261444914 ps
T405 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2227749791 Jun 24 05:54:32 PM PDT 24 Jun 24 05:54:36 PM PDT 24 157758872 ps
T406 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4008202593 Jun 24 05:54:42 PM PDT 24 Jun 24 05:54:45 PM PDT 24 375406483 ps

Test location /workspace/coverage/default/42.rv_dm_stress_all.2020019588
Short name T5
Test name
Test status
Simulation time 17704401177 ps
CPU time 51.41 seconds
Started Jun 24 06:02:31 PM PDT 24
Finished Jun 24 06:03:23 PM PDT 24
Peak memory 204984 kb
Host smart-ceba6cca-eb82-4cb8-be34-26e64232279a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020019588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2020019588
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2382522425
Short name T4
Test name
Test status
Simulation time 5393146023 ps
CPU time 4.88 seconds
Started Jun 24 06:01:45 PM PDT 24
Finished Jun 24 06:01:51 PM PDT 24
Peak memory 205116 kb
Host smart-a3ddc0a2-7b59-411b-b35d-ad29dc13365d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382522425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2382522425
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.563300266
Short name T44
Test name
Test status
Simulation time 3253139855 ps
CPU time 8.43 seconds
Started Jun 24 05:54:41 PM PDT 24
Finished Jun 24 05:54:50 PM PDT 24
Peak memory 221864 kb
Host smart-c1d0a78e-17b0-4f08-b279-d32c743da295
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563300266 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.563300266
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3803329901
Short name T2
Test name
Test status
Simulation time 83705826 ps
CPU time 0.77 seconds
Started Jun 24 06:01:55 PM PDT 24
Finished Jun 24 06:01:56 PM PDT 24
Peak memory 204800 kb
Host smart-3934ab6c-3a10-4ed3-9473-cf192c5b2513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803329901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3803329901
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.4033869915
Short name T6
Test name
Test status
Simulation time 9878723623 ps
CPU time 24.52 seconds
Started Jun 24 06:02:21 PM PDT 24
Finished Jun 24 06:02:47 PM PDT 24
Peak memory 204964 kb
Host smart-f6a100b0-a9f8-4bcf-a9e1-512721939c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033869915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.4033869915
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1156313879
Short name T74
Test name
Test status
Simulation time 1670376257 ps
CPU time 20.56 seconds
Started Jun 24 05:54:42 PM PDT 24
Finished Jun 24 05:55:04 PM PDT 24
Peak memory 213464 kb
Host smart-ef5b4122-45f4-4cb2-8243-83d13a8c1999
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156313879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1156313879
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2374465507
Short name T78
Test name
Test status
Simulation time 1879368831 ps
CPU time 31.44 seconds
Started Jun 24 05:54:31 PM PDT 24
Finished Jun 24 05:55:05 PM PDT 24
Peak memory 213544 kb
Host smart-09e123e0-bc0b-4e00-9be9-94ab08b9d4e3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374465507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2374465507
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2630188845
Short name T21
Test name
Test status
Simulation time 68807042626 ps
CPU time 180.34 seconds
Started Jun 24 06:01:45 PM PDT 24
Finished Jun 24 06:04:47 PM PDT 24
Peak memory 213400 kb
Host smart-7bd3cd22-7c85-444b-b815-f378a8efaae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630188845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2630188845
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2186376799
Short name T33
Test name
Test status
Simulation time 2556756095 ps
CPU time 4.81 seconds
Started Jun 24 06:00:46 PM PDT 24
Finished Jun 24 06:00:52 PM PDT 24
Peak memory 204796 kb
Host smart-9043a9ba-c665-47d4-a393-c63cee504527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186376799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2186376799
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2264423485
Short name T284
Test name
Test status
Simulation time 328250144 ps
CPU time 5.35 seconds
Started Jun 24 05:54:43 PM PDT 24
Finished Jun 24 05:54:50 PM PDT 24
Peak memory 213524 kb
Host smart-176201bd-a486-41ba-83a4-800a977db283
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264423485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2264423485
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.4254879648
Short name T35
Test name
Test status
Simulation time 33488577906 ps
CPU time 42.06 seconds
Started Jun 24 06:01:34 PM PDT 24
Finished Jun 24 06:02:17 PM PDT 24
Peak memory 213192 kb
Host smart-1e622582-62d5-4a65-aaf2-10331f7b4f63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254879648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.4254879648
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2416064562
Short name T51
Test name
Test status
Simulation time 2610090876 ps
CPU time 4.69 seconds
Started Jun 24 06:01:33 PM PDT 24
Finished Jun 24 06:01:39 PM PDT 24
Peak memory 228896 kb
Host smart-922b47dc-54cd-4c03-898b-95230f791fbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416064562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2416064562
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.2319689864
Short name T17
Test name
Test status
Simulation time 1505872509 ps
CPU time 1.29 seconds
Started Jun 24 06:00:53 PM PDT 24
Finished Jun 24 06:00:55 PM PDT 24
Peak memory 204732 kb
Host smart-e5717407-819e-4021-9371-4072884bf68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319689864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2319689864
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.143053932
Short name T15
Test name
Test status
Simulation time 22730286842 ps
CPU time 16.36 seconds
Started Jun 24 06:01:34 PM PDT 24
Finished Jun 24 06:01:51 PM PDT 24
Peak memory 205004 kb
Host smart-f9c5615b-a722-4678-a7e5-f76aedf91ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143053932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.143053932
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3686262821
Short name T31
Test name
Test status
Simulation time 193016520 ps
CPU time 0.99 seconds
Started Jun 24 06:00:54 PM PDT 24
Finished Jun 24 06:00:56 PM PDT 24
Peak memory 204720 kb
Host smart-aad7fadb-eec3-4ac0-899d-51bdafff9220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686262821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3686262821
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3266734590
Short name T72
Test name
Test status
Simulation time 12876404250 ps
CPU time 22.15 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:55:08 PM PDT 24
Peak memory 213596 kb
Host smart-78643a85-dc81-4650-b51d-0c76ce59e361
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266734590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3266734590
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.975229852
Short name T29
Test name
Test status
Simulation time 93421903 ps
CPU time 0.81 seconds
Started Jun 24 06:00:58 PM PDT 24
Finished Jun 24 06:00:59 PM PDT 24
Peak memory 212908 kb
Host smart-59c13edd-aac0-41dc-9067-88e58638d08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975229852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.975229852
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.4001287824
Short name T12
Test name
Test status
Simulation time 301603294 ps
CPU time 1.06 seconds
Started Jun 24 06:01:04 PM PDT 24
Finished Jun 24 06:01:06 PM PDT 24
Peak memory 204736 kb
Host smart-c6505ae5-9760-4470-a924-174308da16cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001287824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.4001287824
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2504909274
Short name T83
Test name
Test status
Simulation time 221941457 ps
CPU time 3.79 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:05 PM PDT 24
Peak memory 205552 kb
Host smart-20630e1f-271d-4880-9aea-0925b04e4ebb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504909274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2504909274
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.1014220471
Short name T9
Test name
Test status
Simulation time 11348911737 ps
CPU time 16.93 seconds
Started Jun 24 06:02:21 PM PDT 24
Finished Jun 24 06:02:39 PM PDT 24
Peak memory 213188 kb
Host smart-aeae6e8f-08a6-4983-bcbe-41e295c79a56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014220471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1014220471
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.804689177
Short name T61
Test name
Test status
Simulation time 551421044 ps
CPU time 1.04 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:54:28 PM PDT 24
Peak memory 205000 kb
Host smart-3b24b38f-5fa3-482f-ad4e-1655a2fe1c73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804689177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.804689177
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1337463754
Short name T37
Test name
Test status
Simulation time 662551319 ps
CPU time 2.25 seconds
Started Jun 24 06:00:58 PM PDT 24
Finished Jun 24 06:01:01 PM PDT 24
Peak memory 204648 kb
Host smart-48e08153-855d-47a1-aba4-c5b50f355651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337463754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1337463754
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.349981567
Short name T19
Test name
Test status
Simulation time 867503574 ps
CPU time 1.25 seconds
Started Jun 24 06:00:39 PM PDT 24
Finished Jun 24 06:00:40 PM PDT 24
Peak memory 204720 kb
Host smart-71e2526a-477f-4cd1-8163-bc192fa841f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349981567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.349981567
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.362715895
Short name T118
Test name
Test status
Simulation time 6157078967 ps
CPU time 23.17 seconds
Started Jun 24 05:54:56 PM PDT 24
Finished Jun 24 05:55:20 PM PDT 24
Peak memory 213628 kb
Host smart-e5d9ee81-ac6b-4311-b683-98c612041441
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362715895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.362715895
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1810031856
Short name T34
Test name
Test status
Simulation time 3073323639 ps
CPU time 9.41 seconds
Started Jun 24 06:01:03 PM PDT 24
Finished Jun 24 06:01:13 PM PDT 24
Peak memory 204984 kb
Host smart-0502d9fb-f2b1-4da2-add8-2fe770eba05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810031856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1810031856
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.340492128
Short name T88
Test name
Test status
Simulation time 2837562193 ps
CPU time 9.47 seconds
Started Jun 24 05:54:26 PM PDT 24
Finished Jun 24 05:54:38 PM PDT 24
Peak memory 205320 kb
Host smart-baba0927-b61d-478d-afc5-83b6f3d7f737
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340492128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.340492128
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2460133747
Short name T121
Test name
Test status
Simulation time 5652565788 ps
CPU time 22.11 seconds
Started Jun 24 05:55:01 PM PDT 24
Finished Jun 24 05:55:25 PM PDT 24
Peak memory 213604 kb
Host smart-63769e5f-c4dd-4673-b4c3-7c11850ea70d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460133747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
460133747
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3582781188
Short name T26
Test name
Test status
Simulation time 911461226 ps
CPU time 2.98 seconds
Started Jun 24 06:00:46 PM PDT 24
Finished Jun 24 06:00:50 PM PDT 24
Peak memory 204608 kb
Host smart-7862a5a6-e554-4852-a2dd-46f78be4c0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582781188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3582781188
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.581450287
Short name T379
Test name
Test status
Simulation time 1744747183 ps
CPU time 3.02 seconds
Started Jun 24 05:54:34 PM PDT 24
Finished Jun 24 05:54:40 PM PDT 24
Peak memory 213632 kb
Host smart-f9c30282-6293-40cb-9ef4-c08fd208a2ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581450287 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.581450287
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.4089278565
Short name T56
Test name
Test status
Simulation time 172435093 ps
CPU time 1.02 seconds
Started Jun 24 06:00:53 PM PDT 24
Finished Jun 24 06:00:54 PM PDT 24
Peak memory 204744 kb
Host smart-877361ab-7a37-4c85-be2c-1360a55907a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089278565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.4089278565
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3334939432
Short name T404
Test name
Test status
Simulation time 2261444914 ps
CPU time 64.76 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:55:30 PM PDT 24
Peak memory 213628 kb
Host smart-2819e543-07e9-4353-a21f-c0179d2cf393
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334939432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3334939432
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.389034142
Short name T377
Test name
Test status
Simulation time 4951038239 ps
CPU time 64.16 seconds
Started Jun 24 05:54:33 PM PDT 24
Finished Jun 24 05:55:39 PM PDT 24
Peak memory 213020 kb
Host smart-6de4abeb-40b9-4cb1-a55f-3b8c15b6468f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389034142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.389034142
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3156016676
Short name T94
Test name
Test status
Simulation time 503387978 ps
CPU time 2.81 seconds
Started Jun 24 05:54:25 PM PDT 24
Finished Jun 24 05:54:30 PM PDT 24
Peak memory 213692 kb
Host smart-d9478926-c5c4-4af2-a759-35c718e22274
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156016676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3156016676
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2604553555
Short name T356
Test name
Test status
Simulation time 76284363 ps
CPU time 1.57 seconds
Started Jun 24 05:54:37 PM PDT 24
Finished Jun 24 05:54:39 PM PDT 24
Peak memory 213532 kb
Host smart-1cc2eb92-a5c2-4b07-a026-88d70fc8c79c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604553555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2604553555
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3187501241
Short name T269
Test name
Test status
Simulation time 37451268910 ps
CPU time 51.95 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:55:17 PM PDT 24
Peak memory 205276 kb
Host smart-d0883dcf-7dee-48da-9746-244d2a12d4d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187501241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3187501241
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3947629142
Short name T283
Test name
Test status
Simulation time 35203552085 ps
CPU time 95.82 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:56:02 PM PDT 24
Peak memory 205272 kb
Host smart-d1db4647-3812-4616-ac0e-28f80dd14190
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947629142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.3947629142
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.200044787
Short name T287
Test name
Test status
Simulation time 1973961426 ps
CPU time 4.06 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:54:30 PM PDT 24
Peak memory 205152 kb
Host smart-1d656061-2415-4dcb-92d0-4e5ff9b8a200
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200044787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.200044787
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.298574424
Short name T334
Test name
Test status
Simulation time 32682178671 ps
CPU time 18.23 seconds
Started Jun 24 05:54:26 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 205248 kb
Host smart-0411fa2f-c9ca-4552-b72b-6af20de6a13e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298574424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.298574424
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3374903363
Short name T327
Test name
Test status
Simulation time 1687362024 ps
CPU time 2.95 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:54:28 PM PDT 24
Peak memory 204976 kb
Host smart-b00b92de-285b-4316-b006-6f9e70967b92
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374903363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3374903363
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.739293842
Short name T398
Test name
Test status
Simulation time 157588174 ps
CPU time 1.08 seconds
Started Jun 24 05:54:25 PM PDT 24
Finished Jun 24 05:54:28 PM PDT 24
Peak memory 205004 kb
Host smart-4e112b81-6091-463d-8402-db1e61dddf5e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739293842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.739293842
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2625462104
Short name T300
Test name
Test status
Simulation time 32548173 ps
CPU time 0.69 seconds
Started Jun 24 05:54:27 PM PDT 24
Finished Jun 24 05:54:30 PM PDT 24
Peak memory 204944 kb
Host smart-bae74a7a-8766-42d0-8ede-dab42c2e25f9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625462104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2625462104
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3612329081
Short name T298
Test name
Test status
Simulation time 97025650 ps
CPU time 0.73 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:54:27 PM PDT 24
Peak memory 205004 kb
Host smart-e8618562-3a22-4d8e-8302-d237a37c6f14
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612329081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3612329081
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2389331600
Short name T99
Test name
Test status
Simulation time 826908202 ps
CPU time 4.49 seconds
Started Jun 24 05:54:30 PM PDT 24
Finished Jun 24 05:54:36 PM PDT 24
Peak memory 205368 kb
Host smart-07546347-3ab2-47f8-9aed-4b3a7d85fda8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389331600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2389331600
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2650425527
Short name T309
Test name
Test status
Simulation time 224178384 ps
CPU time 4.59 seconds
Started Jun 24 05:54:24 PM PDT 24
Finished Jun 24 05:54:30 PM PDT 24
Peak memory 213572 kb
Host smart-6c347914-7dfc-40f2-90a1-f8f2e733e498
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650425527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2650425527
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2769947561
Short name T123
Test name
Test status
Simulation time 2837737724 ps
CPU time 18.67 seconds
Started Jun 24 05:54:26 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 213632 kb
Host smart-7b369e63-d55d-46e1-8839-3381d34ffcd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769947561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2769947561
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2602087210
Short name T367
Test name
Test status
Simulation time 4094824053 ps
CPU time 74.94 seconds
Started Jun 24 05:54:34 PM PDT 24
Finished Jun 24 05:55:51 PM PDT 24
Peak memory 213840 kb
Host smart-a0df21ae-217b-4247-a2e4-da82b905a90c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602087210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2602087210
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.51837267
Short name T106
Test name
Test status
Simulation time 2881951125 ps
CPU time 53.38 seconds
Started Jun 24 05:54:34 PM PDT 24
Finished Jun 24 05:55:30 PM PDT 24
Peak memory 213592 kb
Host smart-7477a264-09b4-486e-b381-9f689fe8b626
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51837267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.51837267
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2724556731
Short name T77
Test name
Test status
Simulation time 146395330 ps
CPU time 2.57 seconds
Started Jun 24 05:54:36 PM PDT 24
Finished Jun 24 05:54:40 PM PDT 24
Peak memory 213536 kb
Host smart-62002c2a-d20f-4b7a-addc-35cae6ff1707
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724556731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2724556731
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1705397114
Short name T312
Test name
Test status
Simulation time 287696072 ps
CPU time 2.55 seconds
Started Jun 24 05:54:37 PM PDT 24
Finished Jun 24 05:54:40 PM PDT 24
Peak memory 221776 kb
Host smart-7c6b5a7c-b857-4098-9cd5-01d200ff44ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705397114 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1705397114
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.762691133
Short name T81
Test name
Test status
Simulation time 153404713 ps
CPU time 2.47 seconds
Started Jun 24 05:54:31 PM PDT 24
Finished Jun 24 05:54:36 PM PDT 24
Peak memory 213540 kb
Host smart-007154fd-9140-486d-9e3f-bb831ed454d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762691133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.762691133
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3280757417
Short name T347
Test name
Test status
Simulation time 12227500914 ps
CPU time 6.48 seconds
Started Jun 24 05:54:34 PM PDT 24
Finished Jun 24 05:54:43 PM PDT 24
Peak memory 205276 kb
Host smart-07ca9a00-ee9e-4b34-bb8a-0cc52c187874
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280757417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3280757417
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3393233434
Short name T364
Test name
Test status
Simulation time 129822925 ps
CPU time 1 seconds
Started Jun 24 05:54:32 PM PDT 24
Finished Jun 24 05:54:36 PM PDT 24
Peak memory 205008 kb
Host smart-272bb368-2cf4-4f70-91d7-d366f1ddaedf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393233434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3393233434
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2331761462
Short name T89
Test name
Test status
Simulation time 7665776699 ps
CPU time 10.69 seconds
Started Jun 24 05:54:31 PM PDT 24
Finished Jun 24 05:54:45 PM PDT 24
Peak memory 205324 kb
Host smart-9b6eb637-6485-4f3d-b6d4-2ceb8d257142
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331761462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2331761462
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4110147244
Short name T306
Test name
Test status
Simulation time 5519872290 ps
CPU time 15.48 seconds
Started Jun 24 05:54:33 PM PDT 24
Finished Jun 24 05:54:51 PM PDT 24
Peak memory 205248 kb
Host smart-8d1129d3-e7a0-4d56-8141-8ae99c840a8c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110147244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.4
110147244
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1313448742
Short name T311
Test name
Test status
Simulation time 902356655 ps
CPU time 1.37 seconds
Started Jun 24 05:54:35 PM PDT 24
Finished Jun 24 05:54:38 PM PDT 24
Peak memory 205036 kb
Host smart-5dd968cb-4b77-4afc-b849-3bdc37e1e940
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313448742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1313448742
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3340553247
Short name T313
Test name
Test status
Simulation time 50643945254 ps
CPU time 126.54 seconds
Started Jun 24 05:54:32 PM PDT 24
Finished Jun 24 05:56:41 PM PDT 24
Peak memory 205256 kb
Host smart-fcb92447-5342-45db-9e5e-61cb42e792fc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340553247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3340553247
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.627886008
Short name T305
Test name
Test status
Simulation time 626898238 ps
CPU time 1.21 seconds
Started Jun 24 05:54:30 PM PDT 24
Finished Jun 24 05:54:32 PM PDT 24
Peak memory 204988 kb
Host smart-3df80feb-977b-4b20-9763-df0af4a2f5cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627886008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.627886008
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.804273584
Short name T274
Test name
Test status
Simulation time 134478106 ps
CPU time 0.84 seconds
Started Jun 24 05:54:30 PM PDT 24
Finished Jun 24 05:54:33 PM PDT 24
Peak memory 205224 kb
Host smart-181d5543-c5ae-425f-9a1a-831109042ccc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804273584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.804273584
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2227749791
Short name T405
Test name
Test status
Simulation time 157758872 ps
CPU time 0.72 seconds
Started Jun 24 05:54:32 PM PDT 24
Finished Jun 24 05:54:36 PM PDT 24
Peak memory 204944 kb
Host smart-bbb7f5d9-8be6-49ed-85da-09d400a3352b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227749791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2227749791
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1773569352
Short name T295
Test name
Test status
Simulation time 114684835 ps
CPU time 0.73 seconds
Started Jun 24 05:54:30 PM PDT 24
Finished Jun 24 05:54:32 PM PDT 24
Peak memory 205016 kb
Host smart-ed39c3d4-883d-4834-bddb-6a080817f469
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773569352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1773569352
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.748409437
Short name T329
Test name
Test status
Simulation time 321444830 ps
CPU time 3.58 seconds
Started Jun 24 05:54:31 PM PDT 24
Finished Jun 24 05:54:36 PM PDT 24
Peak memory 205316 kb
Host smart-6960aaca-19a9-40af-98b4-14dc3c41ebfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748409437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.748409437
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.544980045
Short name T318
Test name
Test status
Simulation time 91908473 ps
CPU time 5.05 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:50 PM PDT 24
Peak memory 213784 kb
Host smart-c18cea89-bb40-4e48-9a56-9ed6ddfb3298
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544980045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.544980045
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.222294915
Short name T282
Test name
Test status
Simulation time 3024140725 ps
CPU time 10.46 seconds
Started Jun 24 05:54:33 PM PDT 24
Finished Jun 24 05:54:46 PM PDT 24
Peak memory 213604 kb
Host smart-89798876-5c70-4725-b2cb-32347a3adaa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222294915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.222294915
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2304589819
Short name T335
Test name
Test status
Simulation time 1124473199 ps
CPU time 5.86 seconds
Started Jun 24 05:54:52 PM PDT 24
Finished Jun 24 05:54:59 PM PDT 24
Peak memory 221804 kb
Host smart-c24872cb-5e6e-4291-8569-157ca643a9ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304589819 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2304589819
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3988619659
Short name T107
Test name
Test status
Simulation time 148457090 ps
CPU time 2.1 seconds
Started Jun 24 05:54:48 PM PDT 24
Finished Jun 24 05:54:51 PM PDT 24
Peak memory 213568 kb
Host smart-18ca3bd3-fd34-4b1d-9103-4a40992122b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988619659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3988619659
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2869796874
Short name T366
Test name
Test status
Simulation time 8899603983 ps
CPU time 7.87 seconds
Started Jun 24 05:54:56 PM PDT 24
Finished Jun 24 05:55:05 PM PDT 24
Peak memory 205272 kb
Host smart-aafa6374-f8d4-46be-a16d-ab841050d58b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869796874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.2869796874
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2458037225
Short name T302
Test name
Test status
Simulation time 3581855857 ps
CPU time 4.41 seconds
Started Jun 24 05:54:56 PM PDT 24
Finished Jun 24 05:55:01 PM PDT 24
Peak memory 205244 kb
Host smart-a51f80e4-aa61-455a-8acf-558b4dcccaee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458037225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2458037225
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4265416080
Short name T60
Test name
Test status
Simulation time 904133661 ps
CPU time 2.89 seconds
Started Jun 24 05:54:49 PM PDT 24
Finished Jun 24 05:54:53 PM PDT 24
Peak memory 204976 kb
Host smart-1ae598d8-e6b2-4c3a-b5b0-674b97584924
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265416080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
4265416080
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.372296849
Short name T110
Test name
Test status
Simulation time 264926047 ps
CPU time 6.83 seconds
Started Jun 24 05:54:51 PM PDT 24
Finished Jun 24 05:54:59 PM PDT 24
Peak memory 205356 kb
Host smart-81f40004-5c79-4cb4-b205-50f922496244
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372296849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.372296849
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1362649839
Short name T70
Test name
Test status
Simulation time 155045045 ps
CPU time 5.04 seconds
Started Jun 24 05:54:50 PM PDT 24
Finished Jun 24 05:54:56 PM PDT 24
Peak memory 213528 kb
Host smart-ce0e9996-1b1c-4e48-8d98-8c6f7efcc69e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362649839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1362649839
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3285030653
Short name T370
Test name
Test status
Simulation time 3225031008 ps
CPU time 8.69 seconds
Started Jun 24 05:54:50 PM PDT 24
Finished Jun 24 05:55:00 PM PDT 24
Peak memory 213604 kb
Host smart-7978c8be-b11a-475a-8d8d-48a9ba4ccd59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285030653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
285030653
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.319370132
Short name T319
Test name
Test status
Simulation time 4563458202 ps
CPU time 9.61 seconds
Started Jun 24 05:54:50 PM PDT 24
Finished Jun 24 05:55:00 PM PDT 24
Peak memory 221784 kb
Host smart-db357f7b-2d9d-4356-8ec0-7127c4b05dda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319370132 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.319370132
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1095112488
Short name T315
Test name
Test status
Simulation time 431902245 ps
CPU time 1.61 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:04 PM PDT 24
Peak memory 213772 kb
Host smart-1e83a253-a223-475a-973d-5e4fdc21d4b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095112488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1095112488
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1202165698
Short name T276
Test name
Test status
Simulation time 27946112173 ps
CPU time 17.59 seconds
Started Jun 24 05:54:55 PM PDT 24
Finished Jun 24 05:55:13 PM PDT 24
Peak memory 205212 kb
Host smart-75ddb314-9e6d-4588-bb71-30f950255c54
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202165698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1202165698
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4287874515
Short name T346
Test name
Test status
Simulation time 11500649772 ps
CPU time 17.26 seconds
Started Jun 24 05:54:54 PM PDT 24
Finished Jun 24 05:55:12 PM PDT 24
Peak memory 205328 kb
Host smart-7fbcb797-5d16-4ea1-a225-2aefab180054
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287874515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
4287874515
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.225355593
Short name T270
Test name
Test status
Simulation time 763213288 ps
CPU time 1.34 seconds
Started Jun 24 05:54:50 PM PDT 24
Finished Jun 24 05:54:52 PM PDT 24
Peak memory 204992 kb
Host smart-9b656756-93db-44e8-8944-053df5a659df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225355593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.225355593
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1435833956
Short name T337
Test name
Test status
Simulation time 183999320 ps
CPU time 2.88 seconds
Started Jun 24 05:54:56 PM PDT 24
Finished Jun 24 05:55:00 PM PDT 24
Peak memory 213500 kb
Host smart-dfdd97ba-6783-4033-a9fb-d99a34fd23ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435833956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1435833956
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3145068840
Short name T321
Test name
Test status
Simulation time 5034004800 ps
CPU time 11.32 seconds
Started Jun 24 05:54:55 PM PDT 24
Finished Jun 24 05:55:07 PM PDT 24
Peak memory 217256 kb
Host smart-d96581ae-5557-4440-999e-ee7ddd5d079e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145068840 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3145068840
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1379069956
Short name T103
Test name
Test status
Simulation time 426727446 ps
CPU time 2.43 seconds
Started Jun 24 05:54:57 PM PDT 24
Finished Jun 24 05:55:00 PM PDT 24
Peak memory 213524 kb
Host smart-ab9cab54-30b2-46f8-89fa-08e1170c556a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379069956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1379069956
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3171495278
Short name T350
Test name
Test status
Simulation time 37686207197 ps
CPU time 46.78 seconds
Started Jun 24 05:54:49 PM PDT 24
Finished Jun 24 05:55:37 PM PDT 24
Peak memory 205272 kb
Host smart-24ef8f7c-4f7e-43bd-8435-c8ffc7b44ab3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171495278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3171495278
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3352530770
Short name T307
Test name
Test status
Simulation time 1344648891 ps
CPU time 4.18 seconds
Started Jun 24 05:54:49 PM PDT 24
Finished Jun 24 05:54:54 PM PDT 24
Peak memory 205144 kb
Host smart-85975a9a-dcfe-4c69-835f-eefe8a01cda8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352530770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3352530770
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3072038376
Short name T280
Test name
Test status
Simulation time 143370294 ps
CPU time 0.74 seconds
Started Jun 24 05:54:51 PM PDT 24
Finished Jun 24 05:54:53 PM PDT 24
Peak memory 205004 kb
Host smart-9493cb0e-4e57-48cf-b3bd-eb9bc6e79124
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072038376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3072038376
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.64937183
Short name T109
Test name
Test status
Simulation time 998502872 ps
CPU time 7.77 seconds
Started Jun 24 05:54:59 PM PDT 24
Finished Jun 24 05:55:09 PM PDT 24
Peak memory 205408 kb
Host smart-947cdf69-e155-4e76-a2a6-bcba686cc20b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64937183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_c
sr_outstanding.64937183
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4006647612
Short name T336
Test name
Test status
Simulation time 199079117 ps
CPU time 2.62 seconds
Started Jun 24 05:54:53 PM PDT 24
Finished Jun 24 05:54:56 PM PDT 24
Peak memory 213544 kb
Host smart-e66ef904-4aff-46b4-aa43-8307d937fd76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006647612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.4006647612
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2159746660
Short name T122
Test name
Test status
Simulation time 5623763641 ps
CPU time 28.52 seconds
Started Jun 24 05:54:52 PM PDT 24
Finished Jun 24 05:55:22 PM PDT 24
Peak memory 213676 kb
Host smart-b0569c30-8a52-45b6-b003-1bc5d1feb2e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159746660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
159746660
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3249838519
Short name T271
Test name
Test status
Simulation time 112975954 ps
CPU time 2.25 seconds
Started Jun 24 05:54:49 PM PDT 24
Finished Jun 24 05:54:52 PM PDT 24
Peak memory 217368 kb
Host smart-6d22c51e-5dce-40aa-919f-096175db8b81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249838519 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3249838519
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.180104614
Short name T301
Test name
Test status
Simulation time 100235782 ps
CPU time 1.75 seconds
Started Jun 24 05:54:52 PM PDT 24
Finished Jun 24 05:54:55 PM PDT 24
Peak memory 213480 kb
Host smart-d9c3135b-14ab-4d2a-85fc-f84aac1c60db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180104614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.180104614
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2240787701
Short name T381
Test name
Test status
Simulation time 76342635 ps
CPU time 0.75 seconds
Started Jun 24 05:54:51 PM PDT 24
Finished Jun 24 05:54:52 PM PDT 24
Peak memory 205008 kb
Host smart-0bc45fe4-b886-498c-95d9-bc33fa1e2a83
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240787701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2240787701
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.108074334
Short name T386
Test name
Test status
Simulation time 2972795912 ps
CPU time 1.52 seconds
Started Jun 24 05:54:56 PM PDT 24
Finished Jun 24 05:54:58 PM PDT 24
Peak memory 205280 kb
Host smart-c389be2e-ea9e-4a8d-847c-163ea436ff18
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108074334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.108074334
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1032627299
Short name T358
Test name
Test status
Simulation time 436886465 ps
CPU time 1.02 seconds
Started Jun 24 05:54:57 PM PDT 24
Finished Jun 24 05:54:59 PM PDT 24
Peak memory 205000 kb
Host smart-8c100dd0-2ecd-4395-8e50-42ad36348b5c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032627299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1032627299
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1630194397
Short name T344
Test name
Test status
Simulation time 359038479 ps
CPU time 6.87 seconds
Started Jun 24 05:54:51 PM PDT 24
Finished Jun 24 05:54:59 PM PDT 24
Peak memory 205300 kb
Host smart-040164ab-c43d-46cd-a1a0-98eb3f867c8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630194397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1630194397
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2287817544
Short name T117
Test name
Test status
Simulation time 232573602 ps
CPU time 3.3 seconds
Started Jun 24 05:54:49 PM PDT 24
Finished Jun 24 05:54:52 PM PDT 24
Peak memory 213532 kb
Host smart-21a012aa-4c39-4bef-b2a1-c9121e8c9ede
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287817544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2287817544
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1565261080
Short name T120
Test name
Test status
Simulation time 1528449724 ps
CPU time 11.7 seconds
Started Jun 24 05:54:52 PM PDT 24
Finished Jun 24 05:55:05 PM PDT 24
Peak memory 213564 kb
Host smart-aa470f55-5ab0-430b-899a-93c110ba959e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565261080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
565261080
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.42193182
Short name T322
Test name
Test status
Simulation time 140219453 ps
CPU time 2.57 seconds
Started Jun 24 05:54:59 PM PDT 24
Finished Jun 24 05:55:03 PM PDT 24
Peak memory 219036 kb
Host smart-752811b3-1b6d-427a-bdc9-d6f4d7fadf39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42193182 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.42193182
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1877913720
Short name T396
Test name
Test status
Simulation time 176736658 ps
CPU time 2.11 seconds
Started Jun 24 05:54:59 PM PDT 24
Finished Jun 24 05:55:01 PM PDT 24
Peak memory 213472 kb
Host smart-a4247075-d0b8-4c14-8a77-0fdada3931b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877913720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1877913720
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3457840611
Short name T289
Test name
Test status
Simulation time 64613976837 ps
CPU time 53.4 seconds
Started Jun 24 05:54:51 PM PDT 24
Finished Jun 24 05:55:45 PM PDT 24
Peak memory 205284 kb
Host smart-82b2d420-88d0-4d42-aa80-1bfe281b69e6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457840611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.3457840611
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.970985639
Short name T294
Test name
Test status
Simulation time 2373497680 ps
CPU time 2.12 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:04 PM PDT 24
Peak memory 205484 kb
Host smart-8e30f861-fa2a-4aa2-b511-c3283b712e2a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970985639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.970985639
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.933795374
Short name T328
Test name
Test status
Simulation time 247514450 ps
CPU time 1.41 seconds
Started Jun 24 05:54:51 PM PDT 24
Finished Jun 24 05:54:53 PM PDT 24
Peak memory 204892 kb
Host smart-b0abd21a-9cb4-4345-8881-3bac26019567
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933795374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.933795374
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1470065765
Short name T100
Test name
Test status
Simulation time 1889303684 ps
CPU time 8.14 seconds
Started Jun 24 05:55:02 PM PDT 24
Finished Jun 24 05:55:13 PM PDT 24
Peak memory 205336 kb
Host smart-d92c655f-2f0a-49de-bb86-c57b87c5fc3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470065765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1470065765
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2328929427
Short name T73
Test name
Test status
Simulation time 2212566930 ps
CPU time 4.24 seconds
Started Jun 24 05:54:59 PM PDT 24
Finished Jun 24 05:55:05 PM PDT 24
Peak memory 213644 kb
Host smart-909b2d56-4cdc-4c1d-ad56-4ba1e7ce41c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328929427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2328929427
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2922901375
Short name T380
Test name
Test status
Simulation time 1968431312 ps
CPU time 9.36 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:12 PM PDT 24
Peak memory 213560 kb
Host smart-2a02cc4c-7f24-4790-b76d-858e62f26cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922901375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
922901375
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2632841877
Short name T400
Test name
Test status
Simulation time 1983742883 ps
CPU time 6.53 seconds
Started Jun 24 05:55:01 PM PDT 24
Finished Jun 24 05:55:09 PM PDT 24
Peak memory 221872 kb
Host smart-a040db60-199a-4ced-b666-b6dd66d1c679
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632841877 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2632841877
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4165040590
Short name T82
Test name
Test status
Simulation time 83751726 ps
CPU time 2.18 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:04 PM PDT 24
Peak memory 213484 kb
Host smart-1cbdc840-ef27-4910-b467-291da2eb1390
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165040590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.4165040590
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.4252379904
Short name T263
Test name
Test status
Simulation time 4059721289 ps
CPU time 5.03 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:08 PM PDT 24
Peak memory 205264 kb
Host smart-8f0d89c6-8009-4f3a-9416-b29ccadee555
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252379904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.4252379904
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1467547444
Short name T317
Test name
Test status
Simulation time 4623158673 ps
CPU time 2.21 seconds
Started Jun 24 05:55:02 PM PDT 24
Finished Jun 24 05:55:06 PM PDT 24
Peak memory 205304 kb
Host smart-2bfd6425-9dc7-4d74-bd06-bf1082d067cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467547444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1467547444
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3551116152
Short name T348
Test name
Test status
Simulation time 182676787 ps
CPU time 0.86 seconds
Started Jun 24 05:54:59 PM PDT 24
Finished Jun 24 05:55:02 PM PDT 24
Peak memory 204996 kb
Host smart-89bc2205-071d-406e-9ffa-a31cb0c64b64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551116152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3551116152
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1254554978
Short name T385
Test name
Test status
Simulation time 119462090 ps
CPU time 3.58 seconds
Started Jun 24 05:55:01 PM PDT 24
Finished Jun 24 05:55:07 PM PDT 24
Peak memory 205332 kb
Host smart-1589eb72-21c7-40ab-8123-d9aaeed7b417
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254554978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1254554978
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3353932991
Short name T290
Test name
Test status
Simulation time 62106756 ps
CPU time 2.59 seconds
Started Jun 24 05:55:01 PM PDT 24
Finished Jun 24 05:55:06 PM PDT 24
Peak memory 213548 kb
Host smart-b2950971-d267-4390-830f-3436d764e2c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353932991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3353932991
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2051753436
Short name T395
Test name
Test status
Simulation time 1180632518 ps
CPU time 16.53 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:19 PM PDT 24
Peak memory 213592 kb
Host smart-573a59ae-c7d2-4ffb-818d-b5265bdb8f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051753436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
051753436
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.493390299
Short name T378
Test name
Test status
Simulation time 1100606871 ps
CPU time 3.06 seconds
Started Jun 24 05:55:01 PM PDT 24
Finished Jun 24 05:55:07 PM PDT 24
Peak memory 213536 kb
Host smart-67763a77-f324-450a-b5cd-826071533a39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493390299 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.493390299
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.294322894
Short name T93
Test name
Test status
Simulation time 233083731 ps
CPU time 2.69 seconds
Started Jun 24 05:55:01 PM PDT 24
Finished Jun 24 05:55:06 PM PDT 24
Peak memory 213544 kb
Host smart-bbea92f5-87d0-425a-be1f-5526c6598683
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294322894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.294322894
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.366781189
Short name T264
Test name
Test status
Simulation time 20865661394 ps
CPU time 58.82 seconds
Started Jun 24 05:54:59 PM PDT 24
Finished Jun 24 05:56:00 PM PDT 24
Peak memory 205272 kb
Host smart-a8b2f64a-bf9d-4d4a-a582-f114e074327d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366781189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
rv_dm_jtag_dmi_csr_bit_bash.366781189
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4077951646
Short name T339
Test name
Test status
Simulation time 1936997219 ps
CPU time 4.16 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:07 PM PDT 24
Peak memory 205452 kb
Host smart-9bdbceca-957c-4ca3-9862-d441f536b8d9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077951646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
4077951646
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1530598692
Short name T286
Test name
Test status
Simulation time 232472726 ps
CPU time 0.92 seconds
Started Jun 24 05:55:03 PM PDT 24
Finished Jun 24 05:55:07 PM PDT 24
Peak memory 204896 kb
Host smart-5c3438c7-0825-4e43-9e07-1a897ee1908d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530598692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1530598692
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1033472684
Short name T92
Test name
Test status
Simulation time 680544536 ps
CPU time 4.31 seconds
Started Jun 24 05:54:59 PM PDT 24
Finished Jun 24 05:55:04 PM PDT 24
Peak memory 205280 kb
Host smart-caee7af9-576e-4ef0-a132-b9bbd3c7b08b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033472684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1033472684
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3284531774
Short name T375
Test name
Test status
Simulation time 193314304 ps
CPU time 5.39 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:07 PM PDT 24
Peak memory 213596 kb
Host smart-37247f8a-b84f-4496-b679-f31b9f10d999
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284531774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3284531774
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3731265118
Short name T125
Test name
Test status
Simulation time 2957283717 ps
CPU time 11.24 seconds
Started Jun 24 05:55:02 PM PDT 24
Finished Jun 24 05:55:16 PM PDT 24
Peak memory 213572 kb
Host smart-91da3035-20fa-40da-b6dc-6cdbb1b9954d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731265118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
731265118
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2937119327
Short name T45
Test name
Test status
Simulation time 4199467266 ps
CPU time 6.55 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:09 PM PDT 24
Peak memory 218376 kb
Host smart-a88e4697-8668-4651-bacf-4cb681774e47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937119327 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2937119327
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2921907526
Short name T80
Test name
Test status
Simulation time 164418635 ps
CPU time 2.52 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:05 PM PDT 24
Peak memory 213512 kb
Host smart-2ed1b857-1468-4ff4-b31a-5a315e8eb9a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921907526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2921907526
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3114025961
Short name T326
Test name
Test status
Simulation time 51782601143 ps
CPU time 141.93 seconds
Started Jun 24 05:55:01 PM PDT 24
Finished Jun 24 05:57:25 PM PDT 24
Peak memory 205308 kb
Host smart-e1f0af94-9b95-48fd-8609-8b0eb38f5087
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114025961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.3114025961
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2295171412
Short name T260
Test name
Test status
Simulation time 2341977289 ps
CPU time 2.36 seconds
Started Jun 24 05:55:01 PM PDT 24
Finished Jun 24 05:55:06 PM PDT 24
Peak memory 205300 kb
Host smart-d6f7adea-ddf6-4429-8a12-e6fa1d5e09ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295171412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2295171412
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1499891826
Short name T278
Test name
Test status
Simulation time 500581637 ps
CPU time 1.31 seconds
Started Jun 24 05:55:02 PM PDT 24
Finished Jun 24 05:55:06 PM PDT 24
Peak memory 204948 kb
Host smart-933e7999-c918-4e8a-abf7-f25a9ed04036
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499891826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1499891826
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.946266332
Short name T345
Test name
Test status
Simulation time 964128682 ps
CPU time 7.83 seconds
Started Jun 24 05:55:03 PM PDT 24
Finished Jun 24 05:55:14 PM PDT 24
Peak memory 205384 kb
Host smart-ba934027-1230-48f4-8786-f572884e7db8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946266332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.946266332
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2380206495
Short name T115
Test name
Test status
Simulation time 514902893 ps
CPU time 6.25 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:08 PM PDT 24
Peak memory 213516 kb
Host smart-0c1edff8-ab5e-4c72-a795-73f5ad39e20a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380206495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2380206495
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2309777810
Short name T338
Test name
Test status
Simulation time 2233759480 ps
CPU time 9.93 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:12 PM PDT 24
Peak memory 221804 kb
Host smart-b2a7377e-f907-42af-a5db-792c9358a7de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309777810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
309777810
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3216674347
Short name T116
Test name
Test status
Simulation time 2562769881 ps
CPU time 8.06 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:11 PM PDT 24
Peak memory 221896 kb
Host smart-e42797a6-e1fc-47bf-b7ab-b69143a5305b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216674347 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3216674347
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1109794228
Short name T48
Test name
Test status
Simulation time 188507656 ps
CPU time 2.12 seconds
Started Jun 24 05:55:02 PM PDT 24
Finished Jun 24 05:55:07 PM PDT 24
Peak memory 213512 kb
Host smart-d12a15b9-ee2e-4deb-84e6-8596b7801c33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109794228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1109794228
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2820720314
Short name T268
Test name
Test status
Simulation time 10489263812 ps
CPU time 30.8 seconds
Started Jun 24 05:55:02 PM PDT 24
Finished Jun 24 05:55:35 PM PDT 24
Peak memory 205260 kb
Host smart-c1c8f431-cefe-4072-ae94-cb0059809a28
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820720314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2820720314
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3918150973
Short name T293
Test name
Test status
Simulation time 1260436634 ps
CPU time 1.16 seconds
Started Jun 24 05:54:59 PM PDT 24
Finished Jun 24 05:55:01 PM PDT 24
Peak memory 205244 kb
Host smart-f73283c8-fb18-4470-8d12-e871b25245f9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918150973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3918150973
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1672504127
Short name T310
Test name
Test status
Simulation time 480762909 ps
CPU time 0.78 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:03 PM PDT 24
Peak memory 205000 kb
Host smart-95649383-9e9c-4dc3-ab91-7800b65a6726
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672504127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1672504127
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3584918548
Short name T368
Test name
Test status
Simulation time 331022675 ps
CPU time 4.48 seconds
Started Jun 24 05:55:03 PM PDT 24
Finished Jun 24 05:55:10 PM PDT 24
Peak memory 205324 kb
Host smart-56554cae-afd8-4a4b-aec7-a1b3071ad70a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584918548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3584918548
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2316964456
Short name T324
Test name
Test status
Simulation time 394298856 ps
CPU time 2.8 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:05 PM PDT 24
Peak memory 213504 kb
Host smart-dca1104a-9723-4eef-a535-18dc12098e34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316964456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2316964456
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2531573606
Short name T275
Test name
Test status
Simulation time 2963194714 ps
CPU time 2.99 seconds
Started Jun 24 05:55:01 PM PDT 24
Finished Jun 24 05:55:06 PM PDT 24
Peak memory 215384 kb
Host smart-d7a72a22-63e0-47fd-9f80-06ac6de26b5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531573606 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2531573606
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2898336150
Short name T97
Test name
Test status
Simulation time 154520111 ps
CPU time 2.56 seconds
Started Jun 24 05:55:03 PM PDT 24
Finished Jun 24 05:55:08 PM PDT 24
Peak memory 213588 kb
Host smart-88957bf9-c334-484f-b9a9-bb488137521d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898336150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2898336150
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.4042895283
Short name T340
Test name
Test status
Simulation time 18679604590 ps
CPU time 44.8 seconds
Started Jun 24 05:55:02 PM PDT 24
Finished Jun 24 05:55:50 PM PDT 24
Peak memory 205244 kb
Host smart-9f8c9212-ba2a-4fb5-9462-ef045f35917e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042895283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.4042895283
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4278331
Short name T393
Test name
Test status
Simulation time 5472661930 ps
CPU time 8.55 seconds
Started Jun 24 05:55:04 PM PDT 24
Finished Jun 24 05:55:16 PM PDT 24
Peak memory 205316 kb
Host smart-70e5a2d1-9c7d-4a54-a2ba-40d3695acbdc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.4278331
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1462700302
Short name T383
Test name
Test status
Simulation time 224025155 ps
CPU time 0.96 seconds
Started Jun 24 05:55:03 PM PDT 24
Finished Jun 24 05:55:07 PM PDT 24
Peak memory 204980 kb
Host smart-f5211bd5-3280-4a7e-b864-2892db47203f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462700302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1462700302
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1938314888
Short name T76
Test name
Test status
Simulation time 734132433 ps
CPU time 6.66 seconds
Started Jun 24 05:54:59 PM PDT 24
Finished Jun 24 05:55:07 PM PDT 24
Peak memory 205336 kb
Host smart-53c69981-ad02-4609-a606-c448b28eb7b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938314888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1938314888
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3690029828
Short name T333
Test name
Test status
Simulation time 328844826 ps
CPU time 5.42 seconds
Started Jun 24 05:55:02 PM PDT 24
Finished Jun 24 05:55:11 PM PDT 24
Peak memory 213496 kb
Host smart-872146ef-39f8-415e-8e12-1d5933dcd38f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690029828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3690029828
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2544869454
Short name T292
Test name
Test status
Simulation time 7332996725 ps
CPU time 10.19 seconds
Started Jun 24 05:55:04 PM PDT 24
Finished Jun 24 05:55:17 PM PDT 24
Peak memory 221784 kb
Host smart-6bc7d4db-0016-4c58-956f-ab82ab820d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544869454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
544869454
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2984166995
Short name T101
Test name
Test status
Simulation time 3713899320 ps
CPU time 36.71 seconds
Started Jun 24 05:54:33 PM PDT 24
Finished Jun 24 05:55:12 PM PDT 24
Peak memory 213608 kb
Host smart-2fbda43b-6d5a-4eb3-94eb-5ddfff01ef1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984166995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2984166995
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2885497850
Short name T359
Test name
Test status
Simulation time 178164394 ps
CPU time 2.55 seconds
Started Jun 24 05:54:31 PM PDT 24
Finished Jun 24 05:54:35 PM PDT 24
Peak memory 213692 kb
Host smart-006145d8-0dbb-4826-95f7-04eb4638536e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885497850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2885497850
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3426517887
Short name T85
Test name
Test status
Simulation time 2006825213 ps
CPU time 7.83 seconds
Started Jun 24 05:54:33 PM PDT 24
Finished Jun 24 05:54:43 PM PDT 24
Peak memory 219448 kb
Host smart-01810a1f-c9a4-49e9-a8d2-2a8e9e781bcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426517887 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3426517887
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.830488024
Short name T105
Test name
Test status
Simulation time 128013130 ps
CPU time 2.5 seconds
Started Jun 24 05:54:33 PM PDT 24
Finished Jun 24 05:54:39 PM PDT 24
Peak memory 213808 kb
Host smart-3769f063-11ee-4e20-b14d-c20f9f1e56e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830488024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.830488024
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.714648613
Short name T357
Test name
Test status
Simulation time 200962826957 ps
CPU time 519.96 seconds
Started Jun 24 05:54:32 PM PDT 24
Finished Jun 24 06:03:15 PM PDT 24
Peak memory 209716 kb
Host smart-3dab571a-5d4e-4b64-af05-5952ebcd368b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714648613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.714648613
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.764401995
Short name T342
Test name
Test status
Simulation time 12395667094 ps
CPU time 6.83 seconds
Started Jun 24 05:54:32 PM PDT 24
Finished Jun 24 05:54:42 PM PDT 24
Peak memory 205284 kb
Host smart-7e446b9b-e139-4287-bd9d-3d2efca92cb4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764401995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r
v_dm_jtag_dmi_csr_bit_bash.764401995
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3145120708
Short name T87
Test name
Test status
Simulation time 4670556003 ps
CPU time 12.4 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:58 PM PDT 24
Peak memory 205568 kb
Host smart-14d88549-00ce-4adf-9931-5bd8ac41fb60
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145120708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3145120708
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2766442690
Short name T277
Test name
Test status
Simulation time 4265319777 ps
CPU time 9.8 seconds
Started Jun 24 05:54:32 PM PDT 24
Finished Jun 24 05:54:44 PM PDT 24
Peak memory 205296 kb
Host smart-8e7c08f7-1c21-4adf-8b6d-fd89284420ef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766442690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
766442690
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2849642080
Short name T62
Test name
Test status
Simulation time 525309671 ps
CPU time 1.05 seconds
Started Jun 24 05:54:32 PM PDT 24
Finished Jun 24 05:54:36 PM PDT 24
Peak memory 204992 kb
Host smart-b8f04078-92b1-45cf-b0fa-8f42a285cddc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849642080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2849642080
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.385467718
Short name T332
Test name
Test status
Simulation time 22343185746 ps
CPU time 59.71 seconds
Started Jun 24 05:54:33 PM PDT 24
Finished Jun 24 05:55:35 PM PDT 24
Peak memory 204616 kb
Host smart-5ddc0d83-73bc-4071-9123-c43fb6320219
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385467718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.385467718
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.4163075958
Short name T343
Test name
Test status
Simulation time 201815302 ps
CPU time 1.01 seconds
Started Jun 24 05:54:30 PM PDT 24
Finished Jun 24 05:54:32 PM PDT 24
Peak memory 204972 kb
Host smart-487b51b7-d89b-4915-89ba-4d083ac2f95a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163075958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.4163075958
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1116341212
Short name T273
Test name
Test status
Simulation time 329027689 ps
CPU time 1.62 seconds
Started Jun 24 05:54:43 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 205220 kb
Host smart-3eb3cc0e-158a-4aed-bff0-0f843105ef6c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116341212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
116341212
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2735185578
Short name T265
Test name
Test status
Simulation time 47605807 ps
CPU time 0.66 seconds
Started Jun 24 05:54:32 PM PDT 24
Finished Jun 24 05:54:35 PM PDT 24
Peak memory 204936 kb
Host smart-99a48b9e-fc4c-44b7-ae4b-0b8cee4cefac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735185578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2735185578
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4220043269
Short name T303
Test name
Test status
Simulation time 117593697 ps
CPU time 0.82 seconds
Started Jun 24 05:54:32 PM PDT 24
Finished Jun 24 05:54:36 PM PDT 24
Peak memory 205008 kb
Host smart-a9a14439-50e5-4125-b4d7-f04319ec024c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220043269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.4220043269
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.4066550180
Short name T96
Test name
Test status
Simulation time 2204052955 ps
CPU time 8.36 seconds
Started Jun 24 05:54:32 PM PDT 24
Finished Jun 24 05:54:43 PM PDT 24
Peak memory 205400 kb
Host smart-81f9c2bb-6c4e-4714-a324-3dd967c85838
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066550180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.4066550180
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.4127418169
Short name T397
Test name
Test status
Simulation time 2830213482 ps
CPU time 4.9 seconds
Started Jun 24 05:54:32 PM PDT 24
Finished Jun 24 05:54:39 PM PDT 24
Peak memory 213620 kb
Host smart-00fb5bb3-cac0-4ccd-ac89-f276da9d02e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127418169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.4127418169
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2421907349
Short name T84
Test name
Test status
Simulation time 4381733224 ps
CPU time 9.78 seconds
Started Jun 24 05:54:31 PM PDT 24
Finished Jun 24 05:54:44 PM PDT 24
Peak memory 213600 kb
Host smart-ba17c890-1bcc-4102-95ac-9cca4b46f04e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421907349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2421907349
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1146635193
Short name T291
Test name
Test status
Simulation time 593549731 ps
CPU time 27.81 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:55:13 PM PDT 24
Peak memory 205580 kb
Host smart-e22b21f3-f922-4c1e-a2fc-0be43e04ef95
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146635193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1146635193
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2038190336
Short name T102
Test name
Test status
Simulation time 3053206247 ps
CPU time 26.69 seconds
Started Jun 24 05:54:38 PM PDT 24
Finished Jun 24 05:55:05 PM PDT 24
Peak memory 213636 kb
Host smart-1a720e17-1d2d-4bbd-8587-c583d5ec272b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038190336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2038190336
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.614396915
Short name T401
Test name
Test status
Simulation time 184365265 ps
CPU time 1.73 seconds
Started Jun 24 05:54:34 PM PDT 24
Finished Jun 24 05:54:38 PM PDT 24
Peak memory 213588 kb
Host smart-73d9ef31-5026-44f5-ad43-0a3b0ab05502
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614396915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.614396915
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.234390940
Short name T71
Test name
Test status
Simulation time 4673581589 ps
CPU time 6.94 seconds
Started Jun 24 05:54:43 PM PDT 24
Finished Jun 24 05:54:52 PM PDT 24
Peak memory 219576 kb
Host smart-0a77dcd4-038f-495d-a098-115ee67bbeda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234390940 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.234390940
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1748580828
Short name T394
Test name
Test status
Simulation time 242062978 ps
CPU time 2.51 seconds
Started Jun 24 05:54:33 PM PDT 24
Finished Jun 24 05:54:38 PM PDT 24
Peak memory 213556 kb
Host smart-6eddce4c-cc3a-4962-a3b9-3a186f5cdef5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748580828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1748580828
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1920975089
Short name T262
Test name
Test status
Simulation time 114001806312 ps
CPU time 59.13 seconds
Started Jun 24 05:54:43 PM PDT 24
Finished Jun 24 05:55:45 PM PDT 24
Peak memory 205504 kb
Host smart-c185578d-8f05-444e-8ea7-e3fe04be8dcf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920975089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1920975089
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1963754834
Short name T316
Test name
Test status
Simulation time 84560396732 ps
CPU time 78.39 seconds
Started Jun 24 05:54:34 PM PDT 24
Finished Jun 24 05:55:55 PM PDT 24
Peak memory 205304 kb
Host smart-ce1d3054-8c47-4a65-a00f-e8b5244fa42d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963754834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.1963754834
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.627278834
Short name T90
Test name
Test status
Simulation time 1669134125 ps
CPU time 4.96 seconds
Started Jun 24 05:54:36 PM PDT 24
Finished Jun 24 05:54:42 PM PDT 24
Peak memory 205336 kb
Host smart-38335dbf-b609-447d-96e9-f21634f8f9f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627278834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.627278834
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2226020455
Short name T382
Test name
Test status
Simulation time 1748380961 ps
CPU time 2.11 seconds
Started Jun 24 05:54:34 PM PDT 24
Finished Jun 24 05:54:38 PM PDT 24
Peak memory 205420 kb
Host smart-81c5456c-8757-4867-b7f1-d1f3c33fbeff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226020455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
226020455
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4098191114
Short name T363
Test name
Test status
Simulation time 1219694127 ps
CPU time 4.05 seconds
Started Jun 24 05:54:30 PM PDT 24
Finished Jun 24 05:54:36 PM PDT 24
Peak memory 205008 kb
Host smart-50ffaabb-50ba-49e7-a402-6f3c57528664
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098191114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.4098191114
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3701474228
Short name T267
Test name
Test status
Simulation time 3769564552 ps
CPU time 11.17 seconds
Started Jun 24 05:54:33 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 205256 kb
Host smart-4fb2ce1e-3edd-406a-834d-7dc55edc3934
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701474228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3701474228
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.442053546
Short name T279
Test name
Test status
Simulation time 159239831 ps
CPU time 1.07 seconds
Started Jun 24 05:54:32 PM PDT 24
Finished Jun 24 05:54:36 PM PDT 24
Peak memory 204992 kb
Host smart-efffbcf5-4595-4d12-b17b-8fc830891c7c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442053546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.442053546
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1410189545
Short name T387
Test name
Test status
Simulation time 262704603 ps
CPU time 1.36 seconds
Started Jun 24 05:54:32 PM PDT 24
Finished Jun 24 05:54:36 PM PDT 24
Peak memory 204988 kb
Host smart-05f88e5c-80cc-4c9f-8826-69fb4cd6e8ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410189545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
410189545
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.527059988
Short name T330
Test name
Test status
Simulation time 134669525 ps
CPU time 0.76 seconds
Started Jun 24 05:54:33 PM PDT 24
Finished Jun 24 05:54:36 PM PDT 24
Peak memory 204952 kb
Host smart-dc7e37b6-8efd-4ff3-8eec-d44f7fc8a333
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527059988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.527059988
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2305786819
Short name T299
Test name
Test status
Simulation time 165430298 ps
CPU time 1.17 seconds
Started Jun 24 05:54:35 PM PDT 24
Finished Jun 24 05:54:38 PM PDT 24
Peak memory 205008 kb
Host smart-84984988-e05f-4d46-bfbe-01b46da4185d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305786819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2305786819
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1906879105
Short name T374
Test name
Test status
Simulation time 589770164 ps
CPU time 7.84 seconds
Started Jun 24 05:54:37 PM PDT 24
Finished Jun 24 05:54:45 PM PDT 24
Peak memory 205328 kb
Host smart-db46b4f3-13fb-4a6d-9d52-cb3c2e0b11f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906879105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1906879105
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3587277329
Short name T314
Test name
Test status
Simulation time 178324087 ps
CPU time 2.65 seconds
Started Jun 24 05:54:35 PM PDT 24
Finished Jun 24 05:54:40 PM PDT 24
Peak memory 213536 kb
Host smart-8cd2a0b0-48ca-46bb-983c-19bda90b54da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587277329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3587277329
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1645181703
Short name T392
Test name
Test status
Simulation time 1590754521 ps
CPU time 10.55 seconds
Started Jun 24 05:54:33 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 213548 kb
Host smart-61a231c4-624f-43ae-adcc-96116b0f20fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645181703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1645181703
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1612887530
Short name T399
Test name
Test status
Simulation time 15629076034 ps
CPU time 77.93 seconds
Started Jun 24 05:54:41 PM PDT 24
Finished Jun 24 05:56:00 PM PDT 24
Peak memory 213596 kb
Host smart-968b6fcc-12ab-46a9-bcc8-8cb039409526
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612887530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1612887530
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1006597490
Short name T403
Test name
Test status
Simulation time 5133992813 ps
CPU time 66.19 seconds
Started Jun 24 05:54:39 PM PDT 24
Finished Jun 24 05:55:46 PM PDT 24
Peak memory 213616 kb
Host smart-cd854471-7679-4018-8f27-25334ece5085
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006597490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1006597490
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1253507533
Short name T272
Test name
Test status
Simulation time 624066974 ps
CPU time 2.45 seconds
Started Jun 24 05:54:43 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 213620 kb
Host smart-d7a4959d-d793-4905-b12d-a2754be8d931
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253507533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1253507533
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.564855709
Short name T389
Test name
Test status
Simulation time 4960984733 ps
CPU time 9.26 seconds
Started Jun 24 05:54:41 PM PDT 24
Finished Jun 24 05:54:51 PM PDT 24
Peak memory 221628 kb
Host smart-f5d6f2ca-ba10-4696-9d60-6e7edf2307d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564855709 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.564855709
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4194202322
Short name T108
Test name
Test status
Simulation time 83569542 ps
CPU time 1.48 seconds
Started Jun 24 05:54:45 PM PDT 24
Finished Jun 24 05:54:48 PM PDT 24
Peak memory 213456 kb
Host smart-cac98f2c-3b25-455d-8d8f-33ea5c1cc762
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194202322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.4194202322
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3466348122
Short name T323
Test name
Test status
Simulation time 30203448520 ps
CPU time 28.57 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:55:15 PM PDT 24
Peak memory 204784 kb
Host smart-bf790f62-085c-4612-96f9-6313d49da75d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466348122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.3466348122
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4038979924
Short name T285
Test name
Test status
Simulation time 6954782582 ps
CPU time 7.29 seconds
Started Jun 24 05:54:41 PM PDT 24
Finished Jun 24 05:54:50 PM PDT 24
Peak memory 205508 kb
Host smart-b534862b-7cfe-4b1a-8bcd-ae2490b7bbe0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038979924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.4038979924
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2916304549
Short name T91
Test name
Test status
Simulation time 3979758305 ps
CPU time 12 seconds
Started Jun 24 05:54:42 PM PDT 24
Finished Jun 24 05:54:55 PM PDT 24
Peak memory 205344 kb
Host smart-b10b5681-e49e-474e-8a49-214b3bd01432
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916304549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2916304549
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4085183922
Short name T297
Test name
Test status
Simulation time 14608120035 ps
CPU time 39.61 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:55:26 PM PDT 24
Peak memory 205252 kb
Host smart-f62002a1-916f-4231-8435-249b9700edac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085183922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.4
085183922
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3172577796
Short name T376
Test name
Test status
Simulation time 1829451672 ps
CPU time 2.19 seconds
Started Jun 24 05:54:45 PM PDT 24
Finished Jun 24 05:54:49 PM PDT 24
Peak memory 205004 kb
Host smart-433912fd-ea9d-4300-b0b5-3daf5d31b755
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172577796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3172577796
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.937319384
Short name T288
Test name
Test status
Simulation time 11227113831 ps
CPU time 15.21 seconds
Started Jun 24 05:54:43 PM PDT 24
Finished Jun 24 05:54:59 PM PDT 24
Peak memory 205240 kb
Host smart-d4d06da9-1dbd-453a-afa5-890f9a2b6d5b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937319384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.937319384
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1143611759
Short name T353
Test name
Test status
Simulation time 166364885 ps
CPU time 1.04 seconds
Started Jun 24 05:54:41 PM PDT 24
Finished Jun 24 05:54:43 PM PDT 24
Peak memory 205000 kb
Host smart-f2557aa0-db21-4d0e-a223-cdb35e808608
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143611759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1143611759
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2424590993
Short name T373
Test name
Test status
Simulation time 609570577 ps
CPU time 1.1 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 204996 kb
Host smart-29d1bffc-546d-4032-a7a5-8cf3c51487c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424590993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
424590993
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2413455556
Short name T369
Test name
Test status
Simulation time 82781432 ps
CPU time 0.82 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 204912 kb
Host smart-02fd2994-cec6-46a5-923b-94c22afc0b0f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413455556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2413455556
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3474658709
Short name T349
Test name
Test status
Simulation time 79846422 ps
CPU time 0.68 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 205012 kb
Host smart-45d8219d-c482-4597-a07f-c15c3de6c4fc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474658709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3474658709
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3216222785
Short name T98
Test name
Test status
Simulation time 417884119 ps
CPU time 7.58 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:54 PM PDT 24
Peak memory 205332 kb
Host smart-4b598685-0565-4555-ba32-4b431975834a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216222785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3216222785
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4202865754
Short name T372
Test name
Test status
Simulation time 135762259 ps
CPU time 1.92 seconds
Started Jun 24 05:54:45 PM PDT 24
Finished Jun 24 05:54:49 PM PDT 24
Peak memory 213536 kb
Host smart-91e266a1-9da0-4b88-a357-e05462dcb844
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202865754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.4202865754
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.787950268
Short name T365
Test name
Test status
Simulation time 3310009738 ps
CPU time 5.09 seconds
Started Jun 24 05:54:41 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 220252 kb
Host smart-6e38821e-2089-4dd5-afb6-95843af27f1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787950268 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.787950268
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3808787619
Short name T104
Test name
Test status
Simulation time 90360757 ps
CPU time 2.16 seconds
Started Jun 24 05:54:42 PM PDT 24
Finished Jun 24 05:54:45 PM PDT 24
Peak memory 213488 kb
Host smart-73a75bff-4451-4a1f-8f3b-089c71f8434d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808787619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3808787619
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.2601184970
Short name T261
Test name
Test status
Simulation time 4821816507 ps
CPU time 4.57 seconds
Started Jun 24 05:54:43 PM PDT 24
Finished Jun 24 05:54:49 PM PDT 24
Peak memory 205248 kb
Host smart-6d30207e-21a5-4986-9f94-d9388a857100
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601184970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.2601184970
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1532364877
Short name T304
Test name
Test status
Simulation time 1938354531 ps
CPU time 2.51 seconds
Started Jun 24 05:54:45 PM PDT 24
Finished Jun 24 05:54:49 PM PDT 24
Peak memory 205196 kb
Host smart-419d5ec8-ebd5-4811-b637-8525de78dbba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532364877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
532364877
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1060456157
Short name T320
Test name
Test status
Simulation time 186893566 ps
CPU time 0.81 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 204968 kb
Host smart-8ee78ad4-2ac0-4e9c-8178-7cfc1f1971de
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060456157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
060456157
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1786897264
Short name T49
Test name
Test status
Simulation time 1209601260 ps
CPU time 4.28 seconds
Started Jun 24 05:54:42 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 205340 kb
Host smart-1ae5f0eb-73a3-4e11-8517-109bf61734c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786897264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1786897264
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3867815628
Short name T75
Test name
Test status
Simulation time 224871776 ps
CPU time 3.73 seconds
Started Jun 24 05:54:42 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 213536 kb
Host smart-33dc1206-7f07-4334-8ba9-8e78c82236ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867815628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3867815628
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3710511890
Short name T119
Test name
Test status
Simulation time 2846454185 ps
CPU time 9.34 seconds
Started Jun 24 05:54:45 PM PDT 24
Finished Jun 24 05:54:56 PM PDT 24
Peak memory 213672 kb
Host smart-8c64a319-a69b-43e5-84ed-eadf812a17bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710511890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3710511890
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.866417672
Short name T351
Test name
Test status
Simulation time 195937222 ps
CPU time 4.22 seconds
Started Jun 24 05:54:42 PM PDT 24
Finished Jun 24 05:54:48 PM PDT 24
Peak memory 219568 kb
Host smart-d909181b-727f-4de5-9a3c-69dccc2b208a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866417672 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.866417672
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1717262040
Short name T79
Test name
Test status
Simulation time 204555081 ps
CPU time 1.77 seconds
Started Jun 24 05:54:40 PM PDT 24
Finished Jun 24 05:54:43 PM PDT 24
Peak memory 213456 kb
Host smart-a2d8bcf8-f105-42c9-b327-ca7b23088816
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717262040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1717262040
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1600557950
Short name T384
Test name
Test status
Simulation time 18169108780 ps
CPU time 9.63 seconds
Started Jun 24 05:54:42 PM PDT 24
Finished Jun 24 05:54:53 PM PDT 24
Peak memory 205304 kb
Host smart-4730c44e-addc-42f4-b0de-bb2bdeb6c60a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600557950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.1600557950
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3091974697
Short name T259
Test name
Test status
Simulation time 14810269546 ps
CPU time 28.33 seconds
Started Jun 24 05:54:42 PM PDT 24
Finished Jun 24 05:55:11 PM PDT 24
Peak memory 205320 kb
Host smart-14d1ed1c-4fa9-43cb-9722-5b973de68e1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091974697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
091974697
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2215798205
Short name T388
Test name
Test status
Simulation time 213088494 ps
CPU time 1.2 seconds
Started Jun 24 05:54:41 PM PDT 24
Finished Jun 24 05:54:43 PM PDT 24
Peak memory 205000 kb
Host smart-a17f3cfa-4472-461a-bc87-6cae2b09267a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215798205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
215798205
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.732283891
Short name T95
Test name
Test status
Simulation time 391075078 ps
CPU time 4.5 seconds
Started Jun 24 05:54:40 PM PDT 24
Finished Jun 24 05:54:45 PM PDT 24
Peak memory 205352 kb
Host smart-06f22461-75fc-4c40-b327-f7325ad7a816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732283891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c
sr_outstanding.732283891
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2221942072
Short name T46
Test name
Test status
Simulation time 1208268427 ps
CPU time 17.42 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:55:04 PM PDT 24
Peak memory 213528 kb
Host smart-74680eae-6b7e-40f7-b036-da4c0b40e636
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221942072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2221942072
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.4008202593
Short name T406
Test name
Test status
Simulation time 375406483 ps
CPU time 1.66 seconds
Started Jun 24 05:54:42 PM PDT 24
Finished Jun 24 05:54:45 PM PDT 24
Peak memory 213516 kb
Host smart-ec58be09-59b4-4bd4-af0a-b7368a26ef9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008202593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.4008202593
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.589873049
Short name T402
Test name
Test status
Simulation time 17932321076 ps
CPU time 12.92 seconds
Started Jun 24 05:54:40 PM PDT 24
Finished Jun 24 05:54:54 PM PDT 24
Peak memory 205200 kb
Host smart-0882e7d7-73db-4dae-b02d-072a3d6f1d8c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589873049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r
v_dm_jtag_dmi_csr_bit_bash.589873049
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.408003520
Short name T308
Test name
Test status
Simulation time 3589262508 ps
CPU time 9.67 seconds
Started Jun 24 05:54:43 PM PDT 24
Finished Jun 24 05:54:54 PM PDT 24
Peak memory 205316 kb
Host smart-e337d8d6-c1c4-430b-be3a-cd6f3dfdd1ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408003520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.408003520
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4272822737
Short name T362
Test name
Test status
Simulation time 229427948 ps
CPU time 0.77 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:47 PM PDT 24
Peak memory 204488 kb
Host smart-4f739c70-ec53-434a-84aa-e238117ba765
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272822737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.4
272822737
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2048913988
Short name T296
Test name
Test status
Simulation time 144020927 ps
CPU time 3.72 seconds
Started Jun 24 05:54:57 PM PDT 24
Finished Jun 24 05:55:01 PM PDT 24
Peak memory 205344 kb
Host smart-93f13e88-a25f-4b21-9954-52fb755c0aec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048913988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2048913988
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3637767589
Short name T371
Test name
Test status
Simulation time 207002137 ps
CPU time 2.34 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:48 PM PDT 24
Peak memory 213564 kb
Host smart-5c32cd3e-8452-4c45-a33e-74a6b63e40ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637767589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3637767589
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3562851999
Short name T325
Test name
Test status
Simulation time 1950753949 ps
CPU time 9.02 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:55 PM PDT 24
Peak memory 213512 kb
Host smart-154d7924-9901-445e-b481-871f7348f7e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562851999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3562851999
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3973402246
Short name T69
Test name
Test status
Simulation time 341382054 ps
CPU time 2.52 seconds
Started Jun 24 05:54:55 PM PDT 24
Finished Jun 24 05:54:58 PM PDT 24
Peak memory 221700 kb
Host smart-6dd51fa8-15d6-475f-a175-6649385236ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973402246 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3973402246
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2818249290
Short name T331
Test name
Test status
Simulation time 137731468 ps
CPU time 1.69 seconds
Started Jun 24 05:54:43 PM PDT 24
Finished Jun 24 05:54:46 PM PDT 24
Peak memory 213544 kb
Host smart-3f8195d5-e765-4516-825d-60e7709ea0b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818249290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2818249290
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3690074335
Short name T352
Test name
Test status
Simulation time 15151338031 ps
CPU time 12 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:58 PM PDT 24
Peak memory 205272 kb
Host smart-318fdce9-54cd-4ce7-a554-4fcb7cb9ba63
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690074335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.3690074335
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2770798688
Short name T281
Test name
Test status
Simulation time 8288307652 ps
CPU time 6.77 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:53 PM PDT 24
Peak memory 205188 kb
Host smart-640fb431-e83f-4e6e-b8f1-571e708bf2f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770798688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2
770798688
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2426288673
Short name T266
Test name
Test status
Simulation time 250165976 ps
CPU time 1.07 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:48 PM PDT 24
Peak memory 204996 kb
Host smart-fb7dd274-7820-4ceb-bae2-8285341458b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426288673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
426288673
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2487672469
Short name T390
Test name
Test status
Simulation time 853228631 ps
CPU time 7.59 seconds
Started Jun 24 05:54:50 PM PDT 24
Finished Jun 24 05:54:59 PM PDT 24
Peak memory 205388 kb
Host smart-78d888f3-110d-4b89-8c1d-81edb53df3e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487672469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2487672469
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1268181924
Short name T47
Test name
Test status
Simulation time 131840960 ps
CPU time 2.66 seconds
Started Jun 24 05:54:44 PM PDT 24
Finished Jun 24 05:54:49 PM PDT 24
Peak memory 213424 kb
Host smart-80de2805-6941-4508-8a01-01f62336716f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268181924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1268181924
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3172590345
Short name T361
Test name
Test status
Simulation time 284718327 ps
CPU time 2.64 seconds
Started Jun 24 05:54:51 PM PDT 24
Finished Jun 24 05:54:55 PM PDT 24
Peak memory 213600 kb
Host smart-39bb6ffb-9b0f-4a6f-b2da-6275e8c7a465
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172590345 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3172590345
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3549231332
Short name T391
Test name
Test status
Simulation time 410484276 ps
CPU time 2.44 seconds
Started Jun 24 05:54:56 PM PDT 24
Finished Jun 24 05:55:00 PM PDT 24
Peak memory 213520 kb
Host smart-0338c6ad-40de-456a-a9e0-e82d71ab9f46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549231332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3549231332
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.42404943
Short name T360
Test name
Test status
Simulation time 97238784 ps
CPU time 0.93 seconds
Started Jun 24 05:54:51 PM PDT 24
Finished Jun 24 05:54:53 PM PDT 24
Peak memory 205008 kb
Host smart-8040fa63-518b-4ab1-aaaa-cc40373150c2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42404943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv
_dm_jtag_dmi_csr_bit_bash.42404943
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3999772283
Short name T355
Test name
Test status
Simulation time 2817045382 ps
CPU time 9.03 seconds
Started Jun 24 05:54:59 PM PDT 24
Finished Jun 24 05:55:08 PM PDT 24
Peak memory 205264 kb
Host smart-e7b5b72f-1753-438a-88dc-e7c93433513c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999772283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
999772283
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3403923436
Short name T354
Test name
Test status
Simulation time 355127101 ps
CPU time 1.27 seconds
Started Jun 24 05:54:53 PM PDT 24
Finished Jun 24 05:54:55 PM PDT 24
Peak memory 205012 kb
Host smart-86cd5927-2ffe-472c-8a97-b6ee6553b1b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403923436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
403923436
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3991038951
Short name T111
Test name
Test status
Simulation time 648624490 ps
CPU time 4.48 seconds
Started Jun 24 05:54:50 PM PDT 24
Finished Jun 24 05:54:55 PM PDT 24
Peak memory 205368 kb
Host smart-045dc65a-4bec-4a47-87d6-e1fcd67f38ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991038951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3991038951
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1126276777
Short name T341
Test name
Test status
Simulation time 1151246251 ps
CPU time 2.71 seconds
Started Jun 24 05:55:00 PM PDT 24
Finished Jun 24 05:55:05 PM PDT 24
Peak memory 213784 kb
Host smart-a577b79d-913f-4b44-acf8-a5684e0a145e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126276777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1126276777
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1960393071
Short name T124
Test name
Test status
Simulation time 2490855585 ps
CPU time 14.23 seconds
Started Jun 24 05:54:55 PM PDT 24
Finished Jun 24 05:55:10 PM PDT 24
Peak memory 213568 kb
Host smart-75dde6df-9c43-479f-8758-df0dc6443843
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960393071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1960393071
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2936623355
Short name T240
Test name
Test status
Simulation time 2793206956 ps
CPU time 7.61 seconds
Started Jun 24 06:00:37 PM PDT 24
Finished Jun 24 06:00:46 PM PDT 24
Peak memory 205176 kb
Host smart-d3bc0194-f851-4947-98de-fd74d03aa135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936623355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2936623355
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2828804118
Short name T185
Test name
Test status
Simulation time 6199800457 ps
CPU time 9.6 seconds
Started Jun 24 06:00:39 PM PDT 24
Finished Jun 24 06:00:50 PM PDT 24
Peak memory 213416 kb
Host smart-8790d44f-e359-4689-b0b5-c9b9800fd7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828804118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2828804118
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1819687296
Short name T114
Test name
Test status
Simulation time 8841232826 ps
CPU time 8.05 seconds
Started Jun 24 06:00:46 PM PDT 24
Finished Jun 24 06:00:55 PM PDT 24
Peak memory 204980 kb
Host smart-0737f331-534d-4143-aead-3d936791e14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819687296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1819687296
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1277078801
Short name T129
Test name
Test status
Simulation time 83578628 ps
CPU time 0.79 seconds
Started Jun 24 06:00:47 PM PDT 24
Finished Jun 24 06:00:49 PM PDT 24
Peak memory 204720 kb
Host smart-f4e4f74d-e88f-439c-9c95-64371cc900e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277078801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1277078801
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3996370669
Short name T172
Test name
Test status
Simulation time 2193761324 ps
CPU time 6.85 seconds
Started Jun 24 06:00:37 PM PDT 24
Finished Jun 24 06:00:44 PM PDT 24
Peak memory 205152 kb
Host smart-acf9a784-ce4e-4661-bd45-df319a3f4a52
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3996370669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3996370669
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2077254705
Short name T30
Test name
Test status
Simulation time 2441930584 ps
CPU time 7.04 seconds
Started Jun 24 06:00:48 PM PDT 24
Finished Jun 24 06:00:55 PM PDT 24
Peak memory 204808 kb
Host smart-084b6de5-1de5-4be4-b976-9241cb4acdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077254705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2077254705
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3652355489
Short name T253
Test name
Test status
Simulation time 336010452 ps
CPU time 0.9 seconds
Started Jun 24 06:00:47 PM PDT 24
Finished Jun 24 06:00:49 PM PDT 24
Peak memory 204620 kb
Host smart-066223e9-5f49-495f-b171-8fbd969f1f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652355489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3652355489
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4042279003
Short name T256
Test name
Test status
Simulation time 448338052 ps
CPU time 1.93 seconds
Started Jun 24 06:00:48 PM PDT 24
Finished Jun 24 06:00:50 PM PDT 24
Peak memory 204600 kb
Host smart-8e244b9c-3300-4946-bce5-2d1e6435a335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042279003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.4042279003
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1379687902
Short name T174
Test name
Test status
Simulation time 1981620690 ps
CPU time 5.21 seconds
Started Jun 24 06:00:47 PM PDT 24
Finished Jun 24 06:00:52 PM PDT 24
Peak memory 204616 kb
Host smart-ba8c9505-d0c1-43e3-be07-117c0352ffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379687902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1379687902
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2277451797
Short name T184
Test name
Test status
Simulation time 4659594321 ps
CPU time 12.5 seconds
Started Jun 24 06:00:52 PM PDT 24
Finished Jun 24 06:01:06 PM PDT 24
Peak memory 204684 kb
Host smart-16a451b5-839d-475d-b68d-8da6de93f162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277451797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2277451797
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.517824884
Short name T38
Test name
Test status
Simulation time 587713779 ps
CPU time 0.96 seconds
Started Jun 24 06:00:47 PM PDT 24
Finished Jun 24 06:00:48 PM PDT 24
Peak memory 204856 kb
Host smart-ec19878a-f75d-45ba-a05f-edf52f365b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517824884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.517824884
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1282016149
Short name T230
Test name
Test status
Simulation time 3644343632 ps
CPU time 9.63 seconds
Started Jun 24 06:00:49 PM PDT 24
Finished Jun 24 06:00:59 PM PDT 24
Peak memory 204788 kb
Host smart-c9e52f80-ae89-47ca-81a8-5fa9514bd149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282016149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1282016149
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2337071440
Short name T8
Test name
Test status
Simulation time 2909094593 ps
CPU time 3.5 seconds
Started Jun 24 06:00:47 PM PDT 24
Finished Jun 24 06:00:51 PM PDT 24
Peak memory 204816 kb
Host smart-860e1d28-ada7-45c4-a8ca-a6ea0a9d688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337071440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2337071440
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.933002003
Short name T257
Test name
Test status
Simulation time 921241851 ps
CPU time 3.34 seconds
Started Jun 24 06:00:47 PM PDT 24
Finished Jun 24 06:00:51 PM PDT 24
Peak memory 204724 kb
Host smart-bb710d0a-74b7-4828-811c-52031979d7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933002003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.933002003
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2638681570
Short name T212
Test name
Test status
Simulation time 12692341366 ps
CPU time 33.04 seconds
Started Jun 24 06:00:39 PM PDT 24
Finished Jun 24 06:01:13 PM PDT 24
Peak memory 205256 kb
Host smart-5c22a641-68d2-458e-ac53-a647df97889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638681570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2638681570
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3088568086
Short name T52
Test name
Test status
Simulation time 1674927845 ps
CPU time 3.38 seconds
Started Jun 24 06:00:53 PM PDT 24
Finished Jun 24 06:00:57 PM PDT 24
Peak memory 228712 kb
Host smart-86d37967-573e-4a98-8266-c857c95b8a91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088568086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3088568086
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.252429057
Short name T199
Test name
Test status
Simulation time 753222794 ps
CPU time 2.38 seconds
Started Jun 24 06:00:36 PM PDT 24
Finished Jun 24 06:00:38 PM PDT 24
Peak memory 204628 kb
Host smart-89fa86ba-3663-4e52-9895-b30de19e709a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252429057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.252429057
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.622230230
Short name T32
Test name
Test status
Simulation time 118724992 ps
CPU time 0.77 seconds
Started Jun 24 06:01:23 PM PDT 24
Finished Jun 24 06:01:24 PM PDT 24
Peak memory 204988 kb
Host smart-044c47dd-ce99-48d1-a0b3-c314dc6e5c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622230230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.622230230
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.643323460
Short name T143
Test name
Test status
Simulation time 53207830 ps
CPU time 0.85 seconds
Started Jun 24 06:01:21 PM PDT 24
Finished Jun 24 06:01:23 PM PDT 24
Peak memory 204788 kb
Host smart-24bf4474-1b27-4d16-8bf1-90bd864c7d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643323460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.643323460
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.373679534
Short name T225
Test name
Test status
Simulation time 23110301218 ps
CPU time 6.96 seconds
Started Jun 24 06:01:02 PM PDT 24
Finished Jun 24 06:01:10 PM PDT 24
Peak memory 217288 kb
Host smart-27a823d8-170f-4340-bb10-d1e3ee9ca8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373679534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.373679534
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.3704773555
Short name T197
Test name
Test status
Simulation time 6095670850 ps
CPU time 16.32 seconds
Started Jun 24 06:00:53 PM PDT 24
Finished Jun 24 06:01:10 PM PDT 24
Peak memory 214648 kb
Host smart-12ec6ca7-b64e-41a4-8150-ae29a4a6a6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704773555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3704773555
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2956660084
Short name T16
Test name
Test status
Simulation time 752019845 ps
CPU time 1.01 seconds
Started Jun 24 06:01:03 PM PDT 24
Finished Jun 24 06:01:04 PM PDT 24
Peak memory 204752 kb
Host smart-73aab4e8-a36e-4c71-a3bf-ea6e684fd4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956660084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2956660084
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1169251214
Short name T27
Test name
Test status
Simulation time 1976512824 ps
CPU time 1.45 seconds
Started Jun 24 06:01:03 PM PDT 24
Finished Jun 24 06:01:05 PM PDT 24
Peak memory 204600 kb
Host smart-a05386dc-4ef4-41b8-8a75-5d5d116f426f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169251214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1169251214
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2040180099
Short name T201
Test name
Test status
Simulation time 376469907 ps
CPU time 0.79 seconds
Started Jun 24 06:01:05 PM PDT 24
Finished Jun 24 06:01:07 PM PDT 24
Peak memory 204620 kb
Host smart-7ddcd7f1-0b9e-4a2e-86cd-4d630fd397e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040180099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2040180099
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2198469036
Short name T227
Test name
Test status
Simulation time 3827409053 ps
CPU time 4.79 seconds
Started Jun 24 06:00:58 PM PDT 24
Finished Jun 24 06:01:04 PM PDT 24
Peak memory 205052 kb
Host smart-1e5c7c46-8e67-43dc-8a9d-65c245fbc514
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198469036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2198469036
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3693189892
Short name T68
Test name
Test status
Simulation time 381355925 ps
CPU time 0.99 seconds
Started Jun 24 06:01:03 PM PDT 24
Finished Jun 24 06:01:05 PM PDT 24
Peak memory 204748 kb
Host smart-834036c3-f1b5-44a0-970a-6ef6b2df8bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693189892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3693189892
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.4178987060
Short name T181
Test name
Test status
Simulation time 711714479 ps
CPU time 1.16 seconds
Started Jun 24 06:01:02 PM PDT 24
Finished Jun 24 06:01:04 PM PDT 24
Peak memory 204596 kb
Host smart-1446c1c3-7f0c-44b9-9178-e779a0eba3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178987060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.4178987060
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1979060874
Short name T170
Test name
Test status
Simulation time 705091414 ps
CPU time 1.65 seconds
Started Jun 24 06:01:21 PM PDT 24
Finished Jun 24 06:01:23 PM PDT 24
Peak memory 204604 kb
Host smart-34f97831-8f11-4176-a149-7c13b378c0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979060874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1979060874
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1654670072
Short name T248
Test name
Test status
Simulation time 1170494762 ps
CPU time 1.51 seconds
Started Jun 24 06:01:02 PM PDT 24
Finished Jun 24 06:01:04 PM PDT 24
Peak memory 204612 kb
Host smart-985f3f9a-4370-41cf-a05c-5e73c9d8f848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654670072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1654670072
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3766198558
Short name T220
Test name
Test status
Simulation time 620643631 ps
CPU time 1.34 seconds
Started Jun 24 06:01:22 PM PDT 24
Finished Jun 24 06:01:24 PM PDT 24
Peak memory 204624 kb
Host smart-36b210c9-efbe-41f1-b0c8-ed1316dd7426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766198558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3766198558
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.48847162
Short name T231
Test name
Test status
Simulation time 429218218 ps
CPU time 0.74 seconds
Started Jun 24 06:01:04 PM PDT 24
Finished Jun 24 06:01:05 PM PDT 24
Peak memory 204576 kb
Host smart-d34edff2-07d4-4a02-aa69-0f9203ca9f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48847162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.48847162
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.770529495
Short name T126
Test name
Test status
Simulation time 167381570 ps
CPU time 1.01 seconds
Started Jun 24 06:01:02 PM PDT 24
Finished Jun 24 06:01:04 PM PDT 24
Peak memory 204748 kb
Host smart-e9557412-9a72-4775-b3ff-8ea9749b19f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770529495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.770529495
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.91126642
Short name T131
Test name
Test status
Simulation time 254309529 ps
CPU time 1.09 seconds
Started Jun 24 06:01:03 PM PDT 24
Finished Jun 24 06:01:05 PM PDT 24
Peak memory 204740 kb
Host smart-623b9bae-0c86-4a5e-9833-f14d65043e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91126642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.91126642
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.948561206
Short name T132
Test name
Test status
Simulation time 3518318088 ps
CPU time 1.8 seconds
Started Jun 24 06:01:04 PM PDT 24
Finished Jun 24 06:01:06 PM PDT 24
Peak memory 204956 kb
Host smart-e3b349af-f3d8-4824-b73a-b95ef1c35a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948561206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.948561206
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3428308911
Short name T18
Test name
Test status
Simulation time 295695014 ps
CPU time 0.97 seconds
Started Jun 24 06:01:23 PM PDT 24
Finished Jun 24 06:01:25 PM PDT 24
Peak memory 204984 kb
Host smart-f2850308-492e-451a-9edb-9fdf9fbf6ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428308911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3428308911
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.193511317
Short name T36
Test name
Test status
Simulation time 244448233 ps
CPU time 0.8 seconds
Started Jun 24 06:01:21 PM PDT 24
Finished Jun 24 06:01:22 PM PDT 24
Peak memory 204764 kb
Host smart-febee4a6-22fa-4152-afc3-d0dc2ca60a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193511317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.193511317
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3949412718
Short name T28
Test name
Test status
Simulation time 68445991 ps
CPU time 0.93 seconds
Started Jun 24 06:01:22 PM PDT 24
Finished Jun 24 06:01:23 PM PDT 24
Peak memory 213040 kb
Host smart-b7d002e7-6f10-4261-9bd5-c9c4ed09a5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949412718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3949412718
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3801284396
Short name T11
Test name
Test status
Simulation time 4413376575 ps
CPU time 4.71 seconds
Started Jun 24 06:00:53 PM PDT 24
Finished Jun 24 06:00:59 PM PDT 24
Peak memory 205224 kb
Host smart-b04895cf-5d43-4e44-a8a4-6f228ef8465e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801284396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3801284396
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.123746138
Short name T40
Test name
Test status
Simulation time 331973635 ps
CPU time 1.28 seconds
Started Jun 24 06:01:21 PM PDT 24
Finished Jun 24 06:01:23 PM PDT 24
Peak memory 229044 kb
Host smart-d1f20367-0b29-42eb-a695-72a6fa39c0d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123746138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.123746138
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3108946751
Short name T10
Test name
Test status
Simulation time 2124177746 ps
CPU time 3.21 seconds
Started Jun 24 06:00:52 PM PDT 24
Finished Jun 24 06:00:56 PM PDT 24
Peak memory 204620 kb
Host smart-eb14f00b-b560-4741-959b-273996e9ea5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108946751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3108946751
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.3763110208
Short name T39
Test name
Test status
Simulation time 9911942905 ps
CPU time 7.69 seconds
Started Jun 24 06:01:21 PM PDT 24
Finished Jun 24 06:01:30 PM PDT 24
Peak memory 213260 kb
Host smart-5af738ae-584a-42c3-9645-c82c0129862e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763110208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3763110208
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3721258648
Short name T155
Test name
Test status
Simulation time 77390794 ps
CPU time 0.74 seconds
Started Jun 24 06:01:46 PM PDT 24
Finished Jun 24 06:01:48 PM PDT 24
Peak memory 204800 kb
Host smart-dedfe7e9-6b1e-4555-a70b-d4b1bb41a241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721258648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3721258648
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.4279695120
Short name T187
Test name
Test status
Simulation time 3226172114 ps
CPU time 2.6 seconds
Started Jun 24 06:01:46 PM PDT 24
Finished Jun 24 06:01:50 PM PDT 24
Peak memory 213404 kb
Host smart-678656bc-ea1c-40c2-9016-c406df26335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279695120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.4279695120
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1853413247
Short name T190
Test name
Test status
Simulation time 8607985006 ps
CPU time 11.87 seconds
Started Jun 24 06:01:46 PM PDT 24
Finished Jun 24 06:02:00 PM PDT 24
Peak memory 205220 kb
Host smart-5921efa6-17dc-4e25-9178-cb105890985f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853413247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1853413247
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.821185103
Short name T226
Test name
Test status
Simulation time 2068164276 ps
CPU time 2.02 seconds
Started Jun 24 06:01:44 PM PDT 24
Finished Jun 24 06:01:46 PM PDT 24
Peak memory 205112 kb
Host smart-81ca92b5-6a31-4fb7-b0ec-46193933b9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821185103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.821185103
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.672203337
Short name T164
Test name
Test status
Simulation time 128331191 ps
CPU time 0.79 seconds
Started Jun 24 06:01:46 PM PDT 24
Finished Jun 24 06:01:48 PM PDT 24
Peak memory 204700 kb
Host smart-ec34282d-77da-43a5-9433-b7236b90af8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672203337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.672203337
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3905591288
Short name T57
Test name
Test status
Simulation time 66234900459 ps
CPU time 46.21 seconds
Started Jun 24 06:01:42 PM PDT 24
Finished Jun 24 06:02:29 PM PDT 24
Peak memory 213388 kb
Host smart-edc3c90c-4e01-410b-8f26-3c7d7e757547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905591288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3905591288
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2556676289
Short name T43
Test name
Test status
Simulation time 17925743866 ps
CPU time 46.43 seconds
Started Jun 24 06:01:45 PM PDT 24
Finished Jun 24 06:02:32 PM PDT 24
Peak memory 213212 kb
Host smart-b555a567-7bd3-404c-9892-95dc510c562c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556676289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2556676289
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.237294631
Short name T202
Test name
Test status
Simulation time 3267528936 ps
CPU time 2.34 seconds
Started Jun 24 06:01:45 PM PDT 24
Finished Jun 24 06:01:48 PM PDT 24
Peak memory 205136 kb
Host smart-18daf72e-221f-4f72-9264-c76e4201f112
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=237294631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.237294631
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.727123993
Short name T180
Test name
Test status
Simulation time 2232610814 ps
CPU time 6.9 seconds
Started Jun 24 06:01:45 PM PDT 24
Finished Jun 24 06:01:53 PM PDT 24
Peak memory 204976 kb
Host smart-548561cf-a1a7-458c-9792-c15a1a9f6344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727123993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.727123993
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2164586552
Short name T153
Test name
Test status
Simulation time 60382801 ps
CPU time 0.86 seconds
Started Jun 24 06:01:57 PM PDT 24
Finished Jun 24 06:01:58 PM PDT 24
Peak memory 204780 kb
Host smart-1c9c5ba1-18a4-4f6a-ab54-78653b859592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164586552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2164586552
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3821276857
Short name T20
Test name
Test status
Simulation time 4704711801 ps
CPU time 7.25 seconds
Started Jun 24 06:01:54 PM PDT 24
Finished Jun 24 06:02:02 PM PDT 24
Peak memory 205112 kb
Host smart-b93309d0-1279-4aa3-aa89-b1ec9b001cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821276857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3821276857
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2756656632
Short name T211
Test name
Test status
Simulation time 5276280123 ps
CPU time 8.35 seconds
Started Jun 24 06:01:47 PM PDT 24
Finished Jun 24 06:01:56 PM PDT 24
Peak memory 205084 kb
Host smart-94d3a20f-3e69-4a76-aacb-3198d8b24f95
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2756656632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2756656632
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2789272487
Short name T221
Test name
Test status
Simulation time 2839139848 ps
CPU time 7.36 seconds
Started Jun 24 06:01:45 PM PDT 24
Finished Jun 24 06:01:53 PM PDT 24
Peak memory 205212 kb
Host smart-7dfdc8f7-c21b-4294-90d5-503a3e00abb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789272487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2789272487
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.2228680863
Short name T7
Test name
Test status
Simulation time 16812177088 ps
CPU time 44.55 seconds
Started Jun 24 06:01:56 PM PDT 24
Finished Jun 24 06:02:41 PM PDT 24
Peak memory 213156 kb
Host smart-33a91091-522f-4877-90c3-7ce5637d45b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228680863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2228680863
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2022785013
Short name T243
Test name
Test status
Simulation time 7252850949 ps
CPU time 3.96 seconds
Started Jun 24 06:01:53 PM PDT 24
Finished Jun 24 06:01:58 PM PDT 24
Peak memory 213412 kb
Host smart-513b2872-a46b-42bb-b4cc-8d41d3039bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022785013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2022785013
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1231405201
Short name T237
Test name
Test status
Simulation time 16529372898 ps
CPU time 11.4 seconds
Started Jun 24 06:01:55 PM PDT 24
Finished Jun 24 06:02:07 PM PDT 24
Peak memory 213376 kb
Host smart-497b8431-09ea-4198-9e7a-ef05b1d2b1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231405201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1231405201
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.4236040633
Short name T53
Test name
Test status
Simulation time 2477899083 ps
CPU time 2.9 seconds
Started Jun 24 06:01:53 PM PDT 24
Finished Jun 24 06:01:56 PM PDT 24
Peak memory 205156 kb
Host smart-bd275183-dcbe-4ecd-a1b2-d4c0fbcbe99f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4236040633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.4236040633
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2095618642
Short name T206
Test name
Test status
Simulation time 2464342734 ps
CPU time 1.7 seconds
Started Jun 24 06:01:54 PM PDT 24
Finished Jun 24 06:01:56 PM PDT 24
Peak memory 205172 kb
Host smart-a2e8b187-6700-47d6-a9f0-01f187049237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095618642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2095618642
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3491344491
Short name T50
Test name
Test status
Simulation time 57508305 ps
CPU time 0.68 seconds
Started Jun 24 06:01:55 PM PDT 24
Finished Jun 24 06:01:58 PM PDT 24
Peak memory 204804 kb
Host smart-fe23ea70-4f43-4f5b-905d-ccb9f63096d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491344491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3491344491
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3864155869
Short name T178
Test name
Test status
Simulation time 5107844284 ps
CPU time 13.84 seconds
Started Jun 24 06:01:55 PM PDT 24
Finished Jun 24 06:02:11 PM PDT 24
Peak memory 213352 kb
Host smart-1ae92fac-955b-45a6-b2fb-bd97d7939c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864155869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3864155869
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2856609153
Short name T229
Test name
Test status
Simulation time 1616974042 ps
CPU time 2.2 seconds
Started Jun 24 06:01:53 PM PDT 24
Finished Jun 24 06:01:56 PM PDT 24
Peak memory 205140 kb
Host smart-9f910791-146b-4678-b718-336b299f1bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856609153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2856609153
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1002052828
Short name T169
Test name
Test status
Simulation time 2029225426 ps
CPU time 5.96 seconds
Started Jun 24 06:01:53 PM PDT 24
Finished Jun 24 06:01:59 PM PDT 24
Peak memory 205124 kb
Host smart-d756ebc0-cffa-4cd7-ab27-211357782162
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002052828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1002052828
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2462873206
Short name T223
Test name
Test status
Simulation time 3089166170 ps
CPU time 2.05 seconds
Started Jun 24 06:01:56 PM PDT 24
Finished Jun 24 06:01:59 PM PDT 24
Peak memory 205180 kb
Host smart-a6999f4a-4ada-456d-ad14-0ec07ab72c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462873206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2462873206
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3216714723
Short name T158
Test name
Test status
Simulation time 76764753 ps
CPU time 0.76 seconds
Started Jun 24 06:02:06 PM PDT 24
Finished Jun 24 06:02:08 PM PDT 24
Peak memory 204792 kb
Host smart-29bdad85-e51c-4ab2-ba4e-74faca3713f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216714723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3216714723
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1361723217
Short name T188
Test name
Test status
Simulation time 6760562594 ps
CPU time 5.89 seconds
Started Jun 24 06:02:03 PM PDT 24
Finished Jun 24 06:02:10 PM PDT 24
Peak memory 205200 kb
Host smart-fe5090a5-9011-4c6e-84be-8e642972bc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361723217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1361723217
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1196558291
Short name T233
Test name
Test status
Simulation time 1242637234 ps
CPU time 4.52 seconds
Started Jun 24 06:01:56 PM PDT 24
Finished Jun 24 06:02:02 PM PDT 24
Peak memory 205076 kb
Host smart-0c2170db-b50d-4db1-8a20-2f6b3809e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196558291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1196558291
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2001308143
Short name T219
Test name
Test status
Simulation time 1911038507 ps
CPU time 5.06 seconds
Started Jun 24 06:01:56 PM PDT 24
Finished Jun 24 06:02:02 PM PDT 24
Peak memory 205140 kb
Host smart-45f897ae-d92c-4dd3-b192-6819dfb6cb20
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2001308143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2001308143
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2226887598
Short name T245
Test name
Test status
Simulation time 14381812576 ps
CPU time 19.61 seconds
Started Jun 24 06:01:57 PM PDT 24
Finished Jun 24 06:02:17 PM PDT 24
Peak memory 205152 kb
Host smart-f4b65740-aa6f-415c-814e-45848a5e3c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226887598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2226887598
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1419771040
Short name T23
Test name
Test status
Simulation time 10175076858 ps
CPU time 7.27 seconds
Started Jun 24 06:02:03 PM PDT 24
Finished Jun 24 06:02:11 PM PDT 24
Peak memory 205040 kb
Host smart-2e433652-39a6-489b-bdb7-4c1e66f70d41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419771040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1419771040
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2139832867
Short name T162
Test name
Test status
Simulation time 29918941 ps
CPU time 0.76 seconds
Started Jun 24 06:02:03 PM PDT 24
Finished Jun 24 06:02:05 PM PDT 24
Peak memory 205044 kb
Host smart-6db652bd-b6a7-4217-bb5a-9beae328843d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139832867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2139832867
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1524031899
Short name T251
Test name
Test status
Simulation time 18933485505 ps
CPU time 46.05 seconds
Started Jun 24 06:02:04 PM PDT 24
Finished Jun 24 06:02:51 PM PDT 24
Peak memory 213392 kb
Host smart-bcca7a5a-19db-4403-abaa-1798b0f2e7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524031899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1524031899
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.652901873
Short name T171
Test name
Test status
Simulation time 1759399168 ps
CPU time 2.16 seconds
Started Jun 24 06:02:02 PM PDT 24
Finished Jun 24 06:02:04 PM PDT 24
Peak memory 205152 kb
Host smart-d9d8f67b-8561-422e-a4cc-4fc04e2ea736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652901873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.652901873
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3710689765
Short name T194
Test name
Test status
Simulation time 2756482415 ps
CPU time 2.32 seconds
Started Jun 24 06:02:02 PM PDT 24
Finished Jun 24 06:02:06 PM PDT 24
Peak memory 205196 kb
Host smart-daa4856d-4b13-4979-a4c9-c70d292c455a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3710689765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.3710689765
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.213214834
Short name T228
Test name
Test status
Simulation time 2563159979 ps
CPU time 4.53 seconds
Started Jun 24 06:02:03 PM PDT 24
Finished Jun 24 06:02:08 PM PDT 24
Peak memory 205172 kb
Host smart-22e44b17-3cc3-4313-8466-e4668c9745b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213214834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.213214834
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3129834822
Short name T146
Test name
Test status
Simulation time 69711239 ps
CPU time 0.75 seconds
Started Jun 24 06:02:02 PM PDT 24
Finished Jun 24 06:02:03 PM PDT 24
Peak memory 204792 kb
Host smart-d6761989-af4f-45cf-a6b6-c401e5f9ec15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129834822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3129834822
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2412259190
Short name T179
Test name
Test status
Simulation time 94709150838 ps
CPU time 129.14 seconds
Started Jun 24 06:02:04 PM PDT 24
Finished Jun 24 06:04:14 PM PDT 24
Peak memory 215788 kb
Host smart-a01bdce0-0c19-4c1c-93f9-38b78448f051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412259190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2412259190
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3088143674
Short name T242
Test name
Test status
Simulation time 2845777452 ps
CPU time 6.17 seconds
Started Jun 24 06:02:04 PM PDT 24
Finished Jun 24 06:02:10 PM PDT 24
Peak memory 205188 kb
Host smart-492ac06f-3d39-44c2-95bd-a0068419884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088143674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3088143674
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.15034416
Short name T183
Test name
Test status
Simulation time 7186096512 ps
CPU time 9.01 seconds
Started Jun 24 06:02:01 PM PDT 24
Finished Jun 24 06:02:11 PM PDT 24
Peak memory 205208 kb
Host smart-d3a896e1-8c13-4140-8c5f-c551876ae11a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15034416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_tl
_access.15034416
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1817929267
Short name T236
Test name
Test status
Simulation time 1418250240 ps
CPU time 2.15 seconds
Started Jun 24 06:02:03 PM PDT 24
Finished Jun 24 06:02:06 PM PDT 24
Peak memory 205128 kb
Host smart-222323ed-34d1-47ad-84c2-7d9ad195f8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817929267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1817929267
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.78512578
Short name T207
Test name
Test status
Simulation time 179776523 ps
CPU time 1.09 seconds
Started Jun 24 06:02:13 PM PDT 24
Finished Jun 24 06:02:15 PM PDT 24
Peak memory 204808 kb
Host smart-7c3fe2dd-2f7d-4be6-8bf5-14524ecd5b35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78512578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.78512578
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2536666872
Short name T239
Test name
Test status
Simulation time 1093172965 ps
CPU time 3.49 seconds
Started Jun 24 06:02:10 PM PDT 24
Finished Jun 24 06:02:14 PM PDT 24
Peak memory 205148 kb
Host smart-db340bb2-e93d-41eb-8823-88f53914c309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536666872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2536666872
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.475199750
Short name T177
Test name
Test status
Simulation time 11171222844 ps
CPU time 25.7 seconds
Started Jun 24 06:02:12 PM PDT 24
Finished Jun 24 06:02:38 PM PDT 24
Peak memory 213436 kb
Host smart-f26b73a3-9cf9-498e-a87d-3c5d50fbfae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475199750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.475199750
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2617685566
Short name T222
Test name
Test status
Simulation time 1346610934 ps
CPU time 2.81 seconds
Started Jun 24 06:02:10 PM PDT 24
Finished Jun 24 06:02:14 PM PDT 24
Peak memory 205124 kb
Host smart-de8f193d-8e2e-4c27-9172-c19ba4d64324
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2617685566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2617685566
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1710061333
Short name T208
Test name
Test status
Simulation time 1900901268 ps
CPU time 2.55 seconds
Started Jun 24 06:02:10 PM PDT 24
Finished Jun 24 06:02:13 PM PDT 24
Peak memory 205140 kb
Host smart-c80224ec-7a83-425d-bffe-e511444a5cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710061333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1710061333
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2881309863
Short name T66
Test name
Test status
Simulation time 177164189 ps
CPU time 0.74 seconds
Started Jun 24 06:02:10 PM PDT 24
Finished Jun 24 06:02:11 PM PDT 24
Peak memory 204812 kb
Host smart-753ae8a2-1756-4b7c-ad07-f7a8daba1029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881309863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2881309863
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2901868014
Short name T254
Test name
Test status
Simulation time 7644788651 ps
CPU time 5.12 seconds
Started Jun 24 06:02:11 PM PDT 24
Finished Jun 24 06:02:17 PM PDT 24
Peak memory 213344 kb
Host smart-e2634e93-2612-4898-bc4b-8207b426f030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901868014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2901868014
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2854957399
Short name T192
Test name
Test status
Simulation time 5976209108 ps
CPU time 16.7 seconds
Started Jun 24 06:02:09 PM PDT 24
Finished Jun 24 06:02:27 PM PDT 24
Peak memory 205300 kb
Host smart-39d82481-00ef-4f9c-8fcc-fbf010c2b769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854957399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2854957399
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3359917805
Short name T3
Test name
Test status
Simulation time 2383888007 ps
CPU time 7.42 seconds
Started Jun 24 06:02:12 PM PDT 24
Finished Jun 24 06:02:20 PM PDT 24
Peak memory 205148 kb
Host smart-77cb22a3-4fe2-434f-9272-70d5aee29ed7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359917805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3359917805
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2832406451
Short name T247
Test name
Test status
Simulation time 3511667578 ps
CPU time 10.84 seconds
Started Jun 24 06:02:11 PM PDT 24
Finished Jun 24 06:02:22 PM PDT 24
Peak memory 205212 kb
Host smart-947ece66-af72-445a-8908-40a71aa4c118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832406451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2832406451
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3418307886
Short name T145
Test name
Test status
Simulation time 93309569 ps
CPU time 0.8 seconds
Started Jun 24 06:01:35 PM PDT 24
Finished Jun 24 06:01:37 PM PDT 24
Peak memory 204748 kb
Host smart-ec56847f-2e6f-4a70-ae4a-8b5d7f322d93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418307886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3418307886
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3460594720
Short name T224
Test name
Test status
Simulation time 3426806381 ps
CPU time 3.23 seconds
Started Jun 24 06:01:35 PM PDT 24
Finished Jun 24 06:01:39 PM PDT 24
Peak memory 205212 kb
Host smart-cffe6d4d-3c84-4d5b-ad05-dd0556ffd982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460594720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3460594720
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3424221657
Short name T217
Test name
Test status
Simulation time 5048225043 ps
CPU time 4.98 seconds
Started Jun 24 06:01:33 PM PDT 24
Finished Jun 24 06:01:39 PM PDT 24
Peak memory 205108 kb
Host smart-ab7af0bc-b0fa-4350-8140-c803cf0124a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424221657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3424221657
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.4292276526
Short name T213
Test name
Test status
Simulation time 5789914807 ps
CPU time 5.02 seconds
Started Jun 24 06:01:21 PM PDT 24
Finished Jun 24 06:01:27 PM PDT 24
Peak memory 205168 kb
Host smart-12456928-1f11-44ce-a5d7-5937b8b467a0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292276526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.4292276526
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3417311201
Short name T168
Test name
Test status
Simulation time 437508851 ps
CPU time 1.8 seconds
Started Jun 24 06:01:36 PM PDT 24
Finished Jun 24 06:01:39 PM PDT 24
Peak memory 204608 kb
Host smart-e4548599-38fd-4aec-815e-5817438c139a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417311201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3417311201
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.752479228
Short name T189
Test name
Test status
Simulation time 9181777945 ps
CPU time 11.51 seconds
Started Jun 24 06:01:21 PM PDT 24
Finished Jun 24 06:01:33 PM PDT 24
Peak memory 205240 kb
Host smart-dfe0e551-a508-4af2-9848-8cacbe2a8ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752479228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.752479228
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2286399870
Short name T41
Test name
Test status
Simulation time 719989564 ps
CPU time 1.73 seconds
Started Jun 24 06:01:33 PM PDT 24
Finished Jun 24 06:01:36 PM PDT 24
Peak memory 228744 kb
Host smart-2d5a6cc4-9cca-4ac9-8a5e-d1dd071c8bf2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286399870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2286399870
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2754293176
Short name T139
Test name
Test status
Simulation time 94753137 ps
CPU time 0.72 seconds
Started Jun 24 06:02:12 PM PDT 24
Finished Jun 24 06:02:13 PM PDT 24
Peak memory 204800 kb
Host smart-1df00d75-0c09-4fcc-b39e-6f5600fad1a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754293176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2754293176
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3836279692
Short name T144
Test name
Test status
Simulation time 41372440 ps
CPU time 0.75 seconds
Started Jun 24 06:02:13 PM PDT 24
Finished Jun 24 06:02:14 PM PDT 24
Peak memory 205044 kb
Host smart-1caf3985-f739-4546-96d4-dfcb3a490030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836279692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3836279692
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.1652442193
Short name T215
Test name
Test status
Simulation time 8156900540 ps
CPU time 22.4 seconds
Started Jun 24 06:02:09 PM PDT 24
Finished Jun 24 06:02:32 PM PDT 24
Peak memory 204984 kb
Host smart-fb877112-342f-49ce-9d99-9db3707f7eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652442193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1652442193
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1994348521
Short name T138
Test name
Test status
Simulation time 130784568 ps
CPU time 0.86 seconds
Started Jun 24 06:02:11 PM PDT 24
Finished Jun 24 06:02:13 PM PDT 24
Peak memory 204800 kb
Host smart-825a83bd-f1e5-478a-8720-f1c1dfde7a01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994348521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1994348521
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3646925880
Short name T163
Test name
Test status
Simulation time 130412269 ps
CPU time 0.73 seconds
Started Jun 24 06:02:12 PM PDT 24
Finished Jun 24 06:02:13 PM PDT 24
Peak memory 204808 kb
Host smart-4853f294-688f-4c08-a7ce-ebe134a8f13e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646925880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3646925880
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.4270300129
Short name T65
Test name
Test status
Simulation time 196225862 ps
CPU time 0.73 seconds
Started Jun 24 06:02:20 PM PDT 24
Finished Jun 24 06:02:22 PM PDT 24
Peak memory 204800 kb
Host smart-759920d8-7730-41ee-9828-7231aa571251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270300129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.4270300129
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3763274648
Short name T113
Test name
Test status
Simulation time 115906793 ps
CPU time 0.72 seconds
Started Jun 24 06:02:25 PM PDT 24
Finished Jun 24 06:02:26 PM PDT 24
Peak memory 204140 kb
Host smart-2e338198-ddde-4e7a-bf08-396d89f3aed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763274648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3763274648
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2581370364
Short name T64
Test name
Test status
Simulation time 127273685 ps
CPU time 0.99 seconds
Started Jun 24 06:02:25 PM PDT 24
Finished Jun 24 06:02:27 PM PDT 24
Peak memory 204028 kb
Host smart-bfd7fcf3-4aa2-4246-a885-ec9989a8f76c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581370364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2581370364
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.461039210
Short name T14
Test name
Test status
Simulation time 10210956423 ps
CPU time 9.1 seconds
Started Jun 24 06:02:22 PM PDT 24
Finished Jun 24 06:02:32 PM PDT 24
Peak memory 204972 kb
Host smart-ad33275a-851e-4159-9b00-920fee63f940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461039210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.461039210
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3854498225
Short name T142
Test name
Test status
Simulation time 144629062 ps
CPU time 0.72 seconds
Started Jun 24 06:02:20 PM PDT 24
Finished Jun 24 06:02:22 PM PDT 24
Peak memory 204792 kb
Host smart-b9e088dc-93ab-4bf2-a424-3e0246b6df81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854498225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3854498225
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.188697670
Short name T157
Test name
Test status
Simulation time 79082362 ps
CPU time 0.83 seconds
Started Jun 24 06:02:20 PM PDT 24
Finished Jun 24 06:02:22 PM PDT 24
Peak memory 204776 kb
Host smart-555b238e-b970-417c-a8fb-72b5ef2cbe6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188697670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.188697670
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.87045858
Short name T159
Test name
Test status
Simulation time 69127797 ps
CPU time 0.68 seconds
Started Jun 24 06:02:22 PM PDT 24
Finished Jun 24 06:02:23 PM PDT 24
Peak memory 204804 kb
Host smart-42c7cae1-c00a-4c3a-9c5e-e10164165fe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87045858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.87045858
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.75599732
Short name T24
Test name
Test status
Simulation time 78433313 ps
CPU time 0.78 seconds
Started Jun 24 06:01:35 PM PDT 24
Finished Jun 24 06:01:37 PM PDT 24
Peak memory 204752 kb
Host smart-085391fe-8e6d-49f7-aa72-dd495d72a616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75599732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.75599732
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.4266136102
Short name T249
Test name
Test status
Simulation time 5144357658 ps
CPU time 7.61 seconds
Started Jun 24 06:01:38 PM PDT 24
Finished Jun 24 06:01:46 PM PDT 24
Peak memory 213404 kb
Host smart-bc2c06a5-e923-44f5-888d-6dcbe9f76ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266136102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.4266136102
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.612314953
Short name T173
Test name
Test status
Simulation time 13779090011 ps
CPU time 12.1 seconds
Started Jun 24 06:01:33 PM PDT 24
Finished Jun 24 06:01:46 PM PDT 24
Peak memory 213412 kb
Host smart-6999d982-467a-48f7-92ec-182bd5e10bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612314953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.612314953
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4212273002
Short name T218
Test name
Test status
Simulation time 3636650994 ps
CPU time 1.99 seconds
Started Jun 24 06:01:33 PM PDT 24
Finished Jun 24 06:01:36 PM PDT 24
Peak memory 205156 kb
Host smart-b44d2414-cb76-415e-b2c7-9ae8e9382e22
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4212273002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.4212273002
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.744394848
Short name T258
Test name
Test status
Simulation time 332651885 ps
CPU time 0.83 seconds
Started Jun 24 06:01:34 PM PDT 24
Finished Jun 24 06:01:36 PM PDT 24
Peak memory 204620 kb
Host smart-e6130dad-32da-4e6a-9069-4450b5ff2371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744394848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.744394848
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1438718582
Short name T204
Test name
Test status
Simulation time 7128190673 ps
CPU time 12.65 seconds
Started Jun 24 06:01:36 PM PDT 24
Finished Jun 24 06:01:50 PM PDT 24
Peak memory 205188 kb
Host smart-6ce91adb-6042-4720-9c43-5b1973803570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438718582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1438718582
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1540658493
Short name T42
Test name
Test status
Simulation time 1254140018 ps
CPU time 2.68 seconds
Started Jun 24 06:01:35 PM PDT 24
Finished Jun 24 06:01:38 PM PDT 24
Peak memory 229088 kb
Host smart-d6c2fc6b-e86c-4311-8fb9-bfb2a5cfa6d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540658493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1540658493
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.4233439085
Short name T232
Test name
Test status
Simulation time 48229186 ps
CPU time 0.73 seconds
Started Jun 24 06:02:20 PM PDT 24
Finished Jun 24 06:02:21 PM PDT 24
Peak memory 204812 kb
Host smart-f0898466-fcdb-4155-81e5-32e7bd10dccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233439085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.4233439085
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.1718237888
Short name T133
Test name
Test status
Simulation time 18459086592 ps
CPU time 14.72 seconds
Started Jun 24 06:02:24 PM PDT 24
Finished Jun 24 06:02:39 PM PDT 24
Peak memory 213136 kb
Host smart-5adc2066-83ab-40ee-af42-c434a162b4d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718237888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1718237888
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1708383335
Short name T161
Test name
Test status
Simulation time 69778661 ps
CPU time 0.7 seconds
Started Jun 24 06:02:22 PM PDT 24
Finished Jun 24 06:02:24 PM PDT 24
Peak memory 204804 kb
Host smart-ee06d6c0-431a-41e7-bc5f-99d9642bc83a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708383335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1708383335
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3378237468
Short name T149
Test name
Test status
Simulation time 103535755 ps
CPU time 0.79 seconds
Started Jun 24 06:02:23 PM PDT 24
Finished Jun 24 06:02:24 PM PDT 24
Peak memory 204804 kb
Host smart-b310b1b2-a1cd-4468-a7ff-8388b0893eb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378237468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3378237468
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.2811502619
Short name T128
Test name
Test status
Simulation time 6729020608 ps
CPU time 4.67 seconds
Started Jun 24 06:02:20 PM PDT 24
Finished Jun 24 06:02:25 PM PDT 24
Peak memory 204992 kb
Host smart-44696ee0-c382-4ad7-a063-0e35b59241c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811502619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.2811502619
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2221644194
Short name T137
Test name
Test status
Simulation time 34420630 ps
CPU time 0.77 seconds
Started Jun 24 06:02:20 PM PDT 24
Finished Jun 24 06:02:22 PM PDT 24
Peak memory 204804 kb
Host smart-3177cbbb-cc55-4b8b-a660-161269a3341c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221644194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2221644194
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.3141081745
Short name T186
Test name
Test status
Simulation time 8272166466 ps
CPU time 3.65 seconds
Started Jun 24 06:02:22 PM PDT 24
Finished Jun 24 06:02:27 PM PDT 24
Peak memory 204988 kb
Host smart-1382dd2c-b08e-4fa9-b873-3b1c92d28556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141081745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3141081745
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.395030538
Short name T54
Test name
Test status
Simulation time 102462129 ps
CPU time 0.72 seconds
Started Jun 24 06:02:22 PM PDT 24
Finished Jun 24 06:02:24 PM PDT 24
Peak memory 204804 kb
Host smart-ea1db485-b345-43e7-8d09-c1bce0c6a64c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395030538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.395030538
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.1556616923
Short name T13
Test name
Test status
Simulation time 11176294497 ps
CPU time 14.14 seconds
Started Jun 24 06:02:19 PM PDT 24
Finished Jun 24 06:02:34 PM PDT 24
Peak memory 205056 kb
Host smart-d5613d1c-c97e-4dc7-8868-b01d8555f9cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556616923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1556616923
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3233034541
Short name T134
Test name
Test status
Simulation time 167352548 ps
CPU time 0.75 seconds
Started Jun 24 06:02:21 PM PDT 24
Finished Jun 24 06:02:23 PM PDT 24
Peak memory 204804 kb
Host smart-61e3a24e-f857-4ad9-a316-ca878dcaedfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233034541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3233034541
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.2733660262
Short name T112
Test name
Test status
Simulation time 93356906 ps
CPU time 0.69 seconds
Started Jun 24 06:02:21 PM PDT 24
Finished Jun 24 06:02:23 PM PDT 24
Peak memory 204820 kb
Host smart-2f7ab140-2750-4726-9670-82170a57f745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733660262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2733660262
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.463599049
Short name T203
Test name
Test status
Simulation time 20189580762 ps
CPU time 14.39 seconds
Started Jun 24 06:02:20 PM PDT 24
Finished Jun 24 06:02:36 PM PDT 24
Peak memory 205088 kb
Host smart-a77c6304-2abe-4258-b75d-5536c771e47f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463599049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.463599049
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1864285759
Short name T135
Test name
Test status
Simulation time 46708213 ps
CPU time 0.79 seconds
Started Jun 24 06:02:21 PM PDT 24
Finished Jun 24 06:02:23 PM PDT 24
Peak memory 204744 kb
Host smart-fdfef2ea-be63-4955-a26d-46588f292396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864285759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1864285759
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2193031239
Short name T148
Test name
Test status
Simulation time 45118314 ps
CPU time 0.71 seconds
Started Jun 24 06:02:21 PM PDT 24
Finished Jun 24 06:02:23 PM PDT 24
Peak memory 204804 kb
Host smart-93f47c22-b103-4a87-98a6-1a5aa61afbe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193031239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2193031239
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1687724493
Short name T193
Test name
Test status
Simulation time 33055202 ps
CPU time 0.82 seconds
Started Jun 24 06:02:22 PM PDT 24
Finished Jun 24 06:02:24 PM PDT 24
Peak memory 204792 kb
Host smart-6dfddfbb-259d-475d-b381-d6794ebda79d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687724493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1687724493
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.353815498
Short name T154
Test name
Test status
Simulation time 153402645 ps
CPU time 1.04 seconds
Started Jun 24 06:01:33 PM PDT 24
Finished Jun 24 06:01:35 PM PDT 24
Peak memory 204804 kb
Host smart-c3a1839b-dc1a-4662-ae2d-d926a16f0aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353815498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.353815498
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1071485625
Short name T1
Test name
Test status
Simulation time 15305538553 ps
CPU time 21.92 seconds
Started Jun 24 06:01:35 PM PDT 24
Finished Jun 24 06:01:58 PM PDT 24
Peak memory 205204 kb
Host smart-fc76a07d-041c-4b79-9946-2bd85f0a4211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071485625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1071485625
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1717811062
Short name T196
Test name
Test status
Simulation time 12766228882 ps
CPU time 34.18 seconds
Started Jun 24 06:01:36 PM PDT 24
Finished Jun 24 06:02:12 PM PDT 24
Peak memory 215436 kb
Host smart-388e1673-0bad-4ec4-b008-91eab5d3deac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717811062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1717811062
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2416003017
Short name T205
Test name
Test status
Simulation time 2374509091 ps
CPU time 3.89 seconds
Started Jun 24 06:01:35 PM PDT 24
Finished Jun 24 06:01:40 PM PDT 24
Peak memory 205184 kb
Host smart-9dec8531-80ad-4f30-8824-0da0c8a866d6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416003017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2416003017
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.269513232
Short name T175
Test name
Test status
Simulation time 167850700 ps
CPU time 1.05 seconds
Started Jun 24 06:01:35 PM PDT 24
Finished Jun 24 06:01:38 PM PDT 24
Peak memory 204612 kb
Host smart-2be63377-7d75-48a3-82d0-b2a8cb67348a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269513232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.269513232
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3326023472
Short name T176
Test name
Test status
Simulation time 7524227561 ps
CPU time 6.26 seconds
Started Jun 24 06:01:33 PM PDT 24
Finished Jun 24 06:01:39 PM PDT 24
Peak memory 205216 kb
Host smart-43d63c47-4b4a-4213-b7d9-fb94bbf95436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326023472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3326023472
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2982762669
Short name T165
Test name
Test status
Simulation time 114153566 ps
CPU time 0.75 seconds
Started Jun 24 06:02:22 PM PDT 24
Finished Jun 24 06:02:24 PM PDT 24
Peak memory 204792 kb
Host smart-98b06696-3d67-4168-9577-659b00c276e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982762669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2982762669
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1007519982
Short name T59
Test name
Test status
Simulation time 115170404 ps
CPU time 0.78 seconds
Started Jun 24 06:02:30 PM PDT 24
Finished Jun 24 06:02:32 PM PDT 24
Peak memory 204804 kb
Host smart-0fefec54-d722-4945-b75b-fb47bbb69fb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007519982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1007519982
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1910653229
Short name T136
Test name
Test status
Simulation time 34982325 ps
CPU time 0.73 seconds
Started Jun 24 06:02:31 PM PDT 24
Finished Jun 24 06:02:34 PM PDT 24
Peak memory 204804 kb
Host smart-3a196099-b704-428e-85f3-60ceecff02dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910653229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1910653229
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2086617047
Short name T160
Test name
Test status
Simulation time 69945510 ps
CPU time 0.81 seconds
Started Jun 24 06:02:31 PM PDT 24
Finished Jun 24 06:02:34 PM PDT 24
Peak memory 204776 kb
Host smart-fb464de2-0d4e-4bc9-b801-20ae5ed92443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086617047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2086617047
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.1439143657
Short name T22
Test name
Test status
Simulation time 9706368433 ps
CPU time 7.92 seconds
Started Jun 24 06:02:36 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 205032 kb
Host smart-97cef1cc-2082-4c8b-aba1-e67964d795ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439143657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1439143657
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2057110915
Short name T150
Test name
Test status
Simulation time 242682846 ps
CPU time 0.75 seconds
Started Jun 24 06:02:31 PM PDT 24
Finished Jun 24 06:02:33 PM PDT 24
Peak memory 205044 kb
Host smart-1725568a-83af-4a71-8f9f-66ba615b7180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057110915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2057110915
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2422034735
Short name T200
Test name
Test status
Simulation time 33379916 ps
CPU time 0.75 seconds
Started Jun 24 06:02:31 PM PDT 24
Finished Jun 24 06:02:33 PM PDT 24
Peak memory 204804 kb
Host smart-2fb06c55-ca34-4b1f-a8cd-2341d3701f5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422034735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2422034735
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.498078837
Short name T140
Test name
Test status
Simulation time 238982048 ps
CPU time 0.72 seconds
Started Jun 24 06:02:29 PM PDT 24
Finished Jun 24 06:02:30 PM PDT 24
Peak memory 204812 kb
Host smart-fb439e5c-2cb9-4aaa-acb3-dc976c1a4d74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498078837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.498078837
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3812170045
Short name T25
Test name
Test status
Simulation time 106813537 ps
CPU time 0.69 seconds
Started Jun 24 06:02:32 PM PDT 24
Finished Jun 24 06:02:35 PM PDT 24
Peak memory 204792 kb
Host smart-4814d8b3-9ca4-436f-876e-1b65e10fad38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812170045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3812170045
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.33603461
Short name T151
Test name
Test status
Simulation time 174402101 ps
CPU time 0.7 seconds
Started Jun 24 06:02:32 PM PDT 24
Finished Jun 24 06:02:35 PM PDT 24
Peak memory 204804 kb
Host smart-d04cc083-851d-43d2-bd2c-3a761f5d715d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33603461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.33603461
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.2841339283
Short name T246
Test name
Test status
Simulation time 5295361326 ps
CPU time 13.36 seconds
Started Jun 24 06:02:32 PM PDT 24
Finished Jun 24 06:02:47 PM PDT 24
Peak memory 213184 kb
Host smart-80338dff-e5c4-4449-8f85-c80b3c90a40e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841339283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2841339283
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3236835883
Short name T152
Test name
Test status
Simulation time 79835249 ps
CPU time 0.76 seconds
Started Jun 24 06:02:35 PM PDT 24
Finished Jun 24 06:02:36 PM PDT 24
Peak memory 204784 kb
Host smart-3a990bdd-81d4-40a4-bbb3-1477934961f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236835883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3236835883
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.632496344
Short name T182
Test name
Test status
Simulation time 80952589 ps
CPU time 0.86 seconds
Started Jun 24 06:01:39 PM PDT 24
Finished Jun 24 06:01:40 PM PDT 24
Peak memory 204776 kb
Host smart-b92863ed-39fa-4b50-9362-979b7dd667f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632496344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.632496344
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2567921128
Short name T58
Test name
Test status
Simulation time 10709731000 ps
CPU time 7.86 seconds
Started Jun 24 06:01:34 PM PDT 24
Finished Jun 24 06:01:42 PM PDT 24
Peak memory 213404 kb
Host smart-e04dab16-1da4-47e5-9ceb-2ed486bf5171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567921128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2567921128
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1636344654
Short name T210
Test name
Test status
Simulation time 2530142826 ps
CPU time 4.68 seconds
Started Jun 24 06:01:35 PM PDT 24
Finished Jun 24 06:01:41 PM PDT 24
Peak memory 205156 kb
Host smart-dc9f2ff8-cff0-4336-8746-cf1ef1c22523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636344654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1636344654
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2889320697
Short name T67
Test name
Test status
Simulation time 4608561939 ps
CPU time 13.74 seconds
Started Jun 24 06:01:38 PM PDT 24
Finished Jun 24 06:01:53 PM PDT 24
Peak memory 205168 kb
Host smart-4b03f872-19fe-4104-a57b-5dd54ffa20d9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2889320697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2889320697
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3122456918
Short name T255
Test name
Test status
Simulation time 2999703508 ps
CPU time 2.25 seconds
Started Jun 24 06:01:33 PM PDT 24
Finished Jun 24 06:01:36 PM PDT 24
Peak memory 205148 kb
Host smart-a893ae7c-d61a-40d7-a8f4-b50288abe283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122456918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3122456918
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.3334724034
Short name T127
Test name
Test status
Simulation time 29189401192 ps
CPU time 8.38 seconds
Started Jun 24 06:01:38 PM PDT 24
Finished Jun 24 06:01:47 PM PDT 24
Peak memory 204956 kb
Host smart-ecab7130-8318-4a3f-bba3-bd22cac040ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334724034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3334724034
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1219702454
Short name T156
Test name
Test status
Simulation time 141002103 ps
CPU time 0.85 seconds
Started Jun 24 06:01:35 PM PDT 24
Finished Jun 24 06:01:37 PM PDT 24
Peak memory 204696 kb
Host smart-6afe6494-f894-49e4-8ad5-4435f3ee3305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219702454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1219702454
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2441669377
Short name T86
Test name
Test status
Simulation time 24181488399 ps
CPU time 34.4 seconds
Started Jun 24 06:01:37 PM PDT 24
Finished Jun 24 06:02:12 PM PDT 24
Peak memory 213396 kb
Host smart-e6748536-bf96-4b80-b683-555cd502634f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441669377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2441669377
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.250806941
Short name T252
Test name
Test status
Simulation time 6886585515 ps
CPU time 10.17 seconds
Started Jun 24 06:01:35 PM PDT 24
Finished Jun 24 06:01:47 PM PDT 24
Peak memory 213392 kb
Host smart-6244c872-3fd3-4cf9-872e-59c4c648b80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250806941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.250806941
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.105248973
Short name T241
Test name
Test status
Simulation time 1910641461 ps
CPU time 2.42 seconds
Started Jun 24 06:01:34 PM PDT 24
Finished Jun 24 06:01:37 PM PDT 24
Peak memory 205076 kb
Host smart-184162f3-6d29-4676-b488-fe4723a2b51e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105248973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.105248973
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3413043489
Short name T167
Test name
Test status
Simulation time 15932952115 ps
CPU time 7.78 seconds
Started Jun 24 06:01:35 PM PDT 24
Finished Jun 24 06:01:44 PM PDT 24
Peak memory 213420 kb
Host smart-35059be1-6da7-4ef0-a515-b28b088c162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413043489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3413043489
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3654638214
Short name T147
Test name
Test status
Simulation time 113029088 ps
CPU time 0.69 seconds
Started Jun 24 06:01:44 PM PDT 24
Finished Jun 24 06:01:46 PM PDT 24
Peak memory 204816 kb
Host smart-0edc03f6-ca2f-4655-bcc7-fe274d76a522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654638214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3654638214
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.2390877396
Short name T166
Test name
Test status
Simulation time 8547790075 ps
CPU time 3.22 seconds
Started Jun 24 06:01:46 PM PDT 24
Finished Jun 24 06:01:51 PM PDT 24
Peak memory 213400 kb
Host smart-76f87612-ac9c-4d39-919f-cdfae6f017ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390877396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2390877396
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2217272888
Short name T244
Test name
Test status
Simulation time 2531614598 ps
CPU time 2.61 seconds
Started Jun 24 06:01:37 PM PDT 24
Finished Jun 24 06:01:41 PM PDT 24
Peak memory 205216 kb
Host smart-848f53b0-dfb3-46bc-a506-3466927fea99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217272888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2217272888
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.951295345
Short name T55
Test name
Test status
Simulation time 10467207895 ps
CPU time 9.71 seconds
Started Jun 24 06:01:38 PM PDT 24
Finished Jun 24 06:01:49 PM PDT 24
Peak memory 205192 kb
Host smart-906cc8b4-f0ff-4242-921b-2b61d948fb33
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=951295345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl
_access.951295345
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2945033136
Short name T250
Test name
Test status
Simulation time 7036011852 ps
CPU time 19.75 seconds
Started Jun 24 06:01:37 PM PDT 24
Finished Jun 24 06:01:58 PM PDT 24
Peak memory 205152 kb
Host smart-1a27de93-191b-4897-a980-c837417ea5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945033136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2945033136
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.432133882
Short name T141
Test name
Test status
Simulation time 63632018 ps
CPU time 0.73 seconds
Started Jun 24 06:01:46 PM PDT 24
Finished Jun 24 06:01:48 PM PDT 24
Peak memory 203804 kb
Host smart-75863381-c56a-48e1-888a-3a8197086109
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432133882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.432133882
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2235561218
Short name T63
Test name
Test status
Simulation time 12096401851 ps
CPU time 11.31 seconds
Started Jun 24 06:01:44 PM PDT 24
Finished Jun 24 06:01:56 PM PDT 24
Peak memory 213480 kb
Host smart-b8bd20b1-24de-4489-b0c5-dd9a783073e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235561218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2235561218
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.423532594
Short name T209
Test name
Test status
Simulation time 5633810920 ps
CPU time 4.81 seconds
Started Jun 24 06:01:44 PM PDT 24
Finished Jun 24 06:01:50 PM PDT 24
Peak memory 205212 kb
Host smart-22dc0349-0ae3-435d-a6f8-ad28d0886cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423532594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.423532594
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.312769192
Short name T234
Test name
Test status
Simulation time 5824193608 ps
CPU time 3 seconds
Started Jun 24 06:01:44 PM PDT 24
Finished Jun 24 06:01:47 PM PDT 24
Peak memory 205156 kb
Host smart-a19449fd-574b-4e11-95d8-c97e635ab107
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312769192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.312769192
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3736585455
Short name T216
Test name
Test status
Simulation time 1323485369 ps
CPU time 2.6 seconds
Started Jun 24 06:01:45 PM PDT 24
Finished Jun 24 06:01:48 PM PDT 24
Peak memory 205108 kb
Host smart-d6c4511c-6c90-414c-89fa-3c760278c049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736585455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3736585455
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.152549271
Short name T191
Test name
Test status
Simulation time 13485696092 ps
CPU time 37.08 seconds
Started Jun 24 06:01:47 PM PDT 24
Finished Jun 24 06:02:25 PM PDT 24
Peak memory 204792 kb
Host smart-1855b990-afc5-4707-8ca2-cd91b4497728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152549271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.152549271
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1062068388
Short name T198
Test name
Test status
Simulation time 54489716 ps
CPU time 0.72 seconds
Started Jun 24 06:01:47 PM PDT 24
Finished Jun 24 06:01:49 PM PDT 24
Peak memory 204784 kb
Host smart-f18c72de-82ed-4f08-9334-41aede8fff0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062068388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1062068388
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1323579086
Short name T195
Test name
Test status
Simulation time 11571464314 ps
CPU time 17.72 seconds
Started Jun 24 06:01:45 PM PDT 24
Finished Jun 24 06:02:03 PM PDT 24
Peak memory 213444 kb
Host smart-93705fe1-d251-4479-b0ad-3471a27a2358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323579086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1323579086
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3313870430
Short name T238
Test name
Test status
Simulation time 2017992228 ps
CPU time 2.54 seconds
Started Jun 24 06:01:47 PM PDT 24
Finished Jun 24 06:01:51 PM PDT 24
Peak memory 205100 kb
Host smart-6a4a4e12-0b7e-4c3a-b77a-b14f8ce9e69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313870430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3313870430
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2692215463
Short name T214
Test name
Test status
Simulation time 7062835735 ps
CPU time 8.67 seconds
Started Jun 24 06:01:46 PM PDT 24
Finished Jun 24 06:01:56 PM PDT 24
Peak memory 205056 kb
Host smart-7f95888f-2ed3-4a95-8f08-2bf388d6cdfd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2692215463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2692215463
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3767226470
Short name T235
Test name
Test status
Simulation time 3444344688 ps
CPU time 3.51 seconds
Started Jun 24 06:01:44 PM PDT 24
Finished Jun 24 06:01:48 PM PDT 24
Peak memory 205220 kb
Host smart-bcb74364-3827-4efd-b89f-2416c3b52bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767226470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3767226470
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.3467620608
Short name T130
Test name
Test status
Simulation time 4387665884 ps
CPU time 11.73 seconds
Started Jun 24 06:01:46 PM PDT 24
Finished Jun 24 06:01:59 PM PDT 24
Peak memory 204052 kb
Host smart-85554eb4-b8d9-4005-8f1e-6c4e2d96dc7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467620608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3467620608
Directory /workspace/9.rv_dm_stress_all/latest
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