Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
81.38 95.27 79.03 88.93 67.95 85.17 98.32 55.01


Total test records in report: 435
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T86 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.58081481 Jun 25 06:08:02 PM PDT 24 Jun 25 06:09:00 PM PDT 24 1488797180 ps
T302 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3714129891 Jun 25 06:08:14 PM PDT 24 Jun 25 06:08:30 PM PDT 24 8697254442 ps
T303 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1770856428 Jun 25 06:08:08 PM PDT 24 Jun 25 06:08:16 PM PDT 24 3653710628 ps
T87 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1091610430 Jun 25 06:08:45 PM PDT 24 Jun 25 06:08:50 PM PDT 24 201595583 ps
T88 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.612567037 Jun 25 06:08:17 PM PDT 24 Jun 25 06:09:14 PM PDT 24 14056590576 ps
T304 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3758190889 Jun 25 06:08:19 PM PDT 24 Jun 25 06:08:21 PM PDT 24 165269294 ps
T305 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3112002179 Jun 25 06:08:31 PM PDT 24 Jun 25 06:08:36 PM PDT 24 2020325436 ps
T306 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3474118976 Jun 25 06:08:02 PM PDT 24 Jun 25 06:08:13 PM PDT 24 6772074239 ps
T307 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2167919878 Jun 25 06:08:15 PM PDT 24 Jun 25 06:08:17 PM PDT 24 91274429 ps
T89 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.570938537 Jun 25 06:08:06 PM PDT 24 Jun 25 06:08:10 PM PDT 24 88915458 ps
T90 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3845683650 Jun 25 06:08:30 PM PDT 24 Jun 25 06:08:34 PM PDT 24 61988394 ps
T74 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.313378279 Jun 25 06:08:29 PM PDT 24 Jun 25 06:08:37 PM PDT 24 4917137105 ps
T91 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1349908923 Jun 25 06:08:51 PM PDT 24 Jun 25 06:09:00 PM PDT 24 2293173449 ps
T95 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3933686060 Jun 25 06:08:46 PM PDT 24 Jun 25 06:08:49 PM PDT 24 128744507 ps
T308 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.152705369 Jun 25 06:08:19 PM PDT 24 Jun 25 06:08:27 PM PDT 24 6431635639 ps
T309 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2366794673 Jun 25 06:08:04 PM PDT 24 Jun 25 06:08:08 PM PDT 24 296751059 ps
T310 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3235915255 Jun 25 06:08:09 PM PDT 24 Jun 25 06:08:12 PM PDT 24 34689264 ps
T96 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3090997364 Jun 25 06:08:13 PM PDT 24 Jun 25 06:08:18 PM PDT 24 483824766 ps
T75 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2594618353 Jun 25 06:08:04 PM PDT 24 Jun 25 06:08:08 PM PDT 24 119858276 ps
T311 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2465060059 Jun 25 06:08:04 PM PDT 24 Jun 25 06:08:07 PM PDT 24 234624762 ps
T76 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3267654568 Jun 25 06:08:17 PM PDT 24 Jun 25 06:08:21 PM PDT 24 903642877 ps
T312 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3462527580 Jun 25 06:08:11 PM PDT 24 Jun 25 06:09:00 PM PDT 24 65594253654 ps
T313 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2554166974 Jun 25 06:08:28 PM PDT 24 Jun 25 06:08:31 PM PDT 24 2219432956 ps
T77 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3477581802 Jun 25 06:08:48 PM PDT 24 Jun 25 06:08:52 PM PDT 24 180138581 ps
T314 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2801172620 Jun 25 06:08:28 PM PDT 24 Jun 25 06:08:30 PM PDT 24 204757079 ps
T104 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.434394180 Jun 25 06:08:28 PM PDT 24 Jun 25 06:08:31 PM PDT 24 291098781 ps
T78 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.158013913 Jun 25 06:08:37 PM PDT 24 Jun 25 06:08:45 PM PDT 24 1279910969 ps
T79 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.426318637 Jun 25 06:08:45 PM PDT 24 Jun 25 06:09:09 PM PDT 24 2883832455 ps
T315 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3704948791 Jun 25 06:08:04 PM PDT 24 Jun 25 06:10:14 PM PDT 24 103325573571 ps
T115 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1816778889 Jun 25 06:08:57 PM PDT 24 Jun 25 06:09:00 PM PDT 24 49603278 ps
T316 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2042201114 Jun 25 06:08:15 PM PDT 24 Jun 25 06:08:17 PM PDT 24 897127914 ps
T110 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.559768591 Jun 25 06:08:31 PM PDT 24 Jun 25 06:08:37 PM PDT 24 221211873 ps
T125 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.457466722 Jun 25 06:08:27 PM PDT 24 Jun 25 06:08:51 PM PDT 24 2583319953 ps
T317 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1420832689 Jun 25 06:08:13 PM PDT 24 Jun 25 06:08:17 PM PDT 24 1803384823 ps
T318 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.739708253 Jun 25 06:08:46 PM PDT 24 Jun 25 06:08:48 PM PDT 24 1030374143 ps
T80 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2461590235 Jun 25 06:08:04 PM PDT 24 Jun 25 06:08:10 PM PDT 24 115140453 ps
T126 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.706908749 Jun 25 06:08:05 PM PDT 24 Jun 25 06:08:24 PM PDT 24 2256289141 ps
T319 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1037551222 Jun 25 06:08:37 PM PDT 24 Jun 25 06:08:40 PM PDT 24 130764486 ps
T320 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4140318971 Jun 25 06:08:18 PM PDT 24 Jun 25 06:08:33 PM PDT 24 5434492789 ps
T321 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3474730348 Jun 25 06:08:19 PM PDT 24 Jun 25 06:08:21 PM PDT 24 110235176 ps
T322 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2891324297 Jun 25 06:08:45 PM PDT 24 Jun 25 06:08:46 PM PDT 24 250095084 ps
T127 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.936293669 Jun 25 06:08:29 PM PDT 24 Jun 25 06:08:48 PM PDT 24 4217876983 ps
T323 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1150707953 Jun 25 06:08:30 PM PDT 24 Jun 25 06:08:34 PM PDT 24 544774170 ps
T122 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.44524255 Jun 25 06:08:37 PM PDT 24 Jun 25 06:08:44 PM PDT 24 138814909 ps
T120 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.627420588 Jun 25 06:08:56 PM PDT 24 Jun 25 06:08:59 PM PDT 24 148502776 ps
T324 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4188127741 Jun 25 06:08:10 PM PDT 24 Jun 25 06:08:18 PM PDT 24 6545623718 ps
T325 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2929748256 Jun 25 06:07:52 PM PDT 24 Jun 25 06:07:56 PM PDT 24 1048956669 ps
T326 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.288086466 Jun 25 06:08:28 PM PDT 24 Jun 25 06:08:31 PM PDT 24 222602360 ps
T327 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2743203112 Jun 25 06:08:10 PM PDT 24 Jun 25 06:08:13 PM PDT 24 38212840 ps
T328 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.729520049 Jun 25 06:08:05 PM PDT 24 Jun 25 06:08:09 PM PDT 24 955957627 ps
T105 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2583812677 Jun 25 06:08:38 PM PDT 24 Jun 25 06:08:42 PM PDT 24 371472229 ps
T329 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2458935378 Jun 25 06:08:39 PM PDT 24 Jun 25 06:09:00 PM PDT 24 7692881044 ps
T330 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2844890748 Jun 25 06:07:56 PM PDT 24 Jun 25 06:08:00 PM PDT 24 1093791105 ps
T331 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.207672251 Jun 25 06:08:28 PM PDT 24 Jun 25 06:08:42 PM PDT 24 7224599920 ps
T128 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.817012900 Jun 25 06:08:03 PM PDT 24 Jun 25 06:08:21 PM PDT 24 7954088087 ps
T106 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.560387227 Jun 25 06:08:48 PM PDT 24 Jun 25 06:08:50 PM PDT 24 158730752 ps
T332 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.979635077 Jun 25 06:08:45 PM PDT 24 Jun 25 06:08:49 PM PDT 24 3872685357 ps
T333 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.522686533 Jun 25 06:08:02 PM PDT 24 Jun 25 06:08:05 PM PDT 24 304024627 ps
T334 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4056808776 Jun 25 06:08:19 PM PDT 24 Jun 25 06:08:47 PM PDT 24 17463466264 ps
T335 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4124970915 Jun 25 06:08:14 PM PDT 24 Jun 25 06:08:18 PM PDT 24 119036870 ps
T336 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1506204278 Jun 25 06:08:40 PM PDT 24 Jun 25 06:08:59 PM PDT 24 2208944581 ps
T195 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3976150012 Jun 25 06:08:19 PM PDT 24 Jun 25 06:08:55 PM PDT 24 2518951688 ps
T107 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1871881692 Jun 25 06:08:02 PM PDT 24 Jun 25 06:08:39 PM PDT 24 4389726838 ps
T337 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3188571729 Jun 25 06:08:48 PM PDT 24 Jun 25 06:08:55 PM PDT 24 3420915820 ps
T338 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1662351036 Jun 25 06:08:12 PM PDT 24 Jun 25 06:08:15 PM PDT 24 79242181 ps
T111 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1191432126 Jun 25 06:08:55 PM PDT 24 Jun 25 06:09:00 PM PDT 24 836700041 ps
T339 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2001694033 Jun 25 06:08:52 PM PDT 24 Jun 25 06:09:02 PM PDT 24 3131874804 ps
T108 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3127235901 Jun 25 06:08:19 PM PDT 24 Jun 25 06:08:23 PM PDT 24 91847554 ps
T340 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.766822232 Jun 25 06:08:05 PM PDT 24 Jun 25 06:11:21 PM PDT 24 148882549570 ps
T123 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1142830129 Jun 25 06:08:29 PM PDT 24 Jun 25 06:08:38 PM PDT 24 566209105 ps
T341 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2668505004 Jun 25 06:08:29 PM PDT 24 Jun 25 06:08:33 PM PDT 24 1320691290 ps
T342 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1292541692 Jun 25 06:08:04 PM PDT 24 Jun 25 06:08:08 PM PDT 24 436299639 ps
T343 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2903425483 Jun 25 06:08:04 PM PDT 24 Jun 25 06:09:59 PM PDT 24 78057040755 ps
T131 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2134462523 Jun 25 06:08:27 PM PDT 24 Jun 25 06:08:41 PM PDT 24 1415395808 ps
T344 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3209289941 Jun 25 06:08:45 PM PDT 24 Jun 25 06:08:51 PM PDT 24 7372317346 ps
T345 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2811065948 Jun 25 06:08:17 PM PDT 24 Jun 25 06:08:21 PM PDT 24 757414597 ps
T346 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4126371193 Jun 25 06:08:29 PM PDT 24 Jun 25 06:08:37 PM PDT 24 2176193745 ps
T347 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1204442385 Jun 25 06:08:28 PM PDT 24 Jun 25 06:08:35 PM PDT 24 314635980 ps
T112 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.255045292 Jun 25 06:08:46 PM PDT 24 Jun 25 06:08:51 PM PDT 24 229911911 ps
T348 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.810739170 Jun 25 06:08:40 PM PDT 24 Jun 25 06:08:47 PM PDT 24 579871608 ps
T97 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.169103510 Jun 25 06:08:50 PM PDT 24 Jun 25 06:08:55 PM PDT 24 468802414 ps
T349 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3858131014 Jun 25 06:08:38 PM PDT 24 Jun 25 06:10:13 PM PDT 24 55803766440 ps
T124 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3322044207 Jun 25 06:08:46 PM PDT 24 Jun 25 06:08:50 PM PDT 24 186469486 ps
T113 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2336756967 Jun 25 06:08:38 PM PDT 24 Jun 25 06:08:45 PM PDT 24 330129268 ps
T350 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3873733236 Jun 25 06:08:28 PM PDT 24 Jun 25 06:08:36 PM PDT 24 1701372209 ps
T351 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3004750895 Jun 25 06:08:45 PM PDT 24 Jun 25 06:09:09 PM PDT 24 12894193975 ps
T114 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3911918339 Jun 25 06:08:45 PM PDT 24 Jun 25 06:08:50 PM PDT 24 895466563 ps
T133 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1040631345 Jun 25 06:08:13 PM PDT 24 Jun 25 06:08:39 PM PDT 24 7619222501 ps
T352 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1838689983 Jun 25 06:08:28 PM PDT 24 Jun 25 06:08:40 PM PDT 24 3476542948 ps
T353 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1543211186 Jun 25 06:08:39 PM PDT 24 Jun 25 06:08:56 PM PDT 24 9983900156 ps
T354 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.905684441 Jun 25 06:07:52 PM PDT 24 Jun 25 06:07:55 PM PDT 24 533024145 ps
T355 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.763575641 Jun 25 06:08:16 PM PDT 24 Jun 25 06:08:17 PM PDT 24 54007889 ps
T356 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2315463832 Jun 25 06:08:04 PM PDT 24 Jun 25 06:08:08 PM PDT 24 340266295 ps
T357 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1265064899 Jun 25 06:08:29 PM PDT 24 Jun 25 06:08:50 PM PDT 24 2874177727 ps
T358 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3703027150 Jun 25 06:08:12 PM PDT 24 Jun 25 06:09:28 PM PDT 24 6762997002 ps
T109 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.389742827 Jun 25 06:08:40 PM PDT 24 Jun 25 06:08:45 PM PDT 24 1536634596 ps
T130 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.334575415 Jun 25 06:08:19 PM PDT 24 Jun 25 06:08:39 PM PDT 24 3070760878 ps
T359 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1925670929 Jun 25 06:08:48 PM PDT 24 Jun 25 06:08:53 PM PDT 24 689283078 ps
T360 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3823607286 Jun 25 06:08:56 PM PDT 24 Jun 25 06:09:01 PM PDT 24 896795010 ps
T361 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2210487001 Jun 25 06:08:37 PM PDT 24 Jun 25 06:08:39 PM PDT 24 178978665 ps
T362 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1963270932 Jun 25 06:08:27 PM PDT 24 Jun 25 06:08:35 PM PDT 24 2423674158 ps
T363 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.950365372 Jun 25 06:08:52 PM PDT 24 Jun 25 06:09:16 PM PDT 24 8534323723 ps
T364 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2812512790 Jun 25 06:08:19 PM PDT 24 Jun 25 06:08:22 PM PDT 24 1030595244 ps
T365 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.122479469 Jun 25 06:08:42 PM PDT 24 Jun 25 06:08:46 PM PDT 24 101623680 ps
T98 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3365516273 Jun 25 06:08:55 PM PDT 24 Jun 25 06:09:00 PM PDT 24 282092608 ps
T366 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.589608333 Jun 25 06:08:37 PM PDT 24 Jun 25 06:08:42 PM PDT 24 1549098203 ps
T367 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3282951396 Jun 25 06:08:45 PM PDT 24 Jun 25 06:08:51 PM PDT 24 410548016 ps
T368 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2673781154 Jun 25 06:08:28 PM PDT 24 Jun 25 06:08:40 PM PDT 24 12236163493 ps
T369 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2221628215 Jun 25 06:08:51 PM PDT 24 Jun 25 06:08:56 PM PDT 24 2603529063 ps
T370 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.501594495 Jun 25 06:07:53 PM PDT 24 Jun 25 06:07:56 PM PDT 24 696627541 ps
T99 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2580779891 Jun 25 06:08:19 PM PDT 24 Jun 25 06:09:35 PM PDT 24 9868019912 ps
T100 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1518631261 Jun 25 06:08:30 PM PDT 24 Jun 25 06:08:35 PM PDT 24 339642287 ps
T371 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.130663390 Jun 25 06:08:04 PM PDT 24 Jun 25 06:08:09 PM PDT 24 421639834 ps
T129 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2392759707 Jun 25 06:08:14 PM PDT 24 Jun 25 06:08:36 PM PDT 24 3265554953 ps
T372 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1872435643 Jun 25 06:08:45 PM PDT 24 Jun 25 06:09:13 PM PDT 24 37742386056 ps
T373 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.82691792 Jun 25 06:08:39 PM PDT 24 Jun 25 06:08:45 PM PDT 24 902776628 ps
T374 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3388232808 Jun 25 06:08:38 PM PDT 24 Jun 25 06:08:45 PM PDT 24 610415370 ps
T375 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3418432659 Jun 25 06:08:40 PM PDT 24 Jun 25 06:08:49 PM PDT 24 2284197929 ps
T376 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.320685373 Jun 25 06:08:18 PM PDT 24 Jun 25 06:08:32 PM PDT 24 17443238200 ps
T377 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3295358881 Jun 25 06:08:04 PM PDT 24 Jun 25 06:08:08 PM PDT 24 74212841 ps
T378 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.692647795 Jun 25 06:08:46 PM PDT 24 Jun 25 06:08:57 PM PDT 24 3946011896 ps
T379 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3925472211 Jun 25 06:08:47 PM PDT 24 Jun 25 06:08:51 PM PDT 24 4446757952 ps
T380 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2076398735 Jun 25 06:08:03 PM PDT 24 Jun 25 06:08:07 PM PDT 24 129922955 ps
T93 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2034785775 Jun 25 06:08:11 PM PDT 24 Jun 25 06:08:16 PM PDT 24 2167597020 ps
T381 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1462388427 Jun 25 06:08:29 PM PDT 24 Jun 25 06:08:43 PM PDT 24 3672435389 ps
T382 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2832641312 Jun 25 06:08:18 PM PDT 24 Jun 25 06:08:20 PM PDT 24 674761752 ps
T383 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1079607776 Jun 25 06:08:31 PM PDT 24 Jun 25 06:08:37 PM PDT 24 889554811 ps
T384 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2644647333 Jun 25 06:08:10 PM PDT 24 Jun 25 06:08:17 PM PDT 24 332732798 ps
T385 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.731116628 Jun 25 06:08:20 PM PDT 24 Jun 25 06:08:26 PM PDT 24 231334482 ps
T386 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3397941024 Jun 25 06:08:19 PM PDT 24 Jun 25 06:08:26 PM PDT 24 1375481280 ps
T387 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1708868718 Jun 25 06:08:51 PM PDT 24 Jun 25 06:08:57 PM PDT 24 2072183070 ps
T101 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2448009205 Jun 25 06:08:39 PM PDT 24 Jun 25 06:08:46 PM PDT 24 294299748 ps
T388 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3731022315 Jun 25 06:08:51 PM PDT 24 Jun 25 06:08:55 PM PDT 24 308032211 ps
T389 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.611030638 Jun 25 06:08:56 PM PDT 24 Jun 25 06:09:10 PM PDT 24 4457980329 ps
T390 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1119335564 Jun 25 06:08:11 PM PDT 24 Jun 25 06:08:20 PM PDT 24 1271520924 ps
T391 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3248471803 Jun 25 06:08:38 PM PDT 24 Jun 25 06:08:50 PM PDT 24 2667505913 ps
T392 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.458127752 Jun 25 06:08:55 PM PDT 24 Jun 25 06:09:05 PM PDT 24 5933628790 ps
T393 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2856483157 Jun 25 06:08:30 PM PDT 24 Jun 25 06:08:36 PM PDT 24 551491993 ps
T394 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.600882526 Jun 25 06:08:45 PM PDT 24 Jun 25 06:08:57 PM PDT 24 4208355582 ps
T395 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2295226641 Jun 25 06:07:54 PM PDT 24 Jun 25 06:08:15 PM PDT 24 7316279203 ps
T396 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.937562539 Jun 25 06:08:31 PM PDT 24 Jun 25 06:08:34 PM PDT 24 2236397089 ps
T397 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2089577705 Jun 25 06:08:42 PM PDT 24 Jun 25 06:09:02 PM PDT 24 7555325160 ps
T398 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2922570413 Jun 25 06:08:12 PM PDT 24 Jun 25 06:08:15 PM PDT 24 284606282 ps
T399 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.4051258125 Jun 25 06:08:03 PM PDT 24 Jun 25 06:08:10 PM PDT 24 6235498128 ps
T400 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1912039966 Jun 25 06:08:28 PM PDT 24 Jun 25 06:08:39 PM PDT 24 3631412342 ps
T132 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.468081739 Jun 25 06:08:51 PM PDT 24 Jun 25 06:09:11 PM PDT 24 2451592750 ps
T401 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1508411352 Jun 25 06:08:29 PM PDT 24 Jun 25 06:08:36 PM PDT 24 74641510 ps
T402 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4277042823 Jun 25 06:08:20 PM PDT 24 Jun 25 06:08:24 PM PDT 24 208734166 ps
T403 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2353881313 Jun 25 06:08:20 PM PDT 24 Jun 25 06:08:23 PM PDT 24 147836646 ps
T404 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3805981139 Jun 25 06:08:38 PM PDT 24 Jun 25 06:08:46 PM PDT 24 388875492 ps
T405 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1780071357 Jun 25 06:08:14 PM PDT 24 Jun 25 06:09:34 PM PDT 24 117192846636 ps
T406 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1550092424 Jun 25 06:08:47 PM PDT 24 Jun 25 06:08:49 PM PDT 24 303808089 ps
T407 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3098659961 Jun 25 06:08:28 PM PDT 24 Jun 25 06:08:30 PM PDT 24 882364474 ps
T408 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.400793900 Jun 25 06:09:00 PM PDT 24 Jun 25 06:09:03 PM PDT 24 236678092 ps
T94 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3274916216 Jun 25 06:07:55 PM PDT 24 Jun 25 06:08:00 PM PDT 24 1144430506 ps
T409 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4033591577 Jun 25 06:08:41 PM PDT 24 Jun 25 06:08:58 PM PDT 24 15117667570 ps
T410 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1802005440 Jun 25 06:08:51 PM PDT 24 Jun 25 06:08:57 PM PDT 24 509621714 ps
T411 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3247813872 Jun 25 06:08:56 PM PDT 24 Jun 25 06:09:01 PM PDT 24 6451665421 ps
T412 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3578446174 Jun 25 06:08:40 PM PDT 24 Jun 25 06:08:43 PM PDT 24 55235713 ps
T413 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1087626525 Jun 25 06:08:45 PM PDT 24 Jun 25 06:08:48 PM PDT 24 50635465 ps
T414 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2877129921 Jun 25 06:08:38 PM PDT 24 Jun 25 06:08:41 PM PDT 24 208884869 ps
T415 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.733191619 Jun 25 06:07:55 PM PDT 24 Jun 25 06:09:15 PM PDT 24 8054475253 ps
T416 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3933623903 Jun 25 06:08:09 PM PDT 24 Jun 25 06:08:43 PM PDT 24 10402459044 ps
T417 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3726609736 Jun 25 06:08:55 PM PDT 24 Jun 25 06:09:18 PM PDT 24 3196072310 ps
T102 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3600753765 Jun 25 06:08:29 PM PDT 24 Jun 25 06:08:38 PM PDT 24 558636442 ps
T418 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.638093628 Jun 25 06:08:11 PM PDT 24 Jun 25 06:08:15 PM PDT 24 3921922649 ps
T419 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.485843651 Jun 25 06:08:19 PM PDT 24 Jun 25 06:09:34 PM PDT 24 55031645560 ps
T420 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.947821559 Jun 25 06:08:28 PM PDT 24 Jun 25 06:08:31 PM PDT 24 52704570 ps
T421 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.200674700 Jun 25 06:08:27 PM PDT 24 Jun 25 06:08:38 PM PDT 24 12154126124 ps
T422 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1280347633 Jun 25 06:08:19 PM PDT 24 Jun 25 06:08:33 PM PDT 24 4419947308 ps
T423 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3097762524 Jun 25 06:08:39 PM PDT 24 Jun 25 06:08:51 PM PDT 24 1423727235 ps
T424 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1136962418 Jun 25 06:08:17 PM PDT 24 Jun 25 06:08:23 PM PDT 24 1922908789 ps
T425 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1558010526 Jun 25 06:08:41 PM PDT 24 Jun 25 06:08:45 PM PDT 24 113558501 ps
T426 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1649556094 Jun 25 06:08:17 PM PDT 24 Jun 25 06:08:20 PM PDT 24 99331963 ps
T427 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3467491994 Jun 25 06:08:14 PM PDT 24 Jun 25 06:08:17 PM PDT 24 369201764 ps
T428 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3857841837 Jun 25 06:08:11 PM PDT 24 Jun 25 06:09:25 PM PDT 24 20546836536 ps
T429 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.485714312 Jun 25 06:08:05 PM PDT 24 Jun 25 06:08:11 PM PDT 24 2620438767 ps
T430 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3810104630 Jun 25 06:08:40 PM PDT 24 Jun 25 06:08:43 PM PDT 24 140522497 ps
T103 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1678168196 Jun 25 06:08:04 PM PDT 24 Jun 25 06:08:09 PM PDT 24 432106787 ps
T431 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3854911525 Jun 25 06:08:19 PM PDT 24 Jun 25 06:08:27 PM PDT 24 186527465 ps
T432 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2889548166 Jun 25 06:08:41 PM PDT 24 Jun 25 06:08:45 PM PDT 24 83380087 ps
T433 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.84034630 Jun 25 06:08:04 PM PDT 24 Jun 25 06:08:11 PM PDT 24 99727692 ps
T434 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1085677597 Jun 25 06:08:11 PM PDT 24 Jun 25 06:08:16 PM PDT 24 1086287579 ps
T134 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3274092189 Jun 25 06:08:39 PM PDT 24 Jun 25 06:08:53 PM PDT 24 4571916784 ps
T435 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.829093945 Jun 25 06:08:46 PM PDT 24 Jun 25 06:09:00 PM PDT 24 5090819911 ps

Test location /workspace/coverage/default/4.rv_dm_stress_all.1908981696
Short name T2
Test name
Test status
Simulation time 6446130464 ps
CPU time 3.88 seconds
Started Jun 25 05:25:46 PM PDT 24
Finished Jun 25 05:25:51 PM PDT 24
Peak memory 213400 kb
Host smart-a5890d74-6d14-44d8-9683-c591085b69bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908981696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1908981696
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1408789590
Short name T25
Test name
Test status
Simulation time 12277831883 ps
CPU time 30.65 seconds
Started Jun 25 05:25:27 PM PDT 24
Finished Jun 25 05:26:01 PM PDT 24
Peak memory 213584 kb
Host smart-0abaef58-a8ff-4598-918d-14fd2c7ef7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408789590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1408789590
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3275027102
Short name T69
Test name
Test status
Simulation time 292529027 ps
CPU time 4.4 seconds
Started Jun 25 06:08:12 PM PDT 24
Finished Jun 25 06:08:18 PM PDT 24
Peak memory 221576 kb
Host smart-b6466ecb-a1e4-4fc0-a064-ae256ebd6843
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275027102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3275027102
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.3575742149
Short name T7
Test name
Test status
Simulation time 16670895926 ps
CPU time 23.68 seconds
Started Jun 25 05:26:07 PM PDT 24
Finished Jun 25 05:26:32 PM PDT 24
Peak memory 205200 kb
Host smart-d0e780b8-2476-4b35-a838-2b85f110a1ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575742149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3575742149
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.671425051
Short name T44
Test name
Test status
Simulation time 47687202 ps
CPU time 0.78 seconds
Started Jun 25 05:25:56 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 204964 kb
Host smart-6d7f9d08-d3ef-44a8-afe1-86aa3bd15ff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671425051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.671425051
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3999843183
Short name T64
Test name
Test status
Simulation time 2272989957 ps
CPU time 15.19 seconds
Started Jun 25 06:08:53 PM PDT 24
Finished Jun 25 06:09:09 PM PDT 24
Peak memory 213500 kb
Host smart-0486b212-50b4-4cbb-985a-9cb19fce14e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999843183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
999843183
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.2571331492
Short name T35
Test name
Test status
Simulation time 151886716 ps
CPU time 0.93 seconds
Started Jun 25 05:25:28 PM PDT 24
Finished Jun 25 05:25:32 PM PDT 24
Peak memory 223460 kb
Host smart-6f9c085e-5e74-4c63-b58b-72f48b942152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571331492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2571331492
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1871881692
Short name T107
Test name
Test status
Simulation time 4389726838 ps
CPU time 34.63 seconds
Started Jun 25 06:08:02 PM PDT 24
Finished Jun 25 06:08:39 PM PDT 24
Peak memory 205112 kb
Host smart-508d5d4f-868f-45d5-9509-ec1f067b7f5c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871881692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1871881692
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2293123050
Short name T20
Test name
Test status
Simulation time 732048073 ps
CPU time 1.15 seconds
Started Jun 25 05:25:28 PM PDT 24
Finished Jun 25 05:25:32 PM PDT 24
Peak memory 204932 kb
Host smart-719814b4-f631-4f7b-b82e-b3a6a0681506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293123050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2293123050
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3899411438
Short name T56
Test name
Test status
Simulation time 275822942 ps
CPU time 1.29 seconds
Started Jun 25 05:25:40 PM PDT 24
Finished Jun 25 05:25:42 PM PDT 24
Peak memory 237436 kb
Host smart-b4660ae0-e2d0-42e0-91f3-93c449998e9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899411438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3899411438
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.817012900
Short name T128
Test name
Test status
Simulation time 7954088087 ps
CPU time 16.66 seconds
Started Jun 25 06:08:03 PM PDT 24
Finished Jun 25 06:08:21 PM PDT 24
Peak memory 213476 kb
Host smart-dae0efde-2a19-4b21-acd7-72dff03c89ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817012900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.817012900
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.3394232156
Short name T11
Test name
Test status
Simulation time 6031895631 ps
CPU time 17.35 seconds
Started Jun 25 05:26:13 PM PDT 24
Finished Jun 25 05:26:32 PM PDT 24
Peak memory 205284 kb
Host smart-b781d4a0-0738-43f4-9a11-99b838c8dcd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394232156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3394232156
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.549813174
Short name T49
Test name
Test status
Simulation time 238717873 ps
CPU time 1.22 seconds
Started Jun 25 05:25:42 PM PDT 24
Finished Jun 25 05:25:45 PM PDT 24
Peak memory 204788 kb
Host smart-be5a1518-8e9e-465f-b5ed-91cfdfb02d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549813174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.549813174
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2120551256
Short name T202
Test name
Test status
Simulation time 2957826933 ps
CPU time 8.42 seconds
Started Jun 25 05:25:43 PM PDT 24
Finished Jun 25 05:25:54 PM PDT 24
Peak memory 205352 kb
Host smart-296dd25c-235b-4a5b-b50b-3b6038d224c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120551256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2120551256
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3090997364
Short name T96
Test name
Test status
Simulation time 483824766 ps
CPU time 2.7 seconds
Started Jun 25 06:08:13 PM PDT 24
Finished Jun 25 06:08:18 PM PDT 24
Peak memory 213516 kb
Host smart-f21d931c-be21-46b1-afcd-50b9e9e63ffa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090997364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3090997364
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3277084374
Short name T47
Test name
Test status
Simulation time 53972928 ps
CPU time 0.82 seconds
Started Jun 25 05:25:30 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 215788 kb
Host smart-5c59282f-75be-4fed-ba1b-fcd6b3d7536a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277084374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3277084374
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.1935059430
Short name T16
Test name
Test status
Simulation time 6723877564 ps
CPU time 7.78 seconds
Started Jun 25 05:26:04 PM PDT 24
Finished Jun 25 05:26:13 PM PDT 24
Peak memory 205152 kb
Host smart-a37b324c-1795-4230-ad9d-c839a2d02b55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935059430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1935059430
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.1823761958
Short name T23
Test name
Test status
Simulation time 1686393302 ps
CPU time 2.63 seconds
Started Jun 25 05:25:54 PM PDT 24
Finished Jun 25 05:25:59 PM PDT 24
Peak memory 205076 kb
Host smart-044ab933-ef75-4ac4-9638-69b7e4414d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823761958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.1823761958
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1219280030
Short name T26
Test name
Test status
Simulation time 9800686109 ps
CPU time 28.92 seconds
Started Jun 25 05:25:35 PM PDT 24
Finished Jun 25 05:26:05 PM PDT 24
Peak memory 213584 kb
Host smart-1a591913-5336-4f7b-98d2-9fc81e415824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219280030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1219280030
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3671127316
Short name T83
Test name
Test status
Simulation time 238540532 ps
CPU time 3.75 seconds
Started Jun 25 06:08:02 PM PDT 24
Finished Jun 25 06:08:07 PM PDT 24
Peak memory 205164 kb
Host smart-52339194-d5ef-43b3-8210-90c6e5a44621
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671127316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3671127316
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3474118976
Short name T306
Test name
Test status
Simulation time 6772074239 ps
CPU time 9.7 seconds
Started Jun 25 06:08:02 PM PDT 24
Finished Jun 25 06:08:13 PM PDT 24
Peak memory 205000 kb
Host smart-26b1decc-f407-4ef2-aa21-95bf60b2ac84
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474118976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3474118976
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.4020277815
Short name T18
Test name
Test status
Simulation time 538828838 ps
CPU time 1.54 seconds
Started Jun 25 05:25:32 PM PDT 24
Finished Jun 25 05:25:35 PM PDT 24
Peak memory 204904 kb
Host smart-c5bd76bf-cf03-4f51-9b21-951d0376607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020277815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.4020277815
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.89237309
Short name T55
Test name
Test status
Simulation time 252114841 ps
CPU time 1.41 seconds
Started Jun 25 05:25:28 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 204924 kb
Host smart-dd18b97d-3ae9-4ab1-967a-f6a96a91461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89237309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.89237309
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.185150210
Short name T21
Test name
Test status
Simulation time 4059987886 ps
CPU time 4.25 seconds
Started Jun 25 05:25:58 PM PDT 24
Finished Jun 25 05:26:04 PM PDT 24
Peak memory 205216 kb
Host smart-c386c37d-c727-4afb-accc-9094983dbd63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185150210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.185150210
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3274092189
Short name T134
Test name
Test status
Simulation time 4571916784 ps
CPU time 11.77 seconds
Started Jun 25 06:08:39 PM PDT 24
Finished Jun 25 06:08:53 PM PDT 24
Peak memory 213448 kb
Host smart-bc61648e-a5fa-4fd8-bd73-b9620b009fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274092189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
274092189
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.843133967
Short name T117
Test name
Test status
Simulation time 65608459 ps
CPU time 0.91 seconds
Started Jun 25 05:25:58 PM PDT 24
Finished Jun 25 05:26:01 PM PDT 24
Peak memory 204980 kb
Host smart-2ee1a47b-1656-4525-ba50-13302229b5db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843133967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.843133967
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1142830129
Short name T123
Test name
Test status
Simulation time 566209105 ps
CPU time 6.67 seconds
Started Jun 25 06:08:29 PM PDT 24
Finished Jun 25 06:08:38 PM PDT 24
Peak memory 213476 kb
Host smart-1722cb73-fcc8-4e98-bc8f-145732c9f9d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142830129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1142830129
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3274916216
Short name T94
Test name
Test status
Simulation time 1144430506 ps
CPU time 3.81 seconds
Started Jun 25 06:07:55 PM PDT 24
Finished Jun 25 06:08:00 PM PDT 24
Peak memory 204960 kb
Host smart-2934642d-d216-43de-afe7-043ef86e2479
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274916216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3274916216
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3614434434
Short name T29
Test name
Test status
Simulation time 10580352477 ps
CPU time 14.7 seconds
Started Jun 25 05:25:44 PM PDT 24
Finished Jun 25 05:26:00 PM PDT 24
Peak memory 213556 kb
Host smart-fa60f477-ecb5-43a6-b1b6-17b2520a8a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614434434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3614434434
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1012314266
Short name T45
Test name
Test status
Simulation time 538592347 ps
CPU time 1.53 seconds
Started Jun 25 05:25:43 PM PDT 24
Finished Jun 25 05:25:51 PM PDT 24
Peak memory 204780 kb
Host smart-c3a7b373-9433-4f59-8f2b-a5c2b7b7426b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012314266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1012314266
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.706908749
Short name T126
Test name
Test status
Simulation time 2256289141 ps
CPU time 17.1 seconds
Started Jun 25 06:08:05 PM PDT 24
Finished Jun 25 06:08:24 PM PDT 24
Peak memory 213352 kb
Host smart-553a8b56-ce95-4388-9d45-6c947c1108a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706908749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.706908749
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1518631261
Short name T100
Test name
Test status
Simulation time 339642287 ps
CPU time 2.45 seconds
Started Jun 25 06:08:30 PM PDT 24
Finished Jun 25 06:08:35 PM PDT 24
Peak memory 213304 kb
Host smart-363084fa-4861-4909-8b47-15f385cfa9c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518631261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1518631261
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.158013913
Short name T78
Test name
Test status
Simulation time 1279910969 ps
CPU time 5.86 seconds
Started Jun 25 06:08:37 PM PDT 24
Finished Jun 25 06:08:45 PM PDT 24
Peak memory 219700 kb
Host smart-578984e7-6196-4b64-bb71-0a805c9676bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158013913 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.158013913
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.733191619
Short name T415
Test name
Test status
Simulation time 8054475253 ps
CPU time 78.16 seconds
Started Jun 25 06:07:55 PM PDT 24
Finished Jun 25 06:09:15 PM PDT 24
Peak memory 204996 kb
Host smart-876733bd-904e-4c38-bd96-0816e04aa22b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733191619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.733191619
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3933623903
Short name T416
Test name
Test status
Simulation time 10402459044 ps
CPU time 32.58 seconds
Started Jun 25 06:08:09 PM PDT 24
Finished Jun 25 06:08:43 PM PDT 24
Peak memory 213396 kb
Host smart-f27484c3-fe74-4a6d-a114-6b7744eba137
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933623903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3933623903
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3295358881
Short name T377
Test name
Test status
Simulation time 74212841 ps
CPU time 1.71 seconds
Started Jun 25 06:08:04 PM PDT 24
Finished Jun 25 06:08:08 PM PDT 24
Peak memory 213204 kb
Host smart-56f4231f-1b1d-41be-8da2-2cec5b59956a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295358881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3295358881
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.522686533
Short name T333
Test name
Test status
Simulation time 304024627 ps
CPU time 2.47 seconds
Started Jun 25 06:08:02 PM PDT 24
Finished Jun 25 06:08:05 PM PDT 24
Peak memory 213392 kb
Host smart-aafda1c6-58c3-4199-944a-a6e50891a3e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522686533 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.522686533
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.570938537
Short name T89
Test name
Test status
Simulation time 88915458 ps
CPU time 2.07 seconds
Started Jun 25 06:08:06 PM PDT 24
Finished Jun 25 06:08:10 PM PDT 24
Peak memory 213212 kb
Host smart-7e45058a-65a0-4c2f-86ba-ebb2e49d369d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570938537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.570938537
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.766822232
Short name T340
Test name
Test status
Simulation time 148882549570 ps
CPU time 193.26 seconds
Started Jun 25 06:08:05 PM PDT 24
Finished Jun 25 06:11:21 PM PDT 24
Peak memory 206216 kb
Host smart-1b73f2d7-ed55-4d21-a61f-989595ec5d86
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766822232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.766822232
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2903425483
Short name T343
Test name
Test status
Simulation time 78057040755 ps
CPU time 111.72 seconds
Started Jun 25 06:08:04 PM PDT 24
Finished Jun 25 06:09:59 PM PDT 24
Peak memory 205052 kb
Host smart-829ebeac-58b1-4343-a054-f637d0b3d7b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903425483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.2903425483
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2844890748
Short name T330
Test name
Test status
Simulation time 1093791105 ps
CPU time 2.65 seconds
Started Jun 25 06:07:56 PM PDT 24
Finished Jun 25 06:08:00 PM PDT 24
Peak memory 204888 kb
Host smart-eb984791-b4a2-4cec-9afd-066a71235886
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844890748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
844890748
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2929748256
Short name T325
Test name
Test status
Simulation time 1048956669 ps
CPU time 2.21 seconds
Started Jun 25 06:07:52 PM PDT 24
Finished Jun 25 06:07:56 PM PDT 24
Peak memory 204788 kb
Host smart-106db06b-183d-469a-b318-0580e25baa11
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929748256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2929748256
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2295226641
Short name T395
Test name
Test status
Simulation time 7316279203 ps
CPU time 19.61 seconds
Started Jun 25 06:07:54 PM PDT 24
Finished Jun 25 06:08:15 PM PDT 24
Peak memory 204928 kb
Host smart-194870ae-7f03-4cb2-a093-5c1334141e42
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295226641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2295226641
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.501594495
Short name T370
Test name
Test status
Simulation time 696627541 ps
CPU time 1.19 seconds
Started Jun 25 06:07:53 PM PDT 24
Finished Jun 25 06:07:56 PM PDT 24
Peak memory 204752 kb
Host smart-b5d23913-d815-45c0-a6e3-3c138f242045
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501594495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_hw_reset.501594495
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.905684441
Short name T354
Test name
Test status
Simulation time 533024145 ps
CPU time 2.09 seconds
Started Jun 25 06:07:52 PM PDT 24
Finished Jun 25 06:07:55 PM PDT 24
Peak memory 204756 kb
Host smart-914e831f-a6b3-40bc-885e-c7984e6cba09
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905684441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.905684441
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1179161339
Short name T297
Test name
Test status
Simulation time 25597469 ps
CPU time 0.73 seconds
Started Jun 25 06:08:03 PM PDT 24
Finished Jun 25 06:08:05 PM PDT 24
Peak memory 204820 kb
Host smart-f649503a-55a1-48a4-92a2-0c4b237fcabd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179161339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1179161339
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2366794673
Short name T309
Test name
Test status
Simulation time 296751059 ps
CPU time 0.68 seconds
Started Jun 25 06:08:04 PM PDT 24
Finished Jun 25 06:08:08 PM PDT 24
Peak memory 204756 kb
Host smart-5dba8ca2-5c80-448f-b51a-b93cd3783b66
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366794673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2366794673
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2594618353
Short name T75
Test name
Test status
Simulation time 119858276 ps
CPU time 2.42 seconds
Started Jun 25 06:08:04 PM PDT 24
Finished Jun 25 06:08:08 PM PDT 24
Peak memory 213380 kb
Host smart-67b27059-fd93-44b3-a819-60e46db9db7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594618353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2594618353
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.58081481
Short name T86
Test name
Test status
Simulation time 1488797180 ps
CPU time 57.94 seconds
Started Jun 25 06:08:02 PM PDT 24
Finished Jun 25 06:09:00 PM PDT 24
Peak memory 213312 kb
Host smart-77ec9fd7-6b27-4764-b67d-8b82287b4c59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58081481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.58081481
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1678168196
Short name T103
Test name
Test status
Simulation time 432106787 ps
CPU time 2.69 seconds
Started Jun 25 06:08:04 PM PDT 24
Finished Jun 25 06:08:09 PM PDT 24
Peak memory 213376 kb
Host smart-f24d8608-9889-4b8c-a458-a2c8a9290c35
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678168196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1678168196
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.485714312
Short name T429
Test name
Test status
Simulation time 2620438767 ps
CPU time 2.73 seconds
Started Jun 25 06:08:05 PM PDT 24
Finished Jun 25 06:08:11 PM PDT 24
Peak memory 217740 kb
Host smart-c2110647-0265-4eea-afcd-0b067d76c8e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485714312 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.485714312
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.130663390
Short name T371
Test name
Test status
Simulation time 421639834 ps
CPU time 2.34 seconds
Started Jun 25 06:08:04 PM PDT 24
Finished Jun 25 06:08:09 PM PDT 24
Peak memory 213328 kb
Host smart-d3b98588-50ca-498f-85c2-35f4c16a58d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130663390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.130663390
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3704948791
Short name T315
Test name
Test status
Simulation time 103325573571 ps
CPU time 127.13 seconds
Started Jun 25 06:08:04 PM PDT 24
Finished Jun 25 06:10:14 PM PDT 24
Peak memory 204996 kb
Host smart-b5eb3767-2826-4045-bbd1-1e52816bc1d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704948791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3704948791
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.592291625
Short name T290
Test name
Test status
Simulation time 76525129709 ps
CPU time 178.32 seconds
Started Jun 25 06:08:03 PM PDT 24
Finished Jun 25 06:11:03 PM PDT 24
Peak memory 205016 kb
Host smart-aa95be66-c3f9-431f-bd45-ee598ce9dbff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592291625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r
v_dm_jtag_dmi_csr_bit_bash.592291625
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.4051258125
Short name T399
Test name
Test status
Simulation time 6235498128 ps
CPU time 5.09 seconds
Started Jun 25 06:08:03 PM PDT 24
Finished Jun 25 06:08:10 PM PDT 24
Peak memory 205068 kb
Host smart-44501bb5-b1cd-464e-bf6f-4fd9b0a37cc2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051258125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.4051258125
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.729520049
Short name T328
Test name
Test status
Simulation time 955957627 ps
CPU time 2.13 seconds
Started Jun 25 06:08:05 PM PDT 24
Finished Jun 25 06:08:09 PM PDT 24
Peak memory 204948 kb
Host smart-82093ffe-4550-4732-b70d-1c2d4a6705de
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729520049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.729520049
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2465060059
Short name T311
Test name
Test status
Simulation time 234624762 ps
CPU time 0.84 seconds
Started Jun 25 06:08:04 PM PDT 24
Finished Jun 25 06:08:07 PM PDT 24
Peak memory 204680 kb
Host smart-8a2813c0-3df7-4cea-932c-e82b2f718594
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465060059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2465060059
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2315463832
Short name T356
Test name
Test status
Simulation time 340266295 ps
CPU time 1.52 seconds
Started Jun 25 06:08:04 PM PDT 24
Finished Jun 25 06:08:08 PM PDT 24
Peak memory 204736 kb
Host smart-bf295f41-f8c7-4547-adde-22dde54bfb99
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315463832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2315463832
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2922570413
Short name T398
Test name
Test status
Simulation time 284606282 ps
CPU time 0.87 seconds
Started Jun 25 06:08:12 PM PDT 24
Finished Jun 25 06:08:15 PM PDT 24
Peak memory 204992 kb
Host smart-66ffccac-71b4-4d28-a56c-bbf7a7f019f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922570413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
922570413
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2743203112
Short name T327
Test name
Test status
Simulation time 38212840 ps
CPU time 0.75 seconds
Started Jun 25 06:08:10 PM PDT 24
Finished Jun 25 06:08:13 PM PDT 24
Peak memory 205060 kb
Host smart-01856df9-cc93-4139-8d48-42b6d32cc259
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743203112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2743203112
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2076398735
Short name T380
Test name
Test status
Simulation time 129922955 ps
CPU time 1.02 seconds
Started Jun 25 06:08:03 PM PDT 24
Finished Jun 25 06:08:07 PM PDT 24
Peak memory 204776 kb
Host smart-05223a4a-0f73-49f8-bc93-9dc9e09ac117
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076398735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2076398735
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.84034630
Short name T433
Test name
Test status
Simulation time 99727692 ps
CPU time 3.6 seconds
Started Jun 25 06:08:04 PM PDT 24
Finished Jun 25 06:08:11 PM PDT 24
Peak memory 205208 kb
Host smart-3c688807-2d90-44a0-a443-c30b334f6c7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84034630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_cs
r_outstanding.84034630
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2461590235
Short name T80
Test name
Test status
Simulation time 115140453 ps
CPU time 2.57 seconds
Started Jun 25 06:08:04 PM PDT 24
Finished Jun 25 06:08:10 PM PDT 24
Peak memory 213332 kb
Host smart-f07ce2c0-8a41-4ac5-9394-62873a35174a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461590235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2461590235
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.82691792
Short name T373
Test name
Test status
Simulation time 902776628 ps
CPU time 4.18 seconds
Started Jun 25 06:08:39 PM PDT 24
Finished Jun 25 06:08:45 PM PDT 24
Peak memory 219252 kb
Host smart-dad5aec8-e1c9-473c-9427-1a5b7f707ddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82691792 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.82691792
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2583812677
Short name T105
Test name
Test status
Simulation time 371472229 ps
CPU time 2.54 seconds
Started Jun 25 06:08:38 PM PDT 24
Finished Jun 25 06:08:42 PM PDT 24
Peak memory 213404 kb
Host smart-66c362f8-ed09-424d-bd82-cd8d5648e7a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583812677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2583812677
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2554166974
Short name T313
Test name
Test status
Simulation time 2219432956 ps
CPU time 2.31 seconds
Started Jun 25 06:08:28 PM PDT 24
Finished Jun 25 06:08:31 PM PDT 24
Peak memory 205020 kb
Host smart-f08468b6-4dc4-456d-87d7-a93811c7b3b3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554166974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.2554166974
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1462388427
Short name T381
Test name
Test status
Simulation time 3672435389 ps
CPU time 11.45 seconds
Started Jun 25 06:08:29 PM PDT 24
Finished Jun 25 06:08:43 PM PDT 24
Peak memory 205032 kb
Host smart-f9a00ec2-88ce-40f0-a58b-6b94f2756f8d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462388427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1462388427
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3098659961
Short name T407
Test name
Test status
Simulation time 882364474 ps
CPU time 1.56 seconds
Started Jun 25 06:08:28 PM PDT 24
Finished Jun 25 06:08:30 PM PDT 24
Peak memory 204772 kb
Host smart-14f6465d-3b80-4272-9de1-8ff99c1131bf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098659961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3098659961
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.169103510
Short name T97
Test name
Test status
Simulation time 468802414 ps
CPU time 3.64 seconds
Started Jun 25 06:08:50 PM PDT 24
Finished Jun 25 06:08:55 PM PDT 24
Peak memory 205216 kb
Host smart-313baaeb-e063-4743-b984-5ada9262220d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169103510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.169103510
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3805981139
Short name T404
Test name
Test status
Simulation time 388875492 ps
CPU time 6.47 seconds
Started Jun 25 06:08:38 PM PDT 24
Finished Jun 25 06:08:46 PM PDT 24
Peak memory 213392 kb
Host smart-e73aedb8-fe80-4451-8975-11f1357634f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805981139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3805981139
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1506204278
Short name T336
Test name
Test status
Simulation time 2208944581 ps
CPU time 16.99 seconds
Started Jun 25 06:08:40 PM PDT 24
Finished Jun 25 06:08:59 PM PDT 24
Peak memory 213432 kb
Host smart-0ead06af-f4e8-4272-b02b-17ea8d17f3cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506204278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
506204278
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1708868718
Short name T387
Test name
Test status
Simulation time 2072183070 ps
CPU time 5.44 seconds
Started Jun 25 06:08:51 PM PDT 24
Finished Jun 25 06:08:57 PM PDT 24
Peak memory 219516 kb
Host smart-d7556747-2d19-41f7-9bce-02b72899576a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708868718 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1708868718
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2889548166
Short name T432
Test name
Test status
Simulation time 83380087 ps
CPU time 2.18 seconds
Started Jun 25 06:08:41 PM PDT 24
Finished Jun 25 06:08:45 PM PDT 24
Peak memory 213324 kb
Host smart-7910d398-59af-4101-a7b5-807d55350abb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889548166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2889548166
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4033591577
Short name T409
Test name
Test status
Simulation time 15117667570 ps
CPU time 15.7 seconds
Started Jun 25 06:08:41 PM PDT 24
Finished Jun 25 06:08:58 PM PDT 24
Peak memory 205056 kb
Host smart-03566da6-4f19-4072-96e1-f4fe50950366
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033591577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.4033591577
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2458935378
Short name T329
Test name
Test status
Simulation time 7692881044 ps
CPU time 18.58 seconds
Started Jun 25 06:08:39 PM PDT 24
Finished Jun 25 06:09:00 PM PDT 24
Peak memory 205032 kb
Host smart-ab229b07-4008-4206-8a3e-64295382c875
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458935378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2458935378
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3810104630
Short name T430
Test name
Test status
Simulation time 140522497 ps
CPU time 1.11 seconds
Started Jun 25 06:08:40 PM PDT 24
Finished Jun 25 06:08:43 PM PDT 24
Peak memory 204776 kb
Host smart-840525a0-f81b-4976-8620-96c491d12aec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810104630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3810104630
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2448009205
Short name T101
Test name
Test status
Simulation time 294299748 ps
CPU time 4.31 seconds
Started Jun 25 06:08:39 PM PDT 24
Finished Jun 25 06:08:46 PM PDT 24
Peak memory 205168 kb
Host smart-659e6a60-af71-4e7e-bd4e-2ed6a18c5499
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448009205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2448009205
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.810739170
Short name T348
Test name
Test status
Simulation time 579871608 ps
CPU time 5.89 seconds
Started Jun 25 06:08:40 PM PDT 24
Finished Jun 25 06:08:47 PM PDT 24
Peak memory 213284 kb
Host smart-e1cfc71d-1f04-47eb-8881-f7396e43b7a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810739170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.810739170
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3248471803
Short name T391
Test name
Test status
Simulation time 2667505913 ps
CPU time 10.29 seconds
Started Jun 25 06:08:38 PM PDT 24
Finished Jun 25 06:08:50 PM PDT 24
Peak memory 213436 kb
Host smart-6ec635d4-9d40-4b59-8698-9fde27630578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248471803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
248471803
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.122479469
Short name T365
Test name
Test status
Simulation time 101623680 ps
CPU time 2.25 seconds
Started Jun 25 06:08:42 PM PDT 24
Finished Jun 25 06:08:46 PM PDT 24
Peak memory 213268 kb
Host smart-c77854e7-9e78-4e7c-8bf3-a509f92b6c05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122479469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.122479469
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2851557934
Short name T296
Test name
Test status
Simulation time 45455826108 ps
CPU time 92.99 seconds
Started Jun 25 06:08:51 PM PDT 24
Finished Jun 25 06:10:25 PM PDT 24
Peak memory 205044 kb
Host smart-458968c6-bd8c-4670-a8db-4ab265991d68
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851557934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2851557934
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1543211186
Short name T353
Test name
Test status
Simulation time 9983900156 ps
CPU time 15.54 seconds
Started Jun 25 06:08:39 PM PDT 24
Finished Jun 25 06:08:56 PM PDT 24
Peak memory 205032 kb
Host smart-c3923920-c636-44d0-81f7-e23f5e6479fc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543211186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1543211186
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2210487001
Short name T361
Test name
Test status
Simulation time 178978665 ps
CPU time 1.08 seconds
Started Jun 25 06:08:37 PM PDT 24
Finished Jun 25 06:08:39 PM PDT 24
Peak memory 204748 kb
Host smart-5474721d-d1f1-4baf-b2cd-fecf540211db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210487001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2210487001
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1349908923
Short name T91
Test name
Test status
Simulation time 2293173449 ps
CPU time 7.95 seconds
Started Jun 25 06:08:51 PM PDT 24
Finished Jun 25 06:09:00 PM PDT 24
Peak memory 205144 kb
Host smart-1c486053-f108-4c82-93ec-caeef055aeac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349908923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1349908923
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.44524255
Short name T122
Test name
Test status
Simulation time 138814909 ps
CPU time 5.24 seconds
Started Jun 25 06:08:37 PM PDT 24
Finished Jun 25 06:08:44 PM PDT 24
Peak memory 213424 kb
Host smart-883a8ae3-b964-4bca-8e22-f0ec5c1e6b52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44524255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.44524255
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.589608333
Short name T366
Test name
Test status
Simulation time 1549098203 ps
CPU time 4.62 seconds
Started Jun 25 06:08:37 PM PDT 24
Finished Jun 25 06:08:42 PM PDT 24
Peak memory 218556 kb
Host smart-7f064091-3985-40e6-b1ad-5cb6b1481164
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589608333 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.589608333
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.389742827
Short name T109
Test name
Test status
Simulation time 1536634596 ps
CPU time 2.54 seconds
Started Jun 25 06:08:40 PM PDT 24
Finished Jun 25 06:08:45 PM PDT 24
Peak memory 213144 kb
Host smart-bacc9c3b-af15-4450-b108-55c4bb2bb825
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389742827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.389742827
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3858131014
Short name T349
Test name
Test status
Simulation time 55803766440 ps
CPU time 93.72 seconds
Started Jun 25 06:08:38 PM PDT 24
Finished Jun 25 06:10:13 PM PDT 24
Peak memory 205032 kb
Host smart-10f615ae-6f67-40a7-8ce9-d5362e4baafb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858131014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.3858131014
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2089577705
Short name T397
Test name
Test status
Simulation time 7555325160 ps
CPU time 18.23 seconds
Started Jun 25 06:08:42 PM PDT 24
Finished Jun 25 06:09:02 PM PDT 24
Peak memory 205036 kb
Host smart-b914e4e7-6ec6-414c-8330-d931d81b07d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089577705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2089577705
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2877129921
Short name T414
Test name
Test status
Simulation time 208884869 ps
CPU time 1.28 seconds
Started Jun 25 06:08:38 PM PDT 24
Finished Jun 25 06:08:41 PM PDT 24
Peak memory 204692 kb
Host smart-71a25f5f-f32d-42cc-b835-d411f142ac54
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877129921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2877129921
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2336756967
Short name T113
Test name
Test status
Simulation time 330129268 ps
CPU time 4.29 seconds
Started Jun 25 06:08:38 PM PDT 24
Finished Jun 25 06:08:45 PM PDT 24
Peak memory 205192 kb
Host smart-2be99d2d-0108-46d5-bbf9-4225b57c9339
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336756967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2336756967
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3388232808
Short name T374
Test name
Test status
Simulation time 610415370 ps
CPU time 5.02 seconds
Started Jun 25 06:08:38 PM PDT 24
Finished Jun 25 06:08:45 PM PDT 24
Peak memory 213388 kb
Host smart-d81c09ba-abab-41fe-868d-339eb01a28e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388232808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3388232808
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3097762524
Short name T423
Test name
Test status
Simulation time 1423727235 ps
CPU time 10.24 seconds
Started Jun 25 06:08:39 PM PDT 24
Finished Jun 25 06:08:51 PM PDT 24
Peak memory 213392 kb
Host smart-220545e4-7d0b-45d8-906b-e0a6ad3ea110
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097762524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
097762524
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2221628215
Short name T369
Test name
Test status
Simulation time 2603529063 ps
CPU time 4.29 seconds
Started Jun 25 06:08:51 PM PDT 24
Finished Jun 25 06:08:56 PM PDT 24
Peak memory 217848 kb
Host smart-2a2eac11-bdd9-4fef-aa3c-9169e3428759
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221628215 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2221628215
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1558010526
Short name T425
Test name
Test status
Simulation time 113558501 ps
CPU time 2.22 seconds
Started Jun 25 06:08:41 PM PDT 24
Finished Jun 25 06:08:45 PM PDT 24
Peak memory 213324 kb
Host smart-2c6d1d43-895e-4d43-9712-7be3fabcdd92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558010526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1558010526
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3578446174
Short name T412
Test name
Test status
Simulation time 55235713 ps
CPU time 0.75 seconds
Started Jun 25 06:08:40 PM PDT 24
Finished Jun 25 06:08:43 PM PDT 24
Peak memory 204736 kb
Host smart-cb233984-3ac4-4f97-8ebb-bf3f57772e40
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578446174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.3578446174
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3418432659
Short name T375
Test name
Test status
Simulation time 2284197929 ps
CPU time 7.21 seconds
Started Jun 25 06:08:40 PM PDT 24
Finished Jun 25 06:08:49 PM PDT 24
Peak memory 205008 kb
Host smart-da80b677-91a8-4e1f-a051-8d286445c67d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418432659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3418432659
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1037551222
Short name T319
Test name
Test status
Simulation time 130764486 ps
CPU time 1.04 seconds
Started Jun 25 06:08:37 PM PDT 24
Finished Jun 25 06:08:40 PM PDT 24
Peak memory 204692 kb
Host smart-62984dc4-ef7e-4318-b5bf-69d2bc061290
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037551222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1037551222
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1802005440
Short name T410
Test name
Test status
Simulation time 509621714 ps
CPU time 4.11 seconds
Started Jun 25 06:08:51 PM PDT 24
Finished Jun 25 06:08:57 PM PDT 24
Peak memory 205176 kb
Host smart-e1ce8b73-9a64-45b3-9b8a-bf373fa2f53e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802005440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1802005440
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3731022315
Short name T388
Test name
Test status
Simulation time 308032211 ps
CPU time 3.39 seconds
Started Jun 25 06:08:51 PM PDT 24
Finished Jun 25 06:08:55 PM PDT 24
Peak memory 213392 kb
Host smart-2d65d5a4-6e35-422a-9758-cb565df0732b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731022315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3731022315
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.468081739
Short name T132
Test name
Test status
Simulation time 2451592750 ps
CPU time 19.69 seconds
Started Jun 25 06:08:51 PM PDT 24
Finished Jun 25 06:09:11 PM PDT 24
Peak memory 213420 kb
Host smart-0a540407-9b7f-4e85-942e-1b2f6f68ce11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468081739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.468081739
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.600882526
Short name T394
Test name
Test status
Simulation time 4208355582 ps
CPU time 10.05 seconds
Started Jun 25 06:08:45 PM PDT 24
Finished Jun 25 06:08:57 PM PDT 24
Peak memory 221896 kb
Host smart-638a96a6-cc4c-4b0c-9f1f-a3769ea78624
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600882526 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.600882526
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.560387227
Short name T106
Test name
Test status
Simulation time 158730752 ps
CPU time 1.64 seconds
Started Jun 25 06:08:48 PM PDT 24
Finished Jun 25 06:08:50 PM PDT 24
Peak memory 213180 kb
Host smart-0619142d-0b2c-4971-88b6-5396cccb88f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560387227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.560387227
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3925472211
Short name T379
Test name
Test status
Simulation time 4446757952 ps
CPU time 3.01 seconds
Started Jun 25 06:08:47 PM PDT 24
Finished Jun 25 06:08:51 PM PDT 24
Peak memory 205016 kb
Host smart-4fa5c56e-f314-4364-a3e7-206cbd2aaf97
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925472211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.3925472211
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.979635077
Short name T332
Test name
Test status
Simulation time 3872685357 ps
CPU time 2.07 seconds
Started Jun 25 06:08:45 PM PDT 24
Finished Jun 25 06:08:49 PM PDT 24
Peak memory 205004 kb
Host smart-50fdf7af-f6ae-4be2-bd72-f66b439f47ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979635077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.979635077
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3569022345
Short name T61
Test name
Test status
Simulation time 207367476 ps
CPU time 0.85 seconds
Started Jun 25 06:08:45 PM PDT 24
Finished Jun 25 06:08:48 PM PDT 24
Peak memory 204768 kb
Host smart-ce0edd2e-6705-4e3b-a818-dd846427ab0e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569022345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3569022345
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1091610430
Short name T87
Test name
Test status
Simulation time 201595583 ps
CPU time 3.73 seconds
Started Jun 25 06:08:45 PM PDT 24
Finished Jun 25 06:08:50 PM PDT 24
Peak memory 205092 kb
Host smart-de27a691-27fe-4f6d-aed2-b9fe94ab4722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091610430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1091610430
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1087626525
Short name T413
Test name
Test status
Simulation time 50635465 ps
CPU time 1.74 seconds
Started Jun 25 06:08:45 PM PDT 24
Finished Jun 25 06:08:48 PM PDT 24
Peak memory 213396 kb
Host smart-efea572e-fd85-4a07-8cd3-3b8ecb1ee2fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087626525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1087626525
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.426318637
Short name T79
Test name
Test status
Simulation time 2883832455 ps
CPU time 22.67 seconds
Started Jun 25 06:08:45 PM PDT 24
Finished Jun 25 06:09:09 PM PDT 24
Peak memory 213464 kb
Host smart-352f71d7-acf8-4d4c-8b0d-75e25a7e178d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426318637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.426318637
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3188571729
Short name T337
Test name
Test status
Simulation time 3420915820 ps
CPU time 6.35 seconds
Started Jun 25 06:08:48 PM PDT 24
Finished Jun 25 06:08:55 PM PDT 24
Peak memory 219644 kb
Host smart-53c87980-52dd-4c30-83c2-d3922ddfd689
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188571729 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3188571729
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3933686060
Short name T95
Test name
Test status
Simulation time 128744507 ps
CPU time 1.57 seconds
Started Jun 25 06:08:46 PM PDT 24
Finished Jun 25 06:08:49 PM PDT 24
Peak memory 213192 kb
Host smart-47c4e066-2208-43d4-a753-2f3f0353b106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933686060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3933686060
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3209289941
Short name T344
Test name
Test status
Simulation time 7372317346 ps
CPU time 5.6 seconds
Started Jun 25 06:08:45 PM PDT 24
Finished Jun 25 06:08:51 PM PDT 24
Peak memory 205012 kb
Host smart-7fe8d55b-0d74-402b-85ce-5cec3af4703e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209289941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.3209289941
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.739708253
Short name T318
Test name
Test status
Simulation time 1030374143 ps
CPU time 1.5 seconds
Started Jun 25 06:08:46 PM PDT 24
Finished Jun 25 06:08:48 PM PDT 24
Peak memory 204952 kb
Host smart-d688264c-2f07-4010-82e1-ab8c0dd2399d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739708253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.739708253
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2891324297
Short name T322
Test name
Test status
Simulation time 250095084 ps
CPU time 0.77 seconds
Started Jun 25 06:08:45 PM PDT 24
Finished Jun 25 06:08:46 PM PDT 24
Peak memory 204784 kb
Host smart-3f745b38-5124-43c8-9817-d48f58330adc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891324297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2891324297
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3911918339
Short name T114
Test name
Test status
Simulation time 895466563 ps
CPU time 4.06 seconds
Started Jun 25 06:08:45 PM PDT 24
Finished Jun 25 06:08:50 PM PDT 24
Peak memory 205152 kb
Host smart-53919e66-61f9-4d69-8db8-8c43f811906a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911918339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3911918339
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3282951396
Short name T367
Test name
Test status
Simulation time 410548016 ps
CPU time 5.42 seconds
Started Jun 25 06:08:45 PM PDT 24
Finished Jun 25 06:08:51 PM PDT 24
Peak memory 213456 kb
Host smart-12d926da-e12d-4546-9289-df61a723da9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282951396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3282951396
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.950365372
Short name T363
Test name
Test status
Simulation time 8534323723 ps
CPU time 23.32 seconds
Started Jun 25 06:08:52 PM PDT 24
Finished Jun 25 06:09:16 PM PDT 24
Peak memory 213420 kb
Host smart-2cd78a42-7246-460d-9cca-601f3da0c350
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950365372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.950365372
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1925670929
Short name T359
Test name
Test status
Simulation time 689283078 ps
CPU time 4.06 seconds
Started Jun 25 06:08:48 PM PDT 24
Finished Jun 25 06:08:53 PM PDT 24
Peak memory 219792 kb
Host smart-66b22448-fa37-4a3a-bbd8-140c5bc85773
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925670929 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1925670929
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1550092424
Short name T406
Test name
Test status
Simulation time 303808089 ps
CPU time 1.68 seconds
Started Jun 25 06:08:47 PM PDT 24
Finished Jun 25 06:08:49 PM PDT 24
Peak memory 213256 kb
Host smart-474f9d1c-d895-4896-91d2-ef265f768756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550092424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1550092424
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1872435643
Short name T372
Test name
Test status
Simulation time 37742386056 ps
CPU time 27.09 seconds
Started Jun 25 06:08:45 PM PDT 24
Finished Jun 25 06:09:13 PM PDT 24
Peak memory 204988 kb
Host smart-2989eb42-6c4f-45c7-bbf3-ee59f075d9d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872435643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.1872435643
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.829093945
Short name T435
Test name
Test status
Simulation time 5090819911 ps
CPU time 12.84 seconds
Started Jun 25 06:08:46 PM PDT 24
Finished Jun 25 06:09:00 PM PDT 24
Peak memory 205008 kb
Host smart-2cd49a41-eb61-41dd-a27e-d4a0c66535bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829093945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.829093945
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1066074108
Short name T59
Test name
Test status
Simulation time 169820977 ps
CPU time 0.89 seconds
Started Jun 25 06:08:46 PM PDT 24
Finished Jun 25 06:08:48 PM PDT 24
Peak memory 204664 kb
Host smart-7d29a8a0-124c-47af-a746-572c28f7755c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066074108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1066074108
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.255045292
Short name T112
Test name
Test status
Simulation time 229911911 ps
CPU time 3.54 seconds
Started Jun 25 06:08:46 PM PDT 24
Finished Jun 25 06:08:51 PM PDT 24
Peak memory 205160 kb
Host smart-00baac05-41a2-4055-af9f-7b7178314d18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255045292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.255045292
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3477581802
Short name T77
Test name
Test status
Simulation time 180138581 ps
CPU time 3.83 seconds
Started Jun 25 06:08:48 PM PDT 24
Finished Jun 25 06:08:52 PM PDT 24
Peak memory 213364 kb
Host smart-f49e22e7-9e0a-4300-afd5-8ba0440c4b22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477581802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3477581802
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3004750895
Short name T351
Test name
Test status
Simulation time 12894193975 ps
CPU time 22.93 seconds
Started Jun 25 06:08:45 PM PDT 24
Finished Jun 25 06:09:09 PM PDT 24
Peak memory 213452 kb
Host smart-7ec32df2-2e52-41cb-be36-429ecbe426fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004750895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
004750895
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.458127752
Short name T392
Test name
Test status
Simulation time 5933628790 ps
CPU time 9.84 seconds
Started Jun 25 06:08:55 PM PDT 24
Finished Jun 25 06:09:05 PM PDT 24
Peak memory 221232 kb
Host smart-463463f6-dcb2-45f9-8fcf-e8f81370943c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458127752 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.458127752
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1816778889
Short name T115
Test name
Test status
Simulation time 49603278 ps
CPU time 1.49 seconds
Started Jun 25 06:08:57 PM PDT 24
Finished Jun 25 06:09:00 PM PDT 24
Peak memory 213248 kb
Host smart-b591dc50-562b-407a-944d-a9e04157ebbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816778889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1816778889
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2001694033
Short name T339
Test name
Test status
Simulation time 3131874804 ps
CPU time 8.99 seconds
Started Jun 25 06:08:52 PM PDT 24
Finished Jun 25 06:09:02 PM PDT 24
Peak memory 205008 kb
Host smart-7b360703-f599-4a81-832b-fdcfa35487bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001694033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2001694033
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.692647795
Short name T378
Test name
Test status
Simulation time 3946011896 ps
CPU time 10.09 seconds
Started Jun 25 06:08:46 PM PDT 24
Finished Jun 25 06:08:57 PM PDT 24
Peak memory 205028 kb
Host smart-eded1679-d69e-4ae6-b52c-1401d682046e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692647795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.692647795
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.588335789
Short name T294
Test name
Test status
Simulation time 1200660078 ps
CPU time 3.78 seconds
Started Jun 25 06:08:43 PM PDT 24
Finished Jun 25 06:08:48 PM PDT 24
Peak memory 204728 kb
Host smart-048a625d-f80e-4f80-9783-99d101983411
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588335789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.588335789
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1191432126
Short name T111
Test name
Test status
Simulation time 836700041 ps
CPU time 4.52 seconds
Started Jun 25 06:08:55 PM PDT 24
Finished Jun 25 06:09:00 PM PDT 24
Peak memory 205208 kb
Host smart-1db4bb40-6863-49e3-a040-8ba5b529c848
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191432126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1191432126
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3322044207
Short name T124
Test name
Test status
Simulation time 186469486 ps
CPU time 2.51 seconds
Started Jun 25 06:08:46 PM PDT 24
Finished Jun 25 06:08:50 PM PDT 24
Peak memory 213376 kb
Host smart-8503805b-a585-4c52-a5b1-6b7c0b607b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322044207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3322044207
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3823607286
Short name T360
Test name
Test status
Simulation time 896795010 ps
CPU time 3 seconds
Started Jun 25 06:08:56 PM PDT 24
Finished Jun 25 06:09:01 PM PDT 24
Peak memory 217788 kb
Host smart-5ce77d1d-d906-4540-806b-164ba5d304d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823607286 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3823607286
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.400793900
Short name T408
Test name
Test status
Simulation time 236678092 ps
CPU time 2.42 seconds
Started Jun 25 06:09:00 PM PDT 24
Finished Jun 25 06:09:03 PM PDT 24
Peak memory 213228 kb
Host smart-65bba24e-e0ea-482b-80de-b6670fab50a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400793900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.400793900
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3247813872
Short name T411
Test name
Test status
Simulation time 6451665421 ps
CPU time 4.47 seconds
Started Jun 25 06:08:56 PM PDT 24
Finished Jun 25 06:09:01 PM PDT 24
Peak memory 204928 kb
Host smart-e056daf4-00e6-415d-9590-e983bc865ffa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247813872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.3247813872
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.611030638
Short name T389
Test name
Test status
Simulation time 4457980329 ps
CPU time 12.84 seconds
Started Jun 25 06:08:56 PM PDT 24
Finished Jun 25 06:09:10 PM PDT 24
Peak memory 205020 kb
Host smart-fdf956ed-a278-4152-bedc-192ffb8e054f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611030638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.611030638
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3003495880
Short name T60
Test name
Test status
Simulation time 915398682 ps
CPU time 2.84 seconds
Started Jun 25 06:08:55 PM PDT 24
Finished Jun 25 06:08:59 PM PDT 24
Peak memory 204764 kb
Host smart-520aab2e-9e2a-4b5b-8c78-eb6b15d16b94
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003495880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3003495880
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3365516273
Short name T98
Test name
Test status
Simulation time 282092608 ps
CPU time 4.6 seconds
Started Jun 25 06:08:55 PM PDT 24
Finished Jun 25 06:09:00 PM PDT 24
Peak memory 205124 kb
Host smart-31c29372-2d1b-480e-b6b1-257973507cdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365516273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3365516273
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.627420588
Short name T120
Test name
Test status
Simulation time 148502776 ps
CPU time 2.35 seconds
Started Jun 25 06:08:56 PM PDT 24
Finished Jun 25 06:08:59 PM PDT 24
Peak memory 213428 kb
Host smart-f502000f-8564-4204-93c4-406d8694318b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627420588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.627420588
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3726609736
Short name T417
Test name
Test status
Simulation time 3196072310 ps
CPU time 21.91 seconds
Started Jun 25 06:08:55 PM PDT 24
Finished Jun 25 06:09:18 PM PDT 24
Peak memory 213424 kb
Host smart-35a3e95d-1efe-4f3f-b49e-17f8a76bc815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726609736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
726609736
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1855029114
Short name T85
Test name
Test status
Simulation time 1174895788 ps
CPU time 63.97 seconds
Started Jun 25 06:08:04 PM PDT 24
Finished Jun 25 06:09:11 PM PDT 24
Peak memory 213328 kb
Host smart-3af32860-ed4b-4c78-8b8c-57f84ba586f0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855029114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1855029114
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3857841837
Short name T428
Test name
Test status
Simulation time 20546836536 ps
CPU time 72.43 seconds
Started Jun 25 06:08:11 PM PDT 24
Finished Jun 25 06:09:25 PM PDT 24
Peak memory 205192 kb
Host smart-3c95054c-d7db-4186-92be-5f763079cb2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857841837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3857841837
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.4124970915
Short name T335
Test name
Test status
Simulation time 119036870 ps
CPU time 1.87 seconds
Started Jun 25 06:08:14 PM PDT 24
Finished Jun 25 06:08:18 PM PDT 24
Peak memory 213336 kb
Host smart-20fbe2ec-cc43-42b5-81bb-5837d03eb3a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124970915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.4124970915
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.813486089
Short name T62
Test name
Test status
Simulation time 7312956130 ps
CPU time 9.4 seconds
Started Jun 25 06:08:12 PM PDT 24
Finished Jun 25 06:08:24 PM PDT 24
Peak memory 221680 kb
Host smart-494c8a15-3e84-45fc-bf4d-18e91c998ab0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813486089 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.813486089
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1101426709
Short name T84
Test name
Test status
Simulation time 94650313 ps
CPU time 1.65 seconds
Started Jun 25 06:08:12 PM PDT 24
Finished Jun 25 06:08:15 PM PDT 24
Peak memory 213308 kb
Host smart-30a92ceb-9ac2-46e2-b618-149de321b84a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101426709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1101426709
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3462527580
Short name T312
Test name
Test status
Simulation time 65594253654 ps
CPU time 46.77 seconds
Started Jun 25 06:08:11 PM PDT 24
Finished Jun 25 06:09:00 PM PDT 24
Peak memory 205036 kb
Host smart-57575c01-ea23-4eb6-acb9-7c8b85ccc0ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462527580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3462527580
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1770856428
Short name T303
Test name
Test status
Simulation time 3653710628 ps
CPU time 6.82 seconds
Started Jun 25 06:08:08 PM PDT 24
Finished Jun 25 06:08:16 PM PDT 24
Peak memory 205068 kb
Host smart-e05ae0f9-4c34-45f9-9305-bf5c9247f6d9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770856428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1770856428
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2034785775
Short name T93
Test name
Test status
Simulation time 2167597020 ps
CPU time 3.79 seconds
Started Jun 25 06:08:11 PM PDT 24
Finished Jun 25 06:08:16 PM PDT 24
Peak memory 205036 kb
Host smart-8b012daa-502b-4098-8c1e-206bbc921123
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034785775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2034785775
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4188127741
Short name T324
Test name
Test status
Simulation time 6545623718 ps
CPU time 6.31 seconds
Started Jun 25 06:08:10 PM PDT 24
Finished Jun 25 06:08:18 PM PDT 24
Peak memory 205028 kb
Host smart-91780d7d-5a22-434f-af21-37ec1ec0afcf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188127741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.4
188127741
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.638093628
Short name T418
Test name
Test status
Simulation time 3921922649 ps
CPU time 1.85 seconds
Started Jun 25 06:08:11 PM PDT 24
Finished Jun 25 06:08:15 PM PDT 24
Peak memory 204820 kb
Host smart-1a95718b-2e5f-4fe5-831b-3a5a4baff82d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638093628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.638093628
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3714129891
Short name T302
Test name
Test status
Simulation time 8697254442 ps
CPU time 14.1 seconds
Started Jun 25 06:08:14 PM PDT 24
Finished Jun 25 06:08:30 PM PDT 24
Peak memory 205096 kb
Host smart-7e0b8e55-f594-4768-800f-e42ccfee62f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714129891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.3714129891
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1292541692
Short name T342
Test name
Test status
Simulation time 436299639 ps
CPU time 1.69 seconds
Started Jun 25 06:08:04 PM PDT 24
Finished Jun 25 06:08:08 PM PDT 24
Peak memory 204688 kb
Host smart-192f6f27-c1c9-4db8-8fe1-19306aad3ccb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292541692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1292541692
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2042201114
Short name T316
Test name
Test status
Simulation time 897127914 ps
CPU time 0.87 seconds
Started Jun 25 06:08:15 PM PDT 24
Finished Jun 25 06:08:17 PM PDT 24
Peak memory 204756 kb
Host smart-49a959ef-1359-468c-80a2-aba46bcaf02a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042201114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
042201114
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2167919878
Short name T307
Test name
Test status
Simulation time 91274429 ps
CPU time 0.86 seconds
Started Jun 25 06:08:15 PM PDT 24
Finished Jun 25 06:08:17 PM PDT 24
Peak memory 204836 kb
Host smart-217d0892-93e1-429c-99cf-f465856f5d73
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167919878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2167919878
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1662351036
Short name T338
Test name
Test status
Simulation time 79242181 ps
CPU time 0.78 seconds
Started Jun 25 06:08:12 PM PDT 24
Finished Jun 25 06:08:15 PM PDT 24
Peak memory 204736 kb
Host smart-cfd273a5-f5a2-48a0-bf11-9a5cb7df5fc3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662351036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1662351036
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2644647333
Short name T384
Test name
Test status
Simulation time 332732798 ps
CPU time 4.24 seconds
Started Jun 25 06:08:10 PM PDT 24
Finished Jun 25 06:08:17 PM PDT 24
Peak memory 205172 kb
Host smart-193e6601-793b-4020-9180-e501a50cafd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644647333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2644647333
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1119335564
Short name T390
Test name
Test status
Simulation time 1271520924 ps
CPU time 6.34 seconds
Started Jun 25 06:08:11 PM PDT 24
Finished Jun 25 06:08:20 PM PDT 24
Peak memory 213352 kb
Host smart-9c2019dc-fb46-4cb4-ae7f-c6291eb2532b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119335564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1119335564
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2392759707
Short name T129
Test name
Test status
Simulation time 3265554953 ps
CPU time 19.58 seconds
Started Jun 25 06:08:14 PM PDT 24
Finished Jun 25 06:08:36 PM PDT 24
Peak memory 213436 kb
Host smart-65f125ca-30a1-45be-935f-db9930ffb654
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392759707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2392759707
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3703027150
Short name T358
Test name
Test status
Simulation time 6762997002 ps
CPU time 73.42 seconds
Started Jun 25 06:08:12 PM PDT 24
Finished Jun 25 06:09:28 PM PDT 24
Peak memory 213384 kb
Host smart-498a469b-980c-4179-9c04-64933189dc15
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703027150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3703027150
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.612567037
Short name T88
Test name
Test status
Simulation time 14056590576 ps
CPU time 55.6 seconds
Started Jun 25 06:08:17 PM PDT 24
Finished Jun 25 06:09:14 PM PDT 24
Peak memory 213388 kb
Host smart-39c8f133-e275-4ec3-9411-945cd0cb8d07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612567037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.612567037
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1649556094
Short name T426
Test name
Test status
Simulation time 99331963 ps
CPU time 2.34 seconds
Started Jun 25 06:08:17 PM PDT 24
Finished Jun 25 06:08:20 PM PDT 24
Peak memory 215188 kb
Host smart-459b6088-8c4d-4082-9acb-830cef4dc0ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649556094 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1649556094
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2353881313
Short name T403
Test name
Test status
Simulation time 147836646 ps
CPU time 2.14 seconds
Started Jun 25 06:08:20 PM PDT 24
Finished Jun 25 06:08:23 PM PDT 24
Peak memory 213212 kb
Host smart-458c2e13-8e58-4c68-b077-feca1e6ea8f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353881313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2353881313
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1780071357
Short name T405
Test name
Test status
Simulation time 117192846636 ps
CPU time 78.79 seconds
Started Jun 25 06:08:14 PM PDT 24
Finished Jun 25 06:09:34 PM PDT 24
Peak memory 205076 kb
Host smart-648ec571-fdf4-4fe5-ac47-0390b7caa7c9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780071357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1780071357
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.672415647
Short name T301
Test name
Test status
Simulation time 4365530649 ps
CPU time 2.79 seconds
Started Jun 25 06:08:13 PM PDT 24
Finished Jun 25 06:08:18 PM PDT 24
Peak memory 205040 kb
Host smart-1a94c17f-f3ba-4a3c-9ab9-171bf70719c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672415647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
v_dm_jtag_dmi_csr_bit_bash.672415647
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.301532329
Short name T92
Test name
Test status
Simulation time 4534045137 ps
CPU time 6.69 seconds
Started Jun 25 06:08:14 PM PDT 24
Finished Jun 25 06:08:23 PM PDT 24
Peak memory 205008 kb
Host smart-eec4be9e-2ce4-459c-8500-3760c375a5ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301532329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.301532329
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1420832689
Short name T317
Test name
Test status
Simulation time 1803384823 ps
CPU time 2.43 seconds
Started Jun 25 06:08:13 PM PDT 24
Finished Jun 25 06:08:17 PM PDT 24
Peak memory 204984 kb
Host smart-1abe432c-8b9f-4eaa-aca9-a9b52cca9bd5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420832689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
420832689
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1085677597
Short name T434
Test name
Test status
Simulation time 1086287579 ps
CPU time 2.05 seconds
Started Jun 25 06:08:11 PM PDT 24
Finished Jun 25 06:08:16 PM PDT 24
Peak memory 204664 kb
Host smart-38742cac-9f90-49cf-a09d-789578dd6943
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085677597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1085677597
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3470988244
Short name T299
Test name
Test status
Simulation time 5628510743 ps
CPU time 14.13 seconds
Started Jun 25 06:08:12 PM PDT 24
Finished Jun 25 06:08:28 PM PDT 24
Peak memory 205000 kb
Host smart-920227bd-60f3-4078-a68e-b21c157a7798
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470988244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3470988244
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3467491994
Short name T427
Test name
Test status
Simulation time 369201764 ps
CPU time 1.77 seconds
Started Jun 25 06:08:14 PM PDT 24
Finished Jun 25 06:08:17 PM PDT 24
Peak memory 204764 kb
Host smart-86afb163-2c5c-44d2-98ec-9ff967d5b9c2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467491994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3467491994
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1141248427
Short name T295
Test name
Test status
Simulation time 283576533 ps
CPU time 0.9 seconds
Started Jun 25 06:08:11 PM PDT 24
Finished Jun 25 06:08:14 PM PDT 24
Peak memory 204748 kb
Host smart-6af9fed8-9d64-4ce6-9fe8-af6e46984ac6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141248427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
141248427
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.763575641
Short name T355
Test name
Test status
Simulation time 54007889 ps
CPU time 0.71 seconds
Started Jun 25 06:08:16 PM PDT 24
Finished Jun 25 06:08:17 PM PDT 24
Peak memory 204824 kb
Host smart-1d427039-5b25-48f0-9fa2-3b08c9244d31
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763575641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.763575641
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3235915255
Short name T310
Test name
Test status
Simulation time 34689264 ps
CPU time 0.73 seconds
Started Jun 25 06:08:09 PM PDT 24
Finished Jun 25 06:08:12 PM PDT 24
Peak memory 204760 kb
Host smart-e045180e-99bc-4019-8692-25033faf6871
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235915255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3235915255
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.731116628
Short name T385
Test name
Test status
Simulation time 231334482 ps
CPU time 3.99 seconds
Started Jun 25 06:08:20 PM PDT 24
Finished Jun 25 06:08:26 PM PDT 24
Peak memory 205100 kb
Host smart-f327d7de-3730-4d86-8b5a-1ccbf927017d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731116628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.731116628
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1040631345
Short name T133
Test name
Test status
Simulation time 7619222501 ps
CPU time 24.1 seconds
Started Jun 25 06:08:13 PM PDT 24
Finished Jun 25 06:08:39 PM PDT 24
Peak memory 213440 kb
Host smart-ad02c637-8a09-4141-9dad-ec011adabd09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040631345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1040631345
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2580779891
Short name T99
Test name
Test status
Simulation time 9868019912 ps
CPU time 73.95 seconds
Started Jun 25 06:08:19 PM PDT 24
Finished Jun 25 06:09:35 PM PDT 24
Peak memory 213336 kb
Host smart-64fd8d22-f10a-454b-92c0-f57aaf4afaff
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580779891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2580779891
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3976150012
Short name T195
Test name
Test status
Simulation time 2518951688 ps
CPU time 34.52 seconds
Started Jun 25 06:08:19 PM PDT 24
Finished Jun 25 06:08:55 PM PDT 24
Peak memory 213392 kb
Host smart-7be37485-20e2-4c6b-ac82-56a1a4a92dd4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976150012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3976150012
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.4277042823
Short name T402
Test name
Test status
Simulation time 208734166 ps
CPU time 2.4 seconds
Started Jun 25 06:08:20 PM PDT 24
Finished Jun 25 06:08:24 PM PDT 24
Peak memory 214240 kb
Host smart-3cc42071-f80d-42d2-a5a1-53653876de8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277042823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.4277042823
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3267654568
Short name T76
Test name
Test status
Simulation time 903642877 ps
CPU time 2.26 seconds
Started Jun 25 06:08:17 PM PDT 24
Finished Jun 25 06:08:21 PM PDT 24
Peak memory 213448 kb
Host smart-fabf76c1-c6b7-4021-9dea-9301d44d6c27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267654568 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3267654568
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3127235901
Short name T108
Test name
Test status
Simulation time 91847554 ps
CPU time 1.43 seconds
Started Jun 25 06:08:19 PM PDT 24
Finished Jun 25 06:08:23 PM PDT 24
Peak memory 213212 kb
Host smart-569218d3-6c77-461b-ab31-f4c1ed9c86d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127235901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3127235901
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.485843651
Short name T419
Test name
Test status
Simulation time 55031645560 ps
CPU time 72.37 seconds
Started Jun 25 06:08:19 PM PDT 24
Finished Jun 25 06:09:34 PM PDT 24
Peak memory 205064 kb
Host smart-37c147d2-8def-42fa-965b-2b15b664e17e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485843651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_aliasing.485843651
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.320685373
Short name T376
Test name
Test status
Simulation time 17443238200 ps
CPU time 12.86 seconds
Started Jun 25 06:08:18 PM PDT 24
Finished Jun 25 06:08:32 PM PDT 24
Peak memory 205064 kb
Host smart-db0938c1-cdb1-477f-be04-173cfbf813aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320685373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.320685373
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1280347633
Short name T422
Test name
Test status
Simulation time 4419947308 ps
CPU time 12.53 seconds
Started Jun 25 06:08:19 PM PDT 24
Finished Jun 25 06:08:33 PM PDT 24
Peak memory 204944 kb
Host smart-e3969a79-327f-4686-b88a-d0866efc94f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280347633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1280347633
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4140318971
Short name T320
Test name
Test status
Simulation time 5434492789 ps
CPU time 13.77 seconds
Started Jun 25 06:08:18 PM PDT 24
Finished Jun 25 06:08:33 PM PDT 24
Peak memory 205008 kb
Host smart-3eb56bf6-0283-43df-aacc-b349352f35e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140318971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.4
140318971
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3397941024
Short name T386
Test name
Test status
Simulation time 1375481280 ps
CPU time 4.69 seconds
Started Jun 25 06:08:19 PM PDT 24
Finished Jun 25 06:08:26 PM PDT 24
Peak memory 204676 kb
Host smart-551bd126-2cb1-4fca-b1df-14ce8ee3d754
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397941024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3397941024
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.152705369
Short name T308
Test name
Test status
Simulation time 6431635639 ps
CPU time 6.11 seconds
Started Jun 25 06:08:19 PM PDT 24
Finished Jun 25 06:08:27 PM PDT 24
Peak memory 205180 kb
Host smart-49c783d3-5dba-4a65-9c4e-c665aff88017
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152705369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.152705369
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2832641312
Short name T382
Test name
Test status
Simulation time 674761752 ps
CPU time 1.11 seconds
Started Jun 25 06:08:18 PM PDT 24
Finished Jun 25 06:08:20 PM PDT 24
Peak memory 204764 kb
Host smart-f36b4346-a21e-4682-b482-bf5c2c0da5e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832641312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2832641312
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2812512790
Short name T364
Test name
Test status
Simulation time 1030595244 ps
CPU time 1.58 seconds
Started Jun 25 06:08:19 PM PDT 24
Finished Jun 25 06:08:22 PM PDT 24
Peak memory 204752 kb
Host smart-9a7ddec4-b07d-4b07-b8f6-e0aab53725f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812512790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
812512790
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3377152967
Short name T293
Test name
Test status
Simulation time 56120430 ps
CPU time 0.71 seconds
Started Jun 25 06:08:18 PM PDT 24
Finished Jun 25 06:08:20 PM PDT 24
Peak memory 204816 kb
Host smart-b9ec0855-3d0e-4616-9a98-96b49dd9e2af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377152967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3377152967
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3474730348
Short name T321
Test name
Test status
Simulation time 110235176 ps
CPU time 0.8 seconds
Started Jun 25 06:08:19 PM PDT 24
Finished Jun 25 06:08:21 PM PDT 24
Peak memory 204792 kb
Host smart-21e5b498-ac51-4c60-961a-3aedce605ecb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474730348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3474730348
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3854911525
Short name T431
Test name
Test status
Simulation time 186527465 ps
CPU time 6.36 seconds
Started Jun 25 06:08:19 PM PDT 24
Finished Jun 25 06:08:27 PM PDT 24
Peak memory 205096 kb
Host smart-de959874-94ab-4fd1-86d0-657c74d77b72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854911525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3854911525
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1136962418
Short name T424
Test name
Test status
Simulation time 1922908789 ps
CPU time 4.7 seconds
Started Jun 25 06:08:17 PM PDT 24
Finished Jun 25 06:08:23 PM PDT 24
Peak memory 213376 kb
Host smart-7c762e1f-9b42-462d-a34e-e642e73fb348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136962418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1136962418
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.334575415
Short name T130
Test name
Test status
Simulation time 3070760878 ps
CPU time 17.98 seconds
Started Jun 25 06:08:19 PM PDT 24
Finished Jun 25 06:08:39 PM PDT 24
Peak memory 213400 kb
Host smart-438af791-f180-4a15-9329-c56997a8e016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334575415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.334575415
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4126371193
Short name T346
Test name
Test status
Simulation time 2176193745 ps
CPU time 5.97 seconds
Started Jun 25 06:08:29 PM PDT 24
Finished Jun 25 06:08:37 PM PDT 24
Peak memory 219292 kb
Host smart-0c3a0a30-36e6-4319-a682-6a436053bdf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126371193 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.4126371193
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.434394180
Short name T104
Test name
Test status
Simulation time 291098781 ps
CPU time 1.56 seconds
Started Jun 25 06:08:28 PM PDT 24
Finished Jun 25 06:08:31 PM PDT 24
Peak memory 213364 kb
Host smart-9c20cd68-3463-4c1b-aeaa-8d2bdce6e72c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434394180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.434394180
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.4056808776
Short name T334
Test name
Test status
Simulation time 17463466264 ps
CPU time 26.89 seconds
Started Jun 25 06:08:19 PM PDT 24
Finished Jun 25 06:08:47 PM PDT 24
Peak memory 205020 kb
Host smart-334a7475-b25b-453a-8014-8ea222e5356c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056808776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.4056808776
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1916422068
Short name T292
Test name
Test status
Simulation time 3885121893 ps
CPU time 11.07 seconds
Started Jun 25 06:08:18 PM PDT 24
Finished Jun 25 06:08:31 PM PDT 24
Peak memory 204932 kb
Host smart-4651b67c-31ab-4c07-86e1-049de977131b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916422068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
916422068
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3758190889
Short name T304
Test name
Test status
Simulation time 165269294 ps
CPU time 0.97 seconds
Started Jun 25 06:08:19 PM PDT 24
Finished Jun 25 06:08:21 PM PDT 24
Peak memory 204744 kb
Host smart-b999fb14-e665-4f30-bdfe-2ea2f102e4de
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758190889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
758190889
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1079607776
Short name T383
Test name
Test status
Simulation time 889554811 ps
CPU time 4.42 seconds
Started Jun 25 06:08:31 PM PDT 24
Finished Jun 25 06:08:37 PM PDT 24
Peak memory 205168 kb
Host smart-8193f6c6-8ac7-46c1-aff8-a752a87b12eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079607776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1079607776
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2811065948
Short name T345
Test name
Test status
Simulation time 757414597 ps
CPU time 2.74 seconds
Started Jun 25 06:08:17 PM PDT 24
Finished Jun 25 06:08:21 PM PDT 24
Peak memory 213412 kb
Host smart-d104991a-61cb-4da0-a6ba-e8e54c0ab8f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811065948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2811065948
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.936293669
Short name T127
Test name
Test status
Simulation time 4217876983 ps
CPU time 17.28 seconds
Started Jun 25 06:08:29 PM PDT 24
Finished Jun 25 06:08:48 PM PDT 24
Peak memory 213420 kb
Host smart-117f2ad6-4e40-43bd-a1d6-195060af40c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936293669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.936293669
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.313378279
Short name T74
Test name
Test status
Simulation time 4917137105 ps
CPU time 4.95 seconds
Started Jun 25 06:08:29 PM PDT 24
Finished Jun 25 06:08:37 PM PDT 24
Peak memory 221624 kb
Host smart-8ae4774b-fcf7-4a01-9030-cbbfea400fc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313378279 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.313378279
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.200674700
Short name T421
Test name
Test status
Simulation time 12154126124 ps
CPU time 9.91 seconds
Started Jun 25 06:08:27 PM PDT 24
Finished Jun 25 06:08:38 PM PDT 24
Peak memory 205020 kb
Host smart-1e99841e-9ecf-4d26-a5b5-8102bb3ebe32
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200674700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
v_dm_jtag_dmi_csr_bit_bash.200674700
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2673781154
Short name T368
Test name
Test status
Simulation time 12236163493 ps
CPU time 9.66 seconds
Started Jun 25 06:08:28 PM PDT 24
Finished Jun 25 06:08:40 PM PDT 24
Peak memory 204944 kb
Host smart-27eeaa0a-35b8-462f-826e-db7fbed8dece
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673781154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
673781154
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1150707953
Short name T323
Test name
Test status
Simulation time 544774170 ps
CPU time 2.09 seconds
Started Jun 25 06:08:30 PM PDT 24
Finished Jun 25 06:08:34 PM PDT 24
Peak memory 204752 kb
Host smart-a78bf196-70da-4b3f-a023-7d703d43d0f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150707953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
150707953
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.559768591
Short name T110
Test name
Test status
Simulation time 221211873 ps
CPU time 4.09 seconds
Started Jun 25 06:08:31 PM PDT 24
Finished Jun 25 06:08:37 PM PDT 24
Peak memory 205152 kb
Host smart-6947e3c9-0a5a-48b3-a34d-615bbccc878a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559768591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c
sr_outstanding.559768591
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1204442385
Short name T347
Test name
Test status
Simulation time 314635980 ps
CPU time 4.75 seconds
Started Jun 25 06:08:28 PM PDT 24
Finished Jun 25 06:08:35 PM PDT 24
Peak memory 213352 kb
Host smart-fe2b1eaf-d028-49c2-b468-3be01c784d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204442385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1204442385
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2134462523
Short name T131
Test name
Test status
Simulation time 1415395808 ps
CPU time 12.53 seconds
Started Jun 25 06:08:27 PM PDT 24
Finished Jun 25 06:08:41 PM PDT 24
Peak memory 213392 kb
Host smart-7602681a-c33a-47a0-9459-4f550529fa62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134462523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2134462523
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.4038787573
Short name T63
Test name
Test status
Simulation time 413171149 ps
CPU time 2.34 seconds
Started Jun 25 06:08:29 PM PDT 24
Finished Jun 25 06:08:33 PM PDT 24
Peak memory 215644 kb
Host smart-ff1b7176-b2ad-447f-a86b-01651c7cda7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038787573 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.4038787573
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3845683650
Short name T90
Test name
Test status
Simulation time 61988394 ps
CPU time 2.19 seconds
Started Jun 25 06:08:30 PM PDT 24
Finished Jun 25 06:08:34 PM PDT 24
Peak memory 213344 kb
Host smart-5cfa2cea-716e-48c7-9507-ff5f536c1da0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845683650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3845683650
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3374462651
Short name T298
Test name
Test status
Simulation time 12005114402 ps
CPU time 12.31 seconds
Started Jun 25 06:08:26 PM PDT 24
Finished Jun 25 06:08:39 PM PDT 24
Peak memory 205016 kb
Host smart-86752c76-e9ee-4d8b-b620-6fe3206c90ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374462651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.3374462651
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.937562539
Short name T396
Test name
Test status
Simulation time 2236397089 ps
CPU time 1.43 seconds
Started Jun 25 06:08:31 PM PDT 24
Finished Jun 25 06:08:34 PM PDT 24
Peak memory 204952 kb
Host smart-b5c3cfb2-7c7e-4b37-be23-99ef20b84eb9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937562539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.937562539
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1375388603
Short name T300
Test name
Test status
Simulation time 233363039 ps
CPU time 1.14 seconds
Started Jun 25 06:08:30 PM PDT 24
Finished Jun 25 06:08:33 PM PDT 24
Peak memory 204680 kb
Host smart-31cbd5e6-3431-4b78-9fdf-5df53d080b46
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375388603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
375388603
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.641205449
Short name T82
Test name
Test status
Simulation time 260055256 ps
CPU time 6.85 seconds
Started Jun 25 06:08:30 PM PDT 24
Finished Jun 25 06:08:39 PM PDT 24
Peak memory 205152 kb
Host smart-eeaf64ef-8ecc-4945-961c-5bec859c32da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641205449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.641205449
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1508411352
Short name T401
Test name
Test status
Simulation time 74641510 ps
CPU time 3.89 seconds
Started Jun 25 06:08:29 PM PDT 24
Finished Jun 25 06:08:36 PM PDT 24
Peak memory 215880 kb
Host smart-83c12305-6765-4309-97c1-107093a88c3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508411352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1508411352
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.457466722
Short name T125
Test name
Test status
Simulation time 2583319953 ps
CPU time 23.47 seconds
Started Jun 25 06:08:27 PM PDT 24
Finished Jun 25 06:08:51 PM PDT 24
Peak memory 213420 kb
Host smart-50ae2abd-b056-47bf-9771-3fcade1ddacf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457466722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.457466722
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3873733236
Short name T350
Test name
Test status
Simulation time 1701372209 ps
CPU time 5.71 seconds
Started Jun 25 06:08:28 PM PDT 24
Finished Jun 25 06:08:36 PM PDT 24
Peak memory 221584 kb
Host smart-81fe554e-0035-43e2-9d10-9827fbf664df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873733236 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3873733236
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.947821559
Short name T420
Test name
Test status
Simulation time 52704570 ps
CPU time 1.5 seconds
Started Jun 25 06:08:28 PM PDT 24
Finished Jun 25 06:08:31 PM PDT 24
Peak memory 213292 kb
Host smart-d5b8cead-098f-47f7-aeb0-59be06e599a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947821559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.947821559
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.207672251
Short name T331
Test name
Test status
Simulation time 7224599920 ps
CPU time 11.92 seconds
Started Jun 25 06:08:28 PM PDT 24
Finished Jun 25 06:08:42 PM PDT 24
Peak memory 205056 kb
Host smart-bb4b55e3-eec0-4270-a227-dcf5bf6d3c16
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207672251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
v_dm_jtag_dmi_csr_bit_bash.207672251
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3112002179
Short name T305
Test name
Test status
Simulation time 2020325436 ps
CPU time 3.66 seconds
Started Jun 25 06:08:31 PM PDT 24
Finished Jun 25 06:08:36 PM PDT 24
Peak memory 204968 kb
Host smart-43b83304-2174-4dd3-83cd-dbc41a0f9d92
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112002179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
112002179
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2801172620
Short name T314
Test name
Test status
Simulation time 204757079 ps
CPU time 0.88 seconds
Started Jun 25 06:08:28 PM PDT 24
Finished Jun 25 06:08:30 PM PDT 24
Peak memory 204780 kb
Host smart-465c4d7f-4088-42d7-8d8e-dd03e718c8ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801172620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
801172620
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1963270932
Short name T362
Test name
Test status
Simulation time 2423674158 ps
CPU time 6.55 seconds
Started Jun 25 06:08:27 PM PDT 24
Finished Jun 25 06:08:35 PM PDT 24
Peak memory 205228 kb
Host smart-318f778d-3e1d-423c-aa38-485474dfe424
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963270932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1963270932
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2856483157
Short name T393
Test name
Test status
Simulation time 551491993 ps
CPU time 3.43 seconds
Started Jun 25 06:08:30 PM PDT 24
Finished Jun 25 06:08:36 PM PDT 24
Peak memory 213400 kb
Host smart-baf3f960-cc10-4ff3-9b7c-99ea4c42fe5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856483157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2856483157
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1265064899
Short name T357
Test name
Test status
Simulation time 2874177727 ps
CPU time 19.37 seconds
Started Jun 25 06:08:29 PM PDT 24
Finished Jun 25 06:08:50 PM PDT 24
Peak memory 213404 kb
Host smart-c38ac55b-809f-406b-a8a8-15c553894ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265064899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1265064899
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1912039966
Short name T400
Test name
Test status
Simulation time 3631412342 ps
CPU time 8.98 seconds
Started Jun 25 06:08:28 PM PDT 24
Finished Jun 25 06:08:39 PM PDT 24
Peak memory 221412 kb
Host smart-534b5e88-b497-4436-897d-94ec60651fb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912039966 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1912039966
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.288086466
Short name T326
Test name
Test status
Simulation time 222602360 ps
CPU time 2.53 seconds
Started Jun 25 06:08:28 PM PDT 24
Finished Jun 25 06:08:31 PM PDT 24
Peak memory 213208 kb
Host smart-22cb1fda-dfc4-4618-ab30-647c6afb0ae2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288086466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.288086466
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1413281532
Short name T291
Test name
Test status
Simulation time 30790587826 ps
CPU time 25.3 seconds
Started Jun 25 06:08:30 PM PDT 24
Finished Jun 25 06:08:57 PM PDT 24
Peak memory 205052 kb
Host smart-74c9ecd3-a78e-4dd0-aec1-83ac7ff1dc6f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413281532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.1413281532
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1838689983
Short name T352
Test name
Test status
Simulation time 3476542948 ps
CPU time 10.16 seconds
Started Jun 25 06:08:28 PM PDT 24
Finished Jun 25 06:08:40 PM PDT 24
Peak memory 205056 kb
Host smart-70f15694-df50-4304-a29c-d892b75fb78e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838689983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
838689983
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2668505004
Short name T341
Test name
Test status
Simulation time 1320691290 ps
CPU time 1.49 seconds
Started Jun 25 06:08:29 PM PDT 24
Finished Jun 25 06:08:33 PM PDT 24
Peak memory 204780 kb
Host smart-f100d44d-75d9-45e1-9374-4a21f4c4d34c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668505004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
668505004
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3600753765
Short name T102
Test name
Test status
Simulation time 558636442 ps
CPU time 7.9 seconds
Started Jun 25 06:08:29 PM PDT 24
Finished Jun 25 06:08:38 PM PDT 24
Peak memory 205200 kb
Host smart-23cbddff-87da-4463-909a-ebf20c41b0ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600753765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3600753765
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3286115194
Short name T70
Test name
Test status
Simulation time 1014268692 ps
CPU time 9.89 seconds
Started Jun 25 06:08:28 PM PDT 24
Finished Jun 25 06:08:40 PM PDT 24
Peak memory 213388 kb
Host smart-3d919156-58cc-455a-a67b-ce963d048678
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286115194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3286115194
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.2399273594
Short name T48
Test name
Test status
Simulation time 199134402 ps
CPU time 0.98 seconds
Started Jun 25 05:25:32 PM PDT 24
Finished Jun 25 05:25:35 PM PDT 24
Peak memory 204940 kb
Host smart-9efa34e2-eb53-4e4a-8e20-3a2785b29d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399273594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2399273594
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3049288676
Short name T187
Test name
Test status
Simulation time 135782303 ps
CPU time 0.82 seconds
Started Jun 25 05:25:29 PM PDT 24
Finished Jun 25 05:25:32 PM PDT 24
Peak memory 204952 kb
Host smart-cf24a9d7-62c6-443b-889b-3937df8fc5c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049288676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3049288676
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3460228329
Short name T4
Test name
Test status
Simulation time 515501763 ps
CPU time 1.02 seconds
Started Jun 25 05:25:35 PM PDT 24
Finished Jun 25 05:25:38 PM PDT 24
Peak memory 204952 kb
Host smart-f301dd8f-1f3b-4d57-a487-ff223c2f5ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460228329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3460228329
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.795713423
Short name T241
Test name
Test status
Simulation time 272861627 ps
CPU time 0.91 seconds
Started Jun 25 05:25:39 PM PDT 24
Finished Jun 25 05:25:41 PM PDT 24
Peak memory 204928 kb
Host smart-0397c609-d7c2-4d13-9412-656ed17c648c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795713423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.795713423
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3902606760
Short name T212
Test name
Test status
Simulation time 118487163 ps
CPU time 0.77 seconds
Started Jun 25 05:25:31 PM PDT 24
Finished Jun 25 05:25:34 PM PDT 24
Peak memory 204924 kb
Host smart-3cfafe0d-85ef-4257-aff1-d4d164e0a71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902606760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3902606760
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1941307658
Short name T210
Test name
Test status
Simulation time 2692140428 ps
CPU time 3.17 seconds
Started Jun 25 05:25:35 PM PDT 24
Finished Jun 25 05:25:40 PM PDT 24
Peak memory 205384 kb
Host smart-84309051-3c94-43b5-8c66-6f248d4c4bd3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1941307658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1941307658
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1274687290
Short name T138
Test name
Test status
Simulation time 332703542 ps
CPU time 1.71 seconds
Started Jun 25 05:25:35 PM PDT 24
Finished Jun 25 05:25:39 PM PDT 24
Peak memory 204952 kb
Host smart-c046c89a-188e-40be-97eb-76858a420492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274687290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1274687290
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3336563172
Short name T289
Test name
Test status
Simulation time 233623421 ps
CPU time 1.25 seconds
Started Jun 25 05:25:27 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 204696 kb
Host smart-5c3a690c-4e4b-408d-80a8-676841fe0c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336563172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3336563172
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1629321007
Short name T277
Test name
Test status
Simulation time 131977553 ps
CPU time 1 seconds
Started Jun 25 05:25:31 PM PDT 24
Finished Jun 25 05:25:35 PM PDT 24
Peak memory 204800 kb
Host smart-fd5f51fb-225b-42cd-ba8e-b34e3f4e7996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629321007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1629321007
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4195420154
Short name T206
Test name
Test status
Simulation time 1094165374 ps
CPU time 3.24 seconds
Started Jun 25 05:25:31 PM PDT 24
Finished Jun 25 05:25:36 PM PDT 24
Peak memory 204800 kb
Host smart-f74dcb33-f0ca-4749-a522-70e2224ebc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195420154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4195420154
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1526282599
Short name T253
Test name
Test status
Simulation time 1220136151 ps
CPU time 1.34 seconds
Started Jun 25 05:25:30 PM PDT 24
Finished Jun 25 05:25:34 PM PDT 24
Peak memory 204784 kb
Host smart-290e3dc7-f775-4e78-8b6f-877acf5c3fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526282599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1526282599
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.403506389
Short name T213
Test name
Test status
Simulation time 198620838 ps
CPU time 0.94 seconds
Started Jun 25 05:25:37 PM PDT 24
Finished Jun 25 05:25:40 PM PDT 24
Peak memory 204780 kb
Host smart-880585a4-ff8c-4879-8ab6-e92a8715da61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403506389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.403506389
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1877270653
Short name T149
Test name
Test status
Simulation time 155586490 ps
CPU time 0.82 seconds
Started Jun 25 05:25:29 PM PDT 24
Finished Jun 25 05:25:32 PM PDT 24
Peak memory 204928 kb
Host smart-cfbadba0-480f-479a-b573-529d58ba7fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877270653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1877270653
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3756238306
Short name T1
Test name
Test status
Simulation time 1004784640 ps
CPU time 2.13 seconds
Started Jun 25 05:25:38 PM PDT 24
Finished Jun 25 05:25:42 PM PDT 24
Peak memory 204940 kb
Host smart-4dbbd98e-dad3-44f5-8e5c-3994793f212b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756238306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3756238306
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.4274850856
Short name T135
Test name
Test status
Simulation time 464721152 ps
CPU time 1.41 seconds
Started Jun 25 05:25:41 PM PDT 24
Finished Jun 25 05:25:48 PM PDT 24
Peak memory 204896 kb
Host smart-743a3ad9-6d80-4e21-8aae-301a6789332d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274850856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.4274850856
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.940098457
Short name T232
Test name
Test status
Simulation time 4541269056 ps
CPU time 11.09 seconds
Started Jun 25 05:25:41 PM PDT 24
Finished Jun 25 05:25:53 PM PDT 24
Peak memory 204768 kb
Host smart-ec6ee9bb-d3cf-4cd7-85a5-52213befeeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940098457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.940098457
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2902099283
Short name T274
Test name
Test status
Simulation time 2833551132 ps
CPU time 7.93 seconds
Started Jun 25 05:25:37 PM PDT 24
Finished Jun 25 05:25:46 PM PDT 24
Peak memory 205284 kb
Host smart-e1158b83-28f5-41d7-9819-a9c06ede9e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902099283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2902099283
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3792786124
Short name T57
Test name
Test status
Simulation time 1323345539 ps
CPU time 4.58 seconds
Started Jun 25 05:25:39 PM PDT 24
Finished Jun 25 05:25:45 PM PDT 24
Peak memory 233852 kb
Host smart-49ecc8bf-404c-45ad-932a-ba98afc1f49f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792786124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3792786124
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2958763031
Short name T242
Test name
Test status
Simulation time 679987221 ps
CPU time 1.28 seconds
Started Jun 25 05:25:27 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 204780 kb
Host smart-73ad1863-fde1-4f50-a21d-73cfa1d4fcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958763031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2958763031
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.3811989983
Short name T136
Test name
Test status
Simulation time 7241254189 ps
CPU time 10.29 seconds
Started Jun 25 05:25:28 PM PDT 24
Finished Jun 25 05:25:41 PM PDT 24
Peak memory 213456 kb
Host smart-9c7162ee-2b23-42be-ad81-79ffb2f62bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811989983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3811989983
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1110034999
Short name T43
Test name
Test status
Simulation time 33302577 ps
CPU time 0.76 seconds
Started Jun 25 05:25:42 PM PDT 24
Finished Jun 25 05:25:45 PM PDT 24
Peak memory 204696 kb
Host smart-2724b58d-ea7b-4fb0-ad17-0cc81b2f25f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110034999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1110034999
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.3528836330
Short name T12
Test name
Test status
Simulation time 1930553100 ps
CPU time 4.6 seconds
Started Jun 25 05:25:42 PM PDT 24
Finished Jun 25 05:25:48 PM PDT 24
Peak memory 205100 kb
Host smart-aaa7578a-9efb-4b04-9564-afdbea03ed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528836330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3528836330
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3032318126
Short name T157
Test name
Test status
Simulation time 269073443 ps
CPU time 1.41 seconds
Started Jun 25 05:25:29 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 204924 kb
Host smart-59c7f07d-e2c9-46c7-9c87-f7cf2445e221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032318126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3032318126
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2969193906
Short name T50
Test name
Test status
Simulation time 555031142 ps
CPU time 2.07 seconds
Started Jun 25 05:25:44 PM PDT 24
Finished Jun 25 05:25:48 PM PDT 24
Peak memory 204876 kb
Host smart-b6644216-5182-4139-ac0d-e04fc2fd8b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969193906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2969193906
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3305685930
Short name T46
Test name
Test status
Simulation time 82259658 ps
CPU time 0.86 seconds
Started Jun 25 05:25:27 PM PDT 24
Finished Jun 25 05:25:31 PM PDT 24
Peak memory 204728 kb
Host smart-00368688-0525-4dc5-b77f-a809242a0fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305685930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3305685930
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1492947179
Short name T204
Test name
Test status
Simulation time 266835418 ps
CPU time 0.9 seconds
Started Jun 25 05:25:28 PM PDT 24
Finished Jun 25 05:25:32 PM PDT 24
Peak memory 204932 kb
Host smart-fb04a943-6743-4e80-91c8-306d28eff47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492947179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1492947179
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2779913185
Short name T155
Test name
Test status
Simulation time 165433730 ps
CPU time 0.82 seconds
Started Jun 25 05:25:41 PM PDT 24
Finished Jun 25 05:25:44 PM PDT 24
Peak memory 204916 kb
Host smart-9dbc8f5e-d12f-4e1d-8dd6-34cb57295aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779913185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2779913185
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.4056700727
Short name T34
Test name
Test status
Simulation time 19175136 ps
CPU time 0.85 seconds
Started Jun 25 05:25:44 PM PDT 24
Finished Jun 25 05:25:46 PM PDT 24
Peak memory 222860 kb
Host smart-39216463-c25e-4178-89f4-92ecdeca3f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056700727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.4056700727
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3995827704
Short name T38
Test name
Test status
Simulation time 2784251853 ps
CPU time 8.51 seconds
Started Jun 25 05:25:29 PM PDT 24
Finished Jun 25 05:25:40 PM PDT 24
Peak memory 205404 kb
Host smart-4747daa2-263a-4f88-ac55-117795d8f2b1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3995827704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3995827704
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1888325923
Short name T53
Test name
Test status
Simulation time 672060493 ps
CPU time 1.51 seconds
Started Jun 25 05:25:37 PM PDT 24
Finished Jun 25 05:25:40 PM PDT 24
Peak memory 204920 kb
Host smart-79c5e570-45d9-4842-bd0a-174d35842656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888325923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1888325923
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.492502650
Short name T229
Test name
Test status
Simulation time 238356789 ps
CPU time 1.01 seconds
Started Jun 25 05:25:35 PM PDT 24
Finished Jun 25 05:25:37 PM PDT 24
Peak memory 204816 kb
Host smart-247be9ff-d4a2-4def-b096-585caaaf71de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492502650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.492502650
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2182767606
Short name T198
Test name
Test status
Simulation time 701538858 ps
CPU time 0.9 seconds
Started Jun 25 05:25:33 PM PDT 24
Finished Jun 25 05:25:36 PM PDT 24
Peak memory 204776 kb
Host smart-27097d6c-5718-4737-bc4f-5c30e0b2ea13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182767606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2182767606
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3691422121
Short name T228
Test name
Test status
Simulation time 1836026933 ps
CPU time 1.37 seconds
Started Jun 25 05:25:42 PM PDT 24
Finished Jun 25 05:25:45 PM PDT 24
Peak memory 204752 kb
Host smart-fe15fe51-aed3-4b7a-8577-29cd2b7a6ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691422121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3691422121
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2864107174
Short name T247
Test name
Test status
Simulation time 2617550539 ps
CPU time 7.18 seconds
Started Jun 25 05:25:36 PM PDT 24
Finished Jun 25 05:25:45 PM PDT 24
Peak memory 204788 kb
Host smart-eb04439f-eeaf-4189-96bc-ccab5481ce29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864107174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2864107174
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1971625437
Short name T208
Test name
Test status
Simulation time 403617165 ps
CPU time 1.15 seconds
Started Jun 25 05:25:44 PM PDT 24
Finished Jun 25 05:25:47 PM PDT 24
Peak memory 204776 kb
Host smart-fab38f50-ecf7-478c-8670-c54e33f81362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971625437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1971625437
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2541056428
Short name T226
Test name
Test status
Simulation time 276144674 ps
CPU time 1.45 seconds
Started Jun 25 05:25:41 PM PDT 24
Finished Jun 25 05:25:44 PM PDT 24
Peak memory 204948 kb
Host smart-78ef8410-9320-4816-a9eb-1ae5f2273f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541056428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2541056428
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3334892217
Short name T144
Test name
Test status
Simulation time 790178275 ps
CPU time 2.96 seconds
Started Jun 25 05:25:28 PM PDT 24
Finished Jun 25 05:25:33 PM PDT 24
Peak memory 205204 kb
Host smart-5fd81236-72b4-4180-abc4-b5cff5e65cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334892217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3334892217
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.1684220243
Short name T154
Test name
Test status
Simulation time 566666508 ps
CPU time 1.63 seconds
Started Jun 25 05:25:33 PM PDT 24
Finished Jun 25 05:25:36 PM PDT 24
Peak memory 204928 kb
Host smart-4a8e1995-ed86-4a62-9330-d4e53facd0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684220243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1684220243
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3965026842
Short name T19
Test name
Test status
Simulation time 1437370367 ps
CPU time 1.48 seconds
Started Jun 25 05:25:33 PM PDT 24
Finished Jun 25 05:25:36 PM PDT 24
Peak memory 204928 kb
Host smart-89d0f01a-21f6-46c0-a3ca-de952439d599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965026842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3965026842
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2564334304
Short name T54
Test name
Test status
Simulation time 793332001 ps
CPU time 2.99 seconds
Started Jun 25 05:25:42 PM PDT 24
Finished Jun 25 05:25:47 PM PDT 24
Peak memory 204784 kb
Host smart-ccb06ded-9fdb-4dfc-b0fd-954d9816c7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564334304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2564334304
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.167193356
Short name T6
Test name
Test status
Simulation time 69000138 ps
CPU time 0.82 seconds
Started Jun 25 05:25:37 PM PDT 24
Finished Jun 25 05:25:40 PM PDT 24
Peak memory 215660 kb
Host smart-796f9bd6-c877-46d1-826d-35664a11dfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167193356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.167193356
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2587326013
Short name T248
Test name
Test status
Simulation time 859186299 ps
CPU time 1.31 seconds
Started Jun 25 05:25:33 PM PDT 24
Finished Jun 25 05:25:36 PM PDT 24
Peak memory 204780 kb
Host smart-45dd6906-dd2a-4059-a58d-745c8077f91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587326013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2587326013
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1383669523
Short name T237
Test name
Test status
Simulation time 3604099480 ps
CPU time 9.31 seconds
Started Jun 25 05:25:36 PM PDT 24
Finished Jun 25 05:25:47 PM PDT 24
Peak memory 205320 kb
Host smart-2d72a68e-6787-4c99-9ebb-e462163a6a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383669523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1383669523
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.452406239
Short name T58
Test name
Test status
Simulation time 2355661337 ps
CPU time 6.63 seconds
Started Jun 25 05:25:37 PM PDT 24
Finished Jun 25 05:25:45 PM PDT 24
Peak memory 229332 kb
Host smart-31ba571c-ec8a-4088-916d-5233ce8c1d8a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452406239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.452406239
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1110924096
Short name T196
Test name
Test status
Simulation time 2716744718 ps
CPU time 4.87 seconds
Started Jun 25 05:25:41 PM PDT 24
Finished Jun 25 05:25:47 PM PDT 24
Peak memory 204836 kb
Host smart-65104ba8-fef6-414a-b20c-ad5933fd68a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110924096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1110924096
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.3500250441
Short name T143
Test name
Test status
Simulation time 8944419586 ps
CPU time 12.32 seconds
Started Jun 25 05:25:41 PM PDT 24
Finished Jun 25 05:25:54 PM PDT 24
Peak memory 213316 kb
Host smart-ec837f62-0dc7-4af1-8803-3d23f740f216
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500250441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3500250441
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.571271303
Short name T33
Test name
Test status
Simulation time 210409829 ps
CPU time 0.76 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:11 PM PDT 24
Peak memory 204892 kb
Host smart-a9f6c117-6657-41f6-a3bc-6307379311d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571271303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.571271303
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.4098416257
Short name T264
Test name
Test status
Simulation time 10372033044 ps
CPU time 4.67 seconds
Started Jun 25 05:25:51 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 213440 kb
Host smart-70632e7d-1204-48a9-9ca0-9741de999e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098416257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.4098416257
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2015530244
Short name T262
Test name
Test status
Simulation time 3459767597 ps
CPU time 3.12 seconds
Started Jun 25 05:25:49 PM PDT 24
Finished Jun 25 05:25:55 PM PDT 24
Peak memory 205288 kb
Host smart-04eaffd7-052b-4317-82a6-b73ba5dd1382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015530244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2015530244
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3289781470
Short name T41
Test name
Test status
Simulation time 5083548764 ps
CPU time 14.14 seconds
Started Jun 25 05:25:51 PM PDT 24
Finished Jun 25 05:26:08 PM PDT 24
Peak memory 205328 kb
Host smart-f99323d4-6d70-4be5-81c0-91dd7ad85c68
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3289781470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3289781470
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3008533553
Short name T197
Test name
Test status
Simulation time 1238519557 ps
CPU time 1.88 seconds
Started Jun 25 05:26:10 PM PDT 24
Finished Jun 25 05:26:14 PM PDT 24
Peak memory 205216 kb
Host smart-76396af0-ad1b-414d-9ff4-7f04c8c1b720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008533553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3008533553
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2250541908
Short name T68
Test name
Test status
Simulation time 138179932 ps
CPU time 1.04 seconds
Started Jun 25 05:26:03 PM PDT 24
Finished Jun 25 05:26:05 PM PDT 24
Peak memory 204984 kb
Host smart-94bd4cb4-0112-4db4-86dc-25e356c90fc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250541908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2250541908
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2380376889
Short name T246
Test name
Test status
Simulation time 1781853111 ps
CPU time 3.1 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:14 PM PDT 24
Peak memory 205280 kb
Host smart-d370e498-2ba4-449f-8601-8957309ff524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380376889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2380376889
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.514993831
Short name T275
Test name
Test status
Simulation time 5133881934 ps
CPU time 13.48 seconds
Started Jun 25 05:25:54 PM PDT 24
Finished Jun 25 05:26:09 PM PDT 24
Peak memory 205340 kb
Host smart-c816e84a-5f43-4189-a9d9-e086deb05e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514993831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.514993831
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3227544886
Short name T234
Test name
Test status
Simulation time 1938659428 ps
CPU time 2.57 seconds
Started Jun 25 05:25:51 PM PDT 24
Finished Jun 25 05:25:56 PM PDT 24
Peak memory 204908 kb
Host smart-1e775ea0-b269-4842-bca7-1d9f19e085ea
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3227544886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3227544886
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1239523042
Short name T272
Test name
Test status
Simulation time 5121643141 ps
CPU time 5.73 seconds
Started Jun 25 05:26:09 PM PDT 24
Finished Jun 25 05:26:17 PM PDT 24
Peak memory 205264 kb
Host smart-c2db055f-f88a-42a4-ab33-118e116c2c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239523042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1239523042
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.1841373541
Short name T142
Test name
Test status
Simulation time 1451064754 ps
CPU time 2.15 seconds
Started Jun 25 05:25:51 PM PDT 24
Finished Jun 25 05:25:56 PM PDT 24
Peak memory 205116 kb
Host smart-d6ecda35-7a63-4406-9e33-0ffcca2ccb7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841373541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1841373541
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2153185909
Short name T169
Test name
Test status
Simulation time 140311949 ps
CPU time 0.85 seconds
Started Jun 25 05:25:53 PM PDT 24
Finished Jun 25 05:25:56 PM PDT 24
Peak memory 204972 kb
Host smart-eb05eba2-3544-487a-86bd-be3ae658b6b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153185909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2153185909
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3450684775
Short name T282
Test name
Test status
Simulation time 6257303210 ps
CPU time 5.38 seconds
Started Jun 25 05:25:49 PM PDT 24
Finished Jun 25 05:25:57 PM PDT 24
Peak memory 205420 kb
Host smart-dfb9c0e7-d873-4433-82ee-65df7f4252c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450684775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3450684775
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.292012782
Short name T286
Test name
Test status
Simulation time 2579410472 ps
CPU time 3.6 seconds
Started Jun 25 05:25:49 PM PDT 24
Finished Jun 25 05:25:55 PM PDT 24
Peak memory 205268 kb
Host smart-e991f9b4-3b2c-482e-a9a2-844a8b047119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292012782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.292012782
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2265179591
Short name T254
Test name
Test status
Simulation time 12411010821 ps
CPU time 11.84 seconds
Started Jun 25 05:25:53 PM PDT 24
Finished Jun 25 05:26:07 PM PDT 24
Peak memory 205412 kb
Host smart-2ba41009-c2b7-4df4-a913-b722d8c7d1ee
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2265179591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2265179591
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3992559180
Short name T217
Test name
Test status
Simulation time 3693232443 ps
CPU time 1.93 seconds
Started Jun 25 05:26:15 PM PDT 24
Finished Jun 25 05:26:19 PM PDT 24
Peak memory 205336 kb
Host smart-58a29236-d7bf-4161-84fa-7932da382ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992559180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3992559180
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3814989338
Short name T17
Test name
Test status
Simulation time 7527493962 ps
CPU time 7.04 seconds
Started Jun 25 05:26:07 PM PDT 24
Finished Jun 25 05:26:16 PM PDT 24
Peak memory 205268 kb
Host smart-3b902baa-7d2d-4d67-aeda-b9359f06aa21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814989338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3814989338
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.760577778
Short name T168
Test name
Test status
Simulation time 121898327 ps
CPU time 0.99 seconds
Started Jun 25 05:25:49 PM PDT 24
Finished Jun 25 05:25:53 PM PDT 24
Peak memory 205132 kb
Host smart-c7763f5e-4939-4e65-8e14-2b204fbbcc51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760577778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.760577778
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.3499166451
Short name T224
Test name
Test status
Simulation time 18478990067 ps
CPU time 31.28 seconds
Started Jun 25 05:25:48 PM PDT 24
Finished Jun 25 05:26:20 PM PDT 24
Peak memory 217780 kb
Host smart-49852b68-065b-4ba5-a6af-ef643a5797cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499166451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3499166451
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1192106872
Short name T288
Test name
Test status
Simulation time 7659597175 ps
CPU time 6.34 seconds
Started Jun 25 05:25:48 PM PDT 24
Finished Jun 25 05:25:56 PM PDT 24
Peak memory 213612 kb
Host smart-c19bd675-a140-4860-a463-d6ca4d1a4744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192106872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1192106872
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2165661918
Short name T238
Test name
Test status
Simulation time 2370467429 ps
CPU time 2.04 seconds
Started Jun 25 05:25:58 PM PDT 24
Finished Jun 25 05:26:02 PM PDT 24
Peak memory 205372 kb
Host smart-04c34d43-f2d0-4fe0-a73d-2a68abc6fc5e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2165661918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2165661918
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.174768461
Short name T14
Test name
Test status
Simulation time 2896879990 ps
CPU time 4.71 seconds
Started Jun 25 05:25:51 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 204996 kb
Host smart-8c06810d-4467-453e-8c03-98a03d685fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174768461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.174768461
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.3750600060
Short name T81
Test name
Test status
Simulation time 1680637945 ps
CPU time 3.12 seconds
Started Jun 25 05:25:56 PM PDT 24
Finished Jun 25 05:26:00 PM PDT 24
Peak memory 205084 kb
Host smart-482c28a8-9e04-400a-b138-395c3c4d1360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750600060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3750600060
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3193341074
Short name T223
Test name
Test status
Simulation time 6563108483 ps
CPU time 3.53 seconds
Started Jun 25 05:25:50 PM PDT 24
Finished Jun 25 05:25:56 PM PDT 24
Peak memory 205412 kb
Host smart-f0159e06-b366-4497-a58d-a69d787ee589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193341074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3193341074
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1808690761
Short name T260
Test name
Test status
Simulation time 1163860522 ps
CPU time 1.76 seconds
Started Jun 25 05:25:49 PM PDT 24
Finished Jun 25 05:25:52 PM PDT 24
Peak memory 205248 kb
Host smart-1c1437dd-a02a-4e2d-9d07-b7d6b13d71ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808690761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1808690761
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1243201922
Short name T220
Test name
Test status
Simulation time 935710160 ps
CPU time 1.68 seconds
Started Jun 25 05:25:48 PM PDT 24
Finished Jun 25 05:25:50 PM PDT 24
Peak memory 205248 kb
Host smart-f627be26-979d-4adc-8305-5daa6db39b33
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243201922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1243201922
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3516506803
Short name T261
Test name
Test status
Simulation time 4391017442 ps
CPU time 6.27 seconds
Started Jun 25 05:26:03 PM PDT 24
Finished Jun 25 05:26:10 PM PDT 24
Peak memory 205400 kb
Host smart-b2a8009a-ff4e-409f-814e-3365a8efffe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516506803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3516506803
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.124731134
Short name T52
Test name
Test status
Simulation time 7566563373 ps
CPU time 19.48 seconds
Started Jun 25 05:25:50 PM PDT 24
Finished Jun 25 05:26:12 PM PDT 24
Peak memory 205208 kb
Host smart-5db7fe53-0e3e-46d0-a366-de49cbce8ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124731134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.124731134
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1567243786
Short name T180
Test name
Test status
Simulation time 100020482 ps
CPU time 0.75 seconds
Started Jun 25 05:25:50 PM PDT 24
Finished Jun 25 05:25:54 PM PDT 24
Peak memory 204992 kb
Host smart-cc39fa57-5dfb-4a5b-b176-ec7b0931b2fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567243786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1567243786
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3076705006
Short name T243
Test name
Test status
Simulation time 5201235300 ps
CPU time 8 seconds
Started Jun 25 05:25:52 PM PDT 24
Finished Jun 25 05:26:03 PM PDT 24
Peak memory 213564 kb
Host smart-6a8b8dcc-4dea-454a-988f-802924064f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076705006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3076705006
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3283674287
Short name T257
Test name
Test status
Simulation time 4434268435 ps
CPU time 3.59 seconds
Started Jun 25 05:25:58 PM PDT 24
Finished Jun 25 05:26:03 PM PDT 24
Peak memory 205400 kb
Host smart-8195a8a1-642f-4f9f-b65d-00f5956a9f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283674287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3283674287
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3462433642
Short name T283
Test name
Test status
Simulation time 2472854298 ps
CPU time 7.27 seconds
Started Jun 25 05:25:49 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 205352 kb
Host smart-6521e18c-2715-496a-a892-4a0c9562558b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3462433642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3462433642
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.3167420074
Short name T280
Test name
Test status
Simulation time 1728505992 ps
CPU time 5.1 seconds
Started Jun 25 05:25:49 PM PDT 24
Finished Jun 25 05:25:57 PM PDT 24
Peak memory 205244 kb
Host smart-2e4f7269-afa3-48f0-a219-2b54de7042d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167420074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3167420074
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.31373203
Short name T146
Test name
Test status
Simulation time 18172070388 ps
CPU time 49.83 seconds
Started Jun 25 05:25:50 PM PDT 24
Finished Jun 25 05:26:43 PM PDT 24
Peak memory 205248 kb
Host smart-affe22c3-c056-4227-8a6a-10568b4c6dd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31373203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.31373203
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3869063528
Short name T182
Test name
Test status
Simulation time 85787943 ps
CPU time 0.76 seconds
Started Jun 25 05:25:57 PM PDT 24
Finished Jun 25 05:26:00 PM PDT 24
Peak memory 204976 kb
Host smart-1a66c6eb-4605-4756-be7b-4f5657f2b417
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869063528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3869063528
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1179684261
Short name T250
Test name
Test status
Simulation time 22541314375 ps
CPU time 20.03 seconds
Started Jun 25 05:25:53 PM PDT 24
Finished Jun 25 05:26:15 PM PDT 24
Peak memory 213616 kb
Host smart-77ea1dcf-ccd8-4a30-88a5-100d95e96402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179684261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1179684261
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1280472277
Short name T281
Test name
Test status
Simulation time 2388246338 ps
CPU time 3.86 seconds
Started Jun 25 05:25:52 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 205396 kb
Host smart-0030cbfa-8a1b-42e9-ac01-eaabca918684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280472277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1280472277
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.4265126307
Short name T263
Test name
Test status
Simulation time 1520543686 ps
CPU time 3.62 seconds
Started Jun 25 05:25:58 PM PDT 24
Finished Jun 25 05:26:03 PM PDT 24
Peak memory 205272 kb
Host smart-44422cd5-bcc2-4358-b89f-7562457de48b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4265126307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.4265126307
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2375942953
Short name T205
Test name
Test status
Simulation time 2934833073 ps
CPU time 3.25 seconds
Started Jun 25 05:25:52 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 205332 kb
Host smart-8089e172-19d8-4727-96d0-11aa2964c5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375942953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2375942953
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2293079420
Short name T36
Test name
Test status
Simulation time 36236167 ps
CPU time 0.76 seconds
Started Jun 25 05:25:50 PM PDT 24
Finished Jun 25 05:25:53 PM PDT 24
Peak memory 204988 kb
Host smart-059c2981-9aa0-45d3-b6b7-ebddcf15e3b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293079420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2293079420
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2977690174
Short name T244
Test name
Test status
Simulation time 4651157983 ps
CPU time 4.56 seconds
Started Jun 25 05:25:50 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 205356 kb
Host smart-75528501-8a38-4ed9-a47e-60a49078957e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977690174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2977690174
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.393109148
Short name T279
Test name
Test status
Simulation time 5187505443 ps
CPU time 3.63 seconds
Started Jun 25 05:25:56 PM PDT 24
Finished Jun 25 05:26:01 PM PDT 24
Peak memory 205380 kb
Host smart-eb8faa44-52f8-44c0-8467-28aa943e3742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393109148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.393109148
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1683720552
Short name T269
Test name
Test status
Simulation time 10522634364 ps
CPU time 7.68 seconds
Started Jun 25 05:25:49 PM PDT 24
Finished Jun 25 05:25:59 PM PDT 24
Peak memory 205364 kb
Host smart-64ab1dee-1dcb-4509-aa24-16a6ba9f08c4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1683720552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1683720552
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3334122531
Short name T231
Test name
Test status
Simulation time 3408577026 ps
CPU time 2.86 seconds
Started Jun 25 05:25:50 PM PDT 24
Finished Jun 25 05:25:56 PM PDT 24
Peak memory 205248 kb
Host smart-12264923-3612-4fc6-ad8f-cadde5e3228b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334122531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3334122531
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2334904675
Short name T170
Test name
Test status
Simulation time 67172280 ps
CPU time 0.85 seconds
Started Jun 25 05:25:48 PM PDT 24
Finished Jun 25 05:25:50 PM PDT 24
Peak memory 204976 kb
Host smart-5628b933-dd03-4b47-b839-39af57cd06c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334904675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2334904675
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2483993750
Short name T266
Test name
Test status
Simulation time 7227840546 ps
CPU time 4.14 seconds
Started Jun 25 05:25:49 PM PDT 24
Finished Jun 25 05:25:56 PM PDT 24
Peak memory 205540 kb
Host smart-031d76de-7563-4491-86d0-ce031852fc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483993750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2483993750
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.200099003
Short name T222
Test name
Test status
Simulation time 4539417585 ps
CPU time 3.91 seconds
Started Jun 25 05:25:52 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 213628 kb
Host smart-3b496227-87b2-4a27-86bb-50896d0e3db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200099003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.200099003
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1401432531
Short name T218
Test name
Test status
Simulation time 5635361464 ps
CPU time 9.07 seconds
Started Jun 25 05:25:50 PM PDT 24
Finished Jun 25 05:26:02 PM PDT 24
Peak memory 205408 kb
Host smart-8c32cb00-4ef0-40bf-9157-8593993112e7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401432531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1401432531
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3318616509
Short name T235
Test name
Test status
Simulation time 1985501489 ps
CPU time 6.71 seconds
Started Jun 25 05:26:00 PM PDT 24
Finished Jun 25 05:26:08 PM PDT 24
Peak memory 205280 kb
Host smart-05bcc09c-704c-472a-acb2-2cc0016557f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318616509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3318616509
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1133120180
Short name T72
Test name
Test status
Simulation time 63035815 ps
CPU time 0.83 seconds
Started Jun 25 05:25:51 PM PDT 24
Finished Jun 25 05:25:54 PM PDT 24
Peak memory 204976 kb
Host smart-7babb1ed-fc77-4dd6-8a14-5a0e5e836e5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133120180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1133120180
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1639262143
Short name T251
Test name
Test status
Simulation time 34777945413 ps
CPU time 27.1 seconds
Started Jun 25 05:26:04 PM PDT 24
Finished Jun 25 05:26:32 PM PDT 24
Peak memory 213576 kb
Host smart-5d66a193-77b5-4bf4-979c-0f7587c008c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639262143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1639262143
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.18375718
Short name T271
Test name
Test status
Simulation time 2608311766 ps
CPU time 7.58 seconds
Started Jun 25 05:25:49 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 205244 kb
Host smart-24ccf53b-43b6-4324-9034-72b292a3eeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18375718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.18375718
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3345742371
Short name T207
Test name
Test status
Simulation time 2519580618 ps
CPU time 3.29 seconds
Started Jun 25 05:26:05 PM PDT 24
Finished Jun 25 05:26:10 PM PDT 24
Peak memory 205280 kb
Host smart-2f594d12-5cb3-48f4-bd71-de7fefd0beae
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345742371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3345742371
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3121434811
Short name T284
Test name
Test status
Simulation time 7344909550 ps
CPU time 4.84 seconds
Started Jun 25 05:26:05 PM PDT 24
Finished Jun 25 05:26:11 PM PDT 24
Peak memory 205404 kb
Host smart-0ee732b2-2270-4d1a-a1bf-283effe7ed1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121434811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3121434811
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.67531139
Short name T5
Test name
Test status
Simulation time 1335349175 ps
CPU time 2.83 seconds
Started Jun 25 05:25:51 PM PDT 24
Finished Jun 25 05:25:56 PM PDT 24
Peak memory 205044 kb
Host smart-1eb5002a-626b-428c-b754-ddc547e98ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67531139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.67531139
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2961285958
Short name T116
Test name
Test status
Simulation time 190846958 ps
CPU time 0.81 seconds
Started Jun 25 05:25:36 PM PDT 24
Finished Jun 25 05:25:39 PM PDT 24
Peak memory 204996 kb
Host smart-5bd79512-1440-49a8-ab77-d337d7979b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961285958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2961285958
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.2509245104
Short name T233
Test name
Test status
Simulation time 82700334301 ps
CPU time 70.21 seconds
Started Jun 25 05:25:51 PM PDT 24
Finished Jun 25 05:27:04 PM PDT 24
Peak memory 215964 kb
Host smart-2aaf96a1-9ddb-49eb-832b-977aa8a2f936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509245104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2509245104
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.137586174
Short name T39
Test name
Test status
Simulation time 8219072599 ps
CPU time 21.39 seconds
Started Jun 25 05:25:42 PM PDT 24
Finished Jun 25 05:26:05 PM PDT 24
Peak memory 205392 kb
Host smart-23153851-96cc-49bf-9da2-e1d4601899eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137586174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.137586174
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3345040402
Short name T201
Test name
Test status
Simulation time 2681487344 ps
CPU time 7.36 seconds
Started Jun 25 05:25:32 PM PDT 24
Finished Jun 25 05:25:41 PM PDT 24
Peak memory 205344 kb
Host smart-658e813e-0674-4f53-8d72-5ba645e12ac4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345040402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3345040402
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3279043578
Short name T65
Test name
Test status
Simulation time 533931697 ps
CPU time 2.2 seconds
Started Jun 25 05:25:35 PM PDT 24
Finished Jun 25 05:25:39 PM PDT 24
Peak memory 204796 kb
Host smart-a8a750ed-fe8b-4bd6-be7d-aa1584a43315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279043578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3279043578
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.306275733
Short name T259
Test name
Test status
Simulation time 1379321792 ps
CPU time 4.55 seconds
Started Jun 25 05:25:43 PM PDT 24
Finished Jun 25 05:25:49 PM PDT 24
Peak memory 205280 kb
Host smart-f0d4273c-e897-4ca4-9695-1f42256a04c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306275733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.306275733
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.614124095
Short name T67
Test name
Test status
Simulation time 347993927 ps
CPU time 1.41 seconds
Started Jun 25 05:25:35 PM PDT 24
Finished Jun 25 05:25:39 PM PDT 24
Peak memory 228204 kb
Host smart-a1c70ffe-b03d-4ff9-80b8-579d9620cc23
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614124095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.614124095
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.110490861
Short name T160
Test name
Test status
Simulation time 8007090230 ps
CPU time 19.62 seconds
Started Jun 25 05:25:41 PM PDT 24
Finished Jun 25 05:26:01 PM PDT 24
Peak memory 213360 kb
Host smart-04a8eb28-7d9b-4fdd-b7be-9dce5bae3a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110490861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.110490861
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2682566190
Short name T174
Test name
Test status
Simulation time 60605585 ps
CPU time 0.83 seconds
Started Jun 25 05:26:11 PM PDT 24
Finished Jun 25 05:26:14 PM PDT 24
Peak memory 204980 kb
Host smart-046d1215-468a-43cf-a3b8-5b05a60cbb4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682566190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2682566190
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2338267368
Short name T249
Test name
Test status
Simulation time 2924601896 ps
CPU time 9.55 seconds
Started Jun 25 05:25:52 PM PDT 24
Finished Jun 25 05:26:04 PM PDT 24
Peak memory 205116 kb
Host smart-cccc5537-c95c-448f-8772-e87c3ab3a824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338267368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2338267368
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3564731663
Short name T273
Test name
Test status
Simulation time 99706904 ps
CPU time 0.78 seconds
Started Jun 25 05:25:53 PM PDT 24
Finished Jun 25 05:25:56 PM PDT 24
Peak memory 204984 kb
Host smart-f95f47a1-7ca7-4dbd-ab2c-79f722f875f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564731663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3564731663
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3468534522
Short name T162
Test name
Test status
Simulation time 59877618 ps
CPU time 0.78 seconds
Started Jun 25 05:25:51 PM PDT 24
Finished Jun 25 05:25:55 PM PDT 24
Peak memory 204976 kb
Host smart-63e49e6a-60bd-4ac7-b74f-cd8eccc39bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468534522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3468534522
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.109276018
Short name T139
Test name
Test status
Simulation time 4451379542 ps
CPU time 7.84 seconds
Started Jun 25 05:26:02 PM PDT 24
Finished Jun 25 05:26:11 PM PDT 24
Peak memory 205252 kb
Host smart-e8bbaa48-a299-4330-a8d1-f9e54c74b820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109276018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.109276018
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1294725993
Short name T176
Test name
Test status
Simulation time 34915781 ps
CPU time 0.75 seconds
Started Jun 25 05:25:56 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 204976 kb
Host smart-aa2ed591-a3ba-4253-94be-2e8117b9b27a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294725993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1294725993
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.1465891538
Short name T156
Test name
Test status
Simulation time 17362931486 ps
CPU time 16.76 seconds
Started Jun 25 05:25:58 PM PDT 24
Finished Jun 25 05:26:16 PM PDT 24
Peak memory 213456 kb
Host smart-974c408c-e460-4b5b-b6bd-40e953fbef0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465891538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1465891538
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1531481160
Short name T172
Test name
Test status
Simulation time 48667452 ps
CPU time 0.81 seconds
Started Jun 25 05:26:00 PM PDT 24
Finished Jun 25 05:26:02 PM PDT 24
Peak memory 204916 kb
Host smart-5e2daccc-39f4-4ee4-8aed-9175df642fb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531481160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1531481160
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.3241997003
Short name T152
Test name
Test status
Simulation time 14659753174 ps
CPU time 13.04 seconds
Started Jun 25 05:26:02 PM PDT 24
Finished Jun 25 05:26:16 PM PDT 24
Peak memory 205260 kb
Host smart-61f7a79f-0501-4c1c-95f2-f77889d416b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241997003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.3241997003
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2555769232
Short name T193
Test name
Test status
Simulation time 29543272 ps
CPU time 0.78 seconds
Started Jun 25 05:25:56 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 204760 kb
Host smart-eb01c1da-91d5-4e22-b928-f6320ca84f36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555769232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2555769232
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.3585484418
Short name T30
Test name
Test status
Simulation time 10464223468 ps
CPU time 17.7 seconds
Started Jun 25 05:25:57 PM PDT 24
Finished Jun 25 05:26:17 PM PDT 24
Peak memory 205104 kb
Host smart-f6c35d06-8c81-4045-bdd9-492335a1dfce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585484418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3585484418
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.646323512
Short name T167
Test name
Test status
Simulation time 70285685 ps
CPU time 0.87 seconds
Started Jun 25 05:25:55 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 204972 kb
Host smart-0ccde2eb-55aa-42b8-983e-7226c4549900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646323512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.646323512
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.1902269619
Short name T22
Test name
Test status
Simulation time 4323126493 ps
CPU time 2.11 seconds
Started Jun 25 05:26:01 PM PDT 24
Finished Jun 25 05:26:04 PM PDT 24
Peak memory 205188 kb
Host smart-300c2447-6544-4fa1-8295-d694100990a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902269619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1902269619
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1655665840
Short name T163
Test name
Test status
Simulation time 35844406 ps
CPU time 0.79 seconds
Started Jun 25 05:26:09 PM PDT 24
Finished Jun 25 05:26:12 PM PDT 24
Peak memory 204860 kb
Host smart-e4de5811-8e68-4ae2-935e-2d4ebd8a5058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655665840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1655665840
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.3485494463
Short name T9
Test name
Test status
Simulation time 11540350649 ps
CPU time 13.25 seconds
Started Jun 25 05:26:06 PM PDT 24
Finished Jun 25 05:26:21 PM PDT 24
Peak memory 205280 kb
Host smart-e475c8fc-bfd5-41ed-bc7b-fc21fe6ce9e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485494463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3485494463
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3833530698
Short name T166
Test name
Test status
Simulation time 78267410 ps
CPU time 0.93 seconds
Started Jun 25 05:25:59 PM PDT 24
Finished Jun 25 05:26:01 PM PDT 24
Peak memory 205004 kb
Host smart-61da67a1-d6a9-4b26-9a29-c990e0d35e45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833530698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3833530698
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.2077659661
Short name T137
Test name
Test status
Simulation time 6827986884 ps
CPU time 9.64 seconds
Started Jun 25 05:26:00 PM PDT 24
Finished Jun 25 05:26:11 PM PDT 24
Peak memory 205252 kb
Host smart-ceaa141e-1e7d-4e71-a5a6-f4724928be24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077659661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2077659661
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2040697867
Short name T190
Test name
Test status
Simulation time 96894711 ps
CPU time 0.77 seconds
Started Jun 25 05:26:09 PM PDT 24
Finished Jun 25 05:26:12 PM PDT 24
Peak memory 205240 kb
Host smart-4ba9a27e-9003-4dfa-a926-adc6aef08942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040697867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2040697867
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.3586748927
Short name T150
Test name
Test status
Simulation time 4126846311 ps
CPU time 4.38 seconds
Started Jun 25 05:25:56 PM PDT 24
Finished Jun 25 05:26:02 PM PDT 24
Peak memory 205256 kb
Host smart-d81336bf-8053-4c9f-8f5b-c925532ebf23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586748927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3586748927
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2970293846
Short name T40
Test name
Test status
Simulation time 44531885 ps
CPU time 0.71 seconds
Started Jun 25 05:25:54 PM PDT 24
Finished Jun 25 05:25:56 PM PDT 24
Peak memory 204856 kb
Host smart-cadf0311-fa58-4090-82ab-f2c2b194c60b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970293846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2970293846
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.4009680082
Short name T219
Test name
Test status
Simulation time 17961506533 ps
CPU time 55.63 seconds
Started Jun 25 05:25:36 PM PDT 24
Finished Jun 25 05:26:34 PM PDT 24
Peak memory 213728 kb
Host smart-1e9149a9-2aca-4fa4-a221-c69afae6dd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009680082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.4009680082
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.532638045
Short name T258
Test name
Test status
Simulation time 9431026571 ps
CPU time 7.29 seconds
Started Jun 25 05:25:44 PM PDT 24
Finished Jun 25 05:25:53 PM PDT 24
Peak memory 205364 kb
Host smart-d20f6711-0c14-4b9b-be18-4191b1d01582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532638045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.532638045
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2297050337
Short name T13
Test name
Test status
Simulation time 5936707017 ps
CPU time 6.76 seconds
Started Jun 25 05:25:35 PM PDT 24
Finished Jun 25 05:25:44 PM PDT 24
Peak memory 205324 kb
Host smart-a31cfa0c-cae4-4c19-9248-e502265d762d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2297050337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2297050337
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2210432452
Short name T216
Test name
Test status
Simulation time 152555303 ps
CPU time 0.88 seconds
Started Jun 25 05:25:46 PM PDT 24
Finished Jun 25 05:25:48 PM PDT 24
Peak memory 204800 kb
Host smart-79c8f91c-37c1-43aa-b062-9364b8ededb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210432452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2210432452
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2129170077
Short name T199
Test name
Test status
Simulation time 9165536289 ps
CPU time 7.38 seconds
Started Jun 25 05:25:43 PM PDT 24
Finished Jun 25 05:25:52 PM PDT 24
Peak memory 205300 kb
Host smart-c3d18604-6534-4495-bb21-373b1a527df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129170077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2129170077
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1385178625
Short name T66
Test name
Test status
Simulation time 789905695 ps
CPU time 3.13 seconds
Started Jun 25 05:25:35 PM PDT 24
Finished Jun 25 05:25:40 PM PDT 24
Peak memory 228932 kb
Host smart-013b16a7-2366-4cb1-9bb5-7a9a9fd7451d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385178625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1385178625
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.324651329
Short name T141
Test name
Test status
Simulation time 11444206833 ps
CPU time 10.31 seconds
Started Jun 25 05:25:47 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 205188 kb
Host smart-be832a2e-2ba8-4d47-a29f-fd29d4b6fce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324651329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.324651329
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.39401845
Short name T185
Test name
Test status
Simulation time 63370245 ps
CPU time 0.72 seconds
Started Jun 25 05:25:59 PM PDT 24
Finished Jun 25 05:26:02 PM PDT 24
Peak memory 204896 kb
Host smart-88877fba-684c-43fc-a74a-9f17c8fc315a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39401845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.39401845
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.1395926854
Short name T145
Test name
Test status
Simulation time 3520488099 ps
CPU time 5.84 seconds
Started Jun 25 05:26:07 PM PDT 24
Finished Jun 25 05:26:15 PM PDT 24
Peak memory 205192 kb
Host smart-e4e859db-2e1f-47c0-b0a0-078f57f9d75b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395926854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1395926854
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2570665411
Short name T184
Test name
Test status
Simulation time 89286497 ps
CPU time 0.72 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:10 PM PDT 24
Peak memory 204896 kb
Host smart-e0d8528b-16fc-4d90-98a8-094222849722
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570665411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2570665411
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1577427630
Short name T161
Test name
Test status
Simulation time 11002110265 ps
CPU time 18.42 seconds
Started Jun 25 05:25:58 PM PDT 24
Finished Jun 25 05:26:18 PM PDT 24
Peak memory 205260 kb
Host smart-6100f76c-d49c-4ad2-bc34-2c8714c2119c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577427630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1577427630
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1101562791
Short name T118
Test name
Test status
Simulation time 43214496 ps
CPU time 0.85 seconds
Started Jun 25 05:25:58 PM PDT 24
Finished Jun 25 05:26:01 PM PDT 24
Peak memory 204948 kb
Host smart-9bbc1b9e-0c02-49d2-9b57-e7c0f58f0e7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101562791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1101562791
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.2557631761
Short name T151
Test name
Test status
Simulation time 7560154245 ps
CPU time 11.5 seconds
Started Jun 25 05:26:00 PM PDT 24
Finished Jun 25 05:26:13 PM PDT 24
Peak memory 213492 kb
Host smart-8233fff1-02db-47c5-a080-5efe51484819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557631761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.2557631761
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1835514268
Short name T188
Test name
Test status
Simulation time 130128080 ps
CPU time 1.07 seconds
Started Jun 25 05:25:56 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 204768 kb
Host smart-61a0744c-83a4-4365-a360-f96dbb62c319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835514268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1835514268
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.2822283575
Short name T31
Test name
Test status
Simulation time 19313622744 ps
CPU time 16.48 seconds
Started Jun 25 05:26:11 PM PDT 24
Finished Jun 25 05:26:29 PM PDT 24
Peak memory 213320 kb
Host smart-56ab6bba-d394-476d-8889-1afcfdb5b466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822283575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2822283575
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2405156988
Short name T73
Test name
Test status
Simulation time 84097447 ps
CPU time 0.76 seconds
Started Jun 25 05:26:06 PM PDT 24
Finished Jun 25 05:26:08 PM PDT 24
Peak memory 204976 kb
Host smart-6d3bafb3-fe9a-4cc7-8c30-803b687fe1c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405156988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2405156988
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1942575313
Short name T164
Test name
Test status
Simulation time 130214491 ps
CPU time 0.78 seconds
Started Jun 25 05:25:59 PM PDT 24
Finished Jun 25 05:26:01 PM PDT 24
Peak memory 205004 kb
Host smart-2f88f8f5-62d5-4299-adda-fee8bfaccf34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942575313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1942575313
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.3131137197
Short name T3
Test name
Test status
Simulation time 5109066967 ps
CPU time 13.64 seconds
Started Jun 25 05:25:59 PM PDT 24
Finished Jun 25 05:26:14 PM PDT 24
Peak memory 205304 kb
Host smart-d54abcc8-1b2b-4dc6-bab8-6bc1ae3424f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131137197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3131137197
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.485135507
Short name T119
Test name
Test status
Simulation time 141383708 ps
CPU time 0.73 seconds
Started Jun 25 05:26:13 PM PDT 24
Finished Jun 25 05:26:15 PM PDT 24
Peak memory 205000 kb
Host smart-899b6600-1301-4b77-8779-47af33afb2e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485135507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.485135507
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.1312661573
Short name T15
Test name
Test status
Simulation time 8201956888 ps
CPU time 20.06 seconds
Started Jun 25 05:26:11 PM PDT 24
Finished Jun 25 05:26:33 PM PDT 24
Peak memory 205280 kb
Host smart-b50822df-9c21-4d3e-8bc1-b4e5902c70ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312661573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1312661573
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.1712687118
Short name T178
Test name
Test status
Simulation time 38204219 ps
CPU time 0.73 seconds
Started Jun 25 05:25:56 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 204980 kb
Host smart-356b9221-fe19-4327-bf0d-2f96a24cd458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712687118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.1712687118
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.4221881497
Short name T256
Test name
Test status
Simulation time 9430979953 ps
CPU time 26.65 seconds
Started Jun 25 05:26:02 PM PDT 24
Finished Jun 25 05:26:30 PM PDT 24
Peak memory 205188 kb
Host smart-8d00978d-1ae1-456c-8982-89ee06789c3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221881497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.4221881497
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2634245060
Short name T179
Test name
Test status
Simulation time 65117255 ps
CPU time 0.71 seconds
Started Jun 25 05:25:58 PM PDT 24
Finished Jun 25 05:26:00 PM PDT 24
Peak memory 204996 kb
Host smart-89c6e60b-d78a-4dc7-9ee2-2235ccd9660e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634245060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2634245060
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.3616032568
Short name T10
Test name
Test status
Simulation time 6565284918 ps
CPU time 16.15 seconds
Started Jun 25 05:26:08 PM PDT 24
Finished Jun 25 05:26:26 PM PDT 24
Peak memory 205216 kb
Host smart-e80cee87-4c5d-4590-b6c0-7682252abed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616032568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3616032568
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.2443639089
Short name T265
Test name
Test status
Simulation time 5890040889 ps
CPU time 15.89 seconds
Started Jun 25 05:26:03 PM PDT 24
Finished Jun 25 05:26:19 PM PDT 24
Peak memory 205196 kb
Host smart-854f7db7-e1f9-4903-8791-4c7e1881068b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443639089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.2443639089
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.243283669
Short name T165
Test name
Test status
Simulation time 64518288 ps
CPU time 0.84 seconds
Started Jun 25 05:25:47 PM PDT 24
Finished Jun 25 05:25:49 PM PDT 24
Peak memory 205004 kb
Host smart-a97cb47a-4543-4f2c-8893-816079215c85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243283669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.243283669
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2700280629
Short name T227
Test name
Test status
Simulation time 83723427654 ps
CPU time 129.97 seconds
Started Jun 25 05:25:40 PM PDT 24
Finished Jun 25 05:27:51 PM PDT 24
Peak memory 214488 kb
Host smart-bd382fae-46df-4524-8c87-3264dda4207d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700280629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2700280629
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3995286119
Short name T209
Test name
Test status
Simulation time 3387041919 ps
CPU time 2.75 seconds
Started Jun 25 05:25:47 PM PDT 24
Finished Jun 25 05:25:50 PM PDT 24
Peak memory 204524 kb
Host smart-57e9fb43-7e81-4f37-ad96-b4baad013113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995286119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3995286119
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3499704547
Short name T215
Test name
Test status
Simulation time 737160024 ps
CPU time 2.95 seconds
Started Jun 25 05:25:40 PM PDT 24
Finished Jun 25 05:25:44 PM PDT 24
Peak memory 205368 kb
Host smart-c603ddfd-a1b2-4e31-b06b-d31fcc462258
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3499704547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3499704547
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1750739196
Short name T221
Test name
Test status
Simulation time 236147362 ps
CPU time 0.98 seconds
Started Jun 25 05:25:38 PM PDT 24
Finished Jun 25 05:25:40 PM PDT 24
Peak memory 204696 kb
Host smart-bd5b8cdd-1c72-4b8e-89b8-4a3af604568f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750739196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1750739196
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1701466074
Short name T255
Test name
Test status
Simulation time 1653458090 ps
CPU time 4.18 seconds
Started Jun 25 05:25:44 PM PDT 24
Finished Jun 25 05:25:50 PM PDT 24
Peak memory 205268 kb
Host smart-f27e9d97-f54b-4dc1-898c-1c8d94464f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701466074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1701466074
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3058601362
Short name T183
Test name
Test status
Simulation time 111495153 ps
CPU time 0.76 seconds
Started Jun 25 05:26:04 PM PDT 24
Finished Jun 25 05:26:06 PM PDT 24
Peak memory 204980 kb
Host smart-1bb500de-d7a8-477f-b0cf-4614a56c70b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058601362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3058601362
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1367796651
Short name T270
Test name
Test status
Simulation time 159223957 ps
CPU time 0.8 seconds
Started Jun 25 05:26:09 PM PDT 24
Finished Jun 25 05:26:11 PM PDT 24
Peak memory 204572 kb
Host smart-94405f5e-5165-44e9-b824-977cd0486d4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367796651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1367796651
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.67849529
Short name T173
Test name
Test status
Simulation time 159147987 ps
CPU time 0.76 seconds
Started Jun 25 05:25:55 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 204976 kb
Host smart-606ccb08-ac75-4872-9ecd-1cdb32200e9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67849529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.67849529
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.2448196543
Short name T147
Test name
Test status
Simulation time 4612863940 ps
CPU time 7.23 seconds
Started Jun 25 05:25:58 PM PDT 24
Finished Jun 25 05:26:07 PM PDT 24
Peak memory 205208 kb
Host smart-743d00eb-a1e7-4b81-8b66-16522e0cefd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448196543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2448196543
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3319614932
Short name T189
Test name
Test status
Simulation time 29463062 ps
CPU time 0.77 seconds
Started Jun 25 05:26:00 PM PDT 24
Finished Jun 25 05:26:02 PM PDT 24
Peak memory 204916 kb
Host smart-509ce8f4-c735-4e79-91b0-9b593d0e57f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319614932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3319614932
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.2619908878
Short name T24
Test name
Test status
Simulation time 12336964721 ps
CPU time 5.37 seconds
Started Jun 25 05:25:59 PM PDT 24
Finished Jun 25 05:26:06 PM PDT 24
Peak memory 213456 kb
Host smart-b93ce032-31a2-49a5-a4af-7a416ac60afc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619908878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2619908878
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3469280150
Short name T177
Test name
Test status
Simulation time 43524751 ps
CPU time 0.75 seconds
Started Jun 25 05:26:09 PM PDT 24
Finished Jun 25 05:26:11 PM PDT 24
Peak memory 204672 kb
Host smart-1285fd59-ae82-4a0d-a617-ba42a227576f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469280150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3469280150
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.4220032063
Short name T148
Test name
Test status
Simulation time 7549944839 ps
CPU time 7.32 seconds
Started Jun 25 05:25:58 PM PDT 24
Finished Jun 25 05:26:07 PM PDT 24
Peak memory 213420 kb
Host smart-58d8b04b-e7e1-44b7-bfc2-3225a21d29ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220032063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.4220032063
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2385872692
Short name T37
Test name
Test status
Simulation time 88435556 ps
CPU time 0.75 seconds
Started Jun 25 05:26:11 PM PDT 24
Finished Jun 25 05:26:14 PM PDT 24
Peak memory 204924 kb
Host smart-04ab4d5a-4c81-4198-8926-8b5487279442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385872692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2385872692
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1877019993
Short name T159
Test name
Test status
Simulation time 11602576950 ps
CPU time 32.32 seconds
Started Jun 25 05:26:05 PM PDT 24
Finished Jun 25 05:26:38 PM PDT 24
Peak memory 205260 kb
Host smart-a5af0ec9-f63c-4e1d-81eb-722fcea95c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877019993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1877019993
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.578454573
Short name T186
Test name
Test status
Simulation time 34951725 ps
CPU time 0.78 seconds
Started Jun 25 05:26:07 PM PDT 24
Finished Jun 25 05:26:10 PM PDT 24
Peak memory 204968 kb
Host smart-dd4018ac-73c0-4604-b26e-d795e1302968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578454573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.578454573
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.609616293
Short name T153
Test name
Test status
Simulation time 4149501064 ps
CPU time 13.2 seconds
Started Jun 25 05:26:11 PM PDT 24
Finished Jun 25 05:26:26 PM PDT 24
Peak memory 205208 kb
Host smart-593ed6ba-2404-4489-9c0c-6826129dc7cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609616293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.609616293
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.584027026
Short name T230
Test name
Test status
Simulation time 59067313 ps
CPU time 0.7 seconds
Started Jun 25 05:26:04 PM PDT 24
Finished Jun 25 05:26:06 PM PDT 24
Peak memory 204980 kb
Host smart-fbb4c347-8358-43de-b67e-f0bd485052a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584027026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.584027026
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.3944695419
Short name T51
Test name
Test status
Simulation time 5269612109 ps
CPU time 4.02 seconds
Started Jun 25 05:26:11 PM PDT 24
Finished Jun 25 05:26:17 PM PDT 24
Peak memory 205200 kb
Host smart-207c5401-d219-4f5c-bb53-0543bce62453
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944695419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3944695419
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2498336366
Short name T175
Test name
Test status
Simulation time 40475216 ps
CPU time 0.78 seconds
Started Jun 25 05:25:56 PM PDT 24
Finished Jun 25 05:25:58 PM PDT 24
Peak memory 204980 kb
Host smart-bc29018e-19e6-4e67-b8a7-b2167f6981f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498336366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2498336366
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2546681793
Short name T191
Test name
Test status
Simulation time 169966521 ps
CPU time 0.85 seconds
Started Jun 25 05:26:07 PM PDT 24
Finished Jun 25 05:26:10 PM PDT 24
Peak memory 204976 kb
Host smart-fd758be9-3ab5-454d-90a9-bfd030a0f536
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546681793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2546681793
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.2328032261
Short name T158
Test name
Test status
Simulation time 5153155093 ps
CPU time 13.89 seconds
Started Jun 25 05:26:06 PM PDT 24
Finished Jun 25 05:26:22 PM PDT 24
Peak memory 205272 kb
Host smart-881e80ae-3a33-47a7-a63a-3aeb5d8e930d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328032261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2328032261
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3075205263
Short name T192
Test name
Test status
Simulation time 31656230 ps
CPU time 0.75 seconds
Started Jun 25 05:25:36 PM PDT 24
Finished Jun 25 05:25:38 PM PDT 24
Peak memory 204964 kb
Host smart-d6e6e9cb-94e7-464b-80a9-f8a74ed6935f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075205263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3075205263
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1571201961
Short name T245
Test name
Test status
Simulation time 16432170468 ps
CPU time 43.7 seconds
Started Jun 25 05:25:42 PM PDT 24
Finished Jun 25 05:26:27 PM PDT 24
Peak memory 213620 kb
Host smart-e4c92007-2dd3-40d7-843a-0103512ec9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571201961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1571201961
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.4177959812
Short name T252
Test name
Test status
Simulation time 4705635596 ps
CPU time 5.81 seconds
Started Jun 25 05:25:42 PM PDT 24
Finished Jun 25 05:25:49 PM PDT 24
Peak memory 205348 kb
Host smart-bfeec057-0a72-40c3-b339-1a63f3c4578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177959812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.4177959812
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1496046757
Short name T278
Test name
Test status
Simulation time 3292051494 ps
CPU time 3.41 seconds
Started Jun 25 05:25:43 PM PDT 24
Finished Jun 25 05:25:48 PM PDT 24
Peak memory 205404 kb
Host smart-8b0aa4b3-8a51-43ee-ba27-9e080a96f697
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496046757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1496046757
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2045969552
Short name T287
Test name
Test status
Simulation time 2788714641 ps
CPU time 3.14 seconds
Started Jun 25 05:25:49 PM PDT 24
Finished Jun 25 05:25:54 PM PDT 24
Peak memory 205412 kb
Host smart-0c7b3876-7a37-4725-929c-c6b4ccd10733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045969552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2045969552
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1115058690
Short name T32
Test name
Test status
Simulation time 42867126 ps
CPU time 0.78 seconds
Started Jun 25 05:25:36 PM PDT 24
Finished Jun 25 05:25:39 PM PDT 24
Peak memory 204996 kb
Host smart-19261952-a96d-44c2-971b-ac39d7a9f8ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115058690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1115058690
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2673347181
Short name T28
Test name
Test status
Simulation time 7501339148 ps
CPU time 18.41 seconds
Started Jun 25 05:25:42 PM PDT 24
Finished Jun 25 05:26:02 PM PDT 24
Peak memory 205372 kb
Host smart-a8f73c59-b54a-4cd6-878b-de52a6103cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673347181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2673347181
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1885950240
Short name T71
Test name
Test status
Simulation time 13338308701 ps
CPU time 6.95 seconds
Started Jun 25 05:25:46 PM PDT 24
Finished Jun 25 05:26:00 PM PDT 24
Peak memory 213528 kb
Host smart-cc3ca4a2-d299-45a5-aec0-44e83e83d39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885950240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1885950240
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1493470634
Short name T200
Test name
Test status
Simulation time 9299367693 ps
CPU time 8.53 seconds
Started Jun 25 05:25:39 PM PDT 24
Finished Jun 25 05:25:49 PM PDT 24
Peak memory 213580 kb
Host smart-45fee8b1-c829-41d0-87b5-d2ed499b1fb2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1493470634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1493470634
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1064933948
Short name T285
Test name
Test status
Simulation time 5843255034 ps
CPU time 9.49 seconds
Started Jun 25 05:25:35 PM PDT 24
Finished Jun 25 05:25:46 PM PDT 24
Peak memory 205384 kb
Host smart-95081a6c-386f-4887-8434-f9bb14f02bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064933948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1064933948
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.2398278447
Short name T8
Test name
Test status
Simulation time 2637675131 ps
CPU time 2.01 seconds
Started Jun 25 05:25:50 PM PDT 24
Finished Jun 25 05:25:55 PM PDT 24
Peak memory 205256 kb
Host smart-0a19439d-0da1-4fea-8a8c-81760fb96d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398278447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2398278447
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1082778037
Short name T171
Test name
Test status
Simulation time 69774939 ps
CPU time 0.83 seconds
Started Jun 25 05:25:55 PM PDT 24
Finished Jun 25 05:25:57 PM PDT 24
Peak memory 204924 kb
Host smart-e9579c96-efb1-4095-b258-9700bcd6a92d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082778037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1082778037
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3690448659
Short name T236
Test name
Test status
Simulation time 48911322358 ps
CPU time 12.03 seconds
Started Jun 25 05:25:51 PM PDT 24
Finished Jun 25 05:26:05 PM PDT 24
Peak memory 205368 kb
Host smart-5ffe1e37-1b81-4880-a7d2-ca7976dc18d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690448659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3690448659
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1776022353
Short name T276
Test name
Test status
Simulation time 2815042059 ps
CPU time 7.21 seconds
Started Jun 25 05:25:45 PM PDT 24
Finished Jun 25 05:25:54 PM PDT 24
Peak memory 205384 kb
Host smart-653bd59a-5365-485c-ac59-b5f29d5d6b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776022353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1776022353
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3546306129
Short name T203
Test name
Test status
Simulation time 1666296878 ps
CPU time 2.08 seconds
Started Jun 25 05:25:36 PM PDT 24
Finished Jun 25 05:25:40 PM PDT 24
Peak memory 205340 kb
Host smart-6e498557-8c8b-4419-87a4-645b4945380c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546306129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3546306129
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3723292150
Short name T268
Test name
Test status
Simulation time 9067930459 ps
CPU time 12.98 seconds
Started Jun 25 05:25:36 PM PDT 24
Finished Jun 25 05:25:51 PM PDT 24
Peak memory 205388 kb
Host smart-63d0a921-2b27-43e6-bdad-9f81f0f6ffc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723292150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3723292150
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.857772396
Short name T27
Test name
Test status
Simulation time 10370742179 ps
CPU time 26.18 seconds
Started Jun 25 05:25:41 PM PDT 24
Finished Jun 25 05:26:08 PM PDT 24
Peak memory 205100 kb
Host smart-aa146cd7-f90f-4e3a-b42f-371b856d51ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857772396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.857772396
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2752275160
Short name T181
Test name
Test status
Simulation time 98512562 ps
CPU time 0.87 seconds
Started Jun 25 05:25:48 PM PDT 24
Finished Jun 25 05:25:50 PM PDT 24
Peak memory 204980 kb
Host smart-68397994-a582-4a6e-aee7-e9a20c8c821d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752275160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2752275160
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.204819576
Short name T239
Test name
Test status
Simulation time 12438124392 ps
CPU time 8.47 seconds
Started Jun 25 05:25:45 PM PDT 24
Finished Jun 25 05:25:55 PM PDT 24
Peak memory 213556 kb
Host smart-862b7422-c112-4c6e-a2bc-a7084228c29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204819576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.204819576
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3636425424
Short name T240
Test name
Test status
Simulation time 3928867190 ps
CPU time 2.92 seconds
Started Jun 25 05:25:49 PM PDT 24
Finished Jun 25 05:25:55 PM PDT 24
Peak memory 205660 kb
Host smart-38934cdf-8277-4cb8-aaa7-4cbff4f9891e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3636425424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3636425424
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1326850028
Short name T214
Test name
Test status
Simulation time 16626322544 ps
CPU time 23.1 seconds
Started Jun 25 05:25:44 PM PDT 24
Finished Jun 25 05:26:08 PM PDT 24
Peak memory 213456 kb
Host smart-49f0f732-dbed-48aa-a1db-ab915157d388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326850028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1326850028
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.2673072168
Short name T140
Test name
Test status
Simulation time 4033528670 ps
CPU time 3.52 seconds
Started Jun 25 05:25:49 PM PDT 24
Finished Jun 25 05:25:55 PM PDT 24
Peak memory 205204 kb
Host smart-60d59b27-ce6c-46b8-8f18-a3051729839c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673072168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2673072168
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2933264833
Short name T194
Test name
Test status
Simulation time 105666613 ps
CPU time 0.81 seconds
Started Jun 25 05:25:42 PM PDT 24
Finished Jun 25 05:25:44 PM PDT 24
Peak memory 204968 kb
Host smart-326622fc-f27c-4595-8511-32d629eccd67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933264833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2933264833
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3472888959
Short name T267
Test name
Test status
Simulation time 14709687192 ps
CPU time 19.05 seconds
Started Jun 25 05:25:43 PM PDT 24
Finished Jun 25 05:26:03 PM PDT 24
Peak memory 213548 kb
Host smart-91263833-c0ad-4672-8f4e-46290388f2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472888959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3472888959
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3922526296
Short name T211
Test name
Test status
Simulation time 7175284484 ps
CPU time 5.75 seconds
Started Jun 25 05:25:41 PM PDT 24
Finished Jun 25 05:25:48 PM PDT 24
Peak memory 213584 kb
Host smart-5ae0ccf1-7944-4fb8-b8f2-e6f03e767ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922526296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3922526296
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1591725280
Short name T225
Test name
Test status
Simulation time 3115279532 ps
CPU time 9.45 seconds
Started Jun 25 05:25:38 PM PDT 24
Finished Jun 25 05:25:49 PM PDT 24
Peak memory 205412 kb
Host smart-afe796b2-bf24-437b-8b52-dedbf85eccf1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591725280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1591725280
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1169906195
Short name T42
Test name
Test status
Simulation time 5726834844 ps
CPU time 9.39 seconds
Started Jun 25 05:25:43 PM PDT 24
Finished Jun 25 05:25:54 PM PDT 24
Peak memory 205300 kb
Host smart-5599f159-6dd4-4109-b3cb-8e8e29f8cae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169906195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1169906195
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.2702724607
Short name T121
Test name
Test status
Simulation time 4613724324 ps
CPU time 13.31 seconds
Started Jun 25 05:25:37 PM PDT 24
Finished Jun 25 05:25:52 PM PDT 24
Peak memory 205176 kb
Host smart-8129ed02-533d-4170-9ff6-6de0733639bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702724607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.2702724607
Directory /workspace/9.rv_dm_stress_all/latest
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