SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
82.84 | 95.27 | 79.59 | 89.42 | 74.36 | 85.50 | 98.42 | 57.31 |
T292 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1892304774 | Jun 27 06:19:32 PM PDT 24 | Jun 27 06:19:45 PM PDT 24 | 9068243066 ps | ||
T91 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4273815240 | Jun 27 06:19:52 PM PDT 24 | Jun 27 06:20:01 PM PDT 24 | 136683847 ps | ||
T293 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.236929405 | Jun 27 06:19:51 PM PDT 24 | Jun 27 06:19:58 PM PDT 24 | 1635723757 ps | ||
T98 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1422187020 | Jun 27 06:19:40 PM PDT 24 | Jun 27 06:20:16 PM PDT 24 | 2528972094 ps | ||
T99 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.126068673 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:02 PM PDT 24 | 302886997 ps | ||
T59 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.591709484 | Jun 27 06:19:47 PM PDT 24 | Jun 27 06:20:47 PM PDT 24 | 75012400566 ps | ||
T294 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2014693844 | Jun 27 06:19:39 PM PDT 24 | Jun 27 06:19:45 PM PDT 24 | 397666556 ps | ||
T295 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3316465543 | Jun 27 06:19:56 PM PDT 24 | Jun 27 06:20:08 PM PDT 24 | 2406967834 ps | ||
T296 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2141716537 | Jun 27 06:19:51 PM PDT 24 | Jun 27 06:19:58 PM PDT 24 | 2674960100 ps | ||
T297 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2562673654 | Jun 27 06:19:49 PM PDT 24 | Jun 27 06:19:56 PM PDT 24 | 2098037361 ps | ||
T298 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2413489520 | Jun 27 06:19:40 PM PDT 24 | Jun 27 06:19:51 PM PDT 24 | 2121375857 ps | ||
T101 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2794505876 | Jun 27 06:19:51 PM PDT 24 | Jun 27 06:20:21 PM PDT 24 | 7906956046 ps | ||
T60 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3115029878 | Jun 27 06:19:37 PM PDT 24 | Jun 27 06:20:07 PM PDT 24 | 30462021766 ps | ||
T299 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.172990714 | Jun 27 06:19:58 PM PDT 24 | Jun 27 06:20:07 PM PDT 24 | 1848813698 ps | ||
T300 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.449504560 | Jun 27 06:19:48 PM PDT 24 | Jun 27 06:19:55 PM PDT 24 | 1468314969 ps | ||
T100 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4112147608 | Jun 27 06:19:50 PM PDT 24 | Jun 27 06:19:56 PM PDT 24 | 241457705 ps | ||
T301 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1936963890 | Jun 27 06:19:37 PM PDT 24 | Jun 27 06:19:42 PM PDT 24 | 75280005 ps | ||
T105 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4098104547 | Jun 27 06:19:50 PM PDT 24 | Jun 27 06:19:58 PM PDT 24 | 148440545 ps | ||
T302 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2589417679 | Jun 27 06:19:35 PM PDT 24 | Jun 27 06:19:41 PM PDT 24 | 4371311032 ps | ||
T303 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3771402014 | Jun 27 06:19:58 PM PDT 24 | Jun 27 06:20:07 PM PDT 24 | 74748609 ps | ||
T304 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1679024584 | Jun 27 06:19:58 PM PDT 24 | Jun 27 06:20:25 PM PDT 24 | 28964110102 ps | ||
T106 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.158604590 | Jun 27 06:19:52 PM PDT 24 | Jun 27 06:20:00 PM PDT 24 | 177270417 ps | ||
T124 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.962139309 | Jun 27 06:19:51 PM PDT 24 | Jun 27 06:20:16 PM PDT 24 | 5504013519 ps | ||
T115 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1416687834 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:04 PM PDT 24 | 250914219 ps | ||
T125 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2055428632 | Jun 27 06:19:41 PM PDT 24 | Jun 27 06:19:52 PM PDT 24 | 1295320547 ps | ||
T126 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3999048960 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:06 PM PDT 24 | 2688557384 ps | ||
T305 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.182538636 | Jun 27 06:19:41 PM PDT 24 | Jun 27 06:19:47 PM PDT 24 | 155568530 ps | ||
T306 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1481852757 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:21:48 PM PDT 24 | 84932637902 ps | ||
T116 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.91615211 | Jun 27 06:20:14 PM PDT 24 | Jun 27 06:20:22 PM PDT 24 | 601350314 ps | ||
T127 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3427375634 | Jun 27 06:20:02 PM PDT 24 | Jun 27 06:20:19 PM PDT 24 | 1064835461 ps | ||
T102 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1317643192 | Jun 27 06:19:53 PM PDT 24 | Jun 27 06:20:01 PM PDT 24 | 2740080764 ps | ||
T307 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2390665007 | Jun 27 06:19:42 PM PDT 24 | Jun 27 06:19:48 PM PDT 24 | 531144944 ps | ||
T107 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3507833290 | Jun 27 06:19:48 PM PDT 24 | Jun 27 06:20:19 PM PDT 24 | 2320712087 ps | ||
T308 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3431493718 | Jun 27 06:19:47 PM PDT 24 | Jun 27 06:20:10 PM PDT 24 | 21754118803 ps | ||
T309 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2189156815 | Jun 27 06:19:59 PM PDT 24 | Jun 27 06:20:06 PM PDT 24 | 394962932 ps | ||
T310 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3001775326 | Jun 27 06:19:35 PM PDT 24 | Jun 27 06:19:39 PM PDT 24 | 63219530 ps | ||
T149 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4280141827 | Jun 27 06:20:09 PM PDT 24 | Jun 27 06:20:30 PM PDT 24 | 2585876767 ps | ||
T311 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.78869940 | Jun 27 06:20:05 PM PDT 24 | Jun 27 06:20:34 PM PDT 24 | 9172142557 ps | ||
T312 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.728081194 | Jun 27 06:20:05 PM PDT 24 | Jun 27 06:20:15 PM PDT 24 | 278665960 ps | ||
T313 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1666737228 | Jun 27 06:19:56 PM PDT 24 | Jun 27 06:20:03 PM PDT 24 | 456294709 ps | ||
T108 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3205451184 | Jun 27 06:19:49 PM PDT 24 | Jun 27 06:19:57 PM PDT 24 | 191539682 ps | ||
T314 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.74809402 | Jun 27 06:19:32 PM PDT 24 | Jun 27 06:19:44 PM PDT 24 | 3396653535 ps | ||
T315 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1343251890 | Jun 27 06:19:32 PM PDT 24 | Jun 27 06:19:45 PM PDT 24 | 13032593733 ps | ||
T109 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2865082592 | Jun 27 06:20:02 PM PDT 24 | Jun 27 06:20:11 PM PDT 24 | 231486977 ps | ||
T316 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2061073771 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:20 PM PDT 24 | 2105569346 ps | ||
T317 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1616072083 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:03 PM PDT 24 | 182998463 ps | ||
T117 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2212483955 | Jun 27 06:19:50 PM PDT 24 | Jun 27 06:19:59 PM PDT 24 | 1076286114 ps | ||
T318 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3969799833 | Jun 27 06:19:42 PM PDT 24 | Jun 27 06:19:48 PM PDT 24 | 36309202 ps | ||
T319 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.333091859 | Jun 27 06:19:48 PM PDT 24 | Jun 27 06:20:15 PM PDT 24 | 8167147584 ps | ||
T152 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3599116246 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:17 PM PDT 24 | 4114829557 ps | ||
T320 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3612047012 | Jun 27 06:19:55 PM PDT 24 | Jun 27 06:20:06 PM PDT 24 | 247518918 ps | ||
T321 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1473890396 | Jun 27 06:19:34 PM PDT 24 | Jun 27 06:19:40 PM PDT 24 | 223735125 ps | ||
T112 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.889946255 | Jun 27 06:20:13 PM PDT 24 | Jun 27 06:20:19 PM PDT 24 | 202780990 ps | ||
T322 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3458857581 | Jun 27 06:19:40 PM PDT 24 | Jun 27 06:20:06 PM PDT 24 | 6670767013 ps | ||
T155 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.364874843 | Jun 27 06:19:59 PM PDT 24 | Jun 27 06:20:16 PM PDT 24 | 1272056193 ps | ||
T323 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3986370420 | Jun 27 06:19:50 PM PDT 24 | Jun 27 06:19:56 PM PDT 24 | 252260530 ps | ||
T324 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3267007243 | Jun 27 06:19:42 PM PDT 24 | Jun 27 06:20:08 PM PDT 24 | 4871403566 ps | ||
T325 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.4169344934 | Jun 27 06:19:50 PM PDT 24 | Jun 27 06:19:56 PM PDT 24 | 210685905 ps | ||
T156 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1397800484 | Jun 27 06:20:04 PM PDT 24 | Jun 27 06:20:18 PM PDT 24 | 2643585138 ps | ||
T154 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2060963192 | Jun 27 06:19:56 PM PDT 24 | Jun 27 06:20:12 PM PDT 24 | 957864500 ps | ||
T326 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.86789207 | Jun 27 06:19:35 PM PDT 24 | Jun 27 06:19:43 PM PDT 24 | 565803942 ps | ||
T327 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3673892368 | Jun 27 06:19:50 PM PDT 24 | Jun 27 06:21:06 PM PDT 24 | 7402119549 ps | ||
T153 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1504458639 | Jun 27 06:19:55 PM PDT 24 | Jun 27 06:20:19 PM PDT 24 | 3001150678 ps | ||
T328 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1715178746 | Jun 27 06:20:03 PM PDT 24 | Jun 27 06:20:09 PM PDT 24 | 229026064 ps | ||
T329 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.92393348 | Jun 27 06:19:53 PM PDT 24 | Jun 27 06:22:21 PM PDT 24 | 114196892829 ps | ||
T110 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3757935923 | Jun 27 06:20:11 PM PDT 24 | Jun 27 06:20:19 PM PDT 24 | 419307714 ps | ||
T330 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1801204072 | Jun 27 06:19:36 PM PDT 24 | Jun 27 06:19:41 PM PDT 24 | 341315984 ps | ||
T118 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2804974221 | Jun 27 06:20:01 PM PDT 24 | Jun 27 06:20:13 PM PDT 24 | 2092816254 ps | ||
T331 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4287105086 | Jun 27 06:19:44 PM PDT 24 | Jun 27 06:19:50 PM PDT 24 | 214562126 ps | ||
T332 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2204669155 | Jun 27 06:20:05 PM PDT 24 | Jun 27 06:20:10 PM PDT 24 | 293861273 ps | ||
T150 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1609370 | Jun 27 06:19:37 PM PDT 24 | Jun 27 06:20:01 PM PDT 24 | 7799238360 ps | ||
T333 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1120122630 | Jun 27 06:19:42 PM PDT 24 | Jun 27 06:20:07 PM PDT 24 | 27663675704 ps | ||
T119 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3153063574 | Jun 27 06:20:09 PM PDT 24 | Jun 27 06:20:20 PM PDT 24 | 172565095 ps | ||
T120 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2916398397 | Jun 27 06:19:52 PM PDT 24 | Jun 27 06:20:06 PM PDT 24 | 780509973 ps | ||
T61 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3263167309 | Jun 27 06:19:51 PM PDT 24 | Jun 27 06:20:12 PM PDT 24 | 36537034187 ps | ||
T334 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1009604035 | Jun 27 06:20:02 PM PDT 24 | Jun 27 06:20:10 PM PDT 24 | 90790415 ps | ||
T335 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2925610640 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:03 PM PDT 24 | 186213654 ps | ||
T121 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3260830506 | Jun 27 06:20:06 PM PDT 24 | Jun 27 06:20:15 PM PDT 24 | 2285276655 ps | ||
T336 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.982140416 | Jun 27 06:20:12 PM PDT 24 | Jun 27 06:20:41 PM PDT 24 | 16887907266 ps | ||
T337 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.857048189 | Jun 27 06:19:50 PM PDT 24 | Jun 27 06:20:03 PM PDT 24 | 1054732519 ps | ||
T338 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3595352286 | Jun 27 06:19:42 PM PDT 24 | Jun 27 06:20:23 PM PDT 24 | 13246345512 ps | ||
T339 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.608102480 | Jun 27 06:19:47 PM PDT 24 | Jun 27 06:19:54 PM PDT 24 | 1188626421 ps | ||
T340 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.922028989 | Jun 27 06:20:06 PM PDT 24 | Jun 27 06:20:13 PM PDT 24 | 63275230 ps | ||
T341 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1270758395 | Jun 27 06:19:43 PM PDT 24 | Jun 27 06:21:48 PM PDT 24 | 56132836388 ps | ||
T342 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2046566567 | Jun 27 06:20:12 PM PDT 24 | Jun 27 06:20:17 PM PDT 24 | 124941687 ps | ||
T343 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1769603693 | Jun 27 06:19:35 PM PDT 24 | Jun 27 06:19:40 PM PDT 24 | 504777989 ps | ||
T344 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1658920325 | Jun 27 06:19:58 PM PDT 24 | Jun 27 06:20:18 PM PDT 24 | 5556205841 ps | ||
T345 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.795265473 | Jun 27 06:20:02 PM PDT 24 | Jun 27 06:20:08 PM PDT 24 | 202822211 ps | ||
T346 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.926435625 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:04 PM PDT 24 | 680476873 ps | ||
T347 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1358022119 | Jun 27 06:19:53 PM PDT 24 | Jun 27 06:20:06 PM PDT 24 | 2496863541 ps | ||
T348 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.372990125 | Jun 27 06:20:06 PM PDT 24 | Jun 27 06:20:14 PM PDT 24 | 116210853 ps | ||
T349 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.869262315 | Jun 27 06:19:41 PM PDT 24 | Jun 27 06:20:23 PM PDT 24 | 9685395761 ps | ||
T350 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.720800079 | Jun 27 06:20:04 PM PDT 24 | Jun 27 06:20:32 PM PDT 24 | 7940090832 ps | ||
T351 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4222177358 | Jun 27 06:20:05 PM PDT 24 | Jun 27 06:20:15 PM PDT 24 | 3734360598 ps | ||
T113 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3024739084 | Jun 27 06:19:49 PM PDT 24 | Jun 27 06:19:55 PM PDT 24 | 417675902 ps | ||
T352 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3276374079 | Jun 27 06:19:49 PM PDT 24 | Jun 27 06:20:12 PM PDT 24 | 6476684132 ps | ||
T114 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4039664225 | Jun 27 06:19:50 PM PDT 24 | Jun 27 06:19:57 PM PDT 24 | 128419079 ps | ||
T353 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.875818404 | Jun 27 06:19:38 PM PDT 24 | Jun 27 06:19:46 PM PDT 24 | 408423775 ps | ||
T354 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2761601202 | Jun 27 06:19:57 PM PDT 24 | Jun 27 06:20:29 PM PDT 24 | 6217568242 ps | ||
T355 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1060521023 | Jun 27 06:19:33 PM PDT 24 | Jun 27 06:19:39 PM PDT 24 | 224285798 ps | ||
T356 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1089470464 | Jun 27 06:19:44 PM PDT 24 | Jun 27 06:19:50 PM PDT 24 | 1343430594 ps | ||
T357 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2526578380 | Jun 27 06:19:56 PM PDT 24 | Jun 27 06:20:07 PM PDT 24 | 211230935 ps | ||
T358 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1639125447 | Jun 27 06:20:12 PM PDT 24 | Jun 27 06:20:20 PM PDT 24 | 686217841 ps | ||
T359 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.183618212 | Jun 27 06:19:35 PM PDT 24 | Jun 27 06:19:43 PM PDT 24 | 1441434297 ps | ||
T360 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1647186132 | Jun 27 06:19:41 PM PDT 24 | Jun 27 06:19:48 PM PDT 24 | 66939596 ps | ||
T361 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3965768334 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:05 PM PDT 24 | 545904689 ps | ||
T362 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3705646910 | Jun 27 06:19:46 PM PDT 24 | Jun 27 06:21:04 PM PDT 24 | 23585753166 ps | ||
T363 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2355354995 | Jun 27 06:20:12 PM PDT 24 | Jun 27 06:20:19 PM PDT 24 | 4579382564 ps | ||
T364 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2712081298 | Jun 27 06:19:40 PM PDT 24 | Jun 27 06:19:47 PM PDT 24 | 77152746 ps | ||
T365 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.978938020 | Jun 27 06:20:00 PM PDT 24 | Jun 27 06:20:10 PM PDT 24 | 709856594 ps | ||
T366 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1011788236 | Jun 27 06:19:39 PM PDT 24 | Jun 27 06:20:41 PM PDT 24 | 20425304018 ps | ||
T367 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4127092489 | Jun 27 06:19:34 PM PDT 24 | Jun 27 06:19:59 PM PDT 24 | 8225598430 ps | ||
T368 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.865733240 | Jun 27 06:20:04 PM PDT 24 | Jun 27 06:20:09 PM PDT 24 | 54514890 ps | ||
T369 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3913751868 | Jun 27 06:19:36 PM PDT 24 | Jun 27 06:19:43 PM PDT 24 | 717671815 ps | ||
T370 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3156487495 | Jun 27 06:20:05 PM PDT 24 | Jun 27 06:20:11 PM PDT 24 | 355029926 ps | ||
T371 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3560563526 | Jun 27 06:19:33 PM PDT 24 | Jun 27 06:19:38 PM PDT 24 | 867748143 ps | ||
T372 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.171996381 | Jun 27 06:20:04 PM PDT 24 | Jun 27 06:20:10 PM PDT 24 | 623666896 ps | ||
T373 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3425946434 | Jun 27 06:19:35 PM PDT 24 | Jun 27 06:19:43 PM PDT 24 | 712349606 ps | ||
T374 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2126935866 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:04 PM PDT 24 | 1899975558 ps | ||
T375 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2462573918 | Jun 27 06:19:32 PM PDT 24 | Jun 27 06:19:38 PM PDT 24 | 1465156808 ps | ||
T157 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1536412663 | Jun 27 06:19:44 PM PDT 24 | Jun 27 06:20:49 PM PDT 24 | 59912874393 ps | ||
T376 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1206264454 | Jun 27 06:19:34 PM PDT 24 | Jun 27 06:19:38 PM PDT 24 | 319326636 ps | ||
T377 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1058224439 | Jun 27 06:19:50 PM PDT 24 | Jun 27 06:19:57 PM PDT 24 | 117933409 ps | ||
T378 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3399773842 | Jun 27 06:19:53 PM PDT 24 | Jun 27 06:20:02 PM PDT 24 | 421491607 ps | ||
T379 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1128378975 | Jun 27 06:19:52 PM PDT 24 | Jun 27 06:19:59 PM PDT 24 | 214327840 ps | ||
T380 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2552828393 | Jun 27 06:19:46 PM PDT 24 | Jun 27 06:19:54 PM PDT 24 | 3858319936 ps | ||
T381 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2910507594 | Jun 27 06:19:51 PM PDT 24 | Jun 27 06:19:58 PM PDT 24 | 286479696 ps | ||
T111 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2347451353 | Jun 27 06:19:43 PM PDT 24 | Jun 27 06:19:50 PM PDT 24 | 125123252 ps | ||
T382 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.316708087 | Jun 27 06:20:12 PM PDT 24 | Jun 27 06:20:38 PM PDT 24 | 14189703305 ps | ||
T383 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2205167473 | Jun 27 06:19:59 PM PDT 24 | Jun 27 06:20:09 PM PDT 24 | 770441344 ps | ||
T384 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.109185558 | Jun 27 06:19:50 PM PDT 24 | Jun 27 06:19:59 PM PDT 24 | 11604128297 ps | ||
T385 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1617019684 | Jun 27 06:19:51 PM PDT 24 | Jun 27 06:19:57 PM PDT 24 | 154947750 ps | ||
T386 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1470979658 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:08 PM PDT 24 | 430250011 ps | ||
T387 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3174953097 | Jun 27 06:19:59 PM PDT 24 | Jun 27 06:20:07 PM PDT 24 | 110952134 ps | ||
T388 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2184242489 | Jun 27 06:19:51 PM PDT 24 | Jun 27 06:20:00 PM PDT 24 | 174510068 ps | ||
T389 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2971113722 | Jun 27 06:19:58 PM PDT 24 | Jun 27 06:20:04 PM PDT 24 | 171741342 ps | ||
T390 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1683936394 | Jun 27 06:20:02 PM PDT 24 | Jun 27 06:20:14 PM PDT 24 | 9458246148 ps | ||
T391 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.4206149438 | Jun 27 06:20:20 PM PDT 24 | Jun 27 06:20:45 PM PDT 24 | 16354235436 ps | ||
T392 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.888705895 | Jun 27 06:19:51 PM PDT 24 | Jun 27 06:19:56 PM PDT 24 | 27286053 ps | ||
T393 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3208142712 | Jun 27 06:19:53 PM PDT 24 | Jun 27 06:20:05 PM PDT 24 | 1061948900 ps | ||
T394 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1096566793 | Jun 27 06:19:43 PM PDT 24 | Jun 27 06:20:20 PM PDT 24 | 22420380551 ps | ||
T395 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3927576288 | Jun 27 06:20:12 PM PDT 24 | Jun 27 06:20:17 PM PDT 24 | 167989777 ps | ||
T103 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.537773507 | Jun 27 06:19:41 PM PDT 24 | Jun 27 06:19:55 PM PDT 24 | 2705000713 ps | ||
T396 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.875720369 | Jun 27 06:19:34 PM PDT 24 | Jun 27 06:19:42 PM PDT 24 | 479623041 ps | ||
T397 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3473593953 | Jun 27 06:20:05 PM PDT 24 | Jun 27 06:20:10 PM PDT 24 | 284876009 ps | ||
T398 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1256889692 | Jun 27 06:19:50 PM PDT 24 | Jun 27 06:20:02 PM PDT 24 | 5246923004 ps | ||
T399 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3519342876 | Jun 27 06:19:51 PM PDT 24 | Jun 27 06:20:03 PM PDT 24 | 2414723412 ps | ||
T400 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1926640147 | Jun 27 06:20:09 PM PDT 24 | Jun 27 06:20:18 PM PDT 24 | 2431215813 ps | ||
T401 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1433369506 | Jun 27 06:19:38 PM PDT 24 | Jun 27 06:20:06 PM PDT 24 | 13919901613 ps | ||
T402 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2539993097 | Jun 27 06:19:37 PM PDT 24 | Jun 27 06:21:31 PM PDT 24 | 72090940292 ps | ||
T403 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1586626916 | Jun 27 06:19:46 PM PDT 24 | Jun 27 06:20:32 PM PDT 24 | 33287717826 ps | ||
T404 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2019106076 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:08 PM PDT 24 | 4771917265 ps | ||
T405 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1525540802 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:03 PM PDT 24 | 2051193690 ps | ||
T406 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2545412892 | Jun 27 06:19:48 PM PDT 24 | Jun 27 06:19:55 PM PDT 24 | 1903874459 ps | ||
T407 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.473239200 | Jun 27 06:19:52 PM PDT 24 | Jun 27 06:20:09 PM PDT 24 | 4187662678 ps | ||
T408 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3659591170 | Jun 27 06:19:52 PM PDT 24 | Jun 27 06:20:02 PM PDT 24 | 1996754437 ps | ||
T104 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1623193719 | Jun 27 06:19:39 PM PDT 24 | Jun 27 06:19:48 PM PDT 24 | 5113809319 ps | ||
T151 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4227888156 | Jun 27 06:19:48 PM PDT 24 | Jun 27 06:20:14 PM PDT 24 | 6097589254 ps | ||
T409 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2549603357 | Jun 27 06:20:11 PM PDT 24 | Jun 27 06:20:20 PM PDT 24 | 236250699 ps | ||
T410 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3501470205 | Jun 27 06:20:02 PM PDT 24 | Jun 27 06:20:11 PM PDT 24 | 249838820 ps | ||
T411 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.904636397 | Jun 27 06:20:05 PM PDT 24 | Jun 27 06:20:15 PM PDT 24 | 7454590873 ps | ||
T412 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3970041079 | Jun 27 06:19:49 PM PDT 24 | Jun 27 06:20:04 PM PDT 24 | 1167267013 ps | ||
T413 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.557387793 | Jun 27 06:19:52 PM PDT 24 | Jun 27 06:20:13 PM PDT 24 | 1877054177 ps | ||
T414 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1607441180 | Jun 27 06:19:49 PM PDT 24 | Jun 27 06:19:57 PM PDT 24 | 260323303 ps | ||
T415 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3104140117 | Jun 27 06:19:40 PM PDT 24 | Jun 27 06:19:48 PM PDT 24 | 5364016831 ps | ||
T416 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2758015245 | Jun 27 06:19:32 PM PDT 24 | Jun 27 06:19:39 PM PDT 24 | 1247095686 ps | ||
T417 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1543794599 | Jun 27 06:20:00 PM PDT 24 | Jun 27 06:20:12 PM PDT 24 | 2400396179 ps | ||
T418 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1127401208 | Jun 27 06:19:53 PM PDT 24 | Jun 27 06:20:21 PM PDT 24 | 58368344503 ps | ||
T419 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3740699436 | Jun 27 06:20:00 PM PDT 24 | Jun 27 06:20:07 PM PDT 24 | 264673232 ps | ||
T420 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1020485783 | Jun 27 06:19:41 PM PDT 24 | Jun 27 06:20:12 PM PDT 24 | 5824155070 ps | ||
T421 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1261499499 | Jun 27 06:19:35 PM PDT 24 | Jun 27 06:19:59 PM PDT 24 | 21394209169 ps | ||
T422 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1092244654 | Jun 27 06:19:50 PM PDT 24 | Jun 27 06:20:00 PM PDT 24 | 191914758 ps | ||
T423 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4231068356 | Jun 27 06:19:59 PM PDT 24 | Jun 27 06:20:06 PM PDT 24 | 1041643269 ps | ||
T424 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1303950397 | Jun 27 06:19:48 PM PDT 24 | Jun 27 06:19:53 PM PDT 24 | 65998207 ps | ||
T425 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.392007654 | Jun 27 06:19:59 PM PDT 24 | Jun 27 06:20:06 PM PDT 24 | 552580663 ps | ||
T426 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2559869631 | Jun 27 06:19:54 PM PDT 24 | Jun 27 06:20:27 PM PDT 24 | 686741865 ps | ||
T427 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4041521145 | Jun 27 06:20:05 PM PDT 24 | Jun 27 06:20:12 PM PDT 24 | 369668494 ps | ||
T428 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3801528910 | Jun 27 06:19:56 PM PDT 24 | Jun 27 06:20:09 PM PDT 24 | 6604405691 ps | ||
T429 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.45841093 | Jun 27 06:19:40 PM PDT 24 | Jun 27 06:20:12 PM PDT 24 | 1234941932 ps | ||
T430 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3027292464 | Jun 27 06:19:46 PM PDT 24 | Jun 27 06:20:32 PM PDT 24 | 24422791927 ps | ||
T431 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1209526145 | Jun 27 06:19:59 PM PDT 24 | Jun 27 06:20:07 PM PDT 24 | 159119321 ps | ||
T432 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2876523262 | Jun 27 06:20:06 PM PDT 24 | Jun 27 06:20:12 PM PDT 24 | 559976148 ps | ||
T433 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3372246548 | Jun 27 06:19:56 PM PDT 24 | Jun 27 06:20:04 PM PDT 24 | 3106010388 ps | ||
T434 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1259738349 | Jun 27 06:19:59 PM PDT 24 | Jun 27 06:20:38 PM PDT 24 | 43263753628 ps | ||
T435 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2787467465 | Jun 27 06:19:40 PM PDT 24 | Jun 27 06:19:50 PM PDT 24 | 243194990 ps | ||
T436 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.605500360 | Jun 27 06:20:10 PM PDT 24 | Jun 27 06:20:21 PM PDT 24 | 557183157 ps | ||
T437 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2031020361 | Jun 27 06:19:46 PM PDT 24 | Jun 27 06:19:52 PM PDT 24 | 50515471 ps | ||
T438 | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2511280776 | Jun 27 06:19:53 PM PDT 24 | Jun 27 06:20:40 PM PDT 24 | 16822494498 ps | ||
T439 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1706516369 | Jun 27 06:19:59 PM PDT 24 | Jun 27 06:20:12 PM PDT 24 | 2134657266 ps | ||
T440 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3650328959 | Jun 27 06:19:46 PM PDT 24 | Jun 27 06:19:54 PM PDT 24 | 9591961082 ps |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.64108979 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 10091987926 ps |
CPU time | 6.84 seconds |
Started | Jun 27 06:22:55 PM PDT 24 |
Finished | Jun 27 06:23:09 PM PDT 24 |
Peak memory | 205300 kb |
Host | smart-ede92af9-c87f-410e-adfc-935088f12385 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64108979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.64108979 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.154183939 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 1245633123 ps |
CPU time | 4.73 seconds |
Started | Jun 27 06:19:51 PM PDT 24 |
Finished | Jun 27 06:20:01 PM PDT 24 |
Peak memory | 219156 kb |
Host | smart-4126ddd8-1d0c-49c5-b464-4aac8624a1a8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154183939 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.154183939 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3603368552 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 6351626550 ps |
CPU time | 10.2 seconds |
Started | Jun 27 06:22:30 PM PDT 24 |
Finished | Jun 27 06:22:43 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-d17c055a-e4c3-467b-a114-a9d91eb85381 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3603368552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.3603368552 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.591709484 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 75012400566 ps |
CPU time | 55.74 seconds |
Started | Jun 27 06:19:47 PM PDT 24 |
Finished | Jun 27 06:20:47 PM PDT 24 |
Peak memory | 229724 kb |
Host | smart-1cc5e089-c6ca-4742-b599-949ddce30cf0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591709484 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.591709484 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/41.rv_dm_stress_all.1159820526 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 13582551262 ps |
CPU time | 11.09 seconds |
Started | Jun 27 06:22:58 PM PDT 24 |
Finished | Jun 27 06:23:19 PM PDT 24 |
Peak memory | 205140 kb |
Host | smart-ee5cc6f8-5e1a-422d-94bc-8b2380e20839 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159820526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1159820526 |
Directory | /workspace/41.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.156471955 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 54004221390 ps |
CPU time | 36.78 seconds |
Started | Jun 27 06:22:48 PM PDT 24 |
Finished | Jun 27 06:23:29 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-5fe6ab0b-f380-4d28-a344-8d07a95d1791 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=156471955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.156471955 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3134289713 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 4533323166 ps |
CPU time | 18.86 seconds |
Started | Jun 27 06:19:53 PM PDT 24 |
Finished | Jun 27 06:20:17 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-7a193407-0dd4-45be-aeb4-8bfb07a54be7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134289713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3134289713 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.2454540450 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 8852157656 ps |
CPU time | 24.49 seconds |
Started | Jun 27 06:22:54 PM PDT 24 |
Finished | Jun 27 06:23:26 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-921ce222-7141-4778-be3f-dba7f4eed02e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454540450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.2454540450 |
Directory | /workspace/9.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.2545043152 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 102945090 ps |
CPU time | 0.94 seconds |
Started | Jun 27 06:22:33 PM PDT 24 |
Finished | Jun 27 06:22:39 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-2b22ac15-cac0-4f27-9b66-3142ca498ce1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545043152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2545043152 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.4288548414 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 74015973 ps |
CPU time | 0.94 seconds |
Started | Jun 27 06:22:32 PM PDT 24 |
Finished | Jun 27 06:22:38 PM PDT 24 |
Peak memory | 215668 kb |
Host | smart-95e79378-3d0d-4fe0-8c57-14fb489c646e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288548414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.4288548414 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.1686347421 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 1462124423 ps |
CPU time | 2.85 seconds |
Started | Jun 27 06:22:31 PM PDT 24 |
Finished | Jun 27 06:22:38 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-3687a789-3353-446a-84d5-6c76ad517efa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686347421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1686347421 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.328524310 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 256419178 ps |
CPU time | 1.63 seconds |
Started | Jun 27 06:20:06 PM PDT 24 |
Finished | Jun 27 06:20:12 PM PDT 24 |
Peak memory | 213180 kb |
Host | smart-f3776398-697a-4708-87f6-c0309e7b1c53 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328524310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.328524310 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_busy.467529008 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 2888128136 ps |
CPU time | 3.51 seconds |
Started | Jun 27 06:22:34 PM PDT 24 |
Finished | Jun 27 06:22:44 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-5ad2ca0e-bb70-42ac-9fac-c506a92e8142 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=467529008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.467529008 |
Directory | /workspace/1.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.2689806210 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 1520377471 ps |
CPU time | 2.37 seconds |
Started | Jun 27 06:22:34 PM PDT 24 |
Finished | Jun 27 06:22:43 PM PDT 24 |
Peak memory | 237140 kb |
Host | smart-5184c9c9-a4bf-4e3a-910c-1e26094255bf |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689806210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2689806210 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/30.rv_dm_stress_all.1285179566 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 3947123239 ps |
CPU time | 11.28 seconds |
Started | Jun 27 06:22:59 PM PDT 24 |
Finished | Jun 27 06:23:20 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-23f89dde-fb8b-4d78-9c42-e624325c59c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285179566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1285179566 |
Directory | /workspace/30.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.44352993 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 348789394 ps |
CPU time | 1.17 seconds |
Started | Jun 27 06:22:31 PM PDT 24 |
Finished | Jun 27 06:22:37 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-7cb9ae7f-7578-4af5-92ae-6f2a552563cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44352993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.44352993 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all.4233898806 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 8084959697 ps |
CPU time | 10.96 seconds |
Started | Jun 27 06:22:37 PM PDT 24 |
Finished | Jun 27 06:22:55 PM PDT 24 |
Peak memory | 213352 kb |
Host | smart-0e3939b6-676a-4a6f-a373-90b0eab66274 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233898806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.4233898806 |
Directory | /workspace/2.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.3450758309 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 51553043 ps |
CPU time | 0.88 seconds |
Started | Jun 27 06:22:31 PM PDT 24 |
Finished | Jun 27 06:22:35 PM PDT 24 |
Peak memory | 213196 kb |
Host | smart-89d97ad5-ea9b-4412-b0bc-f0242fc02774 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450758309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3450758309 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1000918991 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 211864147 ps |
CPU time | 1.11 seconds |
Started | Jun 27 06:22:30 PM PDT 24 |
Finished | Jun 27 06:22:35 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-76b987af-753f-4856-a245-5761725e4e84 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1000918991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1000918991 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2794505876 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 7906956046 ps |
CPU time | 24.51 seconds |
Started | Jun 27 06:19:51 PM PDT 24 |
Finished | Jun 27 06:20:21 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-59d256c1-1ef8-4fe7-a6c4-8efd8688cb1c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794505876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2794505876 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.995079167 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 8825563092 ps |
CPU time | 13.57 seconds |
Started | Jun 27 06:22:37 PM PDT 24 |
Finished | Jun 27 06:22:58 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-d97dae0a-2b4b-4975-bb6d-b55d2b44fd7d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=995079167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.995079167 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3599116246 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 4114829557 ps |
CPU time | 17.19 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:17 PM PDT 24 |
Peak memory | 213336 kb |
Host | smart-02bb3a88-13de-4f4e-a110-89062a498f43 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599116246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3599116246 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3728947665 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 14240265623 ps |
CPU time | 9.95 seconds |
Started | Jun 27 06:22:48 PM PDT 24 |
Finished | Jun 27 06:23:02 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-ce84bb37-b1d3-473f-97e1-175ebcc70a97 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3728947665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3728947665 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1609370 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 7799238360 ps |
CPU time | 20.55 seconds |
Started | Jun 27 06:19:37 PM PDT 24 |
Finished | Jun 27 06:20:01 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-2b68bfd2-61b7-4314-a0d0-66d91ec5e6cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1609370 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1151910245 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 4632815871 ps |
CPU time | 14.13 seconds |
Started | Jun 27 06:22:33 PM PDT 24 |
Finished | Jun 27 06:22:52 PM PDT 24 |
Peak memory | 213452 kb |
Host | smart-26d90d3f-ce20-41c7-bdeb-ef77d6a86878 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1151910245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1151910245 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2299011818 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 13299488023 ps |
CPU time | 75.08 seconds |
Started | Jun 27 06:19:41 PM PDT 24 |
Finished | Jun 27 06:21:02 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-ee1672ee-c5d0-40b0-826d-81430ac8328c |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299011818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.2299011818 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1447761189 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 289780599 ps |
CPU time | 0.81 seconds |
Started | Jun 27 06:19:43 PM PDT 24 |
Finished | Jun 27 06:19:49 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-ce047b08-de9e-4e8a-a589-c3fa34ff0bb1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447761189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1 447761189 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.537773507 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 2705000713 ps |
CPU time | 8.7 seconds |
Started | Jun 27 06:19:41 PM PDT 24 |
Finished | Jun 27 06:19:55 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-5ca4bf07-81ff-4261-9a8f-467fc6baecae |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537773507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr _hw_reset.537773507 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2212483955 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 1076286114 ps |
CPU time | 4.51 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:19:59 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-f1b9b8eb-a05b-4b2a-8598-ccf19bf89e96 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212483955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.2212483955 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3689605386 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 331821558 ps |
CPU time | 1.46 seconds |
Started | Jun 27 06:22:28 PM PDT 24 |
Finished | Jun 27 06:22:31 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-66d8a209-90c5-4240-981f-cfa9aab54c69 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689605386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3689605386 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1261499499 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 21394209169 ps |
CPU time | 20.8 seconds |
Started | Jun 27 06:19:35 PM PDT 24 |
Finished | Jun 27 06:19:59 PM PDT 24 |
Peak memory | 220740 kb |
Host | smart-3664fb8f-35d4-47c4-ac9b-a139daa47402 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261499499 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1261499499 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2761601202 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 6217568242 ps |
CPU time | 26.62 seconds |
Started | Jun 27 06:19:57 PM PDT 24 |
Finished | Jun 27 06:20:29 PM PDT 24 |
Peak memory | 213372 kb |
Host | smart-f355d563-32b4-4415-8741-01f3e945e728 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761601202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2 761601202 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2172697095 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 2414604619 ps |
CPU time | 4.79 seconds |
Started | Jun 27 06:22:37 PM PDT 24 |
Finished | Jun 27 06:22:49 PM PDT 24 |
Peak memory | 213484 kb |
Host | smart-e4414db2-0306-4283-8016-e8775f6d586d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172697095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2172697095 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.2083433465 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 5702452238 ps |
CPU time | 4.67 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:49 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-f49f0b4a-0719-40ff-8ef6-fd51db2aa135 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083433465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2083433465 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/18.rv_dm_stress_all.350562874 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 4359632759 ps |
CPU time | 11.16 seconds |
Started | Jun 27 06:23:06 PM PDT 24 |
Finished | Jun 27 06:23:26 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-cfeb0df1-5900-49c6-9867-74295e34e58f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350562874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.350562874 |
Directory | /workspace/18.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1422187020 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 2528972094 ps |
CPU time | 30.69 seconds |
Started | Jun 27 06:19:40 PM PDT 24 |
Finished | Jun 27 06:20:16 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-d389faf7-e032-4f45-b2e5-9629518f3d8b |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422187020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.1422187020 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3595352286 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 13246345512 ps |
CPU time | 35.4 seconds |
Started | Jun 27 06:19:42 PM PDT 24 |
Finished | Jun 27 06:20:23 PM PDT 24 |
Peak memory | 213336 kb |
Host | smart-8d09e2c9-4b63-4291-a1fc-d4760c0742f9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595352286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3595352286 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1106348950 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 90253850 ps |
CPU time | 1.54 seconds |
Started | Jun 27 06:19:42 PM PDT 24 |
Finished | Jun 27 06:19:50 PM PDT 24 |
Peak memory | 213224 kb |
Host | smart-10200da6-0844-4505-8568-c05d285f2ccd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106348950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1106348950 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.74809402 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 3396653535 ps |
CPU time | 7.69 seconds |
Started | Jun 27 06:19:32 PM PDT 24 |
Finished | Jun 27 06:19:44 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-a3725232-5c19-4a0b-ab25-e7fdd0e11a4c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74809402 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.74809402 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2712081298 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 77152746 ps |
CPU time | 1.44 seconds |
Started | Jun 27 06:19:40 PM PDT 24 |
Finished | Jun 27 06:19:47 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-2e3d16f4-8219-4018-9603-e8344d657197 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712081298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2712081298 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3485190159 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 55426793538 ps |
CPU time | 115.43 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:21:50 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-cdea5ea0-1542-46b7-aa15-399a5e0809ed |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485190159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.3485190159 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3458857581 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 6670767013 ps |
CPU time | 20.42 seconds |
Started | Jun 27 06:19:40 PM PDT 24 |
Finished | Jun 27 06:20:06 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-b20813f1-e89b-43fb-8d1a-244b9225cc2a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458857581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.3458857581 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3104140117 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 5364016831 ps |
CPU time | 2.17 seconds |
Started | Jun 27 06:19:40 PM PDT 24 |
Finished | Jun 27 06:19:48 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-a72a3fde-0fae-4aef-84b5-ef92736a46a8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104140117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.3104140117 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2413489520 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 2121375857 ps |
CPU time | 5.91 seconds |
Started | Jun 27 06:19:40 PM PDT 24 |
Finished | Jun 27 06:19:51 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-cc7a06a9-9f72-4ce3-af38-4792e322cdeb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413489520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2 413489520 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1206264454 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 319326636 ps |
CPU time | 0.89 seconds |
Started | Jun 27 06:19:34 PM PDT 24 |
Finished | Jun 27 06:19:38 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-d892e277-a6d1-4792-bbfe-ae10fd780d6d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206264454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.1206264454 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3650328959 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 9591961082 ps |
CPU time | 3.86 seconds |
Started | Jun 27 06:19:46 PM PDT 24 |
Finished | Jun 27 06:19:54 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-33f611cf-d95f-4137-8861-73f55691f10d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650328959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.3650328959 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2758015245 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 1247095686 ps |
CPU time | 3.02 seconds |
Started | Jun 27 06:19:32 PM PDT 24 |
Finished | Jun 27 06:19:39 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-d63cd402-51e8-4cad-986c-e9c3b0eac7cc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758015245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.2758015245 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3969799833 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 36309202 ps |
CPU time | 0.72 seconds |
Started | Jun 27 06:19:42 PM PDT 24 |
Finished | Jun 27 06:19:48 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-ed7700fc-4d06-4ec6-9862-2793d49906b8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969799833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.3969799833 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1936963890 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 75280005 ps |
CPU time | 0.7 seconds |
Started | Jun 27 06:19:37 PM PDT 24 |
Finished | Jun 27 06:19:42 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-6c4fe198-bd7f-42fc-9bf6-1eb4adbaa7d2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936963890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1936963890 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.875818404 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 408423775 ps |
CPU time | 3.49 seconds |
Started | Jun 27 06:19:38 PM PDT 24 |
Finished | Jun 27 06:19:46 PM PDT 24 |
Peak memory | 205088 kb |
Host | smart-46ff0e1f-581d-482f-a308-d0253fe7f626 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875818404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c sr_outstanding.875818404 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3913751868 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 717671815 ps |
CPU time | 3.36 seconds |
Started | Jun 27 06:19:36 PM PDT 24 |
Finished | Jun 27 06:19:43 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-b84ef12a-e0b5-4cf0-a0bc-cbda6ddc8898 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913751868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3913751868 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1020485783 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 5824155070 ps |
CPU time | 25.65 seconds |
Started | Jun 27 06:19:41 PM PDT 24 |
Finished | Jun 27 06:20:12 PM PDT 24 |
Peak memory | 213364 kb |
Host | smart-f3cc59a8-13a4-4ce8-83f2-f43d0a72bf77 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020485783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1020485783 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.869262315 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 9685395761 ps |
CPU time | 36.52 seconds |
Started | Jun 27 06:19:41 PM PDT 24 |
Finished | Jun 27 06:20:23 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-ce7d942a-345d-4817-9128-0949c5824a24 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869262315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.869262315 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1473890396 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 223735125 ps |
CPU time | 1.75 seconds |
Started | Jun 27 06:19:34 PM PDT 24 |
Finished | Jun 27 06:19:40 PM PDT 24 |
Peak memory | 213128 kb |
Host | smart-f6e42f42-bc5b-4387-8833-d0fba1add9b4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473890396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1473890396 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2055428632 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 1295320547 ps |
CPU time | 5.51 seconds |
Started | Jun 27 06:19:41 PM PDT 24 |
Finished | Jun 27 06:19:52 PM PDT 24 |
Peak memory | 218548 kb |
Host | smart-5c44ead0-b120-4129-81a2-a3514a80a843 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055428632 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2055428632 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2634123514 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 240918166 ps |
CPU time | 2.52 seconds |
Started | Jun 27 06:19:37 PM PDT 24 |
Finished | Jun 27 06:19:42 PM PDT 24 |
Peak memory | 213276 kb |
Host | smart-821a4642-6582-44b7-bf55-b99ae62b7ea6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634123514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2634123514 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2539993097 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 72090940292 ps |
CPU time | 111.35 seconds |
Started | Jun 27 06:19:37 PM PDT 24 |
Finished | Jun 27 06:21:31 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-ec618aea-f9d1-444e-b245-99956676ecc2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539993097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.2539993097 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1433369506 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 13919901613 ps |
CPU time | 24.29 seconds |
Started | Jun 27 06:19:38 PM PDT 24 |
Finished | Jun 27 06:20:06 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-e11abc7e-3ae7-4e50-92ec-a1d274f91c55 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433369506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.1433369506 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2589417679 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 4371311032 ps |
CPU time | 2.5 seconds |
Started | Jun 27 06:19:35 PM PDT 24 |
Finished | Jun 27 06:19:41 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-89130a4d-5f22-4556-93fc-6b50803a2adf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589417679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2 589417679 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2462573918 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 1465156808 ps |
CPU time | 2.06 seconds |
Started | Jun 27 06:19:32 PM PDT 24 |
Finished | Jun 27 06:19:38 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-ed5ea0dd-fd74-4aae-acff-ba5a1943bf7a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462573918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.2462573918 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1120122630 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 27663675704 ps |
CPU time | 19.28 seconds |
Started | Jun 27 06:19:42 PM PDT 24 |
Finished | Jun 27 06:20:07 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-37e76ff2-bc80-4cb6-8de3-7a42215b2cde |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120122630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.1120122630 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3560563526 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 867748143 ps |
CPU time | 0.91 seconds |
Started | Jun 27 06:19:33 PM PDT 24 |
Finished | Jun 27 06:19:38 PM PDT 24 |
Peak memory | 204644 kb |
Host | smart-c765f9ed-12dd-454d-ab65-144c9ea60d39 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560563526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.3560563526 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1769603693 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 504777989 ps |
CPU time | 1.52 seconds |
Started | Jun 27 06:19:35 PM PDT 24 |
Finished | Jun 27 06:19:40 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-bbbc3aba-fab4-49ef-a5de-89e080ade82b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769603693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1 769603693 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1647186132 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 66939596 ps |
CPU time | 0.79 seconds |
Started | Jun 27 06:19:41 PM PDT 24 |
Finished | Jun 27 06:19:48 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-990620e8-343b-4b46-bb97-31f7bc3b3de3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647186132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.1647186132 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3001775326 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 63219530 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:19:35 PM PDT 24 |
Finished | Jun 27 06:19:39 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-df99fd6b-5d1e-423c-b6a5-e11f209836cf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001775326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3001775326 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3425946434 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 712349606 ps |
CPU time | 4.25 seconds |
Started | Jun 27 06:19:35 PM PDT 24 |
Finished | Jun 27 06:19:43 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-324f20c4-92e9-485c-a72b-0bf864434222 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425946434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.3425946434 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.86789207 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 565803942 ps |
CPU time | 3.77 seconds |
Started | Jun 27 06:19:35 PM PDT 24 |
Finished | Jun 27 06:19:43 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-3f720c04-48c8-4e40-a85d-eebb3a426048 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86789207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.86789207 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3612047012 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 247518918 ps |
CPU time | 4.52 seconds |
Started | Jun 27 06:19:55 PM PDT 24 |
Finished | Jun 27 06:20:06 PM PDT 24 |
Peak memory | 221512 kb |
Host | smart-833fc9c0-6145-4927-a9c1-618e6b501d92 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612047012 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3612047012 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.4112147608 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 241457705 ps |
CPU time | 2.3 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:19:56 PM PDT 24 |
Peak memory | 213184 kb |
Host | smart-6048ca3e-b9a4-42af-84c7-6cb9ddb2bb08 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112147608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.4112147608 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1683936394 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 9458246148 ps |
CPU time | 6.93 seconds |
Started | Jun 27 06:20:02 PM PDT 24 |
Finished | Jun 27 06:20:14 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-d6d322ae-844a-4e74-8911-0a615fa96fd6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683936394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.1683936394 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1525540802 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 2051193690 ps |
CPU time | 2.88 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:03 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-3d442f24-854b-403f-8838-be38ddb67fdc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525540802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 1525540802 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.795265473 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 202822211 ps |
CPU time | 1.21 seconds |
Started | Jun 27 06:20:02 PM PDT 24 |
Finished | Jun 27 06:20:08 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-7110619b-418e-4867-a62e-966621619acb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795265473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.795265473 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2207533959 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 415615351 ps |
CPU time | 3.05 seconds |
Started | Jun 27 06:19:58 PM PDT 24 |
Finished | Jun 27 06:20:06 PM PDT 24 |
Peak memory | 213324 kb |
Host | smart-48021937-f089-4bb0-97c3-53ef075e8df2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207533959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2207533959 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.830463858 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 2342611476 ps |
CPU time | 4.88 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:19:59 PM PDT 24 |
Peak memory | 218828 kb |
Host | smart-fa5bca40-ba70-4e4a-9ea8-99b048d36e1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830463858 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.830463858 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4039664225 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 128419079 ps |
CPU time | 1.53 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:19:57 PM PDT 24 |
Peak memory | 213168 kb |
Host | smart-f77d850c-f175-4dec-9af2-218ff0c5a61e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039664225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4039664225 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1078223588 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 2321319391 ps |
CPU time | 6.85 seconds |
Started | Jun 27 06:20:03 PM PDT 24 |
Finished | Jun 27 06:20:14 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-93c8dd9d-9461-4f17-b9f2-a495d7188d5e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078223588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .rv_dm_jtag_dmi_csr_bit_bash.1078223588 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.109185558 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 11604128297 ps |
CPU time | 3.79 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:19:59 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-3f2b25b6-c241-4e59-9822-165385ed4534 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109185558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.109185558 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2278554904 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 137564960 ps |
CPU time | 0.76 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:19:55 PM PDT 24 |
Peak memory | 204732 kb |
Host | smart-240251f1-64f1-48b1-bd62-6d0d0dc5dd8b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278554904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 2278554904 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3501470205 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 249838820 ps |
CPU time | 3.79 seconds |
Started | Jun 27 06:20:02 PM PDT 24 |
Finished | Jun 27 06:20:11 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-a9676f0d-0013-486b-b127-dccb6fcd27d3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501470205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.3501470205 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1256889692 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 5246923004 ps |
CPU time | 6.71 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:20:02 PM PDT 24 |
Peak memory | 221604 kb |
Host | smart-aca0e07d-9f62-4b92-887f-1bba2fc66173 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256889692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1256889692 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.962139309 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 5504013519 ps |
CPU time | 20.23 seconds |
Started | Jun 27 06:19:51 PM PDT 24 |
Finished | Jun 27 06:20:16 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-ebfee5a9-8423-46da-8a5f-b442b022984d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962139309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.962139309 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2126935866 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 1899975558 ps |
CPU time | 4.07 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:04 PM PDT 24 |
Peak memory | 219196 kb |
Host | smart-3a212b74-17b7-4bf0-ad70-20d789b8cd71 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126935866 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2126935866 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1616072083 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 182998463 ps |
CPU time | 2.57 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:03 PM PDT 24 |
Peak memory | 213132 kb |
Host | smart-2389a64b-51dd-46cc-a794-c06bead0d5a8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616072083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1616072083 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1658920325 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 5556205841 ps |
CPU time | 15.46 seconds |
Started | Jun 27 06:19:58 PM PDT 24 |
Finished | Jun 27 06:20:18 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-206fcff1-0ffe-477f-8c1a-5573569d1887 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658920325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .rv_dm_jtag_dmi_csr_bit_bash.1658920325 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3208142712 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 1061948900 ps |
CPU time | 1.49 seconds |
Started | Jun 27 06:19:53 PM PDT 24 |
Finished | Jun 27 06:20:05 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-2e2c89cf-5d6a-4c8f-802d-6c88fce79c89 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208142712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 3208142712 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1715178746 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 229026064 ps |
CPU time | 1.03 seconds |
Started | Jun 27 06:20:03 PM PDT 24 |
Finished | Jun 27 06:20:09 PM PDT 24 |
Peak memory | 204700 kb |
Host | smart-5dbfcc33-f4e8-46cf-b868-8bccfc9fb92c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715178746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 1715178746 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2865082592 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 231486977 ps |
CPU time | 3.65 seconds |
Started | Jun 27 06:20:02 PM PDT 24 |
Finished | Jun 27 06:20:11 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-d6f57fb6-d19c-4078-b724-a5c185992f12 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865082592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.2865082592 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1009604035 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 90790415 ps |
CPU time | 2.8 seconds |
Started | Jun 27 06:20:02 PM PDT 24 |
Finished | Jun 27 06:20:10 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-2f9560c0-ef04-45a4-a09a-032f458aaff0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009604035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1009604035 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2061073771 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 2105569346 ps |
CPU time | 19.41 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:20 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-f52bf53c-ee2a-4aa4-b7f8-a94732a44bd2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061073771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2 061073771 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1926640147 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 2431215813 ps |
CPU time | 4.86 seconds |
Started | Jun 27 06:20:09 PM PDT 24 |
Finished | Jun 27 06:20:18 PM PDT 24 |
Peak memory | 219840 kb |
Host | smart-d54c9332-60d9-4746-9c34-96e705fb7d02 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926640147 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1926640147 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3174953097 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 110952134 ps |
CPU time | 2.46 seconds |
Started | Jun 27 06:19:59 PM PDT 24 |
Finished | Jun 27 06:20:07 PM PDT 24 |
Peak memory | 213212 kb |
Host | smart-3bae571b-fea2-4508-8299-d80e3fd47012 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174953097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3174953097 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1481852757 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 84932637902 ps |
CPU time | 109.41 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:21:48 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-335e26df-ad6c-4f32-af64-0d9647c2d2d2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481852757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.1481852757 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3316465543 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 2406967834 ps |
CPU time | 6.97 seconds |
Started | Jun 27 06:19:56 PM PDT 24 |
Finished | Jun 27 06:20:08 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-37f2a4d8-f192-437d-b485-089a07f62f9c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316465543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 3316465543 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3986370420 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 252260530 ps |
CPU time | 1.34 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:19:56 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-6a49cdb3-f1e0-48f1-a9af-5cc6916af6a8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986370420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 3986370420 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2906613203 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 1277471962 ps |
CPU time | 8.02 seconds |
Started | Jun 27 06:20:00 PM PDT 24 |
Finished | Jun 27 06:20:13 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-515e4bb4-3a6a-4d97-bb83-0e03fef7d11b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906613203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.2906613203 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2526578380 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 211230935 ps |
CPU time | 5.22 seconds |
Started | Jun 27 06:19:56 PM PDT 24 |
Finished | Jun 27 06:20:07 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-c12eecf6-aba5-4a93-a041-e313ba2d08a5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526578380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2526578380 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2060963192 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 957864500 ps |
CPU time | 10.72 seconds |
Started | Jun 27 06:19:56 PM PDT 24 |
Finished | Jun 27 06:20:12 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-598661de-0f1a-4d9c-952c-5cb42bef9278 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060963192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2 060963192 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4222177358 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 3734360598 ps |
CPU time | 5.59 seconds |
Started | Jun 27 06:20:05 PM PDT 24 |
Finished | Jun 27 06:20:15 PM PDT 24 |
Peak memory | 220752 kb |
Host | smart-95b613ae-9cfc-4480-8b74-538395a4a956 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222177358 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4222177358 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1259738349 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 43263753628 ps |
CPU time | 34.2 seconds |
Started | Jun 27 06:19:59 PM PDT 24 |
Finished | Jun 27 06:20:38 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-1ccaaa5f-412c-4058-b669-39b4de4d5518 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259738349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .rv_dm_jtag_dmi_csr_bit_bash.1259738349 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3372246548 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 3106010388 ps |
CPU time | 2.42 seconds |
Started | Jun 27 06:19:56 PM PDT 24 |
Finished | Jun 27 06:20:04 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-7ae74c22-dcfa-4d37-a28f-4ab402220942 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372246548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 3372246548 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3473593953 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 284876009 ps |
CPU time | 0.82 seconds |
Started | Jun 27 06:20:05 PM PDT 24 |
Finished | Jun 27 06:20:10 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-d84509b6-28e8-4e23-b15c-44f4b59e5929 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473593953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 3473593953 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3260830506 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 2285276655 ps |
CPU time | 4.97 seconds |
Started | Jun 27 06:20:06 PM PDT 24 |
Finished | Jun 27 06:20:15 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-d0464f50-e47b-47fd-89c5-de5303fcd58b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260830506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.3260830506 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.922028989 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 63275230 ps |
CPU time | 2.58 seconds |
Started | Jun 27 06:20:06 PM PDT 24 |
Finished | Jun 27 06:20:13 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-130034fb-1d6f-4cfa-8d97-302f92010b1e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922028989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.922028989 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3041164095 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 2398728290 ps |
CPU time | 13.72 seconds |
Started | Jun 27 06:20:22 PM PDT 24 |
Finished | Jun 27 06:20:38 PM PDT 24 |
Peak memory | 213352 kb |
Host | smart-483b6108-dabc-46b5-a880-6020c7581c42 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041164095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3 041164095 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1639125447 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 686217841 ps |
CPU time | 3.47 seconds |
Started | Jun 27 06:20:12 PM PDT 24 |
Finished | Jun 27 06:20:20 PM PDT 24 |
Peak memory | 217628 kb |
Host | smart-3784d37c-678b-497a-84ae-8068af49f776 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639125447 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1639125447 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4041521145 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 369668494 ps |
CPU time | 2.64 seconds |
Started | Jun 27 06:20:05 PM PDT 24 |
Finished | Jun 27 06:20:12 PM PDT 24 |
Peak memory | 213128 kb |
Host | smart-673240d9-46f9-4cd8-9abd-a54192482620 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041521145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.4041521145 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3020251374 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 12431293889 ps |
CPU time | 6.51 seconds |
Started | Jun 27 06:20:00 PM PDT 24 |
Finished | Jun 27 06:20:12 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-c26e1482-441a-4f6b-aa2b-32acae9280d5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020251374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.3020251374 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.904636397 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 7454590873 ps |
CPU time | 6.03 seconds |
Started | Jun 27 06:20:05 PM PDT 24 |
Finished | Jun 27 06:20:15 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-9cf62880-7869-40ab-99eb-a317982c0a8e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904636397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.904636397 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1666737228 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 456294709 ps |
CPU time | 1.14 seconds |
Started | Jun 27 06:19:56 PM PDT 24 |
Finished | Jun 27 06:20:03 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-c156b183-5b16-4a15-aa2d-683a8404a4c7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666737228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 1666737228 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2804974221 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 2092816254 ps |
CPU time | 7.72 seconds |
Started | Jun 27 06:20:01 PM PDT 24 |
Finished | Jun 27 06:20:13 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-fc38279a-ad48-4df5-b464-4527d11513c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804974221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.2804974221 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.605500360 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 557183157 ps |
CPU time | 6.28 seconds |
Started | Jun 27 06:20:10 PM PDT 24 |
Finished | Jun 27 06:20:21 PM PDT 24 |
Peak memory | 213288 kb |
Host | smart-d4676dbc-6056-4b42-bf89-fbd35e05e1ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605500360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.605500360 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3427375634 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 1064835461 ps |
CPU time | 11.5 seconds |
Started | Jun 27 06:20:02 PM PDT 24 |
Finished | Jun 27 06:20:19 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-e6d5778d-c72d-4d42-bd93-0b1ea2e0dec4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427375634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3 427375634 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1209526145 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 159119321 ps |
CPU time | 2.41 seconds |
Started | Jun 27 06:19:59 PM PDT 24 |
Finished | Jun 27 06:20:07 PM PDT 24 |
Peak memory | 217672 kb |
Host | smart-3d5afe7c-9c56-43f2-b85a-b5a85ca50a7c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209526145 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1209526145 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3927576288 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 167989777 ps |
CPU time | 1.64 seconds |
Started | Jun 27 06:20:12 PM PDT 24 |
Finished | Jun 27 06:20:17 PM PDT 24 |
Peak memory | 213228 kb |
Host | smart-ae3f4e77-78d9-4e2a-8dae-cf3f5b677783 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927576288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3927576288 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.720800079 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 7940090832 ps |
CPU time | 22.98 seconds |
Started | Jun 27 06:20:04 PM PDT 24 |
Finished | Jun 27 06:20:32 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-2e3c4d17-b5f7-488e-b3e9-3686e67bbae1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720800079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. rv_dm_jtag_dmi_csr_bit_bash.720800079 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.78869940 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 9172142557 ps |
CPU time | 24.15 seconds |
Started | Jun 27 06:20:05 PM PDT 24 |
Finished | Jun 27 06:20:34 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-8f9ee6b9-ef2e-41c8-97dd-df10fcaeb8ab |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78869940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.78869940 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.171996381 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 623666896 ps |
CPU time | 1.24 seconds |
Started | Jun 27 06:20:04 PM PDT 24 |
Finished | Jun 27 06:20:10 PM PDT 24 |
Peak memory | 204640 kb |
Host | smart-2c1d2a86-f2f4-449c-b0a6-c3898c8b4c9f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171996381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.171996381 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3757935923 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 419307714 ps |
CPU time | 4.02 seconds |
Started | Jun 27 06:20:11 PM PDT 24 |
Finished | Jun 27 06:20:19 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-1416e4b1-8369-470d-86de-e7fcde04835d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757935923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.3757935923 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.372990125 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 116210853 ps |
CPU time | 3.3 seconds |
Started | Jun 27 06:20:06 PM PDT 24 |
Finished | Jun 27 06:20:14 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-743baf4b-6c2a-4396-8881-a3ec70d8baa2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372990125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.372990125 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1397800484 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 2643585138 ps |
CPU time | 10.33 seconds |
Started | Jun 27 06:20:04 PM PDT 24 |
Finished | Jun 27 06:20:18 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-4e95b96a-566d-4354-b103-b06ef1b02e96 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397800484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1 397800484 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.308425752 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 2336654419 ps |
CPU time | 7.36 seconds |
Started | Jun 27 06:20:00 PM PDT 24 |
Finished | Jun 27 06:20:12 PM PDT 24 |
Peak memory | 220036 kb |
Host | smart-5c21e736-24a4-4c61-bd1f-dd0adb964569 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308425752 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.308425752 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2046566567 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 124941687 ps |
CPU time | 1.45 seconds |
Started | Jun 27 06:20:12 PM PDT 24 |
Finished | Jun 27 06:20:17 PM PDT 24 |
Peak memory | 213232 kb |
Host | smart-442b50d1-c1bc-45bd-ba5e-edcb56770d12 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046566567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2046566567 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.982140416 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 16887907266 ps |
CPU time | 26 seconds |
Started | Jun 27 06:20:12 PM PDT 24 |
Finished | Jun 27 06:20:41 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-b021087a-1ac7-461e-a4fd-14a61069d0d8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982140416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. rv_dm_jtag_dmi_csr_bit_bash.982140416 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3801528910 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 6604405691 ps |
CPU time | 8.2 seconds |
Started | Jun 27 06:19:56 PM PDT 24 |
Finished | Jun 27 06:20:09 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-2dd1a834-2861-42ef-ab8f-f85952887d89 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801528910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 3801528910 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2189156815 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 394962932 ps |
CPU time | 1.68 seconds |
Started | Jun 27 06:19:59 PM PDT 24 |
Finished | Jun 27 06:20:06 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-fb80112d-6658-4a90-af9d-fbfcfb6db7ac |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189156815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 2189156815 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3153063574 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 172565095 ps |
CPU time | 6.69 seconds |
Started | Jun 27 06:20:09 PM PDT 24 |
Finished | Jun 27 06:20:20 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-1e16722f-ff5f-40e6-9f76-1a1bc5cb3688 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153063574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.3153063574 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2549603357 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 236250699 ps |
CPU time | 4.54 seconds |
Started | Jun 27 06:20:11 PM PDT 24 |
Finished | Jun 27 06:20:20 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-6eaf1bc7-2951-444d-b62b-63f45fe064bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549603357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2549603357 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2496043108 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 1834214266 ps |
CPU time | 19.96 seconds |
Started | Jun 27 06:20:13 PM PDT 24 |
Finished | Jun 27 06:20:37 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-b7c663cc-aa13-4268-910b-8091dd3fa85c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496043108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2 496043108 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2876523262 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 559976148 ps |
CPU time | 2.33 seconds |
Started | Jun 27 06:20:06 PM PDT 24 |
Finished | Jun 27 06:20:12 PM PDT 24 |
Peak memory | 213388 kb |
Host | smart-7a18c4eb-a553-4dda-b4d6-73c9b880a4e9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876523262 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2876523262 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.865733240 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 54514890 ps |
CPU time | 1.51 seconds |
Started | Jun 27 06:20:04 PM PDT 24 |
Finished | Jun 27 06:20:09 PM PDT 24 |
Peak memory | 213156 kb |
Host | smart-e24e1123-70ae-4b17-8d54-2610e483562c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865733240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.865733240 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.4206149438 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 16354235436 ps |
CPU time | 23.91 seconds |
Started | Jun 27 06:20:20 PM PDT 24 |
Finished | Jun 27 06:20:45 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-99ddb05a-b06c-4e08-8b9c-03862768e223 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206149438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.4206149438 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.172990714 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 1848813698 ps |
CPU time | 3.47 seconds |
Started | Jun 27 06:19:58 PM PDT 24 |
Finished | Jun 27 06:20:07 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-2998e6ad-d3c9-4a0a-a059-c5f7d847507f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172990714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.172990714 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2204669155 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 293861273 ps |
CPU time | 0.85 seconds |
Started | Jun 27 06:20:05 PM PDT 24 |
Finished | Jun 27 06:20:10 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-cd928457-14ab-4d75-9d44-7a5cc691ace7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204669155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 2204669155 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1543794599 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 2400396179 ps |
CPU time | 7.34 seconds |
Started | Jun 27 06:20:00 PM PDT 24 |
Finished | Jun 27 06:20:12 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-5ba20e4f-72c7-443a-8bcb-bef836d8a02d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543794599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.1543794599 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3740699436 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 264673232 ps |
CPU time | 2.48 seconds |
Started | Jun 27 06:20:00 PM PDT 24 |
Finished | Jun 27 06:20:07 PM PDT 24 |
Peak memory | 213328 kb |
Host | smart-ea4913ce-efcb-4298-bad6-e5efe6c3a3c7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740699436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3740699436 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4280141827 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 2585876767 ps |
CPU time | 17.25 seconds |
Started | Jun 27 06:20:09 PM PDT 24 |
Finished | Jun 27 06:20:30 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-6e3551c2-0357-427e-b3cf-57f101127444 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280141827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4 280141827 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2611592033 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 1644206432 ps |
CPU time | 4.88 seconds |
Started | Jun 27 06:20:13 PM PDT 24 |
Finished | Jun 27 06:20:22 PM PDT 24 |
Peak memory | 221524 kb |
Host | smart-a852ac6f-4339-48a6-881d-ce0a29712212 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611592033 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2611592033 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.889946255 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 202780990 ps |
CPU time | 2.22 seconds |
Started | Jun 27 06:20:13 PM PDT 24 |
Finished | Jun 27 06:20:19 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-9fca0f44-4873-465b-acca-7f9887e79782 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889946255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.889946255 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2355354995 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 4579382564 ps |
CPU time | 3.06 seconds |
Started | Jun 27 06:20:12 PM PDT 24 |
Finished | Jun 27 06:20:19 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-584965fe-1872-4df9-901c-b6f70b3f4782 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355354995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .rv_dm_jtag_dmi_csr_bit_bash.2355354995 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.316708087 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 14189703305 ps |
CPU time | 22.14 seconds |
Started | Jun 27 06:20:12 PM PDT 24 |
Finished | Jun 27 06:20:38 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-873d9162-19d8-4927-905c-bd9ee6d4dd8f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316708087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.316708087 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3156487495 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 355029926 ps |
CPU time | 1.75 seconds |
Started | Jun 27 06:20:05 PM PDT 24 |
Finished | Jun 27 06:20:11 PM PDT 24 |
Peak memory | 204672 kb |
Host | smart-37c046c1-4332-441b-84f6-e284622c4ab5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156487495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 3156487495 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.91615211 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 601350314 ps |
CPU time | 4.31 seconds |
Started | Jun 27 06:20:14 PM PDT 24 |
Finished | Jun 27 06:20:22 PM PDT 24 |
Peak memory | 205108 kb |
Host | smart-f5cae669-4876-4bfa-9874-5ccc731e1ff4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91615211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_c sr_outstanding.91615211 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.728081194 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 278665960 ps |
CPU time | 5.95 seconds |
Started | Jun 27 06:20:05 PM PDT 24 |
Finished | Jun 27 06:20:15 PM PDT 24 |
Peak memory | 221440 kb |
Host | smart-77e8a0cf-f4cc-41bf-a0dc-b9722abbd4c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728081194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.728081194 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.364874843 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 1272056193 ps |
CPU time | 11.99 seconds |
Started | Jun 27 06:19:59 PM PDT 24 |
Finished | Jun 27 06:20:16 PM PDT 24 |
Peak memory | 213312 kb |
Host | smart-9311262e-ac2e-4dfc-ada1-065f39d8f82a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364874843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.364874843 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.45841093 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 1234941932 ps |
CPU time | 26.96 seconds |
Started | Jun 27 06:19:40 PM PDT 24 |
Finished | Jun 27 06:20:12 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-36355909-b7ed-4897-825d-a7ed2f854703 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45841093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.rv_dm_csr_aliasing.45841093 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1586626916 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 33287717826 ps |
CPU time | 41.82 seconds |
Started | Jun 27 06:19:46 PM PDT 24 |
Finished | Jun 27 06:20:32 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-60ee592f-fbe9-4e3c-a591-fc2209e588a9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586626916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1586626916 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2347451353 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 125123252 ps |
CPU time | 1.76 seconds |
Started | Jun 27 06:19:43 PM PDT 24 |
Finished | Jun 27 06:19:50 PM PDT 24 |
Peak memory | 213228 kb |
Host | smart-1d81446d-e825-4b75-943f-19104ee8b926 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347451353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2347451353 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.183618212 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 1441434297 ps |
CPU time | 4.33 seconds |
Started | Jun 27 06:19:35 PM PDT 24 |
Finished | Jun 27 06:19:43 PM PDT 24 |
Peak memory | 219008 kb |
Host | smart-bfc8adfc-3984-4ce5-a1ea-70c1095a02b8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183618212 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.183618212 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1060521023 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 224285798 ps |
CPU time | 2.52 seconds |
Started | Jun 27 06:19:33 PM PDT 24 |
Finished | Jun 27 06:19:39 PM PDT 24 |
Peak memory | 213084 kb |
Host | smart-e0f23651-cc52-4433-8673-c3fef8c9adf1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060521023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1060521023 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1270758395 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 56132836388 ps |
CPU time | 119.88 seconds |
Started | Jun 27 06:19:43 PM PDT 24 |
Finished | Jun 27 06:21:48 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-bfe7c95d-cd42-4a9d-951e-67a7db96f7ed |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270758395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_aliasing.1270758395 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4127092489 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 8225598430 ps |
CPU time | 21.77 seconds |
Started | Jun 27 06:19:34 PM PDT 24 |
Finished | Jun 27 06:19:59 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-90565488-5260-4ed3-af5a-866703191e32 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127092489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. rv_dm_jtag_dmi_csr_bit_bash.4127092489 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1623193719 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 5113809319 ps |
CPU time | 5.24 seconds |
Started | Jun 27 06:19:39 PM PDT 24 |
Finished | Jun 27 06:19:48 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-99585f0e-379c-429e-90be-c574f6c2770b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623193719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.1623193719 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1892304774 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 9068243066 ps |
CPU time | 9.33 seconds |
Started | Jun 27 06:19:32 PM PDT 24 |
Finished | Jun 27 06:19:45 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-63d78e4d-a2c1-4a5c-91eb-2607767050ff |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892304774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1 892304774 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1801204072 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 341315984 ps |
CPU time | 1.53 seconds |
Started | Jun 27 06:19:36 PM PDT 24 |
Finished | Jun 27 06:19:41 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-306863ae-5143-436d-8dd8-d20e54ac0e8a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801204072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.1801204072 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1343251890 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 13032593733 ps |
CPU time | 9.94 seconds |
Started | Jun 27 06:19:32 PM PDT 24 |
Finished | Jun 27 06:19:45 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-4550ae1b-3150-4aca-ad28-36dd0388f41c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343251890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.1343251890 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2014693844 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 397666556 ps |
CPU time | 0.74 seconds |
Started | Jun 27 06:19:39 PM PDT 24 |
Finished | Jun 27 06:19:45 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-2c9cc44a-90d7-484a-b38d-f8c8e6e71a44 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014693844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.2014693844 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1089470464 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 1343430594 ps |
CPU time | 1.46 seconds |
Started | Jun 27 06:19:44 PM PDT 24 |
Finished | Jun 27 06:19:50 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-1645536f-8db8-44bc-8201-f7826c648b75 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089470464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1 089470464 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.182538636 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 155568530 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:19:41 PM PDT 24 |
Finished | Jun 27 06:19:47 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-1900ea61-2797-47ae-981a-83ff197d367f |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182538636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part ial_access.182538636 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4213792780 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 87118238 ps |
CPU time | 0.72 seconds |
Started | Jun 27 06:19:40 PM PDT 24 |
Finished | Jun 27 06:19:47 PM PDT 24 |
Peak memory | 204696 kb |
Host | smart-c8190f97-7df7-4e9e-8100-9d68c3fe215f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213792780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.4213792780 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2787467465 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 243194990 ps |
CPU time | 4.26 seconds |
Started | Jun 27 06:19:40 PM PDT 24 |
Finished | Jun 27 06:19:50 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-60a5012d-6810-44c9-a120-4eeba4cfbb44 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787467465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.2787467465 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.875720369 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 479623041 ps |
CPU time | 4.69 seconds |
Started | Jun 27 06:19:34 PM PDT 24 |
Finished | Jun 27 06:19:42 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-384afaf0-7031-4750-9722-71e24fb5245b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875720369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.875720369 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3267007243 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 4871403566 ps |
CPU time | 20.71 seconds |
Started | Jun 27 06:19:42 PM PDT 24 |
Finished | Jun 27 06:20:08 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-46797a6d-e80f-48c3-92c5-706b9dbcbca5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267007243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3267007243 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3507833290 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 2320712087 ps |
CPU time | 26.71 seconds |
Started | Jun 27 06:19:48 PM PDT 24 |
Finished | Jun 27 06:20:19 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-f2377e9d-5baf-47e7-b240-562873129d47 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507833290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.3507833290 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3705646910 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 23585753166 ps |
CPU time | 73 seconds |
Started | Jun 27 06:19:46 PM PDT 24 |
Finished | Jun 27 06:21:04 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-9754ea2a-9dd0-4bd0-8d57-b93c1b4bdc66 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705646910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3705646910 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.126068673 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 302886997 ps |
CPU time | 2.29 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:02 PM PDT 24 |
Peak memory | 213240 kb |
Host | smart-fbb2f7d6-27c2-43b6-a913-9b7f9c143ae3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126068673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.126068673 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.473239200 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 4187662678 ps |
CPU time | 10.73 seconds |
Started | Jun 27 06:19:52 PM PDT 24 |
Finished | Jun 27 06:20:09 PM PDT 24 |
Peak memory | 221388 kb |
Host | smart-170d5346-f273-45a5-b2c8-0dc427004d90 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473239200 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.473239200 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1058224439 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 117933409 ps |
CPU time | 2.26 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:19:57 PM PDT 24 |
Peak memory | 213180 kb |
Host | smart-30318f22-c1e7-455d-af0d-ea330fc267c9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058224439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1058224439 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1011788236 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 20425304018 ps |
CPU time | 56.86 seconds |
Started | Jun 27 06:19:39 PM PDT 24 |
Finished | Jun 27 06:20:41 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-cab91577-3bb0-45d9-a802-cc7918407101 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011788236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.1011788236 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3431493718 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 21754118803 ps |
CPU time | 18.4 seconds |
Started | Jun 27 06:19:47 PM PDT 24 |
Finished | Jun 27 06:20:10 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-a7c85f60-d880-470c-b4e4-77245e029cad |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431493718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rv_dm_jtag_dmi_csr_bit_bash.3431493718 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2552828393 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 3858319936 ps |
CPU time | 3.59 seconds |
Started | Jun 27 06:19:46 PM PDT 24 |
Finished | Jun 27 06:19:54 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-7549e17e-1c8a-464d-a17c-5f5435a542fa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552828393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.2552828393 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.490821386 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 3964866653 ps |
CPU time | 4.52 seconds |
Started | Jun 27 06:19:47 PM PDT 24 |
Finished | Jun 27 06:19:57 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-4a9910c2-6055-40ee-89f2-7b1339ebcd76 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490821386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.490821386 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2545412892 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 1903874459 ps |
CPU time | 3.04 seconds |
Started | Jun 27 06:19:48 PM PDT 24 |
Finished | Jun 27 06:19:55 PM PDT 24 |
Peak memory | 204728 kb |
Host | smart-313ed7d2-6a06-4f15-add7-081dd59ae1e1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545412892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.2545412892 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1096566793 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 22420380551 ps |
CPU time | 31.7 seconds |
Started | Jun 27 06:19:43 PM PDT 24 |
Finished | Jun 27 06:20:20 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-ee8e09d6-e08f-4c08-9583-16f30b79492d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096566793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.1096566793 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2390665007 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 531144944 ps |
CPU time | 1.04 seconds |
Started | Jun 27 06:19:42 PM PDT 24 |
Finished | Jun 27 06:19:48 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-96ab0aef-66f4-460e-8a88-38a41cc2c8e0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390665007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.2390665007 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3908493727 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 647254526 ps |
CPU time | 2.46 seconds |
Started | Jun 27 06:19:43 PM PDT 24 |
Finished | Jun 27 06:19:51 PM PDT 24 |
Peak memory | 204576 kb |
Host | smart-baa2f8da-4c6e-4a28-99e2-3ecd3be1b955 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908493727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3 908493727 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1303950397 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 65998207 ps |
CPU time | 0.74 seconds |
Started | Jun 27 06:19:48 PM PDT 24 |
Finished | Jun 27 06:19:53 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-b53eed17-c14b-4a1c-920f-31ec63ef2eba |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303950397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.1303950397 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2031020361 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 50515471 ps |
CPU time | 0.7 seconds |
Started | Jun 27 06:19:46 PM PDT 24 |
Finished | Jun 27 06:19:52 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-3bd4cd6b-5576-4953-9527-07bd793305b3 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031020361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2031020361 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1416687834 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 250914219 ps |
CPU time | 4.06 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:04 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-462da522-e318-4711-808c-45b47250ff8d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416687834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.1416687834 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3115029878 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 30462021766 ps |
CPU time | 25.65 seconds |
Started | Jun 27 06:19:37 PM PDT 24 |
Finished | Jun 27 06:20:07 PM PDT 24 |
Peak memory | 221452 kb |
Host | smart-bc01aa6c-8635-4229-94f9-7388a2a32ebd |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115029878 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3115029878 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2925610640 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 186213654 ps |
CPU time | 3.16 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:03 PM PDT 24 |
Peak memory | 221504 kb |
Host | smart-f7f313db-c65f-4bb0-bfaf-1c539e2fafaf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925610640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2925610640 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2559869631 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 686741865 ps |
CPU time | 27.13 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:27 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-701adf76-6afd-4a98-9295-a0b40d911391 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559869631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.2559869631 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3673892368 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 7402119549 ps |
CPU time | 70.4 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:21:06 PM PDT 24 |
Peak memory | 213336 kb |
Host | smart-3328ec46-b7c5-4780-9dfc-8c51bee58aad |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673892368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3673892368 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2024122014 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 308485327 ps |
CPU time | 2.29 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:02 PM PDT 24 |
Peak memory | 213188 kb |
Host | smart-1936045b-4aa5-4339-b357-7a3a99e538ac |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024122014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2024122014 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1607441180 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 260323303 ps |
CPU time | 3.8 seconds |
Started | Jun 27 06:19:49 PM PDT 24 |
Finished | Jun 27 06:19:57 PM PDT 24 |
Peak memory | 218300 kb |
Host | smart-a320c7e8-df70-4126-aa67-59f271fbba76 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607441180 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1607441180 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.608102480 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 1188626421 ps |
CPU time | 2.28 seconds |
Started | Jun 27 06:19:47 PM PDT 24 |
Finished | Jun 27 06:19:54 PM PDT 24 |
Peak memory | 213224 kb |
Host | smart-56500549-0bb3-4570-b67d-c6c0ab6ee934 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608102480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.608102480 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3027292464 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 24422791927 ps |
CPU time | 41.54 seconds |
Started | Jun 27 06:19:46 PM PDT 24 |
Finished | Jun 27 06:20:32 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-827de4f5-8d1f-432c-a41e-8a8969ab002e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027292464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.3027292464 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3276374079 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 6476684132 ps |
CPU time | 18.97 seconds |
Started | Jun 27 06:19:49 PM PDT 24 |
Finished | Jun 27 06:20:12 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-285984b1-e8c4-432d-80bf-af29eba39d8d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276374079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. rv_dm_jtag_dmi_csr_bit_bash.3276374079 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1317643192 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 2740080764 ps |
CPU time | 2.97 seconds |
Started | Jun 27 06:19:53 PM PDT 24 |
Finished | Jun 27 06:20:01 PM PDT 24 |
Peak memory | 205092 kb |
Host | smart-33d91813-d00d-45c2-92c5-45ec1e07709d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317643192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.1317643192 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3519342876 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 2414723412 ps |
CPU time | 6.78 seconds |
Started | Jun 27 06:19:51 PM PDT 24 |
Finished | Jun 27 06:20:03 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-bae4f9f0-1eca-4d7b-9165-6be1baeb5b3c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519342876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3 519342876 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.236929405 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 1635723757 ps |
CPU time | 1.67 seconds |
Started | Jun 27 06:19:51 PM PDT 24 |
Finished | Jun 27 06:19:58 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-6ca47f53-368b-44f8-9919-ad3132094433 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236929405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _aliasing.236929405 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.333091859 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 8167147584 ps |
CPU time | 23.19 seconds |
Started | Jun 27 06:19:48 PM PDT 24 |
Finished | Jun 27 06:20:15 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-98457e9b-18ff-478c-9f73-b60f12e73b1a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333091859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _bit_bash.333091859 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.392007654 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 552580663 ps |
CPU time | 1.02 seconds |
Started | Jun 27 06:19:59 PM PDT 24 |
Finished | Jun 27 06:20:06 PM PDT 24 |
Peak memory | 204688 kb |
Host | smart-6097edbb-a456-4707-9ae2-69e4818c1b3a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392007654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _hw_reset.392007654 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1617019684 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 154947750 ps |
CPU time | 1.07 seconds |
Started | Jun 27 06:19:51 PM PDT 24 |
Finished | Jun 27 06:19:57 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-539b8781-69d2-414a-9d81-6a5a2ee448d5 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617019684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1 617019684 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.4169344934 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 210685905 ps |
CPU time | 0.78 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:19:56 PM PDT 24 |
Peak memory | 204732 kb |
Host | smart-b930851e-bcf5-4bda-8d7a-d8d80f13e7b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169344934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.4169344934 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.888705895 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 27286053 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:19:51 PM PDT 24 |
Finished | Jun 27 06:19:56 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-d40881ab-e27b-44a0-831e-4c15c64ef820 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888705895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.888705895 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3205451184 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 191539682 ps |
CPU time | 3.51 seconds |
Started | Jun 27 06:19:49 PM PDT 24 |
Finished | Jun 27 06:19:57 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-45153ebd-b4c5-45ae-ba34-0dab106ff774 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205451184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_ csr_outstanding.3205451184 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1127401208 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 58368344503 ps |
CPU time | 22.77 seconds |
Started | Jun 27 06:19:53 PM PDT 24 |
Finished | Jun 27 06:20:21 PM PDT 24 |
Peak memory | 222420 kb |
Host | smart-416624a5-98f9-4b69-b74a-a3676acb3b1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127401208 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1127401208 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.926435625 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 680476873 ps |
CPU time | 3.45 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:04 PM PDT 24 |
Peak memory | 213368 kb |
Host | smart-a1fec79f-ade6-4dc6-8102-5f1c4d7e2150 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926435625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.926435625 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4227888156 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 6097589254 ps |
CPU time | 21.07 seconds |
Started | Jun 27 06:19:48 PM PDT 24 |
Finished | Jun 27 06:20:14 PM PDT 24 |
Peak memory | 221524 kb |
Host | smart-7b076880-fac0-4fdb-a949-05113a9c8487 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227888156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.4227888156 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4273815240 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 136683847 ps |
CPU time | 2.93 seconds |
Started | Jun 27 06:19:52 PM PDT 24 |
Finished | Jun 27 06:20:01 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-4bb040ee-94b8-42da-b325-a7c89e39c4b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273815240 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.4273815240 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2910507594 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 286479696 ps |
CPU time | 2.38 seconds |
Started | Jun 27 06:19:51 PM PDT 24 |
Finished | Jun 27 06:19:58 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-725b35cf-f725-48ee-b23a-3090e1d8eab0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910507594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2910507594 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.92393348 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 114196892829 ps |
CPU time | 142.89 seconds |
Started | Jun 27 06:19:53 PM PDT 24 |
Finished | Jun 27 06:22:21 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-22754af7-d3b0-482b-9394-2e9e47a0bd55 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92393348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv _dm_jtag_dmi_csr_bit_bash.92393348 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.449504560 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 1468314969 ps |
CPU time | 2.73 seconds |
Started | Jun 27 06:19:48 PM PDT 24 |
Finished | Jun 27 06:19:55 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-e420279b-30b7-4179-9800-2cf6133ad4b9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449504560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.449504560 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3396466768 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 275695602 ps |
CPU time | 0.95 seconds |
Started | Jun 27 06:19:56 PM PDT 24 |
Finished | Jun 27 06:20:03 PM PDT 24 |
Peak memory | 204716 kb |
Host | smart-767c89c9-affa-450d-9b13-a8f8c9ec2832 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396466768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3 396466768 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1470979658 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 430250011 ps |
CPU time | 7.51 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:08 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-2d1ff4e4-4c08-483d-9301-f3de283beed3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470979658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.1470979658 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1536412663 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 59912874393 ps |
CPU time | 60.01 seconds |
Started | Jun 27 06:19:44 PM PDT 24 |
Finished | Jun 27 06:20:49 PM PDT 24 |
Peak memory | 224444 kb |
Host | smart-891d8dc2-1ac1-4082-bbee-18632659fe91 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536412663 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.1536412663 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3771402014 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 74748609 ps |
CPU time | 3.18 seconds |
Started | Jun 27 06:19:58 PM PDT 24 |
Finished | Jun 27 06:20:07 PM PDT 24 |
Peak memory | 213272 kb |
Host | smart-e66f79bf-264e-4467-86fe-677cf4e5f3d5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771402014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3771402014 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3970041079 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 1167267013 ps |
CPU time | 10.11 seconds |
Started | Jun 27 06:19:49 PM PDT 24 |
Finished | Jun 27 06:20:04 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-9787a20a-2172-4b63-813d-785a8879cbe3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970041079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3970041079 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4098104547 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 148440545 ps |
CPU time | 2.14 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:19:58 PM PDT 24 |
Peak memory | 213212 kb |
Host | smart-7086ec7c-e5eb-4d01-a4cf-e467564020a0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098104547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.4098104547 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.675511423 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 22109318493 ps |
CPU time | 31.3 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:31 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-f7bbcc67-05a7-4b1e-95c2-ad39898d4272 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675511423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r v_dm_jtag_dmi_csr_bit_bash.675511423 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2141716537 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 2674960100 ps |
CPU time | 1.46 seconds |
Started | Jun 27 06:19:51 PM PDT 24 |
Finished | Jun 27 06:19:58 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-f7a58806-1ac1-4b26-93d7-269109c77ee1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141716537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2 141716537 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4287105086 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 214562126 ps |
CPU time | 1.2 seconds |
Started | Jun 27 06:19:44 PM PDT 24 |
Finished | Jun 27 06:19:50 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-75daf756-26ef-4105-a223-58c958e627e9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287105086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.4 287105086 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2916398397 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 780509973 ps |
CPU time | 8.16 seconds |
Started | Jun 27 06:19:52 PM PDT 24 |
Finished | Jun 27 06:20:06 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-8432e263-0b44-4eae-b4e5-6a56cced527b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916398397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_ csr_outstanding.2916398397 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1092244654 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 191914758 ps |
CPU time | 4.55 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:20:00 PM PDT 24 |
Peak memory | 215780 kb |
Host | smart-4c343b64-e2d0-411b-ad10-044d1a1dc552 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092244654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1092244654 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3659591170 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 1996754437 ps |
CPU time | 4.68 seconds |
Started | Jun 27 06:19:52 PM PDT 24 |
Finished | Jun 27 06:20:02 PM PDT 24 |
Peak memory | 217868 kb |
Host | smart-05bd00ca-d133-455e-ab84-d5a356d45c22 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659591170 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3659591170 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3024739084 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 417675902 ps |
CPU time | 1.64 seconds |
Started | Jun 27 06:19:49 PM PDT 24 |
Finished | Jun 27 06:19:55 PM PDT 24 |
Peak memory | 213284 kb |
Host | smart-aaec188d-108b-47fe-890e-323b1974ed4e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024739084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3024739084 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1679024584 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 28964110102 ps |
CPU time | 21.15 seconds |
Started | Jun 27 06:19:58 PM PDT 24 |
Finished | Jun 27 06:20:25 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-e1f1c18e-455a-4c5e-9a30-b511c57f9159 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679024584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. rv_dm_jtag_dmi_csr_bit_bash.1679024584 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1829066560 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 2879125961 ps |
CPU time | 8.43 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:20:02 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-d6c3ee57-4c07-412a-ad29-1596968380fa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829066560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1 829066560 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1128378975 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 214327840 ps |
CPU time | 0.81 seconds |
Started | Jun 27 06:19:52 PM PDT 24 |
Finished | Jun 27 06:19:59 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-d71ca347-1d17-4e78-97bb-c5c5e6fd3a5e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128378975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1 128378975 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.857048189 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 1054732519 ps |
CPU time | 7.14 seconds |
Started | Jun 27 06:19:50 PM PDT 24 |
Finished | Jun 27 06:20:03 PM PDT 24 |
Peak memory | 205176 kb |
Host | smart-1b9ae46c-13e6-45f6-9919-4a9bed5a5531 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857048189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c sr_outstanding.857048189 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3263167309 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 36537034187 ps |
CPU time | 15.96 seconds |
Started | Jun 27 06:19:51 PM PDT 24 |
Finished | Jun 27 06:20:12 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-72e54824-a76c-4950-993e-ba90512fd84a |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263167309 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3263167309 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2184242489 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 174510068 ps |
CPU time | 4.27 seconds |
Started | Jun 27 06:19:51 PM PDT 24 |
Finished | Jun 27 06:20:00 PM PDT 24 |
Peak memory | 213280 kb |
Host | smart-45ec4aae-3024-4329-9ccb-aa7eeade0450 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184242489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2184242489 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3399773842 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 421491607 ps |
CPU time | 3.88 seconds |
Started | Jun 27 06:19:53 PM PDT 24 |
Finished | Jun 27 06:20:02 PM PDT 24 |
Peak memory | 221472 kb |
Host | smart-508f4a97-717e-4239-b8b9-dcb071385002 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399773842 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3399773842 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2695692506 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 52702050 ps |
CPU time | 2.2 seconds |
Started | Jun 27 06:20:02 PM PDT 24 |
Finished | Jun 27 06:20:09 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-89fa5f3c-f1d7-41af-9bd3-8b303bce2dab |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695692506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2695692506 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3228860015 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 13755396344 ps |
CPU time | 39.54 seconds |
Started | Jun 27 06:19:51 PM PDT 24 |
Finished | Jun 27 06:20:37 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-8bc8be8d-629d-43a9-8365-46e54cdfe78f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228860015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. rv_dm_jtag_dmi_csr_bit_bash.3228860015 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2562673654 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 2098037361 ps |
CPU time | 2.61 seconds |
Started | Jun 27 06:19:49 PM PDT 24 |
Finished | Jun 27 06:19:56 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-58660592-50f6-4224-a614-a12ca21def7d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562673654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2 562673654 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2971113722 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 171741342 ps |
CPU time | 1.16 seconds |
Started | Jun 27 06:19:58 PM PDT 24 |
Finished | Jun 27 06:20:04 PM PDT 24 |
Peak memory | 204724 kb |
Host | smart-648e336c-052b-4a23-ace5-2de9eb99fef0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971113722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2 971113722 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1706516369 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 2134657266 ps |
CPU time | 7.45 seconds |
Started | Jun 27 06:19:59 PM PDT 24 |
Finished | Jun 27 06:20:12 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-c30b08b9-56c9-45e6-97e0-c306407d09f6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706516369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.1706516369 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2511280776 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 16822494498 ps |
CPU time | 41.51 seconds |
Started | Jun 27 06:19:53 PM PDT 24 |
Finished | Jun 27 06:20:40 PM PDT 24 |
Peak memory | 220680 kb |
Host | smart-665ad1dd-a023-4976-8f16-e4701c4e5c80 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511280776 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.2511280776 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3965768334 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 545904689 ps |
CPU time | 5.44 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:05 PM PDT 24 |
Peak memory | 213288 kb |
Host | smart-072ca36b-bb56-406d-bfd7-8be5c56d75e9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965768334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3965768334 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.557387793 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 1877054177 ps |
CPU time | 15.51 seconds |
Started | Jun 27 06:19:52 PM PDT 24 |
Finished | Jun 27 06:20:13 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-30a368e1-7fcc-4de6-928a-258260c5f59c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557387793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.557387793 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3999048960 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 2688557384 ps |
CPU time | 5.71 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:06 PM PDT 24 |
Peak memory | 221256 kb |
Host | smart-0a2e6d22-5181-41c9-a706-31a871da9a9b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999048960 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3999048960 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.158604590 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 177270417 ps |
CPU time | 2.51 seconds |
Started | Jun 27 06:19:52 PM PDT 24 |
Finished | Jun 27 06:20:00 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-2a5bf761-f33c-4935-bac3-ad6416aebbca |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158604590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.158604590 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2019106076 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 4771917265 ps |
CPU time | 8.91 seconds |
Started | Jun 27 06:19:54 PM PDT 24 |
Finished | Jun 27 06:20:08 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-f01c1f9c-36a2-470a-b62a-62c1cf2b80dd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019106076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.2019106076 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1358022119 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 2496863541 ps |
CPU time | 7.55 seconds |
Started | Jun 27 06:19:53 PM PDT 24 |
Finished | Jun 27 06:20:06 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-6b2de516-c537-4ce7-8cba-a4025a47cd57 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358022119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1 358022119 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4231068356 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 1041643269 ps |
CPU time | 1.42 seconds |
Started | Jun 27 06:19:59 PM PDT 24 |
Finished | Jun 27 06:20:06 PM PDT 24 |
Peak memory | 204720 kb |
Host | smart-1ae54c9f-929d-43c7-9f42-ed7d5a7d3504 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231068356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.4 231068356 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2205167473 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 770441344 ps |
CPU time | 4.28 seconds |
Started | Jun 27 06:19:59 PM PDT 24 |
Finished | Jun 27 06:20:09 PM PDT 24 |
Peak memory | 205104 kb |
Host | smart-5a15cb37-a028-4ece-872f-5726687f678e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205167473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.2205167473 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.978938020 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 709856594 ps |
CPU time | 4.82 seconds |
Started | Jun 27 06:20:00 PM PDT 24 |
Finished | Jun 27 06:20:10 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-6d5ee352-9491-4459-90f7-eca57a8c8732 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978938020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.978938020 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1504458639 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 3001150678 ps |
CPU time | 18.04 seconds |
Started | Jun 27 06:19:55 PM PDT 24 |
Finished | Jun 27 06:20:19 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-5b4f067a-af90-4d2c-b3ce-11e640617e34 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504458639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1504458639 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.698571901 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 10928472375 ps |
CPU time | 8.59 seconds |
Started | Jun 27 06:22:33 PM PDT 24 |
Finished | Jun 27 06:22:47 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-e98bf39e-4103-4af0-a157-f2cc3887e446 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698571901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.698571901 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.3055825277 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 733461440 ps |
CPU time | 1.33 seconds |
Started | Jun 27 06:22:29 PM PDT 24 |
Finished | Jun 27 06:22:32 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-6d0fb2db-b071-4ec1-9766-9094b54cdd16 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055825277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3055825277 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1144449195 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 239166279 ps |
CPU time | 1.36 seconds |
Started | Jun 27 06:22:30 PM PDT 24 |
Finished | Jun 27 06:22:34 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-38f8f0ba-cec5-4c19-bed7-6a7deb9582f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1144449195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1144449195 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3319636209 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 139001182 ps |
CPU time | 1.07 seconds |
Started | Jun 27 06:22:30 PM PDT 24 |
Finished | Jun 27 06:22:34 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-151ee365-0cd5-484f-85e7-8c42ae199edf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3319636209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3319636209 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1042778170 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 362118783 ps |
CPU time | 1.85 seconds |
Started | Jun 27 06:22:31 PM PDT 24 |
Finished | Jun 27 06:22:36 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-be0d2b36-ca80-49d3-8ec8-e12f8e00672f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042778170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1042778170 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.1275077719 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 803333071 ps |
CPU time | 1.76 seconds |
Started | Jun 27 06:22:35 PM PDT 24 |
Finished | Jun 27 06:22:43 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-9f798717-502f-47c0-9fdd-22da18adc99e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275077719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1275077719 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2640396478 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 227609970 ps |
CPU time | 0.86 seconds |
Started | Jun 27 06:22:36 PM PDT 24 |
Finished | Jun 27 06:22:43 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-2167718f-eec7-40d0-a651-5205b814e49e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2640396478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2640396478 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3950589533 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 1284029228 ps |
CPU time | 2.39 seconds |
Started | Jun 27 06:22:31 PM PDT 24 |
Finished | Jun 27 06:22:36 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-48e8a75d-e17c-4f79-80d7-ed151d66f913 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3950589533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3950589533 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2369509624 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 3122252930 ps |
CPU time | 5.75 seconds |
Started | Jun 27 06:22:31 PM PDT 24 |
Finished | Jun 27 06:22:41 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-4c8dddaf-110a-402a-87d0-abe11914db03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2369509624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2369509624 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2388859325 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 390595389 ps |
CPU time | 1.18 seconds |
Started | Jun 27 06:22:31 PM PDT 24 |
Finished | Jun 27 06:22:36 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-41101219-c805-41df-8a92-e4c3b93af51f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388859325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2388859325 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1548993085 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 217901996 ps |
CPU time | 1.26 seconds |
Started | Jun 27 06:22:32 PM PDT 24 |
Finished | Jun 27 06:22:37 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-2d729692-b528-4a66-a066-5b821b8800e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1548993085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1548993085 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.410113423 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 1626272481 ps |
CPU time | 3.24 seconds |
Started | Jun 27 06:22:30 PM PDT 24 |
Finished | Jun 27 06:22:36 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-eba8cb27-0837-4868-bd1b-62ea9e68ca56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=410113423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.410113423 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.4152209527 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 197116994 ps |
CPU time | 1.17 seconds |
Started | Jun 27 06:22:33 PM PDT 24 |
Finished | Jun 27 06:22:39 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-4a4eb436-6742-4f7e-ac13-95cf562d99fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4152209527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.4152209527 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_busy.3493014098 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 1058685654 ps |
CPU time | 3.49 seconds |
Started | Jun 27 06:22:31 PM PDT 24 |
Finished | Jun 27 06:22:38 PM PDT 24 |
Peak memory | 205136 kb |
Host | smart-638cd499-e2d1-4b4f-820b-28a5fa60f518 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493014098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3493014098 |
Directory | /workspace/0.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2862273356 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 696083535 ps |
CPU time | 2.37 seconds |
Started | Jun 27 06:22:32 PM PDT 24 |
Finished | Jun 27 06:22:39 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-63db7806-7c70-4f76-b13b-549c1b41ff46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862273356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2862273356 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.1837329208 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 3552649476 ps |
CPU time | 5.45 seconds |
Started | Jun 27 06:22:29 PM PDT 24 |
Finished | Jun 27 06:22:36 PM PDT 24 |
Peak memory | 213532 kb |
Host | smart-71747dfa-50bb-47f3-8844-69d52a069860 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837329208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1837329208 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.2663035486 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 2831670892 ps |
CPU time | 7.55 seconds |
Started | Jun 27 06:22:30 PM PDT 24 |
Finished | Jun 27 06:22:41 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-ab84f6d7-1291-410a-b84c-2d75b1ded9f8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2663035486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2663035486 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all.2906002303 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 3740493805 ps |
CPU time | 10.93 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:55 PM PDT 24 |
Peak memory | 213396 kb |
Host | smart-6023408c-2e08-4d9f-a798-532fef5f9cd3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906002303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2906002303 |
Directory | /workspace/0.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.836629304 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 510834561 ps |
CPU time | 1.95 seconds |
Started | Jun 27 06:22:36 PM PDT 24 |
Finished | Jun 27 06:22:44 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-c24536b4-1c73-48a3-8e96-23515079c305 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=836629304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.836629304 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.695893230 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 27830716 ps |
CPU time | 0.74 seconds |
Started | Jun 27 06:22:37 PM PDT 24 |
Finished | Jun 27 06:22:45 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-a176cdd5-db9a-4b55-b693-b2fb32148ccc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695893230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.695893230 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1447862224 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 5247581411 ps |
CPU time | 2.16 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:46 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-8f80212a-3e50-4149-aeff-1d925d7db449 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1447862224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1447862224 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.1827063069 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 4495463669 ps |
CPU time | 11 seconds |
Started | Jun 27 06:22:37 PM PDT 24 |
Finished | Jun 27 06:22:55 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-fca3e1e4-601b-4823-ba41-8cce460f1c2b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1827063069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.1827063069 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.2335747798 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 157652500 ps |
CPU time | 1.19 seconds |
Started | Jun 27 06:22:30 PM PDT 24 |
Finished | Jun 27 06:22:34 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-0878ae2e-410f-46f0-b0ce-c6408049de96 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335747798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2335747798 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.2747272166 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 1435640675 ps |
CPU time | 3.91 seconds |
Started | Jun 27 06:22:32 PM PDT 24 |
Finished | Jun 27 06:22:41 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-6403bb7b-5b05-4cfd-b7b0-c951dbc259be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2747272166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2747272166 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.978200998 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 345571601 ps |
CPU time | 1.2 seconds |
Started | Jun 27 06:22:36 PM PDT 24 |
Finished | Jun 27 06:22:44 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-ab0d5def-6151-41ba-a815-c3d97d14a51d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=978200998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.978200998 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.4050405227 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 320454143 ps |
CPU time | 0.85 seconds |
Started | Jun 27 06:22:32 PM PDT 24 |
Finished | Jun 27 06:22:38 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-4df5d60e-5688-46d5-869a-c0aeb6d0f1fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4050405227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.4050405227 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2330575292 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 580514609 ps |
CPU time | 0.99 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:46 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-34ad5644-7655-4268-a8ec-f91181d909e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2330575292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2330575292 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.1833429272 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 209588535 ps |
CPU time | 0.91 seconds |
Started | Jun 27 06:22:36 PM PDT 24 |
Finished | Jun 27 06:22:43 PM PDT 24 |
Peak memory | 215548 kb |
Host | smart-6a7e50a4-8a2e-4211-95cf-61fb6051f5fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833429272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1833429272 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.4173951576 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 1747659234 ps |
CPU time | 3.29 seconds |
Started | Jun 27 06:22:33 PM PDT 24 |
Finished | Jun 27 06:22:42 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-f3745c53-1d31-4a69-8a63-e6e530c784c3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4173951576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t l_access.4173951576 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2988110223 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 401064546 ps |
CPU time | 1.11 seconds |
Started | Jun 27 06:22:31 PM PDT 24 |
Finished | Jun 27 06:22:35 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-3c1c7174-1409-4724-802f-7755029d4fe9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2988110223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2988110223 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.109962116 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 284710725 ps |
CPU time | 0.77 seconds |
Started | Jun 27 06:22:35 PM PDT 24 |
Finished | Jun 27 06:22:42 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-fa816e6d-e807-4bfa-a0b7-8b607defc9db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=109962116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.109962116 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.4015160920 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 684464322 ps |
CPU time | 1.21 seconds |
Started | Jun 27 06:22:35 PM PDT 24 |
Finished | Jun 27 06:22:43 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-b1099609-f2e9-44bf-8a70-38cd7159567f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4015160920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.4015160920 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3641338430 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 2131581227 ps |
CPU time | 6.16 seconds |
Started | Jun 27 06:22:33 PM PDT 24 |
Finished | Jun 27 06:22:44 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-5fa5d95c-247c-4a5f-8eb5-81415e30e92f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3641338430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3641338430 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3406865713 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 754127540 ps |
CPU time | 0.85 seconds |
Started | Jun 27 06:22:35 PM PDT 24 |
Finished | Jun 27 06:22:42 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-69ed647e-a1a9-43aa-95e1-ec87b691b959 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3406865713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3406865713 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3502086486 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 80660318 ps |
CPU time | 0.77 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:45 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-f733d205-be23-42a4-8087-8d8acd368169 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3502086486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3502086486 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.675502419 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 1679247095 ps |
CPU time | 3.3 seconds |
Started | Jun 27 06:22:34 PM PDT 24 |
Finished | Jun 27 06:22:42 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-9510e21b-e041-4306-b956-d99bfe75fd7b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=675502419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.675502419 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1447113230 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 1571684556 ps |
CPU time | 3.06 seconds |
Started | Jun 27 06:22:34 PM PDT 24 |
Finished | Jun 27 06:22:44 PM PDT 24 |
Peak memory | 205112 kb |
Host | smart-d4fe7c88-e6c8-4384-98ba-8d0d8de53607 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1447113230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1447113230 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.1027725320 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 263411826 ps |
CPU time | 0.75 seconds |
Started | Jun 27 06:22:36 PM PDT 24 |
Finished | Jun 27 06:22:43 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-d546b5fd-d151-42e5-9840-d09c8da4c941 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1027725320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1027725320 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.86013623 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 417425835 ps |
CPU time | 1.04 seconds |
Started | Jun 27 06:22:33 PM PDT 24 |
Finished | Jun 27 06:22:39 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-162fab04-f860-435d-bacf-ab94827ff10d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=86013623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.86013623 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.2989333376 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 144892375 ps |
CPU time | 0.87 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:45 PM PDT 24 |
Peak memory | 213200 kb |
Host | smart-13e6bbee-caab-4e28-80f8-294901537dde |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2989333376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2989333376 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.4056158302 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 1240896711 ps |
CPU time | 2.04 seconds |
Started | Jun 27 06:22:32 PM PDT 24 |
Finished | Jun 27 06:22:39 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-fd7d2c1b-257f-4aa1-ad1c-fb0cea0e2fa7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056158302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.4056158302 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.152197986 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 6937550576 ps |
CPU time | 9.61 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:54 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-7d52b816-0e0a-4746-bb64-50982208b86b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=152197986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.152197986 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.2392561711 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 2444260014 ps |
CPU time | 7.37 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:52 PM PDT 24 |
Peak memory | 238144 kb |
Host | smart-a2095dd5-a790-4308-b45b-563c46b6d713 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392561711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2392561711 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.3670979882 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 2282311255 ps |
CPU time | 6.37 seconds |
Started | Jun 27 06:22:29 PM PDT 24 |
Finished | Jun 27 06:22:38 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-fd97ebe1-3c14-430d-a901-107576c64256 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3670979882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3670979882 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.4000876610 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 45292435 ps |
CPU time | 0.7 seconds |
Started | Jun 27 06:23:01 PM PDT 24 |
Finished | Jun 27 06:23:11 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-634ca4a7-fbbb-4d00-bbc0-1d4260c4ea23 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000876610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.4000876610 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3041068257 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 4857580429 ps |
CPU time | 12.56 seconds |
Started | Jun 27 06:22:45 PM PDT 24 |
Finished | Jun 27 06:23:03 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-a6c1a8b2-46b7-472e-8182-f44b3af39d2d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3041068257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3041068257 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2774864879 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 1481462811 ps |
CPU time | 5.24 seconds |
Started | Jun 27 06:22:47 PM PDT 24 |
Finished | Jun 27 06:22:57 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-41aa5569-d02b-4851-9d9f-26d23db4c173 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2774864879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.2774864879 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.3745688994 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 6356187482 ps |
CPU time | 3.42 seconds |
Started | Jun 27 06:22:55 PM PDT 24 |
Finished | Jun 27 06:23:07 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-15a237a6-f6ab-4e71-8703-938a03b03393 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745688994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3745688994 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.4179906249 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 3720247664 ps |
CPU time | 3.73 seconds |
Started | Jun 27 06:22:47 PM PDT 24 |
Finished | Jun 27 06:22:55 PM PDT 24 |
Peak memory | 221500 kb |
Host | smart-2f330ba9-a3a2-43f0-8b76-2376036581b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179906249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.4179906249 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.1098864127 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 62760050 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:22:50 PM PDT 24 |
Finished | Jun 27 06:22:56 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-416851cc-794f-4565-ade2-801a77508bde |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098864127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1098864127 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.666440480 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 1579517566 ps |
CPU time | 2.4 seconds |
Started | Jun 27 06:22:49 PM PDT 24 |
Finished | Jun 27 06:22:57 PM PDT 24 |
Peak memory | 212936 kb |
Host | smart-9e463e49-38d7-4f0a-b38b-477465a4543a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=666440480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.666440480 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.4186807781 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 3608649491 ps |
CPU time | 10.53 seconds |
Started | Jun 27 06:22:45 PM PDT 24 |
Finished | Jun 27 06:23:00 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-2e8e53fb-e4f2-46c6-b6a3-7a31c5ac1ca7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186807781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.4186807781 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1297038655 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 4218215451 ps |
CPU time | 2.17 seconds |
Started | Jun 27 06:22:49 PM PDT 24 |
Finished | Jun 27 06:22:56 PM PDT 24 |
Peak memory | 213560 kb |
Host | smart-a5896cfb-119b-4ded-b024-c6f87a95ba8c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1297038655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.1297038655 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.2847504468 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 2363476486 ps |
CPU time | 6.52 seconds |
Started | Jun 27 06:22:48 PM PDT 24 |
Finished | Jun 27 06:22:59 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-fb799fb2-b736-4598-8a77-641d7a37fdde |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2847504468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2847504468 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.748060926 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 8926883396 ps |
CPU time | 11.13 seconds |
Started | Jun 27 06:22:49 PM PDT 24 |
Finished | Jun 27 06:23:05 PM PDT 24 |
Peak memory | 213352 kb |
Host | smart-331a0ef8-69f5-4a09-845c-1f4b138e96f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748060926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.748060926 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.1593779196 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 154657961 ps |
CPU time | 0.85 seconds |
Started | Jun 27 06:22:45 PM PDT 24 |
Finished | Jun 27 06:22:51 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-c6c397dc-f405-47e8-bd30-26fea607e05e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593779196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1593779196 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.524390303 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 7383462247 ps |
CPU time | 19.65 seconds |
Started | Jun 27 06:22:55 PM PDT 24 |
Finished | Jun 27 06:23:23 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-13c0828d-34a0-4968-a185-15830e6b0e2f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=524390303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.524390303 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2800325092 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 3720448184 ps |
CPU time | 2.18 seconds |
Started | Jun 27 06:22:54 PM PDT 24 |
Finished | Jun 27 06:23:03 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-615b888f-e716-4433-861d-f78b71f47880 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2800325092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2800325092 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3419621949 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 3945671118 ps |
CPU time | 6.81 seconds |
Started | Jun 27 06:22:48 PM PDT 24 |
Finished | Jun 27 06:23:00 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-942ca04e-c6ef-4341-8c8b-d1395a274cbb |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3419621949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_ tl_access.3419621949 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.438223359 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 8175035916 ps |
CPU time | 7.62 seconds |
Started | Jun 27 06:22:48 PM PDT 24 |
Finished | Jun 27 06:23:00 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-1088d395-2b74-416b-b7f5-cd4d1a4f3275 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438223359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.438223359 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_stress_all.1707992061 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 8303049926 ps |
CPU time | 15.91 seconds |
Started | Jun 27 06:22:47 PM PDT 24 |
Finished | Jun 27 06:23:08 PM PDT 24 |
Peak memory | 214780 kb |
Host | smart-bd3bafc9-91c2-4dec-83b2-1e7aea53cab8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707992061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1707992061 |
Directory | /workspace/12.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.1203742207 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 221895085 ps |
CPU time | 0.85 seconds |
Started | Jun 27 06:22:45 PM PDT 24 |
Finished | Jun 27 06:22:51 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-17cb3be6-d44a-4f09-95d1-ab656f5782a1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203742207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1203742207 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.251555359 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 7040822766 ps |
CPU time | 2.96 seconds |
Started | Jun 27 06:22:49 PM PDT 24 |
Finished | Jun 27 06:22:57 PM PDT 24 |
Peak memory | 213020 kb |
Host | smart-9ade8213-5d90-41f5-bb28-e8a8fb5f8b98 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=251555359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.251555359 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1379674968 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 5678205093 ps |
CPU time | 5.67 seconds |
Started | Jun 27 06:22:51 PM PDT 24 |
Finished | Jun 27 06:23:02 PM PDT 24 |
Peak memory | 213032 kb |
Host | smart-5b6a19a9-bc06-4480-a4e6-ba81588fd19a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379674968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1379674968 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1120824317 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 4286087021 ps |
CPU time | 12.75 seconds |
Started | Jun 27 06:22:57 PM PDT 24 |
Finished | Jun 27 06:23:18 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-727b358b-4672-48e6-b3c4-b7e3d9561c62 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1120824317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.1120824317 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.22725539 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 1186368263 ps |
CPU time | 2.2 seconds |
Started | Jun 27 06:22:49 PM PDT 24 |
Finished | Jun 27 06:22:56 PM PDT 24 |
Peak memory | 213372 kb |
Host | smart-9788e317-ff71-40ef-a42e-35dded769f3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22725539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.22725539 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.2270385547 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 62649347 ps |
CPU time | 0.75 seconds |
Started | Jun 27 06:22:50 PM PDT 24 |
Finished | Jun 27 06:22:56 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-a823c6b6-bff2-4504-93e9-010dca9cf96f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270385547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2270385547 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2167919331 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 52314300803 ps |
CPU time | 80.81 seconds |
Started | Jun 27 06:22:49 PM PDT 24 |
Finished | Jun 27 06:24:15 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-b1dc44d4-db6b-4979-a6a3-d6f8ffd2f1e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167919331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2167919331 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.283441572 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 3991324263 ps |
CPU time | 2.65 seconds |
Started | Jun 27 06:22:58 PM PDT 24 |
Finished | Jun 27 06:23:10 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-689e879c-08a2-4c19-b4b3-e3f8a6adc522 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283441572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.283441572 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.552850966 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 4355825451 ps |
CPU time | 3.96 seconds |
Started | Jun 27 06:22:56 PM PDT 24 |
Finished | Jun 27 06:23:07 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-f97394eb-a7c3-4182-9a8f-729bbf9c8b36 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=552850966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t l_access.552850966 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.1023210146 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 10426202567 ps |
CPU time | 3.12 seconds |
Started | Jun 27 06:22:55 PM PDT 24 |
Finished | Jun 27 06:23:06 PM PDT 24 |
Peak memory | 213568 kb |
Host | smart-6d755740-67dc-42bf-9346-108da75c0bb3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023210146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1023210146 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.1593347848 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 8670737975 ps |
CPU time | 5.6 seconds |
Started | Jun 27 06:23:02 PM PDT 24 |
Finished | Jun 27 06:23:16 PM PDT 24 |
Peak memory | 213420 kb |
Host | smart-58598efd-8b67-49cb-bd20-0841c9f09648 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593347848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1593347848 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.1914206104 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 89763151 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:22:55 PM PDT 24 |
Finished | Jun 27 06:23:04 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-8e6410c0-f425-4de8-8622-9c3f6347cd9f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914206104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1914206104 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3057731048 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 2923668320 ps |
CPU time | 9.26 seconds |
Started | Jun 27 06:22:51 PM PDT 24 |
Finished | Jun 27 06:23:06 PM PDT 24 |
Peak memory | 212928 kb |
Host | smart-d120216a-cb33-45ac-81a9-5a12d6e84a7d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057731048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3057731048 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.933514614 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 3475196721 ps |
CPU time | 1.83 seconds |
Started | Jun 27 06:22:48 PM PDT 24 |
Finished | Jun 27 06:22:55 PM PDT 24 |
Peak memory | 213424 kb |
Host | smart-98f53933-8802-4ee3-8244-1ff226b52401 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=933514614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.933514614 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.688958479 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 10750446373 ps |
CPU time | 19.31 seconds |
Started | Jun 27 06:22:47 PM PDT 24 |
Finished | Jun 27 06:23:11 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-d205580e-fe21-4389-b55f-7b48a98c69ff |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=688958479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t l_access.688958479 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.1663437555 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 1323956685 ps |
CPU time | 1.68 seconds |
Started | Jun 27 06:22:55 PM PDT 24 |
Finished | Jun 27 06:23:04 PM PDT 24 |
Peak memory | 213448 kb |
Host | smart-843971c2-21e1-4a9c-868f-24b02130fdc7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663437555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1663437555 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.3977991338 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 220117288 ps |
CPU time | 0.81 seconds |
Started | Jun 27 06:23:07 PM PDT 24 |
Finished | Jun 27 06:23:17 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-cf8929c2-8d25-4e0c-a7c1-d3780e14bb9e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977991338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3977991338 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.87212448 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 54142042009 ps |
CPU time | 40.46 seconds |
Started | Jun 27 06:22:59 PM PDT 24 |
Finished | Jun 27 06:23:48 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-95421cfe-760a-4fa6-8f16-367be5254969 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87212448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.87212448 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.773460920 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 1153247774 ps |
CPU time | 3.57 seconds |
Started | Jun 27 06:23:01 PM PDT 24 |
Finished | Jun 27 06:23:13 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-d8ef980d-8797-46f6-8767-dfc37c118bcf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=773460920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.773460920 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.4082890414 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 1734061390 ps |
CPU time | 2.15 seconds |
Started | Jun 27 06:23:00 PM PDT 24 |
Finished | Jun 27 06:23:12 PM PDT 24 |
Peak memory | 213432 kb |
Host | smart-c5746cbc-f7e5-40eb-90c3-b9416a1f246f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4082890414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_ tl_access.4082890414 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.533227437 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 2043684765 ps |
CPU time | 6.43 seconds |
Started | Jun 27 06:22:52 PM PDT 24 |
Finished | Jun 27 06:23:04 PM PDT 24 |
Peak memory | 213468 kb |
Host | smart-bf95853e-5883-4733-9d05-58e8f0e382ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=533227437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.533227437 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.2576289319 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 96787965 ps |
CPU time | 0.8 seconds |
Started | Jun 27 06:22:56 PM PDT 24 |
Finished | Jun 27 06:23:05 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-9708f934-3ebc-4fb9-94cb-bbe56c1cf922 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576289319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2576289319 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2544777547 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 9231968323 ps |
CPU time | 13.52 seconds |
Started | Jun 27 06:22:58 PM PDT 24 |
Finished | Jun 27 06:23:20 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-5a1c6fa0-f638-4ede-a318-da885a8d9463 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544777547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2544777547 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.315354546 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 15996702255 ps |
CPU time | 23.56 seconds |
Started | Jun 27 06:22:49 PM PDT 24 |
Finished | Jun 27 06:23:17 PM PDT 24 |
Peak memory | 213420 kb |
Host | smart-2e9baec2-7535-40fd-884a-4a2ac1093ba1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315354546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.315354546 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1715416867 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 3036064768 ps |
CPU time | 7.65 seconds |
Started | Jun 27 06:22:56 PM PDT 24 |
Finished | Jun 27 06:23:12 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-25d25a4f-ba75-468b-b646-f19d78f843c2 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1715416867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.1715416867 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.139912635 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 5635138967 ps |
CPU time | 2.69 seconds |
Started | Jun 27 06:22:50 PM PDT 24 |
Finished | Jun 27 06:22:58 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-e723a737-81f4-4f3a-b059-0b135e4605b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=139912635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.139912635 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_stress_all.1798374152 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 5442723705 ps |
CPU time | 7.76 seconds |
Started | Jun 27 06:23:03 PM PDT 24 |
Finished | Jun 27 06:23:20 PM PDT 24 |
Peak memory | 213432 kb |
Host | smart-0b06b2b7-2d37-45fb-ba01-e435c0f2f9a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798374152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1798374152 |
Directory | /workspace/17.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.1909622383 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 30666575 ps |
CPU time | 0.72 seconds |
Started | Jun 27 06:22:57 PM PDT 24 |
Finished | Jun 27 06:23:07 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-7148bbb5-60ad-46a3-9b86-0bda9439ffa9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909622383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1909622383 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2582072990 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 5769370396 ps |
CPU time | 5.08 seconds |
Started | Jun 27 06:22:57 PM PDT 24 |
Finished | Jun 27 06:23:10 PM PDT 24 |
Peak memory | 213116 kb |
Host | smart-7c0d80c1-ed6b-445c-81a4-4f9b7bff7f5e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582072990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2582072990 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3236846869 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 1694964115 ps |
CPU time | 6.21 seconds |
Started | Jun 27 06:22:48 PM PDT 24 |
Finished | Jun 27 06:22:58 PM PDT 24 |
Peak memory | 213436 kb |
Host | smart-4a4b573c-a014-4613-89b0-7042732eebbb |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3236846869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_ tl_access.3236846869 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.1642600435 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 6201382650 ps |
CPU time | 7.04 seconds |
Started | Jun 27 06:23:06 PM PDT 24 |
Finished | Jun 27 06:23:27 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-fd787ece-166a-4d7e-9106-7102ce885a10 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1642600435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1642600435 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.3946533956 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 93031575 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:23:05 PM PDT 24 |
Finished | Jun 27 06:23:14 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-d330a6d4-2094-4f8e-8c24-6a06d2f9f5e4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946533956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3946533956 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3498398645 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 78476504939 ps |
CPU time | 208.23 seconds |
Started | Jun 27 06:23:01 PM PDT 24 |
Finished | Jun 27 06:26:39 PM PDT 24 |
Peak memory | 216176 kb |
Host | smart-231c3def-6654-488b-b742-36d3410211d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498398645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3498398645 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2335102982 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 3751405101 ps |
CPU time | 3.98 seconds |
Started | Jun 27 06:23:05 PM PDT 24 |
Finished | Jun 27 06:23:18 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-4df62152-eb1b-4aa7-aba4-9c1411295152 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335102982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2335102982 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1991230093 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 8377669381 ps |
CPU time | 7.49 seconds |
Started | Jun 27 06:22:57 PM PDT 24 |
Finished | Jun 27 06:23:13 PM PDT 24 |
Peak memory | 213172 kb |
Host | smart-f5c69ae7-89c3-44e2-93e5-13901a33c0f8 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1991230093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.1991230093 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.1047271464 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 3334767827 ps |
CPU time | 9.01 seconds |
Started | Jun 27 06:23:12 PM PDT 24 |
Finished | Jun 27 06:23:29 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-0ad6b441-4b8d-4035-b0f3-38646adc1156 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1047271464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1047271464 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.2526694967 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 8667932854 ps |
CPU time | 6.15 seconds |
Started | Jun 27 06:22:53 PM PDT 24 |
Finished | Jun 27 06:23:04 PM PDT 24 |
Peak memory | 213416 kb |
Host | smart-11c1c748-23b7-4a55-8d29-947aa3fca172 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526694967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2526694967 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.1124309859 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 78551041 ps |
CPU time | 0.74 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:46 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-b57120d1-dbd9-476b-88c3-3c6f13f1a628 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124309859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1124309859 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3594730297 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 1340274634 ps |
CPU time | 1.14 seconds |
Started | Jun 27 06:22:37 PM PDT 24 |
Finished | Jun 27 06:22:44 PM PDT 24 |
Peak memory | 214216 kb |
Host | smart-53f718db-9005-4266-9220-2066d818532b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594730297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3594730297 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.541306994 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 2726188728 ps |
CPU time | 1.96 seconds |
Started | Jun 27 06:22:36 PM PDT 24 |
Finished | Jun 27 06:22:44 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-1a546de4-f121-460f-b285-e765e291bb82 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=541306994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl _access.541306994 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.2140737053 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 143144878 ps |
CPU time | 0.76 seconds |
Started | Jun 27 06:22:33 PM PDT 24 |
Finished | Jun 27 06:22:39 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-3ff36412-76a6-4903-aa27-2871dcd08b96 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2140737053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2140737053 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.2853904075 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 13359155580 ps |
CPU time | 7.91 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:53 PM PDT 24 |
Peak memory | 215444 kb |
Host | smart-9384ec9c-c482-46fb-8340-79d9751e599a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2853904075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2853904075 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.4270104301 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 487394611 ps |
CPU time | 1.6 seconds |
Started | Jun 27 06:22:37 PM PDT 24 |
Finished | Jun 27 06:22:46 PM PDT 24 |
Peak memory | 237648 kb |
Host | smart-79daa069-3538-4804-8f7b-ad9524369935 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270104301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.4270104301 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.488843748 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 58530067 ps |
CPU time | 0.82 seconds |
Started | Jun 27 06:22:53 PM PDT 24 |
Finished | Jun 27 06:23:00 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-52c714ce-51bb-44b3-81b8-86406a7f61c9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488843748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.488843748 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/20.rv_dm_stress_all.3080248324 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 12576562430 ps |
CPU time | 7.86 seconds |
Started | Jun 27 06:22:53 PM PDT 24 |
Finished | Jun 27 06:23:07 PM PDT 24 |
Peak memory | 215496 kb |
Host | smart-41ea5a5e-6995-4d12-9642-ac4df96d4919 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080248324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3080248324 |
Directory | /workspace/20.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.3862102574 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 91783418 ps |
CPU time | 0.78 seconds |
Started | Jun 27 06:22:54 PM PDT 24 |
Finished | Jun 27 06:23:01 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-bc9d8de8-3861-472b-9b7f-153aa607d8ed |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862102574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3862102574 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.2349961970 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 7438142668 ps |
CPU time | 6.69 seconds |
Started | Jun 27 06:22:53 PM PDT 24 |
Finished | Jun 27 06:23:06 PM PDT 24 |
Peak memory | 213360 kb |
Host | smart-7ef3e429-a6db-4ada-973e-e5f364f44de2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349961970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2349961970 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.1308113471 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 129685786 ps |
CPU time | 0.76 seconds |
Started | Jun 27 06:22:54 PM PDT 24 |
Finished | Jun 27 06:23:02 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-4e0a0960-a5bc-4078-bc49-02d6b069e1e0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308113471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1308113471 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.2944627168 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 13773645057 ps |
CPU time | 19.36 seconds |
Started | Jun 27 06:22:54 PM PDT 24 |
Finished | Jun 27 06:23:21 PM PDT 24 |
Peak memory | 213316 kb |
Host | smart-8fb251a2-d17e-4cae-b8b4-1d37d7f5a206 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944627168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2944627168 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.1392322844 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 162734121 ps |
CPU time | 0.78 seconds |
Started | Jun 27 06:22:54 PM PDT 24 |
Finished | Jun 27 06:23:03 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-ae7b4cec-f3e3-4c77-88b7-5b5c511d75b2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392322844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1392322844 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.3303151701 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 46001313 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:22:57 PM PDT 24 |
Finished | Jun 27 06:23:07 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-c194562d-c9a9-4afd-838d-73c5491da291 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303151701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3303151701 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_stress_all.1609640723 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 9931810080 ps |
CPU time | 18.4 seconds |
Started | Jun 27 06:22:53 PM PDT 24 |
Finished | Jun 27 06:23:17 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-92af4e77-16af-4bb4-aef3-a8c0fdada5b5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609640723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1609640723 |
Directory | /workspace/24.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.1976489601 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 108280839 ps |
CPU time | 0.71 seconds |
Started | Jun 27 06:22:58 PM PDT 24 |
Finished | Jun 27 06:23:08 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-f0398251-717a-4346-993e-d3c721531ccf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976489601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1976489601 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.4110650541 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 36158996 ps |
CPU time | 0.75 seconds |
Started | Jun 27 06:22:56 PM PDT 24 |
Finished | Jun 27 06:23:06 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-a2a52ec3-f72b-48ff-9811-1f997f102820 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110650541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.4110650541 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.3505834372 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 109638010 ps |
CPU time | 0.8 seconds |
Started | Jun 27 06:23:07 PM PDT 24 |
Finished | Jun 27 06:23:17 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-634b6a1a-6da5-4a94-9aa5-aafdabf71729 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505834372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3505834372 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.775233322 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 4901347364 ps |
CPU time | 7.41 seconds |
Started | Jun 27 06:22:50 PM PDT 24 |
Finished | Jun 27 06:23:03 PM PDT 24 |
Peak memory | 205160 kb |
Host | smart-245ce1d9-40e9-4767-afd6-bf1d2cf79d42 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775233322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.775233322 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.255411451 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 80598900 ps |
CPU time | 0.82 seconds |
Started | Jun 27 06:22:53 PM PDT 24 |
Finished | Jun 27 06:23:00 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-e73fe35c-7b38-4b30-b638-c28c85d63493 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255411451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.255411451 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.4187276379 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 129150806 ps |
CPU time | 0.78 seconds |
Started | Jun 27 06:23:10 PM PDT 24 |
Finished | Jun 27 06:23:19 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-42407a22-9726-44bf-9a29-31fd94146632 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187276379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.4187276379 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.3371334911 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 139582361 ps |
CPU time | 0.75 seconds |
Started | Jun 27 06:22:36 PM PDT 24 |
Finished | Jun 27 06:22:43 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-187ef953-b1dd-470c-8489-992593309442 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371334911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3371334911 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2827775939 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 1692498692 ps |
CPU time | 3.54 seconds |
Started | Jun 27 06:22:37 PM PDT 24 |
Finished | Jun 27 06:22:47 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-f522ef52-ef06-41d5-8d61-c67c38d4ca33 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2827775939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2827775939 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1835413292 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 2794412414 ps |
CPU time | 5.64 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:51 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-8e157ba5-d8f1-494f-9c52-41778af10d99 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1835413292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1835413292 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3913454899 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 1750207306 ps |
CPU time | 2.1 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:47 PM PDT 24 |
Peak memory | 213444 kb |
Host | smart-8ce09e27-f49d-4dd1-8045-67439f36a2bf |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3913454899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.3913454899 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.3078144097 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 529588228 ps |
CPU time | 1.05 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:46 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-2fad0420-dfca-4e12-a97e-75a592f75147 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3078144097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3078144097 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.3173921759 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 11044807850 ps |
CPU time | 9.5 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:54 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-20699479-8422-4242-b30f-5d1eaf374372 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173921759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3173921759 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.181820833 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 501372426 ps |
CPU time | 1.57 seconds |
Started | Jun 27 06:22:35 PM PDT 24 |
Finished | Jun 27 06:22:43 PM PDT 24 |
Peak memory | 237052 kb |
Host | smart-f5313547-d03a-4cd6-bef1-ea11f2c5f8aa |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181820833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.181820833 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_dm_stress_all.3684932324 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 8486153403 ps |
CPU time | 8.62 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:54 PM PDT 24 |
Peak memory | 214204 kb |
Host | smart-bb38f202-3267-4f9a-afb5-afb8ea2626f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684932324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3684932324 |
Directory | /workspace/3.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.1201025047 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 77247153 ps |
CPU time | 0.87 seconds |
Started | Jun 27 06:23:04 PM PDT 24 |
Finished | Jun 27 06:23:14 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-b649e158-610e-4bfa-946a-b5411db8a3b4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201025047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1201025047 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.3285622040 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 43948039 ps |
CPU time | 0.75 seconds |
Started | Jun 27 06:23:04 PM PDT 24 |
Finished | Jun 27 06:23:14 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-32217abe-30c1-4423-bc88-80a8f257f56b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285622040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3285622040 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.1081592787 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 6220085492 ps |
CPU time | 7.98 seconds |
Started | Jun 27 06:23:09 PM PDT 24 |
Finished | Jun 27 06:23:26 PM PDT 24 |
Peak memory | 213384 kb |
Host | smart-2dc3ca9d-e3a2-4247-a366-5b21e3d7feb3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081592787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1081592787 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.246744434 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 63656956 ps |
CPU time | 0.78 seconds |
Started | Jun 27 06:22:56 PM PDT 24 |
Finished | Jun 27 06:23:06 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-c315e641-0f80-4894-9638-6f17162de90b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246744434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.246744434 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.3441745913 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 14895980839 ps |
CPU time | 14.51 seconds |
Started | Jun 27 06:22:57 PM PDT 24 |
Finished | Jun 27 06:23:21 PM PDT 24 |
Peak memory | 205188 kb |
Host | smart-bf8b298d-d9e6-49e5-8952-a792e5227ec0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441745913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3441745913 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.2115959828 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 189169231 ps |
CPU time | 0.82 seconds |
Started | Jun 27 06:22:57 PM PDT 24 |
Finished | Jun 27 06:23:07 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-cfc3404b-e73c-4e09-9c98-e0389f156747 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115959828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2115959828 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.4202299692 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 5361012996 ps |
CPU time | 4.61 seconds |
Started | Jun 27 06:22:56 PM PDT 24 |
Finished | Jun 27 06:23:09 PM PDT 24 |
Peak memory | 213324 kb |
Host | smart-7bc4d333-d6c5-4fc4-8cbc-0faaac4e4495 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202299692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.4202299692 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.10773836 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 41332511 ps |
CPU time | 0.76 seconds |
Started | Jun 27 06:22:54 PM PDT 24 |
Finished | Jun 27 06:23:02 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-2e0434da-b39d-4b27-8e77-e7b1fe3c16d0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10773836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.10773836 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.3978949153 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 975740175 ps |
CPU time | 3.08 seconds |
Started | Jun 27 06:22:56 PM PDT 24 |
Finished | Jun 27 06:23:08 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-9484b1b8-955d-4e53-9e9f-62241d22f754 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978949153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3978949153 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.239659910 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 65824418 ps |
CPU time | 0.74 seconds |
Started | Jun 27 06:22:56 PM PDT 24 |
Finished | Jun 27 06:23:05 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-b099349d-d0d0-4fa0-92e9-bd92ca0aeb47 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239659910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.239659910 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.1928487230 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 4635709889 ps |
CPU time | 11.79 seconds |
Started | Jun 27 06:22:51 PM PDT 24 |
Finished | Jun 27 06:23:09 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-7ac6b931-8ac1-414a-8e54-2c8546b27acc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928487230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1928487230 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.2276982521 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 52870039 ps |
CPU time | 0.76 seconds |
Started | Jun 27 06:23:04 PM PDT 24 |
Finished | Jun 27 06:23:13 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-eecddd96-be16-4d2d-97bd-212152a1e20e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276982521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2276982521 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_stress_all.3047564147 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 3058408084 ps |
CPU time | 7.95 seconds |
Started | Jun 27 06:22:51 PM PDT 24 |
Finished | Jun 27 06:23:04 PM PDT 24 |
Peak memory | 213356 kb |
Host | smart-62c3c4e3-7e95-4bf1-87d0-e003bfb965d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047564147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3047564147 |
Directory | /workspace/36.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.4136745093 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 99504255 ps |
CPU time | 0.7 seconds |
Started | Jun 27 06:23:08 PM PDT 24 |
Finished | Jun 27 06:23:17 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-a40e2224-463f-4f1a-bdd2-4831a08adae3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136745093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.4136745093 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.3991953252 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 6558146801 ps |
CPU time | 15.68 seconds |
Started | Jun 27 06:22:57 PM PDT 24 |
Finished | Jun 27 06:23:21 PM PDT 24 |
Peak memory | 205156 kb |
Host | smart-81934880-d435-4602-b76b-b54860c86112 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991953252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3991953252 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.1951577248 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 76492919 ps |
CPU time | 0.72 seconds |
Started | Jun 27 06:23:07 PM PDT 24 |
Finished | Jun 27 06:23:17 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-9145deab-ef09-46b2-81e6-e6d351cc3ae2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951577248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1951577248 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.3448477078 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 7512544220 ps |
CPU time | 20.2 seconds |
Started | Jun 27 06:23:07 PM PDT 24 |
Finished | Jun 27 06:23:37 PM PDT 24 |
Peak memory | 213312 kb |
Host | smart-46c8e468-7551-4f9f-b443-ccc7b094dbd2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448477078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3448477078 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.2545429899 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 202935665 ps |
CPU time | 0.72 seconds |
Started | Jun 27 06:23:06 PM PDT 24 |
Finished | Jun 27 06:23:16 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-aec43131-75ec-465b-9879-2a003bc296ca |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545429899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2545429899 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.1484697380 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 6277293987 ps |
CPU time | 10.62 seconds |
Started | Jun 27 06:22:51 PM PDT 24 |
Finished | Jun 27 06:23:08 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-2d51bf20-318f-4e79-bf11-d393eddad92b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484697380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1484697380 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.3015803673 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 159847224 ps |
CPU time | 0.69 seconds |
Started | Jun 27 06:22:28 PM PDT 24 |
Finished | Jun 27 06:22:30 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-af2b512f-add6-471e-bfad-f2a73d2b663a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015803673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3015803673 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3360597127 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 3756873757 ps |
CPU time | 3.6 seconds |
Started | Jun 27 06:22:30 PM PDT 24 |
Finished | Jun 27 06:22:37 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-ead93590-4e8a-4011-8e65-8a750aed722f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3360597127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3360597127 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3237699458 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 2894048417 ps |
CPU time | 2.55 seconds |
Started | Jun 27 06:22:38 PM PDT 24 |
Finished | Jun 27 06:22:48 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-48ed5584-afef-4241-b684-2ffc3abddf33 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3237699458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.3237699458 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.48607392 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 239706076 ps |
CPU time | 0.82 seconds |
Started | Jun 27 06:22:33 PM PDT 24 |
Finished | Jun 27 06:22:39 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-18c10e32-eef3-4afb-a93e-5c314e73014b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48607392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.48607392 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.2728644207 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 2016197871 ps |
CPU time | 2.81 seconds |
Started | Jun 27 06:22:37 PM PDT 24 |
Finished | Jun 27 06:22:46 PM PDT 24 |
Peak memory | 213452 kb |
Host | smart-7570e932-86e0-4540-8bd6-f01784d8be14 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2728644207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2728644207 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.113950607 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 354631301 ps |
CPU time | 1.11 seconds |
Started | Jun 27 06:22:37 PM PDT 24 |
Finished | Jun 27 06:22:44 PM PDT 24 |
Peak memory | 236436 kb |
Host | smart-866ea7bf-4f3b-457b-b67c-f36735e8e2ca |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113950607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.113950607 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all.1883983387 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 11321554683 ps |
CPU time | 11.66 seconds |
Started | Jun 27 06:22:32 PM PDT 24 |
Finished | Jun 27 06:22:49 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-5b63f578-4ca8-4f95-a266-f8d9e4ac6f03 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883983387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1883983387 |
Directory | /workspace/4.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.4121309040 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 45788120 ps |
CPU time | 0.7 seconds |
Started | Jun 27 06:22:52 PM PDT 24 |
Finished | Jun 27 06:22:59 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-2eee7baf-33c1-4356-b23f-e23692c10729 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121309040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.4121309040 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.3460957447 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 5566433105 ps |
CPU time | 7.89 seconds |
Started | Jun 27 06:22:50 PM PDT 24 |
Finished | Jun 27 06:23:04 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-9e4cd5d5-67da-40a8-988b-df3b321503c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460957447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3460957447 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.1551175751 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 138228475 ps |
CPU time | 0.98 seconds |
Started | Jun 27 06:22:53 PM PDT 24 |
Finished | Jun 27 06:22:59 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-bc7c6d06-5e67-4df8-b472-c37359b769af |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551175751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1551175751 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.2281741921 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 258341797 ps |
CPU time | 0.79 seconds |
Started | Jun 27 06:22:52 PM PDT 24 |
Finished | Jun 27 06:22:58 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-642ae960-0efb-4890-b4d7-e4bfb527c4ef |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281741921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2281741921 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.2455468349 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 1995518740 ps |
CPU time | 4.22 seconds |
Started | Jun 27 06:22:52 PM PDT 24 |
Finished | Jun 27 06:23:03 PM PDT 24 |
Peak memory | 213312 kb |
Host | smart-6d8601c7-fbb2-40d9-aa31-677645e0878d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455468349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2455468349 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.1399327380 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 137667981 ps |
CPU time | 0.71 seconds |
Started | Jun 27 06:22:53 PM PDT 24 |
Finished | Jun 27 06:23:01 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-a72e1a94-ce71-4aca-a5fa-178ea68870ef |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399327380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1399327380 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.1815768559 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 4031580559 ps |
CPU time | 5.35 seconds |
Started | Jun 27 06:23:12 PM PDT 24 |
Finished | Jun 27 06:23:26 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-c1dffa27-5c80-482c-ac2b-eb87902436ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815768559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1815768559 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.1740387918 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 85733915 ps |
CPU time | 0.78 seconds |
Started | Jun 27 06:23:02 PM PDT 24 |
Finished | Jun 27 06:23:12 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-9eff560c-8ead-4931-93a3-4fbda797076a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740387918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1740387918 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.4248315757 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 5757890216 ps |
CPU time | 9.08 seconds |
Started | Jun 27 06:22:59 PM PDT 24 |
Finished | Jun 27 06:23:17 PM PDT 24 |
Peak memory | 205132 kb |
Host | smart-3f83a06c-3fc1-4daf-88f4-fe026e88bf22 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248315757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.4248315757 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.1651937852 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 125364453 ps |
CPU time | 0.84 seconds |
Started | Jun 27 06:22:53 PM PDT 24 |
Finished | Jun 27 06:23:00 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-83de9eb5-b498-40cb-9130-2dce24c4ab61 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651937852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1651937852 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_stress_all.1735085473 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 8040064754 ps |
CPU time | 6.68 seconds |
Started | Jun 27 06:23:08 PM PDT 24 |
Finished | Jun 27 06:23:23 PM PDT 24 |
Peak memory | 213404 kb |
Host | smart-34422bb1-7c32-49ab-9761-b5a6a7459565 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735085473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1735085473 |
Directory | /workspace/45.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.2822630064 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 38288272 ps |
CPU time | 0.74 seconds |
Started | Jun 27 06:22:55 PM PDT 24 |
Finished | Jun 27 06:23:03 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-193107e8-2fe6-449e-82d0-8727041c7693 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822630064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2822630064 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.3418077810 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 6400248360 ps |
CPU time | 4.15 seconds |
Started | Jun 27 06:22:54 PM PDT 24 |
Finished | Jun 27 06:23:06 PM PDT 24 |
Peak memory | 214152 kb |
Host | smart-27a2a3c6-5ea7-4230-8d0b-d91e16e041c7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418077810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3418077810 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.2127594390 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 94300045 ps |
CPU time | 0.9 seconds |
Started | Jun 27 06:22:54 PM PDT 24 |
Finished | Jun 27 06:23:02 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-b38bde22-12c7-4b31-92f8-ac8b023d99ee |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127594390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2127594390 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_stress_all.3243088166 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 3913169836 ps |
CPU time | 10.11 seconds |
Started | Jun 27 06:22:49 PM PDT 24 |
Finished | Jun 27 06:23:03 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-a5ba0f6c-ee6a-40a2-aca4-797c729e32a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243088166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3243088166 |
Directory | /workspace/47.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.2336798 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 62069501 ps |
CPU time | 0.73 seconds |
Started | Jun 27 06:22:57 PM PDT 24 |
Finished | Jun 27 06:23:06 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-512a25fd-40d3-4096-924f-92ee35aa870c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2336798 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.39264291 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 9913727905 ps |
CPU time | 5.75 seconds |
Started | Jun 27 06:22:58 PM PDT 24 |
Finished | Jun 27 06:23:13 PM PDT 24 |
Peak memory | 213324 kb |
Host | smart-01f812cd-5573-4e17-b08a-ca88355b5b1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39264291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.39264291 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.2738702522 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 35553313 ps |
CPU time | 0.74 seconds |
Started | Jun 27 06:22:58 PM PDT 24 |
Finished | Jun 27 06:23:08 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-3e5e8656-8699-42b2-b7e3-526569eb92f8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738702522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2738702522 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.345472303 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 8988705513 ps |
CPU time | 8.23 seconds |
Started | Jun 27 06:23:03 PM PDT 24 |
Finished | Jun 27 06:23:21 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-9ca161c7-2dd4-4972-bb2a-babcc9858bb4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345472303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.345472303 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.1157402464 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 96840347 ps |
CPU time | 0.82 seconds |
Started | Jun 27 06:22:48 PM PDT 24 |
Finished | Jun 27 06:22:54 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-e8563390-9c01-423c-b519-1ac946eb4316 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157402464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1157402464 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2878032257 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 802727280 ps |
CPU time | 1.97 seconds |
Started | Jun 27 06:22:34 PM PDT 24 |
Finished | Jun 27 06:22:42 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-9bd69b26-a9ab-406a-8883-ab9c53d42f9f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878032257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2878032257 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1876985658 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 5372877477 ps |
CPU time | 4.87 seconds |
Started | Jun 27 06:22:36 PM PDT 24 |
Finished | Jun 27 06:22:47 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-9ce52a16-e59d-4215-9a38-299a45341db2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1876985658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1876985658 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1207007329 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 1931778396 ps |
CPU time | 6.07 seconds |
Started | Jun 27 06:22:32 PM PDT 24 |
Finished | Jun 27 06:22:44 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-1dd1796b-a918-49c7-b232-c4e957836fcb |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1207007329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t l_access.1207007329 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.1864368470 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 2070004705 ps |
CPU time | 2.76 seconds |
Started | Jun 27 06:22:32 PM PDT 24 |
Finished | Jun 27 06:22:40 PM PDT 24 |
Peak memory | 205256 kb |
Host | smart-815e9981-9e65-4f41-8083-127ab810ebc3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1864368470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1864368470 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.1929845124 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 12488534420 ps |
CPU time | 32.1 seconds |
Started | Jun 27 06:22:34 PM PDT 24 |
Finished | Jun 27 06:23:12 PM PDT 24 |
Peak memory | 213320 kb |
Host | smart-87f207e7-1223-4d17-991a-059f3454506d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929845124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1929845124 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.2365337785 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 45156558 ps |
CPU time | 0.74 seconds |
Started | Jun 27 06:22:45 PM PDT 24 |
Finished | Jun 27 06:22:51 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-3e53ef83-67b7-4611-a434-9aae43f72d19 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365337785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2365337785 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.143659056 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 5786265482 ps |
CPU time | 7.44 seconds |
Started | Jun 27 06:22:48 PM PDT 24 |
Finished | Jun 27 06:23:00 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-89b46003-90ac-436a-be1b-a840fb14e2de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=143659056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.143659056 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1108432549 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 2122958772 ps |
CPU time | 2.74 seconds |
Started | Jun 27 06:22:58 PM PDT 24 |
Finished | Jun 27 06:23:10 PM PDT 24 |
Peak memory | 213596 kb |
Host | smart-83d3e82d-99ee-4842-a7c8-6a8d1f3eaf60 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108432549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1108432549 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.126405323 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 11132584653 ps |
CPU time | 15.95 seconds |
Started | Jun 27 06:22:56 PM PDT 24 |
Finished | Jun 27 06:23:21 PM PDT 24 |
Peak memory | 213472 kb |
Host | smart-c66d0284-4f67-4055-a8a4-4cd7af9cb11d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=126405323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl _access.126405323 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.2616710181 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 1024106156 ps |
CPU time | 1.57 seconds |
Started | Jun 27 06:22:48 PM PDT 24 |
Finished | Jun 27 06:22:53 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-358d1277-de22-4e24-8578-d636ceb59561 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616710181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2616710181 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.3750693452 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 8069377737 ps |
CPU time | 23.3 seconds |
Started | Jun 27 06:22:56 PM PDT 24 |
Finished | Jun 27 06:23:27 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-90819214-e59c-4f1f-b20b-236c2ba5d5d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750693452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3750693452 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.394939030 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 220623353 ps |
CPU time | 0.83 seconds |
Started | Jun 27 06:22:53 PM PDT 24 |
Finished | Jun 27 06:23:00 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-24bfba21-cd3f-41b9-8264-43ed73fd7544 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394939030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.394939030 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3938203232 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 42649430555 ps |
CPU time | 101.45 seconds |
Started | Jun 27 06:22:46 PM PDT 24 |
Finished | Jun 27 06:24:32 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-b4f8d12d-8558-49b9-bfe9-741e7905a7a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3938203232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3938203232 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3912311547 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 7903092895 ps |
CPU time | 10.41 seconds |
Started | Jun 27 06:22:55 PM PDT 24 |
Finished | Jun 27 06:23:14 PM PDT 24 |
Peak memory | 213476 kb |
Host | smart-5f866382-ce49-461b-a2a1-9c71ece247b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3912311547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3912311547 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2718883038 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 4245846835 ps |
CPU time | 11.6 seconds |
Started | Jun 27 06:23:01 PM PDT 24 |
Finished | Jun 27 06:23:22 PM PDT 24 |
Peak memory | 213716 kb |
Host | smart-f55967fa-48be-451b-a3e4-df80fa879751 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2718883038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.2718883038 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.3245566649 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 2098951244 ps |
CPU time | 7.25 seconds |
Started | Jun 27 06:22:53 PM PDT 24 |
Finished | Jun 27 06:23:06 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-30edc94d-41b8-4427-a23f-40602f0b4137 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3245566649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3245566649 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.2026372599 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 8080035301 ps |
CPU time | 19.47 seconds |
Started | Jun 27 06:22:55 PM PDT 24 |
Finished | Jun 27 06:23:22 PM PDT 24 |
Peak memory | 215812 kb |
Host | smart-b3a44ced-fc53-47b6-8c84-8bf2fb0ae0c2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026372599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2026372599 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.1606855579 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 35581015 ps |
CPU time | 0.77 seconds |
Started | Jun 27 06:22:51 PM PDT 24 |
Finished | Jun 27 06:22:58 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-1a055a15-83d1-41bb-b36c-db4dbd76b59d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606855579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1606855579 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3885172489 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 17609433328 ps |
CPU time | 23.6 seconds |
Started | Jun 27 06:22:46 PM PDT 24 |
Finished | Jun 27 06:23:14 PM PDT 24 |
Peak memory | 213480 kb |
Host | smart-667e3c9c-4631-4f58-9f6f-51fa9fc4b2fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885172489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3885172489 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3959204892 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 6946937474 ps |
CPU time | 11.85 seconds |
Started | Jun 27 06:22:50 PM PDT 24 |
Finished | Jun 27 06:23:08 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-2416b8a7-27ae-4b88-b813-3b8b04ceb65f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3959204892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3959204892 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3189494257 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 7134869496 ps |
CPU time | 21.87 seconds |
Started | Jun 27 06:22:47 PM PDT 24 |
Finished | Jun 27 06:23:13 PM PDT 24 |
Peak memory | 213488 kb |
Host | smart-bdb8b00c-d523-4e7f-a7e4-95c62eb15348 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3189494257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t l_access.3189494257 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.3751924549 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 9078615628 ps |
CPU time | 24.7 seconds |
Started | Jun 27 06:23:07 PM PDT 24 |
Finished | Jun 27 06:23:41 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-08a9c3d7-7499-4da9-918c-acc5c27dc31a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3751924549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3751924549 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.1982332069 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 4589674409 ps |
CPU time | 14.87 seconds |
Started | Jun 27 06:22:48 PM PDT 24 |
Finished | Jun 27 06:23:08 PM PDT 24 |
Peak memory | 213304 kb |
Host | smart-cb975d00-1496-4e14-bce5-c6dbe5b86f7c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982332069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.1982332069 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.2178089218 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 85198723 ps |
CPU time | 0.8 seconds |
Started | Jun 27 06:22:55 PM PDT 24 |
Finished | Jun 27 06:23:04 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-ad3f2121-97ab-44f8-b782-ab7aabe4dc3b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178089218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2178089218 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.409001511 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 14693869585 ps |
CPU time | 23.24 seconds |
Started | Jun 27 06:22:55 PM PDT 24 |
Finished | Jun 27 06:23:26 PM PDT 24 |
Peak memory | 213544 kb |
Host | smart-2bd041ad-9b19-4255-8119-971c6d0b8941 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=409001511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.409001511 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1348083214 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 3829100990 ps |
CPU time | 10.22 seconds |
Started | Jun 27 06:22:51 PM PDT 24 |
Finished | Jun 27 06:23:07 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-bc83a545-9801-4854-b239-4b779b514916 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348083214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1348083214 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2219059605 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 7497824267 ps |
CPU time | 2.02 seconds |
Started | Jun 27 06:22:57 PM PDT 24 |
Finished | Jun 27 06:23:07 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-a64a3167-8927-495a-b452-6bf263e607a9 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2219059605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.2219059605 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.2237904624 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 2812174796 ps |
CPU time | 4.22 seconds |
Started | Jun 27 06:22:54 PM PDT 24 |
Finished | Jun 27 06:23:06 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-a9cb797d-df22-46af-b931-dd6f50226de8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2237904624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2237904624 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |