Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.82 95.27 79.45 89.42 74.36 85.50 98.42 57.31


Total test records in report: 442
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T88 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3177539657 Jun 28 07:15:55 PM PDT 24 Jun 28 07:16:34 PM PDT 24 908216684 ps
T94 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4109089041 Jun 28 07:17:14 PM PDT 24 Jun 28 07:17:32 PM PDT 24 1212365539 ps
T105 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1147431330 Jun 28 07:15:14 PM PDT 24 Jun 28 07:15:59 PM PDT 24 7175302977 ps
T95 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1679777795 Jun 28 07:18:18 PM PDT 24 Jun 28 07:18:30 PM PDT 24 116518896 ps
T135 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3526743148 Jun 28 07:16:43 PM PDT 24 Jun 28 07:17:09 PM PDT 24 8881683838 ps
T136 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1686010149 Jun 28 07:16:12 PM PDT 24 Jun 28 07:17:07 PM PDT 24 4616883935 ps
T301 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.4101664720 Jun 28 07:16:44 PM PDT 24 Jun 28 07:17:04 PM PDT 24 3204114030 ps
T99 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2587942531 Jun 28 07:18:19 PM PDT 24 Jun 28 07:18:35 PM PDT 24 588750905 ps
T100 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3383380123 Jun 28 07:17:13 PM PDT 24 Jun 28 07:17:33 PM PDT 24 624239043 ps
T302 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3628736185 Jun 28 07:14:58 PM PDT 24 Jun 28 07:15:35 PM PDT 24 990595054 ps
T101 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1525899347 Jun 28 07:17:13 PM PDT 24 Jun 28 07:17:32 PM PDT 24 178889032 ps
T303 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.993705719 Jun 28 07:15:40 PM PDT 24 Jun 28 07:21:16 PM PDT 24 121026560114 ps
T304 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3266599058 Jun 28 07:17:12 PM PDT 24 Jun 28 07:17:27 PM PDT 24 428593004 ps
T106 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3024538076 Jun 28 07:14:41 PM PDT 24 Jun 28 07:15:27 PM PDT 24 7501965591 ps
T168 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.66746568 Jun 28 07:16:14 PM PDT 24 Jun 28 07:16:43 PM PDT 24 245309471 ps
T305 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1702371342 Jun 28 07:15:16 PM PDT 24 Jun 28 07:15:54 PM PDT 24 1158720629 ps
T306 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2587521185 Jun 28 07:15:14 PM PDT 24 Jun 28 07:16:52 PM PDT 24 25910239617 ps
T102 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.206964606 Jun 28 07:16:45 PM PDT 24 Jun 28 07:17:06 PM PDT 24 948836867 ps
T108 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4088953449 Jun 28 07:17:15 PM PDT 24 Jun 28 07:17:30 PM PDT 24 67349573 ps
T307 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3438190810 Jun 28 07:18:17 PM PDT 24 Jun 28 07:18:35 PM PDT 24 4471621161 ps
T308 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4030904773 Jun 28 07:15:16 PM PDT 24 Jun 28 07:15:53 PM PDT 24 131334996 ps
T107 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.155034125 Jun 28 07:16:15 PM PDT 24 Jun 28 07:16:48 PM PDT 24 1901933995 ps
T309 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1191822943 Jun 28 07:16:45 PM PDT 24 Jun 28 07:17:36 PM PDT 24 14249056663 ps
T310 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3568841439 Jun 28 07:18:18 PM PDT 24 Jun 28 07:18:29 PM PDT 24 118089523 ps
T130 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.590029942 Jun 28 07:16:47 PM PDT 24 Jun 28 07:17:06 PM PDT 24 2114247928 ps
T311 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1413144756 Jun 28 07:14:59 PM PDT 24 Jun 28 07:15:55 PM PDT 24 7578341430 ps
T109 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3810396102 Jun 28 07:14:42 PM PDT 24 Jun 28 07:16:17 PM PDT 24 11838633005 ps
T312 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.546586059 Jun 28 07:18:18 PM PDT 24 Jun 28 07:19:14 PM PDT 24 16888668008 ps
T131 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1066028213 Jun 28 07:17:12 PM PDT 24 Jun 28 07:17:35 PM PDT 24 1087803388 ps
T61 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3793031756 Jun 28 07:16:13 PM PDT 24 Jun 28 07:17:48 PM PDT 24 42045124561 ps
T313 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2288724187 Jun 28 07:17:12 PM PDT 24 Jun 28 07:17:27 PM PDT 24 387835565 ps
T137 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.358342936 Jun 28 07:17:12 PM PDT 24 Jun 28 07:17:29 PM PDT 24 2596312784 ps
T171 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2924449705 Jun 28 07:18:18 PM PDT 24 Jun 28 07:18:37 PM PDT 24 2136737650 ps
T173 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1846143130 Jun 28 07:16:43 PM PDT 24 Jun 28 07:17:18 PM PDT 24 7884490773 ps
T314 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2868607629 Jun 28 07:14:59 PM PDT 24 Jun 28 07:15:37 PM PDT 24 388758911 ps
T138 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.702869860 Jun 28 07:16:44 PM PDT 24 Jun 28 07:17:04 PM PDT 24 911966678 ps
T110 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2589438125 Jun 28 07:16:44 PM PDT 24 Jun 28 07:17:00 PM PDT 24 105783400 ps
T315 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1835442642 Jun 28 07:16:46 PM PDT 24 Jun 28 07:17:04 PM PDT 24 3440897170 ps
T111 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1509587581 Jun 28 07:15:14 PM PDT 24 Jun 28 07:15:49 PM PDT 24 198550459 ps
T316 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1477184774 Jun 28 07:15:54 PM PDT 24 Jun 28 07:16:34 PM PDT 24 4129304183 ps
T317 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1564137328 Jun 28 07:17:14 PM PDT 24 Jun 28 07:17:29 PM PDT 24 120586819 ps
T176 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1253680798 Jun 28 07:16:44 PM PDT 24 Jun 28 07:17:46 PM PDT 24 61187154912 ps
T318 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1724638321 Jun 28 07:17:10 PM PDT 24 Jun 28 07:17:28 PM PDT 24 252660771 ps
T319 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1020857815 Jun 28 07:14:40 PM PDT 24 Jun 28 07:15:25 PM PDT 24 26066069474 ps
T320 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1092635142 Jun 28 07:16:12 PM PDT 24 Jun 28 07:16:56 PM PDT 24 14419463705 ps
T321 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4242719531 Jun 28 07:15:19 PM PDT 24 Jun 28 07:15:56 PM PDT 24 168062413 ps
T139 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2323158843 Jun 28 07:15:55 PM PDT 24 Jun 28 07:17:30 PM PDT 24 74052883565 ps
T322 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3257945038 Jun 28 07:16:46 PM PDT 24 Jun 28 07:18:13 PM PDT 24 46477098533 ps
T323 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.312753847 Jun 28 07:18:17 PM PDT 24 Jun 28 07:18:29 PM PDT 24 212400436 ps
T324 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3530671425 Jun 28 07:17:14 PM PDT 24 Jun 28 07:17:31 PM PDT 24 87061751 ps
T325 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1759851928 Jun 28 07:17:11 PM PDT 24 Jun 28 07:17:27 PM PDT 24 1811516001 ps
T326 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3861182325 Jun 28 07:17:13 PM PDT 24 Jun 28 07:17:31 PM PDT 24 316085782 ps
T140 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3191339580 Jun 28 07:18:18 PM PDT 24 Jun 28 07:18:35 PM PDT 24 535110472 ps
T327 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.339425939 Jun 28 07:15:42 PM PDT 24 Jun 28 07:16:19 PM PDT 24 664329121 ps
T328 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3877166515 Jun 28 07:16:12 PM PDT 24 Jun 28 07:16:41 PM PDT 24 138007196 ps
T329 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2385163337 Jun 28 07:18:19 PM PDT 24 Jun 28 07:19:46 PM PDT 24 30328399365 ps
T112 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4088011795 Jun 28 07:15:55 PM PDT 24 Jun 28 07:16:33 PM PDT 24 289557726 ps
T330 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3137709012 Jun 28 07:17:13 PM PDT 24 Jun 28 07:17:46 PM PDT 24 26322846582 ps
T113 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.467820751 Jun 28 07:14:58 PM PDT 24 Jun 28 07:16:29 PM PDT 24 17629526609 ps
T331 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1771804624 Jun 28 07:14:59 PM PDT 24 Jun 28 07:15:36 PM PDT 24 2884250585 ps
T332 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1184706057 Jun 28 07:16:20 PM PDT 24 Jun 28 07:16:47 PM PDT 24 84039134 ps
T333 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1249347863 Jun 28 07:18:17 PM PDT 24 Jun 28 07:18:34 PM PDT 24 4594231515 ps
T114 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3311028249 Jun 28 07:16:14 PM PDT 24 Jun 28 07:17:52 PM PDT 24 6508983536 ps
T334 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4254433986 Jun 28 07:14:58 PM PDT 24 Jun 28 07:15:35 PM PDT 24 102220880 ps
T335 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3570205514 Jun 28 07:16:43 PM PDT 24 Jun 28 07:17:23 PM PDT 24 13832368875 ps
T336 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1844192707 Jun 28 07:14:41 PM PDT 24 Jun 28 07:15:12 PM PDT 24 1637071784 ps
T337 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2438091156 Jun 28 07:15:53 PM PDT 24 Jun 28 07:16:30 PM PDT 24 90794758 ps
T338 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.682596097 Jun 28 07:15:53 PM PDT 24 Jun 28 07:16:30 PM PDT 24 80006552 ps
T339 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3498324175 Jun 28 07:16:44 PM PDT 24 Jun 28 07:17:01 PM PDT 24 3371654718 ps
T340 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3959427600 Jun 28 07:14:39 PM PDT 24 Jun 28 07:15:07 PM PDT 24 1389257009 ps
T169 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.625610876 Jun 28 07:17:14 PM PDT 24 Jun 28 07:17:41 PM PDT 24 8969617052 ps
T341 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4057265164 Jun 28 07:17:12 PM PDT 24 Jun 28 07:17:33 PM PDT 24 1997288430 ps
T342 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3827819554 Jun 28 07:16:45 PM PDT 24 Jun 28 07:17:16 PM PDT 24 7120470629 ps
T343 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.298471032 Jun 28 07:16:46 PM PDT 24 Jun 28 07:16:59 PM PDT 24 324205893 ps
T344 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3611993275 Jun 28 07:14:58 PM PDT 24 Jun 28 07:15:34 PM PDT 24 213269293 ps
T345 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2726994612 Jun 28 07:16:46 PM PDT 24 Jun 28 07:17:08 PM PDT 24 1092422048 ps
T122 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.759456 Jun 28 07:15:16 PM PDT 24 Jun 28 07:16:44 PM PDT 24 5015794358 ps
T346 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1696976530 Jun 28 07:17:16 PM PDT 24 Jun 28 07:17:33 PM PDT 24 1684693642 ps
T347 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.377293827 Jun 28 07:15:15 PM PDT 24 Jun 28 07:16:17 PM PDT 24 12202707752 ps
T348 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3341632747 Jun 28 07:18:18 PM PDT 24 Jun 28 07:18:30 PM PDT 24 287279818 ps
T349 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.217136997 Jun 28 07:18:18 PM PDT 24 Jun 28 07:18:31 PM PDT 24 499255694 ps
T350 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3824204241 Jun 28 07:15:15 PM PDT 24 Jun 28 07:15:50 PM PDT 24 318833779 ps
T351 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4097255038 Jun 28 07:16:44 PM PDT 24 Jun 28 07:18:25 PM PDT 24 79524285571 ps
T352 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3706108562 Jun 28 07:17:11 PM PDT 24 Jun 28 07:17:30 PM PDT 24 13271871734 ps
T123 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3201914088 Jun 28 07:18:18 PM PDT 24 Jun 28 07:18:30 PM PDT 24 438135472 ps
T353 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.134892987 Jun 28 07:14:39 PM PDT 24 Jun 28 07:15:09 PM PDT 24 3721422080 ps
T354 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1761422983 Jun 28 07:15:01 PM PDT 24 Jun 28 07:15:39 PM PDT 24 277776027 ps
T355 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2877100074 Jun 28 07:16:16 PM PDT 24 Jun 28 07:16:47 PM PDT 24 1694904037 ps
T356 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3603706618 Jun 28 07:16:44 PM PDT 24 Jun 28 07:17:11 PM PDT 24 1236619064 ps
T357 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.500494531 Jun 28 07:17:12 PM PDT 24 Jun 28 07:17:30 PM PDT 24 2055888120 ps
T358 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3914148607 Jun 28 07:16:14 PM PDT 24 Jun 28 07:16:49 PM PDT 24 6093613356 ps
T359 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3354269526 Jun 28 07:16:13 PM PDT 24 Jun 28 07:16:44 PM PDT 24 2194032591 ps
T360 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1292653618 Jun 28 07:16:14 PM PDT 24 Jun 28 07:17:32 PM PDT 24 19421651433 ps
T361 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1558539106 Jun 28 07:14:41 PM PDT 24 Jun 28 07:15:10 PM PDT 24 69988819 ps
T362 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1221454065 Jun 28 07:18:19 PM PDT 24 Jun 28 07:18:34 PM PDT 24 425675660 ps
T363 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1598558426 Jun 28 07:18:19 PM PDT 24 Jun 28 07:18:41 PM PDT 24 7709433907 ps
T124 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2155958895 Jun 28 07:16:44 PM PDT 24 Jun 28 07:17:00 PM PDT 24 53563994 ps
T364 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.226656731 Jun 28 07:14:42 PM PDT 24 Jun 28 07:15:13 PM PDT 24 341956706 ps
T365 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2946863891 Jun 28 07:17:11 PM PDT 24 Jun 28 07:17:35 PM PDT 24 12745032743 ps
T366 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3137038619 Jun 28 07:16:46 PM PDT 24 Jun 28 07:16:59 PM PDT 24 270410388 ps
T174 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2040226487 Jun 28 07:15:54 PM PDT 24 Jun 28 07:16:51 PM PDT 24 2213750525 ps
T367 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4247464681 Jun 28 07:16:13 PM PDT 24 Jun 28 07:16:43 PM PDT 24 204992986 ps
T368 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.419194832 Jun 28 07:17:12 PM PDT 24 Jun 28 07:17:28 PM PDT 24 1397841209 ps
T170 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3126951043 Jun 28 07:18:16 PM PDT 24 Jun 28 07:18:36 PM PDT 24 2458199692 ps
T369 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3518495078 Jun 28 07:14:58 PM PDT 24 Jun 28 07:15:52 PM PDT 24 31445023519 ps
T115 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3936614109 Jun 28 07:14:59 PM PDT 24 Jun 28 07:15:40 PM PDT 24 249607187 ps
T370 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1092969354 Jun 28 07:14:39 PM PDT 24 Jun 28 07:15:05 PM PDT 24 133471340 ps
T371 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.788935958 Jun 28 07:15:15 PM PDT 24 Jun 28 07:15:52 PM PDT 24 1994281045 ps
T372 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2329542836 Jun 28 07:16:15 PM PDT 24 Jun 28 07:16:45 PM PDT 24 1293193375 ps
T373 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1740908676 Jun 28 07:17:10 PM PDT 24 Jun 28 07:17:56 PM PDT 24 17027257536 ps
T374 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1704836063 Jun 28 07:18:17 PM PDT 24 Jun 28 07:18:38 PM PDT 24 2553178236 ps
T375 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.912445774 Jun 28 07:16:44 PM PDT 24 Jun 28 07:16:59 PM PDT 24 323687342 ps
T376 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1430512652 Jun 28 07:18:17 PM PDT 24 Jun 28 07:18:32 PM PDT 24 1072274748 ps
T116 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1031918265 Jun 28 07:15:16 PM PDT 24 Jun 28 07:15:56 PM PDT 24 238584278 ps
T377 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.966862311 Jun 28 07:15:14 PM PDT 24 Jun 28 07:16:21 PM PDT 24 2478633284 ps
T378 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3004119085 Jun 28 07:16:13 PM PDT 24 Jun 28 07:16:45 PM PDT 24 1486039008 ps
T379 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4154044969 Jun 28 07:18:17 PM PDT 24 Jun 28 07:18:31 PM PDT 24 307820137 ps
T380 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.662700011 Jun 28 07:15:00 PM PDT 24 Jun 28 07:15:41 PM PDT 24 1468237530 ps
T381 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3721283511 Jun 28 07:16:12 PM PDT 24 Jun 28 07:16:53 PM PDT 24 4574798826 ps
T117 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.356879186 Jun 28 07:15:56 PM PDT 24 Jun 28 07:17:45 PM PDT 24 6938099797 ps
T382 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1898499088 Jun 28 07:14:39 PM PDT 24 Jun 28 07:15:06 PM PDT 24 259082038 ps
T125 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3939690778 Jun 28 07:16:15 PM PDT 24 Jun 28 07:16:45 PM PDT 24 209535426 ps
T383 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1989389376 Jun 28 07:17:13 PM PDT 24 Jun 28 07:17:29 PM PDT 24 1792090027 ps
T384 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2353804153 Jun 28 07:17:12 PM PDT 24 Jun 28 07:17:27 PM PDT 24 569047986 ps
T127 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2361774966 Jun 28 07:17:12 PM PDT 24 Jun 28 07:17:28 PM PDT 24 259436665 ps
T385 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1273214333 Jun 28 07:15:15 PM PDT 24 Jun 28 07:15:54 PM PDT 24 5543907543 ps
T386 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2880753102 Jun 28 07:18:18 PM PDT 24 Jun 28 07:18:29 PM PDT 24 100239859 ps
T387 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2122610851 Jun 28 07:14:59 PM PDT 24 Jun 28 07:15:39 PM PDT 24 482914343 ps
T175 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2260733861 Jun 28 07:17:15 PM PDT 24 Jun 28 07:17:40 PM PDT 24 1243554269 ps
T388 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1101013271 Jun 28 07:15:42 PM PDT 24 Jun 28 07:16:19 PM PDT 24 665269691 ps
T389 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2116327364 Jun 28 07:18:17 PM PDT 24 Jun 28 07:18:29 PM PDT 24 564200710 ps
T390 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2245503011 Jun 28 07:15:41 PM PDT 24 Jun 28 07:16:22 PM PDT 24 2375160746 ps
T391 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.301485975 Jun 28 07:18:17 PM PDT 24 Jun 28 07:18:36 PM PDT 24 602931814 ps
T128 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4260185080 Jun 28 07:18:17 PM PDT 24 Jun 28 07:18:30 PM PDT 24 183499183 ps
T392 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1889043103 Jun 28 07:16:15 PM PDT 24 Jun 28 07:16:48 PM PDT 24 423896646 ps
T393 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1244313283 Jun 28 07:14:57 PM PDT 24 Jun 28 07:15:51 PM PDT 24 26796722530 ps
T394 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2335919012 Jun 28 07:16:12 PM PDT 24 Jun 28 07:16:47 PM PDT 24 320890603 ps
T395 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1516146714 Jun 28 07:18:16 PM PDT 24 Jun 28 07:18:31 PM PDT 24 1468632605 ps
T396 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.554697055 Jun 28 07:15:16 PM PDT 24 Jun 28 07:15:53 PM PDT 24 171040022 ps
T397 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1250550124 Jun 28 07:18:16 PM PDT 24 Jun 28 07:18:28 PM PDT 24 2457536495 ps
T398 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.547291837 Jun 28 07:17:11 PM PDT 24 Jun 28 07:17:29 PM PDT 24 1916469292 ps
T118 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.4177181537 Jun 28 07:16:12 PM PDT 24 Jun 28 07:16:45 PM PDT 24 297904592 ps
T399 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3157239647 Jun 28 07:16:13 PM PDT 24 Jun 28 07:18:50 PM PDT 24 40220396302 ps
T400 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.910267255 Jun 28 07:17:13 PM PDT 24 Jun 28 07:17:33 PM PDT 24 6598685708 ps
T401 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1018677018 Jun 28 07:15:42 PM PDT 24 Jun 28 07:16:18 PM PDT 24 632061436 ps
T402 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3049773616 Jun 28 07:18:17 PM PDT 24 Jun 28 07:18:30 PM PDT 24 1081848184 ps
T403 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.156975801 Jun 28 07:15:19 PM PDT 24 Jun 28 07:15:57 PM PDT 24 246458600 ps
T404 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2463242335 Jun 28 07:17:15 PM PDT 24 Jun 28 07:17:38 PM PDT 24 993070784 ps
T129 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3275094460 Jun 28 07:16:46 PM PDT 24 Jun 28 07:17:01 PM PDT 24 204638559 ps
T405 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.985720911 Jun 28 07:16:19 PM PDT 24 Jun 28 07:16:48 PM PDT 24 512502127 ps
T406 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.459550327 Jun 28 07:15:41 PM PDT 24 Jun 28 07:16:21 PM PDT 24 2869307259 ps
T407 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3394462639 Jun 28 07:17:12 PM PDT 24 Jun 28 07:17:35 PM PDT 24 2145982685 ps
T408 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4099952816 Jun 28 07:18:18 PM PDT 24 Jun 28 07:18:30 PM PDT 24 319081948 ps
T409 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2928715118 Jun 28 07:16:47 PM PDT 24 Jun 28 07:17:03 PM PDT 24 559586486 ps
T410 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.631540871 Jun 28 07:14:58 PM PDT 24 Jun 28 07:18:25 PM PDT 24 60805627202 ps
T119 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4123464670 Jun 28 07:18:18 PM PDT 24 Jun 28 07:18:32 PM PDT 24 3301377042 ps
T411 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3840413952 Jun 28 07:18:19 PM PDT 24 Jun 28 07:18:31 PM PDT 24 621795004 ps
T120 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2978857329 Jun 28 07:16:43 PM PDT 24 Jun 28 07:17:04 PM PDT 24 237528545 ps
T412 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1447915353 Jun 28 07:16:46 PM PDT 24 Jun 28 07:17:01 PM PDT 24 314538496 ps
T413 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.4251394469 Jun 28 07:14:40 PM PDT 24 Jun 28 07:15:35 PM PDT 24 19600644128 ps
T414 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3125910708 Jun 28 07:16:20 PM PDT 24 Jun 28 07:17:00 PM PDT 24 3713421790 ps
T415 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.4239343075 Jun 28 07:16:15 PM PDT 24 Jun 28 07:16:50 PM PDT 24 977216681 ps
T416 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2834521506 Jun 28 07:16:19 PM PDT 24 Jun 28 07:16:48 PM PDT 24 178866913 ps
T417 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2313892013 Jun 28 07:16:45 PM PDT 24 Jun 28 07:17:00 PM PDT 24 321791954 ps
T418 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1846461913 Jun 28 07:17:15 PM PDT 24 Jun 28 07:17:31 PM PDT 24 209419859 ps
T419 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3927587287 Jun 28 07:15:15 PM PDT 24 Jun 28 07:16:41 PM PDT 24 31028590605 ps
T420 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1278801550 Jun 28 07:17:13 PM PDT 24 Jun 28 07:18:34 PM PDT 24 101723981001 ps
T421 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.558083305 Jun 28 07:14:41 PM PDT 24 Jun 28 07:15:11 PM PDT 24 1412422291 ps
T121 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1022825363 Jun 28 07:15:19 PM PDT 24 Jun 28 07:16:25 PM PDT 24 5540835486 ps
T422 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1303962467 Jun 28 07:14:43 PM PDT 24 Jun 28 07:16:09 PM PDT 24 36659926799 ps
T423 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2344459131 Jun 28 07:15:00 PM PDT 24 Jun 28 07:16:09 PM PDT 24 3358229776 ps
T424 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3097446900 Jun 28 07:14:57 PM PDT 24 Jun 28 07:15:35 PM PDT 24 114729657 ps
T425 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3941436151 Jun 28 07:18:17 PM PDT 24 Jun 28 07:18:29 PM PDT 24 153524401 ps
T426 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.865245110 Jun 28 07:15:41 PM PDT 24 Jun 28 07:16:21 PM PDT 24 5469115201 ps
T427 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1968410636 Jun 28 07:15:40 PM PDT 24 Jun 28 07:17:38 PM PDT 24 31968770128 ps
T428 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2204552985 Jun 28 07:17:12 PM PDT 24 Jun 28 07:17:29 PM PDT 24 1200670669 ps
T429 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.411031693 Jun 28 07:15:00 PM PDT 24 Jun 28 07:15:38 PM PDT 24 761469789 ps
T430 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2498775846 Jun 28 07:15:55 PM PDT 24 Jun 28 07:16:32 PM PDT 24 349498243 ps
T431 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3396175612 Jun 28 07:14:58 PM PDT 24 Jun 28 07:15:35 PM PDT 24 50075272 ps
T432 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1741476270 Jun 28 07:15:17 PM PDT 24 Jun 28 07:15:58 PM PDT 24 138864748 ps
T433 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1063164191 Jun 28 07:16:43 PM PDT 24 Jun 28 07:17:00 PM PDT 24 190535986 ps
T434 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2565463179 Jun 28 07:15:55 PM PDT 24 Jun 28 07:17:09 PM PDT 24 3827123561 ps
T435 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.223344475 Jun 28 07:15:01 PM PDT 24 Jun 28 07:15:58 PM PDT 24 7974862357 ps
T436 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.557454247 Jun 28 07:14:58 PM PDT 24 Jun 28 07:15:37 PM PDT 24 400114589 ps
T437 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1825641652 Jun 28 07:14:57 PM PDT 24 Jun 28 07:16:13 PM PDT 24 23843583324 ps
T438 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1679182705 Jun 28 07:16:14 PM PDT 24 Jun 28 07:17:23 PM PDT 24 14965822588 ps
T439 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2592458965 Jun 28 07:14:39 PM PDT 24 Jun 28 07:15:16 PM PDT 24 2328643575 ps
T172 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.209569294 Jun 28 07:17:11 PM PDT 24 Jun 28 07:17:40 PM PDT 24 2424034479 ps
T440 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.739519711 Jun 28 07:16:44 PM PDT 24 Jun 28 07:16:59 PM PDT 24 99421709 ps
T441 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3254900094 Jun 28 07:15:54 PM PDT 24 Jun 28 07:16:35 PM PDT 24 389034460 ps
T442 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3159193183 Jun 28 07:15:15 PM PDT 24 Jun 28 07:15:51 PM PDT 24 113561140 ps
T126 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3283737387 Jun 28 07:15:41 PM PDT 24 Jun 28 07:17:21 PM PDT 24 1600803946 ps

Test location /workspace/coverage/default/25.rv_dm_stress_all.41786217
Short name T4
Test name
Test status
Simulation time 10320504945 ps
CPU time 13.67 seconds
Started Jun 28 07:25:02 PM PDT 24
Finished Jun 28 07:25:20 PM PDT 24
Peak memory 213352 kb
Host smart-e88d36df-6ba5-4d9c-b90a-7028de49ff51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41786217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.41786217
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3958086942
Short name T7
Test name
Test status
Simulation time 35823028043 ps
CPU time 27.08 seconds
Started Jun 28 07:24:16 PM PDT 24
Finished Jun 28 07:24:57 PM PDT 24
Peak memory 213556 kb
Host smart-c81fe1dd-2a38-43f5-a12d-4dbca4e890b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958086942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3958086942
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4251275925
Short name T69
Test name
Test status
Simulation time 2949854182 ps
CPU time 6.56 seconds
Started Jun 28 07:18:16 PM PDT 24
Finished Jun 28 07:18:33 PM PDT 24
Peak memory 219920 kb
Host smart-07279a39-869d-4635-9e13-e2998a30e35b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251275925 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.4251275925
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1253680798
Short name T176
Test name
Test status
Simulation time 61187154912 ps
CPU time 47.54 seconds
Started Jun 28 07:16:44 PM PDT 24
Finished Jun 28 07:17:46 PM PDT 24
Peak memory 222872 kb
Host smart-3ad4da83-1a04-484a-afba-3f0f0bb29e3b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253680798 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1253680798
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.1953374394
Short name T9
Test name
Test status
Simulation time 9266007984 ps
CPU time 26.52 seconds
Started Jun 28 07:24:31 PM PDT 24
Finished Jun 28 07:25:07 PM PDT 24
Peak memory 213416 kb
Host smart-55ee9580-2516-465d-b859-7e7c9ae8aa6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953374394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1953374394
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1633913349
Short name T91
Test name
Test status
Simulation time 3015950308 ps
CPU time 19.48 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:18:48 PM PDT 24
Peak memory 213368 kb
Host smart-9046734a-8fab-498b-9963-a1004766f661
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633913349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
633913349
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3478141404
Short name T68
Test name
Test status
Simulation time 255476108 ps
CPU time 0.76 seconds
Started Jun 28 07:25:33 PM PDT 24
Finished Jun 28 07:25:39 PM PDT 24
Peak memory 204896 kb
Host smart-1c1c7c16-0358-4b28-9c8c-345ea01a56a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478141404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3478141404
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.3196660672
Short name T36
Test name
Test status
Simulation time 157241739 ps
CPU time 0.94 seconds
Started Jun 28 07:23:28 PM PDT 24
Finished Jun 28 07:23:32 PM PDT 24
Peak memory 215496 kb
Host smart-23a44bd1-c601-45cf-8a69-bc6e61c6707c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196660672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3196660672
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2735372735
Short name T18
Test name
Test status
Simulation time 5733686039 ps
CPU time 4.62 seconds
Started Jun 28 07:23:59 PM PDT 24
Finished Jun 28 07:24:07 PM PDT 24
Peak memory 205188 kb
Host smart-8c1469c3-f7d0-4c25-910f-7320a896d37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735372735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2735372735
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3810396102
Short name T109
Test name
Test status
Simulation time 11838633005 ps
CPU time 64.72 seconds
Started Jun 28 07:14:42 PM PDT 24
Finished Jun 28 07:16:17 PM PDT 24
Peak memory 213312 kb
Host smart-d58556e5-838a-4fd2-8e8c-0fa9ac437e98
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810396102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3810396102
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1686010149
Short name T136
Test name
Test status
Simulation time 4616883935 ps
CPU time 27.52 seconds
Started Jun 28 07:16:12 PM PDT 24
Finished Jun 28 07:17:07 PM PDT 24
Peak memory 213376 kb
Host smart-ac4eb547-4ca5-4412-9f0d-0ac82b5ef642
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686010149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1686010149
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.1633306715
Short name T146
Test name
Test status
Simulation time 4700904554 ps
CPU time 3.58 seconds
Started Jun 28 07:25:13 PM PDT 24
Finished Jun 28 07:25:18 PM PDT 24
Peak memory 213356 kb
Host smart-2f9f6a65-6f1f-40c0-91cf-f3181a8c4465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633306715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1633306715
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1222201279
Short name T210
Test name
Test status
Simulation time 23339281042 ps
CPU time 67.49 seconds
Started Jun 28 07:24:58 PM PDT 24
Finished Jun 28 07:26:10 PM PDT 24
Peak memory 213496 kb
Host smart-613446f1-01b1-482a-a388-42501759e73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222201279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1222201279
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.2138649108
Short name T55
Test name
Test status
Simulation time 87789541 ps
CPU time 0.95 seconds
Started Jun 28 07:23:29 PM PDT 24
Finished Jun 28 07:23:33 PM PDT 24
Peak memory 204856 kb
Host smart-0b9f2e9b-abb5-47a1-a8cd-5a84beca746c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138649108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2138649108
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3293591919
Short name T64
Test name
Test status
Simulation time 355564974 ps
CPU time 2.11 seconds
Started Jun 28 07:24:18 PM PDT 24
Finished Jun 28 07:24:34 PM PDT 24
Peak memory 237140 kb
Host smart-5c666e6a-b6cc-429a-bd21-4c6ac3770953
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293591919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3293591919
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.663298520
Short name T16
Test name
Test status
Simulation time 5170190627 ps
CPU time 13.36 seconds
Started Jun 28 07:25:01 PM PDT 24
Finished Jun 28 07:25:19 PM PDT 24
Peak memory 205332 kb
Host smart-9c5a5235-f252-4ac1-9291-bec12c369d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663298520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.663298520
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3838078119
Short name T20
Test name
Test status
Simulation time 985826654 ps
CPU time 1.41 seconds
Started Jun 28 07:24:00 PM PDT 24
Finished Jun 28 07:24:06 PM PDT 24
Peak memory 204896 kb
Host smart-7116a7b6-0383-46f0-bd7d-34669208d1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838078119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3838078119
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2156301389
Short name T80
Test name
Test status
Simulation time 2539391110 ps
CPU time 3.31 seconds
Started Jun 28 07:24:38 PM PDT 24
Finished Jun 28 07:24:47 PM PDT 24
Peak memory 205276 kb
Host smart-c47e782a-8b4d-42e3-a982-9dda79b6113a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156301389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2156301389
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.393428763
Short name T54
Test name
Test status
Simulation time 191562271 ps
CPU time 0.81 seconds
Started Jun 28 07:23:32 PM PDT 24
Finished Jun 28 07:23:39 PM PDT 24
Peak memory 213196 kb
Host smart-dc355cef-cd71-45bc-9af7-05997e50c8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393428763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.393428763
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3126951043
Short name T170
Test name
Test status
Simulation time 2458199692 ps
CPU time 9.77 seconds
Started Jun 28 07:18:16 PM PDT 24
Finished Jun 28 07:18:36 PM PDT 24
Peak memory 213356 kb
Host smart-9b1dc58b-2b16-40a4-8b13-d6d768a67c30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126951043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
126951043
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2897841542
Short name T142
Test name
Test status
Simulation time 2219688474 ps
CPU time 4 seconds
Started Jun 28 07:24:44 PM PDT 24
Finished Jun 28 07:24:50 PM PDT 24
Peak memory 213552 kb
Host smart-2e7b5677-45df-44db-9cb4-fca956a2b320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897841542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2897841542
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.64937875
Short name T96
Test name
Test status
Simulation time 327754980 ps
CPU time 4.25 seconds
Started Jun 28 07:17:11 PM PDT 24
Finished Jun 28 07:17:30 PM PDT 24
Peak memory 205000 kb
Host smart-01231691-edd7-4630-a9d6-ef501b6c1adf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64937875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_c
sr_outstanding.64937875
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3177539657
Short name T88
Test name
Test status
Simulation time 908216684 ps
CPU time 2.92 seconds
Started Jun 28 07:15:55 PM PDT 24
Finished Jun 28 07:16:34 PM PDT 24
Peak memory 204728 kb
Host smart-838baf4b-c969-4ea7-82ff-58b580605ba3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177539657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3177539657
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.444628014
Short name T57
Test name
Test status
Simulation time 201078876 ps
CPU time 1.2 seconds
Started Jun 28 07:23:30 PM PDT 24
Finished Jun 28 07:23:36 PM PDT 24
Peak memory 204908 kb
Host smart-91a745f1-8b2c-4871-94c7-7eae6ea34980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444628014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.444628014
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1652603888
Short name T53
Test name
Test status
Simulation time 73055374 ps
CPU time 0.83 seconds
Started Jun 28 07:23:59 PM PDT 24
Finished Jun 28 07:24:03 PM PDT 24
Peak memory 204896 kb
Host smart-a781b0aa-93d8-4f7a-ba41-b5b718e72787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652603888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1652603888
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2584015915
Short name T103
Test name
Test status
Simulation time 4853078369 ps
CPU time 20.97 seconds
Started Jun 28 07:17:12 PM PDT 24
Finished Jun 28 07:17:47 PM PDT 24
Peak memory 213388 kb
Host smart-b18a6e65-d617-4729-b998-871b319b8117
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584015915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
584015915
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.1753386609
Short name T17
Test name
Test status
Simulation time 7357740963 ps
CPU time 5.56 seconds
Started Jun 28 07:24:34 PM PDT 24
Finished Jun 28 07:24:47 PM PDT 24
Peak memory 205200 kb
Host smart-c05c4d87-9cbc-421d-ac30-a7b5dc612152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753386609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1753386609
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1052296804
Short name T158
Test name
Test status
Simulation time 2053203113 ps
CPU time 2.77 seconds
Started Jun 28 07:24:58 PM PDT 24
Finished Jun 28 07:25:04 PM PDT 24
Peak memory 213452 kb
Host smart-2e598e6a-54a1-444e-84d1-358615524e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052296804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1052296804
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3024538076
Short name T106
Test name
Test status
Simulation time 7501965591 ps
CPU time 18.13 seconds
Started Jun 28 07:14:41 PM PDT 24
Finished Jun 28 07:15:27 PM PDT 24
Peak memory 205100 kb
Host smart-7ddbf0a1-44d0-4360-bb18-83f8f4596f30
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024538076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3024538076
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2463242335
Short name T404
Test name
Test status
Simulation time 993070784 ps
CPU time 10.26 seconds
Started Jun 28 07:17:15 PM PDT 24
Finished Jun 28 07:17:38 PM PDT 24
Peak memory 213312 kb
Host smart-71ac2464-3448-47ce-8968-9c3ca517af1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463242335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
463242335
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2059951999
Short name T154
Test name
Test status
Simulation time 2045541619 ps
CPU time 6.53 seconds
Started Jun 28 07:24:41 PM PDT 24
Finished Jun 28 07:24:51 PM PDT 24
Peak memory 213260 kb
Host smart-97578430-d4aa-4aff-8e55-f5d572b3db6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059951999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2059951999
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3283737387
Short name T126
Test name
Test status
Simulation time 1600803946 ps
CPU time 64.84 seconds
Started Jun 28 07:15:41 PM PDT 24
Finished Jun 28 07:17:21 PM PDT 24
Peak memory 204972 kb
Host smart-880f5bb4-e79b-4ce1-ab87-96da4ba02239
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283737387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3283737387
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3311028249
Short name T114
Test name
Test status
Simulation time 6508983536 ps
CPU time 69.95 seconds
Started Jun 28 07:16:14 PM PDT 24
Finished Jun 28 07:17:52 PM PDT 24
Peak memory 205128 kb
Host smart-a06c1214-9d56-4c85-9860-5ea5efe430b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311028249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3311028249
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.467820751
Short name T113
Test name
Test status
Simulation time 17629526609 ps
CPU time 55.71 seconds
Started Jun 28 07:14:58 PM PDT 24
Finished Jun 28 07:16:29 PM PDT 24
Peak memory 213248 kb
Host smart-69675bf0-6f9a-4445-9497-91046198358f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467820751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.467820751
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.557454247
Short name T436
Test name
Test status
Simulation time 400114589 ps
CPU time 3.02 seconds
Started Jun 28 07:14:58 PM PDT 24
Finished Jun 28 07:15:37 PM PDT 24
Peak memory 213280 kb
Host smart-6661357f-8a0a-4dd7-9a66-beea5ca57e3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557454247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.557454247
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.662700011
Short name T380
Test name
Test status
Simulation time 1468237530 ps
CPU time 4.45 seconds
Started Jun 28 07:15:00 PM PDT 24
Finished Jun 28 07:15:41 PM PDT 24
Peak memory 219140 kb
Host smart-17678258-b5e1-4b20-a700-22f6daa238a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662700011 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.662700011
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3097446900
Short name T424
Test name
Test status
Simulation time 114729657 ps
CPU time 1.48 seconds
Started Jun 28 07:14:57 PM PDT 24
Finished Jun 28 07:15:35 PM PDT 24
Peak memory 213280 kb
Host smart-13ba7243-d3cb-457c-8038-f1a318f56b3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097446900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3097446900
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.4251394469
Short name T413
Test name
Test status
Simulation time 19600644128 ps
CPU time 30.23 seconds
Started Jun 28 07:14:40 PM PDT 24
Finished Jun 28 07:15:35 PM PDT 24
Peak memory 205028 kb
Host smart-a30cc8bf-9652-4407-a71e-98c0e39e7af9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251394469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.4251394469
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.134892987
Short name T353
Test name
Test status
Simulation time 3721422080 ps
CPU time 4.33 seconds
Started Jun 28 07:14:39 PM PDT 24
Finished Jun 28 07:15:09 PM PDT 24
Peak memory 204976 kb
Host smart-439c5d86-d07d-49b1-9b7e-fc1fa71078bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134892987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
v_dm_jtag_dmi_csr_bit_bash.134892987
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3959427600
Short name T340
Test name
Test status
Simulation time 1389257009 ps
CPU time 3.02 seconds
Started Jun 28 07:14:39 PM PDT 24
Finished Jun 28 07:15:07 PM PDT 24
Peak memory 204900 kb
Host smart-92499101-af2f-40d1-a089-0e6af6e47722
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959427600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
959427600
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.558083305
Short name T421
Test name
Test status
Simulation time 1412422291 ps
CPU time 2.35 seconds
Started Jun 28 07:14:41 PM PDT 24
Finished Jun 28 07:15:11 PM PDT 24
Peak memory 204712 kb
Host smart-10da4672-f4ee-4882-99dd-92ae0bf98063
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558083305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.558083305
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1020857815
Short name T319
Test name
Test status
Simulation time 26066069474 ps
CPU time 16.25 seconds
Started Jun 28 07:14:40 PM PDT 24
Finished Jun 28 07:15:25 PM PDT 24
Peak memory 205012 kb
Host smart-cebf5c9d-7d6d-4568-87a2-53f1977eee95
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020857815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1020857815
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1898499088
Short name T382
Test name
Test status
Simulation time 259082038 ps
CPU time 0.89 seconds
Started Jun 28 07:14:39 PM PDT 24
Finished Jun 28 07:15:06 PM PDT 24
Peak memory 204720 kb
Host smart-cf133d82-e6ce-4d6a-8bb6-fb12c6c84ff3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898499088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1898499088
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.226656731
Short name T364
Test name
Test status
Simulation time 341956706 ps
CPU time 0.91 seconds
Started Jun 28 07:14:42 PM PDT 24
Finished Jun 28 07:15:13 PM PDT 24
Peak memory 204660 kb
Host smart-c463d8d8-9668-4fed-b7dc-ee1383bd57f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226656731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.226656731
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1092969354
Short name T370
Test name
Test status
Simulation time 133471340 ps
CPU time 0.83 seconds
Started Jun 28 07:14:39 PM PDT 24
Finished Jun 28 07:15:05 PM PDT 24
Peak memory 204724 kb
Host smart-504ddf68-0d27-4349-9861-e3bcf6b1cce2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092969354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1092969354
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1558539106
Short name T361
Test name
Test status
Simulation time 69988819 ps
CPU time 0.69 seconds
Started Jun 28 07:14:41 PM PDT 24
Finished Jun 28 07:15:10 PM PDT 24
Peak memory 204720 kb
Host smart-d6aa0717-eb3c-481c-ad28-b250f775a080
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558539106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1558539106
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3936614109
Short name T115
Test name
Test status
Simulation time 249607187 ps
CPU time 4.06 seconds
Started Jun 28 07:14:59 PM PDT 24
Finished Jun 28 07:15:40 PM PDT 24
Peak memory 205076 kb
Host smart-0b7ac4b3-5ee2-4684-a1d3-a04ae62b7e1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936614109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3936614109
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1303962467
Short name T422
Test name
Test status
Simulation time 36659926799 ps
CPU time 54.3 seconds
Started Jun 28 07:14:43 PM PDT 24
Finished Jun 28 07:16:09 PM PDT 24
Peak memory 221536 kb
Host smart-6ecb48f2-5376-4b5f-8627-3d7b01da189a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303962467 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1303962467
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1844192707
Short name T336
Test name
Test status
Simulation time 1637071784 ps
CPU time 3 seconds
Started Jun 28 07:14:41 PM PDT 24
Finished Jun 28 07:15:12 PM PDT 24
Peak memory 213284 kb
Host smart-8df92059-9d79-493b-9d79-ae23c3921c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844192707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1844192707
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2592458965
Short name T439
Test name
Test status
Simulation time 2328643575 ps
CPU time 13.82 seconds
Started Jun 28 07:14:39 PM PDT 24
Finished Jun 28 07:15:16 PM PDT 24
Peak memory 221516 kb
Host smart-9d281ee1-3029-4868-8ebd-e8493fd51335
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592458965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2592458965
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2344459131
Short name T423
Test name
Test status
Simulation time 3358229776 ps
CPU time 32.02 seconds
Started Jun 28 07:15:00 PM PDT 24
Finished Jun 28 07:16:09 PM PDT 24
Peak memory 205068 kb
Host smart-7bdab853-f078-44f6-b559-f86755f3952a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344459131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2344459131
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.759456
Short name T122
Test name
Test status
Simulation time 5015794358 ps
CPU time 55.31 seconds
Started Jun 28 07:15:16 PM PDT 24
Finished Jun 28 07:16:44 PM PDT 24
Peak memory 213308 kb
Host smart-e0bff558-4529-4be0-8574-f6e4fb2c823f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.759456
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2122610851
Short name T387
Test name
Test status
Simulation time 482914343 ps
CPU time 2.38 seconds
Started Jun 28 07:14:59 PM PDT 24
Finished Jun 28 07:15:39 PM PDT 24
Peak memory 213252 kb
Host smart-d29fa6c0-3800-4c7b-8ad5-94318bc181a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122610851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2122610851
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1273214333
Short name T385
Test name
Test status
Simulation time 5543907543 ps
CPU time 5.14 seconds
Started Jun 28 07:15:15 PM PDT 24
Finished Jun 28 07:15:54 PM PDT 24
Peak memory 219640 kb
Host smart-10d5be0a-dccf-44db-9e66-d527ba52b24a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273214333 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1273214333
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1761422983
Short name T354
Test name
Test status
Simulation time 277776027 ps
CPU time 1.55 seconds
Started Jun 28 07:15:01 PM PDT 24
Finished Jun 28 07:15:39 PM PDT 24
Peak memory 213236 kb
Host smart-a7b20e35-867a-4f09-ad0e-9f51a4e6ecfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761422983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1761422983
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1825641652
Short name T437
Test name
Test status
Simulation time 23843583324 ps
CPU time 39.32 seconds
Started Jun 28 07:14:57 PM PDT 24
Finished Jun 28 07:16:13 PM PDT 24
Peak memory 204984 kb
Host smart-220b61e7-a0d2-463d-a888-ee6bc9bc4562
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825641652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1825641652
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1244313283
Short name T393
Test name
Test status
Simulation time 26796722530 ps
CPU time 17.29 seconds
Started Jun 28 07:14:57 PM PDT 24
Finished Jun 28 07:15:51 PM PDT 24
Peak memory 204960 kb
Host smart-4048ba41-1bc0-441e-92c6-aebf8e2c28f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244313283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1244313283
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1771804624
Short name T331
Test name
Test status
Simulation time 2884250585 ps
CPU time 2.32 seconds
Started Jun 28 07:14:59 PM PDT 24
Finished Jun 28 07:15:36 PM PDT 24
Peak memory 205096 kb
Host smart-746f967e-5f0c-4d30-a314-1c125675c4d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771804624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1771804624
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1413144756
Short name T311
Test name
Test status
Simulation time 7578341430 ps
CPU time 18.52 seconds
Started Jun 28 07:14:59 PM PDT 24
Finished Jun 28 07:15:55 PM PDT 24
Peak memory 204956 kb
Host smart-7c27cd54-56c3-492b-9ee6-aba05b66a082
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413144756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
413144756
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.411031693
Short name T429
Test name
Test status
Simulation time 761469789 ps
CPU time 1.35 seconds
Started Jun 28 07:15:00 PM PDT 24
Finished Jun 28 07:15:38 PM PDT 24
Peak memory 204668 kb
Host smart-c306268d-75a4-4801-ab72-8245d1b449a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411031693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.411031693
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.631540871
Short name T410
Test name
Test status
Simulation time 60805627202 ps
CPU time 171.4 seconds
Started Jun 28 07:14:58 PM PDT 24
Finished Jun 28 07:18:25 PM PDT 24
Peak memory 204976 kb
Host smart-fcf21504-5394-4659-a4af-09508a16b02d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631540871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.631540871
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3628736185
Short name T302
Test name
Test status
Simulation time 990595054 ps
CPU time 0.95 seconds
Started Jun 28 07:14:58 PM PDT 24
Finished Jun 28 07:15:35 PM PDT 24
Peak memory 204720 kb
Host smart-1b004770-f4a1-4eb9-b812-50b7cca43c08
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628736185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3628736185
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3611993275
Short name T344
Test name
Test status
Simulation time 213269293 ps
CPU time 0.85 seconds
Started Jun 28 07:14:58 PM PDT 24
Finished Jun 28 07:15:34 PM PDT 24
Peak memory 204704 kb
Host smart-7fac1cdd-bc02-407b-959e-675f08ade2fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611993275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
611993275
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4254433986
Short name T334
Test name
Test status
Simulation time 102220880 ps
CPU time 0.91 seconds
Started Jun 28 07:14:58 PM PDT 24
Finished Jun 28 07:15:35 PM PDT 24
Peak memory 204688 kb
Host smart-c8629d97-8e9b-42a7-814c-20d76241a216
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254433986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.4254433986
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3396175612
Short name T431
Test name
Test status
Simulation time 50075272 ps
CPU time 0.76 seconds
Started Jun 28 07:14:58 PM PDT 24
Finished Jun 28 07:15:35 PM PDT 24
Peak memory 204720 kb
Host smart-c7e9a950-bd33-46a6-bab4-c0cb1c929d2a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396175612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3396175612
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1031918265
Short name T116
Test name
Test status
Simulation time 238584278 ps
CPU time 6.56 seconds
Started Jun 28 07:15:16 PM PDT 24
Finished Jun 28 07:15:56 PM PDT 24
Peak memory 205112 kb
Host smart-6621c3fe-f1bd-4dff-90b2-cc5134b49956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031918265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1031918265
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3518495078
Short name T369
Test name
Test status
Simulation time 31445023519 ps
CPU time 17.92 seconds
Started Jun 28 07:14:58 PM PDT 24
Finished Jun 28 07:15:52 PM PDT 24
Peak memory 221372 kb
Host smart-b1d990d2-2573-426f-876d-7802410d405e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518495078 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3518495078
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2868607629
Short name T314
Test name
Test status
Simulation time 388758911 ps
CPU time 2.34 seconds
Started Jun 28 07:14:59 PM PDT 24
Finished Jun 28 07:15:37 PM PDT 24
Peak memory 213304 kb
Host smart-00341738-92d8-4ccf-b406-b9d8c9494198
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868607629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2868607629
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.223344475
Short name T435
Test name
Test status
Simulation time 7974862357 ps
CPU time 21.48 seconds
Started Jun 28 07:15:01 PM PDT 24
Finished Jun 28 07:15:58 PM PDT 24
Peak memory 213324 kb
Host smart-c9e0bd37-9533-4737-8b29-b0bbba9c79cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223344475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.223344475
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.500494531
Short name T357
Test name
Test status
Simulation time 2055888120 ps
CPU time 4.17 seconds
Started Jun 28 07:17:12 PM PDT 24
Finished Jun 28 07:17:30 PM PDT 24
Peak memory 218040 kb
Host smart-d00b74f0-e2c8-4ece-8e64-42cf547d3265
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500494531 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.500494531
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2361774966
Short name T127
Test name
Test status
Simulation time 259436665 ps
CPU time 1.45 seconds
Started Jun 28 07:17:12 PM PDT 24
Finished Jun 28 07:17:28 PM PDT 24
Peak memory 213284 kb
Host smart-936042b3-7b9b-4bda-a358-8a7fa78d2023
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361774966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2361774966
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.715571460
Short name T294
Test name
Test status
Simulation time 17302149736 ps
CPU time 52.53 seconds
Started Jun 28 07:17:10 PM PDT 24
Finished Jun 28 07:18:16 PM PDT 24
Peak memory 204980 kb
Host smart-6e6723f8-e928-4554-8847-10e050127b3b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715571460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rv_dm_jtag_dmi_csr_bit_bash.715571460
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.910267255
Short name T400
Test name
Test status
Simulation time 6598685708 ps
CPU time 6.24 seconds
Started Jun 28 07:17:13 PM PDT 24
Finished Jun 28 07:17:33 PM PDT 24
Peak memory 204956 kb
Host smart-cce6371c-073b-4d61-b76c-0934b887dd5c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910267255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.910267255
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2288724187
Short name T313
Test name
Test status
Simulation time 387835565 ps
CPU time 0.9 seconds
Started Jun 28 07:17:12 PM PDT 24
Finished Jun 28 07:17:27 PM PDT 24
Peak memory 204720 kb
Host smart-0684f034-2b4a-468d-aece-03059db9b3ac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288724187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2288724187
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3530671425
Short name T324
Test name
Test status
Simulation time 87061751 ps
CPU time 3.29 seconds
Started Jun 28 07:17:14 PM PDT 24
Finished Jun 28 07:17:31 PM PDT 24
Peak memory 213396 kb
Host smart-defeb214-1d93-4bf2-b257-38284ba6a73a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530671425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3530671425
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2260733861
Short name T175
Test name
Test status
Simulation time 1243554269 ps
CPU time 11.71 seconds
Started Jun 28 07:17:15 PM PDT 24
Finished Jun 28 07:17:40 PM PDT 24
Peak memory 213312 kb
Host smart-203f2aa0-9632-4ae4-ad41-64199b05d132
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260733861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
260733861
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.358342936
Short name T137
Test name
Test status
Simulation time 2596312784 ps
CPU time 3.13 seconds
Started Jun 28 07:17:12 PM PDT 24
Finished Jun 28 07:17:29 PM PDT 24
Peak memory 218320 kb
Host smart-04534192-42a5-4b10-9956-f99b5f33cfbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358342936 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.358342936
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1846461913
Short name T418
Test name
Test status
Simulation time 209419859 ps
CPU time 2.38 seconds
Started Jun 28 07:17:15 PM PDT 24
Finished Jun 28 07:17:31 PM PDT 24
Peak memory 213284 kb
Host smart-1281386b-7128-442a-a672-e4b7f9f27946
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846461913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1846461913
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2012894118
Short name T295
Test name
Test status
Simulation time 9250469147 ps
CPU time 27.51 seconds
Started Jun 28 07:17:13 PM PDT 24
Finished Jun 28 07:17:55 PM PDT 24
Peak memory 205012 kb
Host smart-303b7fa0-1dfe-4f5a-8221-db826560b74f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012894118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.2012894118
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1759851928
Short name T325
Test name
Test status
Simulation time 1811516001 ps
CPU time 1.89 seconds
Started Jun 28 07:17:11 PM PDT 24
Finished Jun 28 07:17:27 PM PDT 24
Peak memory 204900 kb
Host smart-27c00e3b-1faa-4a23-8d19-862c9ad872fd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759851928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1759851928
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3266599058
Short name T304
Test name
Test status
Simulation time 428593004 ps
CPU time 0.95 seconds
Started Jun 28 07:17:12 PM PDT 24
Finished Jun 28 07:17:27 PM PDT 24
Peak memory 204820 kb
Host smart-75bd80a2-b366-4460-9d12-4b396384ee23
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266599058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3266599058
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4057265164
Short name T341
Test name
Test status
Simulation time 1997288430 ps
CPU time 6.91 seconds
Started Jun 28 07:17:12 PM PDT 24
Finished Jun 28 07:17:33 PM PDT 24
Peak memory 205104 kb
Host smart-d15adf08-77ef-4418-bd0e-e9997e8ff63f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057265164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.4057265164
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3861182325
Short name T326
Test name
Test status
Simulation time 316085782 ps
CPU time 4.06 seconds
Started Jun 28 07:17:13 PM PDT 24
Finished Jun 28 07:17:31 PM PDT 24
Peak memory 215928 kb
Host smart-c06ce22c-4d29-4f06-b2dd-fdad337cb409
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861182325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3861182325
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.625610876
Short name T169
Test name
Test status
Simulation time 8969617052 ps
CPU time 13.19 seconds
Started Jun 28 07:17:14 PM PDT 24
Finished Jun 28 07:17:41 PM PDT 24
Peak memory 221504 kb
Host smart-338a1ca8-4124-4e29-936a-ddbd3ccfa66e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625610876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.625610876
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.31710064
Short name T70
Test name
Test status
Simulation time 2085644728 ps
CPU time 4.98 seconds
Started Jun 28 07:17:14 PM PDT 24
Finished Jun 28 07:17:33 PM PDT 24
Peak memory 221380 kb
Host smart-fe5dc097-4117-492f-97e5-55fe91ff65f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31710064 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.31710064
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2306173756
Short name T75
Test name
Test status
Simulation time 83410350 ps
CPU time 1.6 seconds
Started Jun 28 07:17:11 PM PDT 24
Finished Jun 28 07:17:26 PM PDT 24
Peak memory 213168 kb
Host smart-5a15ed5d-a0e9-4d0d-bb4d-7d6a1a852086
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306173756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2306173756
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3137709012
Short name T330
Test name
Test status
Simulation time 26322846582 ps
CPU time 18.33 seconds
Started Jun 28 07:17:13 PM PDT 24
Finished Jun 28 07:17:46 PM PDT 24
Peak memory 204928 kb
Host smart-f963e505-fc2f-4f4c-aea7-2472baee119c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137709012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3137709012
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3706108562
Short name T352
Test name
Test status
Simulation time 13271871734 ps
CPU time 5.27 seconds
Started Jun 28 07:17:11 PM PDT 24
Finished Jun 28 07:17:30 PM PDT 24
Peak memory 204932 kb
Host smart-d6df7fd5-fd5c-488e-92e4-37cfe21c2c49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706108562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3706108562
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.419194832
Short name T368
Test name
Test status
Simulation time 1397841209 ps
CPU time 1.63 seconds
Started Jun 28 07:17:12 PM PDT 24
Finished Jun 28 07:17:28 PM PDT 24
Peak memory 204716 kb
Host smart-a24ebcf5-4d65-42ca-901d-407ca03de56d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419194832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.419194832
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1066028213
Short name T131
Test name
Test status
Simulation time 1087803388 ps
CPU time 8.22 seconds
Started Jun 28 07:17:12 PM PDT 24
Finished Jun 28 07:17:35 PM PDT 24
Peak memory 205096 kb
Host smart-1b26bbd5-aad6-490f-a552-5b339b33c4ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066028213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1066028213
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1696976530
Short name T346
Test name
Test status
Simulation time 1684693642 ps
CPU time 4.82 seconds
Started Jun 28 07:17:16 PM PDT 24
Finished Jun 28 07:17:33 PM PDT 24
Peak memory 213380 kb
Host smart-86ad2096-23ae-425d-804c-664d46857133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696976530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1696976530
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1724638321
Short name T318
Test name
Test status
Simulation time 252660771 ps
CPU time 3.95 seconds
Started Jun 28 07:17:10 PM PDT 24
Finished Jun 28 07:17:28 PM PDT 24
Peak memory 218736 kb
Host smart-e5928b46-bd6b-49bd-96f8-c1de096a2b7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724638321 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1724638321
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2988829545
Short name T98
Test name
Test status
Simulation time 107284153 ps
CPU time 2.28 seconds
Started Jun 28 07:17:13 PM PDT 24
Finished Jun 28 07:17:29 PM PDT 24
Peak memory 213208 kb
Host smart-b5af1da7-ef32-475d-8e87-91e1963a579c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988829545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2988829545
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1740908676
Short name T373
Test name
Test status
Simulation time 17027257536 ps
CPU time 31.92 seconds
Started Jun 28 07:17:10 PM PDT 24
Finished Jun 28 07:17:56 PM PDT 24
Peak memory 204992 kb
Host smart-b608b65e-a5a4-4cda-93f9-070457ddcea3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740908676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.1740908676
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2946863891
Short name T365
Test name
Test status
Simulation time 12745032743 ps
CPU time 10.3 seconds
Started Jun 28 07:17:11 PM PDT 24
Finished Jun 28 07:17:35 PM PDT 24
Peak memory 204964 kb
Host smart-f67eada4-456a-49be-924d-53b52723f1b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946863891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2946863891
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1564137328
Short name T317
Test name
Test status
Simulation time 120586819 ps
CPU time 0.84 seconds
Started Jun 28 07:17:14 PM PDT 24
Finished Jun 28 07:17:29 PM PDT 24
Peak memory 204680 kb
Host smart-174555c7-f5a1-4089-8f69-90b56751e97b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564137328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1564137328
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3383380123
Short name T100
Test name
Test status
Simulation time 624239043 ps
CPU time 6.41 seconds
Started Jun 28 07:17:13 PM PDT 24
Finished Jun 28 07:17:33 PM PDT 24
Peak memory 205140 kb
Host smart-5c3e1987-bc07-44c0-a934-f1251a6ff73f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383380123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3383380123
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1076195503
Short name T89
Test name
Test status
Simulation time 319879729 ps
CPU time 4.85 seconds
Started Jun 28 07:17:14 PM PDT 24
Finished Jun 28 07:17:33 PM PDT 24
Peak memory 216056 kb
Host smart-8171f134-9b36-4dc0-9897-612275eb8cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076195503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1076195503
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.209569294
Short name T172
Test name
Test status
Simulation time 2424034479 ps
CPU time 15.01 seconds
Started Jun 28 07:17:11 PM PDT 24
Finished Jun 28 07:17:40 PM PDT 24
Peak memory 213388 kb
Host smart-208b1dec-1556-4b36-86ae-60409d6c9ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209569294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.209569294
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4109089041
Short name T94
Test name
Test status
Simulation time 1212365539 ps
CPU time 3.91 seconds
Started Jun 28 07:17:14 PM PDT 24
Finished Jun 28 07:17:32 PM PDT 24
Peak memory 219044 kb
Host smart-f9460ccd-0d90-467f-b7c4-a4b279b64a54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109089041 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4109089041
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.4088953449
Short name T108
Test name
Test status
Simulation time 67349573 ps
CPU time 2.19 seconds
Started Jun 28 07:17:15 PM PDT 24
Finished Jun 28 07:17:30 PM PDT 24
Peak memory 213204 kb
Host smart-bb01bddb-27ef-42c9-828b-539230ee9102
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088953449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.4088953449
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1278801550
Short name T420
Test name
Test status
Simulation time 101723981001 ps
CPU time 66.71 seconds
Started Jun 28 07:17:13 PM PDT 24
Finished Jun 28 07:18:34 PM PDT 24
Peak memory 204964 kb
Host smart-d42d166d-f767-4ba2-883c-9ce1c9c2b213
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278801550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.1278801550
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.547291837
Short name T398
Test name
Test status
Simulation time 1916469292 ps
CPU time 4.79 seconds
Started Jun 28 07:17:11 PM PDT 24
Finished Jun 28 07:17:29 PM PDT 24
Peak memory 204876 kb
Host smart-c2471882-f569-4cc7-9ba5-9fd64a45ca82
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547291837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.547291837
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2353804153
Short name T384
Test name
Test status
Simulation time 569047986 ps
CPU time 0.99 seconds
Started Jun 28 07:17:12 PM PDT 24
Finished Jun 28 07:17:27 PM PDT 24
Peak memory 204728 kb
Host smart-5406dfc7-5ac2-49d4-a56c-313d416fc7e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353804153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2353804153
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3394462639
Short name T407
Test name
Test status
Simulation time 2145982685 ps
CPU time 7.76 seconds
Started Jun 28 07:17:12 PM PDT 24
Finished Jun 28 07:17:35 PM PDT 24
Peak memory 205096 kb
Host smart-73366d23-7e1e-47ef-b5b4-eb9e1b147853
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394462639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3394462639
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1935932113
Short name T72
Test name
Test status
Simulation time 533269621 ps
CPU time 5.02 seconds
Started Jun 28 07:17:14 PM PDT 24
Finished Jun 28 07:17:33 PM PDT 24
Peak memory 213276 kb
Host smart-3ddd1c70-f743-40b6-8a8b-996d8f8d7279
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935932113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1935932113
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1249347863
Short name T333
Test name
Test status
Simulation time 4594231515 ps
CPU time 6.06 seconds
Started Jun 28 07:18:17 PM PDT 24
Finished Jun 28 07:18:34 PM PDT 24
Peak memory 220288 kb
Host smart-849ee89d-1b44-48f2-906d-37d040249562
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249347863 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1249347863
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4260185080
Short name T128
Test name
Test status
Simulation time 183499183 ps
CPU time 2.64 seconds
Started Jun 28 07:18:17 PM PDT 24
Finished Jun 28 07:18:30 PM PDT 24
Peak memory 213216 kb
Host smart-46bb3317-0c2c-4e86-9357-ec0cd412486b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260185080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.4260185080
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3641616119
Short name T296
Test name
Test status
Simulation time 3994892018 ps
CPU time 3.26 seconds
Started Jun 28 07:17:10 PM PDT 24
Finished Jun 28 07:17:27 PM PDT 24
Peak memory 204980 kb
Host smart-4655170f-9cc1-481d-b06b-470c5336754b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641616119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.3641616119
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1989389376
Short name T383
Test name
Test status
Simulation time 1792090027 ps
CPU time 2.13 seconds
Started Jun 28 07:17:13 PM PDT 24
Finished Jun 28 07:17:29 PM PDT 24
Peak memory 204908 kb
Host smart-0a309fa2-05ad-4073-ab56-306218c09777
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989389376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1989389376
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1654449877
Short name T86
Test name
Test status
Simulation time 311763419 ps
CPU time 1.27 seconds
Started Jun 28 07:17:10 PM PDT 24
Finished Jun 28 07:17:24 PM PDT 24
Peak memory 204724 kb
Host smart-d69ff7aa-bc6d-4ecb-a1a3-282bb66212e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654449877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1654449877
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.4123464670
Short name T119
Test name
Test status
Simulation time 3301377042 ps
CPU time 4.11 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:18:32 PM PDT 24
Peak memory 205164 kb
Host smart-f88141e5-5e3d-4bb3-bbb5-70a698b65221
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123464670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.4123464670
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4154044969
Short name T379
Test name
Test status
Simulation time 307820137 ps
CPU time 4.47 seconds
Started Jun 28 07:18:17 PM PDT 24
Finished Jun 28 07:18:31 PM PDT 24
Peak memory 216072 kb
Host smart-9304d1c6-1255-4f66-9c1f-d874622af394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154044969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.4154044969
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2146250782
Short name T92
Test name
Test status
Simulation time 6135013124 ps
CPU time 23.83 seconds
Started Jun 28 07:18:17 PM PDT 24
Finished Jun 28 07:18:52 PM PDT 24
Peak memory 213352 kb
Host smart-1e294e35-e9e8-456f-ba27-6b64c4e047f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146250782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
146250782
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4099952816
Short name T408
Test name
Test status
Simulation time 319081948 ps
CPU time 2.18 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:18:30 PM PDT 24
Peak memory 214912 kb
Host smart-3c83a597-d60a-4c8c-9e5c-a4e3b971a802
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099952816 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.4099952816
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3341632747
Short name T348
Test name
Test status
Simulation time 287279818 ps
CPU time 2.17 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:18:30 PM PDT 24
Peak memory 213216 kb
Host smart-370d8960-2b8f-42da-8478-08a677e96506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341632747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3341632747
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1598558426
Short name T363
Test name
Test status
Simulation time 7709433907 ps
CPU time 12.64 seconds
Started Jun 28 07:18:19 PM PDT 24
Finished Jun 28 07:18:41 PM PDT 24
Peak memory 205020 kb
Host smart-5420aa65-8b79-47e0-98fd-5b432f60132b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598558426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.1598558426
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1250550124
Short name T397
Test name
Test status
Simulation time 2457536495 ps
CPU time 1.88 seconds
Started Jun 28 07:18:16 PM PDT 24
Finished Jun 28 07:18:28 PM PDT 24
Peak memory 204960 kb
Host smart-036f27cf-2147-4190-b26f-66a5d2a27799
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250550124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1250550124
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2116327364
Short name T389
Test name
Test status
Simulation time 564200710 ps
CPU time 1.99 seconds
Started Jun 28 07:18:17 PM PDT 24
Finished Jun 28 07:18:29 PM PDT 24
Peak memory 204724 kb
Host smart-9cc45c30-1c20-4d2d-b427-0ed2a2aea4d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116327364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2116327364
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1208453670
Short name T97
Test name
Test status
Simulation time 591084979 ps
CPU time 4.2 seconds
Started Jun 28 07:18:16 PM PDT 24
Finished Jun 28 07:18:31 PM PDT 24
Peak memory 205068 kb
Host smart-e77a2e1a-5400-4464-85b5-5aaddd7e45b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208453670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1208453670
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3191339580
Short name T140
Test name
Test status
Simulation time 535110472 ps
CPU time 6.5 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:18:35 PM PDT 24
Peak memory 213328 kb
Host smart-68e6958d-90f8-4a9d-935c-5651f15d12ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191339580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3191339580
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2225597150
Short name T90
Test name
Test status
Simulation time 1004448803 ps
CPU time 4.46 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:18:32 PM PDT 24
Peak memory 219804 kb
Host smart-70cf0a39-6e9e-43f0-878a-01e53cfdc2ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225597150 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2225597150
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3941436151
Short name T425
Test name
Test status
Simulation time 153524401 ps
CPU time 1.47 seconds
Started Jun 28 07:18:17 PM PDT 24
Finished Jun 28 07:18:29 PM PDT 24
Peak memory 213224 kb
Host smart-64d1aac2-669e-4130-b4ac-abe50573388c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941436151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3941436151
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2385163337
Short name T329
Test name
Test status
Simulation time 30328399365 ps
CPU time 76.97 seconds
Started Jun 28 07:18:19 PM PDT 24
Finished Jun 28 07:19:46 PM PDT 24
Peak memory 205020 kb
Host smart-da854ee4-06ba-46a2-95bd-bf262ad5f177
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385163337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.2385163337
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1742266744
Short name T298
Test name
Test status
Simulation time 1487088406 ps
CPU time 1.9 seconds
Started Jun 28 07:18:17 PM PDT 24
Finished Jun 28 07:18:29 PM PDT 24
Peak memory 204920 kb
Host smart-23980f39-5cbb-4d1f-a032-07501293a514
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742266744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1742266744
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3568841439
Short name T310
Test name
Test status
Simulation time 118089523 ps
CPU time 0.93 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:18:29 PM PDT 24
Peak memory 204720 kb
Host smart-6f450a04-ac0e-409b-beab-14781042d90c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568841439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3568841439
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1430512652
Short name T376
Test name
Test status
Simulation time 1072274748 ps
CPU time 4.52 seconds
Started Jun 28 07:18:17 PM PDT 24
Finished Jun 28 07:18:32 PM PDT 24
Peak memory 205100 kb
Host smart-1e62c0c5-f0a4-485b-bd7c-4e232dd41514
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430512652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1430512652
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1539545890
Short name T71
Test name
Test status
Simulation time 238317030 ps
CPU time 2.59 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:18:31 PM PDT 24
Peak memory 213332 kb
Host smart-a76ab457-5b6a-4652-9672-6cf4657f5450
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539545890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1539545890
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2924449705
Short name T171
Test name
Test status
Simulation time 2136737650 ps
CPU time 9.23 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:18:37 PM PDT 24
Peak memory 213268 kb
Host smart-a4a132db-5918-4812-b3cf-a46d2bdd1350
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924449705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
924449705
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1679777795
Short name T95
Test name
Test status
Simulation time 116518896 ps
CPU time 2.25 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:18:30 PM PDT 24
Peak memory 217104 kb
Host smart-d1b4a7a5-72fa-4ccc-8cac-d1077f7a904d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679777795 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1679777795
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.217136997
Short name T349
Test name
Test status
Simulation time 499255694 ps
CPU time 2.39 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:18:31 PM PDT 24
Peak memory 213212 kb
Host smart-fd0166a5-7c13-4fef-b426-35dab8bba9cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217136997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.217136997
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2880753102
Short name T386
Test name
Test status
Simulation time 100239859 ps
CPU time 0.81 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:18:29 PM PDT 24
Peak memory 204732 kb
Host smart-d6cfbd98-2958-4fe4-99c9-eb458f7a3f58
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880753102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2880753102
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1516146714
Short name T395
Test name
Test status
Simulation time 1468632605 ps
CPU time 4.24 seconds
Started Jun 28 07:18:16 PM PDT 24
Finished Jun 28 07:18:31 PM PDT 24
Peak memory 204884 kb
Host smart-6b1704fb-2c63-4ba3-b347-75c167147c9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516146714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1516146714
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.312753847
Short name T323
Test name
Test status
Simulation time 212400436 ps
CPU time 0.75 seconds
Started Jun 28 07:18:17 PM PDT 24
Finished Jun 28 07:18:29 PM PDT 24
Peak memory 204688 kb
Host smart-d69d467d-1074-4a9e-81f8-48e6f400c20f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312753847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.312753847
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2587942531
Short name T99
Test name
Test status
Simulation time 588750905 ps
CPU time 6.85 seconds
Started Jun 28 07:18:19 PM PDT 24
Finished Jun 28 07:18:35 PM PDT 24
Peak memory 205100 kb
Host smart-00080b21-5f43-46f0-b055-bce9561046e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587942531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2587942531
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1221454065
Short name T362
Test name
Test status
Simulation time 425675660 ps
CPU time 5.8 seconds
Started Jun 28 07:18:19 PM PDT 24
Finished Jun 28 07:18:34 PM PDT 24
Peak memory 221492 kb
Host smart-16c0a6c8-877b-48a5-8f70-8a6c8e2ebc5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221454065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1221454065
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3201914088
Short name T123
Test name
Test status
Simulation time 438135472 ps
CPU time 2.09 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:18:30 PM PDT 24
Peak memory 213212 kb
Host smart-ba2340f2-5e5e-4366-bb94-f41c6a7c0706
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201914088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3201914088
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.546586059
Short name T312
Test name
Test status
Simulation time 16888668008 ps
CPU time 46.59 seconds
Started Jun 28 07:18:18 PM PDT 24
Finished Jun 28 07:19:14 PM PDT 24
Peak memory 204976 kb
Host smart-b688cdae-6729-41f2-b73f-52e157f7c2b4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546586059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.546586059
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3438190810
Short name T307
Test name
Test status
Simulation time 4471621161 ps
CPU time 7.22 seconds
Started Jun 28 07:18:17 PM PDT 24
Finished Jun 28 07:18:35 PM PDT 24
Peak memory 204960 kb
Host smart-1870286d-83aa-43d3-8cb7-4db03e1000c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438190810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3438190810
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3840413952
Short name T411
Test name
Test status
Simulation time 621795004 ps
CPU time 2.18 seconds
Started Jun 28 07:18:19 PM PDT 24
Finished Jun 28 07:18:31 PM PDT 24
Peak memory 204708 kb
Host smart-cdc43701-15fb-4caa-a429-eda81761be6b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840413952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3840413952
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.301485975
Short name T391
Test name
Test status
Simulation time 602931814 ps
CPU time 7.87 seconds
Started Jun 28 07:18:17 PM PDT 24
Finished Jun 28 07:18:36 PM PDT 24
Peak memory 205072 kb
Host smart-ef9b943f-690f-4546-9a62-377faed2d654
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301485975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.301485975
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3049773616
Short name T402
Test name
Test status
Simulation time 1081848184 ps
CPU time 2.7 seconds
Started Jun 28 07:18:17 PM PDT 24
Finished Jun 28 07:18:30 PM PDT 24
Peak memory 213336 kb
Host smart-1fdebb5a-120e-4b64-b687-b4ff04e9998a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049773616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3049773616
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1704836063
Short name T374
Test name
Test status
Simulation time 2553178236 ps
CPU time 9.83 seconds
Started Jun 28 07:18:17 PM PDT 24
Finished Jun 28 07:18:38 PM PDT 24
Peak memory 213408 kb
Host smart-a4105604-27a9-4112-9fde-4b58e2bb2498
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704836063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
704836063
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1022825363
Short name T121
Test name
Test status
Simulation time 5540835486 ps
CPU time 31.13 seconds
Started Jun 28 07:15:19 PM PDT 24
Finished Jun 28 07:16:25 PM PDT 24
Peak memory 205040 kb
Host smart-b7158deb-0620-42e3-a0b3-9c801f4aa6c1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022825363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1022825363
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.966862311
Short name T377
Test name
Test status
Simulation time 2478633284 ps
CPU time 32.25 seconds
Started Jun 28 07:15:14 PM PDT 24
Finished Jun 28 07:16:21 PM PDT 24
Peak memory 213316 kb
Host smart-fdbad27d-f575-4a80-a5e1-a8bf0aa21829
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966862311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.966862311
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.156975801
Short name T403
Test name
Test status
Simulation time 246458600 ps
CPU time 2.5 seconds
Started Jun 28 07:15:19 PM PDT 24
Finished Jun 28 07:15:57 PM PDT 24
Peak memory 213280 kb
Host smart-d950ba7f-6ee0-40c7-84d1-f75ccdd69193
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156975801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.156975801
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2245503011
Short name T390
Test name
Test status
Simulation time 2375160746 ps
CPU time 4.98 seconds
Started Jun 28 07:15:41 PM PDT 24
Finished Jun 28 07:16:22 PM PDT 24
Peak memory 220472 kb
Host smart-b2221bae-e3be-4416-88f0-d451987e11bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245503011 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2245503011
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3159193183
Short name T442
Test name
Test status
Simulation time 113561140 ps
CPU time 2.13 seconds
Started Jun 28 07:15:15 PM PDT 24
Finished Jun 28 07:15:51 PM PDT 24
Peak memory 213164 kb
Host smart-ed2dc7e7-eae7-4948-b9fe-c60ccb41017e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159193183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3159193183
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3538869728
Short name T297
Test name
Test status
Simulation time 209497815782 ps
CPU time 605.71 seconds
Started Jun 28 07:15:15 PM PDT 24
Finished Jun 28 07:25:54 PM PDT 24
Peak memory 210264 kb
Host smart-506b22e1-4d21-4e43-8456-a8657e848cd8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538869728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3538869728
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2587521185
Short name T306
Test name
Test status
Simulation time 25910239617 ps
CPU time 65.99 seconds
Started Jun 28 07:15:14 PM PDT 24
Finished Jun 28 07:16:52 PM PDT 24
Peak memory 205012 kb
Host smart-c51aa5f2-154c-4223-a67c-c60fe0936b24
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587521185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.2587521185
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1147431330
Short name T105
Test name
Test status
Simulation time 7175302977 ps
CPU time 10.29 seconds
Started Jun 28 07:15:14 PM PDT 24
Finished Jun 28 07:15:59 PM PDT 24
Peak memory 205100 kb
Host smart-661f1018-f2d4-4f55-9586-67680242adb3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147431330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1147431330
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1702371342
Short name T305
Test name
Test status
Simulation time 1158720629 ps
CPU time 2.48 seconds
Started Jun 28 07:15:16 PM PDT 24
Finished Jun 28 07:15:54 PM PDT 24
Peak memory 204868 kb
Host smart-55e5a9a8-f2a7-4adb-ae03-46332d9774f7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702371342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
702371342
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.788935958
Short name T371
Test name
Test status
Simulation time 1994281045 ps
CPU time 3.46 seconds
Started Jun 28 07:15:15 PM PDT 24
Finished Jun 28 07:15:52 PM PDT 24
Peak memory 204668 kb
Host smart-0b7317c7-19c2-4e3f-928a-2a31a3f243b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788935958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.788935958
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.377293827
Short name T347
Test name
Test status
Simulation time 12202707752 ps
CPU time 27.41 seconds
Started Jun 28 07:15:15 PM PDT 24
Finished Jun 28 07:16:17 PM PDT 24
Peak memory 205024 kb
Host smart-f245910d-b526-4834-ae10-62fee3088178
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377293827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.377293827
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3824204241
Short name T350
Test name
Test status
Simulation time 318833779 ps
CPU time 1.61 seconds
Started Jun 28 07:15:15 PM PDT 24
Finished Jun 28 07:15:50 PM PDT 24
Peak memory 204764 kb
Host smart-67ddde38-9903-4da9-8530-0b84d36135ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824204241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3824204241
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4242719531
Short name T321
Test name
Test status
Simulation time 168062413 ps
CPU time 1.09 seconds
Started Jun 28 07:15:19 PM PDT 24
Finished Jun 28 07:15:56 PM PDT 24
Peak memory 204720 kb
Host smart-cb9b793b-951a-4a91-8d6c-817f631cc0aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242719531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.4
242719531
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.554697055
Short name T396
Test name
Test status
Simulation time 171040022 ps
CPU time 0.69 seconds
Started Jun 28 07:15:16 PM PDT 24
Finished Jun 28 07:15:53 PM PDT 24
Peak memory 204716 kb
Host smart-245e6f41-0d3d-4957-b313-6a0f13501ecc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554697055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.554697055
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4030904773
Short name T308
Test name
Test status
Simulation time 131334996 ps
CPU time 1.03 seconds
Started Jun 28 07:15:16 PM PDT 24
Finished Jun 28 07:15:53 PM PDT 24
Peak memory 204724 kb
Host smart-44888bc8-517e-41f9-b1fb-3161840299da
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030904773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.4030904773
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1509587581
Short name T111
Test name
Test status
Simulation time 198550459 ps
CPU time 3.52 seconds
Started Jun 28 07:15:14 PM PDT 24
Finished Jun 28 07:15:49 PM PDT 24
Peak memory 205088 kb
Host smart-70d6c92a-ff73-4417-a415-469ee7c9c7e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509587581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1509587581
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3927587287
Short name T419
Test name
Test status
Simulation time 31028590605 ps
CPU time 52.04 seconds
Started Jun 28 07:15:15 PM PDT 24
Finished Jun 28 07:16:41 PM PDT 24
Peak memory 221300 kb
Host smart-ab0729e5-3572-41c8-a405-3168922b9527
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927587287 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3927587287
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1741476270
Short name T432
Test name
Test status
Simulation time 138864748 ps
CPU time 3.08 seconds
Started Jun 28 07:15:17 PM PDT 24
Finished Jun 28 07:15:58 PM PDT 24
Peak memory 213300 kb
Host smart-b1db614f-7906-4d6b-ac1d-0738aec44cf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741476270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1741476270
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.534441027
Short name T93
Test name
Test status
Simulation time 3657023729 ps
CPU time 21.93 seconds
Started Jun 28 07:15:15 PM PDT 24
Finished Jun 28 07:16:10 PM PDT 24
Peak memory 213356 kb
Host smart-bd370e09-5750-4a73-b171-a039da4189c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534441027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.534441027
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2565463179
Short name T434
Test name
Test status
Simulation time 3827123561 ps
CPU time 37.94 seconds
Started Jun 28 07:15:55 PM PDT 24
Finished Jun 28 07:17:09 PM PDT 24
Peak memory 213280 kb
Host smart-695966f3-0563-41e5-8564-6dc737c070c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565463179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2565463179
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2498775846
Short name T430
Test name
Test status
Simulation time 349498243 ps
CPU time 1.7 seconds
Started Jun 28 07:15:55 PM PDT 24
Finished Jun 28 07:16:32 PM PDT 24
Peak memory 213308 kb
Host smart-d6705598-d33b-4db1-adfc-664f4ea0b6b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498775846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2498775846
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1477184774
Short name T316
Test name
Test status
Simulation time 4129304183 ps
CPU time 4.39 seconds
Started Jun 28 07:15:54 PM PDT 24
Finished Jun 28 07:16:34 PM PDT 24
Peak memory 220240 kb
Host smart-779af964-98ed-433f-b32d-643e10fd4c99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477184774 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1477184774
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4088011795
Short name T112
Test name
Test status
Simulation time 289557726 ps
CPU time 1.62 seconds
Started Jun 28 07:15:55 PM PDT 24
Finished Jun 28 07:16:33 PM PDT 24
Peak memory 213168 kb
Host smart-ad296e25-d21f-40d0-a54e-4444a236b961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088011795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.4088011795
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.993705719
Short name T303
Test name
Test status
Simulation time 121026560114 ps
CPU time 299.96 seconds
Started Jun 28 07:15:40 PM PDT 24
Finished Jun 28 07:21:16 PM PDT 24
Peak memory 205016 kb
Host smart-fb4032cc-2b97-460e-b894-10c8a67035f7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993705719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.993705719
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.459550327
Short name T406
Test name
Test status
Simulation time 2869307259 ps
CPU time 4.86 seconds
Started Jun 28 07:15:41 PM PDT 24
Finished Jun 28 07:16:21 PM PDT 24
Peak memory 204952 kb
Host smart-f0b29de2-8d08-42e1-9f53-9a1aebbe8cc7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459550327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
v_dm_jtag_dmi_csr_bit_bash.459550327
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2121278793
Short name T104
Test name
Test status
Simulation time 8606394435 ps
CPU time 8.81 seconds
Started Jun 28 07:15:41 PM PDT 24
Finished Jun 28 07:16:25 PM PDT 24
Peak memory 205032 kb
Host smart-2eb40f54-3162-445e-a908-1608fc3934ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121278793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2121278793
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.865245110
Short name T426
Test name
Test status
Simulation time 5469115201 ps
CPU time 5.01 seconds
Started Jun 28 07:15:41 PM PDT 24
Finished Jun 28 07:16:21 PM PDT 24
Peak memory 204960 kb
Host smart-cb5b83da-d7da-4922-a980-f152af93013f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865245110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.865245110
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1018677018
Short name T401
Test name
Test status
Simulation time 632061436 ps
CPU time 1.61 seconds
Started Jun 28 07:15:42 PM PDT 24
Finished Jun 28 07:16:18 PM PDT 24
Peak memory 204736 kb
Host smart-815292d1-4252-4979-8aa0-102d3d79cc41
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018677018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1018677018
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1968410636
Short name T427
Test name
Test status
Simulation time 31968770128 ps
CPU time 83.08 seconds
Started Jun 28 07:15:40 PM PDT 24
Finished Jun 28 07:17:38 PM PDT 24
Peak memory 205000 kb
Host smart-a73b400e-733a-4f3c-b14f-5f8e393caed7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968410636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1968410636
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1101013271
Short name T388
Test name
Test status
Simulation time 665269691 ps
CPU time 2.3 seconds
Started Jun 28 07:15:42 PM PDT 24
Finished Jun 28 07:16:19 PM PDT 24
Peak memory 204724 kb
Host smart-c786725d-3ace-4c86-97ca-0fbd9d504ddf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101013271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1101013271
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.339425939
Short name T327
Test name
Test status
Simulation time 664329121 ps
CPU time 1.91 seconds
Started Jun 28 07:15:42 PM PDT 24
Finished Jun 28 07:16:19 PM PDT 24
Peak memory 204728 kb
Host smart-9a6f6792-a02a-4fbb-8f0d-21c786428b05
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339425939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.339425939
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.682596097
Short name T338
Test name
Test status
Simulation time 80006552 ps
CPU time 0.85 seconds
Started Jun 28 07:15:53 PM PDT 24
Finished Jun 28 07:16:30 PM PDT 24
Peak memory 204720 kb
Host smart-93aebabf-2088-4115-9fbd-d12fef5feca4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682596097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.682596097
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2438091156
Short name T337
Test name
Test status
Simulation time 90794758 ps
CPU time 0.74 seconds
Started Jun 28 07:15:53 PM PDT 24
Finished Jun 28 07:16:30 PM PDT 24
Peak memory 204724 kb
Host smart-6f301cef-02d9-45db-ac3f-fd6ae7595652
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438091156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2438091156
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.548698006
Short name T73
Test name
Test status
Simulation time 468106049 ps
CPU time 6.82 seconds
Started Jun 28 07:15:53 PM PDT 24
Finished Jun 28 07:16:36 PM PDT 24
Peak memory 205032 kb
Host smart-a2ca3aba-e006-4ffc-925c-5ac26db64807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548698006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.548698006
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2323158843
Short name T139
Test name
Test status
Simulation time 74052883565 ps
CPU time 59.05 seconds
Started Jun 28 07:15:55 PM PDT 24
Finished Jun 28 07:17:30 PM PDT 24
Peak memory 223012 kb
Host smart-124fca13-4da1-4088-bcaa-0f24b2300ab5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323158843 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2323158843
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3254900094
Short name T441
Test name
Test status
Simulation time 389034460 ps
CPU time 5.94 seconds
Started Jun 28 07:15:54 PM PDT 24
Finished Jun 28 07:16:35 PM PDT 24
Peak memory 213296 kb
Host smart-9e5558fb-e2c5-415b-be75-e7603fec4afe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254900094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3254900094
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2040226487
Short name T174
Test name
Test status
Simulation time 2213750525 ps
CPU time 20.54 seconds
Started Jun 28 07:15:54 PM PDT 24
Finished Jun 28 07:16:51 PM PDT 24
Peak memory 213372 kb
Host smart-36b581cd-3180-4f46-8465-4a8d3ab5672a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040226487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2040226487
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.356879186
Short name T117
Test name
Test status
Simulation time 6938099797 ps
CPU time 74.19 seconds
Started Jun 28 07:15:56 PM PDT 24
Finished Jun 28 07:17:45 PM PDT 24
Peak memory 213276 kb
Host smart-21c67c0d-9426-49c0-8d99-d729ce35191c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356879186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.356879186
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2877100074
Short name T355
Test name
Test status
Simulation time 1694904037 ps
CPU time 2.55 seconds
Started Jun 28 07:16:16 PM PDT 24
Finished Jun 28 07:16:47 PM PDT 24
Peak memory 214276 kb
Host smart-46b5d54d-01ce-4020-8e72-4ee22b3ca762
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877100074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2877100074
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2834521506
Short name T416
Test name
Test status
Simulation time 178866913 ps
CPU time 2.3 seconds
Started Jun 28 07:16:19 PM PDT 24
Finished Jun 28 07:16:48 PM PDT 24
Peak memory 217072 kb
Host smart-a9296d08-d69c-4b18-b61c-c4d52f2589cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834521506 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2834521506
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1378847464
Short name T74
Test name
Test status
Simulation time 179208432 ps
CPU time 1.53 seconds
Started Jun 28 07:16:19 PM PDT 24
Finished Jun 28 07:16:46 PM PDT 24
Peak memory 213180 kb
Host smart-5232620b-d730-41e8-bcd4-a2852ee9ec6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378847464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1378847464
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1292653618
Short name T360
Test name
Test status
Simulation time 19421651433 ps
CPU time 49.51 seconds
Started Jun 28 07:16:14 PM PDT 24
Finished Jun 28 07:17:32 PM PDT 24
Peak memory 204932 kb
Host smart-506686d9-bb6a-49dc-a308-c0b1e6e65e9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292653618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1292653618
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1092635142
Short name T320
Test name
Test status
Simulation time 14419463705 ps
CPU time 15.49 seconds
Started Jun 28 07:16:12 PM PDT 24
Finished Jun 28 07:16:56 PM PDT 24
Peak memory 204996 kb
Host smart-b88d1d78-3cb0-4bd1-a1d4-5a37c623ce15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092635142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.1092635142
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.155034125
Short name T107
Test name
Test status
Simulation time 1901933995 ps
CPU time 5.98 seconds
Started Jun 28 07:16:15 PM PDT 24
Finished Jun 28 07:16:48 PM PDT 24
Peak memory 204736 kb
Host smart-d6bc083c-ceb4-4fec-aaad-5614b5815670
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155034125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.155034125
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3354269526
Short name T359
Test name
Test status
Simulation time 2194032591 ps
CPU time 3.04 seconds
Started Jun 28 07:16:13 PM PDT 24
Finished Jun 28 07:16:44 PM PDT 24
Peak memory 204996 kb
Host smart-47d31a37-8b92-4cf3-94e5-1c7cfbaecbc0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354269526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
354269526
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3004119085
Short name T378
Test name
Test status
Simulation time 1486039008 ps
CPU time 4.21 seconds
Started Jun 28 07:16:13 PM PDT 24
Finished Jun 28 07:16:45 PM PDT 24
Peak memory 204728 kb
Host smart-e533b138-dbdf-4195-9b63-01c61a1b816f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004119085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3004119085
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1679182705
Short name T438
Test name
Test status
Simulation time 14965822588 ps
CPU time 42.41 seconds
Started Jun 28 07:16:14 PM PDT 24
Finished Jun 28 07:17:23 PM PDT 24
Peak memory 204952 kb
Host smart-efbbd120-4001-4a1b-bb01-c756b6bf7afa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679182705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1679182705
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.985720911
Short name T405
Test name
Test status
Simulation time 512502127 ps
CPU time 2.07 seconds
Started Jun 28 07:16:19 PM PDT 24
Finished Jun 28 07:16:48 PM PDT 24
Peak memory 204736 kb
Host smart-2d2fc814-2160-40bf-8983-24d13e4a3e4b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985720911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.985720911
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.637783641
Short name T300
Test name
Test status
Simulation time 42950392 ps
CPU time 0.75 seconds
Started Jun 28 07:16:14 PM PDT 24
Finished Jun 28 07:16:42 PM PDT 24
Peak memory 204676 kb
Host smart-4641f597-7340-4417-9c91-8a64beb38e17
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637783641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.637783641
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1184706057
Short name T332
Test name
Test status
Simulation time 84039134 ps
CPU time 0.75 seconds
Started Jun 28 07:16:20 PM PDT 24
Finished Jun 28 07:16:47 PM PDT 24
Peak memory 204740 kb
Host smart-774e84b2-a602-4de1-85b5-8f536adbcdd7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184706057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1184706057
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.4177181537
Short name T118
Test name
Test status
Simulation time 297904592 ps
CPU time 4.33 seconds
Started Jun 28 07:16:12 PM PDT 24
Finished Jun 28 07:16:45 PM PDT 24
Peak memory 205088 kb
Host smart-bf37b525-38eb-4dc5-bf15-adf370a057bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177181537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.4177181537
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3793031756
Short name T61
Test name
Test status
Simulation time 42045124561 ps
CPU time 67.27 seconds
Started Jun 28 07:16:13 PM PDT 24
Finished Jun 28 07:17:48 PM PDT 24
Peak memory 220976 kb
Host smart-1ba4c8bc-1634-4b72-8349-8aef020bf227
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793031756 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3793031756
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2335919012
Short name T394
Test name
Test status
Simulation time 320890603 ps
CPU time 6.13 seconds
Started Jun 28 07:16:12 PM PDT 24
Finished Jun 28 07:16:47 PM PDT 24
Peak memory 213336 kb
Host smart-a0521b9c-39ee-4905-b5e7-5c45dbe6a18c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335919012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2335919012
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3125910708
Short name T414
Test name
Test status
Simulation time 3713421790 ps
CPU time 13.71 seconds
Started Jun 28 07:16:20 PM PDT 24
Finished Jun 28 07:17:00 PM PDT 24
Peak memory 213384 kb
Host smart-63cba738-55d9-4f64-856d-2e96abd9f9fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125910708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3125910708
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4247464681
Short name T367
Test name
Test status
Simulation time 204992986 ps
CPU time 2.2 seconds
Started Jun 28 07:16:13 PM PDT 24
Finished Jun 28 07:16:43 PM PDT 24
Peak memory 217228 kb
Host smart-096092d2-23ad-48a1-8e46-acefbd3f03d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247464681 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.4247464681
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3939690778
Short name T125
Test name
Test status
Simulation time 209535426 ps
CPU time 2.33 seconds
Started Jun 28 07:16:15 PM PDT 24
Finished Jun 28 07:16:45 PM PDT 24
Peak memory 213280 kb
Host smart-d055d881-ec23-436d-9f03-0742c31e62a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939690778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3939690778
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3587078093
Short name T299
Test name
Test status
Simulation time 2217276293 ps
CPU time 6.67 seconds
Started Jun 28 07:16:14 PM PDT 24
Finished Jun 28 07:16:49 PM PDT 24
Peak memory 204964 kb
Host smart-01c4d5c8-9e88-4a75-91a8-4e567f13ba11
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587078093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3587078093
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3721283511
Short name T381
Test name
Test status
Simulation time 4574798826 ps
CPU time 12.72 seconds
Started Jun 28 07:16:12 PM PDT 24
Finished Jun 28 07:16:53 PM PDT 24
Peak memory 204960 kb
Host smart-2087cf6e-3056-412b-97a9-864088c10146
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721283511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
721283511
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.750338278
Short name T87
Test name
Test status
Simulation time 139801654 ps
CPU time 0.75 seconds
Started Jun 28 07:16:15 PM PDT 24
Finished Jun 28 07:16:43 PM PDT 24
Peak memory 204696 kb
Host smart-63b26a85-03c4-4fff-a5e8-92ff328d770f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750338278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.750338278
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.4239343075
Short name T415
Test name
Test status
Simulation time 977216681 ps
CPU time 7.61 seconds
Started Jun 28 07:16:15 PM PDT 24
Finished Jun 28 07:16:50 PM PDT 24
Peak memory 205132 kb
Host smart-3f96ec55-bcf3-4b48-948b-f5d7564bf270
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239343075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.4239343075
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.66746568
Short name T168
Test name
Test status
Simulation time 245309471 ps
CPU time 2.55 seconds
Started Jun 28 07:16:14 PM PDT 24
Finished Jun 28 07:16:43 PM PDT 24
Peak memory 213316 kb
Host smart-bf24dc5f-1f94-4333-a2bb-bd499f9f0e86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66746568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.66746568
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1835442642
Short name T315
Test name
Test status
Simulation time 3440897170 ps
CPU time 5.89 seconds
Started Jun 28 07:16:46 PM PDT 24
Finished Jun 28 07:17:04 PM PDT 24
Peak memory 220628 kb
Host smart-4a574cf1-f068-4319-96bb-31ddeeb2b73f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835442642 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1835442642
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2589438125
Short name T110
Test name
Test status
Simulation time 105783400 ps
CPU time 2.36 seconds
Started Jun 28 07:16:44 PM PDT 24
Finished Jun 28 07:17:00 PM PDT 24
Peak memory 213188 kb
Host smart-4321dd99-a7c2-4a9c-a6d1-8c54c76f634f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589438125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2589438125
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3914148607
Short name T358
Test name
Test status
Simulation time 6093613356 ps
CPU time 6.51 seconds
Started Jun 28 07:16:14 PM PDT 24
Finished Jun 28 07:16:49 PM PDT 24
Peak memory 204968 kb
Host smart-956d1da8-a7a0-4347-bf40-a9e33742be25
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914148607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.3914148607
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2329542836
Short name T372
Test name
Test status
Simulation time 1293193375 ps
CPU time 2.73 seconds
Started Jun 28 07:16:15 PM PDT 24
Finished Jun 28 07:16:45 PM PDT 24
Peak memory 204556 kb
Host smart-d4af2dd5-ff01-40df-995b-c92dc99f0a3e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329542836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
329542836
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3877166515
Short name T328
Test name
Test status
Simulation time 138007196 ps
CPU time 0.8 seconds
Started Jun 28 07:16:12 PM PDT 24
Finished Jun 28 07:16:41 PM PDT 24
Peak memory 204720 kb
Host smart-2ccbdc87-9097-43f4-a253-5ebfb49cfa87
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877166515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
877166515
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2978857329
Short name T120
Test name
Test status
Simulation time 237528545 ps
CPU time 6.71 seconds
Started Jun 28 07:16:43 PM PDT 24
Finished Jun 28 07:17:04 PM PDT 24
Peak memory 205116 kb
Host smart-58286eb2-156f-4380-8f83-aecd3cdabbd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978857329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2978857329
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3157239647
Short name T399
Test name
Test status
Simulation time 40220396302 ps
CPU time 129.41 seconds
Started Jun 28 07:16:13 PM PDT 24
Finished Jun 28 07:18:50 PM PDT 24
Peak memory 221524 kb
Host smart-acdeeb2a-1e26-4dfd-8dff-e1076a94c78f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157239647 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3157239647
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1889043103
Short name T392
Test name
Test status
Simulation time 423896646 ps
CPU time 6.1 seconds
Started Jun 28 07:16:15 PM PDT 24
Finished Jun 28 07:16:48 PM PDT 24
Peak memory 215956 kb
Host smart-6f10ac05-68e7-420c-9850-153600fe1e89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889043103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1889043103
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3526743148
Short name T135
Test name
Test status
Simulation time 8881683838 ps
CPU time 11.89 seconds
Started Jun 28 07:16:43 PM PDT 24
Finished Jun 28 07:17:09 PM PDT 24
Peak memory 213364 kb
Host smart-e7d97d00-68fb-445a-954a-b3fa6a4dccb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526743148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3526743148
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2313892013
Short name T417
Test name
Test status
Simulation time 321791954 ps
CPU time 2.34 seconds
Started Jun 28 07:16:45 PM PDT 24
Finished Jun 28 07:17:00 PM PDT 24
Peak memory 216596 kb
Host smart-0231a801-29cc-4002-ae02-70905e1549d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313892013 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2313892013
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3275094460
Short name T129
Test name
Test status
Simulation time 204638559 ps
CPU time 2.76 seconds
Started Jun 28 07:16:46 PM PDT 24
Finished Jun 28 07:17:01 PM PDT 24
Peak memory 213212 kb
Host smart-cf77aebb-24c7-4e4c-ac27-4622d569cdc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275094460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3275094460
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.4101664720
Short name T301
Test name
Test status
Simulation time 3204114030 ps
CPU time 5.61 seconds
Started Jun 28 07:16:44 PM PDT 24
Finished Jun 28 07:17:04 PM PDT 24
Peak memory 204976 kb
Host smart-8e1c19d8-a079-4e22-af39-f3a3acc182a2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101664720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.4101664720
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1191822943
Short name T309
Test name
Test status
Simulation time 14249056663 ps
CPU time 38.36 seconds
Started Jun 28 07:16:45 PM PDT 24
Finished Jun 28 07:17:36 PM PDT 24
Peak memory 204960 kb
Host smart-70916975-ef4c-4279-b897-ce8ac3c154fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191822943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
191822943
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3137038619
Short name T366
Test name
Test status
Simulation time 270410388 ps
CPU time 0.75 seconds
Started Jun 28 07:16:46 PM PDT 24
Finished Jun 28 07:16:59 PM PDT 24
Peak memory 204848 kb
Host smart-75ad913f-3388-4826-a0df-471ede75b7b3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137038619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
137038619
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.590029942
Short name T130
Test name
Test status
Simulation time 2114247928 ps
CPU time 7.73 seconds
Started Jun 28 07:16:47 PM PDT 24
Finished Jun 28 07:17:06 PM PDT 24
Peak memory 205176 kb
Host smart-e9e459e0-37e8-4a42-a954-1bc5d4f8c426
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590029942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.590029942
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1447915353
Short name T412
Test name
Test status
Simulation time 314538496 ps
CPU time 2.82 seconds
Started Jun 28 07:16:46 PM PDT 24
Finished Jun 28 07:17:01 PM PDT 24
Peak memory 212836 kb
Host smart-010705b2-668c-48b8-961b-18aaf7536a55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447915353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1447915353
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2726994612
Short name T345
Test name
Test status
Simulation time 1092422048 ps
CPU time 9.58 seconds
Started Jun 28 07:16:46 PM PDT 24
Finished Jun 28 07:17:08 PM PDT 24
Peak memory 213332 kb
Host smart-1d77a8e7-181d-41db-89ab-93b9fa2b787c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726994612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2726994612
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2928715118
Short name T409
Test name
Test status
Simulation time 559586486 ps
CPU time 4.03 seconds
Started Jun 28 07:16:47 PM PDT 24
Finished Jun 28 07:17:03 PM PDT 24
Peak memory 219800 kb
Host smart-5b6ab0f2-ced9-4caa-85d7-0a95fd7e5a0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928715118 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2928715118
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2155958895
Short name T124
Test name
Test status
Simulation time 53563994 ps
CPU time 2.19 seconds
Started Jun 28 07:16:44 PM PDT 24
Finished Jun 28 07:17:00 PM PDT 24
Peak memory 213268 kb
Host smart-41d13bba-377c-4bb8-891c-af9da4fa961b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155958895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2155958895
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.4097255038
Short name T351
Test name
Test status
Simulation time 79524285571 ps
CPU time 86.94 seconds
Started Jun 28 07:16:44 PM PDT 24
Finished Jun 28 07:18:25 PM PDT 24
Peak memory 204964 kb
Host smart-c9d7302f-8eb4-414c-936b-4389cd24ebda
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097255038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.4097255038
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3827819554
Short name T342
Test name
Test status
Simulation time 7120470629 ps
CPU time 17.74 seconds
Started Jun 28 07:16:45 PM PDT 24
Finished Jun 28 07:17:16 PM PDT 24
Peak memory 205096 kb
Host smart-28d36ba2-3dd8-4b64-ba60-86c2a6859e68
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827819554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
827819554
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.912445774
Short name T375
Test name
Test status
Simulation time 323687342 ps
CPU time 1.44 seconds
Started Jun 28 07:16:44 PM PDT 24
Finished Jun 28 07:16:59 PM PDT 24
Peak memory 204716 kb
Host smart-77504723-fa45-4171-a1de-70fa8b2a2959
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912445774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.912445774
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.206964606
Short name T102
Test name
Test status
Simulation time 948836867 ps
CPU time 7.75 seconds
Started Jun 28 07:16:45 PM PDT 24
Finished Jun 28 07:17:06 PM PDT 24
Peak memory 205096 kb
Host smart-f653ee16-03a1-430f-8944-34e3c81cdf6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206964606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.206964606
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1122272085
Short name T60
Test name
Test status
Simulation time 32020687809 ps
CPU time 20.08 seconds
Started Jun 28 07:16:47 PM PDT 24
Finished Jun 28 07:17:18 PM PDT 24
Peak memory 221528 kb
Host smart-e4e30bd6-4c94-49b7-b0e1-c170011dd2b1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122272085 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1122272085
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1063164191
Short name T433
Test name
Test status
Simulation time 190535986 ps
CPU time 2.87 seconds
Started Jun 28 07:16:43 PM PDT 24
Finished Jun 28 07:17:00 PM PDT 24
Peak memory 213280 kb
Host smart-d419c03e-d5e8-4566-9e7a-77cb9a60baf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063164191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1063164191
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3603706618
Short name T356
Test name
Test status
Simulation time 1236619064 ps
CPU time 12.68 seconds
Started Jun 28 07:16:44 PM PDT 24
Finished Jun 28 07:17:11 PM PDT 24
Peak memory 213280 kb
Host smart-ae4b7184-3861-4607-96a1-0b82ce15c9ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603706618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3603706618
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2204552985
Short name T428
Test name
Test status
Simulation time 1200670669 ps
CPU time 2.78 seconds
Started Jun 28 07:17:12 PM PDT 24
Finished Jun 28 07:17:29 PM PDT 24
Peak memory 214800 kb
Host smart-5dc2c115-8801-4132-ac17-2cfa4487baad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204552985 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2204552985
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.739519711
Short name T440
Test name
Test status
Simulation time 99421709 ps
CPU time 1.43 seconds
Started Jun 28 07:16:44 PM PDT 24
Finished Jun 28 07:16:59 PM PDT 24
Peak memory 213244 kb
Host smart-651bc1a9-efc2-4b3c-8915-5c02b326a2ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739519711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.739519711
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3257945038
Short name T322
Test name
Test status
Simulation time 46477098533 ps
CPU time 74.89 seconds
Started Jun 28 07:16:46 PM PDT 24
Finished Jun 28 07:18:13 PM PDT 24
Peak memory 204964 kb
Host smart-3dcb5300-5fa5-488c-95d7-6ee76420ffe6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257945038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3257945038
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3498324175
Short name T339
Test name
Test status
Simulation time 3371654718 ps
CPU time 2.68 seconds
Started Jun 28 07:16:44 PM PDT 24
Finished Jun 28 07:17:01 PM PDT 24
Peak memory 204968 kb
Host smart-7794563c-d217-4288-a380-673de6691520
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498324175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
498324175
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.298471032
Short name T343
Test name
Test status
Simulation time 324205893 ps
CPU time 0.9 seconds
Started Jun 28 07:16:46 PM PDT 24
Finished Jun 28 07:16:59 PM PDT 24
Peak memory 204704 kb
Host smart-aaa8a899-7108-45fe-8807-066e775ff01f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298471032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.298471032
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1525899347
Short name T101
Test name
Test status
Simulation time 178889032 ps
CPU time 3.98 seconds
Started Jun 28 07:17:13 PM PDT 24
Finished Jun 28 07:17:32 PM PDT 24
Peak memory 205096 kb
Host smart-9ae64e2d-4483-4a61-a736-c0317cd2bc96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525899347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1525899347
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3570205514
Short name T335
Test name
Test status
Simulation time 13832368875 ps
CPU time 25.6 seconds
Started Jun 28 07:16:43 PM PDT 24
Finished Jun 28 07:17:23 PM PDT 24
Peak memory 221508 kb
Host smart-892296f1-b3d0-4dc5-a8c5-f03f64928dc7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570205514 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3570205514
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.702869860
Short name T138
Test name
Test status
Simulation time 911966678 ps
CPU time 6.37 seconds
Started Jun 28 07:16:44 PM PDT 24
Finished Jun 28 07:17:04 PM PDT 24
Peak memory 213280 kb
Host smart-fe9aa652-7ca4-4c59-98be-5fd0ff3e00b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702869860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.702869860
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1846143130
Short name T173
Test name
Test status
Simulation time 7884490773 ps
CPU time 20.89 seconds
Started Jun 28 07:16:43 PM PDT 24
Finished Jun 28 07:17:18 PM PDT 24
Peak memory 213436 kb
Host smart-0b42e2d8-55dc-45c9-99f1-d6d97855b79e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846143130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1846143130
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3372266019
Short name T133
Test name
Test status
Simulation time 49919704 ps
CPU time 0.79 seconds
Started Jun 28 07:23:28 PM PDT 24
Finished Jun 28 07:23:31 PM PDT 24
Peak memory 204884 kb
Host smart-35de91df-24eb-45bb-a45e-abfb3a2b3533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372266019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3372266019
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.508389557
Short name T200
Test name
Test status
Simulation time 3896866192 ps
CPU time 11.64 seconds
Started Jun 28 07:23:30 PM PDT 24
Finished Jun 28 07:23:46 PM PDT 24
Peak memory 213568 kb
Host smart-6a26ab18-0a7e-444a-ac08-823884cf95c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508389557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.508389557
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3746644010
Short name T247
Test name
Test status
Simulation time 1322806742 ps
CPU time 4.03 seconds
Started Jun 28 07:23:30 PM PDT 24
Finished Jun 28 07:23:40 PM PDT 24
Peak memory 205220 kb
Host smart-13329a70-3b95-44e9-9f05-398bab57700a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746644010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3746644010
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.448844502
Short name T25
Test name
Test status
Simulation time 985856169 ps
CPU time 3.26 seconds
Started Jun 28 07:23:29 PM PDT 24
Finished Jun 28 07:23:38 PM PDT 24
Peak memory 204840 kb
Host smart-c17a9550-42be-40bc-8693-a6936a2c3e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448844502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.448844502
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1781049693
Short name T19
Test name
Test status
Simulation time 1826081160 ps
CPU time 1.26 seconds
Started Jun 28 07:23:30 PM PDT 24
Finished Jun 28 07:23:37 PM PDT 24
Peak memory 204928 kb
Host smart-8b2550f6-d3ec-46ef-be1c-382dc0f00740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781049693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1781049693
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2784622783
Short name T52
Test name
Test status
Simulation time 1807703996 ps
CPU time 1.77 seconds
Started Jun 28 07:23:31 PM PDT 24
Finished Jun 28 07:23:39 PM PDT 24
Peak memory 204824 kb
Host smart-a9bf62d3-31d2-4754-b363-ce2edb94b3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784622783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2784622783
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2052433415
Short name T143
Test name
Test status
Simulation time 408057657 ps
CPU time 1.68 seconds
Started Jun 28 07:23:30 PM PDT 24
Finished Jun 28 07:23:38 PM PDT 24
Peak memory 204932 kb
Host smart-75206c7f-5e6a-4458-80e7-e3f28206993a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052433415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2052433415
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.131399887
Short name T30
Test name
Test status
Simulation time 107307670 ps
CPU time 0.78 seconds
Started Jun 28 07:23:30 PM PDT 24
Finished Jun 28 07:23:37 PM PDT 24
Peak memory 204912 kb
Host smart-af23fb4b-cb32-49ae-977b-009a93a7d760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131399887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.131399887
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2467936271
Short name T45
Test name
Test status
Simulation time 3494446523 ps
CPU time 5.02 seconds
Started Jun 28 07:23:31 PM PDT 24
Finished Jun 28 07:23:43 PM PDT 24
Peak memory 213484 kb
Host smart-c97e9cc0-73fe-40f3-993f-9a0e57fd9066
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467936271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2467936271
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3277277
Short name T183
Test name
Test status
Simulation time 387872734 ps
CPU time 1.26 seconds
Started Jun 28 07:23:30 PM PDT 24
Finished Jun 28 07:23:36 PM PDT 24
Peak memory 204892 kb
Host smart-b81df222-5881-4381-8a0d-09ef2995d830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3277277
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1407089067
Short name T287
Test name
Test status
Simulation time 62165770 ps
CPU time 0.76 seconds
Started Jun 28 07:23:31 PM PDT 24
Finished Jun 28 07:23:37 PM PDT 24
Peak memory 204924 kb
Host smart-3ad5a881-a92f-4be1-9e3d-6f93cd908114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407089067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1407089067
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3745901251
Short name T157
Test name
Test status
Simulation time 1538447678 ps
CPU time 4.19 seconds
Started Jun 28 07:23:31 PM PDT 24
Finished Jun 28 07:23:41 PM PDT 24
Peak memory 204912 kb
Host smart-0e84d469-47f1-4545-bef9-9d04edd03050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745901251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3745901251
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3030512483
Short name T266
Test name
Test status
Simulation time 1042470609 ps
CPU time 3.43 seconds
Started Jun 28 07:23:33 PM PDT 24
Finished Jun 28 07:23:44 PM PDT 24
Peak memory 204932 kb
Host smart-289e0b60-8326-449f-84d3-f50285fe98e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030512483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3030512483
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1949340954
Short name T156
Test name
Test status
Simulation time 777906822 ps
CPU time 1.17 seconds
Started Jun 28 07:23:31 PM PDT 24
Finished Jun 28 07:23:39 PM PDT 24
Peak memory 204924 kb
Host smart-05a2bc3f-647b-4af9-ae48-43a822f7008d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949340954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1949340954
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1446460929
Short name T62
Test name
Test status
Simulation time 171658833 ps
CPU time 0.87 seconds
Started Jun 28 07:23:29 PM PDT 24
Finished Jun 28 07:23:33 PM PDT 24
Peak memory 204896 kb
Host smart-09681cfd-7f6d-4df4-9561-9242a473bfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446460929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1446460929
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3535794874
Short name T188
Test name
Test status
Simulation time 593305887 ps
CPU time 1.17 seconds
Started Jun 28 07:23:34 PM PDT 24
Finished Jun 28 07:23:42 PM PDT 24
Peak memory 204928 kb
Host smart-47d1358a-46ed-4f02-adaa-3d2e16f65dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535794874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3535794874
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2246171225
Short name T186
Test name
Test status
Simulation time 857214023 ps
CPU time 0.97 seconds
Started Jun 28 07:23:31 PM PDT 24
Finished Jun 28 07:23:38 PM PDT 24
Peak memory 204876 kb
Host smart-2862c25b-adc2-4520-ae0d-e3618c3da98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246171225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2246171225
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2319143833
Short name T192
Test name
Test status
Simulation time 236080918 ps
CPU time 0.76 seconds
Started Jun 28 07:23:29 PM PDT 24
Finished Jun 28 07:23:33 PM PDT 24
Peak memory 204904 kb
Host smart-7ecfd469-3c05-49a4-b9f1-e2036feafafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319143833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2319143833
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.956205750
Short name T26
Test name
Test status
Simulation time 268735994 ps
CPU time 0.82 seconds
Started Jun 28 07:23:28 PM PDT 24
Finished Jun 28 07:23:32 PM PDT 24
Peak memory 204920 kb
Host smart-5b15842a-68df-4f94-8604-4ec7e9ff8c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956205750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.956205750
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1969535040
Short name T6
Test name
Test status
Simulation time 1490603741 ps
CPU time 1.59 seconds
Started Jun 28 07:23:29 PM PDT 24
Finished Jun 28 07:23:34 PM PDT 24
Peak memory 204912 kb
Host smart-dcfc286b-075a-4faf-bb0c-7f64007a382a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969535040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1969535040
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3926214244
Short name T167
Test name
Test status
Simulation time 3693423199 ps
CPU time 3.57 seconds
Started Jun 28 07:23:29 PM PDT 24
Finished Jun 28 07:23:36 PM PDT 24
Peak memory 213432 kb
Host smart-804039b3-6530-4693-99b8-8ea1cb195e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926214244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3926214244
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2894101509
Short name T78
Test name
Test status
Simulation time 2770351435 ps
CPU time 1.88 seconds
Started Jun 28 07:23:30 PM PDT 24
Finished Jun 28 07:23:38 PM PDT 24
Peak memory 238092 kb
Host smart-b0417d58-e9e3-46ee-9bba-4fb5436d885d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894101509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2894101509
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3793504067
Short name T216
Test name
Test status
Simulation time 3258300689 ps
CPU time 9.04 seconds
Started Jun 28 07:23:34 PM PDT 24
Finished Jun 28 07:23:50 PM PDT 24
Peak memory 204964 kb
Host smart-6e0b5179-dec6-4e81-a38a-41946d23c7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793504067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3793504067
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2762931891
Short name T33
Test name
Test status
Simulation time 11906808849 ps
CPU time 35.4 seconds
Started Jun 28 07:23:31 PM PDT 24
Finished Jun 28 07:24:12 PM PDT 24
Peak memory 213384 kb
Host smart-c27fdd05-262b-4349-8b2c-59bf59145d62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762931891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2762931891
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1725114910
Short name T59
Test name
Test status
Simulation time 11624021575 ps
CPU time 27.95 seconds
Started Jun 28 07:23:32 PM PDT 24
Finished Jun 28 07:24:07 PM PDT 24
Peak memory 205148 kb
Host smart-91a80aab-a428-413c-9102-58c315dc1e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725114910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1725114910
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1548660643
Short name T58
Test name
Test status
Simulation time 367645843 ps
CPU time 0.88 seconds
Started Jun 28 07:24:02 PM PDT 24
Finished Jun 28 07:24:11 PM PDT 24
Peak memory 204896 kb
Host smart-761d902b-28f8-441e-8644-f779b80f40a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548660643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1548660643
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.452478562
Short name T255
Test name
Test status
Simulation time 104467108 ps
CPU time 1 seconds
Started Jun 28 07:24:02 PM PDT 24
Finished Jun 28 07:24:10 PM PDT 24
Peak memory 204904 kb
Host smart-3d002670-8281-487d-a37a-190ae7322462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452478562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.452478562
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3367434920
Short name T258
Test name
Test status
Simulation time 41447546101 ps
CPU time 103.78 seconds
Started Jun 28 07:24:01 PM PDT 24
Finished Jun 28 07:25:51 PM PDT 24
Peak memory 213428 kb
Host smart-e518c806-11a0-41b1-b12b-76a38b191ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367434920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3367434920
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.3382202935
Short name T248
Test name
Test status
Simulation time 4548788180 ps
CPU time 14.91 seconds
Started Jun 28 07:23:58 PM PDT 24
Finished Jun 28 07:24:15 PM PDT 24
Peak memory 213540 kb
Host smart-df971e7c-8342-4d98-bea6-5f257237b900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382202935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3382202935
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2095817906
Short name T189
Test name
Test status
Simulation time 509495074 ps
CPU time 0.97 seconds
Started Jun 28 07:23:59 PM PDT 24
Finished Jun 28 07:24:04 PM PDT 24
Peak memory 204932 kb
Host smart-03be16b7-c9ab-48a1-b291-d68d3971a776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095817906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2095817906
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3612984170
Short name T42
Test name
Test status
Simulation time 133532153 ps
CPU time 0.8 seconds
Started Jun 28 07:24:00 PM PDT 24
Finished Jun 28 07:24:06 PM PDT 24
Peak memory 204924 kb
Host smart-1fde608c-9107-40c2-91be-9430a42e578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612984170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3612984170
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3105275723
Short name T147
Test name
Test status
Simulation time 205270450 ps
CPU time 0.75 seconds
Started Jun 28 07:24:04 PM PDT 24
Finished Jun 28 07:24:13 PM PDT 24
Peak memory 205036 kb
Host smart-44e79f97-391e-4324-bfd6-1b72f9b0cd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105275723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3105275723
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.2273443117
Short name T63
Test name
Test status
Simulation time 79073084 ps
CPU time 0.88 seconds
Started Jun 28 07:24:04 PM PDT 24
Finished Jun 28 07:24:13 PM PDT 24
Peak memory 215536 kb
Host smart-689badc0-746f-4024-bca2-6054ea8f7740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273443117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2273443117
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.105979141
Short name T34
Test name
Test status
Simulation time 2710305124 ps
CPU time 2.62 seconds
Started Jun 28 07:24:00 PM PDT 24
Finished Jun 28 07:24:07 PM PDT 24
Peak memory 205316 kb
Host smart-6dd030d9-b02b-418e-8c2a-0260a44c3f33
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105979141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl
_access.105979141
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1567895484
Short name T292
Test name
Test status
Simulation time 787355004 ps
CPU time 2.87 seconds
Started Jun 28 07:24:03 PM PDT 24
Finished Jun 28 07:24:13 PM PDT 24
Peak memory 205036 kb
Host smart-fb54d879-4c7e-4989-bebe-b039cbe79957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567895484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1567895484
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2415299643
Short name T240
Test name
Test status
Simulation time 201966989 ps
CPU time 0.98 seconds
Started Jun 28 07:24:00 PM PDT 24
Finished Jun 28 07:24:05 PM PDT 24
Peak memory 204880 kb
Host smart-e233a88a-f126-412a-bb5e-340eb7c67a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415299643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2415299643
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3452244794
Short name T280
Test name
Test status
Simulation time 948322478 ps
CPU time 1.95 seconds
Started Jun 28 07:24:02 PM PDT 24
Finished Jun 28 07:24:11 PM PDT 24
Peak memory 204892 kb
Host smart-9c0e8f54-edfd-4a61-8981-848cdbfd4fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452244794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3452244794
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1513075942
Short name T268
Test name
Test status
Simulation time 776042484 ps
CPU time 0.87 seconds
Started Jun 28 07:24:00 PM PDT 24
Finished Jun 28 07:24:05 PM PDT 24
Peak memory 204872 kb
Host smart-d7055851-75c3-4fdb-92eb-e02a8b715b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513075942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1513075942
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3574582840
Short name T37
Test name
Test status
Simulation time 2887375353 ps
CPU time 2.45 seconds
Started Jun 28 07:24:01 PM PDT 24
Finished Jun 28 07:24:10 PM PDT 24
Peak memory 204984 kb
Host smart-538606bf-543e-4b0a-8684-9ea94da0b463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574582840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3574582840
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1290979786
Short name T290
Test name
Test status
Simulation time 116069092 ps
CPU time 0.98 seconds
Started Jun 28 07:24:04 PM PDT 24
Finished Jun 28 07:24:13 PM PDT 24
Peak memory 205032 kb
Host smart-db5aa1f8-eb4f-4c3e-94a0-ddb9c8375567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290979786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1290979786
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3256891055
Short name T180
Test name
Test status
Simulation time 1489823108 ps
CPU time 4.31 seconds
Started Jun 28 07:23:59 PM PDT 24
Finished Jun 28 07:24:07 PM PDT 24
Peak memory 204908 kb
Host smart-ebd9813d-9f4d-43ae-8731-9df164ece445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256891055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3256891055
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1829044143
Short name T32
Test name
Test status
Simulation time 338502200 ps
CPU time 0.93 seconds
Started Jun 28 07:23:58 PM PDT 24
Finished Jun 28 07:24:02 PM PDT 24
Peak memory 204928 kb
Host smart-cf2a997f-f1b6-4ccc-9678-786dde4ede3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829044143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1829044143
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.1642037022
Short name T242
Test name
Test status
Simulation time 480027378 ps
CPU time 1.84 seconds
Started Jun 28 07:24:00 PM PDT 24
Finished Jun 28 07:24:08 PM PDT 24
Peak memory 204928 kb
Host smart-104d9f13-8df4-4357-8828-da41f5e769c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642037022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1642037022
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1056942857
Short name T56
Test name
Test status
Simulation time 588177622 ps
CPU time 2.31 seconds
Started Jun 28 07:24:01 PM PDT 24
Finished Jun 28 07:24:08 PM PDT 24
Peak memory 204852 kb
Host smart-9aa666ef-3ea3-47d0-95d7-9a8fa811fc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056942857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1056942857
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3000436853
Short name T51
Test name
Test status
Simulation time 142509233 ps
CPU time 1.03 seconds
Started Jun 28 07:24:01 PM PDT 24
Finished Jun 28 07:24:08 PM PDT 24
Peak memory 213176 kb
Host smart-ee4640b5-f8e7-4abf-90d1-5bd2f540936c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000436853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3000436853
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.344805541
Short name T275
Test name
Test status
Simulation time 788396701 ps
CPU time 2.66 seconds
Started Jun 28 07:24:01 PM PDT 24
Finished Jun 28 07:24:11 PM PDT 24
Peak memory 204912 kb
Host smart-b5439d0f-9a28-4f61-a7e4-5c02b6205e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344805541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.344805541
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1234784145
Short name T244
Test name
Test status
Simulation time 5393718686 ps
CPU time 5.02 seconds
Started Jun 28 07:23:28 PM PDT 24
Finished Jun 28 07:23:36 PM PDT 24
Peak memory 205336 kb
Host smart-5889a94e-f124-4b56-b363-3324bff3c9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234784145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1234784145
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.363372288
Short name T77
Test name
Test status
Simulation time 681159422 ps
CPU time 1.57 seconds
Started Jun 28 07:24:04 PM PDT 24
Finished Jun 28 07:24:14 PM PDT 24
Peak memory 237208 kb
Host smart-1dbbb1bf-4938-4f4e-8245-4ded6cd17850
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363372288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.363372288
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.418922815
Short name T265
Test name
Test status
Simulation time 3269703636 ps
CPU time 3.22 seconds
Started Jun 28 07:23:29 PM PDT 24
Finished Jun 28 07:23:36 PM PDT 24
Peak memory 204980 kb
Host smart-193cabe9-b361-40be-9fd8-e865417e35e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418922815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.418922815
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.880828296
Short name T270
Test name
Test status
Simulation time 98520458 ps
CPU time 0.94 seconds
Started Jun 28 07:24:30 PM PDT 24
Finished Jun 28 07:24:41 PM PDT 24
Peak memory 205044 kb
Host smart-d3112001-219f-4375-a337-985ed3a9b8d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880828296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.880828296
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.923908658
Short name T14
Test name
Test status
Simulation time 2857992764 ps
CPU time 3.47 seconds
Started Jun 28 07:24:32 PM PDT 24
Finished Jun 28 07:24:44 PM PDT 24
Peak memory 213488 kb
Host smart-ed82cd5d-aba1-409b-877d-f31262a0eaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923908658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.923908658
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3257679555
Short name T289
Test name
Test status
Simulation time 2251888363 ps
CPU time 7.98 seconds
Started Jun 28 07:24:35 PM PDT 24
Finished Jun 28 07:24:50 PM PDT 24
Peak memory 213512 kb
Host smart-dae38c50-9231-4cc0-9e33-1b0ff7add2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257679555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3257679555
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3962567214
Short name T222
Test name
Test status
Simulation time 1234342414 ps
CPU time 2.41 seconds
Started Jun 28 07:24:31 PM PDT 24
Finished Jun 28 07:24:43 PM PDT 24
Peak memory 213420 kb
Host smart-11d2502c-8872-407b-9d84-fd6af03f11e7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3962567214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3962567214
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.2486024628
Short name T229
Test name
Test status
Simulation time 13581633825 ps
CPU time 9.11 seconds
Started Jun 28 07:24:33 PM PDT 24
Finished Jun 28 07:24:50 PM PDT 24
Peak memory 213528 kb
Host smart-206ac30c-91bb-402f-b796-b28ae71c757d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486024628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.2486024628
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.4199886976
Short name T254
Test name
Test status
Simulation time 60346631 ps
CPU time 0.7 seconds
Started Jun 28 07:24:34 PM PDT 24
Finished Jun 28 07:24:42 PM PDT 24
Peak memory 204864 kb
Host smart-1763211c-4aab-4d25-b156-ae9235a9686b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199886976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.4199886976
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2390987784
Short name T251
Test name
Test status
Simulation time 4435197250 ps
CPU time 5.94 seconds
Started Jun 28 07:24:31 PM PDT 24
Finished Jun 28 07:24:46 PM PDT 24
Peak memory 213416 kb
Host smart-0e220894-f0c1-4199-842a-a6eeffee4ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390987784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2390987784
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3283528396
Short name T272
Test name
Test status
Simulation time 1652078648 ps
CPU time 4.04 seconds
Started Jun 28 07:24:32 PM PDT 24
Finished Jun 28 07:24:45 PM PDT 24
Peak memory 213464 kb
Host smart-70e1fc6c-cb21-4334-9911-5cece45ae098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283528396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3283528396
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2256868311
Short name T260
Test name
Test status
Simulation time 2146240783 ps
CPU time 7.41 seconds
Started Jun 28 07:24:31 PM PDT 24
Finished Jun 28 07:24:48 PM PDT 24
Peak memory 205224 kb
Host smart-a3a1e286-7574-4491-a40a-d5404c0d5d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256868311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2256868311
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3767565781
Short name T206
Test name
Test status
Simulation time 147776862 ps
CPU time 0.7 seconds
Started Jun 28 07:24:36 PM PDT 24
Finished Jun 28 07:24:43 PM PDT 24
Peak memory 204912 kb
Host smart-0941f334-f9c4-499a-8b6c-d6c4d0791016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767565781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3767565781
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.1136335589
Short name T145
Test name
Test status
Simulation time 20910106213 ps
CPU time 56.73 seconds
Started Jun 28 07:24:40 PM PDT 24
Finished Jun 28 07:25:41 PM PDT 24
Peak memory 213552 kb
Host smart-f414cd75-fd73-428a-8540-a7d91629124e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136335589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1136335589
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.918443069
Short name T276
Test name
Test status
Simulation time 5275428482 ps
CPU time 15 seconds
Started Jun 28 07:24:37 PM PDT 24
Finished Jun 28 07:24:58 PM PDT 24
Peak memory 213492 kb
Host smart-188d7b09-6772-4a59-ad79-bb9abcc4a1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918443069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.918443069
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.988239432
Short name T221
Test name
Test status
Simulation time 12952471018 ps
CPU time 6.99 seconds
Started Jun 28 07:24:33 PM PDT 24
Finished Jun 28 07:24:48 PM PDT 24
Peak memory 213468 kb
Host smart-4d696c95-9fa9-40d4-bf4d-5f15ab96b384
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988239432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.988239432
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3488747764
Short name T277
Test name
Test status
Simulation time 6850850534 ps
CPU time 5.82 seconds
Started Jun 28 07:24:35 PM PDT 24
Finished Jun 28 07:24:48 PM PDT 24
Peak memory 205280 kb
Host smart-71e97597-bd6b-4284-be24-a38ca3050364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488747764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3488747764
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.217404562
Short name T196
Test name
Test status
Simulation time 36325668 ps
CPU time 0.77 seconds
Started Jun 28 07:24:38 PM PDT 24
Finished Jun 28 07:24:44 PM PDT 24
Peak memory 204904 kb
Host smart-44ab965a-b6d8-4c90-99e8-d3ed4a621b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217404562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.217404562
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.591547802
Short name T214
Test name
Test status
Simulation time 1075642863 ps
CPU time 1.79 seconds
Started Jun 28 07:24:32 PM PDT 24
Finished Jun 28 07:24:42 PM PDT 24
Peak memory 205232 kb
Host smart-51d84fb0-cd8d-41ff-a168-8b70bae00bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591547802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.591547802
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.923070544
Short name T245
Test name
Test status
Simulation time 1657505830 ps
CPU time 4.87 seconds
Started Jun 28 07:24:41 PM PDT 24
Finished Jun 28 07:24:50 PM PDT 24
Peak memory 213240 kb
Host smart-d3345b96-f674-4221-9efa-a9550ba49abf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=923070544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.923070544
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3449507127
Short name T271
Test name
Test status
Simulation time 1852587005 ps
CPU time 3.44 seconds
Started Jun 28 07:24:32 PM PDT 24
Finished Jun 28 07:24:44 PM PDT 24
Peak memory 205256 kb
Host smart-7cf345f4-cb44-46fb-b13f-49167c87439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449507127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3449507127
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2058945266
Short name T278
Test name
Test status
Simulation time 118604502 ps
CPU time 0.85 seconds
Started Jun 28 07:24:52 PM PDT 24
Finished Jun 28 07:24:54 PM PDT 24
Peak memory 204920 kb
Host smart-db1056bb-3efd-4c69-a105-1d4383434e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058945266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2058945266
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2614547617
Short name T257
Test name
Test status
Simulation time 6649461932 ps
CPU time 10.21 seconds
Started Jun 28 07:24:45 PM PDT 24
Finished Jun 28 07:24:57 PM PDT 24
Peak memory 213620 kb
Host smart-d19d2fbf-68fa-4682-8a3b-63027b8af7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614547617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2614547617
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3686221009
Short name T85
Test name
Test status
Simulation time 6339345145 ps
CPU time 3.03 seconds
Started Jun 28 07:24:43 PM PDT 24
Finished Jun 28 07:24:49 PM PDT 24
Peak memory 213468 kb
Host smart-3166d952-d9ff-4253-8b93-d2fd0261d99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686221009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3686221009
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3959381870
Short name T246
Test name
Test status
Simulation time 5601419136 ps
CPU time 11.89 seconds
Started Jun 28 07:24:38 PM PDT 24
Finished Jun 28 07:24:55 PM PDT 24
Peak memory 213452 kb
Host smart-dedeac4d-5110-4373-902e-1e552c0b8ce7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3959381870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3959381870
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.310002451
Short name T164
Test name
Test status
Simulation time 4069320218 ps
CPU time 11.66 seconds
Started Jun 28 07:24:34 PM PDT 24
Finished Jun 28 07:24:53 PM PDT 24
Peak memory 213492 kb
Host smart-154e3d9b-b6cc-4cd6-89ff-6ce74c20ed84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310002451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.310002451
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.237090325
Short name T208
Test name
Test status
Simulation time 47135960 ps
CPU time 0.7 seconds
Started Jun 28 07:24:45 PM PDT 24
Finished Jun 28 07:24:48 PM PDT 24
Peak memory 204908 kb
Host smart-ab5e8313-f51c-4de4-bd55-9310ac4fe084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237090325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.237090325
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3467358099
Short name T67
Test name
Test status
Simulation time 7572070730 ps
CPU time 18.9 seconds
Started Jun 28 07:24:42 PM PDT 24
Finished Jun 28 07:25:04 PM PDT 24
Peak memory 215652 kb
Host smart-aef1aee0-5943-4ec9-bd79-0f4c28d3e670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467358099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3467358099
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3511264799
Short name T282
Test name
Test status
Simulation time 1397717955 ps
CPU time 2.68 seconds
Started Jun 28 07:24:45 PM PDT 24
Finished Jun 28 07:24:50 PM PDT 24
Peak memory 213360 kb
Host smart-002b28ce-755a-4005-91ce-56b7703159b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511264799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3511264799
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3023670634
Short name T264
Test name
Test status
Simulation time 3515661175 ps
CPU time 2.75 seconds
Started Jun 28 07:24:52 PM PDT 24
Finished Jun 28 07:24:56 PM PDT 24
Peak memory 213540 kb
Host smart-4ad39ff1-0da2-4f4a-bff9-2221b465f368
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3023670634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3023670634
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1779709514
Short name T227
Test name
Test status
Simulation time 4598533579 ps
CPU time 13.05 seconds
Started Jun 28 07:24:43 PM PDT 24
Finished Jun 28 07:24:59 PM PDT 24
Peak memory 213540 kb
Host smart-b1e1d0da-c651-4ba3-af4e-015295447487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779709514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1779709514
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.3417288425
Short name T8
Test name
Test status
Simulation time 4424058925 ps
CPU time 4.35 seconds
Started Jun 28 07:24:45 PM PDT 24
Finished Jun 28 07:24:51 PM PDT 24
Peak memory 213556 kb
Host smart-08bc8e27-9f58-4143-97f2-97d9652d3fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417288425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3417288425
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3883901730
Short name T212
Test name
Test status
Simulation time 34933013 ps
CPU time 0.74 seconds
Started Jun 28 07:24:45 PM PDT 24
Finished Jun 28 07:24:48 PM PDT 24
Peak memory 204924 kb
Host smart-de3678eb-93f1-43fe-acc5-46187c3eca36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883901730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3883901730
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3030309347
Short name T226
Test name
Test status
Simulation time 5213615104 ps
CPU time 14.92 seconds
Started Jun 28 07:24:43 PM PDT 24
Finished Jun 28 07:25:01 PM PDT 24
Peak memory 213476 kb
Host smart-70eee8f4-4330-48d0-8861-4d903cbfb6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030309347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3030309347
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1834693551
Short name T225
Test name
Test status
Simulation time 3038618342 ps
CPU time 1.74 seconds
Started Jun 28 07:24:44 PM PDT 24
Finished Jun 28 07:24:48 PM PDT 24
Peak memory 213544 kb
Host smart-24e1b204-2273-4bca-9c92-28b8a996388c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1834693551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1834693551
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1589502763
Short name T267
Test name
Test status
Simulation time 9399669854 ps
CPU time 12.35 seconds
Started Jun 28 07:24:46 PM PDT 24
Finished Jun 28 07:25:00 PM PDT 24
Peak memory 205452 kb
Host smart-5aed6b91-de57-407d-86e1-e8de60e99729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589502763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1589502763
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.977554176
Short name T179
Test name
Test status
Simulation time 7041048056 ps
CPU time 20.63 seconds
Started Jun 28 07:24:45 PM PDT 24
Finished Jun 28 07:25:07 PM PDT 24
Peak memory 213444 kb
Host smart-e36dd022-fa95-4e45-bf35-e432fefb376d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977554176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.977554176
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1612689614
Short name T236
Test name
Test status
Simulation time 38238220 ps
CPU time 0.79 seconds
Started Jun 28 07:24:59 PM PDT 24
Finished Jun 28 07:25:03 PM PDT 24
Peak memory 204928 kb
Host smart-88fe4974-ea03-4b2d-9126-984328ffc4dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612689614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1612689614
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1333304269
Short name T256
Test name
Test status
Simulation time 8202494362 ps
CPU time 16.91 seconds
Started Jun 28 07:24:58 PM PDT 24
Finished Jun 28 07:25:19 PM PDT 24
Peak memory 213484 kb
Host smart-30a89571-e7fd-477c-b69c-e4c15cb7f261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333304269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1333304269
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.353902570
Short name T79
Test name
Test status
Simulation time 1955407841 ps
CPU time 5.57 seconds
Started Jun 28 07:25:00 PM PDT 24
Finished Jun 28 07:25:10 PM PDT 24
Peak memory 205348 kb
Host smart-5e283be0-618f-4fd1-b134-3397a5e254de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353902570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.353902570
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3897654572
Short name T279
Test name
Test status
Simulation time 2823740972 ps
CPU time 3.15 seconds
Started Jun 28 07:24:52 PM PDT 24
Finished Jun 28 07:24:56 PM PDT 24
Peak memory 213480 kb
Host smart-e615f9f6-0da1-42b2-b6b5-9ae9d90259ff
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3897654572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3897654572
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1845610979
Short name T13
Test name
Test status
Simulation time 7026976323 ps
CPU time 10.87 seconds
Started Jun 28 07:24:45 PM PDT 24
Finished Jun 28 07:24:58 PM PDT 24
Peak memory 213488 kb
Host smart-3f5b7508-272b-41ca-8b1c-1c33f5f892ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845610979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1845610979
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.895765131
Short name T178
Test name
Test status
Simulation time 6421144280 ps
CPU time 11.25 seconds
Started Jun 28 07:24:59 PM PDT 24
Finished Jun 28 07:25:15 PM PDT 24
Peak memory 213352 kb
Host smart-412c837f-3d77-4cd5-a984-590000a94ed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895765131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.895765131
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.469839048
Short name T134
Test name
Test status
Simulation time 208266040 ps
CPU time 0.68 seconds
Started Jun 28 07:25:00 PM PDT 24
Finished Jun 28 07:25:05 PM PDT 24
Peak memory 204900 kb
Host smart-26b442f5-fd3a-4917-837d-884986edafe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469839048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.469839048
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.938311987
Short name T288
Test name
Test status
Simulation time 10687937474 ps
CPU time 7.86 seconds
Started Jun 28 07:24:57 PM PDT 24
Finished Jun 28 07:25:07 PM PDT 24
Peak memory 213484 kb
Host smart-0bf99c99-b0b8-4efc-95d0-53c59465eb62
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=938311987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.938311987
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1050130577
Short name T46
Test name
Test status
Simulation time 3860969815 ps
CPU time 10.98 seconds
Started Jun 28 07:24:59 PM PDT 24
Finished Jun 28 07:25:14 PM PDT 24
Peak memory 213516 kb
Host smart-12c7641e-3b51-45b8-87db-2aa5ad3293d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050130577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1050130577
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.1907198473
Short name T38
Test name
Test status
Simulation time 8885158178 ps
CPU time 13 seconds
Started Jun 28 07:24:58 PM PDT 24
Finished Jun 28 07:25:14 PM PDT 24
Peak memory 213364 kb
Host smart-0b393afb-36ad-4c59-8ae5-f175612a53fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907198473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.1907198473
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1840308554
Short name T235
Test name
Test status
Simulation time 82359709 ps
CPU time 0.72 seconds
Started Jun 28 07:24:59 PM PDT 24
Finished Jun 28 07:25:04 PM PDT 24
Peak memory 204928 kb
Host smart-c41b4eaa-5d4c-4752-9931-e6be660e2373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840308554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1840308554
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3963327952
Short name T207
Test name
Test status
Simulation time 17175635575 ps
CPU time 35.51 seconds
Started Jun 28 07:25:02 PM PDT 24
Finished Jun 28 07:25:42 PM PDT 24
Peak memory 213448 kb
Host smart-e8fd59fe-1e66-4e7c-aaea-b459669e2310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963327952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3963327952
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1905294973
Short name T262
Test name
Test status
Simulation time 6145010257 ps
CPU time 3.13 seconds
Started Jun 28 07:24:59 PM PDT 24
Finished Jun 28 07:25:07 PM PDT 24
Peak memory 205256 kb
Host smart-9a96b5c8-6f38-481c-9283-74beaf1a4af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905294973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1905294973
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.42199123
Short name T253
Test name
Test status
Simulation time 3051481418 ps
CPU time 5.63 seconds
Started Jun 28 07:25:02 PM PDT 24
Finished Jun 28 07:25:12 PM PDT 24
Peak memory 213472 kb
Host smart-1a3f6905-6513-41f5-bed9-85d6b2fe536b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42199123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_tl
_access.42199123
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3292828996
Short name T243
Test name
Test status
Simulation time 2347838093 ps
CPU time 4.73 seconds
Started Jun 28 07:24:59 PM PDT 24
Finished Jun 28 07:25:07 PM PDT 24
Peak memory 213540 kb
Host smart-09b2a2f1-afb8-40e8-bb24-4de89dd2bff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292828996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3292828996
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.1546953316
Short name T151
Test name
Test status
Simulation time 7947396852 ps
CPU time 18.48 seconds
Started Jun 28 07:24:57 PM PDT 24
Finished Jun 28 07:25:16 PM PDT 24
Peak memory 205164 kb
Host smart-1f63dd84-b588-4e2b-a1a7-e029cbae107c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546953316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1546953316
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1197977803
Short name T2
Test name
Test status
Simulation time 213534646 ps
CPU time 0.95 seconds
Started Jun 28 07:24:05 PM PDT 24
Finished Jun 28 07:24:16 PM PDT 24
Peak memory 204928 kb
Host smart-0c9b65fa-86ea-450f-93e4-9ef9ee1edb14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197977803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1197977803
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.2932024512
Short name T211
Test name
Test status
Simulation time 5385438950 ps
CPU time 4.49 seconds
Started Jun 28 07:24:02 PM PDT 24
Finished Jun 28 07:24:14 PM PDT 24
Peak memory 213532 kb
Host smart-052f8903-07c5-40b5-8132-e4d802246672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932024512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2932024512
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1875178559
Short name T41
Test name
Test status
Simulation time 8664953970 ps
CPU time 3.72 seconds
Started Jun 28 07:24:02 PM PDT 24
Finished Jun 28 07:24:14 PM PDT 24
Peak memory 213472 kb
Host smart-85ecd2c9-1c04-4896-9733-bb88054bb8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875178559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1875178559
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3423700716
Short name T149
Test name
Test status
Simulation time 1315199871 ps
CPU time 1.96 seconds
Started Jun 28 07:24:03 PM PDT 24
Finished Jun 28 07:24:14 PM PDT 24
Peak memory 213736 kb
Host smart-7f6d96a3-54b2-41af-a2e2-91bdd6544c38
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423700716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3423700716
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2016770842
Short name T213
Test name
Test status
Simulation time 187049497 ps
CPU time 1.19 seconds
Started Jun 28 07:24:04 PM PDT 24
Finished Jun 28 07:24:14 PM PDT 24
Peak memory 204912 kb
Host smart-1392b283-c9e3-4131-85e8-8dd6d8472217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016770842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2016770842
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1379789065
Short name T83
Test name
Test status
Simulation time 4079363927 ps
CPU time 12.44 seconds
Started Jun 28 07:24:01 PM PDT 24
Finished Jun 28 07:24:20 PM PDT 24
Peak memory 213512 kb
Host smart-4e14ba2f-dc27-456c-9348-911d2b7b1aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379789065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1379789065
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1322159934
Short name T66
Test name
Test status
Simulation time 595583228 ps
CPU time 2.59 seconds
Started Jun 28 07:24:04 PM PDT 24
Finished Jun 28 07:24:15 PM PDT 24
Peak memory 237420 kb
Host smart-b5ebdccb-1f42-4db0-bb23-b596d9827bdd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322159934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1322159934
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.3810273212
Short name T187
Test name
Test status
Simulation time 6855978316 ps
CPU time 12.19 seconds
Started Jun 28 07:24:02 PM PDT 24
Finished Jun 28 07:24:21 PM PDT 24
Peak memory 205140 kb
Host smart-61156540-7635-4249-a08e-8816c7702278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810273212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3810273212
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2192089104
Short name T224
Test name
Test status
Simulation time 86380656 ps
CPU time 0.81 seconds
Started Jun 28 07:24:59 PM PDT 24
Finished Jun 28 07:25:04 PM PDT 24
Peak memory 204832 kb
Host smart-82d952a9-17ba-4d62-b80c-6d068c146563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192089104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2192089104
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.567587053
Short name T23
Test name
Test status
Simulation time 8376915491 ps
CPU time 5.78 seconds
Started Jun 28 07:24:58 PM PDT 24
Finished Jun 28 07:25:07 PM PDT 24
Peak memory 205096 kb
Host smart-0f50e313-2dbc-45f2-b024-2dfac29c1a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567587053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.567587053
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1203017623
Short name T3
Test name
Test status
Simulation time 121015272 ps
CPU time 0.71 seconds
Started Jun 28 07:24:59 PM PDT 24
Finished Jun 28 07:25:04 PM PDT 24
Peak memory 204904 kb
Host smart-646a848c-01ba-4e45-a660-49e7e26411ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203017623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1203017623
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.3102699298
Short name T177
Test name
Test status
Simulation time 5499253527 ps
CPU time 5.53 seconds
Started Jun 28 07:24:59 PM PDT 24
Finished Jun 28 07:25:10 PM PDT 24
Peak memory 205216 kb
Host smart-fb6ef7bd-7617-41c4-852f-2c7fcb8f9aba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102699298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3102699298
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3495596981
Short name T35
Test name
Test status
Simulation time 162255630 ps
CPU time 0.79 seconds
Started Jun 28 07:25:02 PM PDT 24
Finished Jun 28 07:25:07 PM PDT 24
Peak memory 204936 kb
Host smart-dee90c81-8986-4b1d-807a-b172f2c2beb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495596981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3495596981
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1586285320
Short name T286
Test name
Test status
Simulation time 140996423 ps
CPU time 0.91 seconds
Started Jun 28 07:25:01 PM PDT 24
Finished Jun 28 07:25:07 PM PDT 24
Peak memory 205044 kb
Host smart-91fc9f37-5aa8-4e74-8cb7-42e189480b08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586285320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1586285320
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.524621815
Short name T82
Test name
Test status
Simulation time 45379068 ps
CPU time 0.73 seconds
Started Jun 28 07:25:00 PM PDT 24
Finished Jun 28 07:25:05 PM PDT 24
Peak memory 204876 kb
Host smart-6b5c4d71-b023-4e8b-824b-77ff860ab500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524621815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.524621815
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.3327832143
Short name T12
Test name
Test status
Simulation time 2536612617 ps
CPU time 2.77 seconds
Started Jun 28 07:25:01 PM PDT 24
Finished Jun 28 07:25:09 PM PDT 24
Peak memory 205176 kb
Host smart-dc3e95d9-492d-4ef3-ab38-3ca53ebf636d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327832143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.3327832143
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2685505953
Short name T81
Test name
Test status
Simulation time 70450994 ps
CPU time 0.73 seconds
Started Jun 28 07:25:00 PM PDT 24
Finished Jun 28 07:25:05 PM PDT 24
Peak memory 204864 kb
Host smart-df1e978e-178e-4510-b159-6bdc7e282b7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685505953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2685505953
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.599277605
Short name T273
Test name
Test status
Simulation time 63080120 ps
CPU time 0.72 seconds
Started Jun 28 07:24:59 PM PDT 24
Finished Jun 28 07:25:03 PM PDT 24
Peak memory 204920 kb
Host smart-c87fd110-bba4-4853-91f8-47ec0e930896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599277605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.599277605
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.3189591307
Short name T162
Test name
Test status
Simulation time 6789114495 ps
CPU time 16.5 seconds
Started Jun 28 07:24:57 PM PDT 24
Finished Jun 28 07:25:15 PM PDT 24
Peak memory 205196 kb
Host smart-1dec61df-8f61-438c-895e-deab3cfc4c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189591307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3189591307
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1530704360
Short name T197
Test name
Test status
Simulation time 79524265 ps
CPU time 0.71 seconds
Started Jun 28 07:24:58 PM PDT 24
Finished Jun 28 07:25:03 PM PDT 24
Peak memory 205020 kb
Host smart-3b375a53-37c2-4468-8d24-be6a8b056428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530704360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1530704360
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.1471155883
Short name T185
Test name
Test status
Simulation time 4285439657 ps
CPU time 4.37 seconds
Started Jun 28 07:24:58 PM PDT 24
Finished Jun 28 07:25:05 PM PDT 24
Peak memory 213352 kb
Host smart-e3624fb4-469e-413d-a612-e7ab3e5d6006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471155883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1471155883
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.4243942321
Short name T40
Test name
Test status
Simulation time 64923402 ps
CPU time 0.75 seconds
Started Jun 28 07:24:58 PM PDT 24
Finished Jun 28 07:25:02 PM PDT 24
Peak memory 204904 kb
Host smart-6de8a403-d4f7-4abb-8bf4-2e374c62882c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243942321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4243942321
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.282348836
Short name T150
Test name
Test status
Simulation time 11098186739 ps
CPU time 4.58 seconds
Started Jun 28 07:24:59 PM PDT 24
Finished Jun 28 07:25:08 PM PDT 24
Peak memory 213412 kb
Host smart-4cb4a51e-9781-4af4-a1a2-29818b25f18a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282348836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.282348836
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2563628394
Short name T263
Test name
Test status
Simulation time 121038947 ps
CPU time 0.89 seconds
Started Jun 28 07:24:58 PM PDT 24
Finished Jun 28 07:25:01 PM PDT 24
Peak memory 204908 kb
Host smart-074c1620-3393-4132-9df2-f79795104bd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563628394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2563628394
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.1845817551
Short name T184
Test name
Test status
Simulation time 2974739196 ps
CPU time 4.16 seconds
Started Jun 28 07:24:58 PM PDT 24
Finished Jun 28 07:25:06 PM PDT 24
Peak memory 205204 kb
Host smart-fd69617f-b15e-489f-ac47-2e7437af08bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845817551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1845817551
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1491491085
Short name T237
Test name
Test status
Simulation time 115049717 ps
CPU time 0.75 seconds
Started Jun 28 07:24:05 PM PDT 24
Finished Jun 28 07:24:14 PM PDT 24
Peak memory 204916 kb
Host smart-1975c68b-030e-416a-981c-e9e2fe501e38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491491085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1491491085
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.398281898
Short name T233
Test name
Test status
Simulation time 84205447968 ps
CPU time 116.38 seconds
Started Jun 28 07:24:06 PM PDT 24
Finished Jun 28 07:26:13 PM PDT 24
Peak memory 213508 kb
Host smart-765a770d-6df3-4c7d-8ada-7ac48dd3c472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398281898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.398281898
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3917786057
Short name T281
Test name
Test status
Simulation time 3062888927 ps
CPU time 7.37 seconds
Started Jun 28 07:24:04 PM PDT 24
Finished Jun 28 07:24:21 PM PDT 24
Peak memory 213572 kb
Host smart-584a5d18-0f2c-4fef-82ad-3688be80fe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917786057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3917786057
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2918686205
Short name T232
Test name
Test status
Simulation time 5716814531 ps
CPU time 5.48 seconds
Started Jun 28 07:24:03 PM PDT 24
Finished Jun 28 07:24:17 PM PDT 24
Peak memory 213540 kb
Host smart-8cb79c2b-a6b8-4983-a4b0-90d830e8fd70
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2918686205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2918686205
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2233776071
Short name T230
Test name
Test status
Simulation time 154458976 ps
CPU time 0.89 seconds
Started Jun 28 07:24:04 PM PDT 24
Finished Jun 28 07:24:13 PM PDT 24
Peak memory 204908 kb
Host smart-1d77de00-7a07-4762-b516-0c083c1188ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233776071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2233776071
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1209229596
Short name T228
Test name
Test status
Simulation time 1315394827 ps
CPU time 1.78 seconds
Started Jun 28 07:24:04 PM PDT 24
Finished Jun 28 07:24:15 PM PDT 24
Peak memory 213472 kb
Host smart-88ef4916-23f2-44a6-bc8e-23b03b77b664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209229596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1209229596
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1519846346
Short name T65
Test name
Test status
Simulation time 658021897 ps
CPU time 1.41 seconds
Started Jun 28 07:24:06 PM PDT 24
Finished Jun 28 07:24:18 PM PDT 24
Peak memory 237472 kb
Host smart-bf121a6c-6145-4422-84d4-76820057c8a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519846346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1519846346
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.272636856
Short name T153
Test name
Test status
Simulation time 8595688376 ps
CPU time 12.57 seconds
Started Jun 28 07:24:01 PM PDT 24
Finished Jun 28 07:24:20 PM PDT 24
Peak memory 214800 kb
Host smart-ca860095-b753-4493-b0d2-ca73b1f6c1e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272636856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.272636856
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.834830848
Short name T199
Test name
Test status
Simulation time 82518557 ps
CPU time 0.71 seconds
Started Jun 28 07:25:18 PM PDT 24
Finished Jun 28 07:25:24 PM PDT 24
Peak memory 204912 kb
Host smart-cb1d635f-e963-4448-a995-e59c7a5201fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834830848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.834830848
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.1990549785
Short name T190
Test name
Test status
Simulation time 11619741897 ps
CPU time 31.64 seconds
Started Jun 28 07:24:57 PM PDT 24
Finished Jun 28 07:25:31 PM PDT 24
Peak memory 213368 kb
Host smart-c6021b0e-6983-4e4b-b7c6-74432557ec2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990549785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1990549785
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2738568097
Short name T203
Test name
Test status
Simulation time 48422684 ps
CPU time 0.76 seconds
Started Jun 28 07:25:12 PM PDT 24
Finished Jun 28 07:25:15 PM PDT 24
Peak memory 204932 kb
Host smart-68b13d05-7911-4a1b-84be-16dce5d1d07e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738568097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2738568097
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2322981991
Short name T239
Test name
Test status
Simulation time 123560111 ps
CPU time 1.09 seconds
Started Jun 28 07:25:14 PM PDT 24
Finished Jun 28 07:25:18 PM PDT 24
Peak memory 204916 kb
Host smart-79bdf414-c861-4ae2-9195-0c99e16a4a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322981991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2322981991
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2118446129
Short name T241
Test name
Test status
Simulation time 59795364 ps
CPU time 0.7 seconds
Started Jun 28 07:25:17 PM PDT 24
Finished Jun 28 07:25:23 PM PDT 24
Peak memory 204920 kb
Host smart-9b13415e-861d-4828-8d21-70e87eddbca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118446129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2118446129
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.994285358
Short name T148
Test name
Test status
Simulation time 4864523781 ps
CPU time 5.74 seconds
Started Jun 28 07:25:14 PM PDT 24
Finished Jun 28 07:25:22 PM PDT 24
Peak memory 213412 kb
Host smart-e8f77d5c-09cb-4139-adbd-ac30660b7c95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994285358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.994285358
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3457445059
Short name T205
Test name
Test status
Simulation time 55923451 ps
CPU time 0.77 seconds
Started Jun 28 07:25:16 PM PDT 24
Finished Jun 28 07:25:21 PM PDT 24
Peak memory 204924 kb
Host smart-c9ae2f80-dae8-4923-b7a9-f5792280d68d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457445059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3457445059
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2914266838
Short name T15
Test name
Test status
Simulation time 1710770962 ps
CPU time 2.55 seconds
Started Jun 28 07:25:18 PM PDT 24
Finished Jun 28 07:25:27 PM PDT 24
Peak memory 213320 kb
Host smart-881d1126-7950-4c89-8b38-f13acaf3d1d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914266838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2914266838
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3099919337
Short name T261
Test name
Test status
Simulation time 142576026 ps
CPU time 0.98 seconds
Started Jun 28 07:25:16 PM PDT 24
Finished Jun 28 07:25:22 PM PDT 24
Peak memory 204920 kb
Host smart-eaf34922-5d6d-4300-ab07-f0dbe6e76e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099919337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3099919337
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.962536215
Short name T209
Test name
Test status
Simulation time 81048715 ps
CPU time 0.72 seconds
Started Jun 28 07:25:14 PM PDT 24
Finished Jun 28 07:25:17 PM PDT 24
Peak memory 204932 kb
Host smart-a1c194f2-798a-4a45-9972-32a008191271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962536215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.962536215
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.515681315
Short name T10
Test name
Test status
Simulation time 9196305876 ps
CPU time 22.07 seconds
Started Jun 28 07:25:16 PM PDT 24
Finished Jun 28 07:25:41 PM PDT 24
Peak memory 214800 kb
Host smart-4bbbcafa-4f4b-4e31-9454-e6dcb1108c0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515681315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.515681315
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2416118758
Short name T76
Test name
Test status
Simulation time 31615014 ps
CPU time 0.82 seconds
Started Jun 28 07:25:15 PM PDT 24
Finished Jun 28 07:25:19 PM PDT 24
Peak memory 204928 kb
Host smart-4a0889f0-fdec-4f7f-b742-0bbc2292fe05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416118758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2416118758
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2358805163
Short name T194
Test name
Test status
Simulation time 52922588 ps
CPU time 0.72 seconds
Started Jun 28 07:25:13 PM PDT 24
Finished Jun 28 07:25:16 PM PDT 24
Peak memory 204920 kb
Host smart-52b125c7-8dd6-4287-8cd7-ba8bbe631b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358805163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2358805163
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.823579229
Short name T182
Test name
Test status
Simulation time 3536582736 ps
CPU time 9.64 seconds
Started Jun 28 07:25:15 PM PDT 24
Finished Jun 28 07:25:27 PM PDT 24
Peak memory 213364 kb
Host smart-fb69b14f-63e4-46da-a473-4e4e48bde7a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823579229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.823579229
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.582174728
Short name T219
Test name
Test status
Simulation time 219866822 ps
CPU time 0.73 seconds
Started Jun 28 07:25:15 PM PDT 24
Finished Jun 28 07:25:19 PM PDT 24
Peak memory 204928 kb
Host smart-96c75c8d-4757-41f0-9595-7cd6afada07f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582174728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.582174728
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.2240898508
Short name T5
Test name
Test status
Simulation time 18853660504 ps
CPU time 44.52 seconds
Started Jun 28 07:25:17 PM PDT 24
Finished Jun 28 07:26:07 PM PDT 24
Peak memory 213288 kb
Host smart-5c1fc569-2011-4f7c-834e-61c31a97df4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240898508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.2240898508
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3756850764
Short name T193
Test name
Test status
Simulation time 122254759 ps
CPU time 0.92 seconds
Started Jun 28 07:24:19 PM PDT 24
Finished Jun 28 07:24:34 PM PDT 24
Peak memory 204900 kb
Host smart-389fed93-62c8-4069-875a-0d888ad52dda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756850764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3756850764
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.776855712
Short name T259
Test name
Test status
Simulation time 2941979381 ps
CPU time 7.06 seconds
Started Jun 28 07:24:15 PM PDT 24
Finished Jun 28 07:24:36 PM PDT 24
Peak memory 213568 kb
Host smart-bac2f19b-a98d-4b76-8259-a40279bf33d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776855712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.776855712
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.708273607
Short name T49
Test name
Test status
Simulation time 2027302345 ps
CPU time 3.84 seconds
Started Jun 28 07:24:04 PM PDT 24
Finished Jun 28 07:24:16 PM PDT 24
Peak memory 205288 kb
Host smart-3a0ed379-cabb-4b0f-95d5-6afd3e081df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708273607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.708273607
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1369257624
Short name T283
Test name
Test status
Simulation time 1697202233 ps
CPU time 1.48 seconds
Started Jun 28 07:24:01 PM PDT 24
Finished Jun 28 07:24:09 PM PDT 24
Peak memory 205308 kb
Host smart-bb450159-484d-4050-8743-5deac7d0e4ff
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369257624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1369257624
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1209519289
Short name T250
Test name
Test status
Simulation time 92703242 ps
CPU time 0.78 seconds
Started Jun 28 07:24:17 PM PDT 24
Finished Jun 28 07:24:31 PM PDT 24
Peak memory 204864 kb
Host smart-5efb9df9-a254-4807-a07a-fd04fa9d44d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209519289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1209519289
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.137580195
Short name T274
Test name
Test status
Simulation time 893667615 ps
CPU time 3.05 seconds
Started Jun 28 07:24:03 PM PDT 24
Finished Jun 28 07:24:15 PM PDT 24
Peak memory 205220 kb
Host smart-0b3675f1-ee24-4c76-8830-6aac9c79b0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137580195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.137580195
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.30063659
Short name T160
Test name
Test status
Simulation time 17963591491 ps
CPU time 13.03 seconds
Started Jun 28 07:24:14 PM PDT 24
Finished Jun 28 07:24:41 PM PDT 24
Peak memory 213388 kb
Host smart-9d68f73f-e582-4049-9ab1-da137e0c6db7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30063659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.30063659
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2749363849
Short name T220
Test name
Test status
Simulation time 122786597 ps
CPU time 0.83 seconds
Started Jun 28 07:25:16 PM PDT 24
Finished Jun 28 07:25:20 PM PDT 24
Peak memory 204920 kb
Host smart-aacf03a7-2725-4984-9c32-ebef8f3cc14f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749363849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2749363849
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.1691127564
Short name T163
Test name
Test status
Simulation time 14258840041 ps
CPU time 13.09 seconds
Started Jun 28 07:25:18 PM PDT 24
Finished Jun 28 07:25:37 PM PDT 24
Peak memory 205148 kb
Host smart-49536b33-2efa-4d4b-9de2-4a1131cc1429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691127564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1691127564
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2349366396
Short name T217
Test name
Test status
Simulation time 64673504 ps
CPU time 0.74 seconds
Started Jun 28 07:25:15 PM PDT 24
Finished Jun 28 07:25:19 PM PDT 24
Peak memory 204892 kb
Host smart-af795e87-1c6c-4d49-a245-ba6c4e4fe82f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349366396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2349366396
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.1132955171
Short name T191
Test name
Test status
Simulation time 4778751461 ps
CPU time 5.53 seconds
Started Jun 28 07:25:15 PM PDT 24
Finished Jun 28 07:25:24 PM PDT 24
Peak memory 213416 kb
Host smart-0115b878-cbcc-4560-a0bb-87a1cb8a9e65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132955171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1132955171
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3577183854
Short name T291
Test name
Test status
Simulation time 106841843 ps
CPU time 0.96 seconds
Started Jun 28 07:25:14 PM PDT 24
Finished Jun 28 07:25:17 PM PDT 24
Peak memory 204924 kb
Host smart-87918e08-3faf-4122-8209-e90d161eaa08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577183854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3577183854
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.2118272391
Short name T22
Test name
Test status
Simulation time 9816698926 ps
CPU time 15.57 seconds
Started Jun 28 07:25:17 PM PDT 24
Finished Jun 28 07:25:37 PM PDT 24
Peak memory 205140 kb
Host smart-aee5dad7-bd5f-4052-9abe-caa7a93f0da2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118272391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2118272391
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.830353147
Short name T84
Test name
Test status
Simulation time 103442695 ps
CPU time 0.96 seconds
Started Jun 28 07:25:19 PM PDT 24
Finished Jun 28 07:25:26 PM PDT 24
Peak memory 204904 kb
Host smart-ac4d83fc-1677-43e0-9fea-7a2408c73347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830353147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.830353147
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.3636741126
Short name T159
Test name
Test status
Simulation time 11186246418 ps
CPU time 4.07 seconds
Started Jun 28 07:25:18 PM PDT 24
Finished Jun 28 07:25:29 PM PDT 24
Peak memory 213420 kb
Host smart-ab517894-729c-43d4-994a-c6e82805b881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636741126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3636741126
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1556070234
Short name T202
Test name
Test status
Simulation time 115113720 ps
CPU time 0.72 seconds
Started Jun 28 07:25:17 PM PDT 24
Finished Jun 28 07:25:23 PM PDT 24
Peak memory 204868 kb
Host smart-b2b51c27-89cc-4f7b-b17c-2c46da8e9740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556070234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1556070234
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.2408101321
Short name T21
Test name
Test status
Simulation time 4187229638 ps
CPU time 3.89 seconds
Started Jun 28 07:25:17 PM PDT 24
Finished Jun 28 07:25:27 PM PDT 24
Peak memory 213444 kb
Host smart-04701851-eaf5-47ad-9262-e29082493334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408101321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2408101321
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2281493587
Short name T132
Test name
Test status
Simulation time 66414259 ps
CPU time 0.8 seconds
Started Jun 28 07:25:17 PM PDT 24
Finished Jun 28 07:25:23 PM PDT 24
Peak memory 204924 kb
Host smart-5cf5d727-000a-4150-b7cd-888b3e9a4b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281493587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2281493587
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.2401428085
Short name T155
Test name
Test status
Simulation time 4979896957 ps
CPU time 14.09 seconds
Started Jun 28 07:25:17 PM PDT 24
Finished Jun 28 07:25:37 PM PDT 24
Peak memory 213344 kb
Host smart-c25dc567-febf-4bf1-a5ee-cdeb855c28bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401428085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.2401428085
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1626277038
Short name T234
Test name
Test status
Simulation time 46702856 ps
CPU time 0.75 seconds
Started Jun 28 07:25:34 PM PDT 24
Finished Jun 28 07:25:40 PM PDT 24
Peak memory 204924 kb
Host smart-52acf939-7bde-4725-9645-c1955df84879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626277038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1626277038
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.1244443238
Short name T11
Test name
Test status
Simulation time 6556473385 ps
CPU time 18.77 seconds
Started Jun 28 07:25:14 PM PDT 24
Finished Jun 28 07:25:35 PM PDT 24
Peak memory 213328 kb
Host smart-c27c69f5-27e7-4079-94dc-59862bb4d3cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244443238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1244443238
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.999891901
Short name T29
Test name
Test status
Simulation time 5614689990 ps
CPU time 7.24 seconds
Started Jun 28 07:25:32 PM PDT 24
Finished Jun 28 07:25:43 PM PDT 24
Peak memory 205128 kb
Host smart-d9c8b37f-090a-445d-a267-89ac8f9fd246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999891901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.999891901
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1234312605
Short name T39
Test name
Test status
Simulation time 60863387 ps
CPU time 0.67 seconds
Started Jun 28 07:25:31 PM PDT 24
Finished Jun 28 07:25:35 PM PDT 24
Peak memory 204924 kb
Host smart-5baf7f11-af05-4f91-907a-b411ff74d5f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234312605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1234312605
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.1210834256
Short name T165
Test name
Test status
Simulation time 7560017601 ps
CPU time 6.83 seconds
Started Jun 28 07:25:32 PM PDT 24
Finished Jun 28 07:25:43 PM PDT 24
Peak memory 213348 kb
Host smart-afe1b43c-837d-458f-96d5-677659dff138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210834256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1210834256
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2041273860
Short name T201
Test name
Test status
Simulation time 147253078 ps
CPU time 1 seconds
Started Jun 28 07:25:31 PM PDT 24
Finished Jun 28 07:25:35 PM PDT 24
Peak memory 204920 kb
Host smart-6f1e3dac-b6a5-436e-bb94-2065a1eb5e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041273860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2041273860
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.3414322165
Short name T166
Test name
Test status
Simulation time 4517458468 ps
CPU time 4.02 seconds
Started Jun 28 07:25:35 PM PDT 24
Finished Jun 28 07:25:45 PM PDT 24
Peak memory 213348 kb
Host smart-5366f26a-22f5-4843-8f56-78395cbc7e9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414322165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3414322165
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1676345424
Short name T215
Test name
Test status
Simulation time 259623982 ps
CPU time 0.72 seconds
Started Jun 28 07:24:16 PM PDT 24
Finished Jun 28 07:24:30 PM PDT 24
Peak memory 204916 kb
Host smart-2fd9e781-2ba8-43a8-a06c-964111ca5358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676345424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1676345424
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.559528372
Short name T50
Test name
Test status
Simulation time 6965150709 ps
CPU time 7.09 seconds
Started Jun 28 07:24:19 PM PDT 24
Finished Jun 28 07:24:40 PM PDT 24
Peak memory 213608 kb
Host smart-ae437760-69ff-4e64-af29-398e85b15991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559528372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.559528372
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3629542469
Short name T144
Test name
Test status
Simulation time 1669942418 ps
CPU time 5.47 seconds
Started Jun 28 07:24:16 PM PDT 24
Finished Jun 28 07:24:35 PM PDT 24
Peak memory 213436 kb
Host smart-3ddb65e4-bcd3-4c84-a32b-d1c5c807680c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629542469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3629542469
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3222960797
Short name T48
Test name
Test status
Simulation time 1880848846 ps
CPU time 1.75 seconds
Started Jun 28 07:24:18 PM PDT 24
Finished Jun 28 07:24:34 PM PDT 24
Peak memory 205176 kb
Host smart-18651a34-6281-431b-9d64-8a4369edbd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222960797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3222960797
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.3895825711
Short name T1
Test name
Test status
Simulation time 9930837015 ps
CPU time 30.62 seconds
Started Jun 28 07:24:15 PM PDT 24
Finished Jun 28 07:25:00 PM PDT 24
Peak memory 213408 kb
Host smart-7763c7e2-5847-412e-8fe1-9ac705f75458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895825711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3895825711
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3450415402
Short name T249
Test name
Test status
Simulation time 76625650 ps
CPU time 0.74 seconds
Started Jun 28 07:24:19 PM PDT 24
Finished Jun 28 07:24:33 PM PDT 24
Peak memory 204916 kb
Host smart-2eb94995-266a-42f1-8442-3a5a1eefe888
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450415402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3450415402
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3755797548
Short name T28
Test name
Test status
Simulation time 11616279773 ps
CPU time 18.63 seconds
Started Jun 28 07:24:17 PM PDT 24
Finished Jun 28 07:24:50 PM PDT 24
Peak memory 213520 kb
Host smart-f59efcb8-df13-435d-bdf2-bf31634fada4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755797548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3755797548
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1917103214
Short name T285
Test name
Test status
Simulation time 5198706347 ps
CPU time 5.22 seconds
Started Jun 28 07:24:16 PM PDT 24
Finished Jun 28 07:24:36 PM PDT 24
Peak memory 215164 kb
Host smart-691f21c9-1d04-487d-8c1d-08137f6335b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917103214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1917103214
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2939598650
Short name T43
Test name
Test status
Simulation time 13021885711 ps
CPU time 12.33 seconds
Started Jun 28 07:24:15 PM PDT 24
Finished Jun 28 07:24:41 PM PDT 24
Peak memory 213452 kb
Host smart-46f535bc-5953-4221-bd4d-32791f6384a0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2939598650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2939598650
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2346358290
Short name T44
Test name
Test status
Simulation time 3596868445 ps
CPU time 8.13 seconds
Started Jun 28 07:24:15 PM PDT 24
Finished Jun 28 07:24:37 PM PDT 24
Peak memory 213416 kb
Host smart-0f3a65ce-fc9a-49b5-86f9-4352293908ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346358290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2346358290
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.3798866688
Short name T31
Test name
Test status
Simulation time 8994424586 ps
CPU time 13.11 seconds
Started Jun 28 07:24:15 PM PDT 24
Finished Jun 28 07:24:42 PM PDT 24
Peak memory 221512 kb
Host smart-ac4e9e2b-286d-47a5-a691-46e478dc6f50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798866688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3798866688
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3098833406
Short name T269
Test name
Test status
Simulation time 93234649 ps
CPU time 0.73 seconds
Started Jun 28 07:24:17 PM PDT 24
Finished Jun 28 07:24:31 PM PDT 24
Peak memory 204920 kb
Host smart-ddeeb1a2-8156-46e8-8441-7d011e5c1307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098833406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3098833406
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1891468251
Short name T284
Test name
Test status
Simulation time 53517033899 ps
CPU time 78.49 seconds
Started Jun 28 07:24:17 PM PDT 24
Finished Jun 28 07:25:49 PM PDT 24
Peak memory 213760 kb
Host smart-d9677f68-18ae-469a-b7f5-49e78c660f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891468251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1891468251
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1933066975
Short name T161
Test name
Test status
Simulation time 8193928708 ps
CPU time 11.55 seconds
Started Jun 28 07:24:15 PM PDT 24
Finished Jun 28 07:24:41 PM PDT 24
Peak memory 205340 kb
Host smart-e8fb0e75-5035-44a1-8012-cf77055e948c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933066975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1933066975
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3475296196
Short name T223
Test name
Test status
Simulation time 2150138115 ps
CPU time 2.07 seconds
Started Jun 28 07:24:17 PM PDT 24
Finished Jun 28 07:24:32 PM PDT 24
Peak memory 205228 kb
Host smart-97d87c60-0a79-45d0-b16b-652a3ca8d48a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3475296196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3475296196
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2357572695
Short name T293
Test name
Test status
Simulation time 8560075458 ps
CPU time 12.89 seconds
Started Jun 28 07:24:15 PM PDT 24
Finished Jun 28 07:24:41 PM PDT 24
Peak memory 213496 kb
Host smart-12ac82d3-325f-4d50-88e2-c07909b91d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357572695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2357572695
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.686702798
Short name T181
Test name
Test status
Simulation time 2507800725 ps
CPU time 4.38 seconds
Started Jun 28 07:24:15 PM PDT 24
Finished Jun 28 07:24:34 PM PDT 24
Peak memory 213324 kb
Host smart-a4328425-6d83-4713-af9f-49c14dd8c87f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686702798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.686702798
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3523803696
Short name T195
Test name
Test status
Simulation time 43770669 ps
CPU time 0.77 seconds
Started Jun 28 07:24:34 PM PDT 24
Finished Jun 28 07:24:42 PM PDT 24
Peak memory 204924 kb
Host smart-0cf3a0f2-352b-45ac-b4de-180a3dca47bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523803696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3523803696
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3324819407
Short name T238
Test name
Test status
Simulation time 12080840171 ps
CPU time 9.81 seconds
Started Jun 28 07:24:32 PM PDT 24
Finished Jun 28 07:24:50 PM PDT 24
Peak memory 213560 kb
Host smart-36ea97b5-7100-4f78-8f4b-f90ddd443893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324819407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3324819407
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.687794467
Short name T218
Test name
Test status
Simulation time 904201577 ps
CPU time 2.39 seconds
Started Jun 28 07:24:32 PM PDT 24
Finished Jun 28 07:24:43 PM PDT 24
Peak memory 213492 kb
Host smart-64694d5c-570a-4bd1-a7c7-1e1a9e1a29b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687794467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.687794467
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3742178682
Short name T231
Test name
Test status
Simulation time 1465588532 ps
CPU time 2.93 seconds
Started Jun 28 07:24:32 PM PDT 24
Finished Jun 28 07:24:43 PM PDT 24
Peak memory 213420 kb
Host smart-a1bfe95b-d346-494a-8770-f929ad93681b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3742178682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3742178682
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.2498722756
Short name T198
Test name
Test status
Simulation time 6315676362 ps
CPU time 4.58 seconds
Started Jun 28 07:24:17 PM PDT 24
Finished Jun 28 07:24:35 PM PDT 24
Peak memory 213552 kb
Host smart-d71dcef6-1a84-4324-ab8c-2c7b306510ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498722756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.2498722756
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.3328215744
Short name T141
Test name
Test status
Simulation time 2439934389 ps
CPU time 8.19 seconds
Started Jun 28 07:24:38 PM PDT 24
Finished Jun 28 07:24:52 PM PDT 24
Peak memory 205156 kb
Host smart-1b43cad3-9257-4eff-b238-9966120cc0d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328215744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3328215744
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2733728462
Short name T204
Test name
Test status
Simulation time 266390040 ps
CPU time 0.75 seconds
Started Jun 28 07:24:32 PM PDT 24
Finished Jun 28 07:24:41 PM PDT 24
Peak memory 204912 kb
Host smart-8ec6ae06-58a5-42ea-b08c-85537dc71ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733728462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2733728462
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3955781945
Short name T152
Test name
Test status
Simulation time 93720298593 ps
CPU time 132.31 seconds
Started Jun 28 07:24:34 PM PDT 24
Finished Jun 28 07:26:54 PM PDT 24
Peak memory 219044 kb
Host smart-cd13cb44-c386-4909-83af-ed4e99787133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955781945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3955781945
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2041146382
Short name T27
Test name
Test status
Simulation time 1057161830 ps
CPU time 1.41 seconds
Started Jun 28 07:24:35 PM PDT 24
Finished Jun 28 07:24:44 PM PDT 24
Peak memory 205232 kb
Host smart-fcc6a5a0-460a-46e6-81fd-050ebfc12071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041146382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2041146382
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1332756551
Short name T47
Test name
Test status
Simulation time 11429656378 ps
CPU time 18.47 seconds
Started Jun 28 07:24:30 PM PDT 24
Finished Jun 28 07:24:58 PM PDT 24
Peak memory 213540 kb
Host smart-9f5517d6-fde7-4695-95b4-66d412c4a1a7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332756551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1332756551
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3368978823
Short name T252
Test name
Test status
Simulation time 1522688734 ps
CPU time 3.14 seconds
Started Jun 28 07:24:35 PM PDT 24
Finished Jun 28 07:24:45 PM PDT 24
Peak memory 213508 kb
Host smart-306428cc-aee6-49d4-a20e-1de472bf3812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368978823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3368978823
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.4000579391
Short name T24
Test name
Test status
Simulation time 4091249706 ps
CPU time 6.51 seconds
Started Jun 28 07:24:31 PM PDT 24
Finished Jun 28 07:24:46 PM PDT 24
Peak memory 213348 kb
Host smart-d609e619-ec51-4ba3-ba75-17af845343aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000579391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.4000579391
Directory /workspace/9.rv_dm_stress_all/latest
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