Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.58 95.32 80.00 89.42 74.36 85.67 98.32 54.99


Total test records in report: 439
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T129 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3276412461 Jun 29 06:40:47 PM PDT 24 Jun 29 06:40:56 PM PDT 24 2142883330 ps
T111 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1497070715 Jun 29 06:40:56 PM PDT 24 Jun 29 06:41:00 PM PDT 24 269558529 ps
T303 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1839809071 Jun 29 06:40:54 PM PDT 24 Jun 29 06:41:03 PM PDT 24 3069865119 ps
T112 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2132413557 Jun 29 06:40:44 PM PDT 24 Jun 29 06:40:46 PM PDT 24 313162965 ps
T130 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.978908032 Jun 29 06:40:26 PM PDT 24 Jun 29 06:40:28 PM PDT 24 437366568 ps
T131 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1637673451 Jun 29 06:40:31 PM PDT 24 Jun 29 06:40:33 PM PDT 24 87124296 ps
T113 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1543217134 Jun 29 06:40:54 PM PDT 24 Jun 29 06:40:59 PM PDT 24 259677833 ps
T103 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3552317666 Jun 29 06:40:22 PM PDT 24 Jun 29 06:40:26 PM PDT 24 1215411946 ps
T114 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1410487867 Jun 29 06:40:45 PM PDT 24 Jun 29 06:40:48 PM PDT 24 195127268 ps
T115 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.946432368 Jun 29 06:40:43 PM PDT 24 Jun 29 06:40:46 PM PDT 24 217190263 ps
T304 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1142894997 Jun 29 06:40:26 PM PDT 24 Jun 29 06:40:27 PM PDT 24 155351353 ps
T116 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1845223765 Jun 29 06:40:50 PM PDT 24 Jun 29 06:40:55 PM PDT 24 222474915 ps
T154 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4021752977 Jun 29 06:40:56 PM PDT 24 Jun 29 06:40:59 PM PDT 24 166210349 ps
T305 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.218058107 Jun 29 06:40:50 PM PDT 24 Jun 29 06:40:52 PM PDT 24 283687910 ps
T132 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2977748888 Jun 29 06:41:00 PM PDT 24 Jun 29 06:41:02 PM PDT 24 244819847 ps
T306 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2174051695 Jun 29 06:40:41 PM PDT 24 Jun 29 06:40:43 PM PDT 24 203344356 ps
T307 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.591022766 Jun 29 06:40:49 PM PDT 24 Jun 29 06:40:51 PM PDT 24 471398688 ps
T237 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3219005891 Jun 29 06:40:50 PM PDT 24 Jun 29 06:40:53 PM PDT 24 50521222 ps
T308 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2542443372 Jun 29 06:40:39 PM PDT 24 Jun 29 06:40:47 PM PDT 24 6108747295 ps
T133 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.569291138 Jun 29 06:40:49 PM PDT 24 Jun 29 06:40:57 PM PDT 24 429554008 ps
T309 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1766419024 Jun 29 06:40:51 PM PDT 24 Jun 29 06:40:56 PM PDT 24 1638667284 ps
T310 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.484003693 Jun 29 06:40:49 PM PDT 24 Jun 29 06:40:51 PM PDT 24 103512951 ps
T134 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2498203443 Jun 29 06:40:42 PM PDT 24 Jun 29 06:40:50 PM PDT 24 1538511303 ps
T238 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1092086955 Jun 29 06:40:56 PM PDT 24 Jun 29 06:41:02 PM PDT 24 1685428476 ps
T311 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.545877630 Jun 29 06:40:38 PM PDT 24 Jun 29 06:40:43 PM PDT 24 657614364 ps
T312 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3901004570 Jun 29 06:40:40 PM PDT 24 Jun 29 06:41:08 PM PDT 24 2841466960 ps
T146 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3884516741 Jun 29 06:40:25 PM PDT 24 Jun 29 06:41:35 PM PDT 24 61055383372 ps
T313 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2756907793 Jun 29 06:40:57 PM PDT 24 Jun 29 06:41:07 PM PDT 24 4171587183 ps
T314 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4436301 Jun 29 06:40:39 PM PDT 24 Jun 29 06:40:42 PM PDT 24 480777684 ps
T125 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1460991039 Jun 29 06:40:15 PM PDT 24 Jun 29 06:40:18 PM PDT 24 2240671034 ps
T149 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1483387894 Jun 29 06:40:39 PM PDT 24 Jun 29 06:40:44 PM PDT 24 225135046 ps
T315 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.320067306 Jun 29 06:40:55 PM PDT 24 Jun 29 06:41:06 PM PDT 24 3478876824 ps
T316 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3317301893 Jun 29 06:41:04 PM PDT 24 Jun 29 06:41:09 PM PDT 24 1522081929 ps
T179 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1933896176 Jun 29 06:40:35 PM PDT 24 Jun 29 06:40:47 PM PDT 24 1793502283 ps
T317 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1626426346 Jun 29 06:40:54 PM PDT 24 Jun 29 06:40:58 PM PDT 24 265428055 ps
T318 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3160928510 Jun 29 06:40:50 PM PDT 24 Jun 29 06:40:53 PM PDT 24 266372054 ps
T319 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1515043390 Jun 29 06:40:50 PM PDT 24 Jun 29 06:40:53 PM PDT 24 154686652 ps
T320 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2665929908 Jun 29 06:40:26 PM PDT 24 Jun 29 06:40:53 PM PDT 24 769222530 ps
T321 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3726455587 Jun 29 06:40:17 PM PDT 24 Jun 29 06:40:45 PM PDT 24 43075309271 ps
T150 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3756385795 Jun 29 06:40:15 PM PDT 24 Jun 29 06:40:22 PM PDT 24 348522146 ps
T322 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3203055126 Jun 29 06:40:16 PM PDT 24 Jun 29 06:40:22 PM PDT 24 3035599857 ps
T323 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3330600068 Jun 29 06:40:12 PM PDT 24 Jun 29 06:40:15 PM PDT 24 2342710423 ps
T324 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2459953928 Jun 29 06:40:12 PM PDT 24 Jun 29 06:40:13 PM PDT 24 49709883 ps
T325 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.538355778 Jun 29 06:40:49 PM PDT 24 Jun 29 06:41:06 PM PDT 24 7365656155 ps
T175 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2872291828 Jun 29 06:40:52 PM PDT 24 Jun 29 06:41:06 PM PDT 24 3118605814 ps
T326 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3120793249 Jun 29 06:40:49 PM PDT 24 Jun 29 06:40:52 PM PDT 24 170304007 ps
T126 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2723468919 Jun 29 06:40:31 PM PDT 24 Jun 29 06:40:45 PM PDT 24 18924338352 ps
T178 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2830336449 Jun 29 06:40:55 PM PDT 24 Jun 29 06:41:16 PM PDT 24 4039121694 ps
T327 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.863155172 Jun 29 06:40:12 PM PDT 24 Jun 29 06:40:34 PM PDT 24 28092361393 ps
T184 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1475998551 Jun 29 06:40:54 PM PDT 24 Jun 29 06:41:13 PM PDT 24 8302545409 ps
T328 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3414492817 Jun 29 06:40:37 PM PDT 24 Jun 29 06:40:40 PM PDT 24 213560382 ps
T329 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2373290044 Jun 29 06:40:48 PM PDT 24 Jun 29 06:40:53 PM PDT 24 355397623 ps
T151 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3216500094 Jun 29 06:40:21 PM PDT 24 Jun 29 06:40:25 PM PDT 24 347174323 ps
T330 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3476487872 Jun 29 06:40:51 PM PDT 24 Jun 29 06:40:53 PM PDT 24 1065909867 ps
T127 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1096551241 Jun 29 06:40:31 PM PDT 24 Jun 29 06:40:36 PM PDT 24 3597319274 ps
T331 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.990176264 Jun 29 06:40:56 PM PDT 24 Jun 29 06:41:03 PM PDT 24 1906723713 ps
T332 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1643008550 Jun 29 06:40:31 PM PDT 24 Jun 29 06:41:10 PM PDT 24 14924054860 ps
T333 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2170239287 Jun 29 06:40:35 PM PDT 24 Jun 29 06:40:37 PM PDT 24 311001511 ps
T334 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2095244860 Jun 29 06:40:39 PM PDT 24 Jun 29 06:40:45 PM PDT 24 2766900354 ps
T335 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2748708284 Jun 29 06:40:33 PM PDT 24 Jun 29 06:40:34 PM PDT 24 138122088 ps
T336 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1574352340 Jun 29 06:40:28 PM PDT 24 Jun 29 06:40:29 PM PDT 24 89309728 ps
T337 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3208316373 Jun 29 06:40:32 PM PDT 24 Jun 29 06:40:34 PM PDT 24 389655465 ps
T176 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.315642421 Jun 29 06:40:23 PM PDT 24 Jun 29 06:40:53 PM PDT 24 5167650701 ps
T338 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1879618551 Jun 29 06:40:38 PM PDT 24 Jun 29 06:40:45 PM PDT 24 2081192930 ps
T339 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.448727133 Jun 29 06:40:21 PM PDT 24 Jun 29 06:40:24 PM PDT 24 110583442 ps
T340 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3901710607 Jun 29 06:40:33 PM PDT 24 Jun 29 06:40:38 PM PDT 24 1110370480 ps
T341 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1473996418 Jun 29 06:40:49 PM PDT 24 Jun 29 06:41:00 PM PDT 24 947511164 ps
T342 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2314535417 Jun 29 06:40:17 PM PDT 24 Jun 29 06:43:09 PM PDT 24 60284613344 ps
T343 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3025074411 Jun 29 06:40:53 PM PDT 24 Jun 29 06:40:54 PM PDT 24 61333984 ps
T344 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1731171212 Jun 29 06:40:47 PM PDT 24 Jun 29 06:41:03 PM PDT 24 2266994382 ps
T345 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3643086921 Jun 29 06:40:46 PM PDT 24 Jun 29 06:41:09 PM PDT 24 10734389439 ps
T135 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1422521242 Jun 29 06:40:25 PM PDT 24 Jun 29 06:40:30 PM PDT 24 303788776 ps
T142 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2893732546 Jun 29 06:40:45 PM PDT 24 Jun 29 06:40:49 PM PDT 24 414228048 ps
T346 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1916809275 Jun 29 06:40:25 PM PDT 24 Jun 29 06:40:59 PM PDT 24 12737369643 ps
T180 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2652660514 Jun 29 06:40:38 PM PDT 24 Jun 29 06:40:50 PM PDT 24 962972880 ps
T347 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3146485383 Jun 29 06:40:40 PM PDT 24 Jun 29 06:40:44 PM PDT 24 488963777 ps
T136 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.965118683 Jun 29 06:40:46 PM PDT 24 Jun 29 06:40:49 PM PDT 24 168892059 ps
T348 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2453258331 Jun 29 06:40:44 PM PDT 24 Jun 29 06:41:39 PM PDT 24 19638013881 ps
T349 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1317550615 Jun 29 06:40:17 PM PDT 24 Jun 29 06:40:21 PM PDT 24 722464559 ps
T350 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.527838173 Jun 29 06:40:55 PM PDT 24 Jun 29 06:41:00 PM PDT 24 256845168 ps
T351 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1014394138 Jun 29 06:40:45 PM PDT 24 Jun 29 06:41:48 PM PDT 24 22094470001 ps
T352 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1615280045 Jun 29 06:40:23 PM PDT 24 Jun 29 06:40:24 PM PDT 24 55702079 ps
T353 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.969738374 Jun 29 06:40:33 PM PDT 24 Jun 29 06:40:35 PM PDT 24 115901557 ps
T354 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3380066869 Jun 29 06:40:49 PM PDT 24 Jun 29 06:40:54 PM PDT 24 215010717 ps
T355 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.736006149 Jun 29 06:41:04 PM PDT 24 Jun 29 06:41:07 PM PDT 24 5407803825 ps
T137 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1461343841 Jun 29 06:40:26 PM PDT 24 Jun 29 06:40:54 PM PDT 24 7602898013 ps
T143 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3561523096 Jun 29 06:40:26 PM PDT 24 Jun 29 06:40:28 PM PDT 24 1099588904 ps
T183 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3720296248 Jun 29 06:40:50 PM PDT 24 Jun 29 06:41:00 PM PDT 24 523315034 ps
T356 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1778604485 Jun 29 06:40:28 PM PDT 24 Jun 29 06:40:29 PM PDT 24 160965938 ps
T75 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3050412947 Jun 29 06:40:41 PM PDT 24 Jun 29 06:41:01 PM PDT 24 66645476159 ps
T76 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3042595310 Jun 29 06:40:50 PM PDT 24 Jun 29 06:41:24 PM PDT 24 41665660326 ps
T357 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3405580612 Jun 29 06:40:41 PM PDT 24 Jun 29 06:40:43 PM PDT 24 78606977 ps
T144 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1622742563 Jun 29 06:40:40 PM PDT 24 Jun 29 06:40:43 PM PDT 24 140368321 ps
T358 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.366600124 Jun 29 06:40:13 PM PDT 24 Jun 29 06:40:15 PM PDT 24 904944795 ps
T138 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2465365587 Jun 29 06:40:43 PM PDT 24 Jun 29 06:40:46 PM PDT 24 364301218 ps
T182 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2896797294 Jun 29 06:40:38 PM PDT 24 Jun 29 06:41:02 PM PDT 24 7030759148 ps
T359 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.48850166 Jun 29 06:40:52 PM PDT 24 Jun 29 06:40:54 PM PDT 24 1273092532 ps
T360 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.460431060 Jun 29 06:40:49 PM PDT 24 Jun 29 06:40:52 PM PDT 24 6323310876 ps
T139 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.101217344 Jun 29 06:40:28 PM PDT 24 Jun 29 06:40:31 PM PDT 24 153582295 ps
T361 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1329558910 Jun 29 06:40:54 PM PDT 24 Jun 29 06:40:59 PM PDT 24 531952191 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3352855110 Jun 29 06:40:17 PM PDT 24 Jun 29 06:40:20 PM PDT 24 409537046 ps
T363 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3570194684 Jun 29 06:40:45 PM PDT 24 Jun 29 06:40:49 PM PDT 24 465083538 ps
T364 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2726223156 Jun 29 06:40:49 PM PDT 24 Jun 29 06:41:20 PM PDT 24 13876522906 ps
T365 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3650456847 Jun 29 06:40:51 PM PDT 24 Jun 29 06:40:58 PM PDT 24 389286463 ps
T366 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1743031807 Jun 29 06:40:22 PM PDT 24 Jun 29 06:40:50 PM PDT 24 2969030657 ps
T367 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3856369753 Jun 29 06:40:47 PM PDT 24 Jun 29 06:40:49 PM PDT 24 62637397 ps
T368 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.721682645 Jun 29 06:40:46 PM PDT 24 Jun 29 06:40:49 PM PDT 24 356087619 ps
T369 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.521048638 Jun 29 06:40:24 PM PDT 24 Jun 29 06:40:29 PM PDT 24 616819634 ps
T370 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.518702431 Jun 29 06:40:51 PM PDT 24 Jun 29 06:40:53 PM PDT 24 988107038 ps
T371 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3413435131 Jun 29 06:40:47 PM PDT 24 Jun 29 06:40:56 PM PDT 24 8463069810 ps
T177 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3897180599 Jun 29 06:40:39 PM PDT 24 Jun 29 06:41:00 PM PDT 24 2523286526 ps
T372 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3999221265 Jun 29 06:40:50 PM PDT 24 Jun 29 06:41:04 PM PDT 24 1554123127 ps
T373 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1696331322 Jun 29 06:40:49 PM PDT 24 Jun 29 06:40:51 PM PDT 24 266405849 ps
T181 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1347895639 Jun 29 06:40:59 PM PDT 24 Jun 29 06:41:12 PM PDT 24 3969970282 ps
T147 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1199035816 Jun 29 06:40:54 PM PDT 24 Jun 29 06:40:57 PM PDT 24 61051145 ps
T374 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.390658445 Jun 29 06:40:39 PM PDT 24 Jun 29 06:40:57 PM PDT 24 6747067149 ps
T375 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2912054425 Jun 29 06:40:57 PM PDT 24 Jun 29 06:41:06 PM PDT 24 513963002 ps
T376 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.584589188 Jun 29 06:40:43 PM PDT 24 Jun 29 06:40:49 PM PDT 24 2876682140 ps
T140 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1295651964 Jun 29 06:40:54 PM PDT 24 Jun 29 06:40:58 PM PDT 24 177546781 ps
T141 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3156896834 Jun 29 06:40:17 PM PDT 24 Jun 29 06:41:24 PM PDT 24 2182150090 ps
T377 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1356981957 Jun 29 06:41:09 PM PDT 24 Jun 29 06:41:20 PM PDT 24 7607575124 ps
T378 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2788726899 Jun 29 06:40:40 PM PDT 24 Jun 29 06:42:10 PM PDT 24 33370418153 ps
T148 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2696671693 Jun 29 06:40:53 PM PDT 24 Jun 29 06:40:56 PM PDT 24 163410998 ps
T379 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.624922212 Jun 29 06:40:45 PM PDT 24 Jun 29 06:41:08 PM PDT 24 8653105630 ps
T380 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1097520332 Jun 29 06:40:42 PM PDT 24 Jun 29 06:40:59 PM PDT 24 9542941536 ps
T381 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.334844238 Jun 29 06:40:53 PM PDT 24 Jun 29 06:40:55 PM PDT 24 133161720 ps
T382 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1481432234 Jun 29 06:40:48 PM PDT 24 Jun 29 06:41:00 PM PDT 24 3453328948 ps
T383 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3191371075 Jun 29 06:40:14 PM PDT 24 Jun 29 06:40:15 PM PDT 24 245812033 ps
T77 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3029843996 Jun 29 06:40:33 PM PDT 24 Jun 29 06:40:45 PM PDT 24 20461039789 ps
T186 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1402274832 Jun 29 06:40:33 PM PDT 24 Jun 29 06:43:00 PM PDT 24 47339112500 ps
T384 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2709852894 Jun 29 06:40:43 PM PDT 24 Jun 29 06:40:44 PM PDT 24 438438193 ps
T385 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1813292495 Jun 29 06:40:42 PM PDT 24 Jun 29 06:40:49 PM PDT 24 629011704 ps
T386 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1552913415 Jun 29 06:41:09 PM PDT 24 Jun 29 06:41:12 PM PDT 24 214610677 ps
T185 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4044146837 Jun 29 06:41:04 PM PDT 24 Jun 29 06:41:23 PM PDT 24 7554960443 ps
T387 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1716916154 Jun 29 06:40:37 PM PDT 24 Jun 29 06:40:53 PM PDT 24 9684884180 ps
T388 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.122422517 Jun 29 06:40:57 PM PDT 24 Jun 29 06:40:59 PM PDT 24 102212069 ps
T389 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1973717416 Jun 29 06:40:50 PM PDT 24 Jun 29 06:41:07 PM PDT 24 2000390143 ps
T145 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1268435109 Jun 29 06:40:25 PM PDT 24 Jun 29 06:41:32 PM PDT 24 2010721423 ps
T390 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1893598046 Jun 29 06:40:36 PM PDT 24 Jun 29 06:41:07 PM PDT 24 7148101482 ps
T391 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2403500449 Jun 29 06:40:58 PM PDT 24 Jun 29 06:41:07 PM PDT 24 18416939531 ps
T392 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2779717874 Jun 29 06:40:34 PM PDT 24 Jun 29 06:41:14 PM PDT 24 36382665370 ps
T393 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2095341829 Jun 29 06:40:47 PM PDT 24 Jun 29 06:40:50 PM PDT 24 493827005 ps
T394 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3677544714 Jun 29 06:40:36 PM PDT 24 Jun 29 06:40:39 PM PDT 24 1655445832 ps
T395 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1355154322 Jun 29 06:40:39 PM PDT 24 Jun 29 06:41:18 PM PDT 24 26505557578 ps
T396 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.685915514 Jun 29 06:40:55 PM PDT 24 Jun 29 06:40:56 PM PDT 24 122171643 ps
T397 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2761699415 Jun 29 06:40:21 PM PDT 24 Jun 29 06:40:22 PM PDT 24 243343793 ps
T398 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4172234613 Jun 29 06:40:47 PM PDT 24 Jun 29 06:40:51 PM PDT 24 49502870 ps
T399 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3707376853 Jun 29 06:40:25 PM PDT 24 Jun 29 06:40:28 PM PDT 24 374380861 ps
T400 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1727161709 Jun 29 06:40:24 PM PDT 24 Jun 29 06:40:25 PM PDT 24 275623534 ps
T401 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1997554768 Jun 29 06:40:39 PM PDT 24 Jun 29 06:40:41 PM PDT 24 488596825 ps
T402 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3519337137 Jun 29 06:41:00 PM PDT 24 Jun 29 06:41:03 PM PDT 24 113487136 ps
T403 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1944165130 Jun 29 06:40:52 PM PDT 24 Jun 29 06:40:56 PM PDT 24 101055014 ps
T404 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1874745107 Jun 29 06:40:37 PM PDT 24 Jun 29 06:40:50 PM PDT 24 9823664120 ps
T405 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1462333993 Jun 29 06:40:48 PM PDT 24 Jun 29 06:40:56 PM PDT 24 4165429588 ps
T406 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.782801105 Jun 29 06:40:47 PM PDT 24 Jun 29 06:40:53 PM PDT 24 2750011281 ps
T407 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3383541877 Jun 29 06:40:31 PM PDT 24 Jun 29 06:40:35 PM PDT 24 9599236150 ps
T408 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3501850149 Jun 29 06:40:48 PM PDT 24 Jun 29 06:40:58 PM PDT 24 2789222823 ps
T409 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.283801316 Jun 29 06:40:45 PM PDT 24 Jun 29 06:40:56 PM PDT 24 1387644103 ps
T410 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.825254281 Jun 29 06:40:59 PM PDT 24 Jun 29 06:41:01 PM PDT 24 800439096 ps
T411 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.306586812 Jun 29 06:40:21 PM PDT 24 Jun 29 06:40:28 PM PDT 24 10595882016 ps
T412 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2007074001 Jun 29 06:40:26 PM PDT 24 Jun 29 06:40:28 PM PDT 24 723653984 ps
T413 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2253813521 Jun 29 06:40:16 PM PDT 24 Jun 29 06:40:22 PM PDT 24 482022284 ps
T414 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1741303001 Jun 29 06:40:50 PM PDT 24 Jun 29 06:41:28 PM PDT 24 29090500214 ps
T415 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.22052452 Jun 29 06:40:41 PM PDT 24 Jun 29 06:40:42 PM PDT 24 244937159 ps
T128 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3633749292 Jun 29 06:40:37 PM PDT 24 Jun 29 06:41:19 PM PDT 24 14627275293 ps
T416 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3778065734 Jun 29 06:40:30 PM PDT 24 Jun 29 06:40:38 PM PDT 24 2674659140 ps
T417 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2600750497 Jun 29 06:40:46 PM PDT 24 Jun 29 06:40:51 PM PDT 24 275695472 ps
T418 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2211895961 Jun 29 06:40:47 PM PDT 24 Jun 29 06:40:55 PM PDT 24 566612830 ps
T419 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2751952305 Jun 29 06:40:45 PM PDT 24 Jun 29 06:40:50 PM PDT 24 215532224 ps
T420 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.614221956 Jun 29 06:40:42 PM PDT 24 Jun 29 06:40:45 PM PDT 24 148981164 ps
T421 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2719695265 Jun 29 06:40:30 PM PDT 24 Jun 29 06:40:33 PM PDT 24 1589099106 ps
T422 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3842275114 Jun 29 06:40:39 PM PDT 24 Jun 29 06:40:48 PM PDT 24 2878912124 ps
T423 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2579374396 Jun 29 06:40:13 PM PDT 24 Jun 29 06:40:14 PM PDT 24 172551284 ps
T424 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1369926715 Jun 29 06:40:47 PM PDT 24 Jun 29 06:40:52 PM PDT 24 840423058 ps
T425 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2678302301 Jun 29 06:40:47 PM PDT 24 Jun 29 06:40:51 PM PDT 24 229723282 ps
T426 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3637858286 Jun 29 06:40:42 PM PDT 24 Jun 29 06:40:49 PM PDT 24 7692766490 ps
T427 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3847811217 Jun 29 06:40:17 PM PDT 24 Jun 29 06:42:13 PM PDT 24 77440187898 ps
T428 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2837526949 Jun 29 06:40:37 PM PDT 24 Jun 29 06:40:40 PM PDT 24 3727570301 ps
T429 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1489478897 Jun 29 06:40:54 PM PDT 24 Jun 29 06:40:57 PM PDT 24 584219453 ps
T430 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3910092791 Jun 29 06:41:03 PM PDT 24 Jun 29 06:41:12 PM PDT 24 2949190657 ps
T431 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3318405938 Jun 29 06:40:13 PM PDT 24 Jun 29 06:40:16 PM PDT 24 2990159297 ps
T432 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.301130686 Jun 29 06:41:03 PM PDT 24 Jun 29 06:41:07 PM PDT 24 4154712923 ps
T433 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4059752109 Jun 29 06:40:33 PM PDT 24 Jun 29 06:40:36 PM PDT 24 1433040826 ps
T434 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3730463152 Jun 29 06:40:20 PM PDT 24 Jun 29 06:40:52 PM PDT 24 2047607210 ps
T435 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1703473495 Jun 29 06:40:51 PM PDT 24 Jun 29 06:40:59 PM PDT 24 762252417 ps
T436 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3062060179 Jun 29 06:40:13 PM PDT 24 Jun 29 06:40:15 PM PDT 24 802915603 ps
T437 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2714194996 Jun 29 06:40:16 PM PDT 24 Jun 29 06:40:18 PM PDT 24 372574694 ps
T438 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2851620280 Jun 29 06:40:47 PM PDT 24 Jun 29 06:40:50 PM PDT 24 532114625 ps
T439 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1406256942 Jun 29 06:40:14 PM PDT 24 Jun 29 06:41:28 PM PDT 24 25502947407 ps

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1162249515
Short name T2
Test name
Test status
Simulation time 1605849421 ps
CPU time 4.39 seconds
Started Jun 29 06:46:17 PM PDT 24
Finished Jun 29 06:46:22 PM PDT 24
Peak memory 205280 kb
Host smart-8fc339cd-ac88-4130-9cb6-f568f1d6b333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162249515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1162249515
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.2834773898
Short name T6
Test name
Test status
Simulation time 8403672580 ps
CPU time 6.55 seconds
Started Jun 29 06:46:10 PM PDT 24
Finished Jun 29 06:46:17 PM PDT 24
Peak memory 213336 kb
Host smart-30d46b04-09ca-446f-b673-1726e274e4b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834773898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.2834773898
Directory /workspace/9.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3584171652
Short name T104
Test name
Test status
Simulation time 253177467 ps
CPU time 6.76 seconds
Started Jun 29 06:40:46 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 213248 kb
Host smart-51e9179a-e2f6-4654-93e7-c2575cde1c78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584171652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3584171652
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3708337988
Short name T31
Test name
Test status
Simulation time 1907293565 ps
CPU time 1.47 seconds
Started Jun 29 06:46:15 PM PDT 24
Finished Jun 29 06:46:17 PM PDT 24
Peak memory 213456 kb
Host smart-974193f6-e7ab-4543-8127-fca9398e72b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708337988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3708337988
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3235914115
Short name T109
Test name
Test status
Simulation time 3516371342 ps
CPU time 11.44 seconds
Started Jun 29 06:40:37 PM PDT 24
Finished Jun 29 06:40:49 PM PDT 24
Peak memory 213372 kb
Host smart-d4ca2b20-d565-413b-8b15-7be10b1e8527
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235914115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3235914115
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3029843996
Short name T77
Test name
Test status
Simulation time 20461039789 ps
CPU time 11.91 seconds
Started Jun 29 06:40:33 PM PDT 24
Finished Jun 29 06:40:45 PM PDT 24
Peak memory 220584 kb
Host smart-c80fbf5f-c889-438e-b871-5f917504ccc3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029843996 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3029843996
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1544718767
Short name T4
Test name
Test status
Simulation time 6394284760 ps
CPU time 9.84 seconds
Started Jun 29 06:46:48 PM PDT 24
Finished Jun 29 06:46:58 PM PDT 24
Peak memory 205152 kb
Host smart-d10ec39d-2216-40be-ab9f-94459f5354c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544718767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1544718767
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1543217134
Short name T113
Test name
Test status
Simulation time 259677833 ps
CPU time 3.86 seconds
Started Jun 29 06:40:54 PM PDT 24
Finished Jun 29 06:40:59 PM PDT 24
Peak memory 213240 kb
Host smart-7fdd07a8-cae6-4afb-a00a-ce0457bb2b05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543217134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1543217134
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3520244952
Short name T3
Test name
Test status
Simulation time 123801025 ps
CPU time 0.73 seconds
Started Jun 29 06:46:48 PM PDT 24
Finished Jun 29 06:46:49 PM PDT 24
Peak memory 204900 kb
Host smart-db77755d-53f7-4d53-aad4-cbf2cb7191a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520244952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3520244952
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.1556204628
Short name T46
Test name
Test status
Simulation time 79717165 ps
CPU time 1.02 seconds
Started Jun 29 06:45:45 PM PDT 24
Finished Jun 29 06:45:46 PM PDT 24
Peak memory 215508 kb
Host smart-bf31f684-e712-4f77-a799-04b8b43b36ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556204628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1556204628
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.501424602
Short name T219
Test name
Test status
Simulation time 23002600861 ps
CPU time 24.34 seconds
Started Jun 29 06:46:25 PM PDT 24
Finished Jun 29 06:46:49 PM PDT 24
Peak memory 213592 kb
Host smart-edee624e-7a49-48fd-ad30-ade5980e2b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501424602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.501424602
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2075790690
Short name T21
Test name
Test status
Simulation time 1343231058 ps
CPU time 2.32 seconds
Started Jun 29 06:45:14 PM PDT 24
Finished Jun 29 06:45:16 PM PDT 24
Peak memory 204900 kb
Host smart-3169e160-5173-4723-9d59-80569af1dc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075790690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2075790690
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.3334449343
Short name T25
Test name
Test status
Simulation time 9827887462 ps
CPU time 23.43 seconds
Started Jun 29 06:46:08 PM PDT 24
Finished Jun 29 06:46:32 PM PDT 24
Peak memory 213312 kb
Host smart-e4578bd2-7434-4cb3-8b5a-0c4a5be9d5fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334449343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3334449343
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1461343841
Short name T137
Test name
Test status
Simulation time 7602898013 ps
CPU time 27.33 seconds
Started Jun 29 06:40:26 PM PDT 24
Finished Jun 29 06:40:54 PM PDT 24
Peak memory 205044 kb
Host smart-544f46a7-f51f-4c75-981c-f9a7bf0425f2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461343841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1461343841
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.143315073
Short name T80
Test name
Test status
Simulation time 1870312757 ps
CPU time 16.53 seconds
Started Jun 29 06:40:56 PM PDT 24
Finished Jun 29 06:41:13 PM PDT 24
Peak memory 213368 kb
Host smart-b4852c48-ddfc-4623-a1d9-4fc0a1e1257b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143315073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.143315073
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.4150195060
Short name T251
Test name
Test status
Simulation time 10704011012 ps
CPU time 12.09 seconds
Started Jun 29 06:46:25 PM PDT 24
Finished Jun 29 06:46:38 PM PDT 24
Peak memory 216464 kb
Host smart-fa317f83-8a34-4d4b-b6e8-820cb95e5a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150195060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.4150195060
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.2212335912
Short name T23
Test name
Test status
Simulation time 2824617302 ps
CPU time 9.19 seconds
Started Jun 29 06:46:15 PM PDT 24
Finished Jun 29 06:46:25 PM PDT 24
Peak memory 213368 kb
Host smart-94278277-1da8-43bd-954c-eaf22e87b354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212335912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2212335912
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3387363793
Short name T91
Test name
Test status
Simulation time 1355477887 ps
CPU time 2.86 seconds
Started Jun 29 06:45:56 PM PDT 24
Finished Jun 29 06:45:59 PM PDT 24
Peak memory 237324 kb
Host smart-6a1f65e6-99d0-401e-a2cf-ce5335a66484
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387363793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3387363793
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.2836746181
Short name T27
Test name
Test status
Simulation time 719608386 ps
CPU time 1.02 seconds
Started Jun 29 06:45:21 PM PDT 24
Finished Jun 29 06:45:23 PM PDT 24
Peak memory 205160 kb
Host smart-3e5f1e9f-2d0f-42cb-8d21-e12bef5a6f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836746181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2836746181
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3041788059
Short name T66
Test name
Test status
Simulation time 257798148 ps
CPU time 0.88 seconds
Started Jun 29 06:45:24 PM PDT 24
Finished Jun 29 06:45:26 PM PDT 24
Peak memory 204908 kb
Host smart-6364eb23-181e-47e8-9321-7a1cb5102757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041788059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3041788059
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1199741955
Short name T122
Test name
Test status
Simulation time 987481747 ps
CPU time 8.09 seconds
Started Jun 29 06:40:53 PM PDT 24
Finished Jun 29 06:41:02 PM PDT 24
Peak memory 205092 kb
Host smart-b1ae79af-f770-45e3-bfc1-27214b1c9063
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199741955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1199741955
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2665929908
Short name T320
Test name
Test status
Simulation time 769222530 ps
CPU time 26.47 seconds
Started Jun 29 06:40:26 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 213220 kb
Host smart-56847021-3847-4f73-a4f6-a3b7359dd2ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665929908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2665929908
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.4233716602
Short name T63
Test name
Test status
Simulation time 85500297 ps
CPU time 0.96 seconds
Started Jun 29 06:45:22 PM PDT 24
Finished Jun 29 06:45:23 PM PDT 24
Peak memory 213188 kb
Host smart-b4cd3451-9ed0-405e-a85e-3c6e75022504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233716602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.4233716602
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3164113319
Short name T198
Test name
Test status
Simulation time 4289802098 ps
CPU time 7.09 seconds
Started Jun 29 06:46:15 PM PDT 24
Finished Jun 29 06:46:23 PM PDT 24
Peak memory 205172 kb
Host smart-41666d07-8a80-4573-9e0d-c3c01aabd374
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164113319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3164113319
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.2070468850
Short name T11
Test name
Test status
Simulation time 9512947880 ps
CPU time 3.26 seconds
Started Jun 29 06:46:01 PM PDT 24
Finished Jun 29 06:46:04 PM PDT 24
Peak memory 213356 kb
Host smart-9b286f40-098a-41dc-953a-654451b75e09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070468850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2070468850
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.3804350473
Short name T67
Test name
Test status
Simulation time 1353044391 ps
CPU time 4.03 seconds
Started Jun 29 06:45:23 PM PDT 24
Finished Jun 29 06:45:28 PM PDT 24
Peak memory 204916 kb
Host smart-c922f31e-4908-48e4-bb98-3ae64e7cd6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804350473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.3804350473
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2534496306
Short name T102
Test name
Test status
Simulation time 16675491534 ps
CPU time 41.99 seconds
Started Jun 29 06:40:21 PM PDT 24
Finished Jun 29 06:41:03 PM PDT 24
Peak memory 204964 kb
Host smart-9efb6003-720e-4493-b1b2-d5c33abe86be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534496306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2534496306
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.315642421
Short name T176
Test name
Test status
Simulation time 5167650701 ps
CPU time 29.49 seconds
Started Jun 29 06:40:23 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 213352 kb
Host smart-746ba493-b4bb-4fad-a9bf-07510199f6d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315642421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.315642421
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2652660514
Short name T180
Test name
Test status
Simulation time 962972880 ps
CPU time 11.29 seconds
Started Jun 29 06:40:38 PM PDT 24
Finished Jun 29 06:40:50 PM PDT 24
Peak memory 213300 kb
Host smart-632542c3-5837-4091-b6d0-94142398b625
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652660514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2652660514
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2342675149
Short name T93
Test name
Test status
Simulation time 16414529716 ps
CPU time 42.81 seconds
Started Jun 29 06:46:30 PM PDT 24
Finished Jun 29 06:47:13 PM PDT 24
Peak memory 213400 kb
Host smart-c730e32d-69fa-4e78-bfa0-670c5aa2f833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342675149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2342675149
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.2844673829
Short name T162
Test name
Test status
Simulation time 7304817101 ps
CPU time 20.06 seconds
Started Jun 29 06:45:54 PM PDT 24
Finished Jun 29 06:46:14 PM PDT 24
Peak memory 213516 kb
Host smart-2053e79c-9151-4b17-9948-7a04cb5a8a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844673829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2844673829
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1708493678
Short name T35
Test name
Test status
Simulation time 6822470999 ps
CPU time 21.14 seconds
Started Jun 29 06:45:53 PM PDT 24
Finished Jun 29 06:46:14 PM PDT 24
Peak memory 213540 kb
Host smart-8250f0b4-d644-44b3-ad24-ee30e0935c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708493678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1708493678
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.3835684213
Short name T160
Test name
Test status
Simulation time 2851953780 ps
CPU time 8.71 seconds
Started Jun 29 06:46:46 PM PDT 24
Finished Jun 29 06:46:56 PM PDT 24
Peak memory 213284 kb
Host smart-38307f9c-e686-4e41-a707-9ae543a599c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835684213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3835684213
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1460991039
Short name T125
Test name
Test status
Simulation time 2240671034 ps
CPU time 2.29 seconds
Started Jun 29 06:40:15 PM PDT 24
Finished Jun 29 06:40:18 PM PDT 24
Peak memory 205024 kb
Host smart-05bb94d9-5dbf-4169-960b-8a64f9ff5f15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460991039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1460991039
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2434716244
Short name T60
Test name
Test status
Simulation time 305406827 ps
CPU time 1.44 seconds
Started Jun 29 06:45:14 PM PDT 24
Finished Jun 29 06:45:16 PM PDT 24
Peak memory 204908 kb
Host smart-43cd5d80-0ad9-4b71-b191-ea1d015dd262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434716244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2434716244
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3901004570
Short name T312
Test name
Test status
Simulation time 2841466960 ps
CPU time 27.48 seconds
Started Jun 29 06:40:40 PM PDT 24
Finished Jun 29 06:41:08 PM PDT 24
Peak memory 205120 kb
Host smart-1d438b15-5d73-40e6-8956-d574b416e431
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901004570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3901004570
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.114738660
Short name T169
Test name
Test status
Simulation time 1528526267 ps
CPU time 4.57 seconds
Started Jun 29 06:46:15 PM PDT 24
Finished Jun 29 06:46:20 PM PDT 24
Peak memory 213432 kb
Host smart-7d67969a-39f9-4e48-8f7c-1394ce6502c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114738660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.114738660
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.4014638850
Short name T171
Test name
Test status
Simulation time 5549325360 ps
CPU time 15.67 seconds
Started Jun 29 06:46:17 PM PDT 24
Finished Jun 29 06:46:33 PM PDT 24
Peak memory 213460 kb
Host smart-966cd47d-4a5d-4466-902d-e4523b2c9e1d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4014638850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.4014638850
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3156896834
Short name T141
Test name
Test status
Simulation time 2182150090 ps
CPU time 66.54 seconds
Started Jun 29 06:40:17 PM PDT 24
Finished Jun 29 06:41:24 PM PDT 24
Peak memory 213276 kb
Host smart-17c1c500-3c97-4d94-a006-aaf619c3e019
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156896834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3156896834
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3414492817
Short name T328
Test name
Test status
Simulation time 213560382 ps
CPU time 2.66 seconds
Started Jun 29 06:40:37 PM PDT 24
Finished Jun 29 06:40:40 PM PDT 24
Peak memory 213268 kb
Host smart-48990aab-cbc0-46b2-b875-4a3f34abd0d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414492817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3414492817
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3330600068
Short name T323
Test name
Test status
Simulation time 2342710423 ps
CPU time 2.77 seconds
Started Jun 29 06:40:12 PM PDT 24
Finished Jun 29 06:40:15 PM PDT 24
Peak memory 213388 kb
Host smart-0dd85588-202d-45eb-8d36-5a5d783ad56f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330600068 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3330600068
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3707376853
Short name T399
Test name
Test status
Simulation time 374380861 ps
CPU time 2.43 seconds
Started Jun 29 06:40:25 PM PDT 24
Finished Jun 29 06:40:28 PM PDT 24
Peak memory 213240 kb
Host smart-6849ee9a-985f-4418-b769-2816010ddb55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707376853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3707376853
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.863155172
Short name T327
Test name
Test status
Simulation time 28092361393 ps
CPU time 22.08 seconds
Started Jun 29 06:40:12 PM PDT 24
Finished Jun 29 06:40:34 PM PDT 24
Peak memory 205004 kb
Host smart-8dfebc76-6214-494c-9e71-8bd592e28698
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863155172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.863155172
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3726455587
Short name T321
Test name
Test status
Simulation time 43075309271 ps
CPU time 28.1 seconds
Started Jun 29 06:40:17 PM PDT 24
Finished Jun 29 06:40:45 PM PDT 24
Peak memory 204964 kb
Host smart-e74acb83-027f-40c4-bcee-8dc29cf29176
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726455587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.3726455587
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1874745107
Short name T404
Test name
Test status
Simulation time 9823664120 ps
CPU time 12.71 seconds
Started Jun 29 06:40:37 PM PDT 24
Finished Jun 29 06:40:50 PM PDT 24
Peak memory 204944 kb
Host smart-b91487da-fa99-42b4-89b0-6f9bc866f24c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874745107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1874745107
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3203055126
Short name T322
Test name
Test status
Simulation time 3035599857 ps
CPU time 5.43 seconds
Started Jun 29 06:40:16 PM PDT 24
Finished Jun 29 06:40:22 PM PDT 24
Peak memory 204964 kb
Host smart-762814cf-5d94-4517-8829-988dd0cc2fd0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203055126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
203055126
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2761699415
Short name T397
Test name
Test status
Simulation time 243343793 ps
CPU time 0.86 seconds
Started Jun 29 06:40:21 PM PDT 24
Finished Jun 29 06:40:22 PM PDT 24
Peak memory 204732 kb
Host smart-d80afc87-4ee8-463c-80ff-6bc07ea15f03
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761699415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2761699415
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3062060179
Short name T436
Test name
Test status
Simulation time 802915603 ps
CPU time 1.45 seconds
Started Jun 29 06:40:13 PM PDT 24
Finished Jun 29 06:40:15 PM PDT 24
Peak memory 204700 kb
Host smart-9ef896c4-49ad-41ab-866d-f46d8f5b6a87
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062060179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3062060179
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3552317666
Short name T103
Test name
Test status
Simulation time 1215411946 ps
CPU time 3.88 seconds
Started Jun 29 06:40:22 PM PDT 24
Finished Jun 29 06:40:26 PM PDT 24
Peak memory 204720 kb
Host smart-660e0111-f37b-4689-8097-96e169c4214e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552317666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
552317666
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3191371075
Short name T383
Test name
Test status
Simulation time 245812033 ps
CPU time 0.73 seconds
Started Jun 29 06:40:14 PM PDT 24
Finished Jun 29 06:40:15 PM PDT 24
Peak memory 204720 kb
Host smart-e62185ac-e62a-42d1-9cd2-fd1646198320
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191371075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3191371075
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2459953928
Short name T324
Test name
Test status
Simulation time 49709883 ps
CPU time 0.79 seconds
Started Jun 29 06:40:12 PM PDT 24
Finished Jun 29 06:40:13 PM PDT 24
Peak memory 204724 kb
Host smart-44fa028f-c05f-4ec9-ae47-1d2835f7e5bc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459953928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2459953928
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3756385795
Short name T150
Test name
Test status
Simulation time 348522146 ps
CPU time 7.14 seconds
Started Jun 29 06:40:15 PM PDT 24
Finished Jun 29 06:40:22 PM PDT 24
Peak memory 205080 kb
Host smart-4de4be15-59fe-4c0b-871d-023c140dbda6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756385795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3756385795
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1406256942
Short name T439
Test name
Test status
Simulation time 25502947407 ps
CPU time 73.77 seconds
Started Jun 29 06:40:14 PM PDT 24
Finished Jun 29 06:41:28 PM PDT 24
Peak memory 221520 kb
Host smart-df16420b-491f-430f-963a-f15bd5c20b19
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406256942 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1406256942
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.448727133
Short name T339
Test name
Test status
Simulation time 110583442 ps
CPU time 2.67 seconds
Started Jun 29 06:40:21 PM PDT 24
Finished Jun 29 06:40:24 PM PDT 24
Peak memory 213304 kb
Host smart-853a5758-37b5-4a34-92af-1c8ab2a08b5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448727133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.448727133
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3730463152
Short name T434
Test name
Test status
Simulation time 2047607210 ps
CPU time 31.69 seconds
Started Jun 29 06:40:20 PM PDT 24
Finished Jun 29 06:40:52 PM PDT 24
Peak memory 205024 kb
Host smart-a5f4df48-a96d-41d3-8581-002e9d94cb89
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730463152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3730463152
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3352855110
Short name T362
Test name
Test status
Simulation time 409537046 ps
CPU time 1.73 seconds
Started Jun 29 06:40:17 PM PDT 24
Finished Jun 29 06:40:20 PM PDT 24
Peak memory 213252 kb
Host smart-d176679e-572f-45ae-940a-3abcd552429d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352855110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3352855110
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1317550615
Short name T349
Test name
Test status
Simulation time 722464559 ps
CPU time 3.71 seconds
Started Jun 29 06:40:17 PM PDT 24
Finished Jun 29 06:40:21 PM PDT 24
Peak memory 217420 kb
Host smart-a0009756-44aa-411c-af03-9dc7095226be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317550615 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1317550615
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2527083091
Short name T123
Test name
Test status
Simulation time 281899784 ps
CPU time 2.43 seconds
Started Jun 29 06:40:13 PM PDT 24
Finished Jun 29 06:40:16 PM PDT 24
Peak memory 213188 kb
Host smart-b5ede590-7f8c-4952-8bb0-c59a0450281b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527083091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2527083091
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2314535417
Short name T342
Test name
Test status
Simulation time 60284613344 ps
CPU time 171.01 seconds
Started Jun 29 06:40:17 PM PDT 24
Finished Jun 29 06:43:09 PM PDT 24
Peak memory 204968 kb
Host smart-fdfd26a7-8015-4d55-af15-29ae1a7917fd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314535417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2314535417
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3847811217
Short name T427
Test name
Test status
Simulation time 77440187898 ps
CPU time 115.37 seconds
Started Jun 29 06:40:17 PM PDT 24
Finished Jun 29 06:42:13 PM PDT 24
Peak memory 204956 kb
Host smart-8c84d94a-dc5e-44b9-9249-0a5ff1036f9a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847811217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3847811217
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3778065734
Short name T416
Test name
Test status
Simulation time 2674659140 ps
CPU time 8.61 seconds
Started Jun 29 06:40:30 PM PDT 24
Finished Jun 29 06:40:38 PM PDT 24
Peak memory 204960 kb
Host smart-fffb5c30-df45-42a2-acd2-745b1e88dd3b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778065734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
778065734
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3318405938
Short name T431
Test name
Test status
Simulation time 2990159297 ps
CPU time 1.57 seconds
Started Jun 29 06:40:13 PM PDT 24
Finished Jun 29 06:40:16 PM PDT 24
Peak memory 204720 kb
Host smart-bc627c69-a972-4036-a094-78cf9d62c0e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318405938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3318405938
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.306586812
Short name T411
Test name
Test status
Simulation time 10595882016 ps
CPU time 7.08 seconds
Started Jun 29 06:40:21 PM PDT 24
Finished Jun 29 06:40:28 PM PDT 24
Peak memory 204972 kb
Host smart-204f0c21-9c7c-4b5e-a399-0c4aa47a11e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306586812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.306586812
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2714194996
Short name T437
Test name
Test status
Simulation time 372574694 ps
CPU time 1.58 seconds
Started Jun 29 06:40:16 PM PDT 24
Finished Jun 29 06:40:18 PM PDT 24
Peak memory 204728 kb
Host smart-112ea742-3a1d-477c-ad65-386ebcce9952
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714194996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2714194996
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2007074001
Short name T412
Test name
Test status
Simulation time 723653984 ps
CPU time 1.01 seconds
Started Jun 29 06:40:26 PM PDT 24
Finished Jun 29 06:40:28 PM PDT 24
Peak memory 204720 kb
Host smart-d6a07151-b55f-43fa-b5f2-58028450741c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007074001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
007074001
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2579374396
Short name T423
Test name
Test status
Simulation time 172551284 ps
CPU time 0.85 seconds
Started Jun 29 06:40:13 PM PDT 24
Finished Jun 29 06:40:14 PM PDT 24
Peak memory 204700 kb
Host smart-227f0614-e49d-4ccf-bdcb-cb14cecca203
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579374396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2579374396
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1615280045
Short name T352
Test name
Test status
Simulation time 55702079 ps
CPU time 0.74 seconds
Started Jun 29 06:40:23 PM PDT 24
Finished Jun 29 06:40:24 PM PDT 24
Peak memory 204724 kb
Host smart-1ffbd4f8-0281-4e2d-830a-75d3fb89ce49
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615280045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1615280045
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3216500094
Short name T151
Test name
Test status
Simulation time 347174323 ps
CPU time 3.64 seconds
Started Jun 29 06:40:21 PM PDT 24
Finished Jun 29 06:40:25 PM PDT 24
Peak memory 205096 kb
Host smart-a1227613-9877-431c-a966-afc6ddc0e0c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216500094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3216500094
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2253813521
Short name T413
Test name
Test status
Simulation time 482022284 ps
CPU time 5.49 seconds
Started Jun 29 06:40:16 PM PDT 24
Finished Jun 29 06:40:22 PM PDT 24
Peak memory 213296 kb
Host smart-031c65ed-e3a3-4875-9c3f-0d34d3b2e3fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253813521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2253813521
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3897180599
Short name T177
Test name
Test status
Simulation time 2523286526 ps
CPU time 19.77 seconds
Started Jun 29 06:40:39 PM PDT 24
Finished Jun 29 06:41:00 PM PDT 24
Peak memory 213380 kb
Host smart-cb23069f-722f-4794-98da-79bfbb1ea70b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897180599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3897180599
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3842275114
Short name T422
Test name
Test status
Simulation time 2878912124 ps
CPU time 8.15 seconds
Started Jun 29 06:40:39 PM PDT 24
Finished Jun 29 06:40:48 PM PDT 24
Peak memory 221544 kb
Host smart-d0633a46-3b3b-4f99-8cba-e375184bcafa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842275114 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3842275114
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2893732546
Short name T142
Test name
Test status
Simulation time 414228048 ps
CPU time 2.43 seconds
Started Jun 29 06:40:45 PM PDT 24
Finished Jun 29 06:40:49 PM PDT 24
Peak memory 213220 kb
Host smart-b5bfa62f-40ae-4551-a6d9-6862589ced8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893732546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2893732546
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.624922212
Short name T379
Test name
Test status
Simulation time 8653105630 ps
CPU time 22.4 seconds
Started Jun 29 06:40:45 PM PDT 24
Finished Jun 29 06:41:08 PM PDT 24
Peak memory 204964 kb
Host smart-0d5017db-42ba-4e2b-ada4-947ebcdd113f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624922212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rv_dm_jtag_dmi_csr_bit_bash.624922212
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3637858286
Short name T426
Test name
Test status
Simulation time 7692766490 ps
CPU time 5.81 seconds
Started Jun 29 06:40:42 PM PDT 24
Finished Jun 29 06:40:49 PM PDT 24
Peak memory 204972 kb
Host smart-4743b4d3-078b-4ef1-a185-7ea31cebf856
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637858286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3637858286
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3476487872
Short name T330
Test name
Test status
Simulation time 1065909867 ps
CPU time 1.47 seconds
Started Jun 29 06:40:51 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 204692 kb
Host smart-eac00588-bcb4-4753-8d80-a505ce3aaf51
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476487872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3476487872
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1703473495
Short name T435
Test name
Test status
Simulation time 762252417 ps
CPU time 7.04 seconds
Started Jun 29 06:40:51 PM PDT 24
Finished Jun 29 06:40:59 PM PDT 24
Peak memory 205096 kb
Host smart-64f2d505-af04-4ae1-8e1a-3ebf47306f95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703473495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.1703473495
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2678302301
Short name T425
Test name
Test status
Simulation time 229723282 ps
CPU time 3 seconds
Started Jun 29 06:40:47 PM PDT 24
Finished Jun 29 06:40:51 PM PDT 24
Peak memory 215900 kb
Host smart-98cc7241-2f71-40dd-ac11-334a9af0b7ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678302301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2678302301
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1473996418
Short name T341
Test name
Test status
Simulation time 947511164 ps
CPU time 10.43 seconds
Started Jun 29 06:40:49 PM PDT 24
Finished Jun 29 06:41:00 PM PDT 24
Peak memory 213288 kb
Host smart-c97bfa27-5939-470c-ab0b-ec943536eca3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473996418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
473996418
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1497070715
Short name T111
Test name
Test status
Simulation time 269558529 ps
CPU time 3.3 seconds
Started Jun 29 06:40:56 PM PDT 24
Finished Jun 29 06:41:00 PM PDT 24
Peak memory 213272 kb
Host smart-fcc2bbbe-8e1f-405b-a049-ad1e3adb42c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497070715 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1497070715
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3519337137
Short name T402
Test name
Test status
Simulation time 113487136 ps
CPU time 1.77 seconds
Started Jun 29 06:41:00 PM PDT 24
Finished Jun 29 06:41:03 PM PDT 24
Peak memory 213224 kb
Host smart-eb5a8450-60c2-4b2c-a632-b549ddef8a36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519337137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3519337137
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1807216351
Short name T299
Test name
Test status
Simulation time 43841473499 ps
CPU time 32.95 seconds
Started Jun 29 06:40:52 PM PDT 24
Finished Jun 29 06:41:26 PM PDT 24
Peak memory 204980 kb
Host smart-ed129c55-a558-4d07-9c56-a4c4446578e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807216351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1807216351
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1839809071
Short name T303
Test name
Test status
Simulation time 3069865119 ps
CPU time 8.21 seconds
Started Jun 29 06:40:54 PM PDT 24
Finished Jun 29 06:41:03 PM PDT 24
Peak memory 204960 kb
Host smart-01abb8dd-03fb-42b2-8baf-8dbbe515e809
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839809071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1839809071
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.22052452
Short name T415
Test name
Test status
Simulation time 244937159 ps
CPU time 1.15 seconds
Started Jun 29 06:40:41 PM PDT 24
Finished Jun 29 06:40:42 PM PDT 24
Peak memory 204704 kb
Host smart-7cca34d7-5c12-4888-8158-eda5fd75b94b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22052452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.22052452
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4066717651
Short name T120
Test name
Test status
Simulation time 3314233133 ps
CPU time 4.25 seconds
Started Jun 29 06:40:49 PM PDT 24
Finished Jun 29 06:40:55 PM PDT 24
Peak memory 205176 kb
Host smart-d1dd5e32-8c2e-46a6-81cf-7a9a34e79f38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066717651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.4066717651
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3146485383
Short name T347
Test name
Test status
Simulation time 488963777 ps
CPU time 3.17 seconds
Started Jun 29 06:40:40 PM PDT 24
Finished Jun 29 06:40:44 PM PDT 24
Peak memory 213364 kb
Host smart-c32572b7-a5d0-4ec7-baa3-675961211541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146485383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3146485383
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1053556682
Short name T79
Test name
Test status
Simulation time 4931848643 ps
CPU time 27.33 seconds
Started Jun 29 06:40:50 PM PDT 24
Finished Jun 29 06:41:19 PM PDT 24
Peak memory 213368 kb
Host smart-756909e6-a6d8-4bf8-bfca-2c0cc3dc269e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053556682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
053556682
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2749123750
Short name T81
Test name
Test status
Simulation time 2823365293 ps
CPU time 3.24 seconds
Started Jun 29 06:40:47 PM PDT 24
Finished Jun 29 06:40:52 PM PDT 24
Peak memory 221612 kb
Host smart-160fd1f2-66f6-4c69-bc9c-f2b5088edf31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749123750 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2749123750
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1823790878
Short name T124
Test name
Test status
Simulation time 66472389 ps
CPU time 1.55 seconds
Started Jun 29 06:40:58 PM PDT 24
Finished Jun 29 06:41:00 PM PDT 24
Peak memory 213228 kb
Host smart-6de68a02-57ba-4a12-839d-6eca94a4f3da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823790878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1823790878
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2421067667
Short name T300
Test name
Test status
Simulation time 102201632 ps
CPU time 0.7 seconds
Started Jun 29 06:40:58 PM PDT 24
Finished Jun 29 06:40:59 PM PDT 24
Peak memory 204696 kb
Host smart-335add00-dc16-4e76-a373-24a3fa3d68af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421067667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2421067667
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.518702431
Short name T370
Test name
Test status
Simulation time 988107038 ps
CPU time 1.53 seconds
Started Jun 29 06:40:51 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 204916 kb
Host smart-bd05a23d-4310-4b99-92a2-959058f052c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518702431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.518702431
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.825254281
Short name T410
Test name
Test status
Simulation time 800439096 ps
CPU time 1.26 seconds
Started Jun 29 06:40:59 PM PDT 24
Finished Jun 29 06:41:01 PM PDT 24
Peak memory 204700 kb
Host smart-d9af3564-5298-4b8c-99f4-8cb8dd6edf32
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825254281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.825254281
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1944165130
Short name T403
Test name
Test status
Simulation time 101055014 ps
CPU time 3.46 seconds
Started Jun 29 06:40:52 PM PDT 24
Finished Jun 29 06:40:56 PM PDT 24
Peak memory 205104 kb
Host smart-a92497cc-30e4-426a-bc1c-4d733db8f4b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944165130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1944165130
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3380066869
Short name T354
Test name
Test status
Simulation time 215010717 ps
CPU time 3.52 seconds
Started Jun 29 06:40:49 PM PDT 24
Finished Jun 29 06:40:54 PM PDT 24
Peak memory 213288 kb
Host smart-1f782f2e-9728-44d3-ac95-05b595bc1cd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380066869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3380066869
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1475998551
Short name T184
Test name
Test status
Simulation time 8302545409 ps
CPU time 18.43 seconds
Started Jun 29 06:40:54 PM PDT 24
Finished Jun 29 06:41:13 PM PDT 24
Peak memory 213312 kb
Host smart-27c34687-7353-46cb-85c6-112d9cb1acf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475998551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
475998551
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3317301893
Short name T316
Test name
Test status
Simulation time 1522081929 ps
CPU time 4.34 seconds
Started Jun 29 06:41:04 PM PDT 24
Finished Jun 29 06:41:09 PM PDT 24
Peak memory 219400 kb
Host smart-09a2de3d-ff26-4d3b-b189-8fc948ea494f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317301893 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3317301893
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1426702411
Short name T118
Test name
Test status
Simulation time 423840482 ps
CPU time 2.47 seconds
Started Jun 29 06:40:59 PM PDT 24
Finished Jun 29 06:41:02 PM PDT 24
Peak memory 213240 kb
Host smart-57a44504-d0dd-410d-8d2c-0e2e1b5540cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426702411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1426702411
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.538355778
Short name T325
Test name
Test status
Simulation time 7365656155 ps
CPU time 16.12 seconds
Started Jun 29 06:40:49 PM PDT 24
Finished Jun 29 06:41:06 PM PDT 24
Peak memory 204940 kb
Host smart-3a8599d7-caf0-4008-a47e-7c0ca9c5e9d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538355778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
rv_dm_jtag_dmi_csr_bit_bash.538355778
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1462333993
Short name T405
Test name
Test status
Simulation time 4165429588 ps
CPU time 7.08 seconds
Started Jun 29 06:40:48 PM PDT 24
Finished Jun 29 06:40:56 PM PDT 24
Peak memory 204960 kb
Host smart-04654544-af0b-4a89-b305-b004f1bee905
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462333993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1462333993
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1696331322
Short name T373
Test name
Test status
Simulation time 266405849 ps
CPU time 0.85 seconds
Started Jun 29 06:40:49 PM PDT 24
Finished Jun 29 06:40:51 PM PDT 24
Peak memory 204724 kb
Host smart-da38c180-7836-47bc-9d3f-8aeb71d819d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696331322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1696331322
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1295651964
Short name T140
Test name
Test status
Simulation time 177546781 ps
CPU time 3.56 seconds
Started Jun 29 06:40:54 PM PDT 24
Finished Jun 29 06:40:58 PM PDT 24
Peak memory 205180 kb
Host smart-0ab1f0f4-1b99-455e-9685-f8170f2eb7dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295651964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1295651964
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2751952305
Short name T419
Test name
Test status
Simulation time 215532224 ps
CPU time 3.25 seconds
Started Jun 29 06:40:45 PM PDT 24
Finished Jun 29 06:40:50 PM PDT 24
Peak memory 213292 kb
Host smart-dc89adf6-1085-4619-8142-2e3771affea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751952305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2751952305
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1347895639
Short name T181
Test name
Test status
Simulation time 3969970282 ps
CPU time 12.95 seconds
Started Jun 29 06:40:59 PM PDT 24
Finished Jun 29 06:41:12 PM PDT 24
Peak memory 213372 kb
Host smart-2e60af97-f46f-461a-9746-80557f77fe7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347895639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
347895639
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2132413557
Short name T112
Test name
Test status
Simulation time 313162965 ps
CPU time 2.18 seconds
Started Jun 29 06:40:44 PM PDT 24
Finished Jun 29 06:40:46 PM PDT 24
Peak memory 215980 kb
Host smart-bce84e12-d5d2-467b-95d6-995d6c5b1da8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132413557 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2132413557
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3120793249
Short name T326
Test name
Test status
Simulation time 170304007 ps
CPU time 1.57 seconds
Started Jun 29 06:40:49 PM PDT 24
Finished Jun 29 06:40:52 PM PDT 24
Peak memory 213188 kb
Host smart-ba8fc1e1-6dca-474d-bfeb-5f9aeb841b80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120793249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3120793249
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.990176264
Short name T331
Test name
Test status
Simulation time 1906723713 ps
CPU time 5.97 seconds
Started Jun 29 06:40:56 PM PDT 24
Finished Jun 29 06:41:03 PM PDT 24
Peak memory 204884 kb
Host smart-551ecc93-5bed-484f-8aab-cc6dd74becc8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990176264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
rv_dm_jtag_dmi_csr_bit_bash.990176264
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.48850166
Short name T359
Test name
Test status
Simulation time 1273092532 ps
CPU time 1.73 seconds
Started Jun 29 06:40:52 PM PDT 24
Finished Jun 29 06:40:54 PM PDT 24
Peak memory 204860 kb
Host smart-c29d4278-ba3d-475b-9c83-3943ff2a6a54
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48850166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.48850166
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.484003693
Short name T310
Test name
Test status
Simulation time 103512951 ps
CPU time 0.89 seconds
Started Jun 29 06:40:49 PM PDT 24
Finished Jun 29 06:40:51 PM PDT 24
Peak memory 204740 kb
Host smart-19142b4e-dadb-416c-917e-b36ae3385a19
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484003693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.484003693
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.569291138
Short name T133
Test name
Test status
Simulation time 429554008 ps
CPU time 6.89 seconds
Started Jun 29 06:40:49 PM PDT 24
Finished Jun 29 06:40:57 PM PDT 24
Peak memory 205104 kb
Host smart-b6a18458-614e-452d-ba00-2567fbfca60c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569291138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_
csr_outstanding.569291138
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1845223765
Short name T116
Test name
Test status
Simulation time 222474915 ps
CPU time 3.47 seconds
Started Jun 29 06:40:50 PM PDT 24
Finished Jun 29 06:40:55 PM PDT 24
Peak memory 213364 kb
Host smart-0c40b40e-d253-40ca-bc5c-9daa7383fd74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845223765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1845223765
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3999221265
Short name T372
Test name
Test status
Simulation time 1554123127 ps
CPU time 12.76 seconds
Started Jun 29 06:40:50 PM PDT 24
Finished Jun 29 06:41:04 PM PDT 24
Peak memory 213292 kb
Host smart-9ae597d7-8624-4b7d-b59d-6399fd26c4ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999221265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
999221265
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1766419024
Short name T309
Test name
Test status
Simulation time 1638667284 ps
CPU time 4.13 seconds
Started Jun 29 06:40:51 PM PDT 24
Finished Jun 29 06:40:56 PM PDT 24
Peak memory 213420 kb
Host smart-1409ee4c-1896-4564-97a4-5f36e1a0759e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766419024 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1766419024
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2696671693
Short name T148
Test name
Test status
Simulation time 163410998 ps
CPU time 2.52 seconds
Started Jun 29 06:40:53 PM PDT 24
Finished Jun 29 06:40:56 PM PDT 24
Peak memory 213236 kb
Host smart-cebe5830-02a6-41fb-8acc-857f441414f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696671693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2696671693
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1741303001
Short name T414
Test name
Test status
Simulation time 29090500214 ps
CPU time 37.07 seconds
Started Jun 29 06:40:50 PM PDT 24
Finished Jun 29 06:41:28 PM PDT 24
Peak memory 204964 kb
Host smart-f5424571-17b3-4a87-9206-99db878af1d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741303001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.1741303001
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.460431060
Short name T360
Test name
Test status
Simulation time 6323310876 ps
CPU time 2.06 seconds
Started Jun 29 06:40:49 PM PDT 24
Finished Jun 29 06:40:52 PM PDT 24
Peak memory 205124 kb
Host smart-b7e79a26-a7a7-424d-89bf-e957a439d819
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460431060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.460431060
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.591022766
Short name T307
Test name
Test status
Simulation time 471398688 ps
CPU time 0.81 seconds
Started Jun 29 06:40:49 PM PDT 24
Finished Jun 29 06:40:51 PM PDT 24
Peak memory 204728 kb
Host smart-7756d987-85cb-4fd9-ba25-6f94fdcf427a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591022766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.591022766
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.946432368
Short name T115
Test name
Test status
Simulation time 217190263 ps
CPU time 1.74 seconds
Started Jun 29 06:40:43 PM PDT 24
Finished Jun 29 06:40:46 PM PDT 24
Peak memory 221576 kb
Host smart-c19dd0f5-2517-4577-a085-f353ec332827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946432368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.946432368
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3215289972
Short name T110
Test name
Test status
Simulation time 1065238690 ps
CPU time 10.71 seconds
Started Jun 29 06:40:50 PM PDT 24
Finished Jun 29 06:41:01 PM PDT 24
Peak memory 213296 kb
Host smart-b523e5f5-ae95-4145-922b-c4e381631de0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215289972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
215289972
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1552913415
Short name T386
Test name
Test status
Simulation time 214610677 ps
CPU time 2.66 seconds
Started Jun 29 06:41:09 PM PDT 24
Finished Jun 29 06:41:12 PM PDT 24
Peak memory 217084 kb
Host smart-7b0cfb7f-7474-47ad-b30b-5bf733c55fd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552913415 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1552913415
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.122422517
Short name T388
Test name
Test status
Simulation time 102212069 ps
CPU time 1.51 seconds
Started Jun 29 06:40:57 PM PDT 24
Finished Jun 29 06:40:59 PM PDT 24
Peak memory 213240 kb
Host smart-79db06d3-171d-4a23-96a8-16e41bb47310
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122422517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.122422517
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.4056364186
Short name T302
Test name
Test status
Simulation time 4866459367 ps
CPU time 13.76 seconds
Started Jun 29 06:40:40 PM PDT 24
Finished Jun 29 06:40:54 PM PDT 24
Peak memory 204932 kb
Host smart-d99f0fad-0dca-4f2a-8ff9-1ed91d236e8f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056364186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.4056364186
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.320067306
Short name T315
Test name
Test status
Simulation time 3478876824 ps
CPU time 10.14 seconds
Started Jun 29 06:40:55 PM PDT 24
Finished Jun 29 06:41:06 PM PDT 24
Peak memory 204976 kb
Host smart-bcf37263-bc5e-4681-94c0-15c25eb9852e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320067306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.320067306
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.218058107
Short name T305
Test name
Test status
Simulation time 283687910 ps
CPU time 0.98 seconds
Started Jun 29 06:40:50 PM PDT 24
Finished Jun 29 06:40:52 PM PDT 24
Peak memory 204728 kb
Host smart-9820e46d-89c5-4494-9b54-90e2ef367c2f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218058107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.218058107
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2600750497
Short name T417
Test name
Test status
Simulation time 275695472 ps
CPU time 4.14 seconds
Started Jun 29 06:40:46 PM PDT 24
Finished Jun 29 06:40:51 PM PDT 24
Peak memory 205036 kb
Host smart-0b1d2ca2-53a9-4e98-aaef-d45770c7eadf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600750497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.2600750497
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1515043390
Short name T319
Test name
Test status
Simulation time 154686652 ps
CPU time 2.29 seconds
Started Jun 29 06:40:50 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 213328 kb
Host smart-a14af3a0-6623-49a9-9aa9-bef4e6aa68ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515043390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1515043390
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4021752977
Short name T154
Test name
Test status
Simulation time 166210349 ps
CPU time 2.47 seconds
Started Jun 29 06:40:56 PM PDT 24
Finished Jun 29 06:40:59 PM PDT 24
Peak memory 221524 kb
Host smart-23e68c32-aed8-4f22-970d-2985913f1ed9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021752977 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.4021752977
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4049039973
Short name T83
Test name
Test status
Simulation time 661348135 ps
CPU time 2.51 seconds
Started Jun 29 06:40:46 PM PDT 24
Finished Jun 29 06:40:49 PM PDT 24
Peak memory 213172 kb
Host smart-b3ea4ccd-585a-4c93-b2ee-f2e3717b2b78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049039973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.4049039973
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.782801105
Short name T406
Test name
Test status
Simulation time 2750011281 ps
CPU time 4.55 seconds
Started Jun 29 06:40:47 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 204972 kb
Host smart-95b75fb8-5eea-4028-957b-92f391004b72
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782801105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.782801105
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3501850149
Short name T408
Test name
Test status
Simulation time 2789222823 ps
CPU time 8.96 seconds
Started Jun 29 06:40:48 PM PDT 24
Finished Jun 29 06:40:58 PM PDT 24
Peak memory 204972 kb
Host smart-9bc0154f-cd26-429e-8b84-4f3088d24d75
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501850149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3501850149
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1489478897
Short name T429
Test name
Test status
Simulation time 584219453 ps
CPU time 1.64 seconds
Started Jun 29 06:40:54 PM PDT 24
Finished Jun 29 06:40:57 PM PDT 24
Peak memory 204656 kb
Host smart-6de8fb23-6028-4135-aeeb-a2bf79f072c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489478897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1489478897
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3650456847
Short name T365
Test name
Test status
Simulation time 389286463 ps
CPU time 6.65 seconds
Started Jun 29 06:40:51 PM PDT 24
Finished Jun 29 06:40:58 PM PDT 24
Peak memory 205092 kb
Host smart-8ad77166-53a0-4a15-bd77-8968995b61e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650456847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3650456847
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1626426346
Short name T317
Test name
Test status
Simulation time 265428055 ps
CPU time 3.21 seconds
Started Jun 29 06:40:54 PM PDT 24
Finished Jun 29 06:40:58 PM PDT 24
Peak memory 213288 kb
Host smart-9217fd2d-3f10-4ed8-a67c-c6bc49b5250d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626426346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1626426346
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3720296248
Short name T183
Test name
Test status
Simulation time 523315034 ps
CPU time 8.91 seconds
Started Jun 29 06:40:50 PM PDT 24
Finished Jun 29 06:41:00 PM PDT 24
Peak memory 213360 kb
Host smart-7aa1a5e6-6ffc-4688-9c00-97a74edae6a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720296248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
720296248
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2756907793
Short name T313
Test name
Test status
Simulation time 4171587183 ps
CPU time 10.17 seconds
Started Jun 29 06:40:57 PM PDT 24
Finished Jun 29 06:41:07 PM PDT 24
Peak memory 220580 kb
Host smart-87f3be1a-d0f5-4953-a900-1362d056b684
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756907793 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2756907793
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1199035816
Short name T147
Test name
Test status
Simulation time 61051145 ps
CPU time 1.47 seconds
Started Jun 29 06:40:54 PM PDT 24
Finished Jun 29 06:40:57 PM PDT 24
Peak memory 213188 kb
Host smart-c6ffd676-d241-487e-a89f-b45ba2581056
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199035816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1199035816
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1356981957
Short name T377
Test name
Test status
Simulation time 7607575124 ps
CPU time 9.64 seconds
Started Jun 29 06:41:09 PM PDT 24
Finished Jun 29 06:41:20 PM PDT 24
Peak memory 204960 kb
Host smart-a1b60b9c-f77c-4256-9f84-ba377bae92ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356981957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.1356981957
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1481432234
Short name T382
Test name
Test status
Simulation time 3453328948 ps
CPU time 10.74 seconds
Started Jun 29 06:40:48 PM PDT 24
Finished Jun 29 06:41:00 PM PDT 24
Peak memory 204960 kb
Host smart-02d391a4-434c-4d50-96c0-a0726e047ccd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481432234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1481432234
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2852025195
Short name T101
Test name
Test status
Simulation time 798317191 ps
CPU time 2.63 seconds
Started Jun 29 06:40:49 PM PDT 24
Finished Jun 29 06:40:52 PM PDT 24
Peak memory 204724 kb
Host smart-83cbca58-49ff-4285-9ed5-45c3d36e1b55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852025195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2852025195
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3276412461
Short name T129
Test name
Test status
Simulation time 2142883330 ps
CPU time 7.95 seconds
Started Jun 29 06:40:47 PM PDT 24
Finished Jun 29 06:40:56 PM PDT 24
Peak memory 205100 kb
Host smart-e0f7df00-ec37-4526-b8ca-b9a1bf89d01f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276412461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3276412461
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1329558910
Short name T361
Test name
Test status
Simulation time 531952191 ps
CPU time 4.44 seconds
Started Jun 29 06:40:54 PM PDT 24
Finished Jun 29 06:40:59 PM PDT 24
Peak memory 213368 kb
Host smart-cf8739df-c77f-4f89-bdd3-20aa6354d9c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329558910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1329558910
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4044146837
Short name T185
Test name
Test status
Simulation time 7554960443 ps
CPU time 18.57 seconds
Started Jun 29 06:41:04 PM PDT 24
Finished Jun 29 06:41:23 PM PDT 24
Peak memory 213292 kb
Host smart-992d3a42-e03f-4505-8918-abec9a0dcc05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044146837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4
044146837
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1092086955
Short name T238
Test name
Test status
Simulation time 1685428476 ps
CPU time 5.25 seconds
Started Jun 29 06:40:56 PM PDT 24
Finished Jun 29 06:41:02 PM PDT 24
Peak memory 220364 kb
Host smart-b2e5262d-4170-4723-9265-dd8efa91a8c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092086955 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1092086955
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3795988154
Short name T119
Test name
Test status
Simulation time 116435657 ps
CPU time 2.43 seconds
Started Jun 29 06:40:48 PM PDT 24
Finished Jun 29 06:40:52 PM PDT 24
Peak memory 213224 kb
Host smart-08ce41ba-7496-4c9f-b2d4-d945d75a3c88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795988154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3795988154
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2403500449
Short name T391
Test name
Test status
Simulation time 18416939531 ps
CPU time 8.4 seconds
Started Jun 29 06:40:58 PM PDT 24
Finished Jun 29 06:41:07 PM PDT 24
Peak memory 204968 kb
Host smart-c6365159-52d0-4691-bab5-0e241e3c79e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403500449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2403500449
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3910092791
Short name T430
Test name
Test status
Simulation time 2949190657 ps
CPU time 8.65 seconds
Started Jun 29 06:41:03 PM PDT 24
Finished Jun 29 06:41:12 PM PDT 24
Peak memory 204960 kb
Host smart-5fbe57fa-3d9c-4b65-88d7-e53da8c8e9b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910092791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3910092791
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2095341829
Short name T393
Test name
Test status
Simulation time 493827005 ps
CPU time 1.91 seconds
Started Jun 29 06:40:47 PM PDT 24
Finished Jun 29 06:40:50 PM PDT 24
Peak memory 204696 kb
Host smart-2f361679-9204-4d1d-9766-ae0d7c5202f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095341829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2095341829
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1369926715
Short name T424
Test name
Test status
Simulation time 840423058 ps
CPU time 4.37 seconds
Started Jun 29 06:40:47 PM PDT 24
Finished Jun 29 06:40:52 PM PDT 24
Peak memory 205092 kb
Host smart-1c2c118c-b016-4c79-a066-823d057b681e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369926715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1369926715
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2373290044
Short name T329
Test name
Test status
Simulation time 355397623 ps
CPU time 3.35 seconds
Started Jun 29 06:40:48 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 213272 kb
Host smart-d7a9610a-59b5-43ea-922b-b454bba5abb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373290044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2373290044
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2830336449
Short name T178
Test name
Test status
Simulation time 4039121694 ps
CPU time 20.56 seconds
Started Jun 29 06:40:55 PM PDT 24
Finished Jun 29 06:41:16 PM PDT 24
Peak memory 213352 kb
Host smart-9b84c9ad-2ab8-4414-a642-d29149d0de1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830336449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
830336449
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1743031807
Short name T366
Test name
Test status
Simulation time 2969030657 ps
CPU time 28.63 seconds
Started Jun 29 06:40:22 PM PDT 24
Finished Jun 29 06:40:50 PM PDT 24
Peak memory 213296 kb
Host smart-ca2360ef-694a-412f-abe6-9949cb5c2a1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743031807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1743031807
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.101217344
Short name T139
Test name
Test status
Simulation time 153582295 ps
CPU time 2.57 seconds
Started Jun 29 06:40:28 PM PDT 24
Finished Jun 29 06:40:31 PM PDT 24
Peak memory 214244 kb
Host smart-231c29e2-0919-4aaa-9dc5-07ce77c341a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101217344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.101217344
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4059752109
Short name T433
Test name
Test status
Simulation time 1433040826 ps
CPU time 3.16 seconds
Started Jun 29 06:40:33 PM PDT 24
Finished Jun 29 06:40:36 PM PDT 24
Peak memory 217184 kb
Host smart-a5e72eed-49f2-4094-ba13-5c2f59723bdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059752109 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.4059752109
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1637673451
Short name T131
Test name
Test status
Simulation time 87124296 ps
CPU time 1.67 seconds
Started Jun 29 06:40:31 PM PDT 24
Finished Jun 29 06:40:33 PM PDT 24
Peak memory 213236 kb
Host smart-25c5ae82-ef09-442a-a4dc-f88e2bec3ee6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637673451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1637673451
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2465401718
Short name T297
Test name
Test status
Simulation time 119632823786 ps
CPU time 316.72 seconds
Started Jun 29 06:40:39 PM PDT 24
Finished Jun 29 06:45:57 PM PDT 24
Peak memory 204968 kb
Host smart-945adb2f-0a59-480d-acf6-ae3b33477eee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465401718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2465401718
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1879618551
Short name T338
Test name
Test status
Simulation time 2081192930 ps
CPU time 6.23 seconds
Started Jun 29 06:40:38 PM PDT 24
Finished Jun 29 06:40:45 PM PDT 24
Peak memory 204788 kb
Host smart-ef10b862-72e4-4485-b65a-6b5159fdcfef
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879618551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1879618551
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1096551241
Short name T127
Test name
Test status
Simulation time 3597319274 ps
CPU time 4.65 seconds
Started Jun 29 06:40:31 PM PDT 24
Finished Jun 29 06:40:36 PM PDT 24
Peak memory 205032 kb
Host smart-e19cd598-5d7a-4155-8a1a-c18fd17d5f02
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096551241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1096551241
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2009258907
Short name T296
Test name
Test status
Simulation time 2878372549 ps
CPU time 8.37 seconds
Started Jun 29 06:40:38 PM PDT 24
Finished Jun 29 06:40:47 PM PDT 24
Peak memory 204960 kb
Host smart-e4bc5dc2-7def-4705-b49c-401074cd332c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009258907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
009258907
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2719695265
Short name T421
Test name
Test status
Simulation time 1589099106 ps
CPU time 2.9 seconds
Started Jun 29 06:40:30 PM PDT 24
Finished Jun 29 06:40:33 PM PDT 24
Peak memory 204712 kb
Host smart-7e0c03be-98fd-4771-aab9-c490a6100cd8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719695265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2719695265
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3413435131
Short name T371
Test name
Test status
Simulation time 8463069810 ps
CPU time 7.67 seconds
Started Jun 29 06:40:47 PM PDT 24
Finished Jun 29 06:40:56 PM PDT 24
Peak memory 204964 kb
Host smart-d8b2e6da-3d6b-4c0a-b812-937ee26ec2bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413435131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.3413435131
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.366600124
Short name T358
Test name
Test status
Simulation time 904944795 ps
CPU time 1.76 seconds
Started Jun 29 06:40:13 PM PDT 24
Finished Jun 29 06:40:15 PM PDT 24
Peak memory 204720 kb
Host smart-dbc07987-eaf2-4484-8dc1-60174d18bf29
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366600124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.366600124
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4436301
Short name T314
Test name
Test status
Simulation time 480777684 ps
CPU time 2.08 seconds
Started Jun 29 06:40:39 PM PDT 24
Finished Jun 29 06:40:42 PM PDT 24
Peak memory 204732 kb
Host smart-92d61815-15d0-4235-99d3-19095d29a8b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4436301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.4436301
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1574352340
Short name T336
Test name
Test status
Simulation time 89309728 ps
CPU time 0.89 seconds
Started Jun 29 06:40:28 PM PDT 24
Finished Jun 29 06:40:29 PM PDT 24
Peak memory 204720 kb
Host smart-cc2a52c4-0ff0-41d7-a511-f042418d2c29
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574352340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1574352340
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1142894997
Short name T304
Test name
Test status
Simulation time 155351353 ps
CPU time 0.79 seconds
Started Jun 29 06:40:26 PM PDT 24
Finished Jun 29 06:40:27 PM PDT 24
Peak memory 204656 kb
Host smart-856bd2f9-5223-4876-880b-32e745b0c3dc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142894997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1142894997
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1422521242
Short name T135
Test name
Test status
Simulation time 303788776 ps
CPU time 4.36 seconds
Started Jun 29 06:40:25 PM PDT 24
Finished Jun 29 06:40:30 PM PDT 24
Peak memory 205136 kb
Host smart-bbf8e3b5-48e7-4719-97ab-553a94f62b36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422521242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1422521242
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1402274832
Short name T186
Test name
Test status
Simulation time 47339112500 ps
CPU time 146.19 seconds
Started Jun 29 06:40:33 PM PDT 24
Finished Jun 29 06:43:00 PM PDT 24
Peak memory 222016 kb
Host smart-ce00a164-1d43-4bfa-a38c-a35e554db1a8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402274832 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.1402274832
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.521048638
Short name T369
Test name
Test status
Simulation time 616819634 ps
CPU time 5.06 seconds
Started Jun 29 06:40:24 PM PDT 24
Finished Jun 29 06:40:29 PM PDT 24
Peak memory 213280 kb
Host smart-020470ae-4fc6-4eff-9e8f-5aa298f1e4c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521048638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.521048638
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1731171212
Short name T344
Test name
Test status
Simulation time 2266994382 ps
CPU time 14.8 seconds
Started Jun 29 06:40:47 PM PDT 24
Finished Jun 29 06:41:03 PM PDT 24
Peak memory 221508 kb
Host smart-fdfae81a-758b-4cd3-83e3-683229157d0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731171212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1731171212
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1893598046
Short name T390
Test name
Test status
Simulation time 7148101482 ps
CPU time 31.03 seconds
Started Jun 29 06:40:36 PM PDT 24
Finished Jun 29 06:41:07 PM PDT 24
Peak memory 204992 kb
Host smart-a089e977-6f7f-4870-a77e-973f5d857e12
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893598046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1893598046
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3884516741
Short name T146
Test name
Test status
Simulation time 61055383372 ps
CPU time 70.34 seconds
Started Jun 29 06:40:25 PM PDT 24
Finished Jun 29 06:41:35 PM PDT 24
Peak memory 205144 kb
Host smart-5c2feb43-1dc8-4d4d-b96f-fdd79cd6806f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884516741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3884516741
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.978908032
Short name T130
Test name
Test status
Simulation time 437366568 ps
CPU time 1.67 seconds
Started Jun 29 06:40:26 PM PDT 24
Finished Jun 29 06:40:28 PM PDT 24
Peak memory 213236 kb
Host smart-20b70aa6-338d-450b-8db8-e08f51cc87a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978908032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.978908032
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3172062550
Short name T105
Test name
Test status
Simulation time 861121038 ps
CPU time 4.14 seconds
Started Jun 29 06:40:25 PM PDT 24
Finished Jun 29 06:40:29 PM PDT 24
Peak memory 221480 kb
Host smart-872cc0ed-bee1-4729-a222-98c9cec033e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172062550 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3172062550
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3561523096
Short name T143
Test name
Test status
Simulation time 1099588904 ps
CPU time 2.42 seconds
Started Jun 29 06:40:26 PM PDT 24
Finished Jun 29 06:40:28 PM PDT 24
Peak memory 213252 kb
Host smart-23e97e0d-2253-4543-9882-2bc8129d6a19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561523096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3561523096
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2779717874
Short name T392
Test name
Test status
Simulation time 36382665370 ps
CPU time 39.85 seconds
Started Jun 29 06:40:34 PM PDT 24
Finished Jun 29 06:41:14 PM PDT 24
Peak memory 204968 kb
Host smart-6ccadb79-9c54-49b5-9a05-dc67d9af3200
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779717874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2779717874
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3241781792
Short name T301
Test name
Test status
Simulation time 15126805897 ps
CPU time 12.54 seconds
Started Jun 29 06:40:26 PM PDT 24
Finished Jun 29 06:40:39 PM PDT 24
Peak memory 204988 kb
Host smart-a3ba3888-5c88-4c53-b8cc-8b6bb8f3b96b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241781792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.3241781792
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2723468919
Short name T126
Test name
Test status
Simulation time 18924338352 ps
CPU time 13.38 seconds
Started Jun 29 06:40:31 PM PDT 24
Finished Jun 29 06:40:45 PM PDT 24
Peak memory 213248 kb
Host smart-17deb54a-dbd2-4fca-be5e-34597b2fd54f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723468919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2723468919
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3383541877
Short name T407
Test name
Test status
Simulation time 9599236150 ps
CPU time 3.25 seconds
Started Jun 29 06:40:31 PM PDT 24
Finished Jun 29 06:40:35 PM PDT 24
Peak memory 204960 kb
Host smart-6b72fcd4-f5b5-4cf2-bd05-5f74d4e115bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383541877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
383541877
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3208316373
Short name T337
Test name
Test status
Simulation time 389655465 ps
CPU time 1.08 seconds
Started Jun 29 06:40:32 PM PDT 24
Finished Jun 29 06:40:34 PM PDT 24
Peak memory 204716 kb
Host smart-039d6043-905f-46a5-9d8d-c33c94e40ef4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208316373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3208316373
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1916809275
Short name T346
Test name
Test status
Simulation time 12737369643 ps
CPU time 33.34 seconds
Started Jun 29 06:40:25 PM PDT 24
Finished Jun 29 06:40:59 PM PDT 24
Peak memory 205012 kb
Host smart-1b1e0844-d015-41dc-a62f-e6b69f377b19
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916809275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1916809275
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1778604485
Short name T356
Test name
Test status
Simulation time 160965938 ps
CPU time 0.93 seconds
Started Jun 29 06:40:28 PM PDT 24
Finished Jun 29 06:40:29 PM PDT 24
Peak memory 204728 kb
Host smart-4d3155d3-395b-4bd3-94ee-e7389e645580
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778604485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1778604485
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.334844238
Short name T381
Test name
Test status
Simulation time 133161720 ps
CPU time 1.03 seconds
Started Jun 29 06:40:53 PM PDT 24
Finished Jun 29 06:40:55 PM PDT 24
Peak memory 204716 kb
Host smart-3c34753e-ef3e-4913-8da4-1f7109b6a3e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334844238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.334844238
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2748708284
Short name T335
Test name
Test status
Simulation time 138122088 ps
CPU time 0.81 seconds
Started Jun 29 06:40:33 PM PDT 24
Finished Jun 29 06:40:34 PM PDT 24
Peak memory 204700 kb
Host smart-2ed3ea85-46cc-4c17-a565-06ee39e88718
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748708284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2748708284
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1246944809
Short name T298
Test name
Test status
Simulation time 25562895 ps
CPU time 0.72 seconds
Started Jun 29 06:40:37 PM PDT 24
Finished Jun 29 06:40:38 PM PDT 24
Peak memory 204724 kb
Host smart-e46b7124-d963-44bf-b55d-e5bb653462ea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246944809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1246944809
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2911450091
Short name T121
Test name
Test status
Simulation time 2705653538 ps
CPU time 8.26 seconds
Started Jun 29 06:40:28 PM PDT 24
Finished Jun 29 06:40:37 PM PDT 24
Peak memory 205152 kb
Host smart-eb6abe89-1b28-42d8-9945-15ae2a0bafb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911450091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2911450091
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1355154322
Short name T395
Test name
Test status
Simulation time 26505557578 ps
CPU time 38.63 seconds
Started Jun 29 06:40:39 PM PDT 24
Finished Jun 29 06:41:18 PM PDT 24
Peak memory 221508 kb
Host smart-69d31eb1-efc2-447c-b470-4ad0b9f9af31
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355154322 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.1355154322
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3901710607
Short name T340
Test name
Test status
Simulation time 1110370480 ps
CPU time 4.39 seconds
Started Jun 29 06:40:33 PM PDT 24
Finished Jun 29 06:40:38 PM PDT 24
Peak memory 213368 kb
Host smart-767fd4fc-438f-4b1e-b507-579a253a9082
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901710607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3901710607
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1268435109
Short name T145
Test name
Test status
Simulation time 2010721423 ps
CPU time 66.9 seconds
Started Jun 29 06:40:25 PM PDT 24
Finished Jun 29 06:41:32 PM PDT 24
Peak memory 213260 kb
Host smart-f5699de7-02c5-4cde-a1b1-495f688455c7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268435109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1268435109
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3908901238
Short name T117
Test name
Test status
Simulation time 4715153563 ps
CPU time 38.2 seconds
Started Jun 29 06:40:42 PM PDT 24
Finished Jun 29 06:41:21 PM PDT 24
Peak memory 205144 kb
Host smart-65d90189-c20f-4122-9c4f-f0c42741a911
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908901238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3908901238
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.965118683
Short name T136
Test name
Test status
Simulation time 168892059 ps
CPU time 1.9 seconds
Started Jun 29 06:40:46 PM PDT 24
Finished Jun 29 06:40:49 PM PDT 24
Peak memory 213200 kb
Host smart-8cd05bc4-1a2f-4839-918f-dc24ef9df170
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965118683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.965118683
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2095244860
Short name T334
Test name
Test status
Simulation time 2766900354 ps
CPU time 5.35 seconds
Started Jun 29 06:40:39 PM PDT 24
Finished Jun 29 06:40:45 PM PDT 24
Peak memory 219244 kb
Host smart-4308f996-49cc-4d97-af61-642270f213e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095244860 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2095244860
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3405580612
Short name T357
Test name
Test status
Simulation time 78606977 ps
CPU time 1.6 seconds
Started Jun 29 06:40:41 PM PDT 24
Finished Jun 29 06:40:43 PM PDT 24
Peak memory 213172 kb
Host smart-872830ae-c2dc-4505-9066-42a2f01ef661
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405580612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3405580612
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1014394138
Short name T351
Test name
Test status
Simulation time 22094470001 ps
CPU time 61.96 seconds
Started Jun 29 06:40:45 PM PDT 24
Finished Jun 29 06:41:48 PM PDT 24
Peak memory 204968 kb
Host smart-4954496b-ff9f-49ac-b97e-6c69da816239
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014394138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1014394138
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1643008550
Short name T332
Test name
Test status
Simulation time 14924054860 ps
CPU time 39.06 seconds
Started Jun 29 06:40:31 PM PDT 24
Finished Jun 29 06:41:10 PM PDT 24
Peak memory 204960 kb
Host smart-a6cf15fe-1152-48ba-b06f-021d192dfba1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643008550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.1643008550
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3633749292
Short name T128
Test name
Test status
Simulation time 14627275293 ps
CPU time 41.89 seconds
Started Jun 29 06:40:37 PM PDT 24
Finished Jun 29 06:41:19 PM PDT 24
Peak memory 213296 kb
Host smart-3163e95e-8132-4216-85f8-9e13d8a60e87
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633749292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3633749292
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.137963522
Short name T295
Test name
Test status
Simulation time 2331142093 ps
CPU time 2.2 seconds
Started Jun 29 06:40:55 PM PDT 24
Finished Jun 29 06:41:03 PM PDT 24
Peak memory 204960 kb
Host smart-4ca070ad-d4a9-4c7a-bf8c-1c6ed2c04aa6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137963522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.137963522
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3677544714
Short name T394
Test name
Test status
Simulation time 1655445832 ps
CPU time 3.3 seconds
Started Jun 29 06:40:36 PM PDT 24
Finished Jun 29 06:40:39 PM PDT 24
Peak memory 204732 kb
Host smart-90b892b9-4e43-4270-963a-aa1fd6bb3c43
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677544714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3677544714
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2837526949
Short name T428
Test name
Test status
Simulation time 3727570301 ps
CPU time 3.12 seconds
Started Jun 29 06:40:37 PM PDT 24
Finished Jun 29 06:40:40 PM PDT 24
Peak memory 204936 kb
Host smart-150adceb-b446-44c2-b8a4-d5540d5dec36
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837526949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2837526949
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1727161709
Short name T400
Test name
Test status
Simulation time 275623534 ps
CPU time 0.97 seconds
Started Jun 29 06:40:24 PM PDT 24
Finished Jun 29 06:40:25 PM PDT 24
Peak memory 204744 kb
Host smart-e61c0f68-ca0d-4522-9b36-ae9e8d46655d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727161709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1727161709
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2170239287
Short name T333
Test name
Test status
Simulation time 311001511 ps
CPU time 1.52 seconds
Started Jun 29 06:40:35 PM PDT 24
Finished Jun 29 06:40:37 PM PDT 24
Peak memory 204728 kb
Host smart-aa9cc95b-f818-4e4c-adf8-f7198f486aa7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170239287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
170239287
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3856369753
Short name T367
Test name
Test status
Simulation time 62637397 ps
CPU time 0.71 seconds
Started Jun 29 06:40:47 PM PDT 24
Finished Jun 29 06:40:49 PM PDT 24
Peak memory 204720 kb
Host smart-70a51d00-089c-44e2-98f8-36c07c35b1be
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856369753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3856369753
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3025074411
Short name T343
Test name
Test status
Simulation time 61333984 ps
CPU time 0.7 seconds
Started Jun 29 06:40:53 PM PDT 24
Finished Jun 29 06:40:54 PM PDT 24
Peak memory 204720 kb
Host smart-af591840-896c-4af1-9e58-93ae4a6ec71b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025074411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3025074411
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1483387894
Short name T149
Test name
Test status
Simulation time 225135046 ps
CPU time 4.08 seconds
Started Jun 29 06:40:39 PM PDT 24
Finished Jun 29 06:40:44 PM PDT 24
Peak memory 205164 kb
Host smart-ad223dcb-3eb6-4a2e-90e2-6cbe3224e03f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483387894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1483387894
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.614221956
Short name T420
Test name
Test status
Simulation time 148981164 ps
CPU time 2.73 seconds
Started Jun 29 06:40:42 PM PDT 24
Finished Jun 29 06:40:45 PM PDT 24
Peak memory 213320 kb
Host smart-f07059b9-a854-493a-ae1c-88612e06ef15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614221956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.614221956
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1973717416
Short name T389
Test name
Test status
Simulation time 2000390143 ps
CPU time 15.93 seconds
Started Jun 29 06:40:50 PM PDT 24
Finished Jun 29 06:41:07 PM PDT 24
Peak memory 213352 kb
Host smart-96693a6b-81a5-4dc0-b243-5f6a33538398
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973717416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1973717416
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.301130686
Short name T432
Test name
Test status
Simulation time 4154712923 ps
CPU time 3.98 seconds
Started Jun 29 06:41:03 PM PDT 24
Finished Jun 29 06:41:07 PM PDT 24
Peak memory 218388 kb
Host smart-b66f601a-e223-4ada-af4c-10c0f52b7c8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301130686 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.301130686
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2465365587
Short name T138
Test name
Test status
Simulation time 364301218 ps
CPU time 2.68 seconds
Started Jun 29 06:40:43 PM PDT 24
Finished Jun 29 06:40:46 PM PDT 24
Peak memory 213236 kb
Host smart-1226ffde-806d-447b-8902-4b8a875d5241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465365587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2465365587
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.584589188
Short name T376
Test name
Test status
Simulation time 2876682140 ps
CPU time 5.62 seconds
Started Jun 29 06:40:43 PM PDT 24
Finished Jun 29 06:40:49 PM PDT 24
Peak memory 204964 kb
Host smart-e758116a-fed1-4866-9b93-6bcef36a19e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584589188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r
v_dm_jtag_dmi_csr_bit_bash.584589188
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1716916154
Short name T387
Test name
Test status
Simulation time 9684884180 ps
CPU time 15.09 seconds
Started Jun 29 06:40:37 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 204964 kb
Host smart-e5caaea2-244b-4437-b030-6cd6ae035091
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716916154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
716916154
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.685915514
Short name T396
Test name
Test status
Simulation time 122171643 ps
CPU time 0.78 seconds
Started Jun 29 06:40:55 PM PDT 24
Finished Jun 29 06:40:56 PM PDT 24
Peak memory 204692 kb
Host smart-388bd6bb-3af7-418b-87e2-1eda9d348472
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685915514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.685915514
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1071903669
Short name T82
Test name
Test status
Simulation time 435513138 ps
CPU time 6.31 seconds
Started Jun 29 06:40:38 PM PDT 24
Finished Jun 29 06:40:45 PM PDT 24
Peak memory 205156 kb
Host smart-7b16e5f4-73de-4a66-b417-51a79530a68d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071903669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1071903669
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.4172234613
Short name T398
Test name
Test status
Simulation time 49502870 ps
CPU time 2.13 seconds
Started Jun 29 06:40:47 PM PDT 24
Finished Jun 29 06:40:51 PM PDT 24
Peak memory 213284 kb
Host smart-e434cc52-ed5a-4fb5-aea3-ed8d465ecc50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172234613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.4172234613
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2872291828
Short name T175
Test name
Test status
Simulation time 3118605814 ps
CPU time 12.7 seconds
Started Jun 29 06:40:52 PM PDT 24
Finished Jun 29 06:41:06 PM PDT 24
Peak memory 213384 kb
Host smart-b1a6bdf4-c345-426d-9d50-fa95c48b3246
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872291828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2872291828
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1410487867
Short name T114
Test name
Test status
Simulation time 195127268 ps
CPU time 2.44 seconds
Started Jun 29 06:40:45 PM PDT 24
Finished Jun 29 06:40:48 PM PDT 24
Peak memory 215520 kb
Host smart-486ddf74-7907-4bdb-985a-2346cf786abc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410487867 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1410487867
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1622742563
Short name T144
Test name
Test status
Simulation time 140368321 ps
CPU time 2.05 seconds
Started Jun 29 06:40:40 PM PDT 24
Finished Jun 29 06:40:43 PM PDT 24
Peak memory 213224 kb
Host smart-547160d7-2f42-4a07-861f-351106fdc506
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622742563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1622742563
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2726223156
Short name T364
Test name
Test status
Simulation time 13876522906 ps
CPU time 30.06 seconds
Started Jun 29 06:40:49 PM PDT 24
Finished Jun 29 06:41:20 PM PDT 24
Peak memory 204900 kb
Host smart-d97dc65d-46cd-41e7-a314-6899e3ee97c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726223156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.2726223156
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1097520332
Short name T380
Test name
Test status
Simulation time 9542941536 ps
CPU time 16.62 seconds
Started Jun 29 06:40:42 PM PDT 24
Finished Jun 29 06:40:59 PM PDT 24
Peak memory 204964 kb
Host smart-82d710c8-ee17-4428-a8f5-ab1f07d01130
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097520332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
097520332
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2709852894
Short name T384
Test name
Test status
Simulation time 438438193 ps
CPU time 1.12 seconds
Started Jun 29 06:40:43 PM PDT 24
Finished Jun 29 06:40:44 PM PDT 24
Peak memory 204740 kb
Host smart-cd119c2d-0b50-468a-9921-9d30ca0d41e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709852894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
709852894
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2498203443
Short name T134
Test name
Test status
Simulation time 1538511303 ps
CPU time 7.78 seconds
Started Jun 29 06:40:42 PM PDT 24
Finished Jun 29 06:40:50 PM PDT 24
Peak memory 205124 kb
Host smart-19ca8c5c-fd60-41be-a511-a76c867552e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498203443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2498203443
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3042595310
Short name T76
Test name
Test status
Simulation time 41665660326 ps
CPU time 32.98 seconds
Started Jun 29 06:40:50 PM PDT 24
Finished Jun 29 06:41:24 PM PDT 24
Peak memory 221516 kb
Host smart-3877ba84-673b-4cd9-bf1b-99f45025edca
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042595310 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3042595310
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1813292495
Short name T385
Test name
Test status
Simulation time 629011704 ps
CPU time 6.27 seconds
Started Jun 29 06:40:42 PM PDT 24
Finished Jun 29 06:40:49 PM PDT 24
Peak memory 213360 kb
Host smart-55fa5c56-64b6-4917-861a-95b020228d85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813292495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1813292495
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.283801316
Short name T409
Test name
Test status
Simulation time 1387644103 ps
CPU time 10.38 seconds
Started Jun 29 06:40:45 PM PDT 24
Finished Jun 29 06:40:56 PM PDT 24
Peak memory 213308 kb
Host smart-19cf6da4-eccd-4435-81e0-e6ea7085529f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283801316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.283801316
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3570194684
Short name T363
Test name
Test status
Simulation time 465083538 ps
CPU time 2.6 seconds
Started Jun 29 06:40:45 PM PDT 24
Finished Jun 29 06:40:49 PM PDT 24
Peak memory 218232 kb
Host smart-a612a584-a284-4eaa-a14a-29e865188132
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570194684 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3570194684
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3160928510
Short name T318
Test name
Test status
Simulation time 266372054 ps
CPU time 1.64 seconds
Started Jun 29 06:40:50 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 213236 kb
Host smart-5fb6c67a-bfc3-425a-906a-5d5857388934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160928510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3160928510
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2788726899
Short name T378
Test name
Test status
Simulation time 33370418153 ps
CPU time 89.54 seconds
Started Jun 29 06:40:40 PM PDT 24
Finished Jun 29 06:42:10 PM PDT 24
Peak memory 205016 kb
Host smart-2961ef27-4725-4738-b0fc-863117c6a085
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788726899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2788726899
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.390658445
Short name T374
Test name
Test status
Simulation time 6747067149 ps
CPU time 17.32 seconds
Started Jun 29 06:40:39 PM PDT 24
Finished Jun 29 06:40:57 PM PDT 24
Peak memory 204960 kb
Host smart-108a07ab-e78b-446e-9248-c5f7879754c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390658445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.390658445
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2174051695
Short name T306
Test name
Test status
Simulation time 203344356 ps
CPU time 1.26 seconds
Started Jun 29 06:40:41 PM PDT 24
Finished Jun 29 06:40:43 PM PDT 24
Peak memory 204704 kb
Host smart-ae2ef773-77b7-424c-9ed9-53a32d946cce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174051695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
174051695
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2211895961
Short name T418
Test name
Test status
Simulation time 566612830 ps
CPU time 6.43 seconds
Started Jun 29 06:40:47 PM PDT 24
Finished Jun 29 06:40:55 PM PDT 24
Peak memory 205140 kb
Host smart-66a2d9f9-abe7-4a36-8d8c-167bc034e9f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211895961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2211895961
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.545877630
Short name T311
Test name
Test status
Simulation time 657614364 ps
CPU time 4.08 seconds
Started Jun 29 06:40:38 PM PDT 24
Finished Jun 29 06:40:43 PM PDT 24
Peak memory 218704 kb
Host smart-2153effe-db08-4467-a3a9-ca98e114f93a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545877630 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.545877630
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.969738374
Short name T353
Test name
Test status
Simulation time 115901557 ps
CPU time 1.5 seconds
Started Jun 29 06:40:33 PM PDT 24
Finished Jun 29 06:40:35 PM PDT 24
Peak memory 213152 kb
Host smart-74010d81-977a-4bb5-b628-d85097e8a4f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969738374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.969738374
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3643086921
Short name T345
Test name
Test status
Simulation time 10734389439 ps
CPU time 22.69 seconds
Started Jun 29 06:40:46 PM PDT 24
Finished Jun 29 06:41:09 PM PDT 24
Peak memory 204988 kb
Host smart-686f32c8-5f1c-48fb-961f-2224f830c64c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643086921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.3643086921
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.736006149
Short name T355
Test name
Test status
Simulation time 5407803825 ps
CPU time 3.33 seconds
Started Jun 29 06:41:04 PM PDT 24
Finished Jun 29 06:41:07 PM PDT 24
Peak memory 204960 kb
Host smart-e4b1abbf-0cad-4290-8c32-8dbaa9529b27
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736006149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.736006149
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2851620280
Short name T438
Test name
Test status
Simulation time 532114625 ps
CPU time 1.06 seconds
Started Jun 29 06:40:47 PM PDT 24
Finished Jun 29 06:40:50 PM PDT 24
Peak memory 204660 kb
Host smart-03785d49-2cf7-4fb8-89b0-9a8a4b9462c4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851620280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
851620280
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.527838173
Short name T350
Test name
Test status
Simulation time 256845168 ps
CPU time 4.18 seconds
Started Jun 29 06:40:55 PM PDT 24
Finished Jun 29 06:41:00 PM PDT 24
Peak memory 205160 kb
Host smart-f0f49a77-a8e6-4f91-930c-47445491f038
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527838173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.527838173
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3050412947
Short name T75
Test name
Test status
Simulation time 66645476159 ps
CPU time 20.2 seconds
Started Jun 29 06:40:41 PM PDT 24
Finished Jun 29 06:41:01 PM PDT 24
Peak memory 221508 kb
Host smart-8aafc014-0508-449c-ab36-24c16d04e67c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050412947 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3050412947
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3219005891
Short name T237
Test name
Test status
Simulation time 50521222 ps
CPU time 2.39 seconds
Started Jun 29 06:40:50 PM PDT 24
Finished Jun 29 06:40:53 PM PDT 24
Peak memory 213300 kb
Host smart-0103f3bc-45d3-4498-aa8c-c1a943c0f93d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219005891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3219005891
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2896797294
Short name T182
Test name
Test status
Simulation time 7030759148 ps
CPU time 24.07 seconds
Started Jun 29 06:40:38 PM PDT 24
Finished Jun 29 06:41:02 PM PDT 24
Peak memory 213448 kb
Host smart-d8bc9c02-e195-4a63-9b1f-8e97564a2ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896797294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2896797294
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.721682645
Short name T368
Test name
Test status
Simulation time 356087619 ps
CPU time 2.64 seconds
Started Jun 29 06:40:46 PM PDT 24
Finished Jun 29 06:40:49 PM PDT 24
Peak memory 221584 kb
Host smart-e2cf1a2e-4453-4434-bc7f-f241974050c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721682645 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.721682645
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2977748888
Short name T132
Test name
Test status
Simulation time 244819847 ps
CPU time 1.7 seconds
Started Jun 29 06:41:00 PM PDT 24
Finished Jun 29 06:41:02 PM PDT 24
Peak memory 213236 kb
Host smart-a7f1ee4e-9e6d-493e-95c2-973e18c3d745
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977748888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2977748888
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2453258331
Short name T348
Test name
Test status
Simulation time 19638013881 ps
CPU time 54.79 seconds
Started Jun 29 06:40:44 PM PDT 24
Finished Jun 29 06:41:39 PM PDT 24
Peak memory 204972 kb
Host smart-fe5c057d-0db2-4835-a672-294cffb806c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453258331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2453258331
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2542443372
Short name T308
Test name
Test status
Simulation time 6108747295 ps
CPU time 7.73 seconds
Started Jun 29 06:40:39 PM PDT 24
Finished Jun 29 06:40:47 PM PDT 24
Peak memory 204936 kb
Host smart-c8baa0e9-0257-46a7-a25a-d508cdf2196a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542443372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
542443372
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1997554768
Short name T401
Test name
Test status
Simulation time 488596825 ps
CPU time 1.97 seconds
Started Jun 29 06:40:39 PM PDT 24
Finished Jun 29 06:40:41 PM PDT 24
Peak memory 204728 kb
Host smart-38d20345-0794-49b8-88ee-071694532f26
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997554768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
997554768
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2912054425
Short name T375
Test name
Test status
Simulation time 513963002 ps
CPU time 7.85 seconds
Started Jun 29 06:40:57 PM PDT 24
Finished Jun 29 06:41:06 PM PDT 24
Peak memory 205096 kb
Host smart-81e4e4f7-8005-401e-b16a-41725ea41b90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912054425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2912054425
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1933896176
Short name T179
Test name
Test status
Simulation time 1793502283 ps
CPU time 11.84 seconds
Started Jun 29 06:40:35 PM PDT 24
Finished Jun 29 06:40:47 PM PDT 24
Peak memory 213280 kb
Host smart-15ad0934-633f-40d6-9e46-e817fe4fe6b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933896176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1933896176
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3379299927
Short name T246
Test name
Test status
Simulation time 73914200 ps
CPU time 0.72 seconds
Started Jun 29 06:45:31 PM PDT 24
Finished Jun 29 06:45:32 PM PDT 24
Peak memory 204920 kb
Host smart-c4c22523-87f3-498e-ad22-ac282ba4d4a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379299927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3379299927
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3661428001
Short name T233
Test name
Test status
Simulation time 6398258034 ps
CPU time 2.78 seconds
Started Jun 29 06:45:07 PM PDT 24
Finished Jun 29 06:45:10 PM PDT 24
Peak memory 213504 kb
Host smart-43462b56-7385-4b88-9e83-e82f4b5cd8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661428001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3661428001
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.755848242
Short name T52
Test name
Test status
Simulation time 4097046960 ps
CPU time 3.57 seconds
Started Jun 29 06:45:04 PM PDT 24
Finished Jun 29 06:45:08 PM PDT 24
Peak memory 213552 kb
Host smart-57926066-915f-4cdf-aaf8-dbe46422802b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755848242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.755848242
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3851013995
Short name T17
Test name
Test status
Simulation time 975242079 ps
CPU time 3.07 seconds
Started Jun 29 06:45:15 PM PDT 24
Finished Jun 29 06:45:19 PM PDT 24
Peak memory 204936 kb
Host smart-cef5f51b-244d-4aa2-821f-6588bbcc56ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851013995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3851013995
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3386771310
Short name T292
Test name
Test status
Simulation time 364796300 ps
CPU time 1.14 seconds
Started Jun 29 06:45:14 PM PDT 24
Finished Jun 29 06:45:16 PM PDT 24
Peak memory 204920 kb
Host smart-438ee136-ada8-45be-b619-95203bb47df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386771310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3386771310
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3642934976
Short name T270
Test name
Test status
Simulation time 120953095 ps
CPU time 0.79 seconds
Started Jun 29 06:45:14 PM PDT 24
Finished Jun 29 06:45:16 PM PDT 24
Peak memory 204880 kb
Host smart-88976630-b8df-410c-a197-4a4763e716a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642934976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3642934976
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.2915196432
Short name T45
Test name
Test status
Simulation time 60643865 ps
CPU time 0.87 seconds
Started Jun 29 06:45:23 PM PDT 24
Finished Jun 29 06:45:24 PM PDT 24
Peak memory 215556 kb
Host smart-0d598296-c1d1-41c6-9406-13b9149f183b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915196432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2915196432
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1703684132
Short name T242
Test name
Test status
Simulation time 4470299360 ps
CPU time 9.89 seconds
Started Jun 29 06:45:05 PM PDT 24
Finished Jun 29 06:45:16 PM PDT 24
Peak memory 213532 kb
Host smart-e1c5eb41-3529-4e59-818d-c1f779e185e2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1703684132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1703684132
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3614910106
Short name T33
Test name
Test status
Simulation time 325600588 ps
CPU time 0.96 seconds
Started Jun 29 06:45:23 PM PDT 24
Finished Jun 29 06:45:25 PM PDT 24
Peak memory 204932 kb
Host smart-bc43d58b-60e4-46f5-b431-bf27aca59a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614910106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3614910106
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1624069641
Short name T49
Test name
Test status
Simulation time 286038487 ps
CPU time 0.94 seconds
Started Jun 29 06:45:13 PM PDT 24
Finished Jun 29 06:45:15 PM PDT 24
Peak memory 204924 kb
Host smart-b19de9ae-a1cb-47bd-ac0d-680c590b2465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624069641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1624069641
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2705902000
Short name T213
Test name
Test status
Simulation time 453266220 ps
CPU time 2.07 seconds
Started Jun 29 06:45:23 PM PDT 24
Finished Jun 29 06:45:26 PM PDT 24
Peak memory 204868 kb
Host smart-0a28df25-0dc0-4c90-b8ae-5bc96f6af489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705902000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2705902000
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2391479164
Short name T281
Test name
Test status
Simulation time 457192802 ps
CPU time 1.01 seconds
Started Jun 29 06:45:24 PM PDT 24
Finished Jun 29 06:45:25 PM PDT 24
Peak memory 204932 kb
Host smart-bb791468-74c8-481e-a915-d6e5f3176c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391479164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2391479164
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.593921721
Short name T278
Test name
Test status
Simulation time 980422614 ps
CPU time 2.92 seconds
Started Jun 29 06:45:22 PM PDT 24
Finished Jun 29 06:45:26 PM PDT 24
Peak memory 204924 kb
Host smart-eafafefe-ce88-4ce4-8368-7ea19ded202a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593921721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.593921721
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2693225699
Short name T47
Test name
Test status
Simulation time 315221582 ps
CPU time 0.78 seconds
Started Jun 29 06:45:22 PM PDT 24
Finished Jun 29 06:45:23 PM PDT 24
Peak memory 204912 kb
Host smart-6091e534-31e5-45e0-9751-5db7fa638cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693225699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2693225699
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.164447395
Short name T294
Test name
Test status
Simulation time 916266303 ps
CPU time 1.54 seconds
Started Jun 29 06:45:14 PM PDT 24
Finished Jun 29 06:45:16 PM PDT 24
Peak memory 204928 kb
Host smart-d6ae836b-5e2f-4cf2-a685-5f8e19bf865b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164447395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.164447395
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3333560190
Short name T100
Test name
Test status
Simulation time 1946387824 ps
CPU time 1.5 seconds
Started Jun 29 06:45:14 PM PDT 24
Finished Jun 29 06:45:16 PM PDT 24
Peak memory 205152 kb
Host smart-4703921c-950f-4523-b9dc-2775fb785a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333560190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3333560190
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2393135613
Short name T55
Test name
Test status
Simulation time 444121411 ps
CPU time 1.73 seconds
Started Jun 29 06:45:23 PM PDT 24
Finished Jun 29 06:45:25 PM PDT 24
Peak memory 204928 kb
Host smart-15b67181-4559-40fe-9092-204835009f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393135613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2393135613
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1415079430
Short name T269
Test name
Test status
Simulation time 1800736085 ps
CPU time 2.59 seconds
Started Jun 29 06:45:22 PM PDT 24
Finished Jun 29 06:45:25 PM PDT 24
Peak memory 204912 kb
Host smart-566b2943-b478-45ac-9728-31f288089d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415079430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1415079430
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3795468030
Short name T273
Test name
Test status
Simulation time 1906303781 ps
CPU time 5.83 seconds
Started Jun 29 06:45:04 PM PDT 24
Finished Jun 29 06:45:10 PM PDT 24
Peak memory 205228 kb
Host smart-7f4c8722-7c64-4f8a-9d89-f085b425062c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795468030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3795468030
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2787466054
Short name T72
Test name
Test status
Simulation time 340332265 ps
CPU time 1.37 seconds
Started Jun 29 06:45:22 PM PDT 24
Finished Jun 29 06:45:23 PM PDT 24
Peak memory 236436 kb
Host smart-7ce59ea3-df6c-4b13-906f-b94f5f0834eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787466054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2787466054
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2855252945
Short name T271
Test name
Test status
Simulation time 4140692293 ps
CPU time 9.99 seconds
Started Jun 29 06:45:05 PM PDT 24
Finished Jun 29 06:45:15 PM PDT 24
Peak memory 204936 kb
Host smart-de61daa1-083f-4d5c-80ee-56d78832c690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855252945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2855252945
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.328795963
Short name T18
Test name
Test status
Simulation time 5022101320 ps
CPU time 4.53 seconds
Started Jun 29 06:45:23 PM PDT 24
Finished Jun 29 06:45:28 PM PDT 24
Peak memory 205120 kb
Host smart-95561e8b-a830-43bd-bdd2-cc159f1f1438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328795963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.328795963
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3535809726
Short name T38
Test name
Test status
Simulation time 8559158310 ps
CPU time 11.16 seconds
Started Jun 29 06:45:05 PM PDT 24
Finished Jun 29 06:45:17 PM PDT 24
Peak memory 205208 kb
Host smart-e273d7bb-13c1-43fd-ab80-52dd2a217b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535809726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3535809726
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1989125692
Short name T69
Test name
Test status
Simulation time 200061656 ps
CPU time 0.92 seconds
Started Jun 29 06:45:44 PM PDT 24
Finished Jun 29 06:45:45 PM PDT 24
Peak memory 204924 kb
Host smart-4586693a-7910-4e04-b1c9-f2c1d3a5ed2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989125692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1989125692
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.466545230
Short name T215
Test name
Test status
Simulation time 197642318 ps
CPU time 0.99 seconds
Started Jun 29 06:45:47 PM PDT 24
Finished Jun 29 06:45:48 PM PDT 24
Peak memory 204848 kb
Host smart-f1bfbfd5-ff9b-4b7c-a0bc-a129ad663324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466545230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.466545230
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1052430810
Short name T214
Test name
Test status
Simulation time 13127243611 ps
CPU time 4.28 seconds
Started Jun 29 06:45:31 PM PDT 24
Finished Jun 29 06:45:36 PM PDT 24
Peak memory 213540 kb
Host smart-52e583c3-8836-41fa-934c-fac5305cd88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052430810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1052430810
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.3764754186
Short name T42
Test name
Test status
Simulation time 2545677943 ps
CPU time 3.19 seconds
Started Jun 29 06:45:33 PM PDT 24
Finished Jun 29 06:45:37 PM PDT 24
Peak memory 213480 kb
Host smart-57b95104-d04c-4c22-a58a-e980d34869f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764754186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3764754186
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.549454056
Short name T191
Test name
Test status
Simulation time 684830512 ps
CPU time 2.38 seconds
Started Jun 29 06:45:32 PM PDT 24
Finished Jun 29 06:45:34 PM PDT 24
Peak memory 204908 kb
Host smart-1b19a8d9-8381-42c2-aa62-fc415dabd087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549454056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.549454056
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1528754364
Short name T20
Test name
Test status
Simulation time 463373292 ps
CPU time 1.97 seconds
Started Jun 29 06:45:37 PM PDT 24
Finished Jun 29 06:45:39 PM PDT 24
Peak memory 204916 kb
Host smart-ffe3633d-e053-4685-8a23-c78d33867473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528754364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1528754364
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1025298091
Short name T61
Test name
Test status
Simulation time 536215538 ps
CPU time 1.97 seconds
Started Jun 29 06:45:40 PM PDT 24
Finished Jun 29 06:45:43 PM PDT 24
Peak memory 204920 kb
Host smart-1f3d9e6f-05eb-4a49-9c2a-6fc470a6eb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025298091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1025298091
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1236493473
Short name T201
Test name
Test status
Simulation time 106373824 ps
CPU time 0.94 seconds
Started Jun 29 06:45:32 PM PDT 24
Finished Jun 29 06:45:33 PM PDT 24
Peak memory 204876 kb
Host smart-754f53ca-b6b8-4b39-bb18-d33cd6f9bcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236493473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1236493473
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.747727205
Short name T197
Test name
Test status
Simulation time 278132484 ps
CPU time 1.15 seconds
Started Jun 29 06:45:40 PM PDT 24
Finished Jun 29 06:45:41 PM PDT 24
Peak memory 204924 kb
Host smart-95c83c44-1b01-4848-8283-f410e8d6b046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747727205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.747727205
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3746336762
Short name T260
Test name
Test status
Simulation time 1217202044 ps
CPU time 3.37 seconds
Started Jun 29 06:45:30 PM PDT 24
Finished Jun 29 06:45:34 PM PDT 24
Peak memory 213416 kb
Host smart-cbb79cd2-8406-4f40-8f69-02de06eb5d56
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3746336762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3746336762
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2239357523
Short name T227
Test name
Test status
Simulation time 1639316384 ps
CPU time 4.61 seconds
Started Jun 29 06:45:41 PM PDT 24
Finished Jun 29 06:45:46 PM PDT 24
Peak memory 204868 kb
Host smart-e37b69c1-db24-47a4-b850-96953fe3fcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239357523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2239357523
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3532006129
Short name T155
Test name
Test status
Simulation time 254691899 ps
CPU time 0.81 seconds
Started Jun 29 06:45:37 PM PDT 24
Finished Jun 29 06:45:38 PM PDT 24
Peak memory 204928 kb
Host smart-d5209f55-c29e-416f-9a62-34d61d2e9fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532006129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3532006129
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3341400181
Short name T50
Test name
Test status
Simulation time 833147273 ps
CPU time 2.14 seconds
Started Jun 29 06:45:45 PM PDT 24
Finished Jun 29 06:45:47 PM PDT 24
Peak memory 204924 kb
Host smart-9bdafbcd-a97e-40e3-b4a4-8380a827668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341400181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3341400181
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.532736008
Short name T289
Test name
Test status
Simulation time 338112658 ps
CPU time 1.07 seconds
Started Jun 29 06:45:47 PM PDT 24
Finished Jun 29 06:45:49 PM PDT 24
Peak memory 204924 kb
Host smart-f1c8edb5-599b-4d92-bf6c-c116687715dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532736008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.532736008
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3661200340
Short name T158
Test name
Test status
Simulation time 2209799980 ps
CPU time 1.13 seconds
Started Jun 29 06:45:46 PM PDT 24
Finished Jun 29 06:45:47 PM PDT 24
Peak memory 204940 kb
Host smart-4311619e-1c62-4e16-baca-8ba19e8db1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661200340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3661200340
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3280418374
Short name T53
Test name
Test status
Simulation time 151291380 ps
CPU time 0.81 seconds
Started Jun 29 06:45:48 PM PDT 24
Finished Jun 29 06:45:49 PM PDT 24
Peak memory 204848 kb
Host smart-101c2efd-978f-4cbd-b038-fcd7ac1235ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280418374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3280418374
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2213255924
Short name T195
Test name
Test status
Simulation time 241708257 ps
CPU time 1.28 seconds
Started Jun 29 06:45:39 PM PDT 24
Finished Jun 29 06:45:40 PM PDT 24
Peak memory 204916 kb
Host smart-867eae5e-2322-4c30-accf-bff1bde10a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213255924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2213255924
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3142342055
Short name T266
Test name
Test status
Simulation time 269335267 ps
CPU time 0.75 seconds
Started Jun 29 06:45:38 PM PDT 24
Finished Jun 29 06:45:39 PM PDT 24
Peak memory 204896 kb
Host smart-60405b5c-2747-4aa3-892c-8352f933aa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142342055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3142342055
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.1331963264
Short name T193
Test name
Test status
Simulation time 142582897 ps
CPU time 0.9 seconds
Started Jun 29 06:45:39 PM PDT 24
Finished Jun 29 06:45:40 PM PDT 24
Peak memory 204932 kb
Host smart-225ae600-2178-4d31-aaa3-919d15fca97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331963264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1331963264
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1319567841
Short name T22
Test name
Test status
Simulation time 722296189 ps
CPU time 1.26 seconds
Started Jun 29 06:45:44 PM PDT 24
Finished Jun 29 06:45:46 PM PDT 24
Peak memory 204932 kb
Host smart-194eb0ff-869e-4212-a4ae-3ff3caca242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319567841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1319567841
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.708296882
Short name T68
Test name
Test status
Simulation time 520347711 ps
CPU time 1.92 seconds
Started Jun 29 06:45:46 PM PDT 24
Finished Jun 29 06:45:48 PM PDT 24
Peak memory 204852 kb
Host smart-4e031a99-d86a-4571-83e5-d0ca2f278b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708296882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.708296882
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1598954607
Short name T64
Test name
Test status
Simulation time 70239329 ps
CPU time 0.9 seconds
Started Jun 29 06:45:43 PM PDT 24
Finished Jun 29 06:45:44 PM PDT 24
Peak memory 213208 kb
Host smart-e2517c44-02a0-41c2-ac3a-4971711b6ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598954607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1598954607
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.1407612060
Short name T8
Test name
Test status
Simulation time 633677118 ps
CPU time 0.87 seconds
Started Jun 29 06:45:38 PM PDT 24
Finished Jun 29 06:45:39 PM PDT 24
Peak memory 204912 kb
Host smart-aeeee38d-3550-4988-bb12-382d498b1372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407612060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.1407612060
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1453714193
Short name T272
Test name
Test status
Simulation time 2769113882 ps
CPU time 2.73 seconds
Started Jun 29 06:45:30 PM PDT 24
Finished Jun 29 06:45:33 PM PDT 24
Peak memory 205328 kb
Host smart-097ee079-e543-4215-9eee-db4c5402754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453714193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1453714193
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1978208665
Short name T92
Test name
Test status
Simulation time 655612139 ps
CPU time 1.42 seconds
Started Jun 29 06:45:46 PM PDT 24
Finished Jun 29 06:45:47 PM PDT 24
Peak memory 237196 kb
Host smart-4c769087-7b16-427b-9b6e-9afb0a255ebd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978208665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1978208665
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.987588065
Short name T258
Test name
Test status
Simulation time 806862472 ps
CPU time 3.04 seconds
Started Jun 29 06:45:31 PM PDT 24
Finished Jun 29 06:45:34 PM PDT 24
Peak memory 204924 kb
Host smart-faacd28d-e568-4b7d-955d-70d4df600113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987588065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.987588065
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.267440608
Short name T97
Test name
Test status
Simulation time 3702334502 ps
CPU time 3.99 seconds
Started Jun 29 06:45:44 PM PDT 24
Finished Jun 29 06:45:48 PM PDT 24
Peak memory 213724 kb
Host smart-5ba906dc-4e1e-41f7-b432-4ae0f5d956c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267440608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.267440608
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.915917835
Short name T44
Test name
Test status
Simulation time 57671027 ps
CPU time 0.72 seconds
Started Jun 29 06:46:15 PM PDT 24
Finished Jun 29 06:46:17 PM PDT 24
Peak memory 204916 kb
Host smart-d66b82db-c387-408c-aea6-76d09a3c7923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915917835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.915917835
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3636956767
Short name T264
Test name
Test status
Simulation time 9645534236 ps
CPU time 9.5 seconds
Started Jun 29 06:46:17 PM PDT 24
Finished Jun 29 06:46:27 PM PDT 24
Peak memory 213476 kb
Host smart-03d934dd-d13c-497c-bc3f-96b3efc2e733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636956767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3636956767
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2997871791
Short name T226
Test name
Test status
Simulation time 1512818489 ps
CPU time 4.68 seconds
Started Jun 29 06:46:15 PM PDT 24
Finished Jun 29 06:46:20 PM PDT 24
Peak memory 213504 kb
Host smart-04d23991-2590-43ee-bd57-87e778a00c9d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2997871791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2997871791
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1301062332
Short name T293
Test name
Test status
Simulation time 1304333864 ps
CPU time 3.88 seconds
Started Jun 29 06:46:07 PM PDT 24
Finished Jun 29 06:46:12 PM PDT 24
Peak memory 205200 kb
Host smart-0b231a1f-11f2-44e9-883a-2cfbdd27b072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301062332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1301062332
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1770587793
Short name T243
Test name
Test status
Simulation time 43864302 ps
CPU time 0.8 seconds
Started Jun 29 06:46:18 PM PDT 24
Finished Jun 29 06:46:19 PM PDT 24
Peak memory 204968 kb
Host smart-af77014a-8db6-476f-9200-8446b48087ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770587793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1770587793
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2731312910
Short name T223
Test name
Test status
Simulation time 11837297176 ps
CPU time 5.28 seconds
Started Jun 29 06:46:15 PM PDT 24
Finished Jun 29 06:46:21 PM PDT 24
Peak memory 213472 kb
Host smart-6d59edfb-dd0f-4483-b510-3066a8de43d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731312910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2731312910
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1761193506
Short name T277
Test name
Test status
Simulation time 6105350922 ps
CPU time 17.03 seconds
Started Jun 29 06:46:18 PM PDT 24
Finished Jun 29 06:46:35 PM PDT 24
Peak memory 205308 kb
Host smart-32978e4a-a3a3-49a0-a216-45e24f8d7640
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761193506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1761193506
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.2030891013
Short name T12
Test name
Test status
Simulation time 2700824039 ps
CPU time 4.7 seconds
Started Jun 29 06:46:14 PM PDT 24
Finished Jun 29 06:46:19 PM PDT 24
Peak memory 213392 kb
Host smart-a1a33260-ff51-4212-bdfa-f108c60e58be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030891013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2030891013
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1369806781
Short name T98
Test name
Test status
Simulation time 54850794 ps
CPU time 0.7 seconds
Started Jun 29 06:46:14 PM PDT 24
Finished Jun 29 06:46:15 PM PDT 24
Peak memory 204912 kb
Host smart-317fd182-2bc6-48dd-8908-44c07c14fc21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369806781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1369806781
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.1319689137
Short name T204
Test name
Test status
Simulation time 4239971188 ps
CPU time 4.58 seconds
Started Jun 29 06:46:13 PM PDT 24
Finished Jun 29 06:46:18 PM PDT 24
Peak memory 213524 kb
Host smart-eadc659d-f53b-4afb-a6ea-915e884037a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319689137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.1319689137
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.48442048
Short name T99
Test name
Test status
Simulation time 5411721418 ps
CPU time 13.35 seconds
Started Jun 29 06:46:16 PM PDT 24
Finished Jun 29 06:46:30 PM PDT 24
Peak memory 213544 kb
Host smart-c9e0415c-32e0-4a35-b701-ce469af7e5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48442048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.48442048
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.1032001079
Short name T85
Test name
Test status
Simulation time 6555843024 ps
CPU time 6.24 seconds
Started Jun 29 06:46:15 PM PDT 24
Finished Jun 29 06:46:22 PM PDT 24
Peak memory 205312 kb
Host smart-ed74e156-83b7-4eeb-93a4-1c620d90917a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032001079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1032001079
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2751370097
Short name T286
Test name
Test status
Simulation time 205066681 ps
CPU time 0.71 seconds
Started Jun 29 06:46:22 PM PDT 24
Finished Jun 29 06:46:23 PM PDT 24
Peak memory 204920 kb
Host smart-33dde803-614f-4471-9379-1d258b43bbca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751370097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2751370097
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2299723786
Short name T174
Test name
Test status
Simulation time 5345134137 ps
CPU time 7.5 seconds
Started Jun 29 06:46:16 PM PDT 24
Finished Jun 29 06:46:24 PM PDT 24
Peak memory 213532 kb
Host smart-0e7c030d-cf9a-4f09-afd5-7f2c7d874d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299723786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2299723786
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.738577455
Short name T159
Test name
Test status
Simulation time 2345828796 ps
CPU time 6.95 seconds
Started Jun 29 06:46:17 PM PDT 24
Finished Jun 29 06:46:25 PM PDT 24
Peak memory 205252 kb
Host smart-cd84e548-40e9-47db-a503-008eac03cb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738577455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.738577455
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.195477073
Short name T10
Test name
Test status
Simulation time 13738688930 ps
CPU time 5.17 seconds
Started Jun 29 06:46:17 PM PDT 24
Finished Jun 29 06:46:22 PM PDT 24
Peak memory 213500 kb
Host smart-d8818caf-b4a0-45d2-93a4-a061552928c8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195477073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.195477073
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.74559144
Short name T291
Test name
Test status
Simulation time 2997740585 ps
CPU time 8.02 seconds
Started Jun 29 06:46:17 PM PDT 24
Finished Jun 29 06:46:25 PM PDT 24
Peak memory 205328 kb
Host smart-fb357c8f-577a-45d3-9ba4-b1b082309d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74559144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.74559144
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.2530868879
Short name T157
Test name
Test status
Simulation time 7935781944 ps
CPU time 6.57 seconds
Started Jun 29 06:46:25 PM PDT 24
Finished Jun 29 06:46:32 PM PDT 24
Peak memory 213304 kb
Host smart-93e1e184-41ed-4a92-9f13-d4807b095237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530868879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2530868879
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2084197653
Short name T254
Test name
Test status
Simulation time 117200958 ps
CPU time 0.78 seconds
Started Jun 29 06:46:23 PM PDT 24
Finished Jun 29 06:46:25 PM PDT 24
Peak memory 204932 kb
Host smart-2fd9b5de-2310-4d2a-a996-14afcfe6bd90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084197653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2084197653
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1975496920
Short name T284
Test name
Test status
Simulation time 10000713748 ps
CPU time 24.24 seconds
Started Jun 29 06:46:23 PM PDT 24
Finished Jun 29 06:46:48 PM PDT 24
Peak memory 213608 kb
Host smart-9e013e02-a384-4881-bfac-b0f86d40e39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975496920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1975496920
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1405905309
Short name T283
Test name
Test status
Simulation time 2922632737 ps
CPU time 3.05 seconds
Started Jun 29 06:46:25 PM PDT 24
Finished Jun 29 06:46:28 PM PDT 24
Peak memory 213556 kb
Host smart-2f20955c-db47-484a-97b0-a699b8298c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405905309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1405905309
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.17309511
Short name T57
Test name
Test status
Simulation time 10360778103 ps
CPU time 15.71 seconds
Started Jun 29 06:46:27 PM PDT 24
Finished Jun 29 06:46:43 PM PDT 24
Peak memory 213416 kb
Host smart-b2b3a795-5758-43df-8990-1b77478ac449
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17309511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_tl
_access.17309511
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3743815344
Short name T173
Test name
Test status
Simulation time 1601121007 ps
CPU time 4.55 seconds
Started Jun 29 06:46:23 PM PDT 24
Finished Jun 29 06:46:28 PM PDT 24
Peak memory 205200 kb
Host smart-918e6f15-b7bf-41dd-afc5-fdae8bcbfa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743815344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3743815344
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.1566852172
Short name T5
Test name
Test status
Simulation time 7986375162 ps
CPU time 8.4 seconds
Started Jun 29 06:46:23 PM PDT 24
Finished Jun 29 06:46:32 PM PDT 24
Peak memory 205212 kb
Host smart-97603f79-c2b1-419f-9b2c-b70191c4ca51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566852172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1566852172
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3708379439
Short name T41
Test name
Test status
Simulation time 62374372 ps
CPU time 0.77 seconds
Started Jun 29 06:46:22 PM PDT 24
Finished Jun 29 06:46:23 PM PDT 24
Peak memory 204916 kb
Host smart-aa339f61-c338-463f-8ba7-87a9148c9e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708379439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3708379439
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1260845077
Short name T276
Test name
Test status
Simulation time 2704443502 ps
CPU time 3.41 seconds
Started Jun 29 06:46:25 PM PDT 24
Finished Jun 29 06:46:28 PM PDT 24
Peak memory 213556 kb
Host smart-5aa94577-702d-4c79-b29d-68b429c0c062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260845077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1260845077
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2459230973
Short name T279
Test name
Test status
Simulation time 784502087 ps
CPU time 2.73 seconds
Started Jun 29 06:46:27 PM PDT 24
Finished Jun 29 06:46:30 PM PDT 24
Peak memory 205232 kb
Host smart-a21e5665-9c4b-443d-9717-e0a0e3201632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459230973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2459230973
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2355299729
Short name T84
Test name
Test status
Simulation time 2708107975 ps
CPU time 7.48 seconds
Started Jun 29 06:46:27 PM PDT 24
Finished Jun 29 06:46:35 PM PDT 24
Peak memory 205308 kb
Host smart-1c835d67-f82b-4840-ab86-4e97446c36fb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355299729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2355299729
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.226844880
Short name T256
Test name
Test status
Simulation time 2890475240 ps
CPU time 3.27 seconds
Started Jun 29 06:46:24 PM PDT 24
Finished Jun 29 06:46:28 PM PDT 24
Peak memory 205328 kb
Host smart-07abe034-9b32-4bf7-8d6c-d0b77b14881b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226844880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.226844880
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1953479459
Short name T156
Test name
Test status
Simulation time 6614697727 ps
CPU time 16.31 seconds
Started Jun 29 06:46:24 PM PDT 24
Finished Jun 29 06:46:41 PM PDT 24
Peak memory 213356 kb
Host smart-e8235c64-17a1-4a95-ad6a-9c26fdf26535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953479459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1953479459
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2063784680
Short name T152
Test name
Test status
Simulation time 66648913 ps
CPU time 0.87 seconds
Started Jun 29 06:46:24 PM PDT 24
Finished Jun 29 06:46:25 PM PDT 24
Peak memory 204852 kb
Host smart-93494a81-99a8-467f-b7cc-c14c45ae816c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063784680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2063784680
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2419937571
Short name T235
Test name
Test status
Simulation time 1280587863 ps
CPU time 1.63 seconds
Started Jun 29 06:46:27 PM PDT 24
Finished Jun 29 06:46:29 PM PDT 24
Peak memory 205228 kb
Host smart-49778826-3595-4ee5-adf8-d8c73e4d2384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419937571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2419937571
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.503406067
Short name T56
Test name
Test status
Simulation time 3817686092 ps
CPU time 2.43 seconds
Started Jun 29 06:46:25 PM PDT 24
Finished Jun 29 06:46:27 PM PDT 24
Peak memory 213480 kb
Host smart-cb8e361c-ecd5-4eec-818e-fc7c3f1ddab4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=503406067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.503406067
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2950335963
Short name T209
Test name
Test status
Simulation time 5929501735 ps
CPU time 8.79 seconds
Started Jun 29 06:46:24 PM PDT 24
Finished Jun 29 06:46:33 PM PDT 24
Peak memory 213480 kb
Host smart-488b70cc-cc65-408d-a802-13c5e4472cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950335963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2950335963
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3226305438
Short name T70
Test name
Test status
Simulation time 87197960 ps
CPU time 0.87 seconds
Started Jun 29 06:46:30 PM PDT 24
Finished Jun 29 06:46:31 PM PDT 24
Peak memory 204968 kb
Host smart-905813f2-8c87-4115-ac83-4eee268b4727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226305438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3226305438
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3042876911
Short name T107
Test name
Test status
Simulation time 9428925059 ps
CPU time 11.92 seconds
Started Jun 29 06:46:24 PM PDT 24
Finished Jun 29 06:46:36 PM PDT 24
Peak memory 213500 kb
Host smart-de0c09c0-fc34-4749-b0a1-9497437be1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042876911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3042876911
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1569746210
Short name T58
Test name
Test status
Simulation time 3670575887 ps
CPU time 1.88 seconds
Started Jun 29 06:46:27 PM PDT 24
Finished Jun 29 06:46:29 PM PDT 24
Peak memory 213476 kb
Host smart-b216df8c-dc54-4466-92a2-e0a56c7230fb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1569746210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1569746210
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.501579500
Short name T282
Test name
Test status
Simulation time 5391289607 ps
CPU time 9.81 seconds
Started Jun 29 06:46:22 PM PDT 24
Finished Jun 29 06:46:32 PM PDT 24
Peak memory 205344 kb
Host smart-241c8df3-cf06-432b-931f-e6a4ac1b4dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501579500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.501579500
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.2208934287
Short name T24
Test name
Test status
Simulation time 11341752460 ps
CPU time 21.2 seconds
Started Jun 29 06:46:29 PM PDT 24
Finished Jun 29 06:46:51 PM PDT 24
Peak memory 205160 kb
Host smart-4dffce60-76bc-44d8-8b39-e060a278d9ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208934287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2208934287
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3037348951
Short name T218
Test name
Test status
Simulation time 103265410 ps
CPU time 0.78 seconds
Started Jun 29 06:46:32 PM PDT 24
Finished Jun 29 06:46:33 PM PDT 24
Peak memory 204920 kb
Host smart-65cf3929-f182-4cc5-8bb7-eea0ad645c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037348951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3037348951
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3183734478
Short name T32
Test name
Test status
Simulation time 1699557026 ps
CPU time 5.16 seconds
Started Jun 29 06:46:33 PM PDT 24
Finished Jun 29 06:46:38 PM PDT 24
Peak memory 213472 kb
Host smart-585a6e33-ccd8-42e2-9282-3e8f30272cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183734478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3183734478
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2222126767
Short name T288
Test name
Test status
Simulation time 2315368224 ps
CPU time 4.87 seconds
Started Jun 29 06:46:33 PM PDT 24
Finished Jun 29 06:46:39 PM PDT 24
Peak memory 213532 kb
Host smart-95ff7981-eb13-4466-95fd-329c2d0c63bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222126767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2222126767
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.4250431394
Short name T43
Test name
Test status
Simulation time 10583166564 ps
CPU time 16.91 seconds
Started Jun 29 06:46:31 PM PDT 24
Finished Jun 29 06:46:48 PM PDT 24
Peak memory 213504 kb
Host smart-dad6fee0-58a3-452c-8865-015090b2eaff
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4250431394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.4250431394
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1253926391
Short name T253
Test name
Test status
Simulation time 3212655748 ps
CPU time 3.94 seconds
Started Jun 29 06:46:33 PM PDT 24
Finished Jun 29 06:46:37 PM PDT 24
Peak memory 214452 kb
Host smart-ca8ea6fb-05d3-4f09-8f4e-3271b9de46ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253926391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1253926391
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3601582135
Short name T78
Test name
Test status
Simulation time 38410703 ps
CPU time 0.77 seconds
Started Jun 29 06:46:32 PM PDT 24
Finished Jun 29 06:46:33 PM PDT 24
Peak memory 204852 kb
Host smart-68534de4-3760-4e8b-9a20-be0e9a31426e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601582135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3601582135
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.161641906
Short name T250
Test name
Test status
Simulation time 8619570662 ps
CPU time 24.88 seconds
Started Jun 29 06:46:30 PM PDT 24
Finished Jun 29 06:46:55 PM PDT 24
Peak memory 213580 kb
Host smart-27c73a9d-e4d3-4451-adbf-2c0931f3901f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161641906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.161641906
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3431327692
Short name T164
Test name
Test status
Simulation time 1724970154 ps
CPU time 1.49 seconds
Started Jun 29 06:46:31 PM PDT 24
Finished Jun 29 06:46:33 PM PDT 24
Peak memory 213444 kb
Host smart-2adba0c7-1ca3-48ae-b90a-79dff35c32bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431327692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3431327692
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1968836132
Short name T221
Test name
Test status
Simulation time 890924140 ps
CPU time 2.41 seconds
Started Jun 29 06:46:31 PM PDT 24
Finished Jun 29 06:46:34 PM PDT 24
Peak memory 213488 kb
Host smart-f4353183-436c-4dec-9eae-fab9d8ff2313
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1968836132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1968836132
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2685649600
Short name T1
Test name
Test status
Simulation time 2923299633 ps
CPU time 9.28 seconds
Started Jun 29 06:46:31 PM PDT 24
Finished Jun 29 06:46:40 PM PDT 24
Peak memory 205372 kb
Host smart-a6867505-492e-4b44-b2da-080f39ecd617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685649600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2685649600
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.546017929
Short name T205
Test name
Test status
Simulation time 9447375960 ps
CPU time 8.35 seconds
Started Jun 29 06:46:31 PM PDT 24
Finished Jun 29 06:46:40 PM PDT 24
Peak memory 205232 kb
Host smart-c869cc79-01bb-4e39-8933-6f9a6648ad1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546017929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.546017929
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3879465059
Short name T285
Test name
Test status
Simulation time 38037997 ps
CPU time 0.79 seconds
Started Jun 29 06:45:54 PM PDT 24
Finished Jun 29 06:45:55 PM PDT 24
Peak memory 204924 kb
Host smart-18d1e2d9-975b-4b03-a78a-938a8c026f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879465059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3879465059
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1963000240
Short name T207
Test name
Test status
Simulation time 18512379565 ps
CPU time 48.14 seconds
Started Jun 29 06:45:55 PM PDT 24
Finished Jun 29 06:46:43 PM PDT 24
Peak memory 216736 kb
Host smart-2e345615-62cb-40b9-9cf1-eb9530e59753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963000240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1963000240
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.214617562
Short name T255
Test name
Test status
Simulation time 2413595859 ps
CPU time 7.19 seconds
Started Jun 29 06:45:46 PM PDT 24
Finished Jun 29 06:45:54 PM PDT 24
Peak memory 205288 kb
Host smart-0c3352eb-45db-4ea4-9c60-fa8f00f46fbc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=214617562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.214617562
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.203780377
Short name T167
Test name
Test status
Simulation time 792104272 ps
CPU time 1.05 seconds
Started Jun 29 06:45:52 PM PDT 24
Finished Jun 29 06:45:53 PM PDT 24
Peak memory 204940 kb
Host smart-2506be4f-b91b-4b8d-a12f-eaa7f1e1b2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203780377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.203780377
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1102627400
Short name T257
Test name
Test status
Simulation time 6419263620 ps
CPU time 8.62 seconds
Started Jun 29 06:45:44 PM PDT 24
Finished Jun 29 06:45:53 PM PDT 24
Peak memory 213480 kb
Host smart-e9266889-5791-4034-b2e2-6486e8659729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102627400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1102627400
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.725319220
Short name T74
Test name
Test status
Simulation time 467527952 ps
CPU time 2.4 seconds
Started Jun 29 06:45:54 PM PDT 24
Finished Jun 29 06:45:56 PM PDT 24
Peak memory 237284 kb
Host smart-b22e9a65-72ec-4be4-aed4-50f1bfbc8cd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725319220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.725319220
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.2747727429
Short name T194
Test name
Test status
Simulation time 5018807495 ps
CPU time 4.46 seconds
Started Jun 29 06:45:52 PM PDT 24
Finished Jun 29 06:45:57 PM PDT 24
Peak memory 205136 kb
Host smart-baf3ced9-c83b-4881-bb77-deb6ebbd83e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747727429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2747727429
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1840409770
Short name T211
Test name
Test status
Simulation time 127813308 ps
CPU time 1 seconds
Started Jun 29 06:46:32 PM PDT 24
Finished Jun 29 06:46:33 PM PDT 24
Peak memory 204900 kb
Host smart-429d03c3-be18-4e2e-9868-617e7a35fc33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840409770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1840409770
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.482791134
Short name T188
Test name
Test status
Simulation time 16952151396 ps
CPU time 40.8 seconds
Started Jun 29 06:46:32 PM PDT 24
Finished Jun 29 06:47:13 PM PDT 24
Peak memory 205124 kb
Host smart-55d05ad0-2d2f-409e-90a8-6743077539a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482791134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.482791134
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3115509069
Short name T153
Test name
Test status
Simulation time 62874596 ps
CPU time 0.69 seconds
Started Jun 29 06:46:37 PM PDT 24
Finished Jun 29 06:46:38 PM PDT 24
Peak memory 204900 kb
Host smart-987dabe2-697e-47cf-9fbc-49c95dbca904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115509069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3115509069
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.951138334
Short name T13
Test name
Test status
Simulation time 2983097917 ps
CPU time 3.61 seconds
Started Jun 29 06:46:41 PM PDT 24
Finished Jun 29 06:46:45 PM PDT 24
Peak memory 213340 kb
Host smart-a47679d8-27aa-4909-8ca4-8b743644f1d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951138334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.951138334
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.593275952
Short name T54
Test name
Test status
Simulation time 68710751 ps
CPU time 0.84 seconds
Started Jun 29 06:46:45 PM PDT 24
Finished Jun 29 06:46:47 PM PDT 24
Peak memory 204808 kb
Host smart-98746be8-b289-4ce3-b9ba-36aeb608ec0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593275952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.593275952
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.4176597098
Short name T71
Test name
Test status
Simulation time 122297636 ps
CPU time 0.93 seconds
Started Jun 29 06:46:39 PM PDT 24
Finished Jun 29 06:46:40 PM PDT 24
Peak memory 204920 kb
Host smart-d84a9658-6108-4ad7-8e1e-efa04d9b581b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176597098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.4176597098
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.423770565
Short name T14
Test name
Test status
Simulation time 7026763886 ps
CPU time 5.79 seconds
Started Jun 29 06:46:38 PM PDT 24
Finished Jun 29 06:46:44 PM PDT 24
Peak memory 205152 kb
Host smart-dbf95256-5fb1-4a6a-ad15-a7438d8d8b15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423770565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.423770565
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.917527182
Short name T203
Test name
Test status
Simulation time 28573077 ps
CPU time 0.78 seconds
Started Jun 29 06:46:39 PM PDT 24
Finished Jun 29 06:46:40 PM PDT 24
Peak memory 204928 kb
Host smart-f7a0d3bf-24f0-4b43-b6c5-bc7a2f056de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917527182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.917527182
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1918234455
Short name T247
Test name
Test status
Simulation time 66317096 ps
CPU time 0.71 seconds
Started Jun 29 06:46:40 PM PDT 24
Finished Jun 29 06:46:41 PM PDT 24
Peak memory 204960 kb
Host smart-6bbb6dd1-3b64-4e5d-80cd-c0d444c1359d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918234455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1918234455
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2247113
Short name T37
Test name
Test status
Simulation time 8329650888 ps
CPU time 22.26 seconds
Started Jun 29 06:46:38 PM PDT 24
Finished Jun 29 06:47:01 PM PDT 24
Peak memory 213328 kb
Host smart-7b32e877-c307-453d-85c9-ac973a5abcd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2247113
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3823867410
Short name T89
Test name
Test status
Simulation time 122943525 ps
CPU time 1.04 seconds
Started Jun 29 06:46:42 PM PDT 24
Finished Jun 29 06:46:43 PM PDT 24
Peak memory 204928 kb
Host smart-ce530dd8-4800-4bed-8605-b9f3e36f9d22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823867410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3823867410
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.1669813138
Short name T161
Test name
Test status
Simulation time 4007420753 ps
CPU time 5.28 seconds
Started Jun 29 06:46:41 PM PDT 24
Finished Jun 29 06:46:47 PM PDT 24
Peak memory 205096 kb
Host smart-4759bed1-ae22-407b-b259-4af6e92e9207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669813138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1669813138
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1605153381
Short name T90
Test name
Test status
Simulation time 124466017 ps
CPU time 0.85 seconds
Started Jun 29 06:46:40 PM PDT 24
Finished Jun 29 06:46:41 PM PDT 24
Peak memory 204952 kb
Host smart-c98e1781-db54-471e-b644-7e60a110caa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605153381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1605153381
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.2691547090
Short name T172
Test name
Test status
Simulation time 5493307562 ps
CPU time 16.5 seconds
Started Jun 29 06:46:40 PM PDT 24
Finished Jun 29 06:46:57 PM PDT 24
Peak memory 213412 kb
Host smart-9d44717b-a70b-4b8d-bcb6-2b13444c45b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691547090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2691547090
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2120359244
Short name T200
Test name
Test status
Simulation time 45207876 ps
CPU time 0.75 seconds
Started Jun 29 06:46:40 PM PDT 24
Finished Jun 29 06:46:41 PM PDT 24
Peak memory 204920 kb
Host smart-9e7e3cde-14c8-40da-bd1e-fa76c28ad95a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120359244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2120359244
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.2048206047
Short name T48
Test name
Test status
Simulation time 2760836778 ps
CPU time 4.62 seconds
Started Jun 29 06:46:39 PM PDT 24
Finished Jun 29 06:46:45 PM PDT 24
Peak memory 213360 kb
Host smart-bb3ffdb3-536a-46e6-8d4a-cecf956f920d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048206047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2048206047
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1134061755
Short name T234
Test name
Test status
Simulation time 98831091 ps
CPU time 0.78 seconds
Started Jun 29 06:46:38 PM PDT 24
Finished Jun 29 06:46:39 PM PDT 24
Peak memory 204912 kb
Host smart-e9dc50b0-6f9c-44f9-9301-719db5d9cb28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134061755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1134061755
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.263118252
Short name T19
Test name
Test status
Simulation time 12350593461 ps
CPU time 30.25 seconds
Started Jun 29 06:46:38 PM PDT 24
Finished Jun 29 06:47:09 PM PDT 24
Peak memory 213284 kb
Host smart-f480d0be-dda2-45a3-92ef-cb0508d1a8a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263118252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.263118252
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2436244935
Short name T236
Test name
Test status
Simulation time 54159833 ps
CPU time 0.72 seconds
Started Jun 29 06:45:54 PM PDT 24
Finished Jun 29 06:45:55 PM PDT 24
Peak memory 204900 kb
Host smart-5f968dfc-c187-4a3a-9801-bd9b7a430d32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436244935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2436244935
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2003516721
Short name T249
Test name
Test status
Simulation time 3623132119 ps
CPU time 8.1 seconds
Started Jun 29 06:45:54 PM PDT 24
Finished Jun 29 06:46:03 PM PDT 24
Peak memory 205364 kb
Host smart-0063c089-359b-4ae4-9a05-a73076f90370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003516721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2003516721
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.896314877
Short name T230
Test name
Test status
Simulation time 2351243840 ps
CPU time 7.31 seconds
Started Jun 29 06:45:54 PM PDT 24
Finished Jun 29 06:46:02 PM PDT 24
Peak memory 213564 kb
Host smart-49ddd3aa-e644-4e1d-87d1-47510a6f7c20
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896314877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.896314877
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3013046744
Short name T231
Test name
Test status
Simulation time 149140036 ps
CPU time 1.07 seconds
Started Jun 29 06:45:53 PM PDT 24
Finished Jun 29 06:45:54 PM PDT 24
Peak memory 204944 kb
Host smart-5b6c0b13-aa7a-49dd-80da-7a4b64d9391d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013046744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3013046744
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3651399060
Short name T263
Test name
Test status
Simulation time 5491208655 ps
CPU time 13.53 seconds
Started Jun 29 06:45:53 PM PDT 24
Finished Jun 29 06:46:07 PM PDT 24
Peak memory 205300 kb
Host smart-ebeff129-b3e4-4117-8f49-2df1c43c3409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651399060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3651399060
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.1571090623
Short name T29
Test name
Test status
Simulation time 17039318748 ps
CPU time 12.04 seconds
Started Jun 29 06:45:55 PM PDT 24
Finished Jun 29 06:46:08 PM PDT 24
Peak memory 205176 kb
Host smart-f4a99318-97eb-43aa-8b2d-30d83765e44a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571090623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1571090623
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3561780441
Short name T229
Test name
Test status
Simulation time 158789784 ps
CPU time 0.95 seconds
Started Jun 29 06:46:41 PM PDT 24
Finished Jun 29 06:46:43 PM PDT 24
Peak memory 204920 kb
Host smart-4f94b66d-c015-4ea3-846c-51106d500158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561780441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3561780441
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.2032201929
Short name T187
Test name
Test status
Simulation time 2328203601 ps
CPU time 4.14 seconds
Started Jun 29 06:46:45 PM PDT 24
Finished Jun 29 06:46:50 PM PDT 24
Peak memory 213372 kb
Host smart-4cf9a8bc-b05b-4492-963a-2109c84e9ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032201929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.2032201929
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2259437396
Short name T265
Test name
Test status
Simulation time 67250017 ps
CPU time 0.74 seconds
Started Jun 29 06:46:39 PM PDT 24
Finished Jun 29 06:46:41 PM PDT 24
Peak memory 204920 kb
Host smart-a2144689-11b5-467f-9ff8-d87475194620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259437396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2259437396
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.4137446480
Short name T192
Test name
Test status
Simulation time 2974576985 ps
CPU time 8.6 seconds
Started Jun 29 06:46:42 PM PDT 24
Finished Jun 29 06:46:51 PM PDT 24
Peak memory 205212 kb
Host smart-fcb1dda7-c8f5-4a2f-abb8-13d2d7895d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137446480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.4137446480
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1165605993
Short name T224
Test name
Test status
Simulation time 87747382 ps
CPU time 0.89 seconds
Started Jun 29 06:46:45 PM PDT 24
Finished Jun 29 06:46:47 PM PDT 24
Peak memory 204924 kb
Host smart-5fd23868-5a27-4376-a8d1-5022bb2d630c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165605993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1165605993
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.1652304922
Short name T189
Test name
Test status
Simulation time 4780880187 ps
CPU time 8.74 seconds
Started Jun 29 06:46:39 PM PDT 24
Finished Jun 29 06:46:48 PM PDT 24
Peak memory 214560 kb
Host smart-51caaba6-8fd3-4bb3-85cc-f38deb55c414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652304922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1652304922
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1945407983
Short name T199
Test name
Test status
Simulation time 77313052 ps
CPU time 0.74 seconds
Started Jun 29 06:46:44 PM PDT 24
Finished Jun 29 06:46:45 PM PDT 24
Peak memory 204924 kb
Host smart-623f7e61-74e8-4faa-a304-cf19b466e4c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945407983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1945407983
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1182099740
Short name T208
Test name
Test status
Simulation time 28812339 ps
CPU time 0.73 seconds
Started Jun 29 06:46:47 PM PDT 24
Finished Jun 29 06:46:48 PM PDT 24
Peak memory 204892 kb
Host smart-710170d3-5048-4752-9c8a-3d5a47115745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182099740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1182099740
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.518317308
Short name T261
Test name
Test status
Simulation time 35426404 ps
CPU time 0.76 seconds
Started Jun 29 06:46:46 PM PDT 24
Finished Jun 29 06:46:47 PM PDT 24
Peak memory 204896 kb
Host smart-81af8fd3-12be-4711-8980-2530ac3adab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518317308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.518317308
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.3295143956
Short name T7
Test name
Test status
Simulation time 3846095844 ps
CPU time 11.33 seconds
Started Jun 29 06:46:44 PM PDT 24
Finished Jun 29 06:46:56 PM PDT 24
Peak memory 213340 kb
Host smart-1e3cd2ba-a673-43ee-9110-e0cd641f834a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295143956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3295143956
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.670853948
Short name T244
Test name
Test status
Simulation time 154616025 ps
CPU time 0.8 seconds
Started Jun 29 06:46:45 PM PDT 24
Finished Jun 29 06:46:47 PM PDT 24
Peak memory 204916 kb
Host smart-d53ed2e4-6dbd-43f1-ae4b-5a02bd7a327d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670853948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.670853948
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.3711666975
Short name T15
Test name
Test status
Simulation time 5288315422 ps
CPU time 5.4 seconds
Started Jun 29 06:46:46 PM PDT 24
Finished Jun 29 06:46:52 PM PDT 24
Peak memory 213352 kb
Host smart-55f4bc79-2bec-4bdb-b4dd-c2650f029e5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711666975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3711666975
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3844394850
Short name T267
Test name
Test status
Simulation time 100946074 ps
CPU time 0.71 seconds
Started Jun 29 06:46:44 PM PDT 24
Finished Jun 29 06:46:45 PM PDT 24
Peak memory 204932 kb
Host smart-8abb5aed-757b-479f-aa53-a21f4f5a7914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844394850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3844394850
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1724062430
Short name T222
Test name
Test status
Simulation time 127894078 ps
CPU time 0.71 seconds
Started Jun 29 06:46:45 PM PDT 24
Finished Jun 29 06:46:46 PM PDT 24
Peak memory 204920 kb
Host smart-943aa2d2-dacb-4cfb-ba78-a901f1b4e18f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724062430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1724062430
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2475422922
Short name T280
Test name
Test status
Simulation time 114436740 ps
CPU time 0.76 seconds
Started Jun 29 06:46:46 PM PDT 24
Finished Jun 29 06:46:47 PM PDT 24
Peak memory 204912 kb
Host smart-0a29cfa0-b88c-465a-b8d5-d32455b07f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475422922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2475422922
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.509134218
Short name T166
Test name
Test status
Simulation time 3118101203 ps
CPU time 2.19 seconds
Started Jun 29 06:46:47 PM PDT 24
Finished Jun 29 06:46:50 PM PDT 24
Peak memory 205136 kb
Host smart-9cfae694-edd9-493d-98f7-19ae15df4fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509134218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.509134218
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3592482768
Short name T239
Test name
Test status
Simulation time 64425757 ps
CPU time 0.72 seconds
Started Jun 29 06:46:02 PM PDT 24
Finished Jun 29 06:46:03 PM PDT 24
Peak memory 204952 kb
Host smart-e15233e0-e8fc-4591-bba3-186001ffc7c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592482768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3592482768
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.4293262716
Short name T212
Test name
Test status
Simulation time 12170818930 ps
CPU time 31.27 seconds
Started Jun 29 06:46:03 PM PDT 24
Finished Jun 29 06:46:34 PM PDT 24
Peak memory 213496 kb
Host smart-c23cfbbe-58f0-4ab1-b465-ea6296a90993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293262716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.4293262716
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3773869745
Short name T96
Test name
Test status
Simulation time 3017466463 ps
CPU time 3.1 seconds
Started Jun 29 06:46:00 PM PDT 24
Finished Jun 29 06:46:03 PM PDT 24
Peak memory 213516 kb
Host smart-f0bed86d-dddb-479d-a968-8a7b9be1e4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773869745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3773869745
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.32553149
Short name T290
Test name
Test status
Simulation time 3240782734 ps
CPU time 9.22 seconds
Started Jun 29 06:45:59 PM PDT 24
Finished Jun 29 06:46:09 PM PDT 24
Peak memory 213536 kb
Host smart-86215269-ba79-4b57-9b2d-ddc71b2d5f0b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=32553149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl_
access.32553149
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1384439150
Short name T34
Test name
Test status
Simulation time 298311247 ps
CPU time 0.86 seconds
Started Jun 29 06:46:01 PM PDT 24
Finished Jun 29 06:46:02 PM PDT 24
Peak memory 204880 kb
Host smart-06352d25-5a28-4112-a923-087d3767bb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384439150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1384439150
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3009230798
Short name T287
Test name
Test status
Simulation time 4875346746 ps
CPU time 4.92 seconds
Started Jun 29 06:45:52 PM PDT 24
Finished Jun 29 06:45:57 PM PDT 24
Peak memory 213496 kb
Host smart-3d111fd6-e806-4547-9435-a2e18e02990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009230798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3009230798
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1799726938
Short name T73
Test name
Test status
Simulation time 1535964240 ps
CPU time 4.73 seconds
Started Jun 29 06:46:00 PM PDT 24
Finished Jun 29 06:46:06 PM PDT 24
Peak memory 236724 kb
Host smart-c88d7daf-1fcf-4574-bd3b-9b38809f6188
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799726938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1799726938
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.638520857
Short name T9
Test name
Test status
Simulation time 7868157146 ps
CPU time 9.93 seconds
Started Jun 29 06:46:02 PM PDT 24
Finished Jun 29 06:46:13 PM PDT 24
Peak memory 213336 kb
Host smart-7035f25b-c928-40f5-a707-1e929de41573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638520857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.638520857
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1620213576
Short name T232
Test name
Test status
Simulation time 117590211 ps
CPU time 1 seconds
Started Jun 29 06:46:45 PM PDT 24
Finished Jun 29 06:46:47 PM PDT 24
Peak memory 204916 kb
Host smart-1ed7c209-0059-4cb1-82b0-6be44bd293d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620213576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1620213576
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.333393487
Short name T168
Test name
Test status
Simulation time 3578401781 ps
CPU time 9.3 seconds
Started Jun 29 06:46:44 PM PDT 24
Finished Jun 29 06:46:54 PM PDT 24
Peak memory 213388 kb
Host smart-e08abec2-e6f3-4534-96bd-ad69630f553f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333393487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.333393487
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2541464194
Short name T217
Test name
Test status
Simulation time 40880040 ps
CPU time 0.77 seconds
Started Jun 29 06:46:46 PM PDT 24
Finished Jun 29 06:46:47 PM PDT 24
Peak memory 204956 kb
Host smart-e62c500e-b158-447a-b3d0-d564f388a1f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541464194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2541464194
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.491278416
Short name T245
Test name
Test status
Simulation time 214043932 ps
CPU time 0.7 seconds
Started Jun 29 06:46:46 PM PDT 24
Finished Jun 29 06:46:48 PM PDT 24
Peak memory 204924 kb
Host smart-52352975-9546-4304-9c34-1bdde8310d6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491278416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.491278416
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.410261387
Short name T65
Test name
Test status
Simulation time 56883362 ps
CPU time 0.81 seconds
Started Jun 29 06:46:46 PM PDT 24
Finished Jun 29 06:46:48 PM PDT 24
Peak memory 204912 kb
Host smart-82fcb0bd-b04d-4e4a-98fd-bd6537b8ce80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410261387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.410261387
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.3895129302
Short name T16
Test name
Test status
Simulation time 3117208579 ps
CPU time 5.27 seconds
Started Jun 29 06:46:49 PM PDT 24
Finished Jun 29 06:46:55 PM PDT 24
Peak memory 213368 kb
Host smart-3e3e9369-6a95-4d42-8ffc-adf999d4e50c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895129302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.3895129302
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2434448654
Short name T225
Test name
Test status
Simulation time 63928778 ps
CPU time 0.75 seconds
Started Jun 29 06:46:46 PM PDT 24
Finished Jun 29 06:46:48 PM PDT 24
Peak memory 204920 kb
Host smart-7ddd290c-87d0-43d0-8572-49636f37cf54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434448654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2434448654
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.3869482981
Short name T26
Test name
Test status
Simulation time 7434278083 ps
CPU time 6.74 seconds
Started Jun 29 06:46:45 PM PDT 24
Finished Jun 29 06:46:52 PM PDT 24
Peak memory 213464 kb
Host smart-c075d2e4-99bb-400f-b5fc-baafce6b96cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869482981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3869482981
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.4211326435
Short name T94
Test name
Test status
Simulation time 62894956 ps
CPU time 0.79 seconds
Started Jun 29 06:46:57 PM PDT 24
Finished Jun 29 06:46:58 PM PDT 24
Peak memory 204876 kb
Host smart-fa98b36a-2382-40a6-a05d-74c29c373e94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211326435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.4211326435
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.3562981002
Short name T196
Test name
Test status
Simulation time 3367244516 ps
CPU time 8.83 seconds
Started Jun 29 06:46:48 PM PDT 24
Finished Jun 29 06:46:57 PM PDT 24
Peak memory 213352 kb
Host smart-0a1faef9-54f4-4872-8450-bd853fa71263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562981002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3562981002
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2075307019
Short name T259
Test name
Test status
Simulation time 209302774 ps
CPU time 0.76 seconds
Started Jun 29 06:46:52 PM PDT 24
Finished Jun 29 06:46:54 PM PDT 24
Peak memory 204872 kb
Host smart-eb7d5aa1-23c2-4c5a-ac55-ce2b0f75ce45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075307019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2075307019
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.1767610837
Short name T28
Test name
Test status
Simulation time 3147175403 ps
CPU time 8.68 seconds
Started Jun 29 06:46:53 PM PDT 24
Finished Jun 29 06:47:02 PM PDT 24
Peak memory 205196 kb
Host smart-f2cd1960-3b07-4739-b833-c0896ca715df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767610837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1767610837
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2010151560
Short name T202
Test name
Test status
Simulation time 72628148 ps
CPU time 0.74 seconds
Started Jun 29 06:46:54 PM PDT 24
Finished Jun 29 06:46:55 PM PDT 24
Peak memory 204908 kb
Host smart-d9968fb5-7600-4161-b93a-dd4cfc1b5753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010151560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2010151560
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.3976898874
Short name T62
Test name
Test status
Simulation time 5370834250 ps
CPU time 17.09 seconds
Started Jun 29 06:46:56 PM PDT 24
Finished Jun 29 06:47:14 PM PDT 24
Peak memory 214988 kb
Host smart-5ee702a8-fd1d-49e8-bb56-43a2514e8890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976898874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3976898874
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.819274835
Short name T262
Test name
Test status
Simulation time 209592832 ps
CPU time 0.76 seconds
Started Jun 29 06:46:54 PM PDT 24
Finished Jun 29 06:46:55 PM PDT 24
Peak memory 204928 kb
Host smart-82e41a9b-02b6-4ccc-ae46-09893d57cdc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819274835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.819274835
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.31887922
Short name T190
Test name
Test status
Simulation time 24097176791 ps
CPU time 8.36 seconds
Started Jun 29 06:46:54 PM PDT 24
Finished Jun 29 06:47:03 PM PDT 24
Peak memory 213364 kb
Host smart-5c911011-2f3c-4d00-bdd9-dcdd5ac7a602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31887922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.31887922
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1974848562
Short name T206
Test name
Test status
Simulation time 38735325 ps
CPU time 0.79 seconds
Started Jun 29 06:45:59 PM PDT 24
Finished Jun 29 06:46:00 PM PDT 24
Peak memory 204896 kb
Host smart-db29b140-0473-4c58-a478-64b7e74da980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974848562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1974848562
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2754558210
Short name T228
Test name
Test status
Simulation time 7136925235 ps
CPU time 6.55 seconds
Started Jun 29 06:45:59 PM PDT 24
Finished Jun 29 06:46:05 PM PDT 24
Peak memory 205364 kb
Host smart-5851d12b-594d-4fa5-83d8-c0805e59def5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754558210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2754558210
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1268637482
Short name T30
Test name
Test status
Simulation time 2937472246 ps
CPU time 9.01 seconds
Started Jun 29 06:46:00 PM PDT 24
Finished Jun 29 06:46:10 PM PDT 24
Peak memory 213484 kb
Host smart-c7634bd5-a0aa-4eb4-966e-0302640e6c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268637482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1268637482
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1274152502
Short name T252
Test name
Test status
Simulation time 4296404619 ps
CPU time 2.32 seconds
Started Jun 29 06:46:00 PM PDT 24
Finished Jun 29 06:46:03 PM PDT 24
Peak memory 205348 kb
Host smart-c09362e9-3068-4345-a281-5e97ec367648
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1274152502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1274152502
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3555295179
Short name T248
Test name
Test status
Simulation time 2572496048 ps
CPU time 3.44 seconds
Started Jun 29 06:45:59 PM PDT 24
Finished Jun 29 06:46:03 PM PDT 24
Peak memory 205296 kb
Host smart-1d77b4ae-0f95-483d-8c61-a264f6d71863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555295179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3555295179
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.2815527892
Short name T170
Test name
Test status
Simulation time 3009233417 ps
CPU time 7.24 seconds
Started Jun 29 06:45:59 PM PDT 24
Finished Jun 29 06:46:06 PM PDT 24
Peak memory 213352 kb
Host smart-bb725cd4-10f7-4505-b22b-870da9689110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815527892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2815527892
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2948769707
Short name T39
Test name
Test status
Simulation time 28110861 ps
CPU time 0.77 seconds
Started Jun 29 06:46:00 PM PDT 24
Finished Jun 29 06:46:01 PM PDT 24
Peak memory 204924 kb
Host smart-7aea02ea-819a-4021-8ebd-734ecdd57887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948769707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2948769707
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1352955058
Short name T95
Test name
Test status
Simulation time 13093328464 ps
CPU time 35.75 seconds
Started Jun 29 06:46:00 PM PDT 24
Finished Jun 29 06:46:36 PM PDT 24
Peak memory 213524 kb
Host smart-c1702a00-f4b7-46b8-afa1-9b8b9709de02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352955058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1352955058
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3405273484
Short name T51
Test name
Test status
Simulation time 7684180679 ps
CPU time 10.5 seconds
Started Jun 29 06:46:02 PM PDT 24
Finished Jun 29 06:46:13 PM PDT 24
Peak memory 213536 kb
Host smart-50d20ef4-8a5c-4ba6-852e-bdc2aa5685de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405273484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3405273484
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1478836678
Short name T220
Test name
Test status
Simulation time 2800099551 ps
CPU time 4.63 seconds
Started Jun 29 06:46:00 PM PDT 24
Finished Jun 29 06:46:05 PM PDT 24
Peak memory 205368 kb
Host smart-52345c7c-7821-4586-96f3-4668e9501bf5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478836678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1478836678
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1252421531
Short name T274
Test name
Test status
Simulation time 10397975191 ps
CPU time 14.1 seconds
Started Jun 29 06:46:00 PM PDT 24
Finished Jun 29 06:46:15 PM PDT 24
Peak memory 213476 kb
Host smart-bbaeb289-a48a-4713-b67d-81dbbac4008c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252421531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1252421531
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.456725294
Short name T86
Test name
Test status
Simulation time 38739060 ps
CPU time 0.79 seconds
Started Jun 29 06:46:08 PM PDT 24
Finished Jun 29 06:46:09 PM PDT 24
Peak memory 204920 kb
Host smart-5c39a9be-c953-4808-b403-2048f2277f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456725294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.456725294
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1958128790
Short name T36
Test name
Test status
Simulation time 3232564211 ps
CPU time 5.43 seconds
Started Jun 29 06:46:06 PM PDT 24
Finished Jun 29 06:46:12 PM PDT 24
Peak memory 213496 kb
Host smart-93df564d-1786-4f1c-94c8-596c6bcb67d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958128790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1958128790
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1027809740
Short name T106
Test name
Test status
Simulation time 5828177021 ps
CPU time 16.31 seconds
Started Jun 29 06:46:11 PM PDT 24
Finished Jun 29 06:46:27 PM PDT 24
Peak memory 213468 kb
Host smart-8f3f0ae4-e415-4767-a5aa-6022289b61bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027809740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1027809740
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.2831876962
Short name T88
Test name
Test status
Simulation time 1830151681 ps
CPU time 2.71 seconds
Started Jun 29 06:46:09 PM PDT 24
Finished Jun 29 06:46:12 PM PDT 24
Peak memory 213420 kb
Host smart-b02ba8ba-bd29-4867-8199-539a988d913d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2831876962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.2831876962
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2441813180
Short name T275
Test name
Test status
Simulation time 3300404813 ps
CPU time 3.2 seconds
Started Jun 29 06:46:07 PM PDT 24
Finished Jun 29 06:46:10 PM PDT 24
Peak memory 205348 kb
Host smart-2ffbfb3a-eb54-4873-912c-3cae9217f510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441813180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2441813180
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1042353517
Short name T40
Test name
Test status
Simulation time 52709495 ps
CPU time 0.76 seconds
Started Jun 29 06:46:10 PM PDT 24
Finished Jun 29 06:46:11 PM PDT 24
Peak memory 204924 kb
Host smart-ca90ad65-14da-46a3-8da1-5930d8aaecb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042353517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1042353517
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2173503177
Short name T268
Test name
Test status
Simulation time 4146569047 ps
CPU time 2.74 seconds
Started Jun 29 06:46:09 PM PDT 24
Finished Jun 29 06:46:12 PM PDT 24
Peak memory 213460 kb
Host smart-d609ba52-1724-4e18-92ea-cf49a06eb7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173503177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2173503177
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.129258734
Short name T240
Test name
Test status
Simulation time 6454855589 ps
CPU time 15.78 seconds
Started Jun 29 06:46:07 PM PDT 24
Finished Jun 29 06:46:23 PM PDT 24
Peak memory 213520 kb
Host smart-df7b533e-2a2c-4fec-9269-b661d9cb14f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129258734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.129258734
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2906499406
Short name T216
Test name
Test status
Simulation time 7713480578 ps
CPU time 16.1 seconds
Started Jun 29 06:46:08 PM PDT 24
Finished Jun 29 06:46:24 PM PDT 24
Peak memory 213520 kb
Host smart-7d41b802-c1fd-4490-9bbd-cc95bcc15024
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2906499406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2906499406
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1595318702
Short name T59
Test name
Test status
Simulation time 1672120988 ps
CPU time 6 seconds
Started Jun 29 06:46:08 PM PDT 24
Finished Jun 29 06:46:15 PM PDT 24
Peak memory 205328 kb
Host smart-8ff5ec6f-f445-4def-a235-26651b8937b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595318702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1595318702
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.152525798
Short name T163
Test name
Test status
Simulation time 5176075130 ps
CPU time 2.84 seconds
Started Jun 29 06:46:09 PM PDT 24
Finished Jun 29 06:46:12 PM PDT 24
Peak memory 213332 kb
Host smart-0c24f87f-1e9c-4144-9f8f-811807f2ae2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152525798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.152525798
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2240353531
Short name T241
Test name
Test status
Simulation time 42369437 ps
CPU time 0.7 seconds
Started Jun 29 06:46:07 PM PDT 24
Finished Jun 29 06:46:08 PM PDT 24
Peak memory 204924 kb
Host smart-e7970118-f969-4ab3-bb35-2b2aa0f2e7b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240353531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2240353531
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.2084667144
Short name T210
Test name
Test status
Simulation time 37539868346 ps
CPU time 103.89 seconds
Started Jun 29 06:46:09 PM PDT 24
Finished Jun 29 06:47:53 PM PDT 24
Peak memory 213492 kb
Host smart-be3364b7-3b6f-4fdf-b287-2efe2185a4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084667144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2084667144
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2740432913
Short name T108
Test name
Test status
Simulation time 875701006 ps
CPU time 3.32 seconds
Started Jun 29 06:46:09 PM PDT 24
Finished Jun 29 06:46:12 PM PDT 24
Peak memory 213436 kb
Host smart-b0743457-138f-4ceb-a3b0-4ebc3bbcfb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740432913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2740432913
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2714864781
Short name T87
Test name
Test status
Simulation time 4392615568 ps
CPU time 8.18 seconds
Started Jun 29 06:46:09 PM PDT 24
Finished Jun 29 06:46:18 PM PDT 24
Peak memory 205280 kb
Host smart-94292eab-c0a3-409d-a578-2ec2964ab305
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2714864781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2714864781
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1098896488
Short name T165
Test name
Test status
Simulation time 3108108007 ps
CPU time 3.67 seconds
Started Jun 29 06:46:08 PM PDT 24
Finished Jun 29 06:46:12 PM PDT 24
Peak memory 213460 kb
Host smart-710e591d-2ff9-46f1-83f6-fbd0d4cab806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098896488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1098896488
Directory /workspace/9.rv_dm_sba_tl_access/latest
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