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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.75 95.27 79.59 89.42 74.36 85.50 97.79 57.31


Total test records in report: 441
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T99 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.573445286 Jul 01 04:24:39 PM PDT 24 Jul 01 04:24:47 PM PDT 24 352895164 ps
T303 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1812402470 Jul 01 04:24:48 PM PDT 24 Jul 01 04:24:54 PM PDT 24 406052375 ps
T100 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1179052344 Jul 01 04:25:22 PM PDT 24 Jul 01 04:25:37 PM PDT 24 935159776 ps
T304 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1557635135 Jul 01 04:24:52 PM PDT 24 Jul 01 04:25:22 PM PDT 24 17840570661 ps
T305 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2100994187 Jul 01 04:25:52 PM PDT 24 Jul 01 04:26:11 PM PDT 24 2405401234 ps
T133 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3822781245 Jul 01 04:24:46 PM PDT 24 Jul 01 04:24:55 PM PDT 24 411011511 ps
T209 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3129115947 Jul 01 04:24:56 PM PDT 24 Jul 01 04:25:03 PM PDT 24 199267815 ps
T135 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.29337634 Jul 01 04:24:34 PM PDT 24 Jul 01 04:24:54 PM PDT 24 2454407429 ps
T306 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3003342249 Jul 01 04:24:28 PM PDT 24 Jul 01 04:24:43 PM PDT 24 3762717378 ps
T101 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3596549403 Jul 01 04:24:48 PM PDT 24 Jul 01 04:24:55 PM PDT 24 145816304 ps
T102 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4225543283 Jul 01 04:24:31 PM PDT 24 Jul 01 04:25:45 PM PDT 24 1188247577 ps
T307 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1175992585 Jul 01 04:24:22 PM PDT 24 Jul 01 04:24:31 PM PDT 24 1223937146 ps
T308 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3466097798 Jul 01 04:24:37 PM PDT 24 Jul 01 04:24:46 PM PDT 24 2411769218 ps
T309 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4009007432 Jul 01 04:24:44 PM PDT 24 Jul 01 04:25:03 PM PDT 24 4767859815 ps
T310 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.604741746 Jul 01 04:25:51 PM PDT 24 Jul 01 04:26:05 PM PDT 24 1003787159 ps
T311 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4264532032 Jul 01 04:24:44 PM PDT 24 Jul 01 04:24:49 PM PDT 24 223338358 ps
T312 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1447350723 Jul 01 04:25:26 PM PDT 24 Jul 01 04:25:41 PM PDT 24 509404203 ps
T313 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4030892192 Jul 01 04:24:27 PM PDT 24 Jul 01 04:24:47 PM PDT 24 6232344356 ps
T125 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2942730785 Jul 01 04:24:55 PM PDT 24 Jul 01 04:25:06 PM PDT 24 2063284305 ps
T134 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3315607963 Jul 01 04:25:03 PM PDT 24 Jul 01 04:25:08 PM PDT 24 312234841 ps
T314 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.4016632141 Jul 01 04:24:46 PM PDT 24 Jul 01 04:26:01 PM PDT 24 40344519648 ps
T129 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1471484039 Jul 01 04:24:21 PM PDT 24 Jul 01 04:25:42 PM PDT 24 8720345994 ps
T315 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1498996282 Jul 01 04:24:43 PM PDT 24 Jul 01 04:24:49 PM PDT 24 708355255 ps
T316 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3554759435 Jul 01 04:24:41 PM PDT 24 Jul 01 04:24:57 PM PDT 24 4091859279 ps
T317 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.692061023 Jul 01 04:24:17 PM PDT 24 Jul 01 04:25:19 PM PDT 24 40289578267 ps
T318 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3026723381 Jul 01 04:24:15 PM PDT 24 Jul 01 04:24:50 PM PDT 24 18517613236 ps
T319 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2518176783 Jul 01 04:24:36 PM PDT 24 Jul 01 04:24:43 PM PDT 24 64260412 ps
T61 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.572315123 Jul 01 04:24:37 PM PDT 24 Jul 01 04:26:05 PM PDT 24 71689002905 ps
T109 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3556219938 Jul 01 04:24:24 PM PDT 24 Jul 01 04:24:59 PM PDT 24 1476968660 ps
T320 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2360348924 Jul 01 04:25:04 PM PDT 24 Jul 01 04:25:11 PM PDT 24 1066542370 ps
T110 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1333375672 Jul 01 04:24:56 PM PDT 24 Jul 01 04:25:07 PM PDT 24 888407041 ps
T321 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1636383814 Jul 01 04:24:37 PM PDT 24 Jul 01 04:25:19 PM PDT 24 7607618681 ps
T117 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.91072489 Jul 01 04:24:41 PM PDT 24 Jul 01 04:24:47 PM PDT 24 91308940 ps
T322 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2583274232 Jul 01 04:24:35 PM PDT 24 Jul 01 04:24:45 PM PDT 24 508559802 ps
T126 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3193160483 Jul 01 04:24:58 PM PDT 24 Jul 01 04:25:08 PM PDT 24 1356693454 ps
T323 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.328645779 Jul 01 04:25:05 PM PDT 24 Jul 01 04:25:09 PM PDT 24 130031153 ps
T324 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1111787940 Jul 01 04:24:42 PM PDT 24 Jul 01 04:24:51 PM PDT 24 2992657363 ps
T325 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2751946869 Jul 01 04:24:37 PM PDT 24 Jul 01 04:24:44 PM PDT 24 119522473 ps
T326 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4274894832 Jul 01 04:24:41 PM PDT 24 Jul 01 04:24:47 PM PDT 24 299996829 ps
T327 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1752897734 Jul 01 04:25:05 PM PDT 24 Jul 01 04:25:10 PM PDT 24 122620421 ps
T328 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2108745286 Jul 01 04:25:45 PM PDT 24 Jul 01 04:26:17 PM PDT 24 7614885647 ps
T111 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1267995306 Jul 01 04:24:25 PM PDT 24 Jul 01 04:24:38 PM PDT 24 473448564 ps
T329 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.593887628 Jul 01 04:24:22 PM PDT 24 Jul 01 04:24:31 PM PDT 24 572368626 ps
T330 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.765211103 Jul 01 04:24:48 PM PDT 24 Jul 01 04:24:56 PM PDT 24 77826238 ps
T118 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2279497442 Jul 01 04:24:39 PM PDT 24 Jul 01 04:24:52 PM PDT 24 102009115 ps
T331 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1221229609 Jul 01 04:24:45 PM PDT 24 Jul 01 04:24:53 PM PDT 24 1209900641 ps
T119 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2931311500 Jul 01 04:24:46 PM PDT 24 Jul 01 04:24:52 PM PDT 24 170489017 ps
T332 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3514327666 Jul 01 04:24:25 PM PDT 24 Jul 01 04:24:36 PM PDT 24 95821320 ps
T163 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1009270080 Jul 01 04:24:35 PM PDT 24 Jul 01 04:24:50 PM PDT 24 809025438 ps
T160 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3187375725 Jul 01 04:24:19 PM PDT 24 Jul 01 04:25:48 PM PDT 24 27764513052 ps
T333 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.431651563 Jul 01 04:24:25 PM PDT 24 Jul 01 04:25:43 PM PDT 24 30461087860 ps
T127 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.896359066 Jul 01 04:24:38 PM PDT 24 Jul 01 04:24:50 PM PDT 24 164396015 ps
T120 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.868548570 Jul 01 04:24:24 PM PDT 24 Jul 01 04:25:38 PM PDT 24 1265019024 ps
T334 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3385038735 Jul 01 04:24:52 PM PDT 24 Jul 01 04:25:14 PM PDT 24 11838613500 ps
T172 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2915000942 Jul 01 04:24:53 PM PDT 24 Jul 01 04:25:07 PM PDT 24 2112703708 ps
T335 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.169219758 Jul 01 04:25:26 PM PDT 24 Jul 01 04:25:40 PM PDT 24 494253179 ps
T336 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1713573802 Jul 01 04:24:27 PM PDT 24 Jul 01 04:24:38 PM PDT 24 206660615 ps
T337 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1236643182 Jul 01 04:24:41 PM PDT 24 Jul 01 04:24:48 PM PDT 24 282140319 ps
T161 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.793602781 Jul 01 04:25:01 PM PDT 24 Jul 01 04:25:08 PM PDT 24 377444007 ps
T338 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3128522944 Jul 01 04:24:48 PM PDT 24 Jul 01 04:25:34 PM PDT 24 37501647933 ps
T122 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.102401103 Jul 01 04:24:56 PM PDT 24 Jul 01 04:25:01 PM PDT 24 99859012 ps
T339 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.272988323 Jul 01 04:24:48 PM PDT 24 Jul 01 04:24:54 PM PDT 24 1046077685 ps
T340 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.582921369 Jul 01 04:24:25 PM PDT 24 Jul 01 04:25:33 PM PDT 24 2940600592 ps
T341 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3891786967 Jul 01 04:24:49 PM PDT 24 Jul 01 04:24:57 PM PDT 24 1029983227 ps
T112 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.218548701 Jul 01 04:24:47 PM PDT 24 Jul 01 04:24:57 PM PDT 24 593349027 ps
T165 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2747264771 Jul 01 04:24:53 PM PDT 24 Jul 01 04:25:11 PM PDT 24 2808006364 ps
T123 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2424504936 Jul 01 04:25:10 PM PDT 24 Jul 01 04:25:16 PM PDT 24 185125604 ps
T342 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1883721319 Jul 01 04:24:59 PM PDT 24 Jul 01 04:25:52 PM PDT 24 18885954597 ps
T343 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1424026381 Jul 01 04:24:25 PM PDT 24 Jul 01 04:24:35 PM PDT 24 197864277 ps
T105 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.241017979 Jul 01 04:24:32 PM PDT 24 Jul 01 04:24:53 PM PDT 24 4581891384 ps
T124 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3529500621 Jul 01 04:24:33 PM PDT 24 Jul 01 04:24:43 PM PDT 24 378091477 ps
T344 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.79759943 Jul 01 04:24:48 PM PDT 24 Jul 01 04:24:53 PM PDT 24 411356740 ps
T345 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3711911400 Jul 01 04:24:26 PM PDT 24 Jul 01 04:24:37 PM PDT 24 1090789168 ps
T346 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.722927875 Jul 01 04:24:34 PM PDT 24 Jul 01 04:27:52 PM PDT 24 66544413556 ps
T347 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2353326420 Jul 01 04:24:31 PM PDT 24 Jul 01 04:24:44 PM PDT 24 339941195 ps
T348 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3318529665 Jul 01 04:24:21 PM PDT 24 Jul 01 04:26:36 PM PDT 24 49498576516 ps
T349 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3918649179 Jul 01 04:24:19 PM PDT 24 Jul 01 04:24:25 PM PDT 24 182992457 ps
T164 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3420746967 Jul 01 04:25:26 PM PDT 24 Jul 01 04:25:49 PM PDT 24 1619224125 ps
T350 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2033406985 Jul 01 04:24:47 PM PDT 24 Jul 01 04:24:53 PM PDT 24 242456704 ps
T351 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2834491646 Jul 01 04:24:26 PM PDT 24 Jul 01 04:24:42 PM PDT 24 10420278617 ps
T162 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.280191713 Jul 01 04:24:51 PM PDT 24 Jul 01 04:24:59 PM PDT 24 214990897 ps
T352 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.403797900 Jul 01 04:25:52 PM PDT 24 Jul 01 04:26:19 PM PDT 24 10556960314 ps
T353 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3241633503 Jul 01 04:24:47 PM PDT 24 Jul 01 04:24:58 PM PDT 24 105732677 ps
T128 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1232036951 Jul 01 04:24:28 PM PDT 24 Jul 01 04:24:45 PM PDT 24 1127798355 ps
T354 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.743016823 Jul 01 04:24:26 PM PDT 24 Jul 01 04:24:36 PM PDT 24 313901729 ps
T168 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2534106951 Jul 01 04:24:54 PM PDT 24 Jul 01 04:25:17 PM PDT 24 4888715953 ps
T355 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.4180940194 Jul 01 04:24:32 PM PDT 24 Jul 01 04:24:44 PM PDT 24 233983786 ps
T177 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2237252965 Jul 01 04:24:30 PM PDT 24 Jul 01 04:25:10 PM PDT 24 17935986835 ps
T171 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.494791662 Jul 01 04:24:39 PM PDT 24 Jul 01 04:25:05 PM PDT 24 4406015686 ps
T356 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.91726857 Jul 01 04:24:49 PM PDT 24 Jul 01 04:24:57 PM PDT 24 314184810 ps
T357 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1848635544 Jul 01 04:24:54 PM PDT 24 Jul 01 04:25:16 PM PDT 24 6763901933 ps
T358 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4190954063 Jul 01 04:24:48 PM PDT 24 Jul 01 04:24:59 PM PDT 24 2308930828 ps
T359 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1321388148 Jul 01 04:24:40 PM PDT 24 Jul 01 04:24:47 PM PDT 24 1153830329 ps
T360 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2737521530 Jul 01 04:24:50 PM PDT 24 Jul 01 04:24:55 PM PDT 24 173017280 ps
T361 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2684253012 Jul 01 04:24:35 PM PDT 24 Jul 01 04:24:44 PM PDT 24 3654366571 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3723603761 Jul 01 04:24:24 PM PDT 24 Jul 01 04:24:33 PM PDT 24 317622279 ps
T363 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1419541042 Jul 01 04:24:24 PM PDT 24 Jul 01 04:24:37 PM PDT 24 694949868 ps
T364 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1914130994 Jul 01 04:24:25 PM PDT 24 Jul 01 04:24:36 PM PDT 24 35825466 ps
T166 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1178826276 Jul 01 04:25:05 PM PDT 24 Jul 01 04:25:28 PM PDT 24 20077945797 ps
T365 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2999772223 Jul 01 04:24:28 PM PDT 24 Jul 01 04:25:51 PM PDT 24 3388762931 ps
T366 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.214200021 Jul 01 04:24:57 PM PDT 24 Jul 01 04:25:04 PM PDT 24 2505528540 ps
T173 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.496853099 Jul 01 04:24:29 PM PDT 24 Jul 01 04:25:00 PM PDT 24 2921957760 ps
T367 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2739116485 Jul 01 04:24:51 PM PDT 24 Jul 01 04:25:06 PM PDT 24 3778123892 ps
T368 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.246873143 Jul 01 04:24:27 PM PDT 24 Jul 01 04:24:40 PM PDT 24 4411728738 ps
T369 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.540963595 Jul 01 04:24:41 PM PDT 24 Jul 01 04:24:46 PM PDT 24 60857599 ps
T174 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2516593390 Jul 01 04:24:50 PM PDT 24 Jul 01 04:25:05 PM PDT 24 1706802581 ps
T175 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.467082324 Jul 01 04:24:22 PM PDT 24 Jul 01 04:24:46 PM PDT 24 3609700277 ps
T370 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3725712665 Jul 01 04:25:06 PM PDT 24 Jul 01 04:25:16 PM PDT 24 3622292914 ps
T371 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2689223088 Jul 01 04:24:20 PM PDT 24 Jul 01 04:25:47 PM PDT 24 28161438177 ps
T372 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1165410138 Jul 01 04:24:53 PM PDT 24 Jul 01 04:25:23 PM PDT 24 5278086766 ps
T373 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3641370845 Jul 01 04:24:27 PM PDT 24 Jul 01 04:24:43 PM PDT 24 2043399639 ps
T106 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2527496672 Jul 01 04:24:29 PM PDT 24 Jul 01 04:24:41 PM PDT 24 4458131676 ps
T374 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3537867539 Jul 01 04:24:31 PM PDT 24 Jul 01 04:24:44 PM PDT 24 865950123 ps
T375 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4112558300 Jul 01 04:24:24 PM PDT 24 Jul 01 04:24:36 PM PDT 24 916069495 ps
T376 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.436011953 Jul 01 04:25:12 PM PDT 24 Jul 01 04:25:19 PM PDT 24 1284823357 ps
T377 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1423363481 Jul 01 04:25:04 PM PDT 24 Jul 01 04:25:11 PM PDT 24 4811910765 ps
T176 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2326982155 Jul 01 04:24:44 PM PDT 24 Jul 01 04:25:32 PM PDT 24 25824493518 ps
T378 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1707335776 Jul 01 04:24:38 PM PDT 24 Jul 01 04:25:26 PM PDT 24 94663132315 ps
T379 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3590588966 Jul 01 04:24:39 PM PDT 24 Jul 01 04:24:48 PM PDT 24 123193553 ps
T380 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.794057050 Jul 01 04:25:46 PM PDT 24 Jul 01 04:26:41 PM PDT 24 33465935969 ps
T381 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3582368993 Jul 01 04:24:48 PM PDT 24 Jul 01 04:24:57 PM PDT 24 352328754 ps
T169 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3817336380 Jul 01 04:25:08 PM PDT 24 Jul 01 04:25:23 PM PDT 24 1259133021 ps
T382 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1709047892 Jul 01 04:24:25 PM PDT 24 Jul 01 04:24:36 PM PDT 24 170605941 ps
T383 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2704370592 Jul 01 04:24:41 PM PDT 24 Jul 01 04:25:07 PM PDT 24 4030745769 ps
T384 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2483770598 Jul 01 04:25:08 PM PDT 24 Jul 01 04:25:12 PM PDT 24 513302437 ps
T385 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1590909613 Jul 01 04:24:31 PM PDT 24 Jul 01 04:24:47 PM PDT 24 4199635333 ps
T386 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1165662019 Jul 01 04:25:51 PM PDT 24 Jul 01 04:26:04 PM PDT 24 497959243 ps
T387 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3263224929 Jul 01 04:24:52 PM PDT 24 Jul 01 04:24:57 PM PDT 24 619977595 ps
T388 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3375076571 Jul 01 04:25:43 PM PDT 24 Jul 01 04:25:55 PM PDT 24 385858067 ps
T389 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.442649571 Jul 01 04:24:25 PM PDT 24 Jul 01 04:24:36 PM PDT 24 293899851 ps
T390 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3670803621 Jul 01 04:24:44 PM PDT 24 Jul 01 04:24:56 PM PDT 24 6119486920 ps
T391 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.676184195 Jul 01 04:24:44 PM PDT 24 Jul 01 04:24:51 PM PDT 24 154798146 ps
T392 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.717070601 Jul 01 04:24:24 PM PDT 24 Jul 01 04:24:33 PM PDT 24 47972058 ps
T393 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2174320302 Jul 01 04:24:19 PM PDT 24 Jul 01 04:24:49 PM PDT 24 8619658896 ps
T394 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1746418133 Jul 01 04:24:47 PM PDT 24 Jul 01 04:24:53 PM PDT 24 55837422 ps
T121 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2746357439 Jul 01 04:24:59 PM PDT 24 Jul 01 04:25:02 PM PDT 24 125683405 ps
T395 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.558143970 Jul 01 04:24:32 PM PDT 24 Jul 01 04:25:02 PM PDT 24 25765156920 ps
T113 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3452610990 Jul 01 04:24:28 PM PDT 24 Jul 01 04:24:45 PM PDT 24 1652547435 ps
T396 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.738475699 Jul 01 04:24:55 PM PDT 24 Jul 01 04:25:04 PM PDT 24 5776733644 ps
T114 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1648287800 Jul 01 04:24:40 PM PDT 24 Jul 01 04:24:53 PM PDT 24 317251787 ps
T397 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1248158027 Jul 01 04:25:52 PM PDT 24 Jul 01 04:26:05 PM PDT 24 166195186 ps
T398 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3301006976 Jul 01 04:24:43 PM PDT 24 Jul 01 04:26:05 PM PDT 24 4579589356 ps
T399 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3824513203 Jul 01 04:24:26 PM PDT 24 Jul 01 04:24:41 PM PDT 24 13606987313 ps
T400 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.4096883396 Jul 01 04:24:34 PM PDT 24 Jul 01 04:24:56 PM PDT 24 15529271721 ps
T401 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.530218960 Jul 01 04:24:23 PM PDT 24 Jul 01 04:24:32 PM PDT 24 132866616 ps
T402 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3732851601 Jul 01 04:24:43 PM PDT 24 Jul 01 04:24:52 PM PDT 24 444893558 ps
T170 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.958435314 Jul 01 04:24:37 PM PDT 24 Jul 01 04:25:01 PM PDT 24 2333364778 ps
T403 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4046652743 Jul 01 04:24:47 PM PDT 24 Jul 01 04:25:14 PM PDT 24 25495254735 ps
T107 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2806811849 Jul 01 04:24:47 PM PDT 24 Jul 01 04:25:35 PM PDT 24 17489475661 ps
T404 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.192774768 Jul 01 04:24:25 PM PDT 24 Jul 01 04:24:35 PM PDT 24 428448130 ps
T405 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3314753511 Jul 01 04:24:20 PM PDT 24 Jul 01 04:24:28 PM PDT 24 143964069 ps
T406 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1149640197 Jul 01 04:24:35 PM PDT 24 Jul 01 04:24:42 PM PDT 24 32508400 ps
T407 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3669863047 Jul 01 04:24:49 PM PDT 24 Jul 01 04:25:07 PM PDT 24 10050472232 ps
T408 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.425701902 Jul 01 04:24:53 PM PDT 24 Jul 01 04:25:16 PM PDT 24 1815183070 ps
T409 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2304354517 Jul 01 04:25:26 PM PDT 24 Jul 01 04:26:10 PM PDT 24 2584798946 ps
T410 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1677081793 Jul 01 04:24:25 PM PDT 24 Jul 01 04:24:39 PM PDT 24 3203989282 ps
T411 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1157673797 Jul 01 04:24:39 PM PDT 24 Jul 01 04:24:59 PM PDT 24 16759934175 ps
T412 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1762950837 Jul 01 04:24:29 PM PDT 24 Jul 01 04:24:39 PM PDT 24 135144141 ps
T115 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4001953967 Jul 01 04:24:32 PM PDT 24 Jul 01 04:24:48 PM PDT 24 660492812 ps
T413 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2344277916 Jul 01 04:24:58 PM PDT 24 Jul 01 04:25:05 PM PDT 24 1293111118 ps
T414 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3933737003 Jul 01 04:24:54 PM PDT 24 Jul 01 04:25:00 PM PDT 24 47716143 ps
T415 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.920096005 Jul 01 04:25:18 PM PDT 24 Jul 01 04:25:29 PM PDT 24 51643265 ps
T116 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1421310977 Jul 01 04:24:37 PM PDT 24 Jul 01 04:24:49 PM PDT 24 756136070 ps
T416 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2936442752 Jul 01 04:24:37 PM PDT 24 Jul 01 04:24:44 PM PDT 24 423472492 ps
T417 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.4237683306 Jul 01 04:24:27 PM PDT 24 Jul 01 04:25:35 PM PDT 24 36818976483 ps
T418 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4251139120 Jul 01 04:25:03 PM PDT 24 Jul 01 04:25:15 PM PDT 24 13366057531 ps
T419 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1459511911 Jul 01 04:24:30 PM PDT 24 Jul 01 04:26:35 PM PDT 24 42679992164 ps
T420 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1621822155 Jul 01 04:24:23 PM PDT 24 Jul 01 04:24:34 PM PDT 24 321773020 ps
T421 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3244944337 Jul 01 04:24:31 PM PDT 24 Jul 01 04:24:42 PM PDT 24 216287670 ps
T422 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2934643846 Jul 01 04:24:37 PM PDT 24 Jul 01 04:24:49 PM PDT 24 966348603 ps
T423 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.883388354 Jul 01 04:24:48 PM PDT 24 Jul 01 04:24:54 PM PDT 24 456282491 ps
T424 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.634364500 Jul 01 04:25:01 PM PDT 24 Jul 01 04:25:13 PM PDT 24 5626684054 ps
T425 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2870968760 Jul 01 04:24:45 PM PDT 24 Jul 01 04:24:55 PM PDT 24 5331226929 ps
T426 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2073052750 Jul 01 04:24:33 PM PDT 24 Jul 01 04:25:24 PM PDT 24 50049808018 ps
T427 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.290990687 Jul 01 04:24:30 PM PDT 24 Jul 01 04:24:39 PM PDT 24 60007201 ps
T428 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3845702395 Jul 01 04:24:27 PM PDT 24 Jul 01 04:24:38 PM PDT 24 332094645 ps
T429 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.105740485 Jul 01 04:24:34 PM PDT 24 Jul 01 04:25:05 PM PDT 24 39501817259 ps
T430 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2734241198 Jul 01 04:24:43 PM PDT 24 Jul 01 04:24:50 PM PDT 24 115440618 ps
T431 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.346594092 Jul 01 04:24:58 PM PDT 24 Jul 01 04:25:03 PM PDT 24 1248263061 ps
T108 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4008447811 Jul 01 04:24:33 PM PDT 24 Jul 01 04:25:39 PM PDT 24 19779335326 ps
T432 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1275522650 Jul 01 04:24:56 PM PDT 24 Jul 01 04:25:05 PM PDT 24 3592702455 ps
T433 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1679685019 Jul 01 04:24:50 PM PDT 24 Jul 01 04:24:57 PM PDT 24 2569072759 ps
T434 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1793665157 Jul 01 04:24:23 PM PDT 24 Jul 01 04:24:34 PM PDT 24 159485838 ps
T435 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.744264730 Jul 01 04:24:49 PM PDT 24 Jul 01 04:25:01 PM PDT 24 14665274215 ps
T436 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1276386468 Jul 01 04:24:52 PM PDT 24 Jul 01 04:24:57 PM PDT 24 210415688 ps
T167 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3918717493 Jul 01 04:24:48 PM PDT 24 Jul 01 04:25:00 PM PDT 24 863530212 ps
T437 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1433846135 Jul 01 04:24:52 PM PDT 24 Jul 01 04:25:03 PM PDT 24 870393980 ps
T438 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2688752595 Jul 01 04:25:19 PM PDT 24 Jul 01 04:25:32 PM PDT 24 261221929 ps
T439 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2488770398 Jul 01 04:24:29 PM PDT 24 Jul 01 04:24:49 PM PDT 24 2193222285 ps
T440 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2798652508 Jul 01 04:24:57 PM PDT 24 Jul 01 04:25:02 PM PDT 24 782796078 ps
T441 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2042800723 Jul 01 04:24:52 PM PDT 24 Jul 01 04:25:03 PM PDT 24 322305975 ps

Test location /workspace/coverage/default/35.rv_dm_stress_all.2010734229
Short name T7
Test name
Test status
Simulation time 3178676300 ps
CPU time 2.66 seconds
Started Jul 01 04:26:16 PM PDT 24
Finished Jul 01 04:26:32 PM PDT 24
Peak memory 213160 kb
Host smart-fa14cfb7-29ec-48ac-a226-87d097250372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010734229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2010734229
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1566478986
Short name T27
Test name
Test status
Simulation time 26872973686 ps
CPU time 31.56 seconds
Started Jul 01 04:26:14 PM PDT 24
Finished Jul 01 04:26:58 PM PDT 24
Peak memory 213328 kb
Host smart-7ac333f4-e36a-47dc-963e-6307af16e490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566478986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1566478986
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1965015446
Short name T60
Test name
Test status
Simulation time 54129578386 ps
CPU time 62.93 seconds
Started Jul 01 04:24:22 PM PDT 24
Finished Jul 01 04:25:31 PM PDT 24
Peak memory 222560 kb
Host smart-75ec23d9-c7b3-4e64-b201-a18658535229
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965015446 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1965015446
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3576400329
Short name T88
Test name
Test status
Simulation time 3197401981 ps
CPU time 18.76 seconds
Started Jul 01 04:24:25 PM PDT 24
Finished Jul 01 04:24:52 PM PDT 24
Peak memory 213120 kb
Host smart-f3a50ce6-1d03-4a78-9b2d-d9b021a05919
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576400329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3576400329
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3899821469
Short name T67
Test name
Test status
Simulation time 202652533 ps
CPU time 0.81 seconds
Started Jul 01 04:26:43 PM PDT 24
Finished Jul 01 04:26:52 PM PDT 24
Peak memory 204636 kb
Host smart-38a9775a-de30-4f23-baf0-c52e098c6c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899821469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3899821469
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.481033608
Short name T84
Test name
Test status
Simulation time 6250253603 ps
CPU time 19.84 seconds
Started Jul 01 04:26:29 PM PDT 24
Finished Jul 01 04:26:57 PM PDT 24
Peak memory 204972 kb
Host smart-7bde3b0b-0468-4439-b057-baae91b7c6db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481033608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.481033608
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4225543283
Short name T102
Test name
Test status
Simulation time 1188247577 ps
CPU time 64.96 seconds
Started Jul 01 04:24:31 PM PDT 24
Finished Jul 01 04:25:45 PM PDT 24
Peak memory 212960 kb
Host smart-f8dcc401-747e-4109-b711-344d076a3b67
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225543283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.4225543283
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.712612122
Short name T66
Test name
Test status
Simulation time 12467229514 ps
CPU time 34.26 seconds
Started Jul 01 04:26:08 PM PDT 24
Finished Jul 01 04:26:53 PM PDT 24
Peak memory 213332 kb
Host smart-36358be8-3ffb-4976-8e1e-e568265647b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712612122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.712612122
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.3619307838
Short name T40
Test name
Test status
Simulation time 50376285 ps
CPU time 0.95 seconds
Started Jul 01 04:26:40 PM PDT 24
Finished Jul 01 04:26:49 PM PDT 24
Peak memory 215356 kb
Host smart-339abedd-3948-46c6-805c-252cf3171809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619307838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3619307838
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.4141186245
Short name T21
Test name
Test status
Simulation time 3073077104 ps
CPU time 4.97 seconds
Started Jul 01 04:26:10 PM PDT 24
Finished Jul 01 04:26:26 PM PDT 24
Peak memory 204996 kb
Host smart-fb9a5c44-5287-460d-87c6-207b3b965fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141186245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.4141186245
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2363909185
Short name T82
Test name
Test status
Simulation time 843924624 ps
CPU time 4.19 seconds
Started Jul 01 04:24:47 PM PDT 24
Finished Jul 01 04:24:55 PM PDT 24
Peak memory 213420 kb
Host smart-b81afc76-8c56-4a83-8559-993d416d4db9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363909185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2363909185
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.4235976189
Short name T12
Test name
Test status
Simulation time 5973669607 ps
CPU time 16.96 seconds
Started Jul 01 04:26:31 PM PDT 24
Finished Jul 01 04:26:55 PM PDT 24
Peak memory 204944 kb
Host smart-8cc5e7dc-63eb-4548-a227-73a96c4d250f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235976189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.4235976189
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1179052344
Short name T100
Test name
Test status
Simulation time 935159776 ps
CPU time 3.98 seconds
Started Jul 01 04:25:22 PM PDT 24
Finished Jul 01 04:25:37 PM PDT 24
Peak memory 204088 kb
Host smart-307096f2-3d0d-4c7e-8161-23b8307c0aad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179052344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1179052344
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.1914640803
Short name T22
Test name
Test status
Simulation time 12756255532 ps
CPU time 32.33 seconds
Started Jul 01 04:26:37 PM PDT 24
Finished Jul 01 04:27:18 PM PDT 24
Peak memory 213208 kb
Host smart-ac1ddce1-c238-4325-bbd2-2fc2ea1c2dc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914640803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1914640803
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3034195967
Short name T70
Test name
Test status
Simulation time 750552886 ps
CPU time 1.08 seconds
Started Jul 01 04:26:37 PM PDT 24
Finished Jul 01 04:26:46 PM PDT 24
Peak memory 236480 kb
Host smart-acd4ffd8-3c21-4075-a82d-59df2801d09e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034195967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3034195967
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1252323007
Short name T57
Test name
Test status
Simulation time 214463423 ps
CPU time 1.17 seconds
Started Jul 01 04:26:45 PM PDT 24
Finished Jul 01 04:26:54 PM PDT 24
Peak memory 205076 kb
Host smart-a097d91d-3a00-484b-ba7c-24f26d59984a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252323007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1252323007
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.2742399214
Short name T6
Test name
Test status
Simulation time 3489270201 ps
CPU time 4.23 seconds
Started Jul 01 04:26:54 PM PDT 24
Finished Jul 01 04:27:09 PM PDT 24
Peak memory 213208 kb
Host smart-40c83942-040c-42f4-89b3-0a167e0b5530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742399214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.2742399214
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2836759389
Short name T55
Test name
Test status
Simulation time 70176127 ps
CPU time 0.77 seconds
Started Jul 01 04:25:59 PM PDT 24
Finished Jul 01 04:26:12 PM PDT 24
Peak memory 212992 kb
Host smart-3ccf5eee-32dd-41d1-a8f8-bf91c60470a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836759389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2836759389
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1178826276
Short name T166
Test name
Test status
Simulation time 20077945797 ps
CPU time 21.75 seconds
Started Jul 01 04:25:05 PM PDT 24
Finished Jul 01 04:25:28 PM PDT 24
Peak memory 214132 kb
Host smart-d8325c54-db5a-431e-925b-6101932c3279
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178826276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
178826276
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.4276123934
Short name T144
Test name
Test status
Simulation time 10873435027 ps
CPU time 33.49 seconds
Started Jul 01 04:26:39 PM PDT 24
Finished Jul 01 04:27:20 PM PDT 24
Peak memory 213384 kb
Host smart-bf3f7db3-ebe1-4884-bb3e-484266979fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276123934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.4276123934
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.746545399
Short name T297
Test name
Test status
Simulation time 17100682131 ps
CPU time 50.23 seconds
Started Jul 01 04:26:04 PM PDT 24
Finished Jul 01 04:27:06 PM PDT 24
Peak memory 215260 kb
Host smart-dc7e1f1b-ac30-47d3-a36f-b12ed07b7021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746545399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.746545399
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1433196331
Short name T148
Test name
Test status
Simulation time 6929852469 ps
CPU time 17.77 seconds
Started Jul 01 04:26:17 PM PDT 24
Finished Jul 01 04:26:48 PM PDT 24
Peak memory 213332 kb
Host smart-e1f4d75f-6a79-4236-ab44-5c80bab50d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433196331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1433196331
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.2463145283
Short name T10
Test name
Test status
Simulation time 3410280635 ps
CPU time 3.87 seconds
Started Jul 01 04:26:29 PM PDT 24
Finished Jul 01 04:26:45 PM PDT 24
Peak memory 213268 kb
Host smart-94f01227-9b4f-4395-ac48-380f7c394ad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463145283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2463145283
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.3661637108
Short name T11
Test name
Test status
Simulation time 5386388387 ps
CPU time 15.17 seconds
Started Jul 01 04:26:57 PM PDT 24
Finished Jul 01 04:27:24 PM PDT 24
Peak memory 204896 kb
Host smart-cfe9bb5f-ab9f-4e1a-beae-ad8cb7dc80b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661637108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.3661637108
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1721387152
Short name T19
Test name
Test status
Simulation time 1159213727 ps
CPU time 2.53 seconds
Started Jul 01 04:26:00 PM PDT 24
Finished Jul 01 04:26:14 PM PDT 24
Peak memory 204948 kb
Host smart-78f541f8-af24-46b2-b3db-78d23598aad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721387152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1721387152
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.4235436
Short name T33
Test name
Test status
Simulation time 610035837 ps
CPU time 2.31 seconds
Started Jul 01 04:26:13 PM PDT 24
Finished Jul 01 04:26:28 PM PDT 24
Peak memory 204756 kb
Host smart-027f7cce-0df4-4326-ab12-d3bc95509456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.4235436
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2534106951
Short name T168
Test name
Test status
Simulation time 4888715953 ps
CPU time 19.75 seconds
Started Jul 01 04:24:54 PM PDT 24
Finished Jul 01 04:25:17 PM PDT 24
Peak memory 213196 kb
Host smart-cad3bfea-3780-47a6-b97a-a2c27d975800
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534106951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
534106951
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3187375725
Short name T160
Test name
Test status
Simulation time 27764513052 ps
CPU time 83.51 seconds
Started Jul 01 04:24:19 PM PDT 24
Finished Jul 01 04:25:48 PM PDT 24
Peak memory 220736 kb
Host smart-635961c5-d4c2-4f7d-a641-8f74f6cd5ce7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187375725 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3187375725
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3845466994
Short name T81
Test name
Test status
Simulation time 1395991688 ps
CPU time 3.91 seconds
Started Jul 01 04:24:32 PM PDT 24
Finished Jul 01 04:24:44 PM PDT 24
Peak memory 204496 kb
Host smart-ebfe5c6e-3e81-4f7f-bc79-893490760722
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845466994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3845466994
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.241017979
Short name T105
Test name
Test status
Simulation time 4581891384 ps
CPU time 12.79 seconds
Started Jul 01 04:24:32 PM PDT 24
Finished Jul 01 04:24:53 PM PDT 24
Peak memory 204872 kb
Host smart-fdf1be84-636a-47d8-95a0-115ed6c0df49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241017979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.241017979
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2051321360
Short name T29
Test name
Test status
Simulation time 76625804 ps
CPU time 0.86 seconds
Started Jul 01 04:26:05 PM PDT 24
Finished Jul 01 04:26:17 PM PDT 24
Peak memory 204708 kb
Host smart-591e1a9a-26ad-46c3-ac0e-279a2262e35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051321360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2051321360
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1165410138
Short name T372
Test name
Test status
Simulation time 5278086766 ps
CPU time 25.86 seconds
Started Jul 01 04:24:53 PM PDT 24
Finished Jul 01 04:25:23 PM PDT 24
Peak memory 213188 kb
Host smart-0bfd2dda-2f00-478f-953f-24bf280a3226
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165410138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
165410138
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2074899063
Short name T158
Test name
Test status
Simulation time 399077357 ps
CPU time 1.78 seconds
Started Jul 01 04:26:39 PM PDT 24
Finished Jul 01 04:26:49 PM PDT 24
Peak memory 204740 kb
Host smart-31072bc9-47bc-40d5-80af-2b7c22eb6371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074899063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2074899063
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.2685486083
Short name T178
Test name
Test status
Simulation time 5951216443 ps
CPU time 4.08 seconds
Started Jul 01 04:26:19 PM PDT 24
Finished Jul 01 04:26:35 PM PDT 24
Peak memory 204968 kb
Host smart-e2c2ab0c-6c2a-4269-a5e9-40a88b9c1a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685486083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2685486083
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2767921269
Short name T234
Test name
Test status
Simulation time 15283919557 ps
CPU time 18.12 seconds
Started Jul 01 04:26:23 PM PDT 24
Finished Jul 01 04:26:51 PM PDT 24
Peak memory 213328 kb
Host smart-45f9aec0-8504-493e-8d9b-08860d9eec14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767921269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2767921269
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.2916240755
Short name T91
Test name
Test status
Simulation time 9230205083 ps
CPU time 3.54 seconds
Started Jul 01 04:26:47 PM PDT 24
Finished Jul 01 04:27:00 PM PDT 24
Peak memory 213280 kb
Host smart-400cc2ab-ed2c-4942-9e5f-827e324bf525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916240755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2916240755
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.868548570
Short name T120
Test name
Test status
Simulation time 1265019024 ps
CPU time 66.25 seconds
Started Jul 01 04:24:24 PM PDT 24
Finished Jul 01 04:25:38 PM PDT 24
Peak memory 213320 kb
Host smart-bf1c1eb9-60df-4ffd-b559-b5c73542eabf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868548570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.868548570
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2304354517
Short name T409
Test name
Test status
Simulation time 2584798946 ps
CPU time 31.22 seconds
Started Jul 01 04:25:26 PM PDT 24
Finished Jul 01 04:26:10 PM PDT 24
Peak memory 211656 kb
Host smart-b9798cd5-e550-49b7-9378-ebbf98bce1fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304354517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2304354517
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3596549403
Short name T101
Test name
Test status
Simulation time 145816304 ps
CPU time 2.37 seconds
Started Jul 01 04:24:48 PM PDT 24
Finished Jul 01 04:24:55 PM PDT 24
Peak memory 213100 kb
Host smart-7361e7d6-253f-44af-bbd1-c684aa528362
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596549403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3596549403
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1256265333
Short name T90
Test name
Test status
Simulation time 3677144627 ps
CPU time 5.05 seconds
Started Jul 01 04:24:23 PM PDT 24
Finished Jul 01 04:24:37 PM PDT 24
Peak memory 221296 kb
Host smart-a77a4064-e18c-4c03-b402-159d037cedf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256265333 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1256265333
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3845702395
Short name T428
Test name
Test status
Simulation time 332094645 ps
CPU time 2.17 seconds
Started Jul 01 04:24:27 PM PDT 24
Finished Jul 01 04:24:38 PM PDT 24
Peak memory 212944 kb
Host smart-e492ebd1-d276-4d89-8368-1e506de28316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845702395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3845702395
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.4237683306
Short name T417
Test name
Test status
Simulation time 36818976483 ps
CPU time 59.36 seconds
Started Jul 01 04:24:27 PM PDT 24
Finished Jul 01 04:25:35 PM PDT 24
Peak memory 204784 kb
Host smart-e4e0f2ff-809c-4acd-bda9-333e68020773
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237683306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.4237683306
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3026723381
Short name T318
Test name
Test status
Simulation time 18517613236 ps
CPU time 30.51 seconds
Started Jul 01 04:24:15 PM PDT 24
Finished Jul 01 04:24:50 PM PDT 24
Peak memory 204724 kb
Host smart-25b5a752-ed5a-487c-ae0f-96ff524f6391
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026723381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.3026723381
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3641370845
Short name T373
Test name
Test status
Simulation time 2043399639 ps
CPU time 5.98 seconds
Started Jul 01 04:24:27 PM PDT 24
Finished Jul 01 04:24:43 PM PDT 24
Peak memory 204688 kb
Host smart-a15288ae-37be-45f0-8678-3e3a87e2c04e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641370845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3641370845
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.246873143
Short name T368
Test name
Test status
Simulation time 4411728738 ps
CPU time 4.07 seconds
Started Jul 01 04:24:27 PM PDT 24
Finished Jul 01 04:24:40 PM PDT 24
Peak memory 204700 kb
Host smart-1e114a04-8ebd-4d98-9e75-ce5cf7e7e66d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246873143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.246873143
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.403797900
Short name T352
Test name
Test status
Simulation time 10556960314 ps
CPU time 15.35 seconds
Started Jul 01 04:25:52 PM PDT 24
Finished Jul 01 04:26:19 PM PDT 24
Peak memory 204672 kb
Host smart-f7691066-556d-4282-b9df-6cf0d505f62a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403797900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.403797900
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.604741746
Short name T310
Test name
Test status
Simulation time 1003787159 ps
CPU time 3.12 seconds
Started Jul 01 04:25:51 PM PDT 24
Finished Jul 01 04:26:05 PM PDT 24
Peak memory 204436 kb
Host smart-21efa203-a779-4d9e-8797-83dfacffe8c9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604741746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_hw_reset.604741746
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1248158027
Short name T397
Test name
Test status
Simulation time 166195186 ps
CPU time 0.85 seconds
Started Jul 01 04:25:52 PM PDT 24
Finished Jul 01 04:26:05 PM PDT 24
Peak memory 204436 kb
Host smart-aa2f4437-27f8-4e18-81b2-e465ae2cf02d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248158027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
248158027
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1914130994
Short name T364
Test name
Test status
Simulation time 35825466 ps
CPU time 0.71 seconds
Started Jul 01 04:24:25 PM PDT 24
Finished Jul 01 04:24:36 PM PDT 24
Peak memory 204488 kb
Host smart-856ecf3e-f046-4646-9aee-31a975ea4ec8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914130994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1914130994
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3918649179
Short name T349
Test name
Test status
Simulation time 182992457 ps
CPU time 0.8 seconds
Started Jul 01 04:24:19 PM PDT 24
Finished Jul 01 04:24:25 PM PDT 24
Peak memory 204736 kb
Host smart-44b67743-48ab-4b01-9e64-48c869feb12f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918649179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3918649179
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1267995306
Short name T111
Test name
Test status
Simulation time 473448564 ps
CPU time 3.59 seconds
Started Jul 01 04:24:25 PM PDT 24
Finished Jul 01 04:24:38 PM PDT 24
Peak memory 204860 kb
Host smart-dd741183-db23-4bfe-b4f7-53d0fb67c9e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267995306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1267995306
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.442649571
Short name T389
Test name
Test status
Simulation time 293899851 ps
CPU time 2.75 seconds
Started Jul 01 04:24:25 PM PDT 24
Finished Jul 01 04:24:36 PM PDT 24
Peak memory 213064 kb
Host smart-c628c17d-4647-469a-8e24-94a5e40c2ac4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442649571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.442649571
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3420746967
Short name T164
Test name
Test status
Simulation time 1619224125 ps
CPU time 9.69 seconds
Started Jul 01 04:25:26 PM PDT 24
Finished Jul 01 04:25:49 PM PDT 24
Peak memory 211404 kb
Host smart-ad5885ae-21e8-4ac9-84b5-cb1024be7f1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420746967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3420746967
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3301006976
Short name T398
Test name
Test status
Simulation time 4579589356 ps
CPU time 76.65 seconds
Started Jul 01 04:24:43 PM PDT 24
Finished Jul 01 04:26:05 PM PDT 24
Peak memory 213356 kb
Host smart-59d2e04c-7e4d-44a4-a9ec-f3d14df406e6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301006976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3301006976
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3556219938
Short name T109
Test name
Test status
Simulation time 1476968660 ps
CPU time 27.65 seconds
Started Jul 01 04:24:24 PM PDT 24
Finished Jul 01 04:24:59 PM PDT 24
Peak memory 204820 kb
Host smart-fdbe4017-1370-4da4-8516-e40b04677cd3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556219938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3556219938
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1709047892
Short name T382
Test name
Test status
Simulation time 170605941 ps
CPU time 1.56 seconds
Started Jul 01 04:24:25 PM PDT 24
Finished Jul 01 04:24:36 PM PDT 24
Peak memory 213008 kb
Host smart-c1f4091b-bb83-4117-b060-28ea1c37720f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709047892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1709047892
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3314753511
Short name T405
Test name
Test status
Simulation time 143964069 ps
CPU time 2.56 seconds
Started Jul 01 04:24:20 PM PDT 24
Finished Jul 01 04:24:28 PM PDT 24
Peak memory 221580 kb
Host smart-1098136e-0ff6-433b-8b0b-41a727a42cc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314753511 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3314753511
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.4036754010
Short name T93
Test name
Test status
Simulation time 133226420 ps
CPU time 1.43 seconds
Started Jul 01 04:24:26 PM PDT 24
Finished Jul 01 04:24:37 PM PDT 24
Peak memory 212992 kb
Host smart-04ae3c49-dcd3-4fcc-ac8b-fac3c0888afa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036754010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.4036754010
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2689223088
Short name T371
Test name
Test status
Simulation time 28161438177 ps
CPU time 80.29 seconds
Started Jul 01 04:24:20 PM PDT 24
Finished Jul 01 04:25:47 PM PDT 24
Peak memory 205024 kb
Host smart-0dd2b6ca-f6ee-400f-9ac3-0ba546bfda23
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689223088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2689223088
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1149640197
Short name T406
Test name
Test status
Simulation time 32508400 ps
CPU time 0.74 seconds
Started Jul 01 04:24:35 PM PDT 24
Finished Jul 01 04:24:42 PM PDT 24
Peak memory 204480 kb
Host smart-8ecbc976-6338-4d61-9938-ceb0315cfc5d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149640197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1149640197
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1677081793
Short name T410
Test name
Test status
Simulation time 3203989282 ps
CPU time 5.51 seconds
Started Jul 01 04:24:25 PM PDT 24
Finished Jul 01 04:24:39 PM PDT 24
Peak memory 204724 kb
Host smart-88ba95a2-6742-4cb0-8614-3e704c356f10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677081793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
677081793
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2100994187
Short name T305
Test name
Test status
Simulation time 2405401234 ps
CPU time 6.78 seconds
Started Jul 01 04:25:52 PM PDT 24
Finished Jul 01 04:26:11 PM PDT 24
Peak memory 204496 kb
Host smart-102a861c-e469-4733-9691-8699edf25767
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100994187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2100994187
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2174320302
Short name T393
Test name
Test status
Simulation time 8619658896 ps
CPU time 23.23 seconds
Started Jul 01 04:24:19 PM PDT 24
Finished Jul 01 04:24:49 PM PDT 24
Peak memory 204728 kb
Host smart-ff8ccbb2-e88a-4735-8d2d-1dc096f9da43
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174320302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2174320302
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3723603761
Short name T362
Test name
Test status
Simulation time 317622279 ps
CPU time 1.47 seconds
Started Jul 01 04:24:24 PM PDT 24
Finished Jul 01 04:24:33 PM PDT 24
Peak memory 204432 kb
Host smart-4c5f14d7-0ef3-43ec-83fd-8b7b02bcf07f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723603761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3723603761
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.169219758
Short name T335
Test name
Test status
Simulation time 494253179 ps
CPU time 1.01 seconds
Started Jul 01 04:25:26 PM PDT 24
Finished Jul 01 04:25:40 PM PDT 24
Peak memory 203000 kb
Host smart-632a0f4a-cdff-4783-92f3-bb8508b691ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169219758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.169219758
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.290990687
Short name T427
Test name
Test status
Simulation time 60007201 ps
CPU time 0.73 seconds
Started Jul 01 04:24:30 PM PDT 24
Finished Jul 01 04:24:39 PM PDT 24
Peak memory 204772 kb
Host smart-5ef1d9ea-64cc-4a3a-981a-797f99c36965
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290990687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.290990687
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.717070601
Short name T392
Test name
Test status
Simulation time 47972058 ps
CPU time 0.7 seconds
Started Jul 01 04:24:24 PM PDT 24
Finished Jul 01 04:24:33 PM PDT 24
Peak memory 204292 kb
Host smart-c5a987c9-8c77-4201-bfc1-159523f3d117
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717070601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.717070601
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1232036951
Short name T128
Test name
Test status
Simulation time 1127798355 ps
CPU time 8.09 seconds
Started Jul 01 04:24:28 PM PDT 24
Finished Jul 01 04:24:45 PM PDT 24
Peak memory 204856 kb
Host smart-b7c3e508-ca07-4b1f-a3a3-93553189bd3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232036951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1232036951
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.4180940194
Short name T355
Test name
Test status
Simulation time 233983786 ps
CPU time 3.95 seconds
Started Jul 01 04:24:32 PM PDT 24
Finished Jul 01 04:24:44 PM PDT 24
Peak memory 213068 kb
Host smart-7c4fbf43-0146-4b26-867a-9b803ae57512
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180940194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.4180940194
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.467082324
Short name T175
Test name
Test status
Simulation time 3609700277 ps
CPU time 17.54 seconds
Started Jul 01 04:24:22 PM PDT 24
Finished Jul 01 04:24:46 PM PDT 24
Peak memory 213116 kb
Host smart-6bdf609f-b8ab-4dd9-9e66-a85778783b8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467082324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.467082324
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3241633503
Short name T353
Test name
Test status
Simulation time 105732677 ps
CPU time 2.16 seconds
Started Jul 01 04:24:47 PM PDT 24
Finished Jul 01 04:24:58 PM PDT 24
Peak memory 216224 kb
Host smart-46524a77-505d-4a78-a422-a1bf8413a13a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241633503 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3241633503
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2931311500
Short name T119
Test name
Test status
Simulation time 170489017 ps
CPU time 1.65 seconds
Started Jul 01 04:24:46 PM PDT 24
Finished Jul 01 04:24:52 PM PDT 24
Peak memory 213048 kb
Host smart-d7304406-b5df-4818-a985-13cd6e09f58f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931311500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2931311500
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.722927875
Short name T346
Test name
Test status
Simulation time 66544413556 ps
CPU time 191.08 seconds
Started Jul 01 04:24:34 PM PDT 24
Finished Jul 01 04:27:52 PM PDT 24
Peak memory 204748 kb
Host smart-1108da60-b3d9-402e-85ba-c5d26ac81d1c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722927875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rv_dm_jtag_dmi_csr_bit_bash.722927875
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3487260802
Short name T298
Test name
Test status
Simulation time 1374594629 ps
CPU time 3.32 seconds
Started Jul 01 04:24:45 PM PDT 24
Finished Jul 01 04:24:53 PM PDT 24
Peak memory 204688 kb
Host smart-b839953a-97fe-41f0-9c09-c5ade4bcee2c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487260802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3487260802
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4274894832
Short name T326
Test name
Test status
Simulation time 299996829 ps
CPU time 1.14 seconds
Started Jul 01 04:24:41 PM PDT 24
Finished Jul 01 04:24:47 PM PDT 24
Peak memory 204484 kb
Host smart-ca85c375-fb7c-4e06-88a2-c7672d43d6ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274894832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
4274894832
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3582368993
Short name T381
Test name
Test status
Simulation time 352328754 ps
CPU time 4.39 seconds
Started Jul 01 04:24:48 PM PDT 24
Finished Jul 01 04:24:57 PM PDT 24
Peak memory 205072 kb
Host smart-dda641ac-53ab-4ad2-bd9c-be0e03973002
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582368993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3582368993
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3891786967
Short name T341
Test name
Test status
Simulation time 1029983227 ps
CPU time 3.48 seconds
Started Jul 01 04:24:49 PM PDT 24
Finished Jul 01 04:24:57 PM PDT 24
Peak memory 213132 kb
Host smart-bdc7e58c-a93a-4a36-911d-91667480f6f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891786967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3891786967
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2915000942
Short name T172
Test name
Test status
Simulation time 2112703708 ps
CPU time 9.77 seconds
Started Jul 01 04:24:53 PM PDT 24
Finished Jul 01 04:25:07 PM PDT 24
Peak memory 213084 kb
Host smart-93176fd1-3ca4-4e67-99aa-ef6e564c8371
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915000942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
915000942
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2344277916
Short name T413
Test name
Test status
Simulation time 1293111118 ps
CPU time 4.58 seconds
Started Jul 01 04:24:58 PM PDT 24
Finished Jul 01 04:25:05 PM PDT 24
Peak memory 221560 kb
Host smart-f1d01aeb-c94a-44a1-9c21-82f57db362fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344277916 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2344277916
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2279497442
Short name T118
Test name
Test status
Simulation time 102009115 ps
CPU time 2.49 seconds
Started Jul 01 04:24:39 PM PDT 24
Finished Jul 01 04:24:52 PM PDT 24
Peak memory 213212 kb
Host smart-8fef5eca-f8c0-43d6-a675-48cba07cc6ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279497442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2279497442
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3554759435
Short name T316
Test name
Test status
Simulation time 4091859279 ps
CPU time 10.32 seconds
Started Jul 01 04:24:41 PM PDT 24
Finished Jul 01 04:24:57 PM PDT 24
Peak memory 204728 kb
Host smart-18e51913-9ee3-4429-be63-54672b252514
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554759435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3554759435
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1221229609
Short name T331
Test name
Test status
Simulation time 1209900641 ps
CPU time 3.08 seconds
Started Jul 01 04:24:45 PM PDT 24
Finished Jul 01 04:24:53 PM PDT 24
Peak memory 204688 kb
Host smart-1e43b0df-50ab-4a19-92bd-3405348f5d95
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221229609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1221229609
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.79759943
Short name T344
Test name
Test status
Simulation time 411356740 ps
CPU time 0.83 seconds
Started Jul 01 04:24:48 PM PDT 24
Finished Jul 01 04:24:53 PM PDT 24
Peak memory 204736 kb
Host smart-f34e3284-58ee-4a6a-bf91-87c1a1ef7672
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79759943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.79759943
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.896359066
Short name T127
Test name
Test status
Simulation time 164396015 ps
CPU time 6.52 seconds
Started Jul 01 04:24:38 PM PDT 24
Finished Jul 01 04:24:50 PM PDT 24
Peak memory 204892 kb
Host smart-89d62a52-86cb-4093-ac23-8b51e59bc08f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896359066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.896359066
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2360348924
Short name T320
Test name
Test status
Simulation time 1066542370 ps
CPU time 5.48 seconds
Started Jul 01 04:25:04 PM PDT 24
Finished Jul 01 04:25:11 PM PDT 24
Peak memory 213100 kb
Host smart-0d8582bb-24cc-44ac-935b-fe90f70cbbf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360348924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2360348924
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3918717493
Short name T167
Test name
Test status
Simulation time 863530212 ps
CPU time 8.15 seconds
Started Jul 01 04:24:48 PM PDT 24
Finished Jul 01 04:25:00 PM PDT 24
Peak memory 213088 kb
Host smart-cfd03a1c-1008-4777-9ec1-b97e52e98a09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918717493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
918717493
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1236643182
Short name T337
Test name
Test status
Simulation time 282140319 ps
CPU time 2.57 seconds
Started Jul 01 04:24:41 PM PDT 24
Finished Jul 01 04:24:48 PM PDT 24
Peak memory 221364 kb
Host smart-fcada19c-1815-4419-a23c-d78ad003e496
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236643182 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1236643182
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3049697672
Short name T97
Test name
Test status
Simulation time 232351925 ps
CPU time 2.27 seconds
Started Jul 01 04:24:53 PM PDT 24
Finished Jul 01 04:25:00 PM PDT 24
Peak memory 212996 kb
Host smart-2c057933-e4bf-4af0-a59e-2379bdee1172
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049697672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3049697672
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3128522944
Short name T338
Test name
Test status
Simulation time 37501647933 ps
CPU time 41.86 seconds
Started Jul 01 04:24:48 PM PDT 24
Finished Jul 01 04:25:34 PM PDT 24
Peak memory 205020 kb
Host smart-3aca0449-ca20-4793-8247-e4755778100d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128522944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3128522944
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.272988323
Short name T339
Test name
Test status
Simulation time 1046077685 ps
CPU time 1.08 seconds
Started Jul 01 04:24:48 PM PDT 24
Finished Jul 01 04:24:54 PM PDT 24
Peak memory 204668 kb
Host smart-527d52ad-8c51-4588-bff5-f93770277157
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272988323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.272988323
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1768819733
Short name T79
Test name
Test status
Simulation time 206282712 ps
CPU time 0.86 seconds
Started Jul 01 04:24:41 PM PDT 24
Finished Jul 01 04:24:47 PM PDT 24
Peak memory 204720 kb
Host smart-49635882-aa0a-4f20-a6cf-ff816e1ea953
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768819733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1768819733
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1648287800
Short name T114
Test name
Test status
Simulation time 317251787 ps
CPU time 3.72 seconds
Started Jul 01 04:24:40 PM PDT 24
Finished Jul 01 04:24:53 PM PDT 24
Peak memory 205088 kb
Host smart-059ac53a-30e1-4ddd-919c-1995ee1ad72f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648287800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1648287800
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2734241198
Short name T430
Test name
Test status
Simulation time 115440618 ps
CPU time 2.33 seconds
Started Jul 01 04:24:43 PM PDT 24
Finished Jul 01 04:24:50 PM PDT 24
Peak memory 213108 kb
Host smart-cc8d83ba-0955-4c7d-aae5-21b50e10aaaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734241198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2734241198
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2747264771
Short name T165
Test name
Test status
Simulation time 2808006364 ps
CPU time 14.05 seconds
Started Jul 01 04:24:53 PM PDT 24
Finished Jul 01 04:25:11 PM PDT 24
Peak memory 213180 kb
Host smart-2a211c7b-8e54-4619-84cd-af3cd356e7b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747264771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
747264771
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.738475699
Short name T396
Test name
Test status
Simulation time 5776733644 ps
CPU time 5.58 seconds
Started Jul 01 04:24:55 PM PDT 24
Finished Jul 01 04:25:04 PM PDT 24
Peak memory 221060 kb
Host smart-45ffeb02-ba00-4db8-8ba8-7bba94bcadcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738475699 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.738475699
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.91072489
Short name T117
Test name
Test status
Simulation time 91308940 ps
CPU time 1.58 seconds
Started Jul 01 04:24:41 PM PDT 24
Finished Jul 01 04:24:47 PM PDT 24
Peak memory 213000 kb
Host smart-bd5beec0-919f-4f94-b7ff-904566741f0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91072489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.91072489
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.4016632141
Short name T314
Test name
Test status
Simulation time 40344519648 ps
CPU time 70.61 seconds
Started Jul 01 04:24:46 PM PDT 24
Finished Jul 01 04:26:01 PM PDT 24
Peak memory 204748 kb
Host smart-ac7960cb-30ff-470d-a8b9-f62e8f52efa6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016632141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.4016632141
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3669863047
Short name T407
Test name
Test status
Simulation time 10050472232 ps
CPU time 13.35 seconds
Started Jul 01 04:24:49 PM PDT 24
Finished Jul 01 04:25:07 PM PDT 24
Peak memory 204740 kb
Host smart-dd15340b-c187-4e5d-9a82-0818b72049ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669863047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3669863047
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1276386468
Short name T436
Test name
Test status
Simulation time 210415688 ps
CPU time 0.85 seconds
Started Jul 01 04:24:52 PM PDT 24
Finished Jul 01 04:24:57 PM PDT 24
Peak memory 204492 kb
Host smart-690c7bc4-e2ad-42fe-b0ab-127b65003f41
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276386468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1276386468
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2042800723
Short name T441
Test name
Test status
Simulation time 322305975 ps
CPU time 6.65 seconds
Started Jul 01 04:24:52 PM PDT 24
Finished Jul 01 04:25:03 PM PDT 24
Peak memory 204856 kb
Host smart-2208d769-afb9-4b9c-8a80-d35bccc13f47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042800723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2042800723
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1009270080
Short name T163
Test name
Test status
Simulation time 809025438 ps
CPU time 8.66 seconds
Started Jul 01 04:24:35 PM PDT 24
Finished Jul 01 04:24:50 PM PDT 24
Peak memory 213080 kb
Host smart-09827c55-30d1-41ea-a2a3-03e216aa4fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009270080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
009270080
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.691677303
Short name T87
Test name
Test status
Simulation time 2811328663 ps
CPU time 5.49 seconds
Started Jul 01 04:24:43 PM PDT 24
Finished Jul 01 04:24:53 PM PDT 24
Peak memory 221380 kb
Host smart-a377422c-89df-466a-9c8b-7917f1516e22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691677303 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.691677303
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2746357439
Short name T121
Test name
Test status
Simulation time 125683405 ps
CPU time 1.47 seconds
Started Jul 01 04:24:59 PM PDT 24
Finished Jul 01 04:25:02 PM PDT 24
Peak memory 212928 kb
Host smart-099744df-7114-4794-b777-8e0f4eb5b4cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746357439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2746357439
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4251139120
Short name T418
Test name
Test status
Simulation time 13366057531 ps
CPU time 10.24 seconds
Started Jul 01 04:25:03 PM PDT 24
Finished Jul 01 04:25:15 PM PDT 24
Peak memory 204728 kb
Host smart-482ee482-7392-4f23-9eb2-68962fdde687
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251139120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.4251139120
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4190954063
Short name T358
Test name
Test status
Simulation time 2308930828 ps
CPU time 7.21 seconds
Started Jul 01 04:24:48 PM PDT 24
Finished Jul 01 04:24:59 PM PDT 24
Peak memory 204704 kb
Host smart-48691da7-fcdd-4235-b284-d9bed0a4d8ff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190954063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
4190954063
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1812402470
Short name T303
Test name
Test status
Simulation time 406052375 ps
CPU time 1.54 seconds
Started Jul 01 04:24:48 PM PDT 24
Finished Jul 01 04:24:54 PM PDT 24
Peak memory 204484 kb
Host smart-018f1d1f-1e0b-4d91-935b-887c15d81b90
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812402470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1812402470
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.91726857
Short name T356
Test name
Test status
Simulation time 314184810 ps
CPU time 3.32 seconds
Started Jul 01 04:24:49 PM PDT 24
Finished Jul 01 04:24:57 PM PDT 24
Peak memory 204836 kb
Host smart-fe6122a4-790e-4610-afca-fe653f8a288c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91726857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_c
sr_outstanding.91726857
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.765211103
Short name T330
Test name
Test status
Simulation time 77826238 ps
CPU time 2.99 seconds
Started Jul 01 04:24:48 PM PDT 24
Finished Jul 01 04:24:56 PM PDT 24
Peak memory 213140 kb
Host smart-921c9b55-3109-4ce6-87d1-2137ad0c88a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765211103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.765211103
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.425701902
Short name T408
Test name
Test status
Simulation time 1815183070 ps
CPU time 19.12 seconds
Started Jul 01 04:24:53 PM PDT 24
Finished Jul 01 04:25:16 PM PDT 24
Peak memory 213068 kb
Host smart-19fd1b0e-0692-4d41-9ef5-af6234c98de4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425701902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.425701902
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3315607963
Short name T134
Test name
Test status
Simulation time 312234841 ps
CPU time 2.71 seconds
Started Jul 01 04:25:03 PM PDT 24
Finished Jul 01 04:25:08 PM PDT 24
Peak memory 214948 kb
Host smart-db5eed32-1efd-460b-a3ec-15509df03ef6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315607963 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3315607963
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.920096005
Short name T415
Test name
Test status
Simulation time 51643265 ps
CPU time 1.45 seconds
Started Jul 01 04:25:18 PM PDT 24
Finished Jul 01 04:25:29 PM PDT 24
Peak memory 213004 kb
Host smart-7b12b8ce-77b3-4ab5-86de-73552ecf8061
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920096005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.920096005
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3670803621
Short name T390
Test name
Test status
Simulation time 6119486920 ps
CPU time 7.68 seconds
Started Jul 01 04:24:44 PM PDT 24
Finished Jul 01 04:24:56 PM PDT 24
Peak memory 205032 kb
Host smart-03d6601d-1117-414c-9074-02f8bfe740ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670803621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.3670803621
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1802442211
Short name T300
Test name
Test status
Simulation time 6322164951 ps
CPU time 9.07 seconds
Started Jul 01 04:24:54 PM PDT 24
Finished Jul 01 04:25:07 PM PDT 24
Peak memory 204016 kb
Host smart-e41099b3-57e5-46e6-8e15-7d711d6c7676
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802442211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1802442211
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4264532032
Short name T311
Test name
Test status
Simulation time 223338358 ps
CPU time 1.25 seconds
Started Jul 01 04:24:44 PM PDT 24
Finished Jul 01 04:24:49 PM PDT 24
Peak memory 204728 kb
Host smart-2ff54dbf-4069-496a-881c-c1f68b8fd6fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264532032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
4264532032
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3193160483
Short name T126
Test name
Test status
Simulation time 1356693454 ps
CPU time 7.15 seconds
Started Jul 01 04:24:58 PM PDT 24
Finished Jul 01 04:25:08 PM PDT 24
Peak memory 204864 kb
Host smart-a8588829-5f27-44fb-b207-a0392d8280de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193160483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3193160483
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3129115947
Short name T209
Test name
Test status
Simulation time 199267815 ps
CPU time 3.76 seconds
Started Jul 01 04:24:56 PM PDT 24
Finished Jul 01 04:25:03 PM PDT 24
Peak memory 213128 kb
Host smart-e63b8af6-154b-43f6-ac42-65c78ca1bef7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129115947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3129115947
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1275522650
Short name T432
Test name
Test status
Simulation time 3592702455 ps
CPU time 5.71 seconds
Started Jul 01 04:24:56 PM PDT 24
Finished Jul 01 04:25:05 PM PDT 24
Peak memory 221344 kb
Host smart-9d055a58-c331-49f5-809f-d94fc942c5e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275522650 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1275522650
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3933737003
Short name T414
Test name
Test status
Simulation time 47716143 ps
CPU time 2.06 seconds
Started Jul 01 04:24:54 PM PDT 24
Finished Jul 01 04:25:00 PM PDT 24
Peak memory 212984 kb
Host smart-5f761a48-997b-4a13-8202-110fed870e3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933737003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3933737003
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.744264730
Short name T435
Test name
Test status
Simulation time 14665274215 ps
CPU time 7.07 seconds
Started Jul 01 04:24:49 PM PDT 24
Finished Jul 01 04:25:01 PM PDT 24
Peak memory 204728 kb
Host smart-b50160a0-b7de-4010-b1a6-2c802ff2ba6b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744264730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
rv_dm_jtag_dmi_csr_bit_bash.744264730
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3832246916
Short name T302
Test name
Test status
Simulation time 13040236116 ps
CPU time 20.14 seconds
Started Jul 01 04:24:43 PM PDT 24
Finished Jul 01 04:25:08 PM PDT 24
Peak memory 205024 kb
Host smart-a0499a1e-950f-47e7-801c-731d0cdeb74e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832246916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3832246916
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.883388354
Short name T423
Test name
Test status
Simulation time 456282491 ps
CPU time 1.24 seconds
Started Jul 01 04:24:48 PM PDT 24
Finished Jul 01 04:24:54 PM PDT 24
Peak memory 204488 kb
Host smart-b5de03cd-aa12-4353-81c4-917781458c33
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883388354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.883388354
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.218548701
Short name T112
Test name
Test status
Simulation time 593349027 ps
CPU time 6.04 seconds
Started Jul 01 04:24:47 PM PDT 24
Finished Jul 01 04:24:57 PM PDT 24
Peak memory 204936 kb
Host smart-026e96e3-04c6-4689-8e72-bfbee1421b77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218548701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.218548701
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1679685019
Short name T433
Test name
Test status
Simulation time 2569072759 ps
CPU time 3.37 seconds
Started Jul 01 04:24:50 PM PDT 24
Finished Jul 01 04:24:57 PM PDT 24
Peak memory 213160 kb
Host smart-fee2cbe6-d21f-4edf-bd42-999231210d06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679685019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1679685019
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3324495255
Short name T68
Test name
Test status
Simulation time 1965166202 ps
CPU time 5.56 seconds
Started Jul 01 04:24:55 PM PDT 24
Finished Jul 01 04:25:04 PM PDT 24
Peak memory 219648 kb
Host smart-99af0451-4528-4348-a21b-1e062d4f0203
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324495255 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3324495255
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.102401103
Short name T122
Test name
Test status
Simulation time 99859012 ps
CPU time 1.45 seconds
Started Jul 01 04:24:56 PM PDT 24
Finished Jul 01 04:25:01 PM PDT 24
Peak memory 212968 kb
Host smart-a6bef8c1-365c-459f-824a-cd7f4180437b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102401103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.102401103
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1423363481
Short name T377
Test name
Test status
Simulation time 4811910765 ps
CPU time 4.63 seconds
Started Jul 01 04:25:04 PM PDT 24
Finished Jul 01 04:25:11 PM PDT 24
Peak memory 204960 kb
Host smart-9404b036-17cf-4fbd-b41c-ea08be4ada32
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423363481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.1423363481
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.436011953
Short name T376
Test name
Test status
Simulation time 1284823357 ps
CPU time 1.68 seconds
Started Jul 01 04:25:12 PM PDT 24
Finished Jul 01 04:25:19 PM PDT 24
Peak memory 204680 kb
Host smart-a4a089e8-147b-41cd-9b63-fdeccd539b50
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436011953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.436011953
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.346594092
Short name T431
Test name
Test status
Simulation time 1248263061 ps
CPU time 2.48 seconds
Started Jul 01 04:24:58 PM PDT 24
Finished Jul 01 04:25:03 PM PDT 24
Peak memory 204484 kb
Host smart-0bffa049-e865-4371-95da-08453a568e2a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346594092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.346594092
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1433846135
Short name T437
Test name
Test status
Simulation time 870393980 ps
CPU time 7.26 seconds
Started Jul 01 04:24:52 PM PDT 24
Finished Jul 01 04:25:03 PM PDT 24
Peak memory 204884 kb
Host smart-4ec011b2-4e92-4930-be8a-5e3d2c963d1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433846135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1433846135
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.793602781
Short name T161
Test name
Test status
Simulation time 377444007 ps
CPU time 5 seconds
Started Jul 01 04:25:01 PM PDT 24
Finished Jul 01 04:25:08 PM PDT 24
Peak memory 212988 kb
Host smart-2da30250-ff38-4154-a9e1-c6e8f2c440e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793602781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.793602781
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1623877424
Short name T89
Test name
Test status
Simulation time 2972994834 ps
CPU time 16.41 seconds
Started Jul 01 04:25:00 PM PDT 24
Finished Jul 01 04:25:18 PM PDT 24
Peak memory 213424 kb
Host smart-90a710f7-ea7e-4402-b5cc-8b0c23e635f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623877424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
623877424
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.634364500
Short name T424
Test name
Test status
Simulation time 5626684054 ps
CPU time 11.07 seconds
Started Jul 01 04:25:01 PM PDT 24
Finished Jul 01 04:25:13 PM PDT 24
Peak memory 221368 kb
Host smart-ef6efe25-a858-4bdb-962b-ff8e5a708e7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634364500 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.634364500
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2424504936
Short name T123
Test name
Test status
Simulation time 185125604 ps
CPU time 1.51 seconds
Started Jul 01 04:25:10 PM PDT 24
Finished Jul 01 04:25:16 PM PDT 24
Peak memory 213000 kb
Host smart-3b9babc8-87bb-4bff-acf9-53b0b3f2e990
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424504936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2424504936
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1848635544
Short name T357
Test name
Test status
Simulation time 6763901933 ps
CPU time 18.2 seconds
Started Jul 01 04:24:54 PM PDT 24
Finished Jul 01 04:25:16 PM PDT 24
Peak memory 204636 kb
Host smart-f71ad712-0a62-4267-be7f-5c759f9f5699
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848635544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.1848635544
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2739116485
Short name T367
Test name
Test status
Simulation time 3778123892 ps
CPU time 10.45 seconds
Started Jul 01 04:24:51 PM PDT 24
Finished Jul 01 04:25:06 PM PDT 24
Peak memory 204740 kb
Host smart-d9a22f91-c5eb-4980-8fdb-abf406f2b4a6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739116485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2739116485
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2483770598
Short name T384
Test name
Test status
Simulation time 513302437 ps
CPU time 1.01 seconds
Started Jul 01 04:25:08 PM PDT 24
Finished Jul 01 04:25:12 PM PDT 24
Peak memory 204484 kb
Host smart-2c9498e9-0572-4153-ad99-0c401a28813c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483770598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2483770598
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2942730785
Short name T125
Test name
Test status
Simulation time 2063284305 ps
CPU time 7.97 seconds
Started Jul 01 04:24:55 PM PDT 24
Finished Jul 01 04:25:06 PM PDT 24
Peak memory 204860 kb
Host smart-05627172-0bcc-4174-bb89-ed75ebc5b1ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942730785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2942730785
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2688752595
Short name T438
Test name
Test status
Simulation time 261221929 ps
CPU time 3.58 seconds
Started Jul 01 04:25:19 PM PDT 24
Finished Jul 01 04:25:32 PM PDT 24
Peak memory 213060 kb
Host smart-37907051-d869-4f9c-b11f-bca4c2f493e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688752595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2688752595
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3817336380
Short name T169
Test name
Test status
Simulation time 1259133021 ps
CPU time 12.03 seconds
Started Jul 01 04:25:08 PM PDT 24
Finished Jul 01 04:25:23 PM PDT 24
Peak memory 213472 kb
Host smart-8c091a35-f6d5-49dc-a5d1-caaff28d27f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817336380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
817336380
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3725712665
Short name T370
Test name
Test status
Simulation time 3622292914 ps
CPU time 8.7 seconds
Started Jul 01 04:25:06 PM PDT 24
Finished Jul 01 04:25:16 PM PDT 24
Peak memory 220560 kb
Host smart-cfc60d46-d606-42ba-b1be-b480dced75dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725712665 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3725712665
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.328645779
Short name T323
Test name
Test status
Simulation time 130031153 ps
CPU time 1.58 seconds
Started Jul 01 04:25:05 PM PDT 24
Finished Jul 01 04:25:09 PM PDT 24
Peak memory 213280 kb
Host smart-b04251d1-d0c3-4b19-8489-580cf39f4be2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328645779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.328645779
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1883721319
Short name T342
Test name
Test status
Simulation time 18885954597 ps
CPU time 50.85 seconds
Started Jul 01 04:24:59 PM PDT 24
Finished Jul 01 04:25:52 PM PDT 24
Peak memory 204984 kb
Host smart-73d2475d-0328-4d21-b5ca-300dbeb87a41
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883721319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.1883721319
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.214200021
Short name T366
Test name
Test status
Simulation time 2505528540 ps
CPU time 4.46 seconds
Started Jul 01 04:24:57 PM PDT 24
Finished Jul 01 04:25:04 PM PDT 24
Peak memory 204736 kb
Host smart-63d4b13f-6b00-4c63-a688-b7957b0a966f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214200021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.214200021
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2798652508
Short name T440
Test name
Test status
Simulation time 782796078 ps
CPU time 1.76 seconds
Started Jul 01 04:24:57 PM PDT 24
Finished Jul 01 04:25:02 PM PDT 24
Peak memory 204724 kb
Host smart-cfa22536-1a1b-4fcc-9833-a9871e9c3431
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798652508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2798652508
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1333375672
Short name T110
Test name
Test status
Simulation time 888407041 ps
CPU time 8.2 seconds
Started Jul 01 04:24:56 PM PDT 24
Finished Jul 01 04:25:07 PM PDT 24
Peak memory 205208 kb
Host smart-414e20a2-73c5-47a7-b273-a218691c4e37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333375672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1333375672
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1752897734
Short name T327
Test name
Test status
Simulation time 122620421 ps
CPU time 3.44 seconds
Started Jul 01 04:25:05 PM PDT 24
Finished Jul 01 04:25:10 PM PDT 24
Peak memory 213080 kb
Host smart-071e9157-5aa3-4380-abe0-3ee4219b7a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752897734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1752897734
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1471484039
Short name T129
Test name
Test status
Simulation time 8720345994 ps
CPU time 74.97 seconds
Started Jul 01 04:24:21 PM PDT 24
Finished Jul 01 04:25:42 PM PDT 24
Peak memory 213080 kb
Host smart-1359ecc8-76f6-4d5b-bb66-ddb681eae793
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471484039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1471484039
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.431651563
Short name T333
Test name
Test status
Simulation time 30461087860 ps
CPU time 69.78 seconds
Started Jul 01 04:24:25 PM PDT 24
Finished Jul 01 04:25:43 PM PDT 24
Peak memory 213108 kb
Host smart-29faa688-364c-4098-bb74-137528565864
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431651563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.431651563
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3529500621
Short name T124
Test name
Test status
Simulation time 378091477 ps
CPU time 2.3 seconds
Started Jul 01 04:24:33 PM PDT 24
Finished Jul 01 04:24:43 PM PDT 24
Peak memory 212956 kb
Host smart-b7528f7b-eec5-4e6a-abbd-03037674e7dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529500621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3529500621
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3943184806
Short name T132
Test name
Test status
Simulation time 242602350 ps
CPU time 2.61 seconds
Started Jul 01 04:24:28 PM PDT 24
Finished Jul 01 04:24:40 PM PDT 24
Peak memory 221312 kb
Host smart-b07cb80f-81e7-46bb-a617-5c1a9a6f5ebf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943184806 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3943184806
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.530218960
Short name T401
Test name
Test status
Simulation time 132866616 ps
CPU time 1.5 seconds
Started Jul 01 04:24:23 PM PDT 24
Finished Jul 01 04:24:32 PM PDT 24
Peak memory 212916 kb
Host smart-43aed5ab-9d61-45f7-8efd-f4cf04565dac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530218960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.530218960
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.105740485
Short name T429
Test name
Test status
Simulation time 39501817259 ps
CPU time 23.71 seconds
Started Jul 01 04:24:34 PM PDT 24
Finished Jul 01 04:25:05 PM PDT 24
Peak memory 204784 kb
Host smart-87272c09-4779-4dad-94dd-00cd67b83267
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105740485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.105740485
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.692061023
Short name T317
Test name
Test status
Simulation time 40289578267 ps
CPU time 57.07 seconds
Started Jul 01 04:24:17 PM PDT 24
Finished Jul 01 04:25:19 PM PDT 24
Peak memory 204668 kb
Host smart-fa9029d9-e285-4900-8c35-624570ecb59b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692061023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r
v_dm_jtag_dmi_csr_bit_bash.692061023
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2806811849
Short name T107
Test name
Test status
Simulation time 17489475661 ps
CPU time 43.48 seconds
Started Jul 01 04:24:47 PM PDT 24
Finished Jul 01 04:25:35 PM PDT 24
Peak memory 204868 kb
Host smart-50e34108-bc0a-49b8-9e50-b21b1f4e1ec7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806811849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2806811849
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3711911400
Short name T345
Test name
Test status
Simulation time 1090789168 ps
CPU time 1.73 seconds
Started Jul 01 04:24:26 PM PDT 24
Finished Jul 01 04:24:37 PM PDT 24
Peak memory 204668 kb
Host smart-15bf120d-509e-4c2d-bc0b-edcd745e6d4c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711911400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
711911400
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1175992585
Short name T307
Test name
Test status
Simulation time 1223937146 ps
CPU time 1.11 seconds
Started Jul 01 04:24:22 PM PDT 24
Finished Jul 01 04:24:31 PM PDT 24
Peak memory 204508 kb
Host smart-5e238138-ab68-412d-a0f6-30b0446154b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175992585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.1175992585
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2834491646
Short name T351
Test name
Test status
Simulation time 10420278617 ps
CPU time 6.4 seconds
Started Jul 01 04:24:26 PM PDT 24
Finished Jul 01 04:24:42 PM PDT 24
Peak memory 204560 kb
Host smart-8659db1d-af3e-43ac-a834-5e784abcda76
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834491646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2834491646
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2936442752
Short name T416
Test name
Test status
Simulation time 423472492 ps
CPU time 1.11 seconds
Started Jul 01 04:24:37 PM PDT 24
Finished Jul 01 04:24:44 PM PDT 24
Peak memory 204824 kb
Host smart-6105a28e-5d97-4392-9dbf-1b39a9bdae64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936442752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2936442752
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.593887628
Short name T329
Test name
Test status
Simulation time 572368626 ps
CPU time 1.31 seconds
Started Jul 01 04:24:22 PM PDT 24
Finished Jul 01 04:24:31 PM PDT 24
Peak memory 204488 kb
Host smart-2fc2cfad-a3a9-4c2b-b344-53b3de723d01
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593887628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.593887628
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1762950837
Short name T412
Test name
Test status
Simulation time 135144141 ps
CPU time 0.78 seconds
Started Jul 01 04:24:29 PM PDT 24
Finished Jul 01 04:24:39 PM PDT 24
Peak memory 204824 kb
Host smart-f683f11f-eae6-4d25-9943-2e878a43b761
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762950837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1762950837
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3514327666
Short name T332
Test name
Test status
Simulation time 95821320 ps
CPU time 0.71 seconds
Started Jul 01 04:24:25 PM PDT 24
Finished Jul 01 04:24:36 PM PDT 24
Peak memory 204492 kb
Host smart-1f038771-3279-4910-b095-ecb4c3a9decc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514327666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3514327666
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1421310977
Short name T116
Test name
Test status
Simulation time 756136070 ps
CPU time 6.37 seconds
Started Jul 01 04:24:37 PM PDT 24
Finished Jul 01 04:24:49 PM PDT 24
Peak memory 204864 kb
Host smart-6b662e58-9dae-4ed7-afc7-0933c5637b24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421310977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1421310977
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2237252965
Short name T177
Test name
Test status
Simulation time 17935986835 ps
CPU time 30.3 seconds
Started Jul 01 04:24:30 PM PDT 24
Finished Jul 01 04:25:10 PM PDT 24
Peak memory 221196 kb
Host smart-1397898c-bdd2-44d4-819a-b9acf5b829ac
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237252965 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2237252965
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2353326420
Short name T347
Test name
Test status
Simulation time 339941195 ps
CPU time 3.58 seconds
Started Jul 01 04:24:31 PM PDT 24
Finished Jul 01 04:24:44 PM PDT 24
Peak memory 213080 kb
Host smart-df732848-986a-4582-a92b-817fa9afc8a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353326420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2353326420
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.582921369
Short name T340
Test name
Test status
Simulation time 2940600592 ps
CPU time 57.83 seconds
Started Jul 01 04:24:25 PM PDT 24
Finished Jul 01 04:25:33 PM PDT 24
Peak memory 213356 kb
Host smart-30f83b83-a884-4cb1-a6b7-1fd4782e8c17
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582921369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.582921369
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.573445286
Short name T99
Test name
Test status
Simulation time 352895164 ps
CPU time 2.66 seconds
Started Jul 01 04:24:39 PM PDT 24
Finished Jul 01 04:24:47 PM PDT 24
Peak memory 213040 kb
Host smart-beaf5156-ad94-4c27-8775-07145d5f0226
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573445286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.573445286
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2962021887
Short name T104
Test name
Test status
Simulation time 3335482940 ps
CPU time 8.39 seconds
Started Jul 01 04:24:22 PM PDT 24
Finished Jul 01 04:24:38 PM PDT 24
Peak memory 219692 kb
Host smart-c0a32d91-8d9a-4ed5-8497-a774d27b64f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962021887 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2962021887
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1621822155
Short name T420
Test name
Test status
Simulation time 321773020 ps
CPU time 2.39 seconds
Started Jul 01 04:24:23 PM PDT 24
Finished Jul 01 04:24:34 PM PDT 24
Peak memory 213220 kb
Host smart-405f1ade-8be0-447d-b1de-a333783c6cfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621822155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1621822155
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1459511911
Short name T419
Test name
Test status
Simulation time 42679992164 ps
CPU time 115.67 seconds
Started Jul 01 04:24:30 PM PDT 24
Finished Jul 01 04:26:35 PM PDT 24
Peak memory 205008 kb
Host smart-1320df60-1409-4262-9fb4-814b1418ba78
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459511911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1459511911
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3824513203
Short name T399
Test name
Test status
Simulation time 13606987313 ps
CPU time 5.82 seconds
Started Jul 01 04:24:26 PM PDT 24
Finished Jul 01 04:24:41 PM PDT 24
Peak memory 204704 kb
Host smart-b87a9076-e16a-44c6-9037-02b1d023e2db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824513203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.3824513203
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2527496672
Short name T106
Test name
Test status
Simulation time 4458131676 ps
CPU time 3.63 seconds
Started Jul 01 04:24:29 PM PDT 24
Finished Jul 01 04:24:41 PM PDT 24
Peak memory 204868 kb
Host smart-6246492a-602d-45a1-9c58-296b8f1b7894
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527496672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2527496672
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1321388148
Short name T359
Test name
Test status
Simulation time 1153830329 ps
CPU time 1.37 seconds
Started Jul 01 04:24:40 PM PDT 24
Finished Jul 01 04:24:47 PM PDT 24
Peak memory 204656 kb
Host smart-2f05deca-10a1-445d-9960-02ba0a44246b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321388148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
321388148
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1713573802
Short name T336
Test name
Test status
Simulation time 206660615 ps
CPU time 1.2 seconds
Started Jul 01 04:24:27 PM PDT 24
Finished Jul 01 04:24:38 PM PDT 24
Peak memory 204496 kb
Host smart-a1ccdf32-693c-4ad3-bf42-d1e683ad94d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713573802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1713573802
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3318529665
Short name T348
Test name
Test status
Simulation time 49498576516 ps
CPU time 129.4 seconds
Started Jul 01 04:24:21 PM PDT 24
Finished Jul 01 04:26:36 PM PDT 24
Peak memory 204748 kb
Host smart-05ca434e-5e46-49a3-9d70-fb2c5be5facb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318529665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3318529665
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.743016823
Short name T354
Test name
Test status
Simulation time 313901729 ps
CPU time 0.95 seconds
Started Jul 01 04:24:26 PM PDT 24
Finished Jul 01 04:24:36 PM PDT 24
Peak memory 204500 kb
Host smart-b057259e-6a54-4533-8241-e3141dd62ee4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743016823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.743016823
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4112558300
Short name T375
Test name
Test status
Simulation time 916069495 ps
CPU time 2.71 seconds
Started Jul 01 04:24:24 PM PDT 24
Finished Jul 01 04:24:36 PM PDT 24
Peak memory 204444 kb
Host smart-bf897fc7-95e2-48e5-9637-830ed83d69c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112558300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.4
112558300
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2633497715
Short name T301
Test name
Test status
Simulation time 106058365 ps
CPU time 0.77 seconds
Started Jul 01 04:24:40 PM PDT 24
Finished Jul 01 04:24:46 PM PDT 24
Peak memory 204488 kb
Host smart-8081cfd4-14f5-49db-82be-42a3e41271a4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633497715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2633497715
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.215945984
Short name T299
Test name
Test status
Simulation time 113283521 ps
CPU time 0.68 seconds
Started Jul 01 04:24:23 PM PDT 24
Finished Jul 01 04:24:31 PM PDT 24
Peak memory 204432 kb
Host smart-47208849-ba9d-4cad-8402-4db9db33a1aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215945984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.215945984
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4001953967
Short name T115
Test name
Test status
Simulation time 660492812 ps
CPU time 8.19 seconds
Started Jul 01 04:24:32 PM PDT 24
Finished Jul 01 04:24:48 PM PDT 24
Peak memory 204860 kb
Host smart-7ef79fbe-cdb4-479b-9746-eaad8479ed8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001953967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.4001953967
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2049082865
Short name T86
Test name
Test status
Simulation time 70064606 ps
CPU time 2.41 seconds
Started Jul 01 04:24:27 PM PDT 24
Finished Jul 01 04:24:38 PM PDT 24
Peak memory 213032 kb
Host smart-f6db450d-64a4-46dc-a71b-7544a7efa308
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049082865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2049082865
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.29337634
Short name T135
Test name
Test status
Simulation time 2454407429 ps
CPU time 12.95 seconds
Started Jul 01 04:24:34 PM PDT 24
Finished Jul 01 04:24:54 PM PDT 24
Peak memory 213120 kb
Host smart-65584d80-185a-4511-9592-fc6b249454de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29337634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.29337634
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2999772223
Short name T365
Test name
Test status
Simulation time 3388762931 ps
CPU time 73.58 seconds
Started Jul 01 04:24:28 PM PDT 24
Finished Jul 01 04:25:51 PM PDT 24
Peak memory 213104 kb
Host smart-9405a408-fd5f-436a-b1ad-13d5dc44ef4d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999772223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2999772223
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1636383814
Short name T321
Test name
Test status
Simulation time 7607618681 ps
CPU time 35.74 seconds
Started Jul 01 04:24:37 PM PDT 24
Finished Jul 01 04:25:19 PM PDT 24
Peak memory 204868 kb
Host smart-16d5b86b-8fa5-4951-aadf-eb1c341b27ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636383814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1636383814
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2033406985
Short name T350
Test name
Test status
Simulation time 242456704 ps
CPU time 1.64 seconds
Started Jul 01 04:24:47 PM PDT 24
Finished Jul 01 04:24:53 PM PDT 24
Peak memory 213180 kb
Host smart-fae33d44-be93-49ec-8949-3f4c0719b036
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033406985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2033406985
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3375076571
Short name T388
Test name
Test status
Simulation time 385858067 ps
CPU time 2.62 seconds
Started Jul 01 04:25:43 PM PDT 24
Finished Jul 01 04:25:55 PM PDT 24
Peak memory 216952 kb
Host smart-91dddb03-a95a-4d4c-8637-6451bbf39c27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375076571 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3375076571
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3244944337
Short name T421
Test name
Test status
Simulation time 216287670 ps
CPU time 2.24 seconds
Started Jul 01 04:24:31 PM PDT 24
Finished Jul 01 04:24:42 PM PDT 24
Peak memory 212996 kb
Host smart-a14298b9-ac58-4394-86c7-4b33e0915ec8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244944337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3244944337
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1707335776
Short name T378
Test name
Test status
Simulation time 94663132315 ps
CPU time 42.02 seconds
Started Jul 01 04:24:38 PM PDT 24
Finished Jul 01 04:25:26 PM PDT 24
Peak memory 204688 kb
Host smart-83e429a9-3509-44c3-a9be-2ab93dc743d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707335776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1707335776
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2108745286
Short name T328
Test name
Test status
Simulation time 7614885647 ps
CPU time 21.67 seconds
Started Jul 01 04:25:45 PM PDT 24
Finished Jul 01 04:26:17 PM PDT 24
Peak memory 204744 kb
Host smart-568dd6b6-4399-4556-8147-1a09c181dfd2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108745286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.2108745286
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4008447811
Short name T108
Test name
Test status
Simulation time 19779335326 ps
CPU time 57.9 seconds
Started Jul 01 04:24:33 PM PDT 24
Finished Jul 01 04:25:39 PM PDT 24
Peak memory 204772 kb
Host smart-c3f4e984-74b0-4ba3-a54a-6fa14fdff95d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008447811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.4008447811
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2684253012
Short name T361
Test name
Test status
Simulation time 3654366571 ps
CPU time 1.87 seconds
Started Jul 01 04:24:35 PM PDT 24
Finished Jul 01 04:24:44 PM PDT 24
Peak memory 204948 kb
Host smart-ba44fefc-9284-4f29-bf0b-c5cd4baab0b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684253012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
684253012
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.192774768
Short name T404
Test name
Test status
Simulation time 428448130 ps
CPU time 1.24 seconds
Started Jul 01 04:24:25 PM PDT 24
Finished Jul 01 04:24:35 PM PDT 24
Peak memory 204484 kb
Host smart-878a993c-3d0c-4476-b6d8-e34c6dd7ef30
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192774768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.192774768
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.794057050
Short name T380
Test name
Test status
Simulation time 33465935969 ps
CPU time 44.81 seconds
Started Jul 01 04:25:46 PM PDT 24
Finished Jul 01 04:26:41 PM PDT 24
Peak memory 204736 kb
Host smart-d4c9d6c2-17c8-499e-be18-747d14691171
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794057050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.794057050
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1498996282
Short name T315
Test name
Test status
Simulation time 708355255 ps
CPU time 1.59 seconds
Started Jul 01 04:24:43 PM PDT 24
Finished Jul 01 04:24:49 PM PDT 24
Peak memory 204468 kb
Host smart-99c0d6c2-67d9-4b10-8b39-603d78435fe3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498996282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1498996282
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3911672813
Short name T80
Test name
Test status
Simulation time 300442308 ps
CPU time 1.57 seconds
Started Jul 01 04:25:26 PM PDT 24
Finished Jul 01 04:25:41 PM PDT 24
Peak memory 202436 kb
Host smart-2cf8825b-6513-4e99-99d6-8959a823ba73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911672813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
911672813
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.540963595
Short name T369
Test name
Test status
Simulation time 60857599 ps
CPU time 0.72 seconds
Started Jul 01 04:24:41 PM PDT 24
Finished Jul 01 04:24:46 PM PDT 24
Peak memory 204488 kb
Host smart-40b82280-0bb2-48e2-b8e3-e443e674e83e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540963595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.540963595
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2518176783
Short name T319
Test name
Test status
Simulation time 64260412 ps
CPU time 0.71 seconds
Started Jul 01 04:24:36 PM PDT 24
Finished Jul 01 04:24:43 PM PDT 24
Peak memory 204720 kb
Host smart-0c087fc0-517e-426d-8448-9e7945f47167
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518176783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2518176783
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1793665157
Short name T434
Test name
Test status
Simulation time 159485838 ps
CPU time 3.36 seconds
Started Jul 01 04:24:23 PM PDT 24
Finished Jul 01 04:24:34 PM PDT 24
Peak memory 213064 kb
Host smart-b46a7726-8ffd-4bb6-a09a-bb46adbda63f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793665157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1793665157
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.496853099
Short name T173
Test name
Test status
Simulation time 2921957760 ps
CPU time 21.96 seconds
Started Jul 01 04:24:29 PM PDT 24
Finished Jul 01 04:25:00 PM PDT 24
Peak memory 213168 kb
Host smart-1c3595bf-0928-4560-b329-d672ea3f813e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496853099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.496853099
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3822781245
Short name T133
Test name
Test status
Simulation time 411011511 ps
CPU time 3.79 seconds
Started Jul 01 04:24:46 PM PDT 24
Finished Jul 01 04:24:55 PM PDT 24
Peak memory 219056 kb
Host smart-3b94f052-ef42-49d6-a9c9-9b4782caa933
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822781245 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3822781245
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2976353205
Short name T96
Test name
Test status
Simulation time 240158936 ps
CPU time 1.48 seconds
Started Jul 01 04:25:52 PM PDT 24
Finished Jul 01 04:26:05 PM PDT 24
Peak memory 212940 kb
Host smart-33366128-3639-4ddf-9646-c19d6e57cd8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976353205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2976353205
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1157673797
Short name T411
Test name
Test status
Simulation time 16759934175 ps
CPU time 14.51 seconds
Started Jul 01 04:24:39 PM PDT 24
Finished Jul 01 04:24:59 PM PDT 24
Peak memory 204720 kb
Host smart-06ffa28b-3794-4039-a232-f1ae19e58bbe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157673797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.1157673797
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.4030892192
Short name T313
Test name
Test status
Simulation time 6232344356 ps
CPU time 11.04 seconds
Started Jul 01 04:24:27 PM PDT 24
Finished Jul 01 04:24:47 PM PDT 24
Peak memory 204728 kb
Host smart-052b37ea-6d28-4bdf-86d0-bbe54a798c50
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030892192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.4
030892192
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3263224929
Short name T387
Test name
Test status
Simulation time 619977595 ps
CPU time 1.15 seconds
Started Jul 01 04:24:52 PM PDT 24
Finished Jul 01 04:24:57 PM PDT 24
Peak memory 204492 kb
Host smart-b13978e3-9df6-45fa-b526-0a0ae04cccdf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263224929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
263224929
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3452610990
Short name T113
Test name
Test status
Simulation time 1652547435 ps
CPU time 7.44 seconds
Started Jul 01 04:24:28 PM PDT 24
Finished Jul 01 04:24:45 PM PDT 24
Peak memory 204864 kb
Host smart-dff70661-600f-4911-a619-8a351db66c6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452610990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3452610990
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2073052750
Short name T426
Test name
Test status
Simulation time 50049808018 ps
CPU time 42.76 seconds
Started Jul 01 04:24:33 PM PDT 24
Finished Jul 01 04:25:24 PM PDT 24
Peak memory 218376 kb
Host smart-d32b2bff-11ec-4608-ab43-10a689c0fb0b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073052750 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2073052750
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2583274232
Short name T322
Test name
Test status
Simulation time 508559802 ps
CPU time 2.94 seconds
Started Jul 01 04:24:35 PM PDT 24
Finished Jul 01 04:24:45 PM PDT 24
Peak memory 221256 kb
Host smart-7a673ac4-13bf-4166-aae6-1df577ce8c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583274232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2583274232
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.958435314
Short name T170
Test name
Test status
Simulation time 2333364778 ps
CPU time 18.34 seconds
Started Jul 01 04:24:37 PM PDT 24
Finished Jul 01 04:25:01 PM PDT 24
Peak memory 213148 kb
Host smart-d0ab12d3-e7be-48da-bb8a-09f74fb47fd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958435314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.958435314
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3003342249
Short name T306
Test name
Test status
Simulation time 3762717378 ps
CPU time 5.59 seconds
Started Jul 01 04:24:28 PM PDT 24
Finished Jul 01 04:24:43 PM PDT 24
Peak memory 220352 kb
Host smart-8311fe46-4125-42a7-b1cd-393330c450a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003342249 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3003342249
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1165662019
Short name T386
Test name
Test status
Simulation time 497959243 ps
CPU time 2.39 seconds
Started Jul 01 04:25:51 PM PDT 24
Finished Jul 01 04:26:04 PM PDT 24
Peak memory 212924 kb
Host smart-38ae0696-c7f1-4bdf-b6c8-1d9af330ea72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165662019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1165662019
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1590909613
Short name T385
Test name
Test status
Simulation time 4199635333 ps
CPU time 7.89 seconds
Started Jul 01 04:24:31 PM PDT 24
Finished Jul 01 04:24:47 PM PDT 24
Peak memory 204652 kb
Host smart-a8e77d31-0e45-40ef-a7b4-eaddab3a0c1d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590909613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.1590909613
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3466097798
Short name T308
Test name
Test status
Simulation time 2411769218 ps
CPU time 2.47 seconds
Started Jul 01 04:24:37 PM PDT 24
Finished Jul 01 04:24:46 PM PDT 24
Peak memory 204680 kb
Host smart-a808243d-f16c-463d-bcc3-8a50acbde814
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466097798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
466097798
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1424026381
Short name T343
Test name
Test status
Simulation time 197864277 ps
CPU time 0.93 seconds
Started Jul 01 04:24:25 PM PDT 24
Finished Jul 01 04:24:35 PM PDT 24
Peak memory 204460 kb
Host smart-ee541c38-c814-412c-830c-d11305e1fef5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424026381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
424026381
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3537867539
Short name T374
Test name
Test status
Simulation time 865950123 ps
CPU time 4.22 seconds
Started Jul 01 04:24:31 PM PDT 24
Finished Jul 01 04:24:44 PM PDT 24
Peak memory 204868 kb
Host smart-86442554-7009-4b76-9fc8-c52fe716bcdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537867539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3537867539
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.572315123
Short name T61
Test name
Test status
Simulation time 71689002905 ps
CPU time 82.31 seconds
Started Jul 01 04:24:37 PM PDT 24
Finished Jul 01 04:26:05 PM PDT 24
Peak memory 225488 kb
Host smart-4689a31a-3740-46cf-9517-2a8bd5f3fb8e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572315123 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.572315123
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1419541042
Short name T363
Test name
Test status
Simulation time 694949868 ps
CPU time 3.65 seconds
Started Jul 01 04:24:24 PM PDT 24
Finished Jul 01 04:24:37 PM PDT 24
Peak memory 213116 kb
Host smart-1e8039e1-33f9-4622-bc10-fe80270f8752
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419541042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1419541042
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2488770398
Short name T439
Test name
Test status
Simulation time 2193222285 ps
CPU time 10.86 seconds
Started Jul 01 04:24:29 PM PDT 24
Finished Jul 01 04:24:49 PM PDT 24
Peak memory 213388 kb
Host smart-a603f059-c201-4111-85b7-f3b74a09c15a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488770398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2488770398
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2323762674
Short name T85
Test name
Test status
Simulation time 831739653 ps
CPU time 2.67 seconds
Started Jul 01 04:24:38 PM PDT 24
Finished Jul 01 04:24:46 PM PDT 24
Peak memory 213088 kb
Host smart-c38a1de6-a339-4b3a-91aa-d20bc4a74309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323762674 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2323762674
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.676184195
Short name T391
Test name
Test status
Simulation time 154798146 ps
CPU time 2.24 seconds
Started Jul 01 04:24:44 PM PDT 24
Finished Jul 01 04:24:51 PM PDT 24
Peak memory 213200 kb
Host smart-3a6c716c-e6c7-40db-a364-57b4f7697c7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676184195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.676184195
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.4096883396
Short name T400
Test name
Test status
Simulation time 15529271721 ps
CPU time 14.78 seconds
Started Jul 01 04:24:34 PM PDT 24
Finished Jul 01 04:24:56 PM PDT 24
Peak memory 204720 kb
Host smart-f1c7d570-301f-446c-a935-f987c2d622f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096883396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.4096883396
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1111787940
Short name T324
Test name
Test status
Simulation time 2992657363 ps
CPU time 4.66 seconds
Started Jul 01 04:24:42 PM PDT 24
Finished Jul 01 04:24:51 PM PDT 24
Peak memory 204728 kb
Host smart-221ed06b-f23e-4bd6-a3f0-14a588606998
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111787940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
111787940
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1447350723
Short name T312
Test name
Test status
Simulation time 509404203 ps
CPU time 1.31 seconds
Started Jul 01 04:25:26 PM PDT 24
Finished Jul 01 04:25:41 PM PDT 24
Peak memory 202656 kb
Host smart-a9e3ae0d-c06a-4c5a-b878-ace4b1983d5a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447350723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
447350723
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3732851601
Short name T402
Test name
Test status
Simulation time 444893558 ps
CPU time 4.2 seconds
Started Jul 01 04:24:43 PM PDT 24
Finished Jul 01 04:24:52 PM PDT 24
Peak memory 204860 kb
Host smart-7b9e0c93-0e5f-4bcf-8dbe-d658b4bb0d36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732851601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3732851601
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.558143970
Short name T395
Test name
Test status
Simulation time 25765156920 ps
CPU time 22.46 seconds
Started Jul 01 04:24:32 PM PDT 24
Finished Jul 01 04:25:02 PM PDT 24
Peak memory 221384 kb
Host smart-865ef35a-4339-4b76-9074-a33d45ec045d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558143970 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.558143970
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2967043133
Short name T103
Test name
Test status
Simulation time 105630957 ps
CPU time 2.37 seconds
Started Jul 01 04:24:45 PM PDT 24
Finished Jul 01 04:24:52 PM PDT 24
Peak memory 213032 kb
Host smart-ed2a068b-ed03-4c03-9f19-7be705bc0ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967043133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2967043133
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2704370592
Short name T383
Test name
Test status
Simulation time 4030745769 ps
CPU time 20.47 seconds
Started Jul 01 04:24:41 PM PDT 24
Finished Jul 01 04:25:07 PM PDT 24
Peak memory 213368 kb
Host smart-dd486633-2c82-4144-af52-64dcf4d27418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704370592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2704370592
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3766308331
Short name T69
Test name
Test status
Simulation time 114295674 ps
CPU time 2.68 seconds
Started Jul 01 04:24:44 PM PDT 24
Finished Jul 01 04:24:51 PM PDT 24
Peak memory 219608 kb
Host smart-6cffb93c-8738-405a-9fa1-8917cdb3ba21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766308331 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3766308331
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.982534331
Short name T94
Test name
Test status
Simulation time 347336207 ps
CPU time 2.44 seconds
Started Jul 01 04:24:43 PM PDT 24
Finished Jul 01 04:24:50 PM PDT 24
Peak memory 213308 kb
Host smart-cbfc204b-2221-4cac-83a0-9b5fee8bbf9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982534331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.982534331
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1557635135
Short name T304
Test name
Test status
Simulation time 17840570661 ps
CPU time 26.4 seconds
Started Jul 01 04:24:52 PM PDT 24
Finished Jul 01 04:25:22 PM PDT 24
Peak memory 204964 kb
Host smart-eb1fa105-54cf-48d0-8fb9-91fce01f053e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557635135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.1557635135
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2870968760
Short name T425
Test name
Test status
Simulation time 5331226929 ps
CPU time 4.59 seconds
Started Jul 01 04:24:45 PM PDT 24
Finished Jul 01 04:24:55 PM PDT 24
Peak memory 204708 kb
Host smart-8599751f-58e9-48f6-bad7-e1e225a1cfca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870968760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2
870968760
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2751946869
Short name T325
Test name
Test status
Simulation time 119522473 ps
CPU time 0.72 seconds
Started Jul 01 04:24:37 PM PDT 24
Finished Jul 01 04:24:44 PM PDT 24
Peak memory 204488 kb
Host smart-39d368a5-659f-4786-92ac-57851c30a4c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751946869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
751946869
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2383366592
Short name T95
Test name
Test status
Simulation time 7578353592 ps
CPU time 8.93 seconds
Started Jul 01 04:24:50 PM PDT 24
Finished Jul 01 04:25:03 PM PDT 24
Peak memory 204908 kb
Host smart-3c3d42e3-2a84-4e01-bd12-22ce5396dadc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383366592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2383366592
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4046652743
Short name T403
Test name
Test status
Simulation time 25495254735 ps
CPU time 23.49 seconds
Started Jul 01 04:24:47 PM PDT 24
Finished Jul 01 04:25:14 PM PDT 24
Peak memory 221328 kb
Host smart-6d142129-679e-4aee-9315-e1e5345e79c9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046652743 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.4046652743
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.280191713
Short name T162
Test name
Test status
Simulation time 214990897 ps
CPU time 3.4 seconds
Started Jul 01 04:24:51 PM PDT 24
Finished Jul 01 04:24:59 PM PDT 24
Peak memory 213124 kb
Host smart-b604606a-4403-4889-8e37-90928c4e2cde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280191713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.280191713
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.494791662
Short name T171
Test name
Test status
Simulation time 4406015686 ps
CPU time 19.9 seconds
Started Jul 01 04:24:39 PM PDT 24
Finished Jul 01 04:25:05 PM PDT 24
Peak memory 213116 kb
Host smart-f3966119-9203-41c6-bf4d-1483c79e077a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494791662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.494791662
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2934643846
Short name T422
Test name
Test status
Simulation time 966348603 ps
CPU time 5.47 seconds
Started Jul 01 04:24:37 PM PDT 24
Finished Jul 01 04:24:49 PM PDT 24
Peak memory 221304 kb
Host smart-4c1430dd-26c0-4d8e-a08e-1b7a800c9f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934643846 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2934643846
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1746418133
Short name T394
Test name
Test status
Simulation time 55837422 ps
CPU time 1.54 seconds
Started Jul 01 04:24:47 PM PDT 24
Finished Jul 01 04:24:53 PM PDT 24
Peak memory 213000 kb
Host smart-d4c22a8a-0554-4c16-b8ac-e0a1845757f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746418133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1746418133
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3385038735
Short name T334
Test name
Test status
Simulation time 11838613500 ps
CPU time 17.67 seconds
Started Jul 01 04:24:52 PM PDT 24
Finished Jul 01 04:25:14 PM PDT 24
Peak memory 204720 kb
Host smart-6d46349b-acec-49cd-84e2-7492215dd338
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385038735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3385038735
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4009007432
Short name T309
Test name
Test status
Simulation time 4767859815 ps
CPU time 14.21 seconds
Started Jul 01 04:24:44 PM PDT 24
Finished Jul 01 04:25:03 PM PDT 24
Peak memory 204716 kb
Host smart-e63f527b-5864-46d1-837a-36941287d643
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009007432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.4
009007432
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2737521530
Short name T360
Test name
Test status
Simulation time 173017280 ps
CPU time 0.95 seconds
Started Jul 01 04:24:50 PM PDT 24
Finished Jul 01 04:24:55 PM PDT 24
Peak memory 204488 kb
Host smart-fa619d13-eea7-4461-9f1f-2ee6b2da32f7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737521530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
737521530
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.373877060
Short name T98
Test name
Test status
Simulation time 1114940517 ps
CPU time 6.96 seconds
Started Jul 01 04:24:49 PM PDT 24
Finished Jul 01 04:25:00 PM PDT 24
Peak memory 204856 kb
Host smart-eb44b931-211e-418d-9fa4-831fb04f159d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373877060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.373877060
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2326982155
Short name T176
Test name
Test status
Simulation time 25824493518 ps
CPU time 43 seconds
Started Jul 01 04:24:44 PM PDT 24
Finished Jul 01 04:25:32 PM PDT 24
Peak memory 220600 kb
Host smart-89c6c83a-b2f5-4130-aeb3-826eb33e2cef
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326982155 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2326982155
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3590588966
Short name T379
Test name
Test status
Simulation time 123193553 ps
CPU time 2.85 seconds
Started Jul 01 04:24:39 PM PDT 24
Finished Jul 01 04:24:48 PM PDT 24
Peak memory 213080 kb
Host smart-2b288488-a8d0-4b94-ad97-5998ed639237
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590588966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3590588966
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2516593390
Short name T174
Test name
Test status
Simulation time 1706802581 ps
CPU time 10.69 seconds
Started Jul 01 04:24:50 PM PDT 24
Finished Jul 01 04:25:05 PM PDT 24
Peak memory 213036 kb
Host smart-c3d92ee1-87c4-4bd8-890b-a93a45f5a3b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516593390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2516593390
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3399709752
Short name T56
Test name
Test status
Simulation time 275211464 ps
CPU time 1.07 seconds
Started Jul 01 04:26:18 PM PDT 24
Finished Jul 01 04:26:32 PM PDT 24
Peak memory 204700 kb
Host smart-0460432b-4aae-4871-a862-1e4569f406f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399709752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3399709752
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.4035443277
Short name T130
Test name
Test status
Simulation time 70632206 ps
CPU time 0.7 seconds
Started Jul 01 04:25:59 PM PDT 24
Finished Jul 01 04:26:12 PM PDT 24
Peak memory 204700 kb
Host smart-792d7811-04ea-463e-b4fc-c60f0d906f53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035443277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.4035443277
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2747011944
Short name T143
Test name
Test status
Simulation time 55255927183 ps
CPU time 28.02 seconds
Started Jul 01 04:26:05 PM PDT 24
Finished Jul 01 04:26:44 PM PDT 24
Peak memory 214752 kb
Host smart-ccb5c374-4584-4f2d-96ee-ea6e79b99cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747011944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2747011944
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1308007376
Short name T248
Test name
Test status
Simulation time 4024405825 ps
CPU time 11.69 seconds
Started Jul 01 04:26:03 PM PDT 24
Finished Jul 01 04:26:26 PM PDT 24
Peak memory 213376 kb
Host smart-b50803f6-66b7-4be2-a1b4-2ac7596f8654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308007376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1308007376
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1666461026
Short name T16
Test name
Test status
Simulation time 207387796 ps
CPU time 1.28 seconds
Started Jul 01 04:26:04 PM PDT 24
Finished Jul 01 04:26:17 PM PDT 24
Peak memory 204692 kb
Host smart-d7429820-9c63-47ad-9f6c-89afca03830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666461026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1666461026
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3191648421
Short name T268
Test name
Test status
Simulation time 277278086 ps
CPU time 1.13 seconds
Started Jul 01 04:26:13 PM PDT 24
Finished Jul 01 04:26:26 PM PDT 24
Peak memory 204700 kb
Host smart-912b35c8-1d4f-4382-aaf9-d22276f1c644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191648421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3191648421
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.772660259
Short name T182
Test name
Test status
Simulation time 251753759 ps
CPU time 1 seconds
Started Jul 01 04:26:09 PM PDT 24
Finished Jul 01 04:26:21 PM PDT 24
Peak memory 204704 kb
Host smart-d7a774d7-a6ef-4370-a309-3f65c67d19a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772660259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.772660259
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.797881776
Short name T1
Test name
Test status
Simulation time 6150850921 ps
CPU time 2.77 seconds
Started Jul 01 04:25:59 PM PDT 24
Finished Jul 01 04:26:14 PM PDT 24
Peak memory 213348 kb
Host smart-8b48cbe0-a5e7-42b4-956c-612f2c44475e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=797881776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.797881776
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.934525746
Short name T72
Test name
Test status
Simulation time 869118981 ps
CPU time 1.98 seconds
Started Jul 01 04:26:07 PM PDT 24
Finished Jul 01 04:26:20 PM PDT 24
Peak memory 204740 kb
Host smart-43c5e210-fe9b-417b-9451-6951ef2d1285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934525746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.934525746
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.950754108
Short name T276
Test name
Test status
Simulation time 174585031 ps
CPU time 0.71 seconds
Started Jul 01 04:26:13 PM PDT 24
Finished Jul 01 04:26:26 PM PDT 24
Peak memory 204708 kb
Host smart-b00995ec-a8d8-4117-a60b-5833a6fd803c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950754108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.950754108
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1187175643
Short name T273
Test name
Test status
Simulation time 1244545239 ps
CPU time 3.65 seconds
Started Jul 01 04:26:35 PM PDT 24
Finished Jul 01 04:26:45 PM PDT 24
Peak memory 204964 kb
Host smart-019afca2-6aaf-4f59-a166-7458d292a969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187175643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1187175643
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1005522505
Short name T270
Test name
Test status
Simulation time 688238775 ps
CPU time 1.15 seconds
Started Jul 01 04:26:06 PM PDT 24
Finished Jul 01 04:26:19 PM PDT 24
Peak memory 204716 kb
Host smart-28605141-2400-4f4a-bbeb-e880034870da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005522505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1005522505
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3561484178
Short name T247
Test name
Test status
Simulation time 6245703743 ps
CPU time 16.81 seconds
Started Jul 01 04:25:59 PM PDT 24
Finished Jul 01 04:26:28 PM PDT 24
Peak memory 204996 kb
Host smart-33107147-8b7b-4d3c-a0ef-083bf0321a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561484178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3561484178
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2707661434
Short name T254
Test name
Test status
Simulation time 286497272 ps
CPU time 0.96 seconds
Started Jul 01 04:26:06 PM PDT 24
Finished Jul 01 04:26:18 PM PDT 24
Peak memory 204680 kb
Host smart-8c9102bb-74a4-41b5-827f-64188452f6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707661434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2707661434
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2317691838
Short name T228
Test name
Test status
Simulation time 510007053 ps
CPU time 1.85 seconds
Started Jul 01 04:26:07 PM PDT 24
Finished Jul 01 04:26:19 PM PDT 24
Peak memory 204696 kb
Host smart-64e27963-b70f-48fc-a814-eaee7693eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317691838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2317691838
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2739730397
Short name T181
Test name
Test status
Simulation time 715684508 ps
CPU time 2.85 seconds
Started Jul 01 04:26:17 PM PDT 24
Finished Jul 01 04:26:33 PM PDT 24
Peak memory 205136 kb
Host smart-af37068d-b49f-4d15-9cdb-e6a95d139971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739730397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2739730397
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.575705094
Short name T184
Test name
Test status
Simulation time 284331831 ps
CPU time 1.03 seconds
Started Jul 01 04:25:58 PM PDT 24
Finished Jul 01 04:26:10 PM PDT 24
Peak memory 204696 kb
Host smart-7896a44a-dc19-48a0-a1a3-e5da8ce2dfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575705094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.575705094
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.15562177
Short name T25
Test name
Test status
Simulation time 224793177 ps
CPU time 0.91 seconds
Started Jul 01 04:26:18 PM PDT 24
Finished Jul 01 04:26:31 PM PDT 24
Peak memory 204688 kb
Host smart-e99adb30-35a8-45a0-9752-ff17bafcb753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15562177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.15562177
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2783532402
Short name T225
Test name
Test status
Simulation time 852469995 ps
CPU time 1.3 seconds
Started Jul 01 04:26:12 PM PDT 24
Finished Jul 01 04:26:26 PM PDT 24
Peak memory 205052 kb
Host smart-2c1d829e-b20b-4063-86b0-6f6b7dca4465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783532402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2783532402
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3043488631
Short name T229
Test name
Test status
Simulation time 4638610291 ps
CPU time 6.49 seconds
Started Jul 01 04:26:19 PM PDT 24
Finished Jul 01 04:26:38 PM PDT 24
Peak memory 214316 kb
Host smart-88f67944-543c-4e86-bc37-64f6bc26a92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043488631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3043488631
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.772192848
Short name T48
Test name
Test status
Simulation time 507043589 ps
CPU time 1.64 seconds
Started Jul 01 04:26:02 PM PDT 24
Finished Jul 01 04:26:15 PM PDT 24
Peak memory 237536 kb
Host smart-677be19b-e7c1-441c-b97e-5f1595280530
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772192848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.772192848
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1033771286
Short name T232
Test name
Test status
Simulation time 849355713 ps
CPU time 2.98 seconds
Started Jul 01 04:26:01 PM PDT 24
Finished Jul 01 04:26:16 PM PDT 24
Peak memory 204848 kb
Host smart-770b7160-df90-4657-9018-21d71f1d25ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033771286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1033771286
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.1802339140
Short name T4
Test name
Test status
Simulation time 3896440588 ps
CPU time 11.14 seconds
Started Jul 01 04:26:04 PM PDT 24
Finished Jul 01 04:26:26 PM PDT 24
Peak memory 213116 kb
Host smart-bb758452-dbee-49ae-b337-282caa0da3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802339140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.1802339140
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.859607409
Short name T59
Test name
Test status
Simulation time 9913666815 ps
CPU time 25.35 seconds
Started Jul 01 04:26:00 PM PDT 24
Finished Jul 01 04:26:37 PM PDT 24
Peak memory 204908 kb
Host smart-fab91d4c-200b-46a8-8c2d-451390a7a403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859607409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.859607409
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.4094755511
Short name T239
Test name
Test status
Simulation time 105039665 ps
CPU time 0.69 seconds
Started Jul 01 04:26:34 PM PDT 24
Finished Jul 01 04:26:42 PM PDT 24
Peak memory 204732 kb
Host smart-56f794c4-8e83-4807-aec5-ca7b23891523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094755511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4094755511
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2501973660
Short name T258
Test name
Test status
Simulation time 17441064978 ps
CPU time 40.72 seconds
Started Jul 01 04:26:33 PM PDT 24
Finished Jul 01 04:27:21 PM PDT 24
Peak memory 205352 kb
Host smart-518930ad-4cf8-4408-b609-0c2d41aaa1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501973660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2501973660
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.684513437
Short name T255
Test name
Test status
Simulation time 1297149508 ps
CPU time 2.13 seconds
Started Jul 01 04:26:05 PM PDT 24
Finished Jul 01 04:26:19 PM PDT 24
Peak memory 213316 kb
Host smart-1d8030f9-53f4-4008-9470-442e35bd91d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684513437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.684513437
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3797574778
Short name T14
Test name
Test status
Simulation time 790903061 ps
CPU time 2.84 seconds
Started Jul 01 04:26:39 PM PDT 24
Finished Jul 01 04:26:55 PM PDT 24
Peak memory 204920 kb
Host smart-969c10c6-3df4-47d7-92b4-3b4924c82091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797574778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3797574778
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3730955982
Short name T20
Test name
Test status
Simulation time 1806901776 ps
CPU time 3.13 seconds
Started Jul 01 04:26:15 PM PDT 24
Finished Jul 01 04:26:31 PM PDT 24
Peak memory 204720 kb
Host smart-ab77f1e1-39ba-4361-9b99-45a4b21a9e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730955982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3730955982
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3652283609
Short name T53
Test name
Test status
Simulation time 204189583 ps
CPU time 0.98 seconds
Started Jul 01 04:26:10 PM PDT 24
Finished Jul 01 04:26:22 PM PDT 24
Peak memory 204676 kb
Host smart-84cb7a03-190b-46c1-a653-1a96af167af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652283609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3652283609
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2242642500
Short name T271
Test name
Test status
Simulation time 172493964 ps
CPU time 1.19 seconds
Started Jul 01 04:26:10 PM PDT 24
Finished Jul 01 04:26:23 PM PDT 24
Peak memory 204912 kb
Host smart-fbb6b18e-ee8b-43de-a6fa-b0f42b940359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242642500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2242642500
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3859423151
Short name T188
Test name
Test status
Simulation time 143566781 ps
CPU time 1.01 seconds
Started Jul 01 04:26:08 PM PDT 24
Finished Jul 01 04:26:20 PM PDT 24
Peak memory 204688 kb
Host smart-eb1c3d92-d072-46dc-b6bb-1c62e4003cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859423151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3859423151
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.3557525144
Short name T41
Test name
Test status
Simulation time 68505045 ps
CPU time 0.83 seconds
Started Jul 01 04:26:19 PM PDT 24
Finished Jul 01 04:26:32 PM PDT 24
Peak memory 215356 kb
Host smart-d1517dda-8e68-46f3-bf32-eb2db1db1036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557525144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3557525144
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3235241012
Short name T155
Test name
Test status
Simulation time 2155806767 ps
CPU time 5.1 seconds
Started Jul 01 04:26:18 PM PDT 24
Finished Jul 01 04:26:36 PM PDT 24
Peak memory 205208 kb
Host smart-ddbdc17f-3bfd-48a2-adaa-cd301330f9a6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235241012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3235241012
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1293423686
Short name T189
Test name
Test status
Simulation time 761585975 ps
CPU time 1.1 seconds
Started Jul 01 04:26:02 PM PDT 24
Finished Jul 01 04:26:15 PM PDT 24
Peak memory 204752 kb
Host smart-f155eeb3-e7f3-47dc-9ef4-c17c01d4a8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293423686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1293423686
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2607024976
Short name T288
Test name
Test status
Simulation time 281616070 ps
CPU time 1.31 seconds
Started Jul 01 04:26:11 PM PDT 24
Finished Jul 01 04:26:26 PM PDT 24
Peak memory 204948 kb
Host smart-a22b3305-302a-4fc0-a643-030d32eba42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607024976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2607024976
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.4130964148
Short name T141
Test name
Test status
Simulation time 2835048314 ps
CPU time 4.36 seconds
Started Jul 01 04:26:01 PM PDT 24
Finished Jul 01 04:26:17 PM PDT 24
Peak memory 204712 kb
Host smart-df75a7af-372a-4e89-9970-a09e3f720155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130964148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.4130964148
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3396444689
Short name T272
Test name
Test status
Simulation time 1902895258 ps
CPU time 3.43 seconds
Started Jul 01 04:26:11 PM PDT 24
Finished Jul 01 04:26:27 PM PDT 24
Peak memory 204756 kb
Host smart-c51a10c1-5dbc-47c1-813b-1ed7a5efff3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396444689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3396444689
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3407216106
Short name T30
Test name
Test status
Simulation time 1686004979 ps
CPU time 1.39 seconds
Started Jul 01 04:26:09 PM PDT 24
Finished Jul 01 04:26:23 PM PDT 24
Peak memory 204892 kb
Host smart-839d1b17-8bb7-47c0-afa3-1689273e906b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407216106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3407216106
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3979794702
Short name T261
Test name
Test status
Simulation time 382533122 ps
CPU time 0.75 seconds
Started Jul 01 04:26:27 PM PDT 24
Finished Jul 01 04:26:37 PM PDT 24
Peak memory 204660 kb
Host smart-ecdf86b0-d762-4cd3-9e23-09a1486fb458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979794702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3979794702
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3629997157
Short name T180
Test name
Test status
Simulation time 4262579284 ps
CPU time 1.64 seconds
Started Jul 01 04:26:08 PM PDT 24
Finished Jul 01 04:26:20 PM PDT 24
Peak memory 204732 kb
Host smart-af803224-1b3c-4902-9237-34953f698274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629997157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3629997157
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3072975523
Short name T187
Test name
Test status
Simulation time 135779109 ps
CPU time 0.75 seconds
Started Jul 01 04:25:59 PM PDT 24
Finished Jul 01 04:26:11 PM PDT 24
Peak memory 204696 kb
Host smart-afb41b3e-8bf6-4c55-b8bd-7e5c426a85c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072975523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3072975523
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3839683656
Short name T58
Test name
Test status
Simulation time 1211713218 ps
CPU time 1.47 seconds
Started Jul 01 04:26:11 PM PDT 24
Finished Jul 01 04:26:25 PM PDT 24
Peak memory 204688 kb
Host smart-e7a0df44-5398-4cdb-8202-9e42caa93634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839683656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3839683656
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3530616391
Short name T54
Test name
Test status
Simulation time 312122230 ps
CPU time 0.8 seconds
Started Jul 01 04:26:09 PM PDT 24
Finished Jul 01 04:26:22 PM PDT 24
Peak memory 212988 kb
Host smart-33eafd9f-4ad1-4a62-9fd4-55b94af78b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530616391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3530616391
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2263792561
Short name T246
Test name
Test status
Simulation time 1236038830 ps
CPU time 3.81 seconds
Started Jul 01 04:26:09 PM PDT 24
Finished Jul 01 04:26:24 PM PDT 24
Peak memory 204720 kb
Host smart-04829c6d-6790-4db3-ae05-db27f8f1199e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263792561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2263792561
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2668200539
Short name T52
Test name
Test status
Simulation time 7053047176 ps
CPU time 19.87 seconds
Started Jul 01 04:26:09 PM PDT 24
Finished Jul 01 04:26:40 PM PDT 24
Peak memory 213364 kb
Host smart-14d16da8-d7b3-48b6-a745-6ba6b5455b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668200539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2668200539
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2834435957
Short name T64
Test name
Test status
Simulation time 2219045666 ps
CPU time 6.7 seconds
Started Jul 01 04:26:10 PM PDT 24
Finished Jul 01 04:26:28 PM PDT 24
Peak memory 236968 kb
Host smart-27329ca9-7362-4586-8baa-e5c6a3152114
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834435957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2834435957
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2774306159
Short name T9
Test name
Test status
Simulation time 1429181285 ps
CPU time 2.93 seconds
Started Jul 01 04:26:13 PM PDT 24
Finished Jul 01 04:26:31 PM PDT 24
Peak memory 204844 kb
Host smart-2a47f95c-563b-4cd2-a055-f15600dbb8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774306159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2774306159
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1294041845
Short name T218
Test name
Test status
Simulation time 81937947 ps
CPU time 0.83 seconds
Started Jul 01 04:26:08 PM PDT 24
Finished Jul 01 04:26:19 PM PDT 24
Peak memory 204708 kb
Host smart-a69abd73-8bcc-494e-8c7b-7dfd99d76d4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294041845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1294041845
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2993228183
Short name T222
Test name
Test status
Simulation time 1334620711 ps
CPU time 4.71 seconds
Started Jul 01 04:26:34 PM PDT 24
Finished Jul 01 04:26:46 PM PDT 24
Peak memory 205100 kb
Host smart-caa06d75-0cab-43b2-b39b-cb87954bad84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993228183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2993228183
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.192208844
Short name T235
Test name
Test status
Simulation time 1252378056 ps
CPU time 1.8 seconds
Started Jul 01 04:26:35 PM PDT 24
Finished Jul 01 04:26:43 PM PDT 24
Peak memory 205464 kb
Host smart-26c03396-ff83-4cc1-9e0e-dfcb0eda2af1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192208844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t
l_access.192208844
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3427309650
Short name T159
Test name
Test status
Simulation time 4776164681 ps
CPU time 7.93 seconds
Started Jul 01 04:26:40 PM PDT 24
Finished Jul 01 04:26:55 PM PDT 24
Peak memory 205132 kb
Host smart-c05c4387-97d4-4c61-a6e2-f2a1620b7253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427309650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3427309650
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2958462955
Short name T192
Test name
Test status
Simulation time 60535608 ps
CPU time 0.77 seconds
Started Jul 01 04:26:18 PM PDT 24
Finished Jul 01 04:26:31 PM PDT 24
Peak memory 204700 kb
Host smart-bb6461dc-23bb-4daf-bfb5-3afdbdcfb3c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958462955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2958462955
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3234059416
Short name T151
Test name
Test status
Simulation time 29379079275 ps
CPU time 68.88 seconds
Started Jul 01 04:26:31 PM PDT 24
Finished Jul 01 04:27:47 PM PDT 24
Peak memory 213316 kb
Host smart-de513722-31d4-4f5d-9f4a-e233cb0fafcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234059416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3234059416
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1870096235
Short name T226
Test name
Test status
Simulation time 2218466102 ps
CPU time 7.37 seconds
Started Jul 01 04:26:52 PM PDT 24
Finished Jul 01 04:27:11 PM PDT 24
Peak memory 213308 kb
Host smart-f6f0ef0c-9ef8-438e-a60c-e5a00fcfee8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870096235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1870096235
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.422606160
Short name T204
Test name
Test status
Simulation time 2528265337 ps
CPU time 3.12 seconds
Started Jul 01 04:26:46 PM PDT 24
Finished Jul 01 04:26:58 PM PDT 24
Peak memory 213308 kb
Host smart-0f1ed32b-f6b4-4b47-a830-2164d7c11039
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=422606160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.422606160
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2713360719
Short name T294
Test name
Test status
Simulation time 1894892330 ps
CPU time 6.1 seconds
Started Jul 01 04:26:14 PM PDT 24
Finished Jul 01 04:26:33 PM PDT 24
Peak memory 205332 kb
Host smart-862becc8-9ab1-4bac-9d25-fe6aa2d7f203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713360719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2713360719
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.3998061812
Short name T149
Test name
Test status
Simulation time 5954424498 ps
CPU time 17.51 seconds
Started Jul 01 04:26:22 PM PDT 24
Finished Jul 01 04:26:50 PM PDT 24
Peak memory 221332 kb
Host smart-d475bd13-2302-4452-bcbf-145dcf64e3ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998061812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3998061812
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3844373982
Short name T193
Test name
Test status
Simulation time 144094211 ps
CPU time 1.08 seconds
Started Jul 01 04:26:24 PM PDT 24
Finished Jul 01 04:26:35 PM PDT 24
Peak memory 205092 kb
Host smart-7eb4a18f-b92f-4bd9-bc8b-fefe3e52ee4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844373982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3844373982
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3512689258
Short name T227
Test name
Test status
Simulation time 2696525708 ps
CPU time 8.44 seconds
Started Jul 01 04:26:35 PM PDT 24
Finished Jul 01 04:26:50 PM PDT 24
Peak memory 213640 kb
Host smart-a03d4b35-6e3f-4004-b5b2-2751ab4cc63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512689258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3512689258
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2461951826
Short name T282
Test name
Test status
Simulation time 990223511 ps
CPU time 1.54 seconds
Started Jul 01 04:26:11 PM PDT 24
Finished Jul 01 04:26:26 PM PDT 24
Peak memory 205272 kb
Host smart-378d7644-d85b-44c4-be77-660715117136
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2461951826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2461951826
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2229629295
Short name T37
Test name
Test status
Simulation time 15387687024 ps
CPU time 39.95 seconds
Started Jul 01 04:26:14 PM PDT 24
Finished Jul 01 04:27:06 PM PDT 24
Peak memory 213636 kb
Host smart-ecb6fc64-3ca5-434c-bece-b7623ff6b977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229629295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2229629295
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3418095058
Short name T145
Test name
Test status
Simulation time 2971402345 ps
CPU time 3.91 seconds
Started Jul 01 04:26:40 PM PDT 24
Finished Jul 01 04:26:51 PM PDT 24
Peak memory 213308 kb
Host smart-7d5545fb-395e-4164-8608-fe32aedc08ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418095058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3418095058
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.925992141
Short name T231
Test name
Test status
Simulation time 44231762 ps
CPU time 0.73 seconds
Started Jul 01 04:26:48 PM PDT 24
Finished Jul 01 04:26:59 PM PDT 24
Peak memory 204696 kb
Host smart-ea9355b1-4d52-4929-81a1-adb7cebaf482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925992141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.925992141
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1472840985
Short name T31
Test name
Test status
Simulation time 10647650415 ps
CPU time 6.14 seconds
Started Jul 01 04:26:13 PM PDT 24
Finished Jul 01 04:26:31 PM PDT 24
Peak memory 213344 kb
Host smart-078ee16d-1b3a-4244-8778-7f2d361ed1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472840985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1472840985
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3969416467
Short name T198
Test name
Test status
Simulation time 2411238942 ps
CPU time 7.1 seconds
Started Jul 01 04:26:32 PM PDT 24
Finished Jul 01 04:26:46 PM PDT 24
Peak memory 213348 kb
Host smart-8362a870-e4f0-419a-bd21-76814bc8b484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969416467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3969416467
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2897972369
Short name T264
Test name
Test status
Simulation time 12768619973 ps
CPU time 20.66 seconds
Started Jul 01 04:26:13 PM PDT 24
Finished Jul 01 04:26:46 PM PDT 24
Peak memory 213396 kb
Host smart-981d3f7f-4f26-4430-b67a-8aa6bd01925f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897972369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2897972369
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3298006652
Short name T216
Test name
Test status
Simulation time 3026518207 ps
CPU time 2.34 seconds
Started Jul 01 04:26:19 PM PDT 24
Finished Jul 01 04:26:33 PM PDT 24
Peak memory 213304 kb
Host smart-f38b565a-4a5b-43e6-b368-ff6c524cce6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298006652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3298006652
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.223500440
Short name T24
Test name
Test status
Simulation time 3795778151 ps
CPU time 5.59 seconds
Started Jul 01 04:26:16 PM PDT 24
Finished Jul 01 04:26:35 PM PDT 24
Peak memory 205024 kb
Host smart-a27bf80d-86b3-4fed-be80-ae7a4beb1739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223500440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.223500440
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2377446423
Short name T243
Test name
Test status
Simulation time 81924457 ps
CPU time 0.87 seconds
Started Jul 01 04:26:33 PM PDT 24
Finished Jul 01 04:26:41 PM PDT 24
Peak memory 204752 kb
Host smart-dccb8363-539f-4d41-8677-c0c3269792fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377446423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2377446423
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3490803139
Short name T260
Test name
Test status
Simulation time 2321938717 ps
CPU time 2.56 seconds
Started Jul 01 04:26:33 PM PDT 24
Finished Jul 01 04:26:43 PM PDT 24
Peak memory 213548 kb
Host smart-c5a8e7de-252c-40c6-bce0-26ce85cb5525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490803139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3490803139
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2711897641
Short name T75
Test name
Test status
Simulation time 2509645755 ps
CPU time 3 seconds
Started Jul 01 04:26:36 PM PDT 24
Finished Jul 01 04:26:46 PM PDT 24
Peak memory 205092 kb
Host smart-53646cae-c7a0-4244-a095-ac3bc23c55b2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2711897641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.2711897641
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3283437282
Short name T71
Test name
Test status
Simulation time 18880141839 ps
CPU time 10.98 seconds
Started Jul 01 04:26:46 PM PDT 24
Finished Jul 01 04:27:06 PM PDT 24
Peak memory 205172 kb
Host smart-b6d0edb5-283d-4137-a82f-ac46302c2174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283437282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3283437282
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3575684392
Short name T140
Test name
Test status
Simulation time 8597300224 ps
CPU time 24.21 seconds
Started Jul 01 04:26:41 PM PDT 24
Finished Jul 01 04:27:12 PM PDT 24
Peak memory 213180 kb
Host smart-c6fd5d71-a2bf-4d61-95d6-8832ad0dc428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575684392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3575684392
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3280287637
Short name T38
Test name
Test status
Simulation time 44840968 ps
CPU time 0.81 seconds
Started Jul 01 04:26:12 PM PDT 24
Finished Jul 01 04:26:25 PM PDT 24
Peak memory 204732 kb
Host smart-e28c4173-6109-4d1a-81fb-ca1ec2b73b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280287637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3280287637
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1173469344
Short name T45
Test name
Test status
Simulation time 11004024966 ps
CPU time 32.65 seconds
Started Jul 01 04:26:36 PM PDT 24
Finished Jul 01 04:27:15 PM PDT 24
Peak memory 213380 kb
Host smart-bd4514dc-1ccf-4faf-ae8a-1fe0f48352bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173469344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1173469344
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3552527470
Short name T291
Test name
Test status
Simulation time 12278164191 ps
CPU time 9.93 seconds
Started Jul 01 04:26:16 PM PDT 24
Finished Jul 01 04:26:38 PM PDT 24
Peak memory 213264 kb
Host smart-ec0b96e0-2438-4247-a766-60ebbea401f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552527470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3552527470
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.757705126
Short name T223
Test name
Test status
Simulation time 1602571490 ps
CPU time 2.34 seconds
Started Jul 01 04:26:23 PM PDT 24
Finished Jul 01 04:26:36 PM PDT 24
Peak memory 205052 kb
Host smart-6c5a2b55-09ce-424a-9c39-6f63d5606f47
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=757705126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.757705126
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.4104377240
Short name T251
Test name
Test status
Simulation time 4483907042 ps
CPU time 12.99 seconds
Started Jul 01 04:26:16 PM PDT 24
Finished Jul 01 04:26:42 PM PDT 24
Peak memory 213316 kb
Host smart-d79a87c4-71ba-444f-953e-c8b751440546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104377240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.4104377240
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1161305545
Short name T253
Test name
Test status
Simulation time 169689547 ps
CPU time 1.15 seconds
Started Jul 01 04:26:15 PM PDT 24
Finished Jul 01 04:26:29 PM PDT 24
Peak memory 204672 kb
Host smart-0ad18998-ffac-4bc0-81d5-6649c5c961de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161305545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1161305545
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2501702523
Short name T28
Test name
Test status
Simulation time 43902872881 ps
CPU time 56.71 seconds
Started Jul 01 04:26:20 PM PDT 24
Finished Jul 01 04:27:29 PM PDT 24
Peak memory 213336 kb
Host smart-1e2b1199-a562-49d7-bca6-e900b25d1936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501702523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2501702523
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.676001586
Short name T289
Test name
Test status
Simulation time 14772305517 ps
CPU time 35.38 seconds
Started Jul 01 04:26:22 PM PDT 24
Finished Jul 01 04:27:11 PM PDT 24
Peak memory 213360 kb
Host smart-1c00dac8-6897-42e0-8ed6-a6efc9ea301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676001586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.676001586
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1491982807
Short name T139
Test name
Test status
Simulation time 2939397795 ps
CPU time 9.79 seconds
Started Jul 01 04:26:41 PM PDT 24
Finished Jul 01 04:26:58 PM PDT 24
Peak memory 205340 kb
Host smart-a4d703a0-8113-45f7-90a4-8f88151635ba
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491982807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1491982807
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2318585064
Short name T285
Test name
Test status
Simulation time 10874539620 ps
CPU time 6.42 seconds
Started Jul 01 04:26:18 PM PDT 24
Finished Jul 01 04:26:37 PM PDT 24
Peak memory 205092 kb
Host smart-359c22cc-ada7-4a38-a259-ef853e01e768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318585064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2318585064
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.1526508267
Short name T42
Test name
Test status
Simulation time 8074916869 ps
CPU time 12.33 seconds
Started Jul 01 04:26:39 PM PDT 24
Finished Jul 01 04:26:59 PM PDT 24
Peak memory 204964 kb
Host smart-2fac6b6f-8176-46c4-b7cf-2bcbe3796164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526508267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1526508267
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1519439605
Short name T200
Test name
Test status
Simulation time 135398061 ps
CPU time 0.83 seconds
Started Jul 01 04:26:34 PM PDT 24
Finished Jul 01 04:26:41 PM PDT 24
Peak memory 204752 kb
Host smart-f013b1da-b166-4bd1-998c-b678d1fbf6ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519439605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1519439605
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1957350579
Short name T208
Test name
Test status
Simulation time 6967330306 ps
CPU time 7.04 seconds
Started Jul 01 04:26:32 PM PDT 24
Finished Jul 01 04:26:46 PM PDT 24
Peak memory 213316 kb
Host smart-f0bacfac-aa1b-44f5-956a-61e752e1dfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957350579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1957350579
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.4185764293
Short name T195
Test name
Test status
Simulation time 5769103389 ps
CPU time 17.46 seconds
Started Jul 01 04:26:33 PM PDT 24
Finished Jul 01 04:26:58 PM PDT 24
Peak memory 205544 kb
Host smart-0f4843c7-d093-4398-8b80-a419a7ee3d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185764293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.4185764293
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3013814702
Short name T266
Test name
Test status
Simulation time 2384036363 ps
CPU time 4.44 seconds
Started Jul 01 04:26:42 PM PDT 24
Finished Jul 01 04:26:54 PM PDT 24
Peak memory 213588 kb
Host smart-949d375c-c7fe-41ac-b170-ef9889bcabf5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3013814702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3013814702
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3558713528
Short name T275
Test name
Test status
Simulation time 1708832191 ps
CPU time 2.24 seconds
Started Jul 01 04:26:42 PM PDT 24
Finished Jul 01 04:26:52 PM PDT 24
Peak memory 205144 kb
Host smart-89cc7ec9-b175-4efe-82b2-6f6b7cb4aa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558713528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3558713528
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.1359108181
Short name T92
Test name
Test status
Simulation time 5241977274 ps
CPU time 8.04 seconds
Started Jul 01 04:26:45 PM PDT 24
Finished Jul 01 04:27:01 PM PDT 24
Peak memory 205072 kb
Host smart-8a77dc5d-e10d-402d-87e3-a0f4d47311f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359108181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1359108181
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.995814229
Short name T203
Test name
Test status
Simulation time 37890757 ps
CPU time 0.84 seconds
Started Jul 01 04:26:41 PM PDT 24
Finished Jul 01 04:26:49 PM PDT 24
Peak memory 204760 kb
Host smart-4dc4c657-3557-4b8a-84c3-5d487f47dba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995814229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.995814229
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3208500746
Short name T83
Test name
Test status
Simulation time 5333714093 ps
CPU time 4.18 seconds
Started Jul 01 04:26:38 PM PDT 24
Finished Jul 01 04:26:50 PM PDT 24
Peak memory 213504 kb
Host smart-44f33bc5-779b-4f8a-9725-9168d39d3358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208500746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3208500746
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1975415842
Short name T259
Test name
Test status
Simulation time 2643941418 ps
CPU time 2.87 seconds
Started Jul 01 04:26:27 PM PDT 24
Finished Jul 01 04:26:39 PM PDT 24
Peak memory 205156 kb
Host smart-b2fa134c-f020-4a30-b876-6768cb64f0e3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1975415842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1975415842
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.2482418440
Short name T296
Test name
Test status
Simulation time 6072137710 ps
CPU time 15.56 seconds
Started Jul 01 04:26:48 PM PDT 24
Finished Jul 01 04:27:13 PM PDT 24
Peak memory 205192 kb
Host smart-0cbea786-ea86-4156-91f5-5f37c9e461f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482418440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2482418440
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2312775015
Short name T205
Test name
Test status
Simulation time 43937698 ps
CPU time 0.76 seconds
Started Jul 01 04:26:37 PM PDT 24
Finished Jul 01 04:26:46 PM PDT 24
Peak memory 204748 kb
Host smart-2952cdc9-71cf-4c2c-9049-3c24f86e40ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312775015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2312775015
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.421215248
Short name T263
Test name
Test status
Simulation time 2897761118 ps
CPU time 5.79 seconds
Started Jul 01 04:26:36 PM PDT 24
Finished Jul 01 04:26:49 PM PDT 24
Peak memory 213416 kb
Host smart-27e36d96-564f-469d-996c-87ee67780835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421215248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.421215248
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3168337536
Short name T197
Test name
Test status
Simulation time 2240567058 ps
CPU time 3.65 seconds
Started Jul 01 04:26:54 PM PDT 24
Finished Jul 01 04:27:08 PM PDT 24
Peak memory 213508 kb
Host smart-4c672cf5-a7e8-467f-b6f4-9e834b8f9817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168337536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3168337536
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.536190261
Short name T50
Test name
Test status
Simulation time 4031481566 ps
CPU time 4.03 seconds
Started Jul 01 04:26:34 PM PDT 24
Finished Jul 01 04:26:45 PM PDT 24
Peak memory 213336 kb
Host smart-68c2f484-c9e4-4291-a9f4-853d14015b53
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=536190261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.536190261
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.1084402312
Short name T201
Test name
Test status
Simulation time 972960635 ps
CPU time 1.73 seconds
Started Jul 01 04:26:27 PM PDT 24
Finished Jul 01 04:26:38 PM PDT 24
Peak memory 205276 kb
Host smart-3fe457b8-3fe7-4ed5-8c1e-f196cd72c534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084402312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1084402312
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.4052209044
Short name T8
Test name
Test status
Simulation time 3665601568 ps
CPU time 6.43 seconds
Started Jul 01 04:26:32 PM PDT 24
Finished Jul 01 04:26:45 PM PDT 24
Peak memory 205016 kb
Host smart-0831fe88-1014-4c17-b271-a5da1f0823f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052209044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.4052209044
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.356688184
Short name T46
Test name
Test status
Simulation time 106172266 ps
CPU time 0.91 seconds
Started Jul 01 04:26:30 PM PDT 24
Finished Jul 01 04:26:38 PM PDT 24
Peak memory 204700 kb
Host smart-eebd34bd-dabf-47c0-8717-620155e72e5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356688184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.356688184
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.628791714
Short name T281
Test name
Test status
Simulation time 80848183185 ps
CPU time 223.96 seconds
Started Jul 01 04:26:09 PM PDT 24
Finished Jul 01 04:30:05 PM PDT 24
Peak memory 215232 kb
Host smart-e52dcf36-2304-4566-aff3-597cb3f3ee7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628791714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.628791714
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.92643077
Short name T3
Test name
Test status
Simulation time 3434233980 ps
CPU time 3.41 seconds
Started Jul 01 04:26:15 PM PDT 24
Finished Jul 01 04:26:31 PM PDT 24
Peak memory 221472 kb
Host smart-694eeae1-84d0-4d49-8d1f-3eec58530c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92643077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.92643077
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2550324321
Short name T244
Test name
Test status
Simulation time 19197006270 ps
CPU time 27.84 seconds
Started Jul 01 04:26:21 PM PDT 24
Finished Jul 01 04:27:00 PM PDT 24
Peak memory 213312 kb
Host smart-fe51a5c7-46b2-40d1-a4e4-3a1544e11552
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2550324321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2550324321
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3116424687
Short name T295
Test name
Test status
Simulation time 583304906 ps
CPU time 2.06 seconds
Started Jul 01 04:26:07 PM PDT 24
Finished Jul 01 04:26:20 PM PDT 24
Peak memory 204756 kb
Host smart-37ae39cd-1fcb-4ce0-ac91-967078978e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116424687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3116424687
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1829120417
Short name T290
Test name
Test status
Simulation time 1850554477 ps
CPU time 3.56 seconds
Started Jul 01 04:26:11 PM PDT 24
Finished Jul 01 04:26:27 PM PDT 24
Peak memory 205032 kb
Host smart-afb39a85-1305-49e1-bfc6-1361b2068228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829120417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1829120417
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.3223870091
Short name T63
Test name
Test status
Simulation time 1384102520 ps
CPU time 2.74 seconds
Started Jul 01 04:26:18 PM PDT 24
Finished Jul 01 04:26:33 PM PDT 24
Peak memory 228868 kb
Host smart-2e989db4-b655-4b92-874f-fd5457b4a9a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223870091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3223870091
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.1384216219
Short name T23
Test name
Test status
Simulation time 6634640864 ps
CPU time 9.63 seconds
Started Jul 01 04:26:17 PM PDT 24
Finished Jul 01 04:26:40 PM PDT 24
Peak memory 213188 kb
Host smart-e74b1e2c-5b25-4c35-bed2-38657f3071d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384216219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1384216219
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3595289435
Short name T245
Test name
Test status
Simulation time 54524131 ps
CPU time 0.79 seconds
Started Jul 01 04:26:19 PM PDT 24
Finished Jul 01 04:26:32 PM PDT 24
Peak memory 204704 kb
Host smart-80d225b1-b1d7-41fb-b7ca-debc6b893893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595289435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3595289435
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.3636787792
Short name T32
Test name
Test status
Simulation time 2504295795 ps
CPU time 3.96 seconds
Started Jul 01 04:26:16 PM PDT 24
Finished Jul 01 04:26:32 PM PDT 24
Peak memory 205008 kb
Host smart-adf6d9c8-7b5f-4623-abcf-994810fcdfc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636787792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3636787792
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.244195140
Short name T78
Test name
Test status
Simulation time 115902729 ps
CPU time 0.7 seconds
Started Jul 01 04:26:43 PM PDT 24
Finished Jul 01 04:26:51 PM PDT 24
Peak memory 204820 kb
Host smart-5b7e61a4-cd5f-4e60-98f0-695f428d0746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244195140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.244195140
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3346507939
Short name T274
Test name
Test status
Simulation time 94398290 ps
CPU time 0.9 seconds
Started Jul 01 04:26:44 PM PDT 24
Finished Jul 01 04:26:53 PM PDT 24
Peak memory 204916 kb
Host smart-df53aa11-e214-4a3c-b649-86f8ba1c7395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346507939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3346507939
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2379296802
Short name T283
Test name
Test status
Simulation time 66386153 ps
CPU time 0.73 seconds
Started Jul 01 04:26:35 PM PDT 24
Finished Jul 01 04:26:42 PM PDT 24
Peak memory 204736 kb
Host smart-147c5c64-6ddd-4b59-a5ab-31653e44d84b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379296802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2379296802
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.915323019
Short name T36
Test name
Test status
Simulation time 122460606 ps
CPU time 0.97 seconds
Started Jul 01 04:26:16 PM PDT 24
Finished Jul 01 04:26:31 PM PDT 24
Peak memory 204744 kb
Host smart-2d721e3f-a529-4ef3-b3b8-1b7cc7ec1619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915323019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.915323019
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.3660801850
Short name T44
Test name
Test status
Simulation time 5288233519 ps
CPU time 11.38 seconds
Started Jul 01 04:27:00 PM PDT 24
Finished Jul 01 04:27:24 PM PDT 24
Peak memory 213528 kb
Host smart-b7aa3d4e-109c-496b-93eb-5a86ca3d9fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660801850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.3660801850
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.4234819023
Short name T256
Test name
Test status
Simulation time 82329060 ps
CPU time 0.75 seconds
Started Jul 01 04:26:16 PM PDT 24
Finished Jul 01 04:26:30 PM PDT 24
Peak memory 204760 kb
Host smart-4c06503e-50d0-4c80-8163-98669283dc93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234819023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.4234819023
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.3171014204
Short name T150
Test name
Test status
Simulation time 6003799873 ps
CPU time 8.81 seconds
Started Jul 01 04:26:15 PM PDT 24
Finished Jul 01 04:26:37 PM PDT 24
Peak memory 213188 kb
Host smart-60b1619a-6b47-4233-b72a-e49f75669b75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171014204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3171014204
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1092337368
Short name T277
Test name
Test status
Simulation time 145038419 ps
CPU time 0.95 seconds
Started Jul 01 04:26:15 PM PDT 24
Finished Jul 01 04:26:29 PM PDT 24
Peak memory 204996 kb
Host smart-7b317d5a-4903-4650-9ac9-cfb63a84e90d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092337368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1092337368
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.2032690862
Short name T73
Test name
Test status
Simulation time 8752308590 ps
CPU time 12.29 seconds
Started Jul 01 04:26:40 PM PDT 24
Finished Jul 01 04:27:00 PM PDT 24
Peak memory 213220 kb
Host smart-aaf906ef-be95-485e-a87e-919051c308a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032690862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.2032690862
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.4091330517
Short name T217
Test name
Test status
Simulation time 57049026 ps
CPU time 0.8 seconds
Started Jul 01 04:26:44 PM PDT 24
Finished Jul 01 04:26:53 PM PDT 24
Peak memory 204920 kb
Host smart-cbf86c6b-c938-490d-98bc-bb2be5c384cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091330517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.4091330517
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2939838469
Short name T292
Test name
Test status
Simulation time 28907655 ps
CPU time 0.74 seconds
Started Jul 01 04:26:35 PM PDT 24
Finished Jul 01 04:26:43 PM PDT 24
Peak memory 204744 kb
Host smart-21526690-f028-4e32-9510-02d7c76ccba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939838469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2939838469
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1018506324
Short name T47
Test name
Test status
Simulation time 65606604 ps
CPU time 0.78 seconds
Started Jul 01 04:26:15 PM PDT 24
Finished Jul 01 04:26:29 PM PDT 24
Peak memory 205004 kb
Host smart-72ab72b7-7463-45e8-bd48-64f8b7a97d83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018506324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1018506324
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.3632468699
Short name T49
Test name
Test status
Simulation time 4211950805 ps
CPU time 11.9 seconds
Started Jul 01 04:26:14 PM PDT 24
Finished Jul 01 04:26:40 PM PDT 24
Peak memory 204912 kb
Host smart-da7654e9-fc95-4042-9f73-5bb9522b6e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632468699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3632468699
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3706036661
Short name T211
Test name
Test status
Simulation time 101996645 ps
CPU time 0.84 seconds
Started Jul 01 04:26:37 PM PDT 24
Finished Jul 01 04:26:45 PM PDT 24
Peak memory 204988 kb
Host smart-3e085650-0310-43de-8904-e02eab0becdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706036661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3706036661
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3147965823
Short name T233
Test name
Test status
Simulation time 38114774477 ps
CPU time 35.21 seconds
Started Jul 01 04:26:12 PM PDT 24
Finished Jul 01 04:27:00 PM PDT 24
Peak memory 213340 kb
Host smart-cc6cd4c0-fb2f-40f0-9dda-fa37d2f38606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147965823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3147965823
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3436092311
Short name T252
Test name
Test status
Simulation time 2062264044 ps
CPU time 2.33 seconds
Started Jul 01 04:26:14 PM PDT 24
Finished Jul 01 04:26:28 PM PDT 24
Peak memory 213456 kb
Host smart-edd5afd6-d901-4e40-b40a-8eccd02d23dd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436092311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3436092311
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1793712123
Short name T153
Test name
Test status
Simulation time 188918251 ps
CPU time 0.71 seconds
Started Jul 01 04:26:11 PM PDT 24
Finished Jul 01 04:26:25 PM PDT 24
Peak memory 204692 kb
Host smart-4d7969a6-925b-48bc-bf02-a3829d390ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793712123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1793712123
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1730628220
Short name T2
Test name
Test status
Simulation time 6111257912 ps
CPU time 11.82 seconds
Started Jul 01 04:26:19 PM PDT 24
Finished Jul 01 04:26:43 PM PDT 24
Peak memory 213292 kb
Host smart-7fc777c8-8cd3-4731-b37f-5a7f5c040d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730628220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1730628220
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.1165810601
Short name T237
Test name
Test status
Simulation time 161040899 ps
CPU time 1.12 seconds
Started Jul 01 04:26:38 PM PDT 24
Finished Jul 01 04:26:46 PM PDT 24
Peak memory 204992 kb
Host smart-a364591a-20ae-47b5-9a62-d949bf1a6045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165810601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1165810601
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.2169510181
Short name T34
Test name
Test status
Simulation time 2753221176 ps
CPU time 3.12 seconds
Started Jul 01 04:26:45 PM PDT 24
Finished Jul 01 04:26:56 PM PDT 24
Peak memory 204916 kb
Host smart-d0ade17b-082d-4a17-8ac9-5e4b42488bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169510181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.2169510181
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.47859320
Short name T206
Test name
Test status
Simulation time 62623244 ps
CPU time 0.82 seconds
Started Jul 01 04:26:27 PM PDT 24
Finished Jul 01 04:26:37 PM PDT 24
Peak memory 204712 kb
Host smart-ed5a108b-1680-4c98-8efd-6a499adc61f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47859320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.47859320
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.4188357312
Short name T236
Test name
Test status
Simulation time 63485999 ps
CPU time 0.86 seconds
Started Jul 01 04:26:32 PM PDT 24
Finished Jul 01 04:26:40 PM PDT 24
Peak memory 205012 kb
Host smart-a1e4175d-67a1-412b-890d-fe96f6a0668c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188357312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.4188357312
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.876945454
Short name T183
Test name
Test status
Simulation time 2974960297 ps
CPU time 6.03 seconds
Started Jul 01 04:26:45 PM PDT 24
Finished Jul 01 04:26:59 PM PDT 24
Peak memory 213460 kb
Host smart-9ac3237f-e350-49d6-8b0a-d1dcf228e98c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876945454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.876945454
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3617661564
Short name T39
Test name
Test status
Simulation time 54436747 ps
CPU time 0.83 seconds
Started Jul 01 04:26:22 PM PDT 24
Finished Jul 01 04:26:34 PM PDT 24
Peak memory 204748 kb
Host smart-e7dd1532-0c9e-48e0-b993-4d659dba3f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617661564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3617661564
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.2663995626
Short name T13
Test name
Test status
Simulation time 3351947906 ps
CPU time 9.76 seconds
Started Jul 01 04:26:29 PM PDT 24
Finished Jul 01 04:26:47 PM PDT 24
Peak memory 213172 kb
Host smart-d9e1b64e-2afc-47ce-a041-e479e7f97f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663995626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2663995626
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.4145425100
Short name T199
Test name
Test status
Simulation time 34487538 ps
CPU time 0.72 seconds
Started Jul 01 04:26:33 PM PDT 24
Finished Jul 01 04:26:41 PM PDT 24
Peak memory 204740 kb
Host smart-441f69f6-3c25-49fe-9b42-cad0a1d95e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145425100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.4145425100
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.1092616613
Short name T154
Test name
Test status
Simulation time 3665722265 ps
CPU time 10.38 seconds
Started Jul 01 04:26:32 PM PDT 24
Finished Jul 01 04:26:49 PM PDT 24
Peak memory 213172 kb
Host smart-8dafd641-3482-42c3-bd1b-f8b641bb27ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092616613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1092616613
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2941506427
Short name T196
Test name
Test status
Simulation time 38949247 ps
CPU time 0.71 seconds
Started Jul 01 04:26:18 PM PDT 24
Finished Jul 01 04:26:31 PM PDT 24
Peak memory 204752 kb
Host smart-15faa1a0-18a8-46a5-8700-dcdce62a99fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941506427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2941506427
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.510182288
Short name T221
Test name
Test status
Simulation time 218797988 ps
CPU time 0.81 seconds
Started Jul 01 04:26:23 PM PDT 24
Finished Jul 01 04:26:34 PM PDT 24
Peak memory 204752 kb
Host smart-bef29ac2-3002-46ea-bd85-0374fc26775e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510182288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.510182288
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.3873029097
Short name T179
Test name
Test status
Simulation time 12423341299 ps
CPU time 10.34 seconds
Started Jul 01 04:26:44 PM PDT 24
Finished Jul 01 04:27:03 PM PDT 24
Peak memory 213184 kb
Host smart-a388a8a1-ceaa-4645-ab19-6167ab8812ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873029097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3873029097
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3538481598
Short name T194
Test name
Test status
Simulation time 77710881 ps
CPU time 0.74 seconds
Started Jul 01 04:26:40 PM PDT 24
Finished Jul 01 04:26:48 PM PDT 24
Peak memory 204756 kb
Host smart-cb31b366-65de-432e-abe5-84efe96a86a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538481598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3538481598
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.2422399876
Short name T185
Test name
Test status
Simulation time 6889255403 ps
CPU time 5.45 seconds
Started Jul 01 04:26:28 PM PDT 24
Finished Jul 01 04:26:42 PM PDT 24
Peak memory 214244 kb
Host smart-e91ebe0e-1ac3-4207-b383-e29dfee379e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422399876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2422399876
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2754155733
Short name T62
Test name
Test status
Simulation time 86359154 ps
CPU time 0.75 seconds
Started Jul 01 04:26:28 PM PDT 24
Finished Jul 01 04:26:37 PM PDT 24
Peak memory 204948 kb
Host smart-31ac8774-059b-4ac2-af2b-f33bc61a8f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754155733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2754155733
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2016929743
Short name T131
Test name
Test status
Simulation time 60045625 ps
CPU time 0.73 seconds
Started Jul 01 04:26:51 PM PDT 24
Finished Jul 01 04:27:03 PM PDT 24
Peak memory 205012 kb
Host smart-48fe82a0-d3ec-491d-a591-2e5f69cf4b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016929743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2016929743
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.863691726
Short name T26
Test name
Test status
Simulation time 12078004280 ps
CPU time 12.03 seconds
Started Jul 01 04:26:36 PM PDT 24
Finished Jul 01 04:26:55 PM PDT 24
Peak memory 213268 kb
Host smart-91180753-f3ba-4c78-ba89-ee2dc6ed7d2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863691726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.863691726
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3610853307
Short name T74
Test name
Test status
Simulation time 72667813 ps
CPU time 0.69 seconds
Started Jul 01 04:26:05 PM PDT 24
Finished Jul 01 04:26:17 PM PDT 24
Peak memory 204744 kb
Host smart-c2cddd6a-8be2-488d-a69a-ab5dfdce06c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610853307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3610853307
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1920614786
Short name T224
Test name
Test status
Simulation time 7744870000 ps
CPU time 8.66 seconds
Started Jul 01 04:26:15 PM PDT 24
Finished Jul 01 04:26:37 PM PDT 24
Peak memory 213388 kb
Host smart-74be3a84-23b8-40ee-8448-63bbf7a7e300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920614786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1920614786
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2311747509
Short name T279
Test name
Test status
Simulation time 1934652674 ps
CPU time 6.37 seconds
Started Jul 01 04:26:10 PM PDT 24
Finished Jul 01 04:26:29 PM PDT 24
Peak memory 213492 kb
Host smart-9824fcf6-6cfb-4645-8f16-4ad26cd1811b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311747509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2311747509
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1398785412
Short name T142
Test name
Test status
Simulation time 986090369 ps
CPU time 3.05 seconds
Started Jul 01 04:26:34 PM PDT 24
Finished Jul 01 04:26:44 PM PDT 24
Peak memory 205068 kb
Host smart-04e362dc-05f1-4545-a8b3-1f0e7a40fb48
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398785412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1398785412
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.573139821
Short name T262
Test name
Test status
Simulation time 217217955 ps
CPU time 1.25 seconds
Started Jul 01 04:26:12 PM PDT 24
Finished Jul 01 04:26:26 PM PDT 24
Peak memory 204752 kb
Host smart-a1e68a82-ac1b-4477-a57a-9838f1585044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573139821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.573139821
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.384156982
Short name T284
Test name
Test status
Simulation time 11160340858 ps
CPU time 23.61 seconds
Started Jul 01 04:26:14 PM PDT 24
Finished Jul 01 04:26:51 PM PDT 24
Peak memory 205064 kb
Host smart-8911f9df-3724-4c12-85a1-496e4302fb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384156982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.384156982
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.4092492452
Short name T65
Test name
Test status
Simulation time 2366392990 ps
CPU time 7.66 seconds
Started Jul 01 04:26:42 PM PDT 24
Finished Jul 01 04:26:57 PM PDT 24
Peak memory 237984 kb
Host smart-89c23828-0f7d-4b8b-aab9-d54cbca76e86
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092492452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.4092492452
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.4168795752
Short name T146
Test name
Test status
Simulation time 12811925042 ps
CPU time 10.23 seconds
Started Jul 01 04:26:10 PM PDT 24
Finished Jul 01 04:26:33 PM PDT 24
Peak memory 213184 kb
Host smart-022c6566-8fb3-4e8d-a464-4435b588f352
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168795752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.4168795752
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.288170864
Short name T137
Test name
Test status
Simulation time 74865523 ps
CPU time 0.87 seconds
Started Jul 01 04:26:46 PM PDT 24
Finished Jul 01 04:26:55 PM PDT 24
Peak memory 204720 kb
Host smart-f357f93f-c5f7-4088-94f2-a642ef1ddbd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288170864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.288170864
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.2777253697
Short name T43
Test name
Test status
Simulation time 1263118182 ps
CPU time 2.97 seconds
Started Jul 01 04:26:31 PM PDT 24
Finished Jul 01 04:26:41 PM PDT 24
Peak memory 205076 kb
Host smart-b8b19e2d-355e-4202-ad11-118306e43adc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777253697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2777253697
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2776352309
Short name T250
Test name
Test status
Simulation time 46215307 ps
CPU time 0.71 seconds
Started Jul 01 04:26:37 PM PDT 24
Finished Jul 01 04:26:45 PM PDT 24
Peak memory 205052 kb
Host smart-e763bff0-375f-40ec-8644-53558f21ef1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776352309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2776352309
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.642266429
Short name T136
Test name
Test status
Simulation time 34897190 ps
CPU time 0.75 seconds
Started Jul 01 04:26:29 PM PDT 24
Finished Jul 01 04:26:38 PM PDT 24
Peak memory 204748 kb
Host smart-55636250-880e-4af5-b997-46f8e0d0d1ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642266429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.642266429
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3136150921
Short name T241
Test name
Test status
Simulation time 136197032 ps
CPU time 0.79 seconds
Started Jul 01 04:26:33 PM PDT 24
Finished Jul 01 04:26:41 PM PDT 24
Peak memory 204748 kb
Host smart-58e24cf0-5c1b-47a4-9284-5a197c351f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136150921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3136150921
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.456602208
Short name T15
Test name
Test status
Simulation time 5954183424 ps
CPU time 10.59 seconds
Started Jul 01 04:26:36 PM PDT 24
Finished Jul 01 04:26:53 PM PDT 24
Peak memory 205176 kb
Host smart-4cde1048-61a6-4081-935d-5f12d0c1debb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456602208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.456602208
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.976720166
Short name T18
Test name
Test status
Simulation time 3822026049 ps
CPU time 9.81 seconds
Started Jul 01 04:26:48 PM PDT 24
Finished Jul 01 04:27:08 PM PDT 24
Peak memory 205316 kb
Host smart-97ecca07-db88-494a-883e-48164c02f9a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976720166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.976720166
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3433417747
Short name T214
Test name
Test status
Simulation time 76066497 ps
CPU time 0.78 seconds
Started Jul 01 04:26:30 PM PDT 24
Finished Jul 01 04:26:39 PM PDT 24
Peak memory 204732 kb
Host smart-f10c757f-24fc-4780-bc1f-72e5e89d4b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433417747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3433417747
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.345185614
Short name T238
Test name
Test status
Simulation time 53158361 ps
CPU time 0.79 seconds
Started Jul 01 04:26:42 PM PDT 24
Finished Jul 01 04:26:50 PM PDT 24
Peak memory 204864 kb
Host smart-6d46e977-1d47-4223-8be8-57050038476d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345185614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.345185614
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.1106186124
Short name T17
Test name
Test status
Simulation time 6310747665 ps
CPU time 11.48 seconds
Started Jul 01 04:26:43 PM PDT 24
Finished Jul 01 04:27:01 PM PDT 24
Peak memory 204924 kb
Host smart-ece7d0c6-e8e0-441b-a0da-5c1fda83d8e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106186124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1106186124
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2816909006
Short name T249
Test name
Test status
Simulation time 57983642 ps
CPU time 0.71 seconds
Started Jul 01 04:26:42 PM PDT 24
Finished Jul 01 04:26:51 PM PDT 24
Peak memory 204684 kb
Host smart-5609b4bb-9ad7-47ee-85b2-db2069e2ec38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816909006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2816909006
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2080079768
Short name T242
Test name
Test status
Simulation time 40814106 ps
CPU time 0.75 seconds
Started Jul 01 04:26:47 PM PDT 24
Finished Jul 01 04:26:57 PM PDT 24
Peak memory 204748 kb
Host smart-87d935bd-c53a-43e6-a88e-4452a2f3a056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080079768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2080079768
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2210202976
Short name T278
Test name
Test status
Simulation time 152037393 ps
CPU time 0.96 seconds
Started Jul 01 04:26:46 PM PDT 24
Finished Jul 01 04:26:56 PM PDT 24
Peak memory 204752 kb
Host smart-fea6eba3-ac41-4144-9d28-7d3a2b372be6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210202976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2210202976
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.3057195044
Short name T5
Test name
Test status
Simulation time 8496675936 ps
CPU time 7.22 seconds
Started Jul 01 04:26:30 PM PDT 24
Finished Jul 01 04:26:45 PM PDT 24
Peak memory 213136 kb
Host smart-5f5b232e-27f0-4cc7-b94b-4364413fd976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057195044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3057195044
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.23064335
Short name T76
Test name
Test status
Simulation time 164763632 ps
CPU time 1.09 seconds
Started Jul 01 04:26:02 PM PDT 24
Finished Jul 01 04:26:14 PM PDT 24
Peak memory 204692 kb
Host smart-c5d16617-8b88-426a-9b30-fe237028f8ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23064335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.23064335
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3536907427
Short name T77
Test name
Test status
Simulation time 16114498748 ps
CPU time 6.66 seconds
Started Jul 01 04:26:17 PM PDT 24
Finished Jul 01 04:26:36 PM PDT 24
Peak memory 205116 kb
Host smart-61521949-f09b-41a7-ab25-26f82a2fcc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536907427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3536907427
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3385463332
Short name T220
Test name
Test status
Simulation time 14778366640 ps
CPU time 11.78 seconds
Started Jul 01 04:26:10 PM PDT 24
Finished Jul 01 04:26:35 PM PDT 24
Peak memory 213352 kb
Host smart-9eec4ed9-11e5-4ea5-8823-182da2ee6e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385463332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3385463332
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1642161888
Short name T267
Test name
Test status
Simulation time 4200987670 ps
CPU time 3.94 seconds
Started Jul 01 04:26:11 PM PDT 24
Finished Jul 01 04:26:28 PM PDT 24
Peak memory 213284 kb
Host smart-4e61a620-a4a5-4d9a-951f-73c0afc214ae
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642161888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1642161888
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3061074643
Short name T210
Test name
Test status
Simulation time 2366986683 ps
CPU time 2.58 seconds
Started Jul 01 04:26:05 PM PDT 24
Finished Jul 01 04:26:25 PM PDT 24
Peak memory 205348 kb
Host smart-a8a63730-d866-4844-a9a0-c7cb402dac65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061074643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3061074643
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.1355070498
Short name T186
Test name
Test status
Simulation time 6663075389 ps
CPU time 9.95 seconds
Started Jul 01 04:26:10 PM PDT 24
Finished Jul 01 04:26:33 PM PDT 24
Peak memory 213096 kb
Host smart-3307f320-3ec1-4f78-8629-65974998fa7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355070498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1355070498
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3904213192
Short name T257
Test name
Test status
Simulation time 147656305 ps
CPU time 0.77 seconds
Started Jul 01 04:26:04 PM PDT 24
Finished Jul 01 04:26:16 PM PDT 24
Peak memory 204688 kb
Host smart-713fe1a0-d2af-4193-8658-45da74e21d9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904213192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3904213192
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.468039407
Short name T293
Test name
Test status
Simulation time 1005530862 ps
CPU time 2.24 seconds
Started Jul 01 04:26:15 PM PDT 24
Finished Jul 01 04:26:30 PM PDT 24
Peak memory 213260 kb
Host smart-b2126fbe-5e60-4d84-a47c-1fc7aa3652dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468039407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.468039407
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2360337875
Short name T269
Test name
Test status
Simulation time 1043166264 ps
CPU time 3.76 seconds
Started Jul 01 04:26:04 PM PDT 24
Finished Jul 01 04:26:19 PM PDT 24
Peak memory 205072 kb
Host smart-e33bdc46-cd9f-4902-9462-ccefbe708872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360337875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2360337875
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3033876913
Short name T213
Test name
Test status
Simulation time 7895838387 ps
CPU time 6.19 seconds
Started Jul 01 04:26:20 PM PDT 24
Finished Jul 01 04:26:38 PM PDT 24
Peak memory 213280 kb
Host smart-62a133c9-3507-4b20-82ab-f9c2b1b749fb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3033876913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3033876913
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1986479508
Short name T219
Test name
Test status
Simulation time 709566449 ps
CPU time 2.29 seconds
Started Jul 01 04:26:05 PM PDT 24
Finished Jul 01 04:26:19 PM PDT 24
Peak memory 205064 kb
Host smart-6f74cc94-4062-4283-aea9-2397c07b7010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986479508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1986479508
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.3401845477
Short name T156
Test name
Test status
Simulation time 15096818489 ps
CPU time 36.43 seconds
Started Jul 01 04:26:04 PM PDT 24
Finished Jul 01 04:26:52 PM PDT 24
Peak memory 213180 kb
Host smart-47cf768d-9429-4aa7-bcc1-373b7e4ef13e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401845477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3401845477
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.555159088
Short name T286
Test name
Test status
Simulation time 50958482 ps
CPU time 0.73 seconds
Started Jul 01 04:26:19 PM PDT 24
Finished Jul 01 04:26:32 PM PDT 24
Peak memory 204700 kb
Host smart-4b710e69-b1a0-4ec8-bb4d-63ef2c1f029c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555159088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.555159088
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3986450215
Short name T152
Test name
Test status
Simulation time 9591042804 ps
CPU time 27.1 seconds
Started Jul 01 04:26:34 PM PDT 24
Finished Jul 01 04:27:08 PM PDT 24
Peak memory 213368 kb
Host smart-df0284d1-cbea-4c39-9dac-37c20fbbcfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986450215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3986450215
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.326046749
Short name T287
Test name
Test status
Simulation time 2321536974 ps
CPU time 1.75 seconds
Started Jul 01 04:26:44 PM PDT 24
Finished Jul 01 04:26:55 PM PDT 24
Peak memory 205220 kb
Host smart-36a22989-631c-4e05-8b6f-7c1bdbe71ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326046749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.326046749
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3547830205
Short name T51
Test name
Test status
Simulation time 3531648363 ps
CPU time 11.27 seconds
Started Jul 01 04:26:39 PM PDT 24
Finished Jul 01 04:26:58 PM PDT 24
Peak memory 205164 kb
Host smart-e2dfb0a3-2e40-4208-935b-94a2e2188080
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3547830205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3547830205
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3196472006
Short name T240
Test name
Test status
Simulation time 2515240391 ps
CPU time 2.8 seconds
Started Jul 01 04:26:04 PM PDT 24
Finished Jul 01 04:26:18 PM PDT 24
Peak memory 213268 kb
Host smart-f355f97e-d73b-4b1c-9357-61b07bc10cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196472006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3196472006
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.2576825871
Short name T157
Test name
Test status
Simulation time 3885268400 ps
CPU time 2.39 seconds
Started Jul 01 04:26:14 PM PDT 24
Finished Jul 01 04:26:29 PM PDT 24
Peak memory 213100 kb
Host smart-57591159-a01f-4ec6-be20-e6b67078f2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576825871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2576825871
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1321771596
Short name T215
Test name
Test status
Simulation time 62326857 ps
CPU time 0.7 seconds
Started Jul 01 04:26:51 PM PDT 24
Finished Jul 01 04:27:01 PM PDT 24
Peak memory 204684 kb
Host smart-d777a4a3-f23d-49d1-a1bb-9106f2025698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321771596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1321771596
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3124895327
Short name T147
Test name
Test status
Simulation time 2002412559 ps
CPU time 2.64 seconds
Started Jul 01 04:26:11 PM PDT 24
Finished Jul 01 04:26:26 PM PDT 24
Peak memory 213392 kb
Host smart-71c7e864-0ff3-4065-a88e-5afd737337ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124895327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3124895327
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3472983777
Short name T207
Test name
Test status
Simulation time 1200432718 ps
CPU time 3.93 seconds
Started Jul 01 04:26:12 PM PDT 24
Finished Jul 01 04:26:28 PM PDT 24
Peak memory 205040 kb
Host smart-52e3d9a8-c095-4b26-a94b-01345a6cdb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472983777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3472983777
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.702143639
Short name T265
Test name
Test status
Simulation time 1735330516 ps
CPU time 3.9 seconds
Started Jul 01 04:26:16 PM PDT 24
Finished Jul 01 04:26:33 PM PDT 24
Peak memory 213280 kb
Host smart-ea12da85-0a5c-45ea-9b7d-db002f960dbb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=702143639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.702143639
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3866522462
Short name T230
Test name
Test status
Simulation time 7736733415 ps
CPU time 10.29 seconds
Started Jul 01 04:26:19 PM PDT 24
Finished Jul 01 04:26:41 PM PDT 24
Peak memory 213344 kb
Host smart-c590d22b-cd7f-4ec1-8f76-75eb7ea46f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866522462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3866522462
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.3240186836
Short name T35
Test name
Test status
Simulation time 12030738560 ps
CPU time 11.58 seconds
Started Jul 01 04:26:48 PM PDT 24
Finished Jul 01 04:27:09 PM PDT 24
Peak memory 213196 kb
Host smart-8ff43b18-9967-443f-84b9-cbcb2131c0dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240186836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3240186836
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2919774691
Short name T191
Test name
Test status
Simulation time 66792292 ps
CPU time 0.7 seconds
Started Jul 01 04:26:37 PM PDT 24
Finished Jul 01 04:26:44 PM PDT 24
Peak memory 204684 kb
Host smart-b5f2a4a9-d581-403f-99f1-4abfb7c8c236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919774691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2919774691
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.228066380
Short name T212
Test name
Test status
Simulation time 5178559661 ps
CPU time 16.05 seconds
Started Jul 01 04:26:21 PM PDT 24
Finished Jul 01 04:26:48 PM PDT 24
Peak memory 213392 kb
Host smart-9f96bffc-e4f2-4aa3-804d-c75917b606d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228066380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.228066380
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.4112512729
Short name T138
Test name
Test status
Simulation time 1766282459 ps
CPU time 4.35 seconds
Started Jul 01 04:26:33 PM PDT 24
Finished Jul 01 04:26:44 PM PDT 24
Peak memory 213496 kb
Host smart-218b3229-ac1c-4664-bb8b-d5228d6ecf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112512729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.4112512729
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.896088454
Short name T202
Test name
Test status
Simulation time 3530102585 ps
CPU time 4.05 seconds
Started Jul 01 04:26:09 PM PDT 24
Finished Jul 01 04:26:25 PM PDT 24
Peak memory 205292 kb
Host smart-263e001a-baa6-42bd-8953-8c1d97a0b90b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896088454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.896088454
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1346204991
Short name T280
Test name
Test status
Simulation time 2850410959 ps
CPU time 6.6 seconds
Started Jul 01 04:26:13 PM PDT 24
Finished Jul 01 04:26:32 PM PDT 24
Peak memory 205136 kb
Host smart-83acd697-0cba-4c89-a1d6-6b7e396598ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346204991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1346204991
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.472703501
Short name T190
Test name
Test status
Simulation time 6443273685 ps
CPU time 3.81 seconds
Started Jul 01 04:26:15 PM PDT 24
Finished Jul 01 04:26:32 PM PDT 24
Peak memory 213120 kb
Host smart-5dc4d285-7e16-428e-871c-87b6fdcbf4a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472703501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.472703501
Directory /workspace/9.rv_dm_stress_all/latest
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