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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.08 95.27 79.45 89.42 74.36 85.50 97.79 52.76


Total test records in report: 431
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T292 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2301399802 Jul 03 04:47:02 PM PDT 24 Jul 03 04:47:46 PM PDT 24 16083730353 ps
T128 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3832957880 Jul 03 04:47:03 PM PDT 24 Jul 03 04:47:11 PM PDT 24 1980647644 ps
T129 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4119950280 Jul 03 04:47:11 PM PDT 24 Jul 03 04:47:14 PM PDT 24 493695890 ps
T293 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1429155538 Jul 03 04:47:03 PM PDT 24 Jul 03 04:47:05 PM PDT 24 48693362 ps
T294 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1260745204 Jul 03 04:47:37 PM PDT 24 Jul 03 04:48:11 PM PDT 24 24178126176 ps
T295 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2505038435 Jul 03 04:47:04 PM PDT 24 Jul 03 04:47:05 PM PDT 24 331551888 ps
T296 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3781415709 Jul 03 04:46:59 PM PDT 24 Jul 03 04:47:00 PM PDT 24 117163093 ps
T297 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.87004501 Jul 03 04:47:13 PM PDT 24 Jul 03 04:47:33 PM PDT 24 6575192920 ps
T171 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2768296752 Jul 03 04:47:32 PM PDT 24 Jul 03 04:47:51 PM PDT 24 1879853583 ps
T101 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3131281912 Jul 03 04:47:11 PM PDT 24 Jul 03 04:47:39 PM PDT 24 813503569 ps
T130 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.928859433 Jul 03 04:47:15 PM PDT 24 Jul 03 04:47:21 PM PDT 24 1577035243 ps
T168 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2227323839 Jul 03 04:47:23 PM PDT 24 Jul 03 04:47:45 PM PDT 24 3874087541 ps
T298 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3759642587 Jul 03 04:47:32 PM PDT 24 Jul 03 04:47:34 PM PDT 24 201318085 ps
T299 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2134662330 Jul 03 04:47:16 PM PDT 24 Jul 03 04:47:20 PM PDT 24 1041970793 ps
T300 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.168360372 Jul 03 04:47:08 PM PDT 24 Jul 03 04:47:09 PM PDT 24 128733714 ps
T102 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3449915215 Jul 03 04:47:10 PM PDT 24 Jul 03 04:47:11 PM PDT 24 76412887 ps
T301 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1177052363 Jul 03 04:47:09 PM PDT 24 Jul 03 04:48:17 PM PDT 24 113255357592 ps
T302 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3078773172 Jul 03 04:47:22 PM PDT 24 Jul 03 04:47:35 PM PDT 24 4676844950 ps
T303 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.793444092 Jul 03 04:47:23 PM PDT 24 Jul 03 04:47:27 PM PDT 24 150942592 ps
T304 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4164036310 Jul 03 04:47:24 PM PDT 24 Jul 03 04:47:30 PM PDT 24 5595905249 ps
T305 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1245187167 Jul 03 04:46:58 PM PDT 24 Jul 03 04:47:04 PM PDT 24 3562730740 ps
T105 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4159325228 Jul 03 04:47:12 PM PDT 24 Jul 03 04:47:14 PM PDT 24 88167861 ps
T306 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1577549591 Jul 03 04:47:05 PM PDT 24 Jul 03 04:47:31 PM PDT 24 17316446152 ps
T131 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.316293303 Jul 03 04:47:23 PM PDT 24 Jul 03 04:47:28 PM PDT 24 706703998 ps
T165 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1761342792 Jul 03 04:47:29 PM PDT 24 Jul 03 04:47:52 PM PDT 24 5903947829 ps
T175 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4148148353 Jul 03 04:47:25 PM PDT 24 Jul 03 04:49:07 PM PDT 24 56031367044 ps
T307 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3282115274 Jul 03 04:47:32 PM PDT 24 Jul 03 04:47:35 PM PDT 24 873364456 ps
T308 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2949274318 Jul 03 04:47:05 PM PDT 24 Jul 03 04:47:07 PM PDT 24 572195676 ps
T132 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2345698233 Jul 03 04:47:33 PM PDT 24 Jul 03 04:47:38 PM PDT 24 182226246 ps
T309 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1631376812 Jul 03 04:47:01 PM PDT 24 Jul 03 04:47:06 PM PDT 24 214517361 ps
T310 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4148401521 Jul 03 04:47:11 PM PDT 24 Jul 03 04:47:12 PM PDT 24 641201922 ps
T106 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3711410168 Jul 03 04:47:10 PM PDT 24 Jul 03 04:47:37 PM PDT 24 1222077879 ps
T311 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4204196547 Jul 03 04:47:26 PM PDT 24 Jul 03 04:47:30 PM PDT 24 1797121005 ps
T312 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1727616870 Jul 03 04:47:28 PM PDT 24 Jul 03 04:47:31 PM PDT 24 194459282 ps
T313 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2648069142 Jul 03 04:47:02 PM PDT 24 Jul 03 04:47:38 PM PDT 24 4071886472 ps
T166 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4167270069 Jul 03 04:47:13 PM PDT 24 Jul 03 04:47:31 PM PDT 24 3994771782 ps
T314 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1037034417 Jul 03 04:47:13 PM PDT 24 Jul 03 04:47:17 PM PDT 24 2129808753 ps
T115 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3045439792 Jul 03 04:47:18 PM PDT 24 Jul 03 04:47:21 PM PDT 24 435460989 ps
T315 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2458591136 Jul 03 04:47:37 PM PDT 24 Jul 03 04:48:12 PM PDT 24 12231516359 ps
T316 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.513765066 Jul 03 04:47:34 PM PDT 24 Jul 03 04:47:37 PM PDT 24 321870459 ps
T125 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2913261526 Jul 03 04:47:27 PM PDT 24 Jul 03 04:47:29 PM PDT 24 95456209 ps
T317 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4287465708 Jul 03 04:47:06 PM PDT 24 Jul 03 04:47:39 PM PDT 24 11791748940 ps
T318 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3579790043 Jul 03 04:47:32 PM PDT 24 Jul 03 04:47:35 PM PDT 24 333018224 ps
T319 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.4083802134 Jul 03 04:47:09 PM PDT 24 Jul 03 04:47:20 PM PDT 24 1092333224 ps
T107 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2174289252 Jul 03 04:47:23 PM PDT 24 Jul 03 04:47:27 PM PDT 24 334729542 ps
T320 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.57340667 Jul 03 04:47:26 PM PDT 24 Jul 03 04:47:29 PM PDT 24 131127267 ps
T321 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2211912565 Jul 03 04:47:31 PM PDT 24 Jul 03 04:47:42 PM PDT 24 4730798481 ps
T322 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.250202483 Jul 03 04:47:00 PM PDT 24 Jul 03 04:47:02 PM PDT 24 200957774 ps
T323 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.733205827 Jul 03 04:47:19 PM PDT 24 Jul 03 04:47:22 PM PDT 24 1282952589 ps
T167 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.114276353 Jul 03 04:47:17 PM PDT 24 Jul 03 04:47:37 PM PDT 24 2176354028 ps
T324 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3085275939 Jul 03 04:47:21 PM PDT 24 Jul 03 04:47:35 PM PDT 24 1640508878 ps
T325 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2511865886 Jul 03 04:47:12 PM PDT 24 Jul 03 04:47:13 PM PDT 24 422619241 ps
T326 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3218120850 Jul 03 04:47:05 PM PDT 24 Jul 03 04:47:06 PM PDT 24 162460787 ps
T176 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3565449026 Jul 03 04:47:13 PM PDT 24 Jul 03 04:48:11 PM PDT 24 23364252877 ps
T327 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3499921524 Jul 03 04:47:03 PM PDT 24 Jul 03 04:47:05 PM PDT 24 37956414 ps
T328 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.543172365 Jul 03 04:47:31 PM PDT 24 Jul 03 04:47:48 PM PDT 24 12330212430 ps
T116 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.717760166 Jul 03 04:47:25 PM PDT 24 Jul 03 04:47:28 PM PDT 24 323540472 ps
T329 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3256890425 Jul 03 04:47:23 PM PDT 24 Jul 03 04:47:30 PM PDT 24 2327619579 ps
T330 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2843621898 Jul 03 04:47:12 PM PDT 24 Jul 03 04:47:14 PM PDT 24 772193614 ps
T108 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.81337994 Jul 03 04:47:16 PM PDT 24 Jul 03 04:47:20 PM PDT 24 129402644 ps
T122 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2135558657 Jul 03 04:47:24 PM PDT 24 Jul 03 04:47:28 PM PDT 24 232342615 ps
T331 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.718596186 Jul 03 04:47:26 PM PDT 24 Jul 03 04:47:31 PM PDT 24 589430446 ps
T109 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.575978375 Jul 03 04:47:31 PM PDT 24 Jul 03 04:47:38 PM PDT 24 589539900 ps
T332 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.406844004 Jul 03 04:47:01 PM PDT 24 Jul 03 04:47:10 PM PDT 24 14317762998 ps
T333 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.961185610 Jul 03 04:47:19 PM PDT 24 Jul 03 04:47:22 PM PDT 24 1211066524 ps
T334 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1192790573 Jul 03 04:47:00 PM PDT 24 Jul 03 04:48:17 PM PDT 24 14965682668 ps
T335 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3700363490 Jul 03 04:47:23 PM PDT 24 Jul 03 04:47:33 PM PDT 24 6694714646 ps
T336 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3702744845 Jul 03 04:47:33 PM PDT 24 Jul 03 04:47:50 PM PDT 24 5576222229 ps
T117 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1569463974 Jul 03 04:47:08 PM PDT 24 Jul 03 04:47:10 PM PDT 24 77632481 ps
T337 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2615669107 Jul 03 04:47:01 PM PDT 24 Jul 03 04:47:04 PM PDT 24 2396505604 ps
T338 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2549212348 Jul 03 04:47:23 PM PDT 24 Jul 03 04:50:58 PM PDT 24 83681548539 ps
T339 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3286303107 Jul 03 04:47:21 PM PDT 24 Jul 03 04:48:00 PM PDT 24 59286600166 ps
T118 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.268731592 Jul 03 04:47:32 PM PDT 24 Jul 03 04:47:34 PM PDT 24 201280547 ps
T123 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2374573202 Jul 03 04:47:31 PM PDT 24 Jul 03 04:47:40 PM PDT 24 1085347871 ps
T340 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2473732774 Jul 03 04:47:12 PM PDT 24 Jul 03 04:47:33 PM PDT 24 19567801988 ps
T110 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1991903485 Jul 03 04:47:32 PM PDT 24 Jul 03 04:47:41 PM PDT 24 5631479751 ps
T341 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.293344895 Jul 03 04:47:03 PM PDT 24 Jul 03 04:47:18 PM PDT 24 12473998358 ps
T124 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3040682606 Jul 03 04:47:11 PM PDT 24 Jul 03 04:47:15 PM PDT 24 597628722 ps
T342 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4162266780 Jul 03 04:47:11 PM PDT 24 Jul 03 04:47:14 PM PDT 24 245310864 ps
T111 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2812982099 Jul 03 04:47:33 PM PDT 24 Jul 03 04:47:40 PM PDT 24 574915204 ps
T343 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.493978246 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:41 PM PDT 24 1296926870 ps
T344 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2442113702 Jul 03 04:47:29 PM PDT 24 Jul 03 04:47:40 PM PDT 24 3775774293 ps
T345 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2303982745 Jul 03 04:47:01 PM PDT 24 Jul 03 04:47:25 PM PDT 24 16561967640 ps
T174 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1419543750 Jul 03 04:47:01 PM PDT 24 Jul 03 04:47:22 PM PDT 24 15662240209 ps
T346 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1334740112 Jul 03 04:47:29 PM PDT 24 Jul 03 04:47:32 PM PDT 24 339644649 ps
T347 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3009700241 Jul 03 04:47:24 PM PDT 24 Jul 03 04:47:32 PM PDT 24 603222063 ps
T119 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3068389940 Jul 03 04:47:07 PM PDT 24 Jul 03 04:47:10 PM PDT 24 186004028 ps
T348 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.843051046 Jul 03 04:47:02 PM PDT 24 Jul 03 04:47:04 PM PDT 24 88874010 ps
T349 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2007407158 Jul 03 04:47:11 PM PDT 24 Jul 03 04:47:54 PM PDT 24 60714753086 ps
T350 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.338443455 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:39 PM PDT 24 496028102 ps
T351 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3197894101 Jul 03 04:47:23 PM PDT 24 Jul 03 04:47:27 PM PDT 24 106797283 ps
T352 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.4204783738 Jul 03 04:47:06 PM PDT 24 Jul 03 04:47:40 PM PDT 24 9158378268 ps
T353 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1750924377 Jul 03 04:47:03 PM PDT 24 Jul 03 04:47:05 PM PDT 24 187667392 ps
T354 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.316841744 Jul 03 04:47:05 PM PDT 24 Jul 03 04:47:06 PM PDT 24 166874604 ps
T355 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.763446377 Jul 03 04:47:03 PM PDT 24 Jul 03 04:47:22 PM PDT 24 6623049839 ps
T356 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1470822990 Jul 03 04:47:20 PM PDT 24 Jul 03 04:47:24 PM PDT 24 868429805 ps
T112 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.57250873 Jul 03 04:47:00 PM PDT 24 Jul 03 04:48:08 PM PDT 24 1760155048 ps
T120 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.122105094 Jul 03 04:47:22 PM PDT 24 Jul 03 04:47:24 PM PDT 24 127547031 ps
T357 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.845546023 Jul 03 04:47:02 PM PDT 24 Jul 03 04:47:06 PM PDT 24 196826097 ps
T358 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3321231730 Jul 03 04:47:24 PM PDT 24 Jul 03 04:47:25 PM PDT 24 122984058 ps
T359 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.615788108 Jul 03 04:47:25 PM PDT 24 Jul 03 04:48:42 PM PDT 24 27203943357 ps
T169 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3313034254 Jul 03 04:47:34 PM PDT 24 Jul 03 04:47:44 PM PDT 24 826212613 ps
T360 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3687227917 Jul 03 04:47:25 PM PDT 24 Jul 03 04:47:27 PM PDT 24 97223820 ps
T361 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.954057284 Jul 03 04:47:12 PM PDT 24 Jul 03 04:47:13 PM PDT 24 120476818 ps
T362 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.149577829 Jul 03 04:47:23 PM PDT 24 Jul 03 04:47:28 PM PDT 24 102920129 ps
T172 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2663333206 Jul 03 04:47:16 PM PDT 24 Jul 03 04:47:36 PM PDT 24 4707948124 ps
T363 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3267682713 Jul 03 04:47:18 PM PDT 24 Jul 03 04:47:21 PM PDT 24 223557635 ps
T364 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1727140188 Jul 03 04:47:31 PM PDT 24 Jul 03 04:47:42 PM PDT 24 3429999386 ps
T365 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3418430458 Jul 03 04:47:33 PM PDT 24 Jul 03 04:47:40 PM PDT 24 443537184 ps
T366 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3802944573 Jul 03 04:47:09 PM PDT 24 Jul 03 04:47:11 PM PDT 24 768009544 ps
T103 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4265030499 Jul 03 04:47:01 PM PDT 24 Jul 03 04:47:04 PM PDT 24 3160830196 ps
T367 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.930963750 Jul 03 04:47:26 PM PDT 24 Jul 03 04:47:29 PM PDT 24 189134327 ps
T368 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3450421571 Jul 03 04:47:16 PM PDT 24 Jul 03 04:47:21 PM PDT 24 5334726784 ps
T369 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3601877270 Jul 03 04:47:20 PM PDT 24 Jul 03 04:47:28 PM PDT 24 3534683451 ps
T370 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3289218146 Jul 03 04:47:12 PM PDT 24 Jul 03 04:47:30 PM PDT 24 6441379712 ps
T371 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.976189816 Jul 03 04:47:05 PM PDT 24 Jul 03 04:47:21 PM PDT 24 9264308445 ps
T113 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2555077597 Jul 03 04:47:20 PM PDT 24 Jul 03 04:47:29 PM PDT 24 624918913 ps
T372 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3390286956 Jul 03 04:47:21 PM PDT 24 Jul 03 04:47:23 PM PDT 24 176209312 ps
T373 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3398130501 Jul 03 04:47:06 PM PDT 24 Jul 03 04:47:14 PM PDT 24 1241895014 ps
T374 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1408165206 Jul 03 04:47:04 PM PDT 24 Jul 03 04:47:06 PM PDT 24 103186148 ps
T114 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1619298983 Jul 03 04:47:15 PM PDT 24 Jul 03 04:47:19 PM PDT 24 95386436 ps
T375 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2824744312 Jul 03 04:47:00 PM PDT 24 Jul 03 04:47:08 PM PDT 24 2495959408 ps
T376 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.27318656 Jul 03 04:47:03 PM PDT 24 Jul 03 04:47:27 PM PDT 24 27753841907 ps
T377 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3780415986 Jul 03 04:47:33 PM PDT 24 Jul 03 04:47:44 PM PDT 24 1542886173 ps
T378 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1340562002 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:40 PM PDT 24 64257494 ps
T379 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2884090826 Jul 03 04:47:31 PM PDT 24 Jul 03 04:47:59 PM PDT 24 10714145241 ps
T380 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2384772804 Jul 03 04:47:07 PM PDT 24 Jul 03 04:47:09 PM PDT 24 124659635 ps
T381 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2457635789 Jul 03 04:47:16 PM PDT 24 Jul 03 04:47:19 PM PDT 24 232380780 ps
T382 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1318969587 Jul 03 04:47:31 PM PDT 24 Jul 03 04:47:33 PM PDT 24 96088269 ps
T383 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3573501971 Jul 03 04:47:19 PM PDT 24 Jul 03 04:47:23 PM PDT 24 139800956 ps
T384 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2701498032 Jul 03 04:47:08 PM PDT 24 Jul 03 04:47:13 PM PDT 24 1815149905 ps
T385 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1442527898 Jul 03 04:47:33 PM PDT 24 Jul 03 04:47:41 PM PDT 24 3997265441 ps
T386 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2562202130 Jul 03 04:47:32 PM PDT 24 Jul 03 04:47:34 PM PDT 24 76598814 ps
T387 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.242287374 Jul 03 04:47:22 PM PDT 24 Jul 03 04:47:29 PM PDT 24 3879467045 ps
T388 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.18190409 Jul 03 04:47:10 PM PDT 24 Jul 03 04:47:13 PM PDT 24 992051678 ps
T389 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.860941761 Jul 03 04:47:20 PM PDT 24 Jul 03 04:48:09 PM PDT 24 18710423705 ps
T390 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1288320017 Jul 03 04:47:31 PM PDT 24 Jul 03 04:47:32 PM PDT 24 870900070 ps
T391 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3434816527 Jul 03 04:47:05 PM PDT 24 Jul 03 04:47:34 PM PDT 24 2843939763 ps
T392 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4018651574 Jul 03 04:47:10 PM PDT 24 Jul 03 04:47:13 PM PDT 24 532815535 ps
T393 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2702136645 Jul 03 04:47:19 PM PDT 24 Jul 03 04:47:24 PM PDT 24 2212357572 ps
T394 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2373214504 Jul 03 04:47:20 PM PDT 24 Jul 03 04:47:23 PM PDT 24 986136513 ps
T173 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3004028226 Jul 03 04:47:17 PM PDT 24 Jul 03 04:47:28 PM PDT 24 2232931192 ps
T395 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4067570694 Jul 03 04:47:23 PM PDT 24 Jul 03 04:47:24 PM PDT 24 206802742 ps
T396 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.624363402 Jul 03 04:47:12 PM PDT 24 Jul 03 04:47:19 PM PDT 24 586765546 ps
T397 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3443337548 Jul 03 04:47:14 PM PDT 24 Jul 03 04:47:18 PM PDT 24 2926657992 ps
T398 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2066993011 Jul 03 04:47:04 PM PDT 24 Jul 03 04:47:06 PM PDT 24 155167307 ps
T104 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1404265380 Jul 03 04:47:01 PM PDT 24 Jul 03 04:47:10 PM PDT 24 3421383988 ps
T399 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1625856221 Jul 03 04:47:08 PM PDT 24 Jul 03 04:48:29 PM PDT 24 16956070191 ps
T400 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1366729675 Jul 03 04:47:07 PM PDT 24 Jul 03 04:47:10 PM PDT 24 3022494858 ps
T401 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.623011116 Jul 03 04:47:06 PM PDT 24 Jul 03 04:47:07 PM PDT 24 29885104 ps
T402 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.4198703545 Jul 03 04:47:13 PM PDT 24 Jul 03 04:47:15 PM PDT 24 82619943 ps
T403 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.87262127 Jul 03 04:47:25 PM PDT 24 Jul 03 04:48:29 PM PDT 24 93803167888 ps
T404 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.402575929 Jul 03 04:47:04 PM PDT 24 Jul 03 04:47:18 PM PDT 24 17576919772 ps
T405 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3023525475 Jul 03 04:47:11 PM PDT 24 Jul 03 04:47:14 PM PDT 24 359721863 ps
T406 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3494634154 Jul 03 04:47:30 PM PDT 24 Jul 03 04:47:34 PM PDT 24 4522202155 ps
T407 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.182470954 Jul 03 04:47:22 PM PDT 24 Jul 03 04:47:24 PM PDT 24 63346155 ps
T408 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1987698178 Jul 03 04:47:03 PM PDT 24 Jul 03 04:47:04 PM PDT 24 240214791 ps
T409 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.4235384876 Jul 03 04:47:00 PM PDT 24 Jul 03 04:47:01 PM PDT 24 139005410 ps
T121 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.754487487 Jul 03 04:47:01 PM PDT 24 Jul 03 04:47:03 PM PDT 24 828033447 ps
T410 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1177901250 Jul 03 04:47:29 PM PDT 24 Jul 03 04:47:36 PM PDT 24 568324098 ps
T411 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3142051714 Jul 03 04:47:34 PM PDT 24 Jul 03 04:47:48 PM PDT 24 8990738308 ps
T412 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.382490414 Jul 03 04:47:03 PM PDT 24 Jul 03 04:50:52 PM PDT 24 94368534956 ps
T413 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2135901046 Jul 03 04:47:12 PM PDT 24 Jul 03 04:47:15 PM PDT 24 202575786 ps
T414 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3489369148 Jul 03 04:47:05 PM PDT 24 Jul 03 04:47:06 PM PDT 24 301624467 ps
T415 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1964077012 Jul 03 04:47:12 PM PDT 24 Jul 03 04:47:19 PM PDT 24 7268639606 ps
T416 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2904809755 Jul 03 04:47:33 PM PDT 24 Jul 03 04:47:37 PM PDT 24 283757170 ps
T417 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4289478461 Jul 03 04:47:11 PM PDT 24 Jul 03 04:47:28 PM PDT 24 2162176131 ps
T418 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1071806297 Jul 03 04:47:21 PM PDT 24 Jul 03 04:47:29 PM PDT 24 390256061 ps
T419 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3809927134 Jul 03 04:47:37 PM PDT 24 Jul 03 04:47:49 PM PDT 24 7654578892 ps
T420 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3302028255 Jul 03 04:47:02 PM PDT 24 Jul 03 04:47:08 PM PDT 24 2113243189 ps
T421 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4289433579 Jul 03 04:47:07 PM PDT 24 Jul 03 04:47:18 PM PDT 24 6644893787 ps
T422 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2770748303 Jul 03 04:47:15 PM PDT 24 Jul 03 04:47:17 PM PDT 24 2410722326 ps
T423 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1178120497 Jul 03 04:47:15 PM PDT 24 Jul 03 04:47:20 PM PDT 24 154966985 ps
T424 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2673684623 Jul 03 04:47:03 PM PDT 24 Jul 03 04:47:11 PM PDT 24 319308811 ps
T425 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.212468669 Jul 03 04:47:01 PM PDT 24 Jul 03 04:47:03 PM PDT 24 680738979 ps
T426 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.190393679 Jul 03 04:47:19 PM PDT 24 Jul 03 04:47:39 PM PDT 24 13001658806 ps
T427 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4219691470 Jul 03 04:47:20 PM PDT 24 Jul 03 04:47:21 PM PDT 24 256336443 ps
T428 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3646721532 Jul 03 04:47:11 PM PDT 24 Jul 03 04:47:13 PM PDT 24 386105327 ps
T429 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2013813743 Jul 03 04:47:22 PM PDT 24 Jul 03 04:47:28 PM PDT 24 3424985587 ps
T430 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2476379064 Jul 03 04:47:10 PM PDT 24 Jul 03 04:47:43 PM PDT 24 3815846719 ps
T431 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1833370528 Jul 03 04:47:25 PM PDT 24 Jul 03 04:47:26 PM PDT 24 150433994 ps

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.415886342
Short name T11
Test name
Test status
Simulation time 10922987190 ps
CPU time 6.04 seconds
Started Jul 03 05:15:08 PM PDT 24
Finished Jul 03 05:15:15 PM PDT 24
Peak memory 213676 kb
Host smart-6f322dfa-fd9c-47f3-be6b-d48550bcb975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415886342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.415886342
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.3605336743
Short name T4
Test name
Test status
Simulation time 5329025866 ps
CPU time 8.19 seconds
Started Jul 03 05:16:30 PM PDT 24
Finished Jul 03 05:16:39 PM PDT 24
Peak memory 205284 kb
Host smart-9068278f-92e8-4c3e-b858-559a56c754d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605336743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3605336743
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.196616975
Short name T53
Test name
Test status
Simulation time 47132535444 ps
CPU time 52.42 seconds
Started Jul 03 04:47:08 PM PDT 24
Finished Jul 03 04:48:01 PM PDT 24
Peak memory 221524 kb
Host smart-5e8f7b30-ae0e-463b-ace1-d4ee839183e4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196616975 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.196616975
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.624149946
Short name T5
Test name
Test status
Simulation time 156780351 ps
CPU time 1.12 seconds
Started Jul 03 05:14:49 PM PDT 24
Finished Jul 03 05:14:51 PM PDT 24
Peak memory 205092 kb
Host smart-21e48d2a-f03d-4e3a-ac6d-d320ad9eabcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624149946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.624149946
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.1767660627
Short name T25
Test name
Test status
Simulation time 10136007640 ps
CPU time 27.25 seconds
Started Jul 03 05:15:23 PM PDT 24
Finished Jul 03 05:15:50 PM PDT 24
Peak memory 205272 kb
Host smart-e8643477-9ffe-4d0b-be70-3f7b096ad392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767660627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.1767660627
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3018774852
Short name T59
Test name
Test status
Simulation time 95321378 ps
CPU time 0.77 seconds
Started Jul 03 05:16:01 PM PDT 24
Finished Jul 03 05:16:03 PM PDT 24
Peak memory 205048 kb
Host smart-f9f51531-a8bf-442a-a891-027730d38447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018774852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3018774852
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2448703735
Short name T89
Test name
Test status
Simulation time 1039673060 ps
CPU time 17.18 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 04:47:19 PM PDT 24
Peak memory 213356 kb
Host smart-722fb110-0922-45ac-a6bd-b9f8c3eca317
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448703735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2448703735
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2970317536
Short name T160
Test name
Test status
Simulation time 38060466566 ps
CPU time 81.56 seconds
Started Jul 03 05:16:06 PM PDT 24
Finished Jul 03 05:17:28 PM PDT 24
Peak memory 213572 kb
Host smart-3d3be63b-f671-4213-b8fd-475e329fd299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970317536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2970317536
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.2738842563
Short name T9
Test name
Test status
Simulation time 52363088 ps
CPU time 0.92 seconds
Started Jul 03 05:15:21 PM PDT 24
Finished Jul 03 05:15:23 PM PDT 24
Peak memory 215644 kb
Host smart-03af0937-b7a4-4637-89a8-b3ca0862f0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738842563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2738842563
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.272021865
Short name T156
Test name
Test status
Simulation time 14228264475 ps
CPU time 10.74 seconds
Started Jul 03 05:15:43 PM PDT 24
Finished Jul 03 05:15:54 PM PDT 24
Peak memory 213588 kb
Host smart-dd2bee11-0df6-4ae4-b87a-0112197bd5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272021865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.272021865
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.1062819410
Short name T29
Test name
Test status
Simulation time 2710559695 ps
CPU time 8.7 seconds
Started Jul 03 05:16:23 PM PDT 24
Finished Jul 03 05:16:32 PM PDT 24
Peak memory 205404 kb
Host smart-73ff1354-397e-4b84-8d0e-798ff2b46642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062819410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1062819410
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2187973136
Short name T99
Test name
Test status
Simulation time 289991513 ps
CPU time 2.87 seconds
Started Jul 03 04:47:05 PM PDT 24
Finished Jul 03 04:47:09 PM PDT 24
Peak memory 213436 kb
Host smart-18923dfb-9af1-44bd-b413-dff725f90b9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187973136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2187973136
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.4075059345
Short name T14
Test name
Test status
Simulation time 7354463509 ps
CPU time 6.25 seconds
Started Jul 03 05:16:26 PM PDT 24
Finished Jul 03 05:16:33 PM PDT 24
Peak memory 205280 kb
Host smart-f6ca6b2e-1895-4c15-bb3c-d5db5ab085e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075059345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.4075059345
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.551874342
Short name T46
Test name
Test status
Simulation time 540710872 ps
CPU time 1.07 seconds
Started Jul 03 05:15:22 PM PDT 24
Finished Jul 03 05:15:23 PM PDT 24
Peak memory 205064 kb
Host smart-c7ee63b1-9731-4c7d-a126-77df56990436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551874342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.551874342
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1004415448
Short name T73
Test name
Test status
Simulation time 351614608 ps
CPU time 1.25 seconds
Started Jul 03 05:15:35 PM PDT 24
Finished Jul 03 05:15:36 PM PDT 24
Peak memory 229524 kb
Host smart-814fe1c7-48e8-480b-900b-d0b9acb37cd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004415448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1004415448
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.3898420779
Short name T17
Test name
Test status
Simulation time 2946439855 ps
CPU time 4.51 seconds
Started Jul 03 05:16:04 PM PDT 24
Finished Jul 03 05:16:09 PM PDT 24
Peak memory 205304 kb
Host smart-d6940a0b-7159-43c9-b087-e1942971ce72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898420779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3898420779
Directory /workspace/9.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.674927113
Short name T231
Test name
Test status
Simulation time 25357090047 ps
CPU time 66.11 seconds
Started Jul 03 05:16:15 PM PDT 24
Finished Jul 03 05:17:21 PM PDT 24
Peak memory 213664 kb
Host smart-ba4207a0-01f0-4ae2-bba4-cf9c462fe9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674927113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.674927113
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1796950884
Short name T43
Test name
Test status
Simulation time 178027942 ps
CPU time 0.99 seconds
Started Jul 03 05:15:02 PM PDT 24
Finished Jul 03 05:15:03 PM PDT 24
Peak memory 213344 kb
Host smart-15cbb399-8a3f-4d29-9cfb-e4feff77bc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796950884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1796950884
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2420449778
Short name T96
Test name
Test status
Simulation time 1683840418 ps
CPU time 7.58 seconds
Started Jul 03 04:47:30 PM PDT 24
Finished Jul 03 04:47:38 PM PDT 24
Peak memory 205140 kb
Host smart-6cdcc9db-2e98-486e-bb4b-7747a28a6f3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420449778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2420449778
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2682537874
Short name T50
Test name
Test status
Simulation time 447870048 ps
CPU time 1.56 seconds
Started Jul 03 05:15:26 PM PDT 24
Finished Jul 03 05:15:27 PM PDT 24
Peak memory 205020 kb
Host smart-bb57424b-7df7-4676-8f64-3e9c492389cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682537874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2682537874
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.743933251
Short name T151
Test name
Test status
Simulation time 2004816147 ps
CPU time 3.02 seconds
Started Jul 03 05:16:15 PM PDT 24
Finished Jul 03 05:16:18 PM PDT 24
Peak memory 213520 kb
Host smart-4bf57503-f9c3-4112-b110-3751be43f4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743933251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.743933251
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.867464647
Short name T27
Test name
Test status
Simulation time 287243237 ps
CPU time 1.15 seconds
Started Jul 03 05:14:43 PM PDT 24
Finished Jul 03 05:14:45 PM PDT 24
Peak memory 205060 kb
Host smart-2458b335-485f-495e-90f4-14febdf1ddd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867464647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.867464647
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.3035339613
Short name T30
Test name
Test status
Simulation time 2587172488 ps
CPU time 3.34 seconds
Started Jul 03 05:16:20 PM PDT 24
Finished Jul 03 05:16:24 PM PDT 24
Peak memory 205356 kb
Host smart-61a836f3-0180-4bb2-b4a0-965267211027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035339613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3035339613
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.825824406
Short name T8
Test name
Test status
Simulation time 265883051 ps
CPU time 0.91 seconds
Started Jul 03 05:14:57 PM PDT 24
Finished Jul 03 05:14:58 PM PDT 24
Peak memory 205092 kb
Host smart-6aece001-d522-4e8b-953e-f0eb1d748026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825824406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.825824406
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1503613764
Short name T164
Test name
Test status
Simulation time 3889909149 ps
CPU time 24.36 seconds
Started Jul 03 04:47:15 PM PDT 24
Finished Jul 03 04:47:40 PM PDT 24
Peak memory 213424 kb
Host smart-f72a50ff-4587-4b06-a792-ec5077047690
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503613764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1503613764
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3094654914
Short name T152
Test name
Test status
Simulation time 1761193502 ps
CPU time 6.17 seconds
Started Jul 03 05:16:11 PM PDT 24
Finished Jul 03 05:16:18 PM PDT 24
Peak memory 213524 kb
Host smart-09308bcc-b8e7-4084-b4ec-b5d4614dadae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094654914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3094654914
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.114276353
Short name T167
Test name
Test status
Simulation time 2176354028 ps
CPU time 19.71 seconds
Started Jul 03 04:47:17 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 213388 kb
Host smart-d6672fa4-3970-4c5d-885c-fc4a69ffda2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114276353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.114276353
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1972053276
Short name T153
Test name
Test status
Simulation time 2424329078 ps
CPU time 8.01 seconds
Started Jul 03 05:16:12 PM PDT 24
Finished Jul 03 05:16:20 PM PDT 24
Peak memory 213584 kb
Host smart-a29a670e-7359-449c-ae77-7263bd646291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972053276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1972053276
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.481991378
Short name T159
Test name
Test status
Simulation time 2608464991 ps
CPU time 4.17 seconds
Started Jul 03 05:15:28 PM PDT 24
Finished Jul 03 05:15:33 PM PDT 24
Peak memory 205336 kb
Host smart-172ab13d-6dc6-4e8f-81fa-d314bfb28275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481991378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.481991378
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3373717742
Short name T139
Test name
Test status
Simulation time 5541207316 ps
CPU time 9.69 seconds
Started Jul 03 05:16:25 PM PDT 24
Finished Jul 03 05:16:36 PM PDT 24
Peak memory 213476 kb
Host smart-eeda62be-8947-40d1-ab73-6e72d4d10429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373717742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3373717742
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1245187167
Short name T305
Test name
Test status
Simulation time 3562730740 ps
CPU time 5.94 seconds
Started Jul 03 04:46:58 PM PDT 24
Finished Jul 03 04:47:04 PM PDT 24
Peak memory 205024 kb
Host smart-e815a504-2f2d-46d3-bb94-6c7f06f577fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245187167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1245187167
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2663333206
Short name T172
Test name
Test status
Simulation time 4707948124 ps
CPU time 19.31 seconds
Started Jul 03 04:47:16 PM PDT 24
Finished Jul 03 04:47:36 PM PDT 24
Peak memory 213376 kb
Host smart-c63d460a-c6eb-4f02-a666-9d023d47c799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663333206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2663333206
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.1776539584
Short name T148
Test name
Test status
Simulation time 932217161 ps
CPU time 1.94 seconds
Started Jul 03 05:14:45 PM PDT 24
Finished Jul 03 05:14:48 PM PDT 24
Peak memory 205308 kb
Host smart-05a89abe-cd6a-42f6-9117-2b813431a79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776539584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.1776539584
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.3730807678
Short name T142
Test name
Test status
Simulation time 3396988070 ps
CPU time 10.1 seconds
Started Jul 03 05:15:04 PM PDT 24
Finished Jul 03 05:15:15 PM PDT 24
Peak memory 205292 kb
Host smart-f98760d9-12cb-460a-ac22-a6d89d16e38a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730807678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3730807678
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.32232418
Short name T22
Test name
Test status
Simulation time 13409654514 ps
CPU time 18.77 seconds
Started Jul 03 05:16:01 PM PDT 24
Finished Jul 03 05:16:20 PM PDT 24
Peak memory 213532 kb
Host smart-cc08f718-53f4-4957-8ba5-f9d7a6da3bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32232418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.32232418
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2570878553
Short name T161
Test name
Test status
Simulation time 24423852545 ps
CPU time 21.48 seconds
Started Jul 03 05:16:06 PM PDT 24
Finished Jul 03 05:16:28 PM PDT 24
Peak memory 216636 kb
Host smart-b08924e6-5612-42af-b2a4-35967b87691d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570878553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2570878553
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.3785932754
Short name T133
Test name
Test status
Simulation time 1341647049 ps
CPU time 3.86 seconds
Started Jul 03 05:16:18 PM PDT 24
Finished Jul 03 05:16:22 PM PDT 24
Peak memory 205268 kb
Host smart-58ea9778-5783-4549-bd50-f1afeb7368e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785932754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3785932754
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.233914565
Short name T138
Test name
Test status
Simulation time 7130410434 ps
CPU time 21.02 seconds
Started Jul 03 05:16:31 PM PDT 24
Finished Jul 03 05:16:53 PM PDT 24
Peak memory 205372 kb
Host smart-0f098572-6989-47db-bb02-5213ee4bfe37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233914565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.233914565
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.1450546617
Short name T6
Test name
Test status
Simulation time 3797345388 ps
CPU time 5.58 seconds
Started Jul 03 05:15:55 PM PDT 24
Finished Jul 03 05:16:01 PM PDT 24
Peak memory 205348 kb
Host smart-8c590d81-34a0-4059-a2b8-548d06cb0dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450546617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1450546617
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1404265380
Short name T104
Test name
Test status
Simulation time 3421383988 ps
CPU time 7.88 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 04:47:10 PM PDT 24
Peak memory 205128 kb
Host smart-1ef09070-585c-4861-b8b4-030321ab1289
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404265380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1404265380
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.518747368
Short name T42
Test name
Test status
Simulation time 539967786 ps
CPU time 1.12 seconds
Started Jul 03 05:14:51 PM PDT 24
Finished Jul 03 05:14:53 PM PDT 24
Peak memory 205096 kb
Host smart-d6fc8398-7f1c-4685-84e8-23d2c88c1073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518747368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.518747368
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1860089585
Short name T150
Test name
Test status
Simulation time 16424469985 ps
CPU time 22.6 seconds
Started Jul 03 05:14:45 PM PDT 24
Finished Jul 03 05:15:08 PM PDT 24
Peak memory 213648 kb
Host smart-66b3e565-aa42-44dc-be3c-fceaa2f41753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860089585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1860089585
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.512412518
Short name T154
Test name
Test status
Simulation time 1528236968 ps
CPU time 1.2 seconds
Started Jul 03 05:14:54 PM PDT 24
Finished Jul 03 05:14:55 PM PDT 24
Peak memory 205068 kb
Host smart-794f28ec-1c1e-410a-a37c-d6065f034816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512412518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.512412518
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1275884238
Short name T51
Test name
Test status
Simulation time 941262064 ps
CPU time 3.45 seconds
Started Jul 03 05:15:00 PM PDT 24
Finished Jul 03 05:15:04 PM PDT 24
Peak memory 205100 kb
Host smart-23e2f60e-d755-4264-967e-420221d1f230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275884238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1275884238
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.271950445
Short name T26
Test name
Test status
Simulation time 709588080 ps
CPU time 1.15 seconds
Started Jul 03 05:15:07 PM PDT 24
Finished Jul 03 05:15:08 PM PDT 24
Peak memory 205032 kb
Host smart-c0e9830e-ed3a-476e-a70a-4a8bdf1434e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271950445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.271950445
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2836165252
Short name T147
Test name
Test status
Simulation time 6028598815 ps
CPU time 9.32 seconds
Started Jul 03 05:16:03 PM PDT 24
Finished Jul 03 05:16:12 PM PDT 24
Peak memory 213308 kb
Host smart-34f87abd-b828-455d-8540-fbf8efb3a348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836165252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2836165252
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1578440699
Short name T146
Test name
Test status
Simulation time 1027686273 ps
CPU time 2.2 seconds
Started Jul 03 05:16:06 PM PDT 24
Finished Jul 03 05:16:09 PM PDT 24
Peak memory 205332 kb
Host smart-72f16d80-e3c0-48b6-991e-fa33635a6f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578440699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1578440699
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.978689528
Short name T158
Test name
Test status
Simulation time 5950520268 ps
CPU time 3.34 seconds
Started Jul 03 05:16:08 PM PDT 24
Finished Jul 03 05:16:12 PM PDT 24
Peak memory 213684 kb
Host smart-b714f0aa-1ecc-4a79-a851-4538174a7afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978689528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.978689528
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1841366250
Short name T85
Test name
Test status
Simulation time 9049120797 ps
CPU time 24.74 seconds
Started Jul 03 05:16:10 PM PDT 24
Finished Jul 03 05:16:35 PM PDT 24
Peak memory 213620 kb
Host smart-959b8c82-a3c2-4900-bc7e-3f720ca368b1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1841366250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1841366250
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.149932494
Short name T21
Test name
Test status
Simulation time 5958341797 ps
CPU time 9.21 seconds
Started Jul 03 05:16:13 PM PDT 24
Finished Jul 03 05:16:23 PM PDT 24
Peak memory 213516 kb
Host smart-6a8c0f82-003a-41ed-a3e2-457de6f499e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149932494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.149932494
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3942117181
Short name T37
Test name
Test status
Simulation time 21446047352 ps
CPU time 57.16 seconds
Started Jul 03 05:16:18 PM PDT 24
Finished Jul 03 05:17:15 PM PDT 24
Peak memory 213588 kb
Host smart-8573f015-537b-4c1a-9cac-0f2c4563973b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942117181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3942117181
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.3875049794
Short name T23
Test name
Test status
Simulation time 2198320175 ps
CPU time 3.76 seconds
Started Jul 03 05:16:21 PM PDT 24
Finished Jul 03 05:16:25 PM PDT 24
Peak memory 205368 kb
Host smart-cc132787-a4a8-4ad0-bdbf-6cc3dcb66b13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875049794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3875049794
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.3027042616
Short name T145
Test name
Test status
Simulation time 4875064205 ps
CPU time 11.3 seconds
Started Jul 03 05:16:19 PM PDT 24
Finished Jul 03 05:16:31 PM PDT 24
Peak memory 214516 kb
Host smart-08cefb96-5e5c-424a-9a38-2fa6622fb968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027042616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3027042616
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.1033526841
Short name T15
Test name
Test status
Simulation time 9314387543 ps
CPU time 22.4 seconds
Started Jul 03 05:16:16 PM PDT 24
Finished Jul 03 05:16:39 PM PDT 24
Peak memory 213516 kb
Host smart-458065a2-f5c3-4095-a329-eb7015dfce75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033526841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.1033526841
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.4204980200
Short name T144
Test name
Test status
Simulation time 1226283531 ps
CPU time 2.2 seconds
Started Jul 03 05:16:29 PM PDT 24
Finished Jul 03 05:16:32 PM PDT 24
Peak memory 205296 kb
Host smart-637b72ce-5e98-4d59-83aa-fb3032930c41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204980200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.4204980200
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3085275939
Short name T324
Test name
Test status
Simulation time 1640508878 ps
CPU time 13.47 seconds
Started Jul 03 04:47:21 PM PDT 24
Finished Jul 03 04:47:35 PM PDT 24
Peak memory 213300 kb
Host smart-fc40a9ca-244e-4dd1-8092-2baf97df86eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085275939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
085275939
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2211912565
Short name T321
Test name
Test status
Simulation time 4730798481 ps
CPU time 11.28 seconds
Started Jul 03 04:47:31 PM PDT 24
Finished Jul 03 04:47:42 PM PDT 24
Peak memory 213340 kb
Host smart-01e01934-7339-4e56-b895-3d41848af341
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211912565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2211912565
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.57250873
Short name T112
Test name
Test status
Simulation time 1760155048 ps
CPU time 67.43 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 04:48:08 PM PDT 24
Peak memory 213344 kb
Host smart-7ba7a59c-d9bf-4b02-8f90-b5cd15a6f269
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57250873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV
M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.rv_dm_csr_aliasing.57250873
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1192790573
Short name T334
Test name
Test status
Simulation time 14965682668 ps
CPU time 75.99 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 04:48:17 PM PDT 24
Peak memory 213452 kb
Host smart-11fa6431-d4db-49ed-886e-a7f1cdddc6c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192790573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1192790573
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2208595775
Short name T64
Test name
Test status
Simulation time 386735982 ps
CPU time 1.79 seconds
Started Jul 03 04:46:59 PM PDT 24
Finished Jul 03 04:47:01 PM PDT 24
Peak memory 213216 kb
Host smart-aeddf34a-a49e-4f55-bc54-9dcb5f9d8132
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208595775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2208595775
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1631376812
Short name T309
Test name
Test status
Simulation time 214517361 ps
CPU time 3.82 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 04:47:06 PM PDT 24
Peak memory 218488 kb
Host smart-42a30426-9bfd-4b3b-8020-a2c86673ed9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631376812 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1631376812
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.754487487
Short name T121
Test name
Test status
Simulation time 828033447 ps
CPU time 1.7 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 04:47:03 PM PDT 24
Peak memory 213328 kb
Host smart-bd8c3c4d-5d61-4f77-b9ba-874ad003c2c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754487487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.754487487
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2301399802
Short name T292
Test name
Test status
Simulation time 16083730353 ps
CPU time 43.02 seconds
Started Jul 03 04:47:02 PM PDT 24
Finished Jul 03 04:47:46 PM PDT 24
Peak memory 205108 kb
Host smart-7c4767bf-2284-45d6-b8df-c792c32dc27c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301399802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2301399802
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2303982745
Short name T345
Test name
Test status
Simulation time 16561967640 ps
CPU time 23.32 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 04:47:25 PM PDT 24
Peak memory 205008 kb
Host smart-4bd3ff33-593a-46a2-9776-87de1164b1e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303982745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.2303982745
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.406844004
Short name T332
Test name
Test status
Simulation time 14317762998 ps
CPU time 8.14 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 04:47:10 PM PDT 24
Peak memory 204964 kb
Host smart-5bb8cfe6-4269-4e29-a5f8-aae272a5e4c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406844004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.406844004
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2615669107
Short name T337
Test name
Test status
Simulation time 2396505604 ps
CPU time 2.14 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 04:47:04 PM PDT 24
Peak memory 204824 kb
Host smart-8c93494f-4c81-4add-997b-9cef80a69fbf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615669107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2615669107
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1987698178
Short name T408
Test name
Test status
Simulation time 240214791 ps
CPU time 0.86 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 04:47:04 PM PDT 24
Peak memory 204864 kb
Host smart-b8fdfcee-544e-4657-b191-c59801076016
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987698178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1987698178
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.250202483
Short name T322
Test name
Test status
Simulation time 200957774 ps
CPU time 0.84 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 04:47:02 PM PDT 24
Peak memory 204772 kb
Host smart-9bfee10b-58fd-4ede-99b8-7fdfaa78c396
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250202483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.250202483
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3781415709
Short name T296
Test name
Test status
Simulation time 117163093 ps
CPU time 0.92 seconds
Started Jul 03 04:46:59 PM PDT 24
Finished Jul 03 04:47:00 PM PDT 24
Peak memory 204704 kb
Host smart-6cc940d2-cadb-43dd-996f-99689480f78f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781415709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3781415709
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.4235384876
Short name T409
Test name
Test status
Simulation time 139005410 ps
CPU time 0.78 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 04:47:01 PM PDT 24
Peak memory 204764 kb
Host smart-ae03b768-67cd-4c81-a538-585bc4cd94c0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235384876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.4235384876
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2824744312
Short name T375
Test name
Test status
Simulation time 2495959408 ps
CPU time 8.16 seconds
Started Jul 03 04:47:00 PM PDT 24
Finished Jul 03 04:47:08 PM PDT 24
Peak memory 205192 kb
Host smart-3e0a241e-0243-424d-8d78-e439b8ac35d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824744312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2824744312
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.27318656
Short name T376
Test name
Test status
Simulation time 27753841907 ps
CPU time 22.87 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 04:47:27 PM PDT 24
Peak memory 221456 kb
Host smart-06aceb54-c0a7-4f34-858c-5d00d59ee3da
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27318656 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.27318656
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.845546023
Short name T357
Test name
Test status
Simulation time 196826097 ps
CPU time 3.13 seconds
Started Jul 03 04:47:02 PM PDT 24
Finished Jul 03 04:47:06 PM PDT 24
Peak memory 213376 kb
Host smart-6c47a2be-bb51-4876-b5ef-1dc323fe82ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845546023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.845546023
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1419543750
Short name T174
Test name
Test status
Simulation time 15662240209 ps
CPU time 20.76 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 04:47:22 PM PDT 24
Peak memory 213400 kb
Host smart-022c414e-ab5f-4ca5-a3fc-2c5721570cfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419543750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1419543750
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2648069142
Short name T313
Test name
Test status
Simulation time 4071886472 ps
CPU time 35.58 seconds
Started Jul 03 04:47:02 PM PDT 24
Finished Jul 03 04:47:38 PM PDT 24
Peak memory 213432 kb
Host smart-d11b6a46-8b93-4017-a3e0-4a731c6a9f00
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648069142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2648069142
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4287465708
Short name T317
Test name
Test status
Simulation time 11791748940 ps
CPU time 32.89 seconds
Started Jul 03 04:47:06 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 213264 kb
Host smart-60cbf824-c8ab-4a57-9d7f-fb3a12d9b0b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287465708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4287465708
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2066993011
Short name T398
Test name
Test status
Simulation time 155167307 ps
CPU time 1.67 seconds
Started Jul 03 04:47:04 PM PDT 24
Finished Jul 03 04:47:06 PM PDT 24
Peak memory 213332 kb
Host smart-5716d2ca-7f72-477e-9d0f-6098b4fe6070
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066993011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2066993011
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3832957880
Short name T128
Test name
Test status
Simulation time 1980647644 ps
CPU time 6.51 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 04:47:11 PM PDT 24
Peak memory 218840 kb
Host smart-a0ba0f8d-796d-4add-90b0-6a8e9d98cb15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832957880 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3832957880
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1408165206
Short name T374
Test name
Test status
Simulation time 103186148 ps
CPU time 1.79 seconds
Started Jul 03 04:47:04 PM PDT 24
Finished Jul 03 04:47:06 PM PDT 24
Peak memory 213384 kb
Host smart-a6637b51-cced-4d93-818a-a7e9c250ed66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408165206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1408165206
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.293344895
Short name T341
Test name
Test status
Simulation time 12473998358 ps
CPU time 14.23 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 04:47:18 PM PDT 24
Peak memory 204988 kb
Host smart-4283590e-80a2-4d7c-8eee-513f8c97f2cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293344895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.293344895
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.763446377
Short name T355
Test name
Test status
Simulation time 6623049839 ps
CPU time 18.06 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 04:47:22 PM PDT 24
Peak memory 204960 kb
Host smart-503ec821-37da-49fe-83b4-58ebc7ab3d4c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763446377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r
v_dm_jtag_dmi_csr_bit_bash.763446377
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1577549591
Short name T306
Test name
Test status
Simulation time 17316446152 ps
CPU time 25.48 seconds
Started Jul 03 04:47:05 PM PDT 24
Finished Jul 03 04:47:31 PM PDT 24
Peak memory 205060 kb
Host smart-30e70e62-3739-4612-9442-85a1be3e0a6c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577549591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1577549591
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3302028255
Short name T420
Test name
Test status
Simulation time 2113243189 ps
CPU time 4.84 seconds
Started Jul 03 04:47:02 PM PDT 24
Finished Jul 03 04:47:08 PM PDT 24
Peak memory 204948 kb
Host smart-46e5c262-646e-44a2-91b5-b66be27687c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302028255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
302028255
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.316841744
Short name T354
Test name
Test status
Simulation time 166874604 ps
CPU time 0.97 seconds
Started Jul 03 04:47:05 PM PDT 24
Finished Jul 03 04:47:06 PM PDT 24
Peak memory 204764 kb
Host smart-01d14206-1c00-44db-8570-1090451df78c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316841744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.316841744
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.976189816
Short name T371
Test name
Test status
Simulation time 9264308445 ps
CPU time 15.5 seconds
Started Jul 03 04:47:05 PM PDT 24
Finished Jul 03 04:47:21 PM PDT 24
Peak memory 204980 kb
Host smart-f35739d6-5101-48a3-a0f5-3071e5e0036f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976189816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.976189816
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.212468669
Short name T425
Test name
Test status
Simulation time 680738979 ps
CPU time 1.14 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 04:47:03 PM PDT 24
Peak memory 204784 kb
Host smart-e61b18a4-12d5-493b-8cae-1a4eb6fd2bdb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212468669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.212468669
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3489369148
Short name T414
Test name
Test status
Simulation time 301624467 ps
CPU time 0.99 seconds
Started Jul 03 04:47:05 PM PDT 24
Finished Jul 03 04:47:06 PM PDT 24
Peak memory 204776 kb
Host smart-f4e44cbf-3370-4dce-b617-a3a743bbeea6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489369148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
489369148
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1429155538
Short name T293
Test name
Test status
Simulation time 48693362 ps
CPU time 0.67 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 04:47:05 PM PDT 24
Peak memory 204672 kb
Host smart-72857aa7-eb96-43bb-8cc7-7f7fa24ab4bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429155538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1429155538
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.843051046
Short name T348
Test name
Test status
Simulation time 88874010 ps
CPU time 0.78 seconds
Started Jul 03 04:47:02 PM PDT 24
Finished Jul 03 04:47:04 PM PDT 24
Peak memory 204740 kb
Host smart-41e74525-998f-404d-b60e-d345de746b13
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843051046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.843051046
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3398130501
Short name T373
Test name
Test status
Simulation time 1241895014 ps
CPU time 7.9 seconds
Started Jul 03 04:47:06 PM PDT 24
Finished Jul 03 04:47:14 PM PDT 24
Peak memory 204956 kb
Host smart-34f0f325-52db-4e64-9d44-34bbbd454bf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398130501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3398130501
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2673684623
Short name T424
Test name
Test status
Simulation time 319308811 ps
CPU time 7.04 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 04:47:11 PM PDT 24
Peak memory 213356 kb
Host smart-d21f9250-1c8a-4a91-9018-eff1b6718f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673684623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2673684623
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.242287374
Short name T387
Test name
Test status
Simulation time 3879467045 ps
CPU time 6.32 seconds
Started Jul 03 04:47:22 PM PDT 24
Finished Jul 03 04:47:29 PM PDT 24
Peak memory 221624 kb
Host smart-2bf81e40-3176-4f67-8f28-a99fbf7e9ca6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242287374 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.242287374
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1058126064
Short name T63
Test name
Test status
Simulation time 114067052 ps
CPU time 1.73 seconds
Started Jul 03 04:47:31 PM PDT 24
Finished Jul 03 04:47:33 PM PDT 24
Peak memory 213272 kb
Host smart-85e09622-f52e-4097-a4f5-86d248827c27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058126064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1058126064
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.190393679
Short name T426
Test name
Test status
Simulation time 13001658806 ps
CPU time 19.62 seconds
Started Jul 03 04:47:19 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 205036 kb
Host smart-c248b2d8-7e1d-42f8-b452-e888d6d197bf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190393679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rv_dm_jtag_dmi_csr_bit_bash.190393679
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3809927134
Short name T419
Test name
Test status
Simulation time 7654578892 ps
CPU time 10.63 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:49 PM PDT 24
Peak memory 204956 kb
Host smart-e32ac683-cb8b-4544-ab62-bf7083980a9d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809927134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3809927134
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.338443455
Short name T350
Test name
Test status
Simulation time 496028102 ps
CPU time 1.34 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 204748 kb
Host smart-dd6cd836-fcca-454d-a0bc-dd38a15dd4c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338443455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.338443455
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.575978375
Short name T109
Test name
Test status
Simulation time 589539900 ps
CPU time 6.44 seconds
Started Jul 03 04:47:31 PM PDT 24
Finished Jul 03 04:47:38 PM PDT 24
Peak memory 205084 kb
Host smart-87f1cf58-57a3-46b8-8fd0-7aa7a09fe53f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575978375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.575978375
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.793444092
Short name T303
Test name
Test status
Simulation time 150942592 ps
CPU time 3.82 seconds
Started Jul 03 04:47:23 PM PDT 24
Finished Jul 03 04:47:27 PM PDT 24
Peak memory 221444 kb
Host smart-753dd183-8d10-4157-86e8-76dddf0b0fa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793444092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.793444092
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2702136645
Short name T393
Test name
Test status
Simulation time 2212357572 ps
CPU time 4.85 seconds
Started Jul 03 04:47:19 PM PDT 24
Finished Jul 03 04:47:24 PM PDT 24
Peak memory 218432 kb
Host smart-61ded1f1-5941-458b-82ca-b0d9c738448e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702136645 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2702136645
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3267682713
Short name T363
Test name
Test status
Simulation time 223557635 ps
CPU time 2.53 seconds
Started Jul 03 04:47:18 PM PDT 24
Finished Jul 03 04:47:21 PM PDT 24
Peak memory 213332 kb
Host smart-d026e7c0-93c0-464f-b958-3990c1b2cb86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267682713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3267682713
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2458591136
Short name T315
Test name
Test status
Simulation time 12231516359 ps
CPU time 34.34 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:48:12 PM PDT 24
Peak memory 204976 kb
Host smart-c3265c0b-59b7-4cc9-a9e7-b1ca00b69204
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458591136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.2458591136
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.493978246
Short name T343
Test name
Test status
Simulation time 1296926870 ps
CPU time 2.98 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:41 PM PDT 24
Peak memory 204924 kb
Host smart-10eb1980-49f8-47fb-90f7-31d7b44e0398
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493978246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.493978246
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.961185610
Short name T333
Test name
Test status
Simulation time 1211066524 ps
CPU time 3.09 seconds
Started Jul 03 04:47:19 PM PDT 24
Finished Jul 03 04:47:22 PM PDT 24
Peak memory 204772 kb
Host smart-99272ad6-0576-4238-a7af-11dc9c1eab40
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961185610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.961185610
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1340562002
Short name T378
Test name
Test status
Simulation time 64257494 ps
CPU time 2.23 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:40 PM PDT 24
Peak memory 213304 kb
Host smart-8a6416d9-4677-49d1-92c3-4619f5a3cf66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340562002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1340562002
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2749085957
Short name T60
Test name
Test status
Simulation time 1569612247 ps
CPU time 9.23 seconds
Started Jul 03 04:47:21 PM PDT 24
Finished Jul 03 04:47:30 PM PDT 24
Peak memory 213316 kb
Host smart-96f613f1-2606-4e09-80ab-8d18c97c179a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749085957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
749085957
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1168892461
Short name T91
Test name
Test status
Simulation time 3884541183 ps
CPU time 8.14 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:47:46 PM PDT 24
Peak memory 213428 kb
Host smart-de0d24a8-e190-4493-8e17-a4952aa799e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168892461 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1168892461
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.122105094
Short name T120
Test name
Test status
Simulation time 127547031 ps
CPU time 2.24 seconds
Started Jul 03 04:47:22 PM PDT 24
Finished Jul 03 04:47:24 PM PDT 24
Peak memory 213236 kb
Host smart-f897d0da-5238-470e-929b-5795bcc51614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122105094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.122105094
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1260745204
Short name T294
Test name
Test status
Simulation time 24178126176 ps
CPU time 33.04 seconds
Started Jul 03 04:47:37 PM PDT 24
Finished Jul 03 04:48:11 PM PDT 24
Peak memory 205000 kb
Host smart-74e9e724-19e1-41ee-9359-d7b35e5fc88f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260745204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.1260745204
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2013813743
Short name T429
Test name
Test status
Simulation time 3424985587 ps
CPU time 5.16 seconds
Started Jul 03 04:47:22 PM PDT 24
Finished Jul 03 04:47:28 PM PDT 24
Peak memory 204904 kb
Host smart-451ce04b-5e47-4aa4-86a4-4fbe70a76a1e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013813743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2013813743
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1833370528
Short name T431
Test name
Test status
Simulation time 150433994 ps
CPU time 0.81 seconds
Started Jul 03 04:47:25 PM PDT 24
Finished Jul 03 04:47:26 PM PDT 24
Peak memory 204700 kb
Host smart-bb8d4a1b-54a3-43ea-a769-4eb06973b535
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833370528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1833370528
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2374573202
Short name T123
Test name
Test status
Simulation time 1085347871 ps
CPU time 8.39 seconds
Started Jul 03 04:47:31 PM PDT 24
Finished Jul 03 04:47:40 PM PDT 24
Peak memory 205140 kb
Host smart-263bf72b-2d0d-4126-8001-4628a23ffe9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374573202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2374573202
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.793495018
Short name T127
Test name
Test status
Simulation time 886417745 ps
CPU time 4.88 seconds
Started Jul 03 04:47:25 PM PDT 24
Finished Jul 03 04:47:31 PM PDT 24
Peak memory 213292 kb
Host smart-5b6cc193-e87e-4e22-8a57-fd4f778e7957
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793495018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.793495018
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.718596186
Short name T331
Test name
Test status
Simulation time 589430446 ps
CPU time 3.88 seconds
Started Jul 03 04:47:26 PM PDT 24
Finished Jul 03 04:47:31 PM PDT 24
Peak memory 221580 kb
Host smart-9867cbdc-5685-4bb8-9792-a64bddf91073
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718596186 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.718596186
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.930963750
Short name T367
Test name
Test status
Simulation time 189134327 ps
CPU time 2.28 seconds
Started Jul 03 04:47:26 PM PDT 24
Finished Jul 03 04:47:29 PM PDT 24
Peak memory 213304 kb
Host smart-2bc6ec7e-c9a8-4786-a0e0-93f2efa528d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930963750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.930963750
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2884090826
Short name T379
Test name
Test status
Simulation time 10714145241 ps
CPU time 27.91 seconds
Started Jul 03 04:47:31 PM PDT 24
Finished Jul 03 04:47:59 PM PDT 24
Peak memory 204992 kb
Host smart-a3b9cb2c-99c8-41a7-9c33-f853cf6d0513
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884090826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2884090826
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3078773172
Short name T302
Test name
Test status
Simulation time 4676844950 ps
CPU time 13.16 seconds
Started Jul 03 04:47:22 PM PDT 24
Finished Jul 03 04:47:35 PM PDT 24
Peak memory 204968 kb
Host smart-88b71883-03cc-4947-accd-5222f015b81a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078773172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3078773172
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2373214504
Short name T394
Test name
Test status
Simulation time 986136513 ps
CPU time 2.36 seconds
Started Jul 03 04:47:20 PM PDT 24
Finished Jul 03 04:47:23 PM PDT 24
Peak memory 204748 kb
Host smart-1d812da1-a21d-4368-9c27-afedc025ba14
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373214504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2373214504
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2135558657
Short name T122
Test name
Test status
Simulation time 232342615 ps
CPU time 4.19 seconds
Started Jul 03 04:47:24 PM PDT 24
Finished Jul 03 04:47:28 PM PDT 24
Peak memory 205084 kb
Host smart-147c5d50-17fa-4b31-b092-ed77d1dd4c22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135558657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2135558657
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.316293303
Short name T131
Test name
Test status
Simulation time 706703998 ps
CPU time 5.34 seconds
Started Jul 03 04:47:23 PM PDT 24
Finished Jul 03 04:47:28 PM PDT 24
Peak memory 213244 kb
Host smart-e18ead5a-a93b-45b3-82da-8e9bc25fd51a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316293303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.316293303
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1761342792
Short name T165
Test name
Test status
Simulation time 5903947829 ps
CPU time 22.54 seconds
Started Jul 03 04:47:29 PM PDT 24
Finished Jul 03 04:47:52 PM PDT 24
Peak memory 213356 kb
Host smart-2e0c89bd-3b13-4763-a4f6-b3271671bd6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761342792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
761342792
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1727616870
Short name T312
Test name
Test status
Simulation time 194459282 ps
CPU time 2.6 seconds
Started Jul 03 04:47:28 PM PDT 24
Finished Jul 03 04:47:31 PM PDT 24
Peak memory 218444 kb
Host smart-1e2c68fa-23a0-402d-852d-4315b7f7ce42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727616870 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1727616870
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.57340667
Short name T320
Test name
Test status
Simulation time 131127267 ps
CPU time 2.46 seconds
Started Jul 03 04:47:26 PM PDT 24
Finished Jul 03 04:47:29 PM PDT 24
Peak memory 213332 kb
Host smart-eab47b43-deba-468c-b4ac-23fef5199afe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57340667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.57340667
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1720957909
Short name T287
Test name
Test status
Simulation time 23337714196 ps
CPU time 8.55 seconds
Started Jul 03 04:47:25 PM PDT 24
Finished Jul 03 04:47:34 PM PDT 24
Peak memory 205040 kb
Host smart-6abf5a5b-743a-4427-82f1-8b1a1a65219e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720957909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.1720957909
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4204196547
Short name T311
Test name
Test status
Simulation time 1797121005 ps
CPU time 3.21 seconds
Started Jul 03 04:47:26 PM PDT 24
Finished Jul 03 04:47:30 PM PDT 24
Peak memory 204924 kb
Host smart-b4fcafc1-6087-4a8b-9b40-fe895f776bb4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204196547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
4204196547
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3321231730
Short name T358
Test name
Test status
Simulation time 122984058 ps
CPU time 0.82 seconds
Started Jul 03 04:47:24 PM PDT 24
Finished Jul 03 04:47:25 PM PDT 24
Peak memory 204808 kb
Host smart-15d1e3f5-b478-4c30-abb0-d692d1b8821a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321231730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
3321231730
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3009700241
Short name T347
Test name
Test status
Simulation time 603222063 ps
CPU time 8.13 seconds
Started Jul 03 04:47:24 PM PDT 24
Finished Jul 03 04:47:32 PM PDT 24
Peak memory 205208 kb
Host smart-627f8e64-690a-4c5e-9127-cf94c48ca1fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009700241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3009700241
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3727477355
Short name T62
Test name
Test status
Simulation time 760614355 ps
CPU time 4.26 seconds
Started Jul 03 04:47:25 PM PDT 24
Finished Jul 03 04:47:30 PM PDT 24
Peak memory 213324 kb
Host smart-8212c9fd-52cb-4257-a6cb-03dd0a8fb36a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727477355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3727477355
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2227323839
Short name T168
Test name
Test status
Simulation time 3874087541 ps
CPU time 21.43 seconds
Started Jul 03 04:47:23 PM PDT 24
Finished Jul 03 04:47:45 PM PDT 24
Peak memory 213392 kb
Host smart-ed24d265-cf03-4b9a-85ff-bad60210bb06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227323839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
227323839
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3398841538
Short name T291
Test name
Test status
Simulation time 4290032538 ps
CPU time 3.86 seconds
Started Jul 03 04:47:23 PM PDT 24
Finished Jul 03 04:47:27 PM PDT 24
Peak memory 217888 kb
Host smart-e9bc02cc-8eaf-42b0-8eb5-fa2b7a79093a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398841538 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3398841538
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2913261526
Short name T125
Test name
Test status
Simulation time 95456209 ps
CPU time 1.58 seconds
Started Jul 03 04:47:27 PM PDT 24
Finished Jul 03 04:47:29 PM PDT 24
Peak memory 213284 kb
Host smart-970b2701-97cc-4f6b-aa8a-9b99a492e701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913261526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2913261526
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3256890425
Short name T329
Test name
Test status
Simulation time 2327619579 ps
CPU time 6.95 seconds
Started Jul 03 04:47:23 PM PDT 24
Finished Jul 03 04:47:30 PM PDT 24
Peak memory 205032 kb
Host smart-043ad912-091c-48f5-b16a-efebfcb08ad3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256890425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.3256890425
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3700363490
Short name T335
Test name
Test status
Simulation time 6694714646 ps
CPU time 9.55 seconds
Started Jul 03 04:47:23 PM PDT 24
Finished Jul 03 04:47:33 PM PDT 24
Peak memory 204968 kb
Host smart-a3748d5d-baa3-48ef-bcc5-b918d5a2a7b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700363490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3700363490
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4067570694
Short name T395
Test name
Test status
Simulation time 206802742 ps
CPU time 0.86 seconds
Started Jul 03 04:47:23 PM PDT 24
Finished Jul 03 04:47:24 PM PDT 24
Peak memory 204736 kb
Host smart-e81f4c83-ed72-413e-9bd5-5f6160a82f68
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067570694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
4067570694
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2174289252
Short name T107
Test name
Test status
Simulation time 334729542 ps
CPU time 3.7 seconds
Started Jul 03 04:47:23 PM PDT 24
Finished Jul 03 04:47:27 PM PDT 24
Peak memory 205052 kb
Host smart-426285f7-42c3-4375-8098-0b3d68b71b14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174289252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2174289252
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2545439226
Short name T61
Test name
Test status
Simulation time 142502192 ps
CPU time 2.38 seconds
Started Jul 03 04:47:28 PM PDT 24
Finished Jul 03 04:47:31 PM PDT 24
Peak memory 213376 kb
Host smart-35bad503-d0a6-4136-9df9-0ff41fbbdb50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545439226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2545439226
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.4179159560
Short name T170
Test name
Test status
Simulation time 1255080488 ps
CPU time 8.53 seconds
Started Jul 03 04:47:24 PM PDT 24
Finished Jul 03 04:47:33 PM PDT 24
Peak memory 213348 kb
Host smart-ceed2f3a-46de-413e-a061-1750b0b38db0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179159560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.4
179159560
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2562202130
Short name T386
Test name
Test status
Simulation time 76598814 ps
CPU time 2.04 seconds
Started Jul 03 04:47:32 PM PDT 24
Finished Jul 03 04:47:34 PM PDT 24
Peak memory 214868 kb
Host smart-9a2df963-3684-4615-95d9-e20ea250231d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562202130 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2562202130
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1867435762
Short name T100
Test name
Test status
Simulation time 222647127 ps
CPU time 2.33 seconds
Started Jul 03 04:47:29 PM PDT 24
Finished Jul 03 04:47:32 PM PDT 24
Peak memory 213328 kb
Host smart-f9d297ac-bb94-4c40-a6ee-e394bf3e916a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867435762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1867435762
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2549212348
Short name T338
Test name
Test status
Simulation time 83681548539 ps
CPU time 214.1 seconds
Started Jul 03 04:47:23 PM PDT 24
Finished Jul 03 04:50:58 PM PDT 24
Peak memory 204992 kb
Host smart-194e0448-1812-48b7-a9d3-e18a364affd5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549212348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.2549212348
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4164036310
Short name T304
Test name
Test status
Simulation time 5595905249 ps
CPU time 5.5 seconds
Started Jul 03 04:47:24 PM PDT 24
Finished Jul 03 04:47:30 PM PDT 24
Peak memory 204992 kb
Host smart-33e5e043-6772-4a8e-8e8f-195b3e2ded62
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164036310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
4164036310
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3687227917
Short name T360
Test name
Test status
Simulation time 97223820 ps
CPU time 0.92 seconds
Started Jul 03 04:47:25 PM PDT 24
Finished Jul 03 04:47:27 PM PDT 24
Peak memory 204752 kb
Host smart-9cadd815-deb6-4a94-a0ca-194b96f2367d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687227917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3687227917
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3418430458
Short name T365
Test name
Test status
Simulation time 443537184 ps
CPU time 6.31 seconds
Started Jul 03 04:47:33 PM PDT 24
Finished Jul 03 04:47:40 PM PDT 24
Peak memory 205172 kb
Host smart-31c18519-ca25-495a-90c0-7ccb607f5076
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418430458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3418430458
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.149577829
Short name T362
Test name
Test status
Simulation time 102920129 ps
CPU time 4.16 seconds
Started Jul 03 04:47:23 PM PDT 24
Finished Jul 03 04:47:28 PM PDT 24
Peak memory 221412 kb
Host smart-10b8cda6-5190-444b-ae5c-385d924c2af6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149577829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.149577829
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3780415986
Short name T377
Test name
Test status
Simulation time 1542886173 ps
CPU time 9.89 seconds
Started Jul 03 04:47:33 PM PDT 24
Finished Jul 03 04:47:44 PM PDT 24
Peak memory 213284 kb
Host smart-115e7d87-f070-4620-a880-c99879e0434a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780415986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
780415986
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1334740112
Short name T346
Test name
Test status
Simulation time 339644649 ps
CPU time 2.48 seconds
Started Jul 03 04:47:29 PM PDT 24
Finished Jul 03 04:47:32 PM PDT 24
Peak memory 217032 kb
Host smart-588a294f-4dce-4daa-be9d-c29d12dc4695
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334740112 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1334740112
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3579790043
Short name T318
Test name
Test status
Simulation time 333018224 ps
CPU time 2.43 seconds
Started Jul 03 04:47:32 PM PDT 24
Finished Jul 03 04:47:35 PM PDT 24
Peak memory 213420 kb
Host smart-e9c27182-d35f-4520-afd6-281b822a38c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579790043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3579790043
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.543172365
Short name T328
Test name
Test status
Simulation time 12330212430 ps
CPU time 16.1 seconds
Started Jul 03 04:47:31 PM PDT 24
Finished Jul 03 04:47:48 PM PDT 24
Peak memory 205008 kb
Host smart-4769119a-b0f5-42af-9dd7-21b5599337c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543172365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.543172365
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3702744845
Short name T336
Test name
Test status
Simulation time 5576222229 ps
CPU time 16.38 seconds
Started Jul 03 04:47:33 PM PDT 24
Finished Jul 03 04:47:50 PM PDT 24
Peak memory 205060 kb
Host smart-dc381a34-2410-452e-a77d-24aec54c90ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702744845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3702744845
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3282115274
Short name T307
Test name
Test status
Simulation time 873364456 ps
CPU time 2.88 seconds
Started Jul 03 04:47:32 PM PDT 24
Finished Jul 03 04:47:35 PM PDT 24
Peak memory 204800 kb
Host smart-6d09afd1-92e1-4aed-9bc8-eea8a1533658
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282115274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3282115274
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1177901250
Short name T410
Test name
Test status
Simulation time 568324098 ps
CPU time 6.07 seconds
Started Jul 03 04:47:29 PM PDT 24
Finished Jul 03 04:47:36 PM PDT 24
Peak memory 205104 kb
Host smart-c801a0a6-c7c0-484b-ada3-f5afca76f230
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177901250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1177901250
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2904809755
Short name T416
Test name
Test status
Simulation time 283757170 ps
CPU time 3.55 seconds
Started Jul 03 04:47:33 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 213376 kb
Host smart-14df5bc3-42d4-4110-b967-20567a274f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904809755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2904809755
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2768296752
Short name T171
Test name
Test status
Simulation time 1879853583 ps
CPU time 18.89 seconds
Started Jul 03 04:47:32 PM PDT 24
Finished Jul 03 04:47:51 PM PDT 24
Peak memory 213336 kb
Host smart-fcf69e78-17e8-4310-83e8-fe71cf306b29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768296752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
768296752
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.513765066
Short name T316
Test name
Test status
Simulation time 321870459 ps
CPU time 2.45 seconds
Started Jul 03 04:47:34 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 216620 kb
Host smart-cc185189-6886-4f94-a336-081ad55fd76f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513765066 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.513765066
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1318969587
Short name T382
Test name
Test status
Simulation time 96088269 ps
CPU time 1.54 seconds
Started Jul 03 04:47:31 PM PDT 24
Finished Jul 03 04:47:33 PM PDT 24
Peak memory 213316 kb
Host smart-03001eaa-ca07-4a97-af99-f72a53d761fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318969587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1318969587
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2442113702
Short name T344
Test name
Test status
Simulation time 3775774293 ps
CPU time 10.26 seconds
Started Jul 03 04:47:29 PM PDT 24
Finished Jul 03 04:47:40 PM PDT 24
Peak memory 205036 kb
Host smart-bb69ddec-55de-47f3-98c1-61d7552f6771
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442113702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2442113702
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1727140188
Short name T364
Test name
Test status
Simulation time 3429999386 ps
CPU time 9.89 seconds
Started Jul 03 04:47:31 PM PDT 24
Finished Jul 03 04:47:42 PM PDT 24
Peak memory 204924 kb
Host smart-1d614172-27fb-443a-9211-ea1aeea82094
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727140188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1727140188
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3759642587
Short name T298
Test name
Test status
Simulation time 201318085 ps
CPU time 0.89 seconds
Started Jul 03 04:47:32 PM PDT 24
Finished Jul 03 04:47:34 PM PDT 24
Peak memory 204760 kb
Host smart-e05d51d3-395f-41b7-ad70-1e1d0af46751
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759642587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3759642587
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1991903485
Short name T110
Test name
Test status
Simulation time 5631479751 ps
CPU time 8.01 seconds
Started Jul 03 04:47:32 PM PDT 24
Finished Jul 03 04:47:41 PM PDT 24
Peak memory 205228 kb
Host smart-86e0f49a-c7a4-476c-8777-87e793b55282
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991903485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1991903485
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1432388869
Short name T126
Test name
Test status
Simulation time 1736899228 ps
CPU time 4.42 seconds
Started Jul 03 04:47:33 PM PDT 24
Finished Jul 03 04:47:38 PM PDT 24
Peak memory 213364 kb
Host smart-bec778bc-ad77-410f-ab1b-62d3f5813a00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432388869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1432388869
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1167281399
Short name T92
Test name
Test status
Simulation time 1711879032 ps
CPU time 10.18 seconds
Started Jul 03 04:47:34 PM PDT 24
Finished Jul 03 04:47:45 PM PDT 24
Peak memory 213332 kb
Host smart-3a78853a-2936-433c-bb00-dad546ea95ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167281399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
167281399
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1442527898
Short name T385
Test name
Test status
Simulation time 3997265441 ps
CPU time 6.24 seconds
Started Jul 03 04:47:33 PM PDT 24
Finished Jul 03 04:47:41 PM PDT 24
Peak memory 213420 kb
Host smart-827f85de-8f5d-4e5b-af40-4d2b3ca7f8ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442527898 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1442527898
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.268731592
Short name T118
Test name
Test status
Simulation time 201280547 ps
CPU time 2.26 seconds
Started Jul 03 04:47:32 PM PDT 24
Finished Jul 03 04:47:34 PM PDT 24
Peak memory 213384 kb
Host smart-05533449-8520-47d7-9ed0-c6a75432b048
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268731592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.268731592
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3142051714
Short name T411
Test name
Test status
Simulation time 8990738308 ps
CPU time 12.92 seconds
Started Jul 03 04:47:34 PM PDT 24
Finished Jul 03 04:47:48 PM PDT 24
Peak memory 204988 kb
Host smart-93358822-1ced-4a23-b59a-6b68ef0b5407
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142051714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.3142051714
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3494634154
Short name T406
Test name
Test status
Simulation time 4522202155 ps
CPU time 3.64 seconds
Started Jul 03 04:47:30 PM PDT 24
Finished Jul 03 04:47:34 PM PDT 24
Peak memory 204904 kb
Host smart-cf5d716a-e3c1-4a0d-ab6d-346a8c29e2f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494634154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3494634154
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1288320017
Short name T390
Test name
Test status
Simulation time 870900070 ps
CPU time 0.85 seconds
Started Jul 03 04:47:31 PM PDT 24
Finished Jul 03 04:47:32 PM PDT 24
Peak memory 204756 kb
Host smart-67e0f92c-b700-41f2-9f19-51032022a630
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288320017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1288320017
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2812982099
Short name T111
Test name
Test status
Simulation time 574915204 ps
CPU time 6.91 seconds
Started Jul 03 04:47:33 PM PDT 24
Finished Jul 03 04:47:40 PM PDT 24
Peak memory 205132 kb
Host smart-dfa799dd-37b7-4bfa-b889-edb88417eed4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812982099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2812982099
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2345698233
Short name T132
Test name
Test status
Simulation time 182226246 ps
CPU time 3.2 seconds
Started Jul 03 04:47:33 PM PDT 24
Finished Jul 03 04:47:38 PM PDT 24
Peak memory 213280 kb
Host smart-4e876d0e-fa27-47d6-ada6-c0ef50d3a028
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345698233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2345698233
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3313034254
Short name T169
Test name
Test status
Simulation time 826212613 ps
CPU time 9.63 seconds
Started Jul 03 04:47:34 PM PDT 24
Finished Jul 03 04:47:44 PM PDT 24
Peak memory 213308 kb
Host smart-acef5d0a-9237-4a7f-b8df-39e281df72aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313034254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
313034254
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.4204783738
Short name T352
Test name
Test status
Simulation time 9158378268 ps
CPU time 33.42 seconds
Started Jul 03 04:47:06 PM PDT 24
Finished Jul 03 04:47:40 PM PDT 24
Peak memory 213436 kb
Host smart-32339228-998b-4066-bf90-40f443dde273
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204783738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.4204783738
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3434816527
Short name T391
Test name
Test status
Simulation time 2843939763 ps
CPU time 28.99 seconds
Started Jul 03 04:47:05 PM PDT 24
Finished Jul 03 04:47:34 PM PDT 24
Peak memory 205224 kb
Host smart-fd860be4-e467-49aa-86f0-49a00baecfb9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434816527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3434816527
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3068389940
Short name T119
Test name
Test status
Simulation time 186004028 ps
CPU time 2.68 seconds
Started Jul 03 04:47:07 PM PDT 24
Finished Jul 03 04:47:10 PM PDT 24
Peak memory 213484 kb
Host smart-9fe9de4f-497e-4b6e-9216-7ce56f823991
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068389940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3068389940
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2648497595
Short name T95
Test name
Test status
Simulation time 334439755 ps
CPU time 4.38 seconds
Started Jul 03 04:47:09 PM PDT 24
Finished Jul 03 04:47:13 PM PDT 24
Peak memory 221608 kb
Host smart-a19fe78b-5e71-40c3-be4e-37d11c3ef3f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648497595 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2648497595
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1569463974
Short name T117
Test name
Test status
Simulation time 77632481 ps
CPU time 1.69 seconds
Started Jul 03 04:47:08 PM PDT 24
Finished Jul 03 04:47:10 PM PDT 24
Peak memory 213300 kb
Host smart-7317711f-f1f2-44c7-9d8c-ded14c047c15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569463974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1569463974
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.382490414
Short name T412
Test name
Test status
Simulation time 94368534956 ps
CPU time 228.06 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 04:50:52 PM PDT 24
Peak memory 204996 kb
Host smart-ffff1e53-62b0-48ed-ac87-2c2ef08179b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382490414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.382490414
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3433283621
Short name T289
Test name
Test status
Simulation time 87009009447 ps
CPU time 52.96 seconds
Started Jul 03 04:47:02 PM PDT 24
Finished Jul 03 04:47:56 PM PDT 24
Peak memory 205028 kb
Host smart-2be5ca74-c77b-4f74-990d-3bb2878e34cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433283621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.3433283621
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4265030499
Short name T103
Test name
Test status
Simulation time 3160830196 ps
CPU time 2.05 seconds
Started Jul 03 04:47:01 PM PDT 24
Finished Jul 03 04:47:04 PM PDT 24
Peak memory 205188 kb
Host smart-95592068-9ab1-4297-a720-2612c7495a4b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265030499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.4265030499
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2552341541
Short name T282
Test name
Test status
Simulation time 3034358297 ps
CPU time 9.44 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 04:47:13 PM PDT 24
Peak memory 205012 kb
Host smart-ff68e70a-6f09-47c1-af22-cd732d0fa0d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552341541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
552341541
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2949274318
Short name T308
Test name
Test status
Simulation time 572195676 ps
CPU time 1.26 seconds
Started Jul 03 04:47:05 PM PDT 24
Finished Jul 03 04:47:07 PM PDT 24
Peak memory 204744 kb
Host smart-29821367-087c-418b-9367-995d42aeaf26
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949274318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2949274318
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.402575929
Short name T404
Test name
Test status
Simulation time 17576919772 ps
CPU time 13.98 seconds
Started Jul 03 04:47:04 PM PDT 24
Finished Jul 03 04:47:18 PM PDT 24
Peak memory 204972 kb
Host smart-2b77b659-da07-48d2-b84f-007fb573cb4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402575929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.402575929
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2505038435
Short name T295
Test name
Test status
Simulation time 331551888 ps
CPU time 0.85 seconds
Started Jul 03 04:47:04 PM PDT 24
Finished Jul 03 04:47:05 PM PDT 24
Peak memory 204796 kb
Host smart-5b7c150e-0f95-445b-b0c6-e21b6708044c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505038435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2505038435
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3218120850
Short name T326
Test name
Test status
Simulation time 162460787 ps
CPU time 1.04 seconds
Started Jul 03 04:47:05 PM PDT 24
Finished Jul 03 04:47:06 PM PDT 24
Peak memory 204752 kb
Host smart-1f9fbf06-d2d2-46ed-a91e-252d74c17a4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218120850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
218120850
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3499921524
Short name T327
Test name
Test status
Simulation time 37956414 ps
CPU time 0.73 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 04:47:05 PM PDT 24
Peak memory 204496 kb
Host smart-8f17ad3b-2fb4-4af5-a41f-185b433879ce
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499921524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3499921524
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1750924377
Short name T353
Test name
Test status
Simulation time 187667392 ps
CPU time 0.8 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 04:47:05 PM PDT 24
Peak memory 204800 kb
Host smart-f812f0c4-2cd8-4de7-88da-b5e17cbd7848
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750924377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1750924377
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2633477377
Short name T65
Test name
Test status
Simulation time 167916092 ps
CPU time 3.58 seconds
Started Jul 03 04:47:06 PM PDT 24
Finished Jul 03 04:47:10 PM PDT 24
Peak memory 205076 kb
Host smart-91e770ac-0f74-4df8-815a-049bd8ac69fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633477377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2633477377
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3380990042
Short name T90
Test name
Test status
Simulation time 259869775 ps
CPU time 2.43 seconds
Started Jul 03 04:47:03 PM PDT 24
Finished Jul 03 04:47:07 PM PDT 24
Peak memory 213180 kb
Host smart-d3a703bf-6cd2-4244-97e2-6d6f1fe55034
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380990042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3380990042
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4280587246
Short name T94
Test name
Test status
Simulation time 3496567021 ps
CPU time 17.02 seconds
Started Jul 03 04:47:02 PM PDT 24
Finished Jul 03 04:47:20 PM PDT 24
Peak memory 213372 kb
Host smart-c88451c1-6904-428c-aa18-7f7b8aee0bc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280587246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.4280587246
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1625856221
Short name T399
Test name
Test status
Simulation time 16956070191 ps
CPU time 81.09 seconds
Started Jul 03 04:47:08 PM PDT 24
Finished Jul 03 04:48:29 PM PDT 24
Peak memory 213404 kb
Host smart-cabd2719-ab1f-4890-8d8d-53a5bc7c4444
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625856221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1625856221
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3131281912
Short name T101
Test name
Test status
Simulation time 813503569 ps
CPU time 28.3 seconds
Started Jul 03 04:47:11 PM PDT 24
Finished Jul 03 04:47:39 PM PDT 24
Peak memory 205164 kb
Host smart-3ccee3d2-4cad-40dd-bbf5-82aeed391b4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131281912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3131281912
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1385159326
Short name T290
Test name
Test status
Simulation time 262655970 ps
CPU time 3.06 seconds
Started Jul 03 04:47:13 PM PDT 24
Finished Jul 03 04:47:17 PM PDT 24
Peak memory 221624 kb
Host smart-9915c93e-4074-437c-9b5d-a9c9dc233220
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385159326 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1385159326
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3449915215
Short name T102
Test name
Test status
Simulation time 76412887 ps
CPU time 1.47 seconds
Started Jul 03 04:47:10 PM PDT 24
Finished Jul 03 04:47:11 PM PDT 24
Peak memory 213244 kb
Host smart-329dfadd-a4e0-4b21-a086-8feef66a5a2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449915215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3449915215
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.776435955
Short name T285
Test name
Test status
Simulation time 55630310048 ps
CPU time 143.98 seconds
Started Jul 03 04:47:09 PM PDT 24
Finished Jul 03 04:49:34 PM PDT 24
Peak memory 204976 kb
Host smart-d92d7c9a-99e0-486b-b6c2-0a101d266924
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776435955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.776435955
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1477249106
Short name T284
Test name
Test status
Simulation time 12273683499 ps
CPU time 8.68 seconds
Started Jul 03 04:47:10 PM PDT 24
Finished Jul 03 04:47:19 PM PDT 24
Peak memory 204964 kb
Host smart-8029f660-1879-4059-9864-f26ac6e952ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477249106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.1477249106
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2701498032
Short name T384
Test name
Test status
Simulation time 1815149905 ps
CPU time 4.96 seconds
Started Jul 03 04:47:08 PM PDT 24
Finished Jul 03 04:47:13 PM PDT 24
Peak memory 204996 kb
Host smart-f310a959-de1f-4722-9f9f-d567ead350aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701498032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2701498032
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1366729675
Short name T400
Test name
Test status
Simulation time 3022494858 ps
CPU time 2.91 seconds
Started Jul 03 04:47:07 PM PDT 24
Finished Jul 03 04:47:10 PM PDT 24
Peak memory 205044 kb
Host smart-e37a4eeb-19bb-4b1f-a3cf-9a068857b16b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366729675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
366729675
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4148401521
Short name T310
Test name
Test status
Simulation time 641201922 ps
CPU time 1.22 seconds
Started Jul 03 04:47:11 PM PDT 24
Finished Jul 03 04:47:12 PM PDT 24
Peak memory 204760 kb
Host smart-53cc80e6-b3e5-4268-bb61-d5f27d8efa05
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148401521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.4148401521
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.4289433579
Short name T421
Test name
Test status
Simulation time 6644893787 ps
CPU time 10.69 seconds
Started Jul 03 04:47:07 PM PDT 24
Finished Jul 03 04:47:18 PM PDT 24
Peak memory 205000 kb
Host smart-00d35c72-08b8-4e6d-a96c-98b31270c9a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289433579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.4289433579
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3802944573
Short name T366
Test name
Test status
Simulation time 768009544 ps
CPU time 1.26 seconds
Started Jul 03 04:47:09 PM PDT 24
Finished Jul 03 04:47:11 PM PDT 24
Peak memory 204824 kb
Host smart-08b0010c-898d-4255-a9da-e18b52031874
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802944573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3802944573
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2384772804
Short name T380
Test name
Test status
Simulation time 124659635 ps
CPU time 1 seconds
Started Jul 03 04:47:07 PM PDT 24
Finished Jul 03 04:47:09 PM PDT 24
Peak memory 204756 kb
Host smart-83b82369-2e73-4016-b44a-9e5a8fcc6a4c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384772804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
384772804
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.623011116
Short name T401
Test name
Test status
Simulation time 29885104 ps
CPU time 0.79 seconds
Started Jul 03 04:47:06 PM PDT 24
Finished Jul 03 04:47:07 PM PDT 24
Peak memory 204728 kb
Host smart-f8c3f252-0edf-4818-9d1b-2954887effdc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623011116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.623011116
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.168360372
Short name T300
Test name
Test status
Simulation time 128733714 ps
CPU time 0.7 seconds
Started Jul 03 04:47:08 PM PDT 24
Finished Jul 03 04:47:09 PM PDT 24
Peak memory 204792 kb
Host smart-d07cbb30-56c0-44ed-880e-398e95d8847b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168360372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.168360372
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3040682606
Short name T124
Test name
Test status
Simulation time 597628722 ps
CPU time 3.7 seconds
Started Jul 03 04:47:11 PM PDT 24
Finished Jul 03 04:47:15 PM PDT 24
Peak memory 205152 kb
Host smart-982a34bf-126c-4975-9f90-7587ae422f7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040682606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3040682606
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4162266780
Short name T342
Test name
Test status
Simulation time 245310864 ps
CPU time 2.45 seconds
Started Jul 03 04:47:11 PM PDT 24
Finished Jul 03 04:47:14 PM PDT 24
Peak memory 213328 kb
Host smart-faefd12b-5e0c-4193-a5f4-f1f16e9fed0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162266780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4162266780
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.4083802134
Short name T319
Test name
Test status
Simulation time 1092333224 ps
CPU time 10.8 seconds
Started Jul 03 04:47:09 PM PDT 24
Finished Jul 03 04:47:20 PM PDT 24
Peak memory 213300 kb
Host smart-575d599c-2a61-48f5-97ec-38f260ede257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083802134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.4083802134
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2476379064
Short name T430
Test name
Test status
Simulation time 3815846719 ps
CPU time 32.61 seconds
Started Jul 03 04:47:10 PM PDT 24
Finished Jul 03 04:47:43 PM PDT 24
Peak memory 205192 kb
Host smart-efdf087f-7a5d-469c-9c98-aa35df8c0d9c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476379064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2476379064
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3711410168
Short name T106
Test name
Test status
Simulation time 1222077879 ps
CPU time 26.24 seconds
Started Jul 03 04:47:10 PM PDT 24
Finished Jul 03 04:47:37 PM PDT 24
Peak memory 205084 kb
Host smart-6252cc36-d2bf-41ea-b555-77cb970f7b5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711410168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3711410168
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3023525475
Short name T405
Test name
Test status
Simulation time 359721863 ps
CPU time 2.4 seconds
Started Jul 03 04:47:11 PM PDT 24
Finished Jul 03 04:47:14 PM PDT 24
Peak memory 213388 kb
Host smart-221d7ddc-2374-40b9-a163-47f2e6fdb279
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023525475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3023525475
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.18190409
Short name T388
Test name
Test status
Simulation time 992051678 ps
CPU time 2.35 seconds
Started Jul 03 04:47:10 PM PDT 24
Finished Jul 03 04:47:13 PM PDT 24
Peak memory 214692 kb
Host smart-0d107a3d-ccd1-4fca-bf56-5c40c2cfd582
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18190409 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.18190409
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2135901046
Short name T413
Test name
Test status
Simulation time 202575786 ps
CPU time 2.72 seconds
Started Jul 03 04:47:12 PM PDT 24
Finished Jul 03 04:47:15 PM PDT 24
Peak memory 213232 kb
Host smart-bc6f42e0-8c82-4786-b483-e9211c1d816d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135901046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2135901046
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1177052363
Short name T301
Test name
Test status
Simulation time 113255357592 ps
CPU time 67.72 seconds
Started Jul 03 04:47:09 PM PDT 24
Finished Jul 03 04:48:17 PM PDT 24
Peak memory 205056 kb
Host smart-bdad7073-0787-4ed4-86a9-c012d56a4af2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177052363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1177052363
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2473732774
Short name T340
Test name
Test status
Simulation time 19567801988 ps
CPU time 20.72 seconds
Started Jul 03 04:47:12 PM PDT 24
Finished Jul 03 04:47:33 PM PDT 24
Peak memory 205040 kb
Host smart-12cb2d64-3bb3-42e2-8d9e-ed64a7a87661
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473732774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.2473732774
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2770748303
Short name T422
Test name
Test status
Simulation time 2410722326 ps
CPU time 1.6 seconds
Started Jul 03 04:47:15 PM PDT 24
Finished Jul 03 04:47:17 PM PDT 24
Peak memory 204980 kb
Host smart-188c3f79-9b54-4a05-bf4e-aac8df26e06b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770748303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2770748303
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3289218146
Short name T370
Test name
Test status
Simulation time 6441379712 ps
CPU time 17.63 seconds
Started Jul 03 04:47:12 PM PDT 24
Finished Jul 03 04:47:30 PM PDT 24
Peak memory 205012 kb
Host smart-f52af159-c882-4e3e-a5dd-42ba13c2f0aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289218146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
289218146
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2511865886
Short name T325
Test name
Test status
Simulation time 422619241 ps
CPU time 1.29 seconds
Started Jul 03 04:47:12 PM PDT 24
Finished Jul 03 04:47:13 PM PDT 24
Peak memory 204740 kb
Host smart-a6717517-1c44-4717-8658-23825333466c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511865886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2511865886
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.4062393978
Short name T87
Test name
Test status
Simulation time 34838936461 ps
CPU time 48.71 seconds
Started Jul 03 04:47:12 PM PDT 24
Finished Jul 03 04:48:01 PM PDT 24
Peak memory 205028 kb
Host smart-6f4b84e2-da57-46e8-95ba-b6e47a6f4d3d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062393978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.4062393978
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2843621898
Short name T330
Test name
Test status
Simulation time 772193614 ps
CPU time 2.03 seconds
Started Jul 03 04:47:12 PM PDT 24
Finished Jul 03 04:47:14 PM PDT 24
Peak memory 204756 kb
Host smart-bfeb4104-3f92-492a-a252-9e1a43c64f79
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843621898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2843621898
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2134662330
Short name T299
Test name
Test status
Simulation time 1041970793 ps
CPU time 3.28 seconds
Started Jul 03 04:47:16 PM PDT 24
Finished Jul 03 04:47:20 PM PDT 24
Peak memory 204676 kb
Host smart-b8533dce-9bbd-4d98-9567-a7f0b92055ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134662330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
134662330
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.4198703545
Short name T402
Test name
Test status
Simulation time 82619943 ps
CPU time 0.69 seconds
Started Jul 03 04:47:13 PM PDT 24
Finished Jul 03 04:47:15 PM PDT 24
Peak memory 204656 kb
Host smart-ee084234-803d-4891-af48-baa5642abfa0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198703545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.4198703545
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.954057284
Short name T361
Test name
Test status
Simulation time 120476818 ps
CPU time 0.81 seconds
Started Jul 03 04:47:12 PM PDT 24
Finished Jul 03 04:47:13 PM PDT 24
Peak memory 204796 kb
Host smart-381815cc-34c8-42bc-8804-79c8dc433fab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954057284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.954057284
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.624363402
Short name T396
Test name
Test status
Simulation time 586765546 ps
CPU time 6.58 seconds
Started Jul 03 04:47:12 PM PDT 24
Finished Jul 03 04:47:19 PM PDT 24
Peak memory 205072 kb
Host smart-ac2d9a34-ccbe-4735-a898-1b22cac63eee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624363402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.624363402
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2007407158
Short name T349
Test name
Test status
Simulation time 60714753086 ps
CPU time 42.07 seconds
Started Jul 03 04:47:11 PM PDT 24
Finished Jul 03 04:47:54 PM PDT 24
Peak memory 222876 kb
Host smart-641b1dad-8f03-4105-91a3-eee426a1ac27
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007407158 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2007407158
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4119950280
Short name T129
Test name
Test status
Simulation time 493695890 ps
CPU time 2.89 seconds
Started Jul 03 04:47:11 PM PDT 24
Finished Jul 03 04:47:14 PM PDT 24
Peak memory 213336 kb
Host smart-2e8fc8ed-a2a7-4b0c-9c0b-017958d4ed8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119950280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.4119950280
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.4289478461
Short name T417
Test name
Test status
Simulation time 2162176131 ps
CPU time 17.04 seconds
Started Jul 03 04:47:11 PM PDT 24
Finished Jul 03 04:47:28 PM PDT 24
Peak memory 213320 kb
Host smart-616bc187-20f4-42db-ae44-bc8fe23671e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289478461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.4289478461
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2102970515
Short name T93
Test name
Test status
Simulation time 2465242430 ps
CPU time 3.17 seconds
Started Jul 03 04:47:20 PM PDT 24
Finished Jul 03 04:47:24 PM PDT 24
Peak memory 213408 kb
Host smart-395deee6-1ac3-41d5-a481-a65e43b35db6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102970515 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2102970515
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4159325228
Short name T105
Test name
Test status
Simulation time 88167861 ps
CPU time 2.08 seconds
Started Jul 03 04:47:12 PM PDT 24
Finished Jul 03 04:47:14 PM PDT 24
Peak memory 213332 kb
Host smart-915ed839-e5ec-427f-bd5b-64310122e9b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159325228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.4159325228
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1964077012
Short name T415
Test name
Test status
Simulation time 7268639606 ps
CPU time 6.65 seconds
Started Jul 03 04:47:12 PM PDT 24
Finished Jul 03 04:47:19 PM PDT 24
Peak memory 205048 kb
Host smart-69858433-8f31-4635-98f5-453ee8f11971
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964077012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.1964077012
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.87004501
Short name T297
Test name
Test status
Simulation time 6575192920 ps
CPU time 19.85 seconds
Started Jul 03 04:47:13 PM PDT 24
Finished Jul 03 04:47:33 PM PDT 24
Peak memory 205016 kb
Host smart-83381eb3-44c6-440c-89db-4e035d7460c0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87004501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.87004501
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4018651574
Short name T392
Test name
Test status
Simulation time 532815535 ps
CPU time 2.11 seconds
Started Jul 03 04:47:10 PM PDT 24
Finished Jul 03 04:47:13 PM PDT 24
Peak memory 204744 kb
Host smart-9eaaaf33-f6e6-494d-a860-64258d36acd4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018651574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.4
018651574
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2555077597
Short name T113
Test name
Test status
Simulation time 624918913 ps
CPU time 8.04 seconds
Started Jul 03 04:47:20 PM PDT 24
Finished Jul 03 04:47:29 PM PDT 24
Peak memory 205128 kb
Host smart-bc82ab3e-7f90-4ce9-be8d-779e2d857322
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555077597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2555077597
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3565449026
Short name T176
Test name
Test status
Simulation time 23364252877 ps
CPU time 57.61 seconds
Started Jul 03 04:47:13 PM PDT 24
Finished Jul 03 04:48:11 PM PDT 24
Peak memory 220996 kb
Host smart-1632945b-4550-45a7-9de1-eee7a8f012a7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565449026 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3565449026
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3646721532
Short name T428
Test name
Test status
Simulation time 386105327 ps
CPU time 2.25 seconds
Started Jul 03 04:47:11 PM PDT 24
Finished Jul 03 04:47:13 PM PDT 24
Peak memory 213320 kb
Host smart-e44db245-8edc-4850-9e0b-eddb684c80dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646721532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3646721532
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.4167270069
Short name T166
Test name
Test status
Simulation time 3994771782 ps
CPU time 17.5 seconds
Started Jul 03 04:47:13 PM PDT 24
Finished Jul 03 04:47:31 PM PDT 24
Peak memory 213408 kb
Host smart-4779f5bf-f087-4ecd-9998-3ccb8494b968
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167270069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.4167270069
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3601877270
Short name T369
Test name
Test status
Simulation time 3534683451 ps
CPU time 7.65 seconds
Started Jul 03 04:47:20 PM PDT 24
Finished Jul 03 04:47:28 PM PDT 24
Peak memory 213476 kb
Host smart-86822be5-9499-430a-98fb-98a77c56adf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601877270 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3601877270
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3045439792
Short name T115
Test name
Test status
Simulation time 435460989 ps
CPU time 2.55 seconds
Started Jul 03 04:47:18 PM PDT 24
Finished Jul 03 04:47:21 PM PDT 24
Peak memory 213324 kb
Host smart-d7cc5ec3-1bbc-4201-9aa9-c2de4497ff93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045439792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3045439792
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3443337548
Short name T397
Test name
Test status
Simulation time 2926657992 ps
CPU time 3.85 seconds
Started Jul 03 04:47:14 PM PDT 24
Finished Jul 03 04:47:18 PM PDT 24
Peak memory 204988 kb
Host smart-13b70d08-6206-4135-b642-a2f83da1c8ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443337548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.3443337548
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3875972014
Short name T286
Test name
Test status
Simulation time 3669243033 ps
CPU time 2.18 seconds
Started Jul 03 04:47:25 PM PDT 24
Finished Jul 03 04:47:27 PM PDT 24
Peak memory 204980 kb
Host smart-af2de36d-182e-4cda-ba4f-1e6a41144a76
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875972014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
875972014
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3390286956
Short name T372
Test name
Test status
Simulation time 176209312 ps
CPU time 0.94 seconds
Started Jul 03 04:47:21 PM PDT 24
Finished Jul 03 04:47:23 PM PDT 24
Peak memory 204764 kb
Host smart-4f292da7-abdc-4f7c-bed6-6425c2f0c7e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390286956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
390286956
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.81337994
Short name T108
Test name
Test status
Simulation time 129402644 ps
CPU time 3.62 seconds
Started Jul 03 04:47:16 PM PDT 24
Finished Jul 03 04:47:20 PM PDT 24
Peak memory 205116 kb
Host smart-6555665b-4436-4be4-b57f-6ccf34f4fdb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81337994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_cs
r_outstanding.81337994
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.615788108
Short name T359
Test name
Test status
Simulation time 27203943357 ps
CPU time 77 seconds
Started Jul 03 04:47:25 PM PDT 24
Finished Jul 03 04:48:42 PM PDT 24
Peak memory 221452 kb
Host smart-c03ea2f3-2471-4adf-8536-549b6a2ad91c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615788108 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.615788108
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.928859433
Short name T130
Test name
Test status
Simulation time 1577035243 ps
CPU time 5.61 seconds
Started Jul 03 04:47:15 PM PDT 24
Finished Jul 03 04:47:21 PM PDT 24
Peak memory 213356 kb
Host smart-9d6ff647-6fa6-4265-af82-17e354cb1dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928859433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.928859433
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2457635789
Short name T381
Test name
Test status
Simulation time 232380780 ps
CPU time 2.87 seconds
Started Jul 03 04:47:16 PM PDT 24
Finished Jul 03 04:47:19 PM PDT 24
Peak memory 213372 kb
Host smart-cf698f5d-8d63-4b38-a00e-576f938a5912
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457635789 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2457635789
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.717760166
Short name T116
Test name
Test status
Simulation time 323540472 ps
CPU time 2.55 seconds
Started Jul 03 04:47:25 PM PDT 24
Finished Jul 03 04:47:28 PM PDT 24
Peak memory 213160 kb
Host smart-2fa34477-e237-4bdd-8ece-b20f17ad92d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717760166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.717760166
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.3286303107
Short name T339
Test name
Test status
Simulation time 59286600166 ps
CPU time 38.6 seconds
Started Jul 03 04:47:21 PM PDT 24
Finished Jul 03 04:48:00 PM PDT 24
Peak memory 205008 kb
Host smart-ba506ad5-5b9c-40a5-8f35-1c911e566384
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286303107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.3286303107
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2435709672
Short name T283
Test name
Test status
Simulation time 2929470406 ps
CPU time 5.64 seconds
Started Jul 03 04:47:15 PM PDT 24
Finished Jul 03 04:47:22 PM PDT 24
Peak memory 204988 kb
Host smart-498bfe46-a028-4b69-a026-eeb77bc5f311
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435709672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
435709672
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3365821380
Short name T88
Test name
Test status
Simulation time 98967267 ps
CPU time 0.84 seconds
Started Jul 03 04:47:25 PM PDT 24
Finished Jul 03 04:47:26 PM PDT 24
Peak memory 204748 kb
Host smart-659761cc-e827-42a9-8410-0dc1ac6272d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365821380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
365821380
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.380491221
Short name T97
Test name
Test status
Simulation time 590384257 ps
CPU time 8.05 seconds
Started Jul 03 04:47:15 PM PDT 24
Finished Jul 03 04:47:24 PM PDT 24
Peak memory 205068 kb
Host smart-d76c554e-07dc-499e-b114-2422786fd5f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380491221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.380491221
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4148148353
Short name T175
Test name
Test status
Simulation time 56031367044 ps
CPU time 101.94 seconds
Started Jul 03 04:47:25 PM PDT 24
Finished Jul 03 04:49:07 PM PDT 24
Peak memory 229776 kb
Host smart-0e0d613c-e7d6-4c3b-b39f-d636bd042e39
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148148353 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.4148148353
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1037034417
Short name T314
Test name
Test status
Simulation time 2129808753 ps
CPU time 3.31 seconds
Started Jul 03 04:47:13 PM PDT 24
Finished Jul 03 04:47:17 PM PDT 24
Peak memory 213404 kb
Host smart-15ed5b44-adca-4f3d-b811-4eb33dbbd520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037034417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1037034417
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3004028226
Short name T173
Test name
Test status
Simulation time 2232931192 ps
CPU time 10.7 seconds
Started Jul 03 04:47:17 PM PDT 24
Finished Jul 03 04:47:28 PM PDT 24
Peak memory 213360 kb
Host smart-baf88cca-c129-4245-a8e6-3e9f18d6a5a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004028226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3004028226
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1470822990
Short name T356
Test name
Test status
Simulation time 868429805 ps
CPU time 3.99 seconds
Started Jul 03 04:47:20 PM PDT 24
Finished Jul 03 04:47:24 PM PDT 24
Peak memory 221568 kb
Host smart-257098cd-ca94-4ef2-8643-b0c6e6f26b74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470822990 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1470822990
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.820904109
Short name T98
Test name
Test status
Simulation time 120643195 ps
CPU time 2.11 seconds
Started Jul 03 04:47:14 PM PDT 24
Finished Jul 03 04:47:16 PM PDT 24
Peak memory 213376 kb
Host smart-3492e1f9-46e7-421e-94c1-d0e5df0d46bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820904109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.820904109
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3609855814
Short name T288
Test name
Test status
Simulation time 129101853129 ps
CPU time 308.11 seconds
Started Jul 03 04:47:17 PM PDT 24
Finished Jul 03 04:52:25 PM PDT 24
Peak memory 204976 kb
Host smart-67d3283c-4b1c-4877-805b-bb1b4473b91f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609855814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.3609855814
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3450421571
Short name T368
Test name
Test status
Simulation time 5334726784 ps
CPU time 4.58 seconds
Started Jul 03 04:47:16 PM PDT 24
Finished Jul 03 04:47:21 PM PDT 24
Peak memory 205008 kb
Host smart-ee971557-607f-4014-ab88-9ee635cb937e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450421571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
450421571
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2117991801
Short name T86
Test name
Test status
Simulation time 195539154 ps
CPU time 0.9 seconds
Started Jul 03 04:47:14 PM PDT 24
Finished Jul 03 04:47:16 PM PDT 24
Peak memory 204736 kb
Host smart-a9c1b7f9-faba-4735-ae5a-f3ff16c063a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117991801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
117991801
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1619298983
Short name T114
Test name
Test status
Simulation time 95386436 ps
CPU time 3.66 seconds
Started Jul 03 04:47:15 PM PDT 24
Finished Jul 03 04:47:19 PM PDT 24
Peak memory 205208 kb
Host smart-e9fe4ea0-7678-4929-af7d-27e0ed4e932d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619298983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1619298983
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4208877409
Short name T54
Test name
Test status
Simulation time 34590362739 ps
CPU time 14.47 seconds
Started Jul 03 04:47:25 PM PDT 24
Finished Jul 03 04:47:40 PM PDT 24
Peak memory 217620 kb
Host smart-910193b9-1d3e-451f-a61f-bb8873e82a8a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208877409 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.4208877409
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1178120497
Short name T423
Test name
Test status
Simulation time 154966985 ps
CPU time 4.54 seconds
Started Jul 03 04:47:15 PM PDT 24
Finished Jul 03 04:47:20 PM PDT 24
Peak memory 213308 kb
Host smart-8d4cede6-00ae-4fc7-a71f-a3d4ea338d04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178120497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1178120497
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3197894101
Short name T351
Test name
Test status
Simulation time 106797283 ps
CPU time 4.1 seconds
Started Jul 03 04:47:23 PM PDT 24
Finished Jul 03 04:47:27 PM PDT 24
Peak memory 219588 kb
Host smart-22b90758-a122-4390-a0c0-b07e2e435002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197894101 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3197894101
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.182470954
Short name T407
Test name
Test status
Simulation time 63346155 ps
CPU time 1.68 seconds
Started Jul 03 04:47:22 PM PDT 24
Finished Jul 03 04:47:24 PM PDT 24
Peak memory 213268 kb
Host smart-f1d31c06-5851-4e72-9bda-35d506f32696
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182470954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.182470954
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.87262127
Short name T403
Test name
Test status
Simulation time 93803167888 ps
CPU time 63.25 seconds
Started Jul 03 04:47:25 PM PDT 24
Finished Jul 03 04:48:29 PM PDT 24
Peak memory 204964 kb
Host smart-92566562-6222-4197-a4fa-da804ffa3fd3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87262127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv
_dm_jtag_dmi_csr_bit_bash.87262127
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.733205827
Short name T323
Test name
Test status
Simulation time 1282952589 ps
CPU time 2.86 seconds
Started Jul 03 04:47:19 PM PDT 24
Finished Jul 03 04:47:22 PM PDT 24
Peak memory 204944 kb
Host smart-44cb98c4-06f1-4162-86c8-2ae95ad246bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733205827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.733205827
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4219691470
Short name T427
Test name
Test status
Simulation time 256336443 ps
CPU time 0.83 seconds
Started Jul 03 04:47:20 PM PDT 24
Finished Jul 03 04:47:21 PM PDT 24
Peak memory 204792 kb
Host smart-6d8cb30c-e8b0-4905-a279-675b297eb61d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219691470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.4
219691470
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1071806297
Short name T418
Test name
Test status
Simulation time 390256061 ps
CPU time 7.17 seconds
Started Jul 03 04:47:21 PM PDT 24
Finished Jul 03 04:47:29 PM PDT 24
Peak memory 205156 kb
Host smart-74b56485-30e4-448f-8ea1-2f39ee4ecfdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071806297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1071806297
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.860941761
Short name T389
Test name
Test status
Simulation time 18710423705 ps
CPU time 48.03 seconds
Started Jul 03 04:47:20 PM PDT 24
Finished Jul 03 04:48:09 PM PDT 24
Peak memory 221536 kb
Host smart-92e9bd12-adcc-4ec3-865c-9164cdb11cde
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860941761 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.860941761
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3573501971
Short name T383
Test name
Test status
Simulation time 139800956 ps
CPU time 3.26 seconds
Started Jul 03 04:47:19 PM PDT 24
Finished Jul 03 04:47:23 PM PDT 24
Peak memory 213296 kb
Host smart-8533b372-07bd-44fb-88cc-f3913044a510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573501971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3573501971
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.4232941573
Short name T45
Test name
Test status
Simulation time 330817847 ps
CPU time 1.47 seconds
Started Jul 03 05:14:55 PM PDT 24
Finished Jul 03 05:14:56 PM PDT 24
Peak memory 205120 kb
Host smart-905f3b2a-ff5d-42d6-8fab-35a2b43fb8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232941573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.4232941573
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1031474201
Short name T67
Test name
Test status
Simulation time 78993317 ps
CPU time 0.87 seconds
Started Jul 03 05:15:05 PM PDT 24
Finished Jul 03 05:15:06 PM PDT 24
Peak memory 205104 kb
Host smart-26c97db9-5836-4725-8f8f-e35c84f70dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031474201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1031474201
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3986256003
Short name T218
Test name
Test status
Simulation time 35061043086 ps
CPU time 80.02 seconds
Started Jul 03 05:14:45 PM PDT 24
Finished Jul 03 05:16:06 PM PDT 24
Peak memory 213688 kb
Host smart-7cc5fc0a-be7c-4bf8-a147-f414ea78e94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986256003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3986256003
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2007323496
Short name T7
Test name
Test status
Simulation time 189906540 ps
CPU time 0.8 seconds
Started Jul 03 05:14:46 PM PDT 24
Finished Jul 03 05:14:47 PM PDT 24
Peak memory 205092 kb
Host smart-a3325133-f54f-43f5-83ba-b6e085e59fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007323496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2007323496
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2692960538
Short name T39
Test name
Test status
Simulation time 150156806 ps
CPU time 1.1 seconds
Started Jul 03 05:14:53 PM PDT 24
Finished Jul 03 05:14:55 PM PDT 24
Peak memory 205084 kb
Host smart-59b005cd-f9af-4e69-b3dd-90fdcbe8b089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692960538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2692960538
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.3699855421
Short name T55
Test name
Test status
Simulation time 57473118 ps
CPU time 0.91 seconds
Started Jul 03 05:15:00 PM PDT 24
Finished Jul 03 05:15:01 PM PDT 24
Peak memory 215712 kb
Host smart-14a9d3ee-922f-4d50-ab4e-7495cadb0cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699855421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3699855421
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.634838785
Short name T13
Test name
Test status
Simulation time 5439036347 ps
CPU time 5.61 seconds
Started Jul 03 05:14:46 PM PDT 24
Finished Jul 03 05:14:52 PM PDT 24
Peak memory 213676 kb
Host smart-aa13deb0-0a06-424a-9d6b-58d5065334c4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634838785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.634838785
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3203273182
Short name T280
Test name
Test status
Simulation time 194162894 ps
CPU time 0.94 seconds
Started Jul 03 05:14:49 PM PDT 24
Finished Jul 03 05:14:50 PM PDT 24
Peak memory 205064 kb
Host smart-1fb9ac00-fd60-4781-92e1-e8f55247340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203273182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3203273182
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2465057201
Short name T247
Test name
Test status
Simulation time 671954215 ps
CPU time 1.66 seconds
Started Jul 03 05:14:52 PM PDT 24
Finished Jul 03 05:14:54 PM PDT 24
Peak memory 205092 kb
Host smart-5ff66c23-35a9-453d-805c-d1d4a6af8caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465057201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2465057201
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.964691390
Short name T279
Test name
Test status
Simulation time 914176513 ps
CPU time 1.41 seconds
Started Jul 03 05:14:52 PM PDT 24
Finished Jul 03 05:14:54 PM PDT 24
Peak memory 204932 kb
Host smart-566d723d-8239-4968-9a01-d44da4e1db7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964691390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.964691390
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3539889595
Short name T35
Test name
Test status
Simulation time 2260353329 ps
CPU time 2.48 seconds
Started Jul 03 05:14:57 PM PDT 24
Finished Jul 03 05:15:00 PM PDT 24
Peak memory 205176 kb
Host smart-33596f8a-ebb7-47ff-9601-a81fbc9fdd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539889595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3539889595
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.204703981
Short name T199
Test name
Test status
Simulation time 279932093 ps
CPU time 0.83 seconds
Started Jul 03 05:14:50 PM PDT 24
Finished Jul 03 05:14:52 PM PDT 24
Peak memory 205008 kb
Host smart-34422729-4e26-475c-a33d-37e7e9ba5d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204703981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.204703981
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3240985758
Short name T155
Test name
Test status
Simulation time 507555294 ps
CPU time 1.97 seconds
Started Jul 03 05:14:46 PM PDT 24
Finished Jul 03 05:14:49 PM PDT 24
Peak memory 205092 kb
Host smart-812050d5-45e7-4d85-bb71-75e18bdd4968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240985758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3240985758
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.667695448
Short name T179
Test name
Test status
Simulation time 6928823514 ps
CPU time 17.43 seconds
Started Jul 03 05:14:48 PM PDT 24
Finished Jul 03 05:15:06 PM PDT 24
Peak memory 205352 kb
Host smart-50cef160-b008-4d83-89e8-bb889ff0503a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667695448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.667695448
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2019843594
Short name T40
Test name
Test status
Simulation time 304612085 ps
CPU time 1.22 seconds
Started Jul 03 05:14:52 PM PDT 24
Finished Jul 03 05:14:53 PM PDT 24
Peak memory 205124 kb
Host smart-d81f7f44-2d2e-4049-ba27-da5a73c3faa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019843594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2019843594
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3669416743
Short name T56
Test name
Test status
Simulation time 530231771 ps
CPU time 1.4 seconds
Started Jul 03 05:15:04 PM PDT 24
Finished Jul 03 05:15:05 PM PDT 24
Peak memory 229160 kb
Host smart-8066eb58-d6cf-4dce-8f42-9a3352e78b9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669416743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3669416743
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2500399677
Short name T143
Test name
Test status
Simulation time 818322080 ps
CPU time 2.73 seconds
Started Jul 03 05:14:40 PM PDT 24
Finished Jul 03 05:14:43 PM PDT 24
Peak memory 205316 kb
Host smart-741bf67c-d86a-46c6-92ff-b1469aa49af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500399677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2500399677
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2523656142
Short name T10
Test name
Test status
Simulation time 6498013893 ps
CPU time 18.53 seconds
Started Jul 03 05:14:40 PM PDT 24
Finished Jul 03 05:14:59 PM PDT 24
Peak memory 205384 kb
Host smart-17b05ab7-1a17-442c-ad16-d5a11d1d8112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523656142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2523656142
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.4046572045
Short name T196
Test name
Test status
Simulation time 67404974 ps
CPU time 0.72 seconds
Started Jul 03 05:15:28 PM PDT 24
Finished Jul 03 05:15:29 PM PDT 24
Peak memory 205100 kb
Host smart-d66caeca-3497-44b2-8126-2245695c4f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046572045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4046572045
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2862998706
Short name T181
Test name
Test status
Simulation time 6492361958 ps
CPU time 4.44 seconds
Started Jul 03 05:15:09 PM PDT 24
Finished Jul 03 05:15:14 PM PDT 24
Peak memory 213652 kb
Host smart-46e8dd90-4934-4cf9-b3f9-c020078900ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862998706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2862998706
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1482181151
Short name T47
Test name
Test status
Simulation time 907862688 ps
CPU time 1.83 seconds
Started Jul 03 05:15:22 PM PDT 24
Finished Jul 03 05:15:24 PM PDT 24
Peak memory 205092 kb
Host smart-0731f5b4-7ded-44fe-9247-65be7ce89278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482181151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1482181151
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.4274912901
Short name T41
Test name
Test status
Simulation time 145876135 ps
CPU time 0.86 seconds
Started Jul 03 05:15:23 PM PDT 24
Finished Jul 03 05:15:24 PM PDT 24
Peak memory 205088 kb
Host smart-bbd07890-20a2-4585-8fe4-0e0d3b89fa5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274912901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.4274912901
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2984903099
Short name T248
Test name
Test status
Simulation time 164147195 ps
CPU time 0.95 seconds
Started Jul 03 05:15:08 PM PDT 24
Finished Jul 03 05:15:09 PM PDT 24
Peak memory 205052 kb
Host smart-850f4c91-1f10-4204-a319-fb1ddbf47d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984903099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2984903099
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1753679865
Short name T267
Test name
Test status
Simulation time 73045192 ps
CPU time 0.81 seconds
Started Jul 03 05:15:21 PM PDT 24
Finished Jul 03 05:15:22 PM PDT 24
Peak memory 205116 kb
Host smart-9a7d0633-3957-4744-95f9-77b5f9fafed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753679865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1753679865
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3791396309
Short name T201
Test name
Test status
Simulation time 2764168201 ps
CPU time 6.55 seconds
Started Jul 03 05:15:06 PM PDT 24
Finished Jul 03 05:15:13 PM PDT 24
Peak memory 205500 kb
Host smart-db3ea50f-315d-4b66-9eaa-cb6cd891c058
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3791396309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3791396309
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2731248152
Short name T48
Test name
Test status
Simulation time 2178141439 ps
CPU time 6.17 seconds
Started Jul 03 05:15:21 PM PDT 24
Finished Jul 03 05:15:28 PM PDT 24
Peak memory 205112 kb
Host smart-e39c6dfa-2aba-423f-97e2-76ec0b5cd539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731248152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2731248152
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.562594144
Short name T12
Test name
Test status
Simulation time 214475112 ps
CPU time 0.84 seconds
Started Jul 03 05:15:13 PM PDT 24
Finished Jul 03 05:15:14 PM PDT 24
Peak memory 205032 kb
Host smart-2b980b1d-1c0e-41ff-8af1-16584ddf6f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562594144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.562594144
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2488244422
Short name T228
Test name
Test status
Simulation time 533411139 ps
CPU time 2.24 seconds
Started Jul 03 05:15:23 PM PDT 24
Finished Jul 03 05:15:25 PM PDT 24
Peak memory 205072 kb
Host smart-6d9c8162-73ae-4b12-b877-ed41bbd55f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488244422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2488244422
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3659618868
Short name T245
Test name
Test status
Simulation time 2072165184 ps
CPU time 3.62 seconds
Started Jul 03 05:15:20 PM PDT 24
Finished Jul 03 05:15:24 PM PDT 24
Peak memory 205004 kb
Host smart-4ff53122-e5ce-4f13-9ec4-bbefd1336375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659618868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3659618868
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.110211579
Short name T221
Test name
Test status
Simulation time 1261088718 ps
CPU time 3.92 seconds
Started Jul 03 05:15:21 PM PDT 24
Finished Jul 03 05:15:25 PM PDT 24
Peak memory 205080 kb
Host smart-e70af193-2a52-4357-9afa-ecb621cca854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110211579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.110211579
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3462150973
Short name T211
Test name
Test status
Simulation time 222700658 ps
CPU time 0.84 seconds
Started Jul 03 05:15:20 PM PDT 24
Finished Jul 03 05:15:21 PM PDT 24
Peak memory 205088 kb
Host smart-353d29d3-36f2-48cd-9069-b5722a7220ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462150973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3462150973
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.480283470
Short name T235
Test name
Test status
Simulation time 1047393698 ps
CPU time 2.23 seconds
Started Jul 03 05:15:20 PM PDT 24
Finished Jul 03 05:15:23 PM PDT 24
Peak memory 205088 kb
Host smart-9fbeaa5a-f0e4-4770-a734-70f1062e9bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480283470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.480283470
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.442096818
Short name T178
Test name
Test status
Simulation time 4960522394 ps
CPU time 7.79 seconds
Started Jul 03 05:15:21 PM PDT 24
Finished Jul 03 05:15:29 PM PDT 24
Peak memory 205364 kb
Host smart-0930f25c-f9d0-4e3f-b45a-5cdb984e1f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442096818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.442096818
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1559224427
Short name T24
Test name
Test status
Simulation time 414727194 ps
CPU time 1.83 seconds
Started Jul 03 05:15:21 PM PDT 24
Finished Jul 03 05:15:24 PM PDT 24
Peak memory 205052 kb
Host smart-218b1e69-10d6-4bae-b9fe-fc34bb4ec9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559224427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1559224427
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1200364998
Short name T44
Test name
Test status
Simulation time 74531800 ps
CPU time 0.91 seconds
Started Jul 03 05:15:21 PM PDT 24
Finished Jul 03 05:15:22 PM PDT 24
Peak memory 213372 kb
Host smart-aaf3f734-e966-48b3-baa9-4d8f2611607d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200364998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1200364998
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.154455705
Short name T75
Test name
Test status
Simulation time 5160666741 ps
CPU time 4.86 seconds
Started Jul 03 05:15:10 PM PDT 24
Finished Jul 03 05:15:15 PM PDT 24
Peak memory 213688 kb
Host smart-209ede51-c949-4791-bbb5-4d6aeae9d7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154455705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.154455705
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3388419749
Short name T57
Test name
Test status
Simulation time 1639188102 ps
CPU time 1.69 seconds
Started Jul 03 05:15:23 PM PDT 24
Finished Jul 03 05:15:25 PM PDT 24
Peak memory 229480 kb
Host smart-57062344-466f-45e0-b7e5-ec37a22483c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388419749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3388419749
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.398761891
Short name T272
Test name
Test status
Simulation time 393943678 ps
CPU time 1.27 seconds
Started Jul 03 05:15:08 PM PDT 24
Finished Jul 03 05:15:09 PM PDT 24
Peak memory 205096 kb
Host smart-2a61b016-0084-4ee5-b667-324d6b814b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398761891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.398761891
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3696250920
Short name T213
Test name
Test status
Simulation time 155473345 ps
CPU time 0.76 seconds
Started Jul 03 05:16:02 PM PDT 24
Finished Jul 03 05:16:03 PM PDT 24
Peak memory 205080 kb
Host smart-8b1ac6d3-5cb8-4078-afe0-a285e39f6369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696250920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3696250920
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.626162589
Short name T31
Test name
Test status
Simulation time 24199038075 ps
CPU time 16.82 seconds
Started Jul 03 05:16:03 PM PDT 24
Finished Jul 03 05:16:20 PM PDT 24
Peak memory 213080 kb
Host smart-9d474d99-73d3-4ea5-a003-fc4890398030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626162589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.626162589
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.564605708
Short name T210
Test name
Test status
Simulation time 1971334164 ps
CPU time 6.59 seconds
Started Jul 03 05:16:02 PM PDT 24
Finished Jul 03 05:16:09 PM PDT 24
Peak memory 205364 kb
Host smart-1d21f543-1ac4-4388-b355-78ea48651336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564605708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.564605708
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1437070768
Short name T188
Test name
Test status
Simulation time 2163307003 ps
CPU time 3.1 seconds
Started Jul 03 05:16:01 PM PDT 24
Finished Jul 03 05:16:05 PM PDT 24
Peak memory 213688 kb
Host smart-72d68700-d30f-4b91-9b78-a101fda050fc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1437070768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1437070768
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3912541467
Short name T249
Test name
Test status
Simulation time 1691411606 ps
CPU time 3.56 seconds
Started Jul 03 05:16:01 PM PDT 24
Finished Jul 03 05:16:05 PM PDT 24
Peak memory 205360 kb
Host smart-b62d62e4-9579-4c57-9e6b-004f5510c1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912541467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3912541467
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.3544886794
Short name T137
Test name
Test status
Simulation time 4078934895 ps
CPU time 5.87 seconds
Started Jul 03 05:16:01 PM PDT 24
Finished Jul 03 05:16:07 PM PDT 24
Peak memory 213564 kb
Host smart-c97f4b76-e4a8-4809-8ec9-a32129348852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544886794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3544886794
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1690316550
Short name T230
Test name
Test status
Simulation time 59634767656 ps
CPU time 24.51 seconds
Started Jul 03 05:16:02 PM PDT 24
Finished Jul 03 05:16:27 PM PDT 24
Peak memory 213688 kb
Host smart-e5deccb9-63e7-4905-b328-450780a73ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690316550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1690316550
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.3744291562
Short name T32
Test name
Test status
Simulation time 5196215107 ps
CPU time 8.07 seconds
Started Jul 03 05:16:02 PM PDT 24
Finished Jul 03 05:16:10 PM PDT 24
Peak memory 205376 kb
Host smart-a5fac4a5-e8af-497c-9355-d15cbe409815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744291562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.3744291562
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3986462474
Short name T187
Test name
Test status
Simulation time 3356526777 ps
CPU time 5.54 seconds
Started Jul 03 05:16:01 PM PDT 24
Finished Jul 03 05:16:07 PM PDT 24
Peak memory 205436 kb
Host smart-ee2bf27d-4642-496c-b6aa-b04c590cab22
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986462474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3986462474
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2252958702
Short name T273
Test name
Test status
Simulation time 87021689 ps
CPU time 0.68 seconds
Started Jul 03 05:16:06 PM PDT 24
Finished Jul 03 05:16:07 PM PDT 24
Peak memory 205108 kb
Host smart-aef33f5f-3284-4f82-9d35-4d52c7e019c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252958702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2252958702
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1178419404
Short name T259
Test name
Test status
Simulation time 2421102353 ps
CPU time 4.18 seconds
Started Jul 03 05:16:05 PM PDT 24
Finished Jul 03 05:16:10 PM PDT 24
Peak memory 205380 kb
Host smart-3c462c8c-166f-4dfb-a1b7-647912e65ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178419404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1178419404
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1198660100
Short name T251
Test name
Test status
Simulation time 8539423850 ps
CPU time 7.33 seconds
Started Jul 03 05:16:04 PM PDT 24
Finished Jul 03 05:16:11 PM PDT 24
Peak memory 205460 kb
Host smart-f09f0d73-ef73-494d-b8c5-e54cd5ae0100
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1198660100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1198660100
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.1120586970
Short name T237
Test name
Test status
Simulation time 3646411971 ps
CPU time 9.59 seconds
Started Jul 03 05:16:02 PM PDT 24
Finished Jul 03 05:16:12 PM PDT 24
Peak memory 205348 kb
Host smart-9fa7e7d0-9f64-451c-8490-b36da1194aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120586970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1120586970
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.1829711181
Short name T49
Test name
Test status
Simulation time 8366502940 ps
CPU time 7.02 seconds
Started Jul 03 05:16:08 PM PDT 24
Finished Jul 03 05:16:15 PM PDT 24
Peak memory 213508 kb
Host smart-600ae8e1-0ed9-4a06-8842-0d5c336c986b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829711181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1829711181
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.771213796
Short name T182
Test name
Test status
Simulation time 137938200 ps
CPU time 0.78 seconds
Started Jul 03 05:16:04 PM PDT 24
Finished Jul 03 05:16:05 PM PDT 24
Peak memory 205132 kb
Host smart-f52760c7-75bc-46c5-b01f-344b40442811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771213796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.771213796
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1177180825
Short name T71
Test name
Test status
Simulation time 8118994661 ps
CPU time 7.81 seconds
Started Jul 03 05:16:03 PM PDT 24
Finished Jul 03 05:16:11 PM PDT 24
Peak memory 205432 kb
Host smart-f2c38680-247b-4a78-b701-9b5a7807a7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177180825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1177180825
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2555619276
Short name T276
Test name
Test status
Simulation time 1220285024 ps
CPU time 2.65 seconds
Started Jul 03 05:16:05 PM PDT 24
Finished Jul 03 05:16:08 PM PDT 24
Peak memory 205292 kb
Host smart-9c596270-460b-4e14-9630-81171b761152
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2555619276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2555619276
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2913645571
Short name T266
Test name
Test status
Simulation time 48352491 ps
CPU time 0.7 seconds
Started Jul 03 05:16:10 PM PDT 24
Finished Jul 03 05:16:11 PM PDT 24
Peak memory 205080 kb
Host smart-f582aa20-1363-4237-b96a-e608136bc767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913645571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2913645571
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3748593412
Short name T257
Test name
Test status
Simulation time 5341551427 ps
CPU time 7.6 seconds
Started Jul 03 05:16:07 PM PDT 24
Finished Jul 03 05:16:15 PM PDT 24
Peak memory 205412 kb
Host smart-bfea782a-6897-4e63-a645-2663fe9169d7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748593412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3748593412
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.469331106
Short name T270
Test name
Test status
Simulation time 2622316127 ps
CPU time 2.96 seconds
Started Jul 03 05:16:06 PM PDT 24
Finished Jul 03 05:16:10 PM PDT 24
Peak memory 213560 kb
Host smart-8c08c1e4-a304-4d50-ab3e-f3be81498050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469331106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.469331106
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.415111160
Short name T186
Test name
Test status
Simulation time 98651087 ps
CPU time 0.73 seconds
Started Jul 03 05:16:10 PM PDT 24
Finished Jul 03 05:16:11 PM PDT 24
Peak memory 205076 kb
Host smart-c75eafb2-76be-4186-920a-8e1705ec9f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415111160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.415111160
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2318707734
Short name T261
Test name
Test status
Simulation time 2864458672 ps
CPU time 3.76 seconds
Started Jul 03 05:16:08 PM PDT 24
Finished Jul 03 05:16:12 PM PDT 24
Peak memory 213580 kb
Host smart-3f1e248b-999c-4c1e-a2fb-66ed806d28a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318707734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2318707734
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3470254178
Short name T227
Test name
Test status
Simulation time 3495661718 ps
CPU time 2.44 seconds
Started Jul 03 05:16:11 PM PDT 24
Finished Jul 03 05:16:14 PM PDT 24
Peak memory 205328 kb
Host smart-f7a33fbb-3aaf-4e36-8a94-afac1f0c671e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470254178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3470254178
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.314249377
Short name T264
Test name
Test status
Simulation time 1246052083 ps
CPU time 1.89 seconds
Started Jul 03 05:16:14 PM PDT 24
Finished Jul 03 05:16:16 PM PDT 24
Peak memory 205364 kb
Host smart-b7339c02-04ff-4d33-92c3-084b5b6ac889
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=314249377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.314249377
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.873820509
Short name T269
Test name
Test status
Simulation time 4685414606 ps
CPU time 7.65 seconds
Started Jul 03 05:16:11 PM PDT 24
Finished Jul 03 05:16:19 PM PDT 24
Peak memory 205460 kb
Host smart-7da26936-321a-4f5b-a446-dee51d06993a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873820509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.873820509
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.3845093586
Short name T18
Test name
Test status
Simulation time 5424821184 ps
CPU time 5.08 seconds
Started Jul 03 05:16:08 PM PDT 24
Finished Jul 03 05:16:13 PM PDT 24
Peak memory 213536 kb
Host smart-f136ad8e-26f1-4aa4-915f-bd3f3560e2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845093586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3845093586
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2330155743
Short name T72
Test name
Test status
Simulation time 60231083 ps
CPU time 0.88 seconds
Started Jul 03 05:16:13 PM PDT 24
Finished Jul 03 05:16:14 PM PDT 24
Peak memory 205096 kb
Host smart-362d8248-7bdf-4fc7-adc1-248c0370b560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330155743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2330155743
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2824497322
Short name T79
Test name
Test status
Simulation time 119171922732 ps
CPU time 185.64 seconds
Started Jul 03 05:16:09 PM PDT 24
Finished Jul 03 05:19:14 PM PDT 24
Peak memory 219748 kb
Host smart-1c11a343-2f50-48d3-9759-fd278a52a4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824497322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2824497322
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1927350622
Short name T83
Test name
Test status
Simulation time 1183430709 ps
CPU time 4.58 seconds
Started Jul 03 05:16:11 PM PDT 24
Finished Jul 03 05:16:16 PM PDT 24
Peak memory 205336 kb
Host smart-fecbb08b-e992-4922-bb15-6bc0c9ff6477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927350622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1927350622
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3564482265
Short name T208
Test name
Test status
Simulation time 62042857 ps
CPU time 0.84 seconds
Started Jul 03 05:16:15 PM PDT 24
Finished Jul 03 05:16:16 PM PDT 24
Peak memory 205072 kb
Host smart-9f22433a-8c5f-4c5a-9415-92eb4d30e241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564482265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3564482265
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3751545365
Short name T254
Test name
Test status
Simulation time 76188411420 ps
CPU time 55.49 seconds
Started Jul 03 05:16:13 PM PDT 24
Finished Jul 03 05:17:09 PM PDT 24
Peak memory 217064 kb
Host smart-4264c46e-dcc7-4525-8b05-7832897051fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751545365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3751545365
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.335981291
Short name T265
Test name
Test status
Simulation time 3505862385 ps
CPU time 10.35 seconds
Started Jul 03 05:16:08 PM PDT 24
Finished Jul 03 05:16:18 PM PDT 24
Peak memory 213512 kb
Host smart-d54defa5-5528-4cbd-bfec-54005ffd8beb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335981291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.335981291
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.2910911840
Short name T192
Test name
Test status
Simulation time 7127023325 ps
CPU time 4.1 seconds
Started Jul 03 05:16:10 PM PDT 24
Finished Jul 03 05:16:14 PM PDT 24
Peak memory 205404 kb
Host smart-0e029196-756e-4bf4-a1b8-6c5eb5640ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910911840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2910911840
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.3299389130
Short name T190
Test name
Test status
Simulation time 147649854 ps
CPU time 0.84 seconds
Started Jul 03 05:16:12 PM PDT 24
Finished Jul 03 05:16:13 PM PDT 24
Peak memory 205072 kb
Host smart-587f5fcd-d96b-4eea-953a-5aadb4bd367b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299389130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.3299389130
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3471347672
Short name T278
Test name
Test status
Simulation time 3146668673 ps
CPU time 8.99 seconds
Started Jul 03 05:16:14 PM PDT 24
Finished Jul 03 05:16:23 PM PDT 24
Peak memory 213616 kb
Host smart-80863546-6cde-4e49-96ca-d4f5d1923af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471347672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3471347672
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3551995827
Short name T241
Test name
Test status
Simulation time 1267646389 ps
CPU time 1.67 seconds
Started Jul 03 05:16:14 PM PDT 24
Finished Jul 03 05:16:16 PM PDT 24
Peak memory 205376 kb
Host smart-4df4e160-0fee-4c32-b946-db129c763b90
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3551995827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.3551995827
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1061720505
Short name T244
Test name
Test status
Simulation time 9292479431 ps
CPU time 20.3 seconds
Started Jul 03 05:16:15 PM PDT 24
Finished Jul 03 05:16:36 PM PDT 24
Peak memory 213660 kb
Host smart-19b76ed8-2ddc-4bd8-be80-ac656f6a9fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061720505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1061720505
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.204155055
Short name T226
Test name
Test status
Simulation time 95303757 ps
CPU time 0.98 seconds
Started Jul 03 05:16:21 PM PDT 24
Finished Jul 03 05:16:22 PM PDT 24
Peak memory 205044 kb
Host smart-40a9195b-243b-4e3b-9921-4c06976de72c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204155055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.204155055
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3804277540
Short name T255
Test name
Test status
Simulation time 4920293028 ps
CPU time 4.57 seconds
Started Jul 03 05:16:16 PM PDT 24
Finished Jul 03 05:16:21 PM PDT 24
Peak memory 205384 kb
Host smart-ba941d6c-07e8-48bb-ac1f-ced6e0838668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804277540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3804277540
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2166085274
Short name T220
Test name
Test status
Simulation time 3515588725 ps
CPU time 2.81 seconds
Started Jul 03 05:16:13 PM PDT 24
Finished Jul 03 05:16:16 PM PDT 24
Peak memory 205472 kb
Host smart-26e4e2fd-c4d9-4da7-ba3a-aeed3bd91564
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2166085274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.2166085274
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2187642895
Short name T250
Test name
Test status
Simulation time 3341845156 ps
CPU time 3.42 seconds
Started Jul 03 05:16:15 PM PDT 24
Finished Jul 03 05:16:19 PM PDT 24
Peak memory 205444 kb
Host smart-1edb7f2c-8ad5-46fe-abd1-769f0ef74e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187642895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2187642895
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.168159519
Short name T275
Test name
Test status
Simulation time 53819084 ps
CPU time 0.8 seconds
Started Jul 03 05:15:28 PM PDT 24
Finished Jul 03 05:15:29 PM PDT 24
Peak memory 205108 kb
Host smart-fd081609-e606-43c4-9e6a-a551b436d5e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168159519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.168159519
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.703482994
Short name T271
Test name
Test status
Simulation time 30251988608 ps
CPU time 13.2 seconds
Started Jul 03 05:15:31 PM PDT 24
Finished Jul 03 05:15:45 PM PDT 24
Peak memory 213664 kb
Host smart-65d81786-4f53-427a-9076-69d90e34f556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703482994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.703482994
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.358968057
Short name T66
Test name
Test status
Simulation time 640397680 ps
CPU time 1.32 seconds
Started Jul 03 05:15:31 PM PDT 24
Finished Jul 03 05:15:32 PM PDT 24
Peak memory 205388 kb
Host smart-ad76dbd5-32e4-43e3-be1a-7b40451102fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358968057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.358968057
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2612246775
Short name T162
Test name
Test status
Simulation time 2131676578 ps
CPU time 4.01 seconds
Started Jul 03 05:15:26 PM PDT 24
Finished Jul 03 05:15:30 PM PDT 24
Peak memory 213612 kb
Host smart-d8f1f6d2-2301-491d-9f90-8a5f23e4a3b4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612246775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2612246775
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.747483463
Short name T252
Test name
Test status
Simulation time 178341349 ps
CPU time 0.71 seconds
Started Jul 03 05:15:26 PM PDT 24
Finished Jul 03 05:15:27 PM PDT 24
Peak memory 205000 kb
Host smart-7b3b5285-d760-480c-bd13-db7bdbe228a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747483463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.747483463
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1596436562
Short name T239
Test name
Test status
Simulation time 1009670705 ps
CPU time 3.61 seconds
Started Jul 03 05:15:24 PM PDT 24
Finished Jul 03 05:15:28 PM PDT 24
Peak memory 205308 kb
Host smart-82f157ce-acd6-445d-be98-c7db647c5c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596436562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1596436562
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2812165563
Short name T74
Test name
Test status
Simulation time 265583550 ps
CPU time 1.22 seconds
Started Jul 03 05:15:26 PM PDT 24
Finished Jul 03 05:15:28 PM PDT 24
Peak memory 229588 kb
Host smart-43e0f194-5efa-40ea-9874-6a136247cbe1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812165563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2812165563
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.2566229649
Short name T140
Test name
Test status
Simulation time 1556070033 ps
CPU time 4.32 seconds
Started Jul 03 05:15:31 PM PDT 24
Finished Jul 03 05:15:35 PM PDT 24
Peak memory 205288 kb
Host smart-3325ccdd-8aef-41a8-8c45-ae040c172683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566229649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2566229649
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.748608470
Short name T193
Test name
Test status
Simulation time 35904985 ps
CPU time 0.78 seconds
Started Jul 03 05:16:19 PM PDT 24
Finished Jul 03 05:16:20 PM PDT 24
Peak memory 205048 kb
Host smart-988ccb05-bcd8-4f40-8b60-880a3795a5ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748608470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.748608470
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.736592850
Short name T78
Test name
Test status
Simulation time 3127875671 ps
CPU time 2.81 seconds
Started Jul 03 05:16:16 PM PDT 24
Finished Jul 03 05:16:19 PM PDT 24
Peak memory 205364 kb
Host smart-4664b7b3-a863-4296-bf68-748539af23a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736592850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.736592850
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3368518889
Short name T68
Test name
Test status
Simulation time 27720842 ps
CPU time 0.73 seconds
Started Jul 03 05:16:21 PM PDT 24
Finished Jul 03 05:16:22 PM PDT 24
Peak memory 205128 kb
Host smart-9ee380b2-7be7-4449-bec0-d4adb704b156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368518889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3368518889
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3003396256
Short name T205
Test name
Test status
Simulation time 242484937 ps
CPU time 0.8 seconds
Started Jul 03 05:16:19 PM PDT 24
Finished Jul 03 05:16:20 PM PDT 24
Peak memory 205044 kb
Host smart-b7abf187-1959-48cf-9743-179e43518d83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003396256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3003396256
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2996423223
Short name T209
Test name
Test status
Simulation time 196629634 ps
CPU time 0.71 seconds
Started Jul 03 05:16:18 PM PDT 24
Finished Jul 03 05:16:19 PM PDT 24
Peak memory 205080 kb
Host smart-39d40499-5920-4f46-b676-fff7c3f60ef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996423223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2996423223
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.757407978
Short name T136
Test name
Test status
Simulation time 6753777671 ps
CPU time 19.08 seconds
Started Jul 03 05:16:21 PM PDT 24
Finished Jul 03 05:16:40 PM PDT 24
Peak memory 205340 kb
Host smart-5876435f-4862-4ce8-8455-3742245e8c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757407978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.757407978
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1206693092
Short name T3
Test name
Test status
Simulation time 94633684 ps
CPU time 0.75 seconds
Started Jul 03 05:16:18 PM PDT 24
Finished Jul 03 05:16:19 PM PDT 24
Peak memory 205052 kb
Host smart-c77959c2-c2da-4ab1-bbc6-39d2cf969d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206693092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1206693092
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.223252793
Short name T262
Test name
Test status
Simulation time 37280597 ps
CPU time 0.72 seconds
Started Jul 03 05:16:17 PM PDT 24
Finished Jul 03 05:16:18 PM PDT 24
Peak memory 205092 kb
Host smart-11d11988-25d5-43cc-b7b3-7586bcbdcf7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223252793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.223252793
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.544502002
Short name T206
Test name
Test status
Simulation time 53795249 ps
CPU time 0.71 seconds
Started Jul 03 05:16:18 PM PDT 24
Finished Jul 03 05:16:19 PM PDT 24
Peak memory 205084 kb
Host smart-cba41061-3c82-4328-853d-4a356c6c69b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544502002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.544502002
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1777557954
Short name T2
Test name
Test status
Simulation time 136592741 ps
CPU time 0.85 seconds
Started Jul 03 05:16:20 PM PDT 24
Finished Jul 03 05:16:21 PM PDT 24
Peak memory 205100 kb
Host smart-09dcdf2d-1498-44dd-9660-04dcb024db25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777557954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1777557954
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.4168757473
Short name T52
Test name
Test status
Simulation time 5102221392 ps
CPU time 3.87 seconds
Started Jul 03 05:16:20 PM PDT 24
Finished Jul 03 05:16:24 PM PDT 24
Peak memory 213508 kb
Host smart-686f61b0-4ee8-4797-8567-91492bf01259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168757473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.4168757473
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.4273932208
Short name T80
Test name
Test status
Simulation time 149016757 ps
CPU time 0.77 seconds
Started Jul 03 05:16:17 PM PDT 24
Finished Jul 03 05:16:18 PM PDT 24
Peak memory 205036 kb
Host smart-f470a32d-32d1-4d5f-a4ae-d659be7b5b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273932208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4273932208
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.45698155
Short name T197
Test name
Test status
Simulation time 64712819 ps
CPU time 0.74 seconds
Started Jul 03 05:16:21 PM PDT 24
Finished Jul 03 05:16:22 PM PDT 24
Peak memory 205080 kb
Host smart-b38eff5a-10e5-4b8e-b6e3-78c3a65494d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45698155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.45698155
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.3744165904
Short name T33
Test name
Test status
Simulation time 3470535292 ps
CPU time 10.18 seconds
Started Jul 03 05:16:17 PM PDT 24
Finished Jul 03 05:16:28 PM PDT 24
Peak memory 205404 kb
Host smart-53a346a9-d7b6-4981-bb1f-05b3235c9205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744165904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3744165904
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3004428326
Short name T238
Test name
Test status
Simulation time 133202889 ps
CPU time 1 seconds
Started Jul 03 05:15:35 PM PDT 24
Finished Jul 03 05:15:36 PM PDT 24
Peak memory 205140 kb
Host smart-a87b5e94-9a73-4a65-af48-4400ebc6b6d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004428326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3004428326
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.914792648
Short name T246
Test name
Test status
Simulation time 8170071625 ps
CPU time 7.45 seconds
Started Jul 03 05:15:28 PM PDT 24
Finished Jul 03 05:15:35 PM PDT 24
Peak memory 215620 kb
Host smart-81d57c72-b5f0-4e57-ba52-bb6ed89b91f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914792648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.914792648
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2326107276
Short name T242
Test name
Test status
Simulation time 6450487518 ps
CPU time 9.91 seconds
Started Jul 03 05:15:32 PM PDT 24
Finished Jul 03 05:15:42 PM PDT 24
Peak memory 213560 kb
Host smart-1d55fd96-18b9-41e1-9f45-b985f9a47abc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2326107276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2326107276
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.104207208
Short name T81
Test name
Test status
Simulation time 72292967 ps
CPU time 0.74 seconds
Started Jul 03 05:15:35 PM PDT 24
Finished Jul 03 05:15:36 PM PDT 24
Peak memory 205064 kb
Host smart-2146542b-4d1d-4e0c-ac20-5dec489e87c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104207208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.104207208
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2098707767
Short name T222
Test name
Test status
Simulation time 2862476466 ps
CPU time 3.76 seconds
Started Jul 03 05:15:31 PM PDT 24
Finished Jul 03 05:15:35 PM PDT 24
Peak memory 213612 kb
Host smart-97fcd262-1770-48c6-a00f-ba93d0c680c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098707767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2098707767
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.160378694
Short name T34
Test name
Test status
Simulation time 4559628363 ps
CPU time 4.85 seconds
Started Jul 03 05:15:32 PM PDT 24
Finished Jul 03 05:15:37 PM PDT 24
Peak memory 205428 kb
Host smart-83a8b4b5-dd76-4994-b026-74db8d360c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160378694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.160378694
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2410276308
Short name T191
Test name
Test status
Simulation time 67290474 ps
CPU time 0.72 seconds
Started Jul 03 05:16:20 PM PDT 24
Finished Jul 03 05:16:21 PM PDT 24
Peak memory 205036 kb
Host smart-c7f03a1c-60f1-4b4c-ae46-6ab19263800b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410276308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2410276308
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3381559079
Short name T70
Test name
Test status
Simulation time 7121290680 ps
CPU time 8.56 seconds
Started Jul 03 05:16:22 PM PDT 24
Finished Jul 03 05:16:31 PM PDT 24
Peak memory 205428 kb
Host smart-ff749139-00ca-48e1-ae8f-b42060bb9e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381559079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3381559079
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1360698998
Short name T217
Test name
Test status
Simulation time 148418486 ps
CPU time 0.84 seconds
Started Jul 03 05:16:21 PM PDT 24
Finished Jul 03 05:16:22 PM PDT 24
Peak memory 205036 kb
Host smart-4e9254ac-9d50-4370-a259-e0f7245debc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360698998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1360698998
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.3179305690
Short name T177
Test name
Test status
Simulation time 5165121164 ps
CPU time 4.61 seconds
Started Jul 03 05:16:21 PM PDT 24
Finished Jul 03 05:16:27 PM PDT 24
Peak memory 205244 kb
Host smart-d306eee7-2ccf-4bcf-a6cc-e433fadde510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179305690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3179305690
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2978533998
Short name T232
Test name
Test status
Simulation time 81293443 ps
CPU time 0.76 seconds
Started Jul 03 05:16:22 PM PDT 24
Finished Jul 03 05:16:23 PM PDT 24
Peak memory 205040 kb
Host smart-86b44add-5bd3-4044-91ca-bb8d5a33661e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978533998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2978533998
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.2662760891
Short name T16
Test name
Test status
Simulation time 4748268596 ps
CPU time 4.29 seconds
Started Jul 03 05:16:25 PM PDT 24
Finished Jul 03 05:16:29 PM PDT 24
Peak memory 213576 kb
Host smart-6b53c2bd-a24c-4bcc-b650-37d4a1a84aef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662760891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.2662760891
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.373490622
Short name T215
Test name
Test status
Simulation time 29128853 ps
CPU time 0.78 seconds
Started Jul 03 05:16:22 PM PDT 24
Finished Jul 03 05:16:23 PM PDT 24
Peak memory 205080 kb
Host smart-f93876a4-91ed-4f6f-9fec-6fa2cb2fda82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373490622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.373490622
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1400769720
Short name T198
Test name
Test status
Simulation time 72896838 ps
CPU time 0.69 seconds
Started Jul 03 05:16:21 PM PDT 24
Finished Jul 03 05:16:22 PM PDT 24
Peak memory 205124 kb
Host smart-777d489e-6108-4140-9b52-c972ede116df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400769720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1400769720
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1311631967
Short name T263
Test name
Test status
Simulation time 105254537 ps
CPU time 0.72 seconds
Started Jul 03 05:16:26 PM PDT 24
Finished Jul 03 05:16:27 PM PDT 24
Peak memory 205100 kb
Host smart-f18e5bcb-c97a-4c90-aa1f-c51d5fc5571f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311631967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1311631967
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1196436566
Short name T234
Test name
Test status
Simulation time 144625904 ps
CPU time 0.84 seconds
Started Jul 03 05:16:25 PM PDT 24
Finished Jul 03 05:16:27 PM PDT 24
Peak memory 205068 kb
Host smart-86633f66-c12f-4a0c-bafc-e2d0c3f3b5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196436566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1196436566
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3267875074
Short name T69
Test name
Test status
Simulation time 33495660 ps
CPU time 0.71 seconds
Started Jul 03 05:16:26 PM PDT 24
Finished Jul 03 05:16:27 PM PDT 24
Peak memory 205128 kb
Host smart-2243a169-4f03-45b2-b83f-7d1e73d99e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267875074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3267875074
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.1866888517
Short name T141
Test name
Test status
Simulation time 6403437877 ps
CPU time 18.31 seconds
Started Jul 03 05:16:25 PM PDT 24
Finished Jul 03 05:16:44 PM PDT 24
Peak memory 205276 kb
Host smart-4000ea00-8e2b-4225-8560-8be3c9ed08d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866888517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1866888517
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3293435829
Short name T183
Test name
Test status
Simulation time 65753249 ps
CPU time 0.69 seconds
Started Jul 03 05:16:23 PM PDT 24
Finished Jul 03 05:16:24 PM PDT 24
Peak memory 205128 kb
Host smart-d4a5c4cc-0890-4388-901d-2918a2155004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293435829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3293435829
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1147435426
Short name T180
Test name
Test status
Simulation time 131086569 ps
CPU time 1 seconds
Started Jul 03 05:16:24 PM PDT 24
Finished Jul 03 05:16:26 PM PDT 24
Peak memory 205124 kb
Host smart-eccdf33e-4afd-41d6-a9b8-0a3d196499b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147435426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1147435426
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2715355703
Short name T200
Test name
Test status
Simulation time 102843606 ps
CPU time 0.96 seconds
Started Jul 03 05:15:40 PM PDT 24
Finished Jul 03 05:15:41 PM PDT 24
Peak memory 205128 kb
Host smart-bab2152e-19e6-4d64-a13f-02fed0ac12b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715355703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2715355703
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.574088760
Short name T225
Test name
Test status
Simulation time 40021299023 ps
CPU time 91.35 seconds
Started Jul 03 05:15:37 PM PDT 24
Finished Jul 03 05:17:09 PM PDT 24
Peak memory 213616 kb
Host smart-710f756f-0b5e-4b30-88d4-f08a1265281e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574088760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.574088760
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.619496883
Short name T189
Test name
Test status
Simulation time 14080413059 ps
CPU time 6.37 seconds
Started Jul 03 05:15:38 PM PDT 24
Finished Jul 03 05:15:45 PM PDT 24
Peak memory 213648 kb
Host smart-dc14daa6-dcb4-4e3a-9b8e-8468ce0848d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619496883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.619496883
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3895002726
Short name T233
Test name
Test status
Simulation time 5928388016 ps
CPU time 9.18 seconds
Started Jul 03 05:15:40 PM PDT 24
Finished Jul 03 05:15:49 PM PDT 24
Peak memory 214756 kb
Host smart-87e0bdd8-2f02-43b2-9cb0-5da899ca5c93
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3895002726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3895002726
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2369018189
Short name T256
Test name
Test status
Simulation time 1062713978 ps
CPU time 1.9 seconds
Started Jul 03 05:15:40 PM PDT 24
Finished Jul 03 05:15:42 PM PDT 24
Peak memory 205024 kb
Host smart-ebf76214-4b76-4b88-aa9e-dfe8a59fb036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369018189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2369018189
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3654066063
Short name T260
Test name
Test status
Simulation time 2152397129 ps
CPU time 6.64 seconds
Started Jul 03 05:15:39 PM PDT 24
Finished Jul 03 05:15:46 PM PDT 24
Peak memory 205400 kb
Host smart-d36bd3b4-457e-4955-b085-6441a2692b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654066063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3654066063
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3212231174
Short name T58
Test name
Test status
Simulation time 260593022 ps
CPU time 1.27 seconds
Started Jul 03 05:15:39 PM PDT 24
Finished Jul 03 05:15:40 PM PDT 24
Peak memory 229616 kb
Host smart-8586592a-3883-48f8-8e52-d41069a67dce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212231174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3212231174
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.2744115510
Short name T134
Test name
Test status
Simulation time 6865038733 ps
CPU time 10.41 seconds
Started Jul 03 05:15:39 PM PDT 24
Finished Jul 03 05:15:50 PM PDT 24
Peak memory 213548 kb
Host smart-438b400a-1239-4fde-b699-bbd6b642329c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744115510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.2744115510
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.959910368
Short name T185
Test name
Test status
Simulation time 33306593 ps
CPU time 0.8 seconds
Started Jul 03 05:16:26 PM PDT 24
Finished Jul 03 05:16:28 PM PDT 24
Peak memory 205104 kb
Host smart-cec555b8-7d2f-4b3c-81b2-1c3d760fd74e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959910368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.959910368
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1647648475
Short name T216
Test name
Test status
Simulation time 59532924 ps
CPU time 0.83 seconds
Started Jul 03 05:16:25 PM PDT 24
Finished Jul 03 05:16:26 PM PDT 24
Peak memory 205028 kb
Host smart-aeafadd0-d4d1-49fe-b135-a28006b38a95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647648475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1647648475
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3679379352
Short name T203
Test name
Test status
Simulation time 112834165 ps
CPU time 0.75 seconds
Started Jul 03 05:16:29 PM PDT 24
Finished Jul 03 05:16:30 PM PDT 24
Peak memory 205100 kb
Host smart-0fc84b97-a5b8-45ac-be67-89eb3708edb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679379352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3679379352
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.3680611904
Short name T214
Test name
Test status
Simulation time 57822520 ps
CPU time 0.68 seconds
Started Jul 03 05:16:35 PM PDT 24
Finished Jul 03 05:16:36 PM PDT 24
Peak memory 205076 kb
Host smart-a035e9ab-6b2b-4cbf-a249-da9cc5c13988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680611904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.3680611904
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1523281031
Short name T194
Test name
Test status
Simulation time 133943602 ps
CPU time 0.99 seconds
Started Jul 03 05:16:32 PM PDT 24
Finished Jul 03 05:16:33 PM PDT 24
Peak memory 205108 kb
Host smart-50277209-47e2-40d9-84ee-e20ec83d735d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523281031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1523281031
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.4254269343
Short name T28
Test name
Test status
Simulation time 3715623681 ps
CPU time 3.74 seconds
Started Jul 03 05:16:30 PM PDT 24
Finished Jul 03 05:16:34 PM PDT 24
Peak memory 205368 kb
Host smart-2cce4862-802f-4ee1-817c-180754b9484c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254269343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.4254269343
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.552534903
Short name T277
Test name
Test status
Simulation time 126565998 ps
CPU time 0.82 seconds
Started Jul 03 05:16:29 PM PDT 24
Finished Jul 03 05:16:30 PM PDT 24
Peak memory 205088 kb
Host smart-a1286d69-3a64-456f-a793-163759096f4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552534903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.552534903
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.2797246737
Short name T36
Test name
Test status
Simulation time 10255890258 ps
CPU time 11.09 seconds
Started Jul 03 05:16:29 PM PDT 24
Finished Jul 03 05:16:41 PM PDT 24
Peak memory 213504 kb
Host smart-19a3535b-1878-41cd-a651-ca8101c458bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797246737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.2797246737
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.1773068077
Short name T204
Test name
Test status
Simulation time 94107767 ps
CPU time 0.76 seconds
Started Jul 03 05:16:30 PM PDT 24
Finished Jul 03 05:16:31 PM PDT 24
Peak memory 205104 kb
Host smart-614934c6-dfce-46a3-a799-02f97fff2747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773068077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.1773068077
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2898446043
Short name T1
Test name
Test status
Simulation time 46897278 ps
CPU time 0.82 seconds
Started Jul 03 05:16:29 PM PDT 24
Finished Jul 03 05:16:31 PM PDT 24
Peak memory 205128 kb
Host smart-be1073b9-e8df-46ee-a70d-d48bfc7dae15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898446043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2898446043
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1053521489
Short name T76
Test name
Test status
Simulation time 103132412 ps
CPU time 0.73 seconds
Started Jul 03 05:16:38 PM PDT 24
Finished Jul 03 05:16:39 PM PDT 24
Peak memory 205076 kb
Host smart-b5ce3c3c-5ff0-4980-8bcf-d7a0823101c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053521489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1053521489
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.1529967455
Short name T19
Test name
Test status
Simulation time 11668397938 ps
CPU time 9.97 seconds
Started Jul 03 05:16:36 PM PDT 24
Finished Jul 03 05:16:46 PM PDT 24
Peak memory 213460 kb
Host smart-40757875-dfc4-49f1-9f54-57bd49e19b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529967455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1529967455
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2636928535
Short name T82
Test name
Test status
Simulation time 95675096 ps
CPU time 0.9 seconds
Started Jul 03 05:16:35 PM PDT 24
Finished Jul 03 05:16:36 PM PDT 24
Peak memory 205136 kb
Host smart-87cbbde4-e5db-48f5-8059-a4e6418737aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636928535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2636928535
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.120249763
Short name T195
Test name
Test status
Simulation time 56953764 ps
CPU time 0.69 seconds
Started Jul 03 05:15:45 PM PDT 24
Finished Jul 03 05:15:46 PM PDT 24
Peak memory 205116 kb
Host smart-db488c72-be66-4c2a-8d85-082678a5bbf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120249763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.120249763
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2361575352
Short name T219
Test name
Test status
Simulation time 6260038146 ps
CPU time 17.74 seconds
Started Jul 03 05:15:43 PM PDT 24
Finished Jul 03 05:16:01 PM PDT 24
Peak memory 213572 kb
Host smart-97b733bf-a7bb-4d47-b71b-262edb2d19c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361575352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2361575352
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2149815394
Short name T20
Test name
Test status
Simulation time 1650598779 ps
CPU time 6.04 seconds
Started Jul 03 05:15:40 PM PDT 24
Finished Jul 03 05:15:47 PM PDT 24
Peak memory 205252 kb
Host smart-793d1615-3db0-4bc4-9b73-b491450679be
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2149815394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2149815394
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3686325662
Short name T236
Test name
Test status
Simulation time 6001136295 ps
CPU time 6.18 seconds
Started Jul 03 05:15:42 PM PDT 24
Finished Jul 03 05:15:49 PM PDT 24
Peak memory 205400 kb
Host smart-cb30320d-0f2d-4413-90e9-98d5c040a71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686325662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3686325662
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.2518863935
Short name T135
Test name
Test status
Simulation time 3511558140 ps
CPU time 3.53 seconds
Started Jul 03 05:15:41 PM PDT 24
Finished Jul 03 05:15:45 PM PDT 24
Peak memory 205336 kb
Host smart-66401d81-7855-4b7b-a3ea-a622bcdccf8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518863935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2518863935
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3002737393
Short name T202
Test name
Test status
Simulation time 50350529 ps
CPU time 0.75 seconds
Started Jul 03 05:15:50 PM PDT 24
Finished Jul 03 05:15:51 PM PDT 24
Peak memory 205104 kb
Host smart-c63dbd9b-2548-4968-b1b6-57379b965fcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002737393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3002737393
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2739995098
Short name T274
Test name
Test status
Simulation time 9304821373 ps
CPU time 6.48 seconds
Started Jul 03 05:15:49 PM PDT 24
Finished Jul 03 05:15:56 PM PDT 24
Peak memory 215884 kb
Host smart-f9120a3d-bcdb-46e8-a9d7-0be18dabe837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739995098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2739995098
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.646091074
Short name T281
Test name
Test status
Simulation time 1229000007 ps
CPU time 4.02 seconds
Started Jul 03 05:15:46 PM PDT 24
Finished Jul 03 05:15:50 PM PDT 24
Peak memory 213480 kb
Host smart-91e37e4f-784d-46ce-8288-5ccccf2ead40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646091074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.646091074
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1166746642
Short name T240
Test name
Test status
Simulation time 4253254468 ps
CPU time 3.02 seconds
Started Jul 03 05:15:44 PM PDT 24
Finished Jul 03 05:15:47 PM PDT 24
Peak memory 205408 kb
Host smart-bdc95977-7331-4013-9e6e-7f299dd0510f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1166746642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1166746642
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3913802562
Short name T253
Test name
Test status
Simulation time 1969818226 ps
CPU time 3.84 seconds
Started Jul 03 05:15:47 PM PDT 24
Finished Jul 03 05:15:51 PM PDT 24
Peak memory 213588 kb
Host smart-06df2528-2bd1-41b7-b230-f10b24ad739c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913802562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3913802562
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.334523690
Short name T224
Test name
Test status
Simulation time 53093067 ps
CPU time 0.8 seconds
Started Jul 03 05:16:01 PM PDT 24
Finished Jul 03 05:16:02 PM PDT 24
Peak memory 205096 kb
Host smart-53948e63-30c0-4ca0-8461-d3a89c5f4d9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334523690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.334523690
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1631930477
Short name T38
Test name
Test status
Simulation time 92306336872 ps
CPU time 91.17 seconds
Started Jul 03 05:15:54 PM PDT 24
Finished Jul 03 05:17:26 PM PDT 24
Peak memory 217432 kb
Host smart-22abeb4b-2ffb-4f7b-aa53-9e157cd4fa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631930477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1631930477
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2532075782
Short name T223
Test name
Test status
Simulation time 4485117941 ps
CPU time 12.15 seconds
Started Jul 03 05:15:50 PM PDT 24
Finished Jul 03 05:16:03 PM PDT 24
Peak memory 213592 kb
Host smart-21b76297-6a27-4a46-aa0b-910b153365bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532075782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2532075782
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1086991427
Short name T163
Test name
Test status
Simulation time 7743951252 ps
CPU time 5.7 seconds
Started Jul 03 05:15:48 PM PDT 24
Finished Jul 03 05:15:54 PM PDT 24
Peak memory 221768 kb
Host smart-45c9b873-fd2b-48a6-8058-32a4480e6f23
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086991427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1086991427
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1992301474
Short name T84
Test name
Test status
Simulation time 4719178969 ps
CPU time 4.03 seconds
Started Jul 03 05:15:51 PM PDT 24
Finished Jul 03 05:15:56 PM PDT 24
Peak memory 213536 kb
Host smart-adb9cf0f-67f3-4989-a2a3-c734da8d9e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992301474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1992301474
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1792397315
Short name T77
Test name
Test status
Simulation time 95044540 ps
CPU time 0.73 seconds
Started Jul 03 05:16:00 PM PDT 24
Finished Jul 03 05:16:01 PM PDT 24
Peak memory 205104 kb
Host smart-9a488256-3466-44cb-9ab0-fee407b66055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792397315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1792397315
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2593180282
Short name T258
Test name
Test status
Simulation time 1845308543 ps
CPU time 4.24 seconds
Started Jul 03 05:15:59 PM PDT 24
Finished Jul 03 05:16:03 PM PDT 24
Peak memory 213540 kb
Host smart-e57d779e-aa04-4f25-9310-4436c0a53326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593180282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2593180282
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1599070102
Short name T207
Test name
Test status
Simulation time 3035629909 ps
CPU time 1.71 seconds
Started Jul 03 05:15:59 PM PDT 24
Finished Jul 03 05:16:01 PM PDT 24
Peak memory 221892 kb
Host smart-883fa102-73ff-4bd0-bae7-7866a29794f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599070102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1599070102
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2664302929
Short name T229
Test name
Test status
Simulation time 4163550543 ps
CPU time 6.99 seconds
Started Jul 03 05:15:56 PM PDT 24
Finished Jul 03 05:16:03 PM PDT 24
Peak memory 205340 kb
Host smart-29743d6f-4a92-4e55-ae80-2798efb961db
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2664302929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2664302929
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3701940676
Short name T268
Test name
Test status
Simulation time 2510572189 ps
CPU time 4.63 seconds
Started Jul 03 05:16:01 PM PDT 24
Finished Jul 03 05:16:06 PM PDT 24
Peak memory 205492 kb
Host smart-b660fee3-aa21-4f97-a2ef-3ebb34fd7835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701940676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3701940676
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3996855130
Short name T184
Test name
Test status
Simulation time 122733930 ps
CPU time 0.69 seconds
Started Jul 03 05:15:59 PM PDT 24
Finished Jul 03 05:16:00 PM PDT 24
Peak memory 205104 kb
Host smart-a276d948-0a3b-4713-a966-ab4cb23cdb01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996855130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3996855130
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3558674068
Short name T157
Test name
Test status
Simulation time 3793899741 ps
CPU time 10.24 seconds
Started Jul 03 05:15:59 PM PDT 24
Finished Jul 03 05:16:10 PM PDT 24
Peak memory 213684 kb
Host smart-93e68ad0-cc9f-48a0-ba34-3b5c9dac171f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558674068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3558674068
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.713544747
Short name T149
Test name
Test status
Simulation time 5039472430 ps
CPU time 10.85 seconds
Started Jul 03 05:16:01 PM PDT 24
Finished Jul 03 05:16:12 PM PDT 24
Peak memory 213580 kb
Host smart-a966d2a9-be93-42a0-a0ac-811b36c229d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713544747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.713544747
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.428623256
Short name T243
Test name
Test status
Simulation time 11853518321 ps
CPU time 32.76 seconds
Started Jul 03 05:15:56 PM PDT 24
Finished Jul 03 05:16:30 PM PDT 24
Peak memory 213520 kb
Host smart-4932f2fa-ca8d-4369-8f1e-cddaa59b7476
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428623256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.428623256
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1034812047
Short name T212
Test name
Test status
Simulation time 5457226999 ps
CPU time 8.56 seconds
Started Jul 03 05:15:58 PM PDT 24
Finished Jul 03 05:16:07 PM PDT 24
Peak memory 213524 kb
Host smart-242a8b4c-ae4e-4fc6-bf6a-3ba8070a38d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034812047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1034812047
Directory /workspace/9.rv_dm_sba_tl_access/latest
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