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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.28 95.27 79.59 89.42 74.36 85.50 98.42 53.40


Total test records in report: 429
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T118 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3354385193 Jul 04 05:11:46 PM PDT 24 Jul 04 05:11:48 PM PDT 24 57421698 ps
T112 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1313439750 Jul 04 05:12:17 PM PDT 24 Jul 04 05:12:24 PM PDT 24 3210031540 ps
T181 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3676561038 Jul 04 05:11:52 PM PDT 24 Jul 04 05:12:14 PM PDT 24 4821046787 ps
T288 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1722785010 Jul 04 05:11:45 PM PDT 24 Jul 04 05:12:13 PM PDT 24 816522685 ps
T191 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3514843043 Jul 04 05:11:56 PM PDT 24 Jul 04 05:12:19 PM PDT 24 8020247299 ps
T289 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2057592872 Jul 04 05:12:02 PM PDT 24 Jul 04 05:12:04 PM PDT 24 585778644 ps
T290 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4059455309 Jul 04 05:11:45 PM PDT 24 Jul 04 05:11:46 PM PDT 24 73503237 ps
T291 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.338138380 Jul 04 05:11:52 PM PDT 24 Jul 04 05:11:57 PM PDT 24 3181484379 ps
T292 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2019666953 Jul 04 05:11:46 PM PDT 24 Jul 04 05:11:55 PM PDT 24 4949278483 ps
T293 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2581819707 Jul 04 05:12:17 PM PDT 24 Jul 04 05:12:19 PM PDT 24 1789687140 ps
T140 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3186932659 Jul 04 05:11:57 PM PDT 24 Jul 04 05:12:02 PM PDT 24 2927229208 ps
T294 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.797169500 Jul 04 05:11:36 PM PDT 24 Jul 04 05:11:40 PM PDT 24 2423580335 ps
T295 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3638082817 Jul 04 05:11:44 PM PDT 24 Jul 04 05:11:45 PM PDT 24 208817053 ps
T296 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2253104254 Jul 04 05:11:44 PM PDT 24 Jul 04 05:11:45 PM PDT 24 91274450 ps
T119 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.347509141 Jul 04 05:11:54 PM PDT 24 Jul 04 05:11:56 PM PDT 24 93754009 ps
T297 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1628499858 Jul 04 05:12:00 PM PDT 24 Jul 04 05:12:04 PM PDT 24 5109107562 ps
T298 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2023223031 Jul 04 05:12:18 PM PDT 24 Jul 04 05:12:20 PM PDT 24 1101814915 ps
T299 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2104639544 Jul 04 05:12:19 PM PDT 24 Jul 04 05:12:23 PM PDT 24 153843866 ps
T120 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1723661042 Jul 04 05:12:18 PM PDT 24 Jul 04 05:12:21 PM PDT 24 220054752 ps
T141 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3119296313 Jul 04 05:11:45 PM PDT 24 Jul 04 05:11:50 PM PDT 24 802093831 ps
T121 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1869868387 Jul 04 05:12:06 PM PDT 24 Jul 04 05:12:11 PM PDT 24 263040432 ps
T300 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1925964441 Jul 04 05:11:46 PM PDT 24 Jul 04 05:12:22 PM PDT 24 7785467955 ps
T189 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.753634275 Jul 04 05:12:06 PM PDT 24 Jul 04 05:12:17 PM PDT 24 3796093686 ps
T301 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1216842546 Jul 04 05:11:52 PM PDT 24 Jul 04 05:11:56 PM PDT 24 194024447 ps
T133 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.4005113991 Jul 04 05:12:17 PM PDT 24 Jul 04 05:12:21 PM PDT 24 815480569 ps
T134 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1551157055 Jul 04 05:12:12 PM PDT 24 Jul 04 05:12:19 PM PDT 24 438466058 ps
T302 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3443964462 Jul 04 05:11:38 PM PDT 24 Jul 04 05:11:48 PM PDT 24 23747407413 ps
T303 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1662016345 Jul 04 05:12:15 PM PDT 24 Jul 04 05:12:17 PM PDT 24 60655308 ps
T304 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1980077101 Jul 04 05:12:00 PM PDT 24 Jul 04 05:12:39 PM PDT 24 27528014025 ps
T305 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1211198858 Jul 04 05:12:01 PM PDT 24 Jul 04 05:12:05 PM PDT 24 2255326807 ps
T306 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2279387565 Jul 04 05:11:46 PM PDT 24 Jul 04 05:11:51 PM PDT 24 1873351733 ps
T307 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3930210178 Jul 04 05:12:07 PM PDT 24 Jul 04 05:12:09 PM PDT 24 128171809 ps
T135 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4028167151 Jul 04 05:12:01 PM PDT 24 Jul 04 05:12:05 PM PDT 24 1895701257 ps
T127 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4019593813 Jul 04 05:11:36 PM PDT 24 Jul 04 05:12:45 PM PDT 24 14554200076 ps
T308 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3480330256 Jul 04 05:11:51 PM PDT 24 Jul 04 05:11:53 PM PDT 24 412292775 ps
T309 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.130514911 Jul 04 05:11:52 PM PDT 24 Jul 04 05:13:34 PM PDT 24 40539348197 ps
T129 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2913356819 Jul 04 05:12:18 PM PDT 24 Jul 04 05:12:21 PM PDT 24 117951390 ps
T310 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.610668760 Jul 04 05:11:58 PM PDT 24 Jul 04 05:12:01 PM PDT 24 1577548369 ps
T311 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2855575128 Jul 04 05:11:45 PM PDT 24 Jul 04 05:11:50 PM PDT 24 2428559413 ps
T182 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2230102687 Jul 04 05:12:01 PM PDT 24 Jul 04 05:12:23 PM PDT 24 1726582420 ps
T312 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1964659678 Jul 04 05:11:52 PM PDT 24 Jul 04 05:12:15 PM PDT 24 24233745832 ps
T313 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3696890090 Jul 04 05:12:02 PM PDT 24 Jul 04 05:12:09 PM PDT 24 2799330244 ps
T183 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3285154872 Jul 04 05:11:36 PM PDT 24 Jul 04 05:11:53 PM PDT 24 5343264250 ps
T180 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3032165590 Jul 04 05:11:36 PM PDT 24 Jul 04 05:13:24 PM PDT 24 70479763786 ps
T314 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2331397147 Jul 04 05:11:36 PM PDT 24 Jul 04 05:11:38 PM PDT 24 554994461 ps
T315 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2023467115 Jul 04 05:12:06 PM PDT 24 Jul 04 05:12:09 PM PDT 24 291074737 ps
T122 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.919779752 Jul 04 05:11:45 PM PDT 24 Jul 04 05:11:53 PM PDT 24 270289254 ps
T316 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2664955173 Jul 04 05:12:02 PM PDT 24 Jul 04 05:12:18 PM PDT 24 5761422692 ps
T317 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1669411558 Jul 04 05:12:00 PM PDT 24 Jul 04 05:12:04 PM PDT 24 1077753339 ps
T318 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.64470702 Jul 04 05:11:46 PM PDT 24 Jul 04 05:12:47 PM PDT 24 15643457698 ps
T319 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4257949292 Jul 04 05:12:17 PM PDT 24 Jul 04 05:12:20 PM PDT 24 92821726 ps
T320 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1635579203 Jul 04 05:12:17 PM PDT 24 Jul 04 05:12:20 PM PDT 24 1993823231 ps
T321 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.169725410 Jul 04 05:11:38 PM PDT 24 Jul 04 05:11:51 PM PDT 24 2892323275 ps
T322 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.157300862 Jul 04 05:12:17 PM PDT 24 Jul 04 05:12:26 PM PDT 24 9701536631 ps
T136 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.648064265 Jul 04 05:12:19 PM PDT 24 Jul 04 05:12:23 PM PDT 24 227872717 ps
T323 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3043682987 Jul 04 05:11:36 PM PDT 24 Jul 04 05:11:38 PM PDT 24 53029189 ps
T114 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2912021155 Jul 04 05:11:37 PM PDT 24 Jul 04 05:11:46 PM PDT 24 9029213738 ps
T137 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3976226359 Jul 04 05:12:06 PM PDT 24 Jul 04 05:12:14 PM PDT 24 979606577 ps
T324 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2679398843 Jul 04 05:12:02 PM PDT 24 Jul 04 05:12:08 PM PDT 24 1677511289 ps
T325 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2062964923 Jul 04 05:11:35 PM PDT 24 Jul 04 05:11:37 PM PDT 24 415328455 ps
T123 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1181958788 Jul 04 05:11:54 PM PDT 24 Jul 04 05:12:02 PM PDT 24 513736276 ps
T326 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1350904112 Jul 04 05:12:02 PM PDT 24 Jul 04 05:12:03 PM PDT 24 131832095 ps
T327 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.204853151 Jul 04 05:11:36 PM PDT 24 Jul 04 05:11:37 PM PDT 24 164508550 ps
T328 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1362755743 Jul 04 05:11:58 PM PDT 24 Jul 04 05:12:00 PM PDT 24 1983264971 ps
T329 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2852353123 Jul 04 05:11:45 PM PDT 24 Jul 04 05:12:02 PM PDT 24 35136130952 ps
T330 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2019549974 Jul 04 05:12:17 PM PDT 24 Jul 04 05:12:46 PM PDT 24 23847181861 ps
T331 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2589433536 Jul 04 05:12:03 PM PDT 24 Jul 04 05:12:05 PM PDT 24 54690830 ps
T332 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4131799818 Jul 04 05:11:52 PM PDT 24 Jul 04 05:13:01 PM PDT 24 5145095238 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1751978672 Jul 04 05:11:37 PM PDT 24 Jul 04 05:11:39 PM PDT 24 318525512 ps
T334 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4267572899 Jul 04 05:11:45 PM PDT 24 Jul 04 05:12:21 PM PDT 24 9982370316 ps
T335 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1361365656 Jul 04 05:12:01 PM PDT 24 Jul 04 05:12:05 PM PDT 24 1482054293 ps
T336 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.323465503 Jul 04 05:12:01 PM PDT 24 Jul 04 05:12:07 PM PDT 24 1020841384 ps
T337 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3989286699 Jul 04 05:11:44 PM PDT 24 Jul 04 05:11:46 PM PDT 24 103123725 ps
T338 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1118648481 Jul 04 05:11:36 PM PDT 24 Jul 04 05:11:43 PM PDT 24 1648338827 ps
T339 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2256720806 Jul 04 05:12:16 PM PDT 24 Jul 04 05:12:18 PM PDT 24 121401181 ps
T340 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2536747826 Jul 04 05:12:14 PM PDT 24 Jul 04 05:12:16 PM PDT 24 397258709 ps
T341 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.650141190 Jul 04 05:11:36 PM PDT 24 Jul 04 05:11:37 PM PDT 24 257813496 ps
T185 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3299708462 Jul 04 05:12:17 PM PDT 24 Jul 04 05:12:27 PM PDT 24 1579348492 ps
T342 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.400386133 Jul 04 05:12:11 PM PDT 24 Jul 04 05:12:13 PM PDT 24 160172464 ps
T343 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3212417862 Jul 04 05:11:46 PM PDT 24 Jul 04 05:15:08 PM PDT 24 84362277888 ps
T344 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2955278738 Jul 04 05:12:00 PM PDT 24 Jul 04 05:12:26 PM PDT 24 60080031819 ps
T124 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3721257194 Jul 04 05:11:43 PM PDT 24 Jul 04 05:12:17 PM PDT 24 7433413996 ps
T345 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2550629836 Jul 04 05:12:16 PM PDT 24 Jul 04 05:12:21 PM PDT 24 2353006794 ps
T346 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2127791569 Jul 04 05:11:36 PM PDT 24 Jul 04 05:14:49 PM PDT 24 70701827440 ps
T125 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2696920435 Jul 04 05:12:15 PM PDT 24 Jul 04 05:12:19 PM PDT 24 761432921 ps
T347 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.919805072 Jul 04 05:11:36 PM PDT 24 Jul 04 05:11:38 PM PDT 24 1052593601 ps
T348 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2078331383 Jul 04 05:11:37 PM PDT 24 Jul 04 05:13:12 PM PDT 24 33211361220 ps
T349 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.851247939 Jul 04 05:11:39 PM PDT 24 Jul 04 05:12:15 PM PDT 24 10315886955 ps
T190 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3372741698 Jul 04 05:12:16 PM PDT 24 Jul 04 05:12:29 PM PDT 24 1633334020 ps
T350 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1789319381 Jul 04 05:12:09 PM PDT 24 Jul 04 05:12:12 PM PDT 24 1018485603 ps
T351 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1125117658 Jul 04 05:11:54 PM PDT 24 Jul 04 05:11:56 PM PDT 24 202202826 ps
T352 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.270062646 Jul 04 05:11:47 PM PDT 24 Jul 04 05:11:48 PM PDT 24 267331586 ps
T353 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2999743509 Jul 04 05:11:39 PM PDT 24 Jul 04 05:11:42 PM PDT 24 2415820362 ps
T187 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1102131914 Jul 04 05:12:05 PM PDT 24 Jul 04 05:12:18 PM PDT 24 3251087639 ps
T354 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.927953611 Jul 04 05:11:51 PM PDT 24 Jul 04 05:12:58 PM PDT 24 23456454414 ps
T186 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4176546332 Jul 04 05:11:43 PM PDT 24 Jul 04 05:12:11 PM PDT 24 5137373888 ps
T355 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1983199398 Jul 04 05:12:07 PM PDT 24 Jul 04 05:12:09 PM PDT 24 178957843 ps
T356 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.782346632 Jul 04 05:12:17 PM PDT 24 Jul 04 05:12:21 PM PDT 24 2352602815 ps
T357 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.362978547 Jul 04 05:11:58 PM PDT 24 Jul 04 05:12:02 PM PDT 24 555769036 ps
T358 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.477035689 Jul 04 05:12:17 PM PDT 24 Jul 04 05:12:21 PM PDT 24 1508707678 ps
T359 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2267267777 Jul 04 05:12:04 PM PDT 24 Jul 04 05:12:10 PM PDT 24 554253372 ps
T360 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1922500939 Jul 04 05:12:18 PM PDT 24 Jul 04 05:12:30 PM PDT 24 3894095692 ps
T361 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4129039499 Jul 04 05:12:01 PM PDT 24 Jul 04 05:12:03 PM PDT 24 154242330 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.973199404 Jul 04 05:11:38 PM PDT 24 Jul 04 05:11:39 PM PDT 24 72815494 ps
T130 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3980756914 Jul 04 05:12:02 PM PDT 24 Jul 04 05:12:04 PM PDT 24 67475964 ps
T363 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2898385762 Jul 04 05:11:45 PM PDT 24 Jul 04 05:11:52 PM PDT 24 740222070 ps
T364 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3466486594 Jul 04 05:11:42 PM PDT 24 Jul 04 05:11:45 PM PDT 24 153909643 ps
T365 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2028754605 Jul 04 05:11:44 PM PDT 24 Jul 04 05:11:45 PM PDT 24 89650258 ps
T188 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3159099349 Jul 04 05:12:15 PM PDT 24 Jul 04 05:12:35 PM PDT 24 2829263907 ps
T366 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4129870651 Jul 04 05:12:02 PM PDT 24 Jul 04 05:12:05 PM PDT 24 225858898 ps
T367 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1119816985 Jul 04 05:11:57 PM PDT 24 Jul 04 05:11:59 PM PDT 24 171336540 ps
T126 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4001236369 Jul 04 05:12:00 PM PDT 24 Jul 04 05:12:05 PM PDT 24 936533433 ps
T368 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3707481502 Jul 04 05:12:16 PM PDT 24 Jul 04 05:12:17 PM PDT 24 507668138 ps
T369 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3627603831 Jul 04 05:12:02 PM PDT 24 Jul 04 05:12:10 PM PDT 24 1415850152 ps
T370 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.305103733 Jul 04 05:11:56 PM PDT 24 Jul 04 05:11:57 PM PDT 24 36732377 ps
T371 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1125019400 Jul 04 05:11:52 PM PDT 24 Jul 04 05:11:58 PM PDT 24 1247627201 ps
T115 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.695096470 Jul 04 05:11:42 PM PDT 24 Jul 04 05:11:49 PM PDT 24 3286163216 ps
T372 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2760330426 Jul 04 05:11:58 PM PDT 24 Jul 04 05:11:59 PM PDT 24 322093973 ps
T373 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1623418404 Jul 04 05:11:53 PM PDT 24 Jul 04 05:12:00 PM PDT 24 236992951 ps
T374 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.676735957 Jul 04 05:12:01 PM PDT 24 Jul 04 05:12:07 PM PDT 24 2480424025 ps
T375 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2823513955 Jul 04 05:12:03 PM PDT 24 Jul 04 05:12:06 PM PDT 24 3062444897 ps
T128 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.373797119 Jul 04 05:11:53 PM PDT 24 Jul 04 05:11:56 PM PDT 24 263400183 ps
T376 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3592953735 Jul 04 05:11:45 PM PDT 24 Jul 04 05:11:47 PM PDT 24 394381350 ps
T377 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.594530632 Jul 04 05:12:18 PM PDT 24 Jul 04 05:12:20 PM PDT 24 936302807 ps
T378 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2701681199 Jul 04 05:11:52 PM PDT 24 Jul 04 05:11:58 PM PDT 24 171706310 ps
T379 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.102202725 Jul 04 05:12:19 PM PDT 24 Jul 04 05:12:21 PM PDT 24 142259790 ps
T380 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1447023699 Jul 04 05:12:01 PM PDT 24 Jul 04 05:12:02 PM PDT 24 501208329 ps
T381 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2385623684 Jul 04 05:11:49 PM PDT 24 Jul 04 05:11:51 PM PDT 24 368848945 ps
T382 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.957674862 Jul 04 05:12:07 PM PDT 24 Jul 04 05:12:12 PM PDT 24 265942298 ps
T383 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3146844389 Jul 04 05:11:37 PM PDT 24 Jul 04 05:11:38 PM PDT 24 610650207 ps
T384 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1785533380 Jul 04 05:12:16 PM PDT 24 Jul 04 05:12:20 PM PDT 24 643694287 ps
T385 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2924227198 Jul 04 05:12:15 PM PDT 24 Jul 04 05:12:19 PM PDT 24 156597441 ps
T386 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1199569528 Jul 04 05:12:07 PM PDT 24 Jul 04 05:12:13 PM PDT 24 7673072597 ps
T387 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.998557577 Jul 04 05:11:47 PM PDT 24 Jul 04 05:11:49 PM PDT 24 143628540 ps
T388 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.4125375399 Jul 04 05:12:16 PM PDT 24 Jul 04 05:12:28 PM PDT 24 15961713057 ps
T389 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1952562704 Jul 04 05:11:36 PM PDT 24 Jul 04 05:11:37 PM PDT 24 505706172 ps
T184 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3536434035 Jul 04 05:12:08 PM PDT 24 Jul 04 05:12:27 PM PDT 24 5854286193 ps
T390 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.99474758 Jul 04 05:11:36 PM PDT 24 Jul 04 05:11:42 PM PDT 24 520305742 ps
T391 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.194527417 Jul 04 05:11:45 PM PDT 24 Jul 04 05:12:08 PM PDT 24 2292270090 ps
T392 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.733927958 Jul 04 05:12:02 PM PDT 24 Jul 04 05:12:21 PM PDT 24 1924029336 ps
T393 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2938917433 Jul 04 05:12:11 PM PDT 24 Jul 04 05:12:17 PM PDT 24 3641181791 ps
T394 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.235285495 Jul 04 05:11:37 PM PDT 24 Jul 04 05:11:47 PM PDT 24 3654570283 ps
T395 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3825341820 Jul 04 05:12:08 PM PDT 24 Jul 04 05:12:12 PM PDT 24 2307891007 ps
T396 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.870759016 Jul 04 05:11:42 PM PDT 24 Jul 04 05:11:43 PM PDT 24 83194123 ps
T397 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.259078485 Jul 04 05:11:56 PM PDT 24 Jul 04 05:12:19 PM PDT 24 3109803485 ps
T398 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1892654884 Jul 04 05:12:08 PM PDT 24 Jul 04 05:12:09 PM PDT 24 141493911 ps
T399 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1285355377 Jul 04 05:11:56 PM PDT 24 Jul 04 05:12:07 PM PDT 24 6856284690 ps
T400 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2578627665 Jul 04 05:12:08 PM PDT 24 Jul 04 05:12:10 PM PDT 24 128268072 ps
T401 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1293593905 Jul 04 05:11:36 PM PDT 24 Jul 04 05:11:37 PM PDT 24 67239477 ps
T402 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.651792543 Jul 04 05:11:53 PM PDT 24 Jul 04 05:12:18 PM PDT 24 47858900360 ps
T403 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.451724769 Jul 04 05:12:09 PM PDT 24 Jul 04 05:12:59 PM PDT 24 18286951288 ps
T404 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1184596918 Jul 04 05:12:07 PM PDT 24 Jul 04 05:12:10 PM PDT 24 1528444732 ps
T405 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1265978734 Jul 04 05:12:01 PM PDT 24 Jul 04 05:12:03 PM PDT 24 179739307 ps
T131 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1606174465 Jul 04 05:11:39 PM PDT 24 Jul 04 05:12:07 PM PDT 24 636928402 ps
T406 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1458281340 Jul 04 05:11:54 PM PDT 24 Jul 04 05:11:57 PM PDT 24 261066574 ps
T407 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.985664350 Jul 04 05:12:12 PM PDT 24 Jul 04 05:12:15 PM PDT 24 2863283662 ps
T408 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.941596180 Jul 04 05:12:05 PM PDT 24 Jul 04 05:12:07 PM PDT 24 398253683 ps
T409 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2861873134 Jul 04 05:11:52 PM PDT 24 Jul 04 05:11:56 PM PDT 24 415136803 ps
T132 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1527055275 Jul 04 05:12:20 PM PDT 24 Jul 04 05:12:22 PM PDT 24 121997394 ps
T410 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.275059478 Jul 04 05:12:18 PM PDT 24 Jul 04 05:12:22 PM PDT 24 490589128 ps
T411 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3837320628 Jul 04 05:11:43 PM PDT 24 Jul 04 05:11:50 PM PDT 24 703366840 ps
T412 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2322085860 Jul 04 05:12:02 PM PDT 24 Jul 04 05:12:28 PM PDT 24 23771020334 ps
T413 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1176808402 Jul 04 05:12:15 PM PDT 24 Jul 04 05:12:19 PM PDT 24 205877845 ps
T414 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1934995199 Jul 04 05:11:51 PM PDT 24 Jul 04 05:11:53 PM PDT 24 828164029 ps
T415 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2656541933 Jul 04 05:12:16 PM PDT 24 Jul 04 05:12:20 PM PDT 24 970849374 ps
T416 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.808572180 Jul 04 05:11:46 PM PDT 24 Jul 04 05:11:47 PM PDT 24 96618434 ps
T417 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3559268041 Jul 04 05:11:42 PM PDT 24 Jul 04 05:14:05 PM PDT 24 56565192836 ps
T418 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.478731108 Jul 04 05:12:15 PM PDT 24 Jul 04 05:13:02 PM PDT 24 34898860499 ps
T419 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3258601929 Jul 04 05:11:47 PM PDT 24 Jul 04 05:11:53 PM PDT 24 782814330 ps
T420 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.377619001 Jul 04 05:12:09 PM PDT 24 Jul 04 05:12:31 PM PDT 24 5076407293 ps
T421 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.749044530 Jul 04 05:12:07 PM PDT 24 Jul 04 05:12:08 PM PDT 24 270466251 ps
T422 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.875347975 Jul 04 05:12:04 PM PDT 24 Jul 04 05:12:50 PM PDT 24 16864474855 ps
T423 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.567169442 Jul 04 05:12:02 PM PDT 24 Jul 04 05:12:12 PM PDT 24 6215222104 ps
T424 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1681563270 Jul 04 05:11:53 PM PDT 24 Jul 04 05:11:54 PM PDT 24 233500399 ps
T425 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2765255146 Jul 04 05:12:10 PM PDT 24 Jul 04 05:12:13 PM PDT 24 152056772 ps
T426 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3788318035 Jul 04 05:12:02 PM PDT 24 Jul 04 05:12:08 PM PDT 24 4760128557 ps
T427 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3303257552 Jul 04 05:12:17 PM PDT 24 Jul 04 05:14:08 PM PDT 24 43037487285 ps
T428 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3819250261 Jul 04 05:12:18 PM PDT 24 Jul 04 05:12:46 PM PDT 24 4505614319 ps
T429 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.272745153 Jul 04 05:11:47 PM PDT 24 Jul 04 05:12:19 PM PDT 24 40689842870 ps

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2602828532
Short name T26
Test name
Test status
Simulation time 9025871633 ps
CPU time 7.58 seconds
Started Jul 04 05:13:05 PM PDT 24
Finished Jul 04 05:13:13 PM PDT 24
Peak memory 213548 kb
Host smart-d241395b-bfa2-4db0-beed-31f86316c9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602828532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2602828532
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.4062466483
Short name T5
Test name
Test status
Simulation time 8665595904 ps
CPU time 12.97 seconds
Started Jul 04 05:14:34 PM PDT 24
Finished Jul 04 05:14:48 PM PDT 24
Peak memory 213544 kb
Host smart-2ddfda28-b529-4582-bf73-9809e964ae8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062466483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.4062466483
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3622296006
Short name T49
Test name
Test status
Simulation time 31088941860 ps
CPU time 90.21 seconds
Started Jul 04 05:11:56 PM PDT 24
Finished Jul 04 05:13:27 PM PDT 24
Peak memory 221636 kb
Host smart-8380928f-8b24-45d7-acaa-49259ad061ce
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622296006 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3622296006
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3234173441
Short name T16
Test name
Test status
Simulation time 4010560714 ps
CPU time 11.24 seconds
Started Jul 04 05:14:17 PM PDT 24
Finished Jul 04 05:14:29 PM PDT 24
Peak memory 205164 kb
Host smart-27311bd2-6097-4d10-9d3e-3c71fb28f2d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234173441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3234173441
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.185807673
Short name T242
Test name
Test status
Simulation time 57872633126 ps
CPU time 49.15 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:14:39 PM PDT 24
Peak memory 213596 kb
Host smart-4657d6bb-5dcf-4901-9799-5ddf95f332d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185807673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.185807673
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.2826639070
Short name T4
Test name
Test status
Simulation time 5579591282 ps
CPU time 9.07 seconds
Started Jul 04 05:14:28 PM PDT 24
Finished Jul 04 05:14:37 PM PDT 24
Peak memory 205304 kb
Host smart-d61396d0-9e4b-4be5-bf7f-97d3ae1bcb4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826639070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2826639070
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1856866881
Short name T63
Test name
Test status
Simulation time 2330814241 ps
CPU time 9.95 seconds
Started Jul 04 05:12:09 PM PDT 24
Finished Jul 04 05:12:19 PM PDT 24
Peak memory 213392 kb
Host smart-5a190fdf-a48a-49fe-be47-48b01082e23f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856866881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
856866881
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1288629104
Short name T110
Test name
Test status
Simulation time 167613160 ps
CPU time 0.77 seconds
Started Jul 04 05:14:25 PM PDT 24
Finished Jul 04 05:14:26 PM PDT 24
Peak memory 205020 kb
Host smart-5139bfc2-637c-4d7d-9424-50723c9f8623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288629104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1288629104
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.458116768
Short name T8
Test name
Test status
Simulation time 125322582 ps
CPU time 0.85 seconds
Started Jul 04 05:13:08 PM PDT 24
Finished Jul 04 05:13:10 PM PDT 24
Peak memory 215728 kb
Host smart-c70d8fa4-060f-4e99-9e35-ca59ba8f6914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458116768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.458116768
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2990432991
Short name T88
Test name
Test status
Simulation time 3969340933 ps
CPU time 4.81 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:52 PM PDT 24
Peak memory 213576 kb
Host smart-b89f2bb6-1715-469c-b30b-a934470e5fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990432991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2990432991
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.850077745
Short name T43
Test name
Test status
Simulation time 2127814152 ps
CPU time 2.39 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:12:54 PM PDT 24
Peak memory 204924 kb
Host smart-105ec834-3840-472e-a9a8-7993471a3ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850077745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.850077745
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2306088963
Short name T81
Test name
Test status
Simulation time 3136167923 ps
CPU time 8.33 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:15 PM PDT 24
Peak memory 205264 kb
Host smart-aa43660b-efab-4bd8-b28e-6e41a4189328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306088963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2306088963
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.128118287
Short name T66
Test name
Test status
Simulation time 360674365 ps
CPU time 2.8 seconds
Started Jul 04 05:11:45 PM PDT 24
Finished Jul 04 05:11:48 PM PDT 24
Peak memory 213456 kb
Host smart-8e59fec2-94a2-48a2-a41c-6f31b12b406d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128118287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.128118287
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.1056388800
Short name T24
Test name
Test status
Simulation time 2106577964 ps
CPU time 5.67 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:58 PM PDT 24
Peak memory 213500 kb
Host smart-ddff8e32-0832-4e8c-8bad-da6a1be01ef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056388800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1056388800
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3236041442
Short name T150
Test name
Test status
Simulation time 18960381351 ps
CPU time 46.2 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:14:35 PM PDT 24
Peak memory 213524 kb
Host smart-bbb00542-8e6d-4f37-8390-52c4f0a187d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236041442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3236041442
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.3951571666
Short name T12
Test name
Test status
Simulation time 4646959504 ps
CPU time 4.31 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:13:54 PM PDT 24
Peak memory 205296 kb
Host smart-bf5fb359-85bc-4c54-8176-848b9e7ff7c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951571666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3951571666
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.764751512
Short name T39
Test name
Test status
Simulation time 14327096786 ps
CPU time 40.91 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:14:35 PM PDT 24
Peak memory 213504 kb
Host smart-6bfd242f-66b5-43a1-92e8-71d4cc0ae69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764751512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.764751512
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.1781583826
Short name T75
Test name
Test status
Simulation time 1137487584 ps
CPU time 2.05 seconds
Started Jul 04 05:13:37 PM PDT 24
Finished Jul 04 05:13:40 PM PDT 24
Peak memory 229288 kb
Host smart-93f41d5c-ce04-4a9f-bbe4-e92823966c28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781583826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.1781583826
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2789670988
Short name T37
Test name
Test status
Simulation time 139637827 ps
CPU time 0.96 seconds
Started Jul 04 05:13:08 PM PDT 24
Finished Jul 04 05:13:10 PM PDT 24
Peak memory 213300 kb
Host smart-6b2ef7cc-ae06-4dd0-8e48-f87f6510ee47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789670988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2789670988
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.1305959799
Short name T42
Test name
Test status
Simulation time 379585357 ps
CPU time 0.87 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:08 PM PDT 24
Peak memory 205060 kb
Host smart-3271fb74-c0b4-4a12-be87-cd1821abdcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305959799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.1305959799
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3676561038
Short name T181
Test name
Test status
Simulation time 4821046787 ps
CPU time 21.64 seconds
Started Jul 04 05:11:52 PM PDT 24
Finished Jul 04 05:12:14 PM PDT 24
Peak memory 213424 kb
Host smart-141bb0c0-b410-4d4a-8c54-725790dc0998
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676561038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3676561038
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1576119415
Short name T156
Test name
Test status
Simulation time 2725200014 ps
CPU time 3.06 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:50 PM PDT 24
Peak memory 205420 kb
Host smart-3eb6a713-a727-46cc-8fe8-e63a8fe7cd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576119415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1576119415
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.607802350
Short name T173
Test name
Test status
Simulation time 4590545087 ps
CPU time 4.13 seconds
Started Jul 04 05:13:43 PM PDT 24
Finished Jul 04 05:13:47 PM PDT 24
Peak memory 205292 kb
Host smart-554f41c4-cabc-42ec-a704-c10a0b5c387c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607802350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.607802350
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.3778859373
Short name T18
Test name
Test status
Simulation time 16587742920 ps
CPU time 22.46 seconds
Started Jul 04 05:14:03 PM PDT 24
Finished Jul 04 05:14:25 PM PDT 24
Peak memory 213504 kb
Host smart-5b007896-5f6c-4db0-ad4d-f98a753dba65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778859373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.3778859373
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.646609973
Short name T19
Test name
Test status
Simulation time 5114805961 ps
CPU time 1.92 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:09 PM PDT 24
Peak memory 205284 kb
Host smart-1b321711-a046-495f-9146-9fdfb4ab461a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646609973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.646609973
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.681444915
Short name T50
Test name
Test status
Simulation time 55986227940 ps
CPU time 150.28 seconds
Started Jul 04 05:11:53 PM PDT 24
Finished Jul 04 05:14:24 PM PDT 24
Peak memory 221668 kb
Host smart-09cd6ac6-04e4-4031-a040-ccb7bd472ab7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681444915 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.681444915
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1107262125
Short name T46
Test name
Test status
Simulation time 447613806 ps
CPU time 1.14 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:07 PM PDT 24
Peak memory 205024 kb
Host smart-db6e0c91-82c6-49ef-a4d4-f7a7e9946b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107262125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1107262125
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3536434035
Short name T184
Test name
Test status
Simulation time 5854286193 ps
CPU time 18.81 seconds
Started Jul 04 05:12:08 PM PDT 24
Finished Jul 04 05:12:27 PM PDT 24
Peak memory 213448 kb
Host smart-0ff6ab4f-4cd9-4a62-9ec5-cc699958d298
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536434035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
536434035
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3759071903
Short name T151
Test name
Test status
Simulation time 35729985599 ps
CPU time 28.62 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:14:18 PM PDT 24
Peak memory 213612 kb
Host smart-f7b306c0-0556-472e-bea2-d9de2a1051fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759071903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3759071903
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1645011488
Short name T162
Test name
Test status
Simulation time 9569142669 ps
CPU time 8.53 seconds
Started Jul 04 05:13:57 PM PDT 24
Finished Jul 04 05:14:06 PM PDT 24
Peak memory 213540 kb
Host smart-e968d3b1-1e00-4047-8e2a-5409b82b6e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645011488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1645011488
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3412843448
Short name T149
Test name
Test status
Simulation time 20309442358 ps
CPU time 8.18 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:14:00 PM PDT 24
Peak memory 213540 kb
Host smart-45e1237a-2c9f-4ef7-bce0-fce1536334c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412843448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3412843448
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.3721257194
Short name T124
Test name
Test status
Simulation time 7433413996 ps
CPU time 33.26 seconds
Started Jul 04 05:11:43 PM PDT 24
Finished Jul 04 05:12:17 PM PDT 24
Peak memory 213320 kb
Host smart-a1bbf966-df41-4b52-a650-c90e121cad89
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721257194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.3721257194
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.797169500
Short name T294
Test name
Test status
Simulation time 2423580335 ps
CPU time 2.46 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:40 PM PDT 24
Peak memory 204804 kb
Host smart-6aa38ab5-9099-4e80-9236-6954a7caebaa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797169500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.797169500
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3462862801
Short name T145
Test name
Test status
Simulation time 5144070625 ps
CPU time 4.53 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:12:56 PM PDT 24
Peak memory 205420 kb
Host smart-7c9eab4e-2e47-4e45-9ef8-8c7f712d5004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462862801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3462862801
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.1370739338
Short name T171
Test name
Test status
Simulation time 9662831124 ps
CPU time 10.09 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:14:03 PM PDT 24
Peak memory 205268 kb
Host smart-39e16ef2-2ab6-4a7d-88f8-9139a5e33d2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370739338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1370739338
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2341910972
Short name T178
Test name
Test status
Simulation time 9445665475 ps
CPU time 28.61 seconds
Started Jul 04 05:14:00 PM PDT 24
Finished Jul 04 05:14:29 PM PDT 24
Peak memory 205244 kb
Host smart-3b1e81fb-1f56-4416-9957-aa62240d4313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341910972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2341910972
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3634232027
Short name T148
Test name
Test status
Simulation time 1672378499 ps
CPU time 1.62 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:13:52 PM PDT 24
Peak memory 213572 kb
Host smart-443ad05a-a9f2-4463-a5bd-812783811468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634232027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3634232027
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2550822609
Short name T161
Test name
Test status
Simulation time 6807024529 ps
CPU time 10.66 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:14:04 PM PDT 24
Peak memory 213604 kb
Host smart-2b1ba7a9-1e6c-4237-b13b-580e93805c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550822609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2550822609
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2912021155
Short name T114
Test name
Test status
Simulation time 9029213738 ps
CPU time 8.63 seconds
Started Jul 04 05:11:37 PM PDT 24
Finished Jul 04 05:11:46 PM PDT 24
Peak memory 205152 kb
Host smart-837b524e-077e-44a3-b504-e9d55880a0d9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912021155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2912021155
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4028167151
Short name T135
Test name
Test status
Simulation time 1895701257 ps
CPU time 4.34 seconds
Started Jul 04 05:12:01 PM PDT 24
Finished Jul 04 05:12:05 PM PDT 24
Peak memory 205164 kb
Host smart-b73a5be6-2e5a-435f-9a75-3363087d2f10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028167151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.4028167151
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2086100194
Short name T68
Test name
Test status
Simulation time 833242369 ps
CPU time 1.92 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:49 PM PDT 24
Peak memory 213516 kb
Host smart-ce5d4474-39a9-4148-971f-6c4caef97361
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2086100194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2086100194
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2000698229
Short name T33
Test name
Test status
Simulation time 1850766036 ps
CPU time 2.05 seconds
Started Jul 04 05:12:54 PM PDT 24
Finished Jul 04 05:12:56 PM PDT 24
Peak memory 205060 kb
Host smart-c3075d95-ba46-4d80-834d-8e206081a84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000698229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2000698229
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3285154872
Short name T183
Test name
Test status
Simulation time 5343264250 ps
CPU time 15.96 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:53 PM PDT 24
Peak memory 213424 kb
Host smart-1853fb19-1254-401e-aac9-4dd9bc7553e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285154872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3285154872
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.4285801783
Short name T152
Test name
Test status
Simulation time 10498557432 ps
CPU time 7.41 seconds
Started Jul 04 05:12:50 PM PDT 24
Finished Jul 04 05:12:58 PM PDT 24
Peak memory 213616 kb
Host smart-e9e80222-4878-4ded-aaad-9990c33ac03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285801783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.4285801783
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.803232751
Short name T138
Test name
Test status
Simulation time 693181297 ps
CPU time 1.6 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:12:53 PM PDT 24
Peak memory 205000 kb
Host smart-b3f96b06-ba34-43b1-9a3c-0fdfbfa793ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803232751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.803232751
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2776106709
Short name T44
Test name
Test status
Simulation time 9828853497 ps
CPU time 9.35 seconds
Started Jul 04 05:12:48 PM PDT 24
Finished Jul 04 05:12:58 PM PDT 24
Peak memory 205256 kb
Host smart-080a3aaf-23b6-4ee2-8688-dca54b212e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776106709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2776106709
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3879068305
Short name T14
Test name
Test status
Simulation time 263335280 ps
CPU time 0.82 seconds
Started Jul 04 05:13:05 PM PDT 24
Finished Jul 04 05:13:07 PM PDT 24
Peak memory 205036 kb
Host smart-fd66735d-3e6e-4915-bffe-77532f2a4eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879068305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3879068305
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.1559663758
Short name T52
Test name
Test status
Simulation time 71590505 ps
CPU time 0.85 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:13:38 PM PDT 24
Peak memory 215624 kb
Host smart-0b6a770b-17ec-4d80-873b-eff6383429e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559663758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1559663758
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.952429980
Short name T146
Test name
Test status
Simulation time 3636032683 ps
CPU time 4.29 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:13:53 PM PDT 24
Peak memory 213568 kb
Host smart-4b207e58-7a98-4111-a89b-4bc6d939ca49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952429980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.952429980
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.2200345520
Short name T17
Test name
Test status
Simulation time 13499669091 ps
CPU time 28.96 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:14:17 PM PDT 24
Peak memory 213396 kb
Host smart-87917229-b449-4797-b137-3267e93506ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200345520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2200345520
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.888200576
Short name T48
Test name
Test status
Simulation time 1533149438 ps
CPU time 1.82 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:13:52 PM PDT 24
Peak memory 205288 kb
Host smart-f661c409-d253-4477-a264-1e92ddb96386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888200576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.888200576
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3245440968
Short name T155
Test name
Test status
Simulation time 1956000725 ps
CPU time 2.44 seconds
Started Jul 04 05:13:57 PM PDT 24
Finished Jul 04 05:13:59 PM PDT 24
Peak memory 213484 kb
Host smart-c362e169-a089-4d9a-b9fa-9e84ddf855d5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3245440968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3245440968
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.2433136070
Short name T167
Test name
Test status
Simulation time 3766523247 ps
CPU time 3.24 seconds
Started Jul 04 05:14:09 PM PDT 24
Finished Jul 04 05:14:12 PM PDT 24
Peak memory 205244 kb
Host smart-e4cf67bb-d727-44de-ad4c-1bffa4d19f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433136070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2433136070
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.3183883591
Short name T179
Test name
Test status
Simulation time 4335732551 ps
CPU time 5.8 seconds
Started Jul 04 05:14:19 PM PDT 24
Finished Jul 04 05:14:25 PM PDT 24
Peak memory 213444 kb
Host smart-546183de-da44-4816-8b17-016d181d1d77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183883591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.3183883591
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.2996602812
Short name T10
Test name
Test status
Simulation time 6555307740 ps
CPU time 18.35 seconds
Started Jul 04 05:14:16 PM PDT 24
Finished Jul 04 05:14:35 PM PDT 24
Peak memory 205360 kb
Host smart-aef2ea93-89b4-4f9a-b5d0-bd403fc776f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996602812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2996602812
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.1756138830
Short name T175
Test name
Test status
Simulation time 8415200301 ps
CPU time 12.9 seconds
Started Jul 04 05:14:25 PM PDT 24
Finished Jul 04 05:14:38 PM PDT 24
Peak memory 205288 kb
Host smart-d0d90e77-d0bc-4d9c-a13a-7c6edf162bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756138830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1756138830
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.4037868625
Short name T143
Test name
Test status
Simulation time 824399035 ps
CPU time 1.23 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:13:49 PM PDT 24
Peak memory 205296 kb
Host smart-78a7d00d-82c2-464a-8725-86ebb1b7d162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037868625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.4037868625
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1452960193
Short name T144
Test name
Test status
Simulation time 3833854869 ps
CPU time 9.83 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:13:59 PM PDT 24
Peak memory 205440 kb
Host smart-01f87409-70b6-43f0-b35f-992863f8692f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452960193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1452960193
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3598318319
Short name T69
Test name
Test status
Simulation time 1637101912 ps
CPU time 1.67 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:12:53 PM PDT 24
Peak memory 205272 kb
Host smart-9932f8f0-c66a-45b1-9da7-9f5c15e3d927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598318319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3598318319
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4019593813
Short name T127
Test name
Test status
Simulation time 14554200076 ps
CPU time 69.54 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:12:45 PM PDT 24
Peak memory 205044 kb
Host smart-78b0a3ac-f60c-4599-878c-378e6d6a41fb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019593813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.4019593813
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.851247939
Short name T349
Test name
Test status
Simulation time 10315886955 ps
CPU time 35.87 seconds
Started Jul 04 05:11:39 PM PDT 24
Finished Jul 04 05:12:15 PM PDT 24
Peak memory 213384 kb
Host smart-29ce1436-d7d7-44db-8724-d5f2b20823e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851247939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.851247939
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3071201086
Short name T106
Test name
Test status
Simulation time 80549093 ps
CPU time 1.6 seconds
Started Jul 04 05:11:38 PM PDT 24
Finished Jul 04 05:11:40 PM PDT 24
Peak memory 213320 kb
Host smart-04acdccb-b74c-4cdc-8b09-7b6832c94f50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071201086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3071201086
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.447967990
Short name T96
Test name
Test status
Simulation time 7181724611 ps
CPU time 14.07 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:51 PM PDT 24
Peak memory 219864 kb
Host smart-7d9c49cc-fb0a-44c5-a0c9-54efc147078d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447967990 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.447967990
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2331397147
Short name T314
Test name
Test status
Simulation time 554994461 ps
CPU time 1.56 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:38 PM PDT 24
Peak memory 213348 kb
Host smart-4ed5afda-3e5f-448b-b6a6-a6bb78781e2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331397147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2331397147
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3189398414
Short name T279
Test name
Test status
Simulation time 100358691573 ps
CPU time 259.42 seconds
Started Jul 04 05:11:37 PM PDT 24
Finished Jul 04 05:15:57 PM PDT 24
Peak memory 204980 kb
Host smart-3f25d154-2353-4cf5-a8cd-540872209052
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189398414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3189398414
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3443964462
Short name T302
Test name
Test status
Simulation time 23747407413 ps
CPU time 10.37 seconds
Started Jul 04 05:11:38 PM PDT 24
Finished Jul 04 05:11:48 PM PDT 24
Peak memory 205040 kb
Host smart-b763d70f-412f-4bf8-b185-6ba9bd2885f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443964462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.3443964462
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1080473720
Short name T287
Test name
Test status
Simulation time 1524636292 ps
CPU time 1.7 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:38 PM PDT 24
Peak memory 204904 kb
Host smart-1f32be6a-0dac-46ec-b72f-1a09d57be63c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080473720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
080473720
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2062964923
Short name T325
Test name
Test status
Simulation time 415328455 ps
CPU time 1.66 seconds
Started Jul 04 05:11:35 PM PDT 24
Finished Jul 04 05:11:37 PM PDT 24
Peak memory 204784 kb
Host smart-e92706bb-8406-4437-ac12-1321442d3f95
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062964923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2062964923
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.235285495
Short name T394
Test name
Test status
Simulation time 3654570283 ps
CPU time 9.73 seconds
Started Jul 04 05:11:37 PM PDT 24
Finished Jul 04 05:11:47 PM PDT 24
Peak memory 204936 kb
Host smart-6f6a6dd0-86e1-4628-965a-9210486247a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235285495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.235285495
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1952562704
Short name T389
Test name
Test status
Simulation time 505706172 ps
CPU time 1.04 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:37 PM PDT 24
Peak memory 204808 kb
Host smart-eeb15c8b-6a3e-45c3-a4ac-0b19c74e4e71
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952562704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1952562704
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3146844389
Short name T383
Test name
Test status
Simulation time 610650207 ps
CPU time 0.77 seconds
Started Jul 04 05:11:37 PM PDT 24
Finished Jul 04 05:11:38 PM PDT 24
Peak memory 204736 kb
Host smart-1eb8484b-7535-47f1-9521-a9bbb5472316
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146844389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
146844389
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1293593905
Short name T401
Test name
Test status
Simulation time 67239477 ps
CPU time 0.73 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:37 PM PDT 24
Peak memory 204648 kb
Host smart-e631acc7-9b6e-4450-a281-214668ee8dfa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293593905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1293593905
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.204853151
Short name T327
Test name
Test status
Simulation time 164508550 ps
CPU time 0.72 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:37 PM PDT 24
Peak memory 204776 kb
Host smart-da0b1df4-76e3-4cc1-9866-2311deaae6f9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204853151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.204853151
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1118648481
Short name T338
Test name
Test status
Simulation time 1648338827 ps
CPU time 7.21 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:43 PM PDT 24
Peak memory 205104 kb
Host smart-30b8fe9a-dfe4-400f-8612-122314d35cd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118648481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1118648481
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.2078331383
Short name T348
Test name
Test status
Simulation time 33211361220 ps
CPU time 94.16 seconds
Started Jul 04 05:11:37 PM PDT 24
Finished Jul 04 05:13:12 PM PDT 24
Peak memory 221544 kb
Host smart-9404c3ff-0ac8-48e5-83b0-6c2dabee66e1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078331383 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.2078331383
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.99474758
Short name T390
Test name
Test status
Simulation time 520305742 ps
CPU time 5.64 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:42 PM PDT 24
Peak memory 213256 kb
Host smart-7350be71-3e53-488f-b0e5-157b35d86e14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99474758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.99474758
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.169725410
Short name T321
Test name
Test status
Simulation time 2892323275 ps
CPU time 13.72 seconds
Started Jul 04 05:11:38 PM PDT 24
Finished Jul 04 05:11:51 PM PDT 24
Peak memory 213380 kb
Host smart-5ab85e17-e937-437e-934b-fe52836de8d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169725410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.169725410
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1606174465
Short name T131
Test name
Test status
Simulation time 636928402 ps
CPU time 27.41 seconds
Started Jul 04 05:11:39 PM PDT 24
Finished Jul 04 05:12:07 PM PDT 24
Peak memory 213336 kb
Host smart-78cdf7b7-c6b2-4fdb-a842-95cba9985bf7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606174465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1606174465
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4267572899
Short name T334
Test name
Test status
Simulation time 9982370316 ps
CPU time 35.96 seconds
Started Jul 04 05:11:45 PM PDT 24
Finished Jul 04 05:12:21 PM PDT 24
Peak memory 205240 kb
Host smart-0ee62985-791f-4e4a-a5e5-ed60c676b8c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267572899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4267572899
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3466486594
Short name T364
Test name
Test status
Simulation time 153909643 ps
CPU time 1.89 seconds
Started Jul 04 05:11:42 PM PDT 24
Finished Jul 04 05:11:45 PM PDT 24
Peak memory 213272 kb
Host smart-09df2efa-8c5e-43dd-b307-eee18407c551
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466486594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3466486594
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3119296313
Short name T141
Test name
Test status
Simulation time 802093831 ps
CPU time 4.07 seconds
Started Jul 04 05:11:45 PM PDT 24
Finished Jul 04 05:11:50 PM PDT 24
Peak memory 221476 kb
Host smart-9d5c4411-ab19-41b8-9c0c-286e4312499f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119296313 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3119296313
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2435413986
Short name T116
Test name
Test status
Simulation time 135550565 ps
CPU time 1.46 seconds
Started Jul 04 05:11:44 PM PDT 24
Finished Jul 04 05:11:46 PM PDT 24
Peak memory 213372 kb
Host smart-2d443beb-9774-4e01-890e-58dc7e11cc2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435413986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2435413986
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2127791569
Short name T346
Test name
Test status
Simulation time 70701827440 ps
CPU time 192.92 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:14:49 PM PDT 24
Peak memory 205004 kb
Host smart-ae7ceffe-d119-48a2-8a21-a9142dac9ce7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127791569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2127791569
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1725958438
Short name T280
Test name
Test status
Simulation time 22596233337 ps
CPU time 32.75 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:12:09 PM PDT 24
Peak memory 205008 kb
Host smart-3c8c4a0d-d52d-41ce-adf4-aaa3b19e0850
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725958438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1725958438
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.932249401
Short name T113
Test name
Test status
Simulation time 1553971231 ps
CPU time 1.56 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:39 PM PDT 24
Peak memory 205120 kb
Host smart-15394070-e3a4-42f4-a59b-f60a8008ac8f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932249401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.932249401
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.919805072
Short name T347
Test name
Test status
Simulation time 1052593601 ps
CPU time 1.81 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:38 PM PDT 24
Peak memory 204940 kb
Host smart-4768f16d-a4de-440e-ae31-db5591cac679
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919805072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.919805072
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2999743509
Short name T353
Test name
Test status
Simulation time 2415820362 ps
CPU time 2.77 seconds
Started Jul 04 05:11:39 PM PDT 24
Finished Jul 04 05:11:42 PM PDT 24
Peak memory 205000 kb
Host smart-dd0307a7-3d3f-4387-9928-61ef7cc920af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999743509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2999743509
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1751978672
Short name T333
Test name
Test status
Simulation time 318525512 ps
CPU time 1.13 seconds
Started Jul 04 05:11:37 PM PDT 24
Finished Jul 04 05:11:39 PM PDT 24
Peak memory 204800 kb
Host smart-ada5f0b2-3df5-4b8c-af02-4a8600eea42a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751978672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1751978672
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.650141190
Short name T341
Test name
Test status
Simulation time 257813496 ps
CPU time 1.22 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:37 PM PDT 24
Peak memory 204796 kb
Host smart-9798fcd8-7708-4580-ad43-660176b61157
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650141190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.650141190
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.973199404
Short name T362
Test name
Test status
Simulation time 72815494 ps
CPU time 0.68 seconds
Started Jul 04 05:11:38 PM PDT 24
Finished Jul 04 05:11:39 PM PDT 24
Peak memory 204700 kb
Host smart-8c8e0ec9-e8e8-49fe-b157-d004dc56744f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973199404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_part
ial_access.973199404
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3043682987
Short name T323
Test name
Test status
Simulation time 53029189 ps
CPU time 0.71 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:11:38 PM PDT 24
Peak memory 204688 kb
Host smart-f050c8e0-83fb-4dba-8508-2b84eefe7509
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043682987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3043682987
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3837320628
Short name T411
Test name
Test status
Simulation time 703366840 ps
CPU time 6.55 seconds
Started Jul 04 05:11:43 PM PDT 24
Finished Jul 04 05:11:50 PM PDT 24
Peak memory 205208 kb
Host smart-aba8321e-5020-4b17-8509-2c86df6b3939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837320628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3837320628
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3032165590
Short name T180
Test name
Test status
Simulation time 70479763786 ps
CPU time 106.98 seconds
Started Jul 04 05:11:36 PM PDT 24
Finished Jul 04 05:13:24 PM PDT 24
Peak memory 222756 kb
Host smart-4ab3a709-fe66-46ca-a15a-dbde64b0a1dd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032165590 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3032165590
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2168292529
Short name T65
Test name
Test status
Simulation time 261028079 ps
CPU time 4.89 seconds
Started Jul 04 05:11:37 PM PDT 24
Finished Jul 04 05:11:42 PM PDT 24
Peak memory 213328 kb
Host smart-ee851ae5-7d60-4ec5-8467-fdbcb68a61d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168292529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2168292529
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1211198858
Short name T305
Test name
Test status
Simulation time 2255326807 ps
CPU time 2.81 seconds
Started Jul 04 05:12:01 PM PDT 24
Finished Jul 04 05:12:05 PM PDT 24
Peak memory 215584 kb
Host smart-c191e608-ae00-4d2b-b9e3-9fdaa6e3dd01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211198858 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1211198858
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3980756914
Short name T130
Test name
Test status
Simulation time 67475964 ps
CPU time 1.56 seconds
Started Jul 04 05:12:02 PM PDT 24
Finished Jul 04 05:12:04 PM PDT 24
Peak memory 213340 kb
Host smart-8c7eedf4-968b-4cf6-b12b-bf6f6636bb63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980756914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3980756914
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1980077101
Short name T304
Test name
Test status
Simulation time 27528014025 ps
CPU time 38.46 seconds
Started Jul 04 05:12:00 PM PDT 24
Finished Jul 04 05:12:39 PM PDT 24
Peak memory 205012 kb
Host smart-c8220645-ce00-4ad5-81f5-1ae79a0c404c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980077101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.1980077101
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2823513955
Short name T375
Test name
Test status
Simulation time 3062444897 ps
CPU time 3.08 seconds
Started Jul 04 05:12:03 PM PDT 24
Finished Jul 04 05:12:06 PM PDT 24
Peak memory 205008 kb
Host smart-90eb4873-938e-4ae7-944b-26eb57c8c8d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823513955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2823513955
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2057592872
Short name T289
Test name
Test status
Simulation time 585778644 ps
CPU time 1.01 seconds
Started Jul 04 05:12:02 PM PDT 24
Finished Jul 04 05:12:04 PM PDT 24
Peak memory 204772 kb
Host smart-3a34a187-6383-4309-b5b4-15bbd5275f1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057592872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2057592872
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4001236369
Short name T126
Test name
Test status
Simulation time 936533433 ps
CPU time 4.05 seconds
Started Jul 04 05:12:00 PM PDT 24
Finished Jul 04 05:12:05 PM PDT 24
Peak memory 205124 kb
Host smart-13a6fa04-edab-4e54-875a-fc0bd6119960
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001236369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.4001236369
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4129870651
Short name T366
Test name
Test status
Simulation time 225858898 ps
CPU time 2.48 seconds
Started Jul 04 05:12:02 PM PDT 24
Finished Jul 04 05:12:05 PM PDT 24
Peak memory 213248 kb
Host smart-d100b37b-4a9d-44b3-83a2-a175b16f0627
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129870651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.4129870651
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2230102687
Short name T182
Test name
Test status
Simulation time 1726582420 ps
CPU time 20.73 seconds
Started Jul 04 05:12:01 PM PDT 24
Finished Jul 04 05:12:23 PM PDT 24
Peak memory 213328 kb
Host smart-5a060a51-48ae-4c59-8245-33da6573682e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230102687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
230102687
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1361365656
Short name T335
Test name
Test status
Simulation time 1482054293 ps
CPU time 2.87 seconds
Started Jul 04 05:12:01 PM PDT 24
Finished Jul 04 05:12:05 PM PDT 24
Peak memory 221552 kb
Host smart-c506d122-4bf1-42c4-8af3-8d83e5412215
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361365656 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1361365656
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4129039499
Short name T361
Test name
Test status
Simulation time 154242330 ps
CPU time 1.49 seconds
Started Jul 04 05:12:01 PM PDT 24
Finished Jul 04 05:12:03 PM PDT 24
Peak memory 213356 kb
Host smart-66a33afe-3c55-4b39-8584-4f03be42a288
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129039499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4129039499
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2679398843
Short name T324
Test name
Test status
Simulation time 1677511289 ps
CPU time 5.51 seconds
Started Jul 04 05:12:02 PM PDT 24
Finished Jul 04 05:12:08 PM PDT 24
Peak memory 204956 kb
Host smart-d31554c2-2db3-4108-b95a-0712b400d0e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679398843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.2679398843
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3788318035
Short name T426
Test name
Test status
Simulation time 4760128557 ps
CPU time 4.91 seconds
Started Jul 04 05:12:02 PM PDT 24
Finished Jul 04 05:12:08 PM PDT 24
Peak memory 205004 kb
Host smart-35c40489-7a0f-4d63-a585-82c0bf5ad6c8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788318035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3788318035
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.941596180
Short name T408
Test name
Test status
Simulation time 398253683 ps
CPU time 1.69 seconds
Started Jul 04 05:12:05 PM PDT 24
Finished Jul 04 05:12:07 PM PDT 24
Peak memory 204728 kb
Host smart-f2a97eb9-50ac-4cce-be5c-a52be0ad9d2a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941596180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.941596180
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1617243327
Short name T95
Test name
Test status
Simulation time 649468372 ps
CPU time 4.61 seconds
Started Jul 04 05:12:06 PM PDT 24
Finished Jul 04 05:12:11 PM PDT 24
Peak memory 213332 kb
Host smart-db150f05-7c51-4dd6-99dd-7e16fc345d48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617243327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1617243327
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1102131914
Short name T187
Test name
Test status
Simulation time 3251087639 ps
CPU time 12.57 seconds
Started Jul 04 05:12:05 PM PDT 24
Finished Jul 04 05:12:18 PM PDT 24
Peak memory 213368 kb
Host smart-00a06b39-e03a-4019-9df3-90c26f691b36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102131914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
102131914
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2578627665
Short name T400
Test name
Test status
Simulation time 128268072 ps
CPU time 2.14 seconds
Started Jul 04 05:12:08 PM PDT 24
Finished Jul 04 05:12:10 PM PDT 24
Peak memory 216816 kb
Host smart-49121817-5470-416b-b36e-f8b04c327abe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578627665 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2578627665
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3930210178
Short name T307
Test name
Test status
Simulation time 128171809 ps
CPU time 1.48 seconds
Started Jul 04 05:12:07 PM PDT 24
Finished Jul 04 05:12:09 PM PDT 24
Peak memory 213332 kb
Host smart-0005e0cb-50a5-4a2a-a412-3ca18b83dffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930210178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3930210178
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2019549974
Short name T330
Test name
Test status
Simulation time 23847181861 ps
CPU time 27.98 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:12:46 PM PDT 24
Peak memory 204948 kb
Host smart-22c08746-bb1f-4117-b010-e01c61e5a9c2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019549974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2019549974
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.985664350
Short name T407
Test name
Test status
Simulation time 2863283662 ps
CPU time 2.77 seconds
Started Jul 04 05:12:12 PM PDT 24
Finished Jul 04 05:12:15 PM PDT 24
Peak memory 204964 kb
Host smart-50be7ca4-9521-4095-9d53-b94302535d0c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985664350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.985664350
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1447023699
Short name T380
Test name
Test status
Simulation time 501208329 ps
CPU time 0.76 seconds
Started Jul 04 05:12:01 PM PDT 24
Finished Jul 04 05:12:02 PM PDT 24
Peak memory 204756 kb
Host smart-45533ffa-c585-45ef-adf4-dcce7b4b6f74
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447023699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1447023699
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2696920435
Short name T125
Test name
Test status
Simulation time 761432921 ps
CPU time 3.89 seconds
Started Jul 04 05:12:15 PM PDT 24
Finished Jul 04 05:12:19 PM PDT 24
Peak memory 205068 kb
Host smart-22c43d99-53b1-4bce-9c0f-bb6c25b40956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696920435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2696920435
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1983199398
Short name T355
Test name
Test status
Simulation time 178957843 ps
CPU time 2.22 seconds
Started Jul 04 05:12:07 PM PDT 24
Finished Jul 04 05:12:09 PM PDT 24
Peak memory 213400 kb
Host smart-0892b9a1-c0e0-4011-8576-e3339419afeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983199398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1983199398
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3299708462
Short name T185
Test name
Test status
Simulation time 1579348492 ps
CPU time 9.11 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:12:27 PM PDT 24
Peak memory 213272 kb
Host smart-e5c626da-3bc1-4b2b-8ee6-c6b22597ef68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299708462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
299708462
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1184596918
Short name T404
Test name
Test status
Simulation time 1528444732 ps
CPU time 2.97 seconds
Started Jul 04 05:12:07 PM PDT 24
Finished Jul 04 05:12:10 PM PDT 24
Peak memory 213396 kb
Host smart-8e762b3c-22d6-4586-b3f5-cf552c03ba7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184596918 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1184596918
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1806924542
Short name T117
Test name
Test status
Simulation time 144769815 ps
CPU time 2.38 seconds
Started Jul 04 05:12:12 PM PDT 24
Finished Jul 04 05:12:14 PM PDT 24
Peak memory 213304 kb
Host smart-64984050-f66e-4b03-9d05-9dee493a3e42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806924542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1806924542
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.157300862
Short name T322
Test name
Test status
Simulation time 9701536631 ps
CPU time 9.39 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:12:26 PM PDT 24
Peak memory 204992 kb
Host smart-2de16044-749a-4bb6-9964-4000e802e026
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157300862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
rv_dm_jtag_dmi_csr_bit_bash.157300862
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1675180182
Short name T282
Test name
Test status
Simulation time 5844996949 ps
CPU time 10.88 seconds
Started Jul 04 05:12:08 PM PDT 24
Finished Jul 04 05:12:19 PM PDT 24
Peak memory 204884 kb
Host smart-943e0663-6de9-41c6-8beb-55e6c49971d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675180182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1675180182
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1892654884
Short name T398
Test name
Test status
Simulation time 141493911 ps
CPU time 0.8 seconds
Started Jul 04 05:12:08 PM PDT 24
Finished Jul 04 05:12:09 PM PDT 24
Peak memory 204768 kb
Host smart-8488d386-cf1c-4bd4-9004-99424fe4eefb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892654884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1892654884
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.4099424171
Short name T99
Test name
Test status
Simulation time 1183030317 ps
CPU time 4.29 seconds
Started Jul 04 05:12:07 PM PDT 24
Finished Jul 04 05:12:12 PM PDT 24
Peak memory 205136 kb
Host smart-7ca343a0-22f8-48a9-82bb-c3d64bca020d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099424171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.4099424171
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2765255146
Short name T425
Test name
Test status
Simulation time 152056772 ps
CPU time 2.5 seconds
Started Jul 04 05:12:10 PM PDT 24
Finished Jul 04 05:12:13 PM PDT 24
Peak memory 213252 kb
Host smart-dd6a0dec-47da-4740-9508-94824a07c894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765255146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2765255146
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3406645294
Short name T93
Test name
Test status
Simulation time 1875860517 ps
CPU time 3.9 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:12:21 PM PDT 24
Peak memory 221424 kb
Host smart-3f0da5a2-ee8b-440d-957a-1fee3238d892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406645294 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3406645294
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.400386133
Short name T342
Test name
Test status
Simulation time 160172464 ps
CPU time 1.47 seconds
Started Jul 04 05:12:11 PM PDT 24
Finished Jul 04 05:12:13 PM PDT 24
Peak memory 213288 kb
Host smart-45680e2c-8d75-4e28-850b-3ebbfce26342
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400386133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.400386133
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1199569528
Short name T386
Test name
Test status
Simulation time 7673072597 ps
CPU time 5.77 seconds
Started Jul 04 05:12:07 PM PDT 24
Finished Jul 04 05:12:13 PM PDT 24
Peak memory 204960 kb
Host smart-c8b79660-9689-44f0-8f36-c42db0abf50c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199569528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.1199569528
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1789319381
Short name T350
Test name
Test status
Simulation time 1018485603 ps
CPU time 3.49 seconds
Started Jul 04 05:12:09 PM PDT 24
Finished Jul 04 05:12:12 PM PDT 24
Peak memory 204888 kb
Host smart-6e8ff599-0f6b-4e84-8681-327b97b32c5b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789319381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1789319381
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.749044530
Short name T421
Test name
Test status
Simulation time 270466251 ps
CPU time 1.3 seconds
Started Jul 04 05:12:07 PM PDT 24
Finished Jul 04 05:12:08 PM PDT 24
Peak memory 204760 kb
Host smart-54b1b146-a15f-4b50-af65-eafb26d13a4b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749044530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.749044530
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1551157055
Short name T134
Test name
Test status
Simulation time 438466058 ps
CPU time 7.21 seconds
Started Jul 04 05:12:12 PM PDT 24
Finished Jul 04 05:12:19 PM PDT 24
Peak memory 205040 kb
Host smart-196198d3-84ea-40fc-8d43-05d47a9a5ac0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551157055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1551157055
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2938917433
Short name T393
Test name
Test status
Simulation time 3641181791 ps
CPU time 6.24 seconds
Started Jul 04 05:12:11 PM PDT 24
Finished Jul 04 05:12:17 PM PDT 24
Peak memory 213272 kb
Host smart-ac86a220-84eb-4067-902a-74ada5deffaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938917433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2938917433
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.377619001
Short name T420
Test name
Test status
Simulation time 5076407293 ps
CPU time 21.44 seconds
Started Jul 04 05:12:09 PM PDT 24
Finished Jul 04 05:12:31 PM PDT 24
Peak memory 213388 kb
Host smart-6a256b3e-4dcd-4894-9c1d-7debf69ed21f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377619001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.377619001
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1313439750
Short name T112
Test name
Test status
Simulation time 3210031540 ps
CPU time 6.25 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:12:24 PM PDT 24
Peak memory 220164 kb
Host smart-036272c8-8c7b-4450-8e26-3a9cb8f452d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313439750 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1313439750
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1723661042
Short name T120
Test name
Test status
Simulation time 220054752 ps
CPU time 2.34 seconds
Started Jul 04 05:12:18 PM PDT 24
Finished Jul 04 05:12:21 PM PDT 24
Peak memory 213236 kb
Host smart-9425bb6b-cb8c-45b2-b86b-616dcfb8342f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723661042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1723661042
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.451724769
Short name T403
Test name
Test status
Simulation time 18286951288 ps
CPU time 49.39 seconds
Started Jul 04 05:12:09 PM PDT 24
Finished Jul 04 05:12:59 PM PDT 24
Peak memory 205028 kb
Host smart-00c1d733-d94b-4f63-9e48-a16d766349d9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451724769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rv_dm_jtag_dmi_csr_bit_bash.451724769
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3825341820
Short name T395
Test name
Test status
Simulation time 2307891007 ps
CPU time 3.92 seconds
Started Jul 04 05:12:08 PM PDT 24
Finished Jul 04 05:12:12 PM PDT 24
Peak memory 205004 kb
Host smart-bdda6e5c-5ec4-4d7b-b151-53a8b7222a66
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825341820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3825341820
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2124884626
Short name T91
Test name
Test status
Simulation time 193079771 ps
CPU time 0.81 seconds
Started Jul 04 05:12:08 PM PDT 24
Finished Jul 04 05:12:09 PM PDT 24
Peak memory 204768 kb
Host smart-3578636e-81e1-4b76-a1e9-763713288872
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124884626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2124884626
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.648064265
Short name T136
Test name
Test status
Simulation time 227872717 ps
CPU time 3.49 seconds
Started Jul 04 05:12:19 PM PDT 24
Finished Jul 04 05:12:23 PM PDT 24
Peak memory 205100 kb
Host smart-f59cc71b-a6fe-48bd-bf36-7605771dd006
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648064265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_
csr_outstanding.648064265
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.957674862
Short name T382
Test name
Test status
Simulation time 265942298 ps
CPU time 4.39 seconds
Started Jul 04 05:12:07 PM PDT 24
Finished Jul 04 05:12:12 PM PDT 24
Peak memory 213316 kb
Host smart-53deddde-a306-4f97-b13b-49ef46b1acf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957674862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.957674862
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2550629836
Short name T345
Test name
Test status
Simulation time 2353006794 ps
CPU time 4.08 seconds
Started Jul 04 05:12:16 PM PDT 24
Finished Jul 04 05:12:21 PM PDT 24
Peak memory 219504 kb
Host smart-6dbf9d24-3172-46a4-a387-2f15ecb9b941
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550629836 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2550629836
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1662016345
Short name T303
Test name
Test status
Simulation time 60655308 ps
CPU time 1.44 seconds
Started Jul 04 05:12:15 PM PDT 24
Finished Jul 04 05:12:17 PM PDT 24
Peak memory 213292 kb
Host smart-91098817-c858-4f8b-87f8-ead3b61fc160
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662016345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1662016345
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2581819707
Short name T293
Test name
Test status
Simulation time 1789687140 ps
CPU time 1.36 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:12:19 PM PDT 24
Peak memory 204960 kb
Host smart-32392a74-a678-4009-84d7-3c53c075ba38
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581819707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.2581819707
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.477035689
Short name T358
Test name
Test status
Simulation time 1508707678 ps
CPU time 3.14 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:12:21 PM PDT 24
Peak memory 204960 kb
Host smart-509c5340-c41e-4ef2-b33d-0b1f4570a9e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477035689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.477035689
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3707481502
Short name T368
Test name
Test status
Simulation time 507668138 ps
CPU time 1.01 seconds
Started Jul 04 05:12:16 PM PDT 24
Finished Jul 04 05:12:17 PM PDT 24
Peak memory 204768 kb
Host smart-d82550c6-2291-44bd-bb17-d4989cd33147
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707481502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3707481502
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.556656249
Short name T103
Test name
Test status
Simulation time 398310586 ps
CPU time 4.39 seconds
Started Jul 04 05:12:15 PM PDT 24
Finished Jul 04 05:12:20 PM PDT 24
Peak memory 205064 kb
Host smart-1aaf07c5-26b1-45ee-9003-2e7ec053eca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556656249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.556656249
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.275059478
Short name T410
Test name
Test status
Simulation time 490589128 ps
CPU time 3.05 seconds
Started Jul 04 05:12:18 PM PDT 24
Finished Jul 04 05:12:22 PM PDT 24
Peak memory 215948 kb
Host smart-352d36b3-db58-40c0-bc30-916624164ab5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275059478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.275059478
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3372741698
Short name T190
Test name
Test status
Simulation time 1633334020 ps
CPU time 12.32 seconds
Started Jul 04 05:12:16 PM PDT 24
Finished Jul 04 05:12:29 PM PDT 24
Peak memory 213408 kb
Host smart-c310907c-97d7-4902-b2d9-b67b9143d3b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372741698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
372741698
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1785533380
Short name T384
Test name
Test status
Simulation time 643694287 ps
CPU time 3.76 seconds
Started Jul 04 05:12:16 PM PDT 24
Finished Jul 04 05:12:20 PM PDT 24
Peak memory 217104 kb
Host smart-7bfe3ded-7b76-4d73-8ebc-92d3e402335e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785533380 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1785533380
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1527055275
Short name T132
Test name
Test status
Simulation time 121997394 ps
CPU time 2.23 seconds
Started Jul 04 05:12:20 PM PDT 24
Finished Jul 04 05:12:22 PM PDT 24
Peak memory 213388 kb
Host smart-b03f904f-558f-48a7-91c0-18a8c814bc9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527055275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1527055275
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.4125375399
Short name T388
Test name
Test status
Simulation time 15961713057 ps
CPU time 12.11 seconds
Started Jul 04 05:12:16 PM PDT 24
Finished Jul 04 05:12:28 PM PDT 24
Peak memory 204968 kb
Host smart-b390d3b6-73c9-474d-a6d2-0adb2987bff3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125375399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.4125375399
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1635579203
Short name T320
Test name
Test status
Simulation time 1993823231 ps
CPU time 2.77 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:12:20 PM PDT 24
Peak memory 204928 kb
Host smart-11e5c76e-4b4d-434c-8319-3fc7fd5a36c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635579203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1635579203
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2023223031
Short name T298
Test name
Test status
Simulation time 1101814915 ps
CPU time 1.72 seconds
Started Jul 04 05:12:18 PM PDT 24
Finished Jul 04 05:12:20 PM PDT 24
Peak memory 204752 kb
Host smart-e6b646cd-39ec-47b4-b558-36777f5143e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023223031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2023223031
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2656541933
Short name T415
Test name
Test status
Simulation time 970849374 ps
CPU time 4.04 seconds
Started Jul 04 05:12:16 PM PDT 24
Finished Jul 04 05:12:20 PM PDT 24
Peak memory 205204 kb
Host smart-9845164f-7a74-479c-ad5e-7957280a46c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656541933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2656541933
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2924227198
Short name T385
Test name
Test status
Simulation time 156597441 ps
CPU time 3.86 seconds
Started Jul 04 05:12:15 PM PDT 24
Finished Jul 04 05:12:19 PM PDT 24
Peak memory 213332 kb
Host smart-dc391890-fc0c-4194-88bd-4b10680d6571
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924227198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2924227198
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2343293207
Short name T139
Test name
Test status
Simulation time 4000700043 ps
CPU time 19.71 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:12:37 PM PDT 24
Peak memory 213304 kb
Host smart-efb098e2-fd0d-4285-8fb1-0ec59fb97575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343293207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
343293207
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.782346632
Short name T356
Test name
Test status
Simulation time 2352602815 ps
CPU time 3.81 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:12:21 PM PDT 24
Peak memory 221548 kb
Host smart-d7763b1a-c963-45eb-a8e5-7efa29f48802
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782346632 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.782346632
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2256720806
Short name T339
Test name
Test status
Simulation time 121401181 ps
CPU time 1.49 seconds
Started Jul 04 05:12:16 PM PDT 24
Finished Jul 04 05:12:18 PM PDT 24
Peak memory 213284 kb
Host smart-8019c5f7-9682-4551-bad7-9264f6bae718
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256720806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2256720806
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3303257552
Short name T427
Test name
Test status
Simulation time 43037487285 ps
CPU time 110.21 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:14:08 PM PDT 24
Peak memory 205028 kb
Host smart-5ac5d78b-af06-4ec4-bda0-68447a162dcd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303257552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.3303257552
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.594530632
Short name T377
Test name
Test status
Simulation time 936302807 ps
CPU time 1.39 seconds
Started Jul 04 05:12:18 PM PDT 24
Finished Jul 04 05:12:20 PM PDT 24
Peak memory 204964 kb
Host smart-65cef87c-1f77-4b21-8820-e4edbcb8ecbd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594530632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.594530632
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.102202725
Short name T379
Test name
Test status
Simulation time 142259790 ps
CPU time 0.88 seconds
Started Jul 04 05:12:19 PM PDT 24
Finished Jul 04 05:12:21 PM PDT 24
Peak memory 204740 kb
Host smart-205f0c63-553e-4eb3-87ab-f9472926e1e3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102202725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.102202725
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.4005113991
Short name T133
Test name
Test status
Simulation time 815480569 ps
CPU time 3.97 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:12:21 PM PDT 24
Peak memory 205188 kb
Host smart-30664e85-539c-4fad-9218-92084dbfb3c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005113991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.4005113991
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2042742277
Short name T97
Test name
Test status
Simulation time 1044646334 ps
CPU time 3.27 seconds
Started Jul 04 05:12:19 PM PDT 24
Finished Jul 04 05:12:23 PM PDT 24
Peak memory 213372 kb
Host smart-41c970dd-296b-41db-881b-8ec87fb89128
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042742277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2042742277
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3159099349
Short name T188
Test name
Test status
Simulation time 2829263907 ps
CPU time 19.75 seconds
Started Jul 04 05:12:15 PM PDT 24
Finished Jul 04 05:12:35 PM PDT 24
Peak memory 213364 kb
Host smart-16002d80-76e5-4ef6-a515-6442d17ff3f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159099349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
159099349
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4257949292
Short name T319
Test name
Test status
Simulation time 92821726 ps
CPU time 2.71 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:12:20 PM PDT 24
Peak memory 218152 kb
Host smart-63548128-36fc-4890-acd3-8dceae1fd201
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257949292 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.4257949292
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2913356819
Short name T129
Test name
Test status
Simulation time 117951390 ps
CPU time 2.45 seconds
Started Jul 04 05:12:18 PM PDT 24
Finished Jul 04 05:12:21 PM PDT 24
Peak memory 213276 kb
Host smart-07198c4e-9b9b-46d1-be69-3680155a5861
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913356819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2913356819
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.478731108
Short name T418
Test name
Test status
Simulation time 34898860499 ps
CPU time 47.09 seconds
Started Jul 04 05:12:15 PM PDT 24
Finished Jul 04 05:13:02 PM PDT 24
Peak memory 205004 kb
Host smart-85fe5dc7-b119-40e3-aa57-2147c2fae0ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478731108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.478731108
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1922500939
Short name T360
Test name
Test status
Simulation time 3894095692 ps
CPU time 11.82 seconds
Started Jul 04 05:12:18 PM PDT 24
Finished Jul 04 05:12:30 PM PDT 24
Peak memory 204948 kb
Host smart-2b6ec71c-0ebe-45cd-a915-7ececc3e666e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922500939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1922500939
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2536747826
Short name T340
Test name
Test status
Simulation time 397258709 ps
CPU time 1.26 seconds
Started Jul 04 05:12:14 PM PDT 24
Finished Jul 04 05:12:16 PM PDT 24
Peak memory 204740 kb
Host smart-eb0e99d0-4317-4e1a-bfd8-14406cc0f344
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536747826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2536747826
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1176808402
Short name T413
Test name
Test status
Simulation time 205877845 ps
CPU time 3.79 seconds
Started Jul 04 05:12:15 PM PDT 24
Finished Jul 04 05:12:19 PM PDT 24
Peak memory 205156 kb
Host smart-13fd2323-376a-454d-a9a6-0249c26d56d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176808402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1176808402
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2104639544
Short name T299
Test name
Test status
Simulation time 153843866 ps
CPU time 3.54 seconds
Started Jul 04 05:12:19 PM PDT 24
Finished Jul 04 05:12:23 PM PDT 24
Peak memory 213368 kb
Host smart-d0237dda-8818-46d1-a843-d6c0111cae74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104639544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2104639544
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3819250261
Short name T428
Test name
Test status
Simulation time 4505614319 ps
CPU time 27.62 seconds
Started Jul 04 05:12:18 PM PDT 24
Finished Jul 04 05:12:46 PM PDT 24
Peak memory 213348 kb
Host smart-c3b166a5-5de6-4c38-9824-1a8396dae977
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819250261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
819250261
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.64470702
Short name T318
Test name
Test status
Simulation time 15643457698 ps
CPU time 60.71 seconds
Started Jul 04 05:11:46 PM PDT 24
Finished Jul 04 05:12:47 PM PDT 24
Peak memory 213344 kb
Host smart-d3b03e78-1570-4216-8c00-a020cd2dad4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64470702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.64470702
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2855575128
Short name T311
Test name
Test status
Simulation time 2428559413 ps
CPU time 4.85 seconds
Started Jul 04 05:11:45 PM PDT 24
Finished Jul 04 05:11:50 PM PDT 24
Peak memory 219740 kb
Host smart-edd3d716-9e32-49cb-9ef0-3c27e8e4d328
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855575128 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2855575128
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3354385193
Short name T118
Test name
Test status
Simulation time 57421698 ps
CPU time 1.45 seconds
Started Jul 04 05:11:46 PM PDT 24
Finished Jul 04 05:11:48 PM PDT 24
Peak memory 213332 kb
Host smart-f11d771c-4604-40e1-b02e-7da1ea61eee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354385193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3354385193
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3212417862
Short name T343
Test name
Test status
Simulation time 84362277888 ps
CPU time 201.32 seconds
Started Jul 04 05:11:46 PM PDT 24
Finished Jul 04 05:15:08 PM PDT 24
Peak memory 205028 kb
Host smart-bd5849f0-efe6-43b5-be3c-1f78d11d83b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212417862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3212417862
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2852353123
Short name T329
Test name
Test status
Simulation time 35136130952 ps
CPU time 17.21 seconds
Started Jul 04 05:11:45 PM PDT 24
Finished Jul 04 05:12:02 PM PDT 24
Peak memory 205024 kb
Host smart-7903d66f-d8b7-48bf-bf58-224f4100f7be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852353123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.2852353123
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2019666953
Short name T292
Test name
Test status
Simulation time 4949278483 ps
CPU time 8.81 seconds
Started Jul 04 05:11:46 PM PDT 24
Finished Jul 04 05:11:55 PM PDT 24
Peak memory 205012 kb
Host smart-fa16675b-95f7-43de-a303-aa57c5846543
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019666953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2019666953
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2279387565
Short name T306
Test name
Test status
Simulation time 1873351733 ps
CPU time 4.87 seconds
Started Jul 04 05:11:46 PM PDT 24
Finished Jul 04 05:11:51 PM PDT 24
Peak memory 204952 kb
Host smart-0fa05976-17a6-49b0-9c59-29a7c4be1e37
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279387565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
279387565
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2385623684
Short name T381
Test name
Test status
Simulation time 368848945 ps
CPU time 1.25 seconds
Started Jul 04 05:11:49 PM PDT 24
Finished Jul 04 05:11:51 PM PDT 24
Peak memory 204728 kb
Host smart-23393fd2-eaa1-4f8d-acaf-2b4a91c58c0f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385623684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2385623684
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2665110895
Short name T285
Test name
Test status
Simulation time 5174078612 ps
CPU time 15.29 seconds
Started Jul 04 05:11:45 PM PDT 24
Finished Jul 04 05:12:00 PM PDT 24
Peak memory 205004 kb
Host smart-8fc82426-dbad-490f-945f-7cb701e4378c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665110895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2665110895
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3638082817
Short name T295
Test name
Test status
Simulation time 208817053 ps
CPU time 0.78 seconds
Started Jul 04 05:11:44 PM PDT 24
Finished Jul 04 05:11:45 PM PDT 24
Peak memory 204840 kb
Host smart-229cf3b6-929f-4405-aa98-b854cc53ac16
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638082817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3638082817
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3989286699
Short name T337
Test name
Test status
Simulation time 103123725 ps
CPU time 0.9 seconds
Started Jul 04 05:11:44 PM PDT 24
Finished Jul 04 05:11:46 PM PDT 24
Peak memory 204776 kb
Host smart-e5a3fd9e-7ba4-4c6a-808c-2325faff4d73
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989286699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
989286699
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.808572180
Short name T416
Test name
Test status
Simulation time 96618434 ps
CPU time 0.65 seconds
Started Jul 04 05:11:46 PM PDT 24
Finished Jul 04 05:11:47 PM PDT 24
Peak memory 204708 kb
Host smart-560ddb58-2e18-415c-a41a-a10360431425
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808572180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.808572180
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4059455309
Short name T290
Test name
Test status
Simulation time 73503237 ps
CPU time 0.67 seconds
Started Jul 04 05:11:45 PM PDT 24
Finished Jul 04 05:11:46 PM PDT 24
Peak memory 204792 kb
Host smart-d5b9688c-0f7c-422a-a97c-53f31f9f65ba
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059455309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.4059455309
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2898385762
Short name T363
Test name
Test status
Simulation time 740222070 ps
CPU time 6.49 seconds
Started Jul 04 05:11:45 PM PDT 24
Finished Jul 04 05:11:52 PM PDT 24
Peak memory 205152 kb
Host smart-d6f4d000-182b-4f2f-86de-0c9ed83976c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898385762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2898385762
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3559268041
Short name T417
Test name
Test status
Simulation time 56565192836 ps
CPU time 142.3 seconds
Started Jul 04 05:11:42 PM PDT 24
Finished Jul 04 05:14:05 PM PDT 24
Peak memory 221460 kb
Host smart-13e038e5-c5d8-4e45-bb20-0b7b3778a247
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559268041 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3559268041
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3258601929
Short name T419
Test name
Test status
Simulation time 782814330 ps
CPU time 5.26 seconds
Started Jul 04 05:11:47 PM PDT 24
Finished Jul 04 05:11:53 PM PDT 24
Peak memory 213348 kb
Host smart-1137b159-4562-4ab0-855a-1ce74e7a8f0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258601929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3258601929
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4176546332
Short name T186
Test name
Test status
Simulation time 5137373888 ps
CPU time 27.63 seconds
Started Jul 04 05:11:43 PM PDT 24
Finished Jul 04 05:12:11 PM PDT 24
Peak memory 213380 kb
Host smart-405440e2-4612-415c-b4fa-97d1c897db5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176546332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.4176546332
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1925964441
Short name T300
Test name
Test status
Simulation time 7785467955 ps
CPU time 34.93 seconds
Started Jul 04 05:11:46 PM PDT 24
Finished Jul 04 05:12:22 PM PDT 24
Peak memory 205128 kb
Host smart-b3ac4bf3-f04e-40f7-bbc7-bcaa1f9d0f71
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925964441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1925964441
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1722785010
Short name T288
Test name
Test status
Simulation time 816522685 ps
CPU time 27.67 seconds
Started Jul 04 05:11:45 PM PDT 24
Finished Jul 04 05:12:13 PM PDT 24
Peak memory 213332 kb
Host smart-a3e2025d-47c7-4908-82ab-32844d5545e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722785010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1722785010
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.998557577
Short name T387
Test name
Test status
Simulation time 143628540 ps
CPU time 1.79 seconds
Started Jul 04 05:11:47 PM PDT 24
Finished Jul 04 05:11:49 PM PDT 24
Peak memory 213344 kb
Host smart-abd76c8c-6d5e-40d4-afb0-d6d4077a73b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998557577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.998557577
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3474844462
Short name T94
Test name
Test status
Simulation time 127474399 ps
CPU time 2.28 seconds
Started Jul 04 05:11:45 PM PDT 24
Finished Jul 04 05:11:47 PM PDT 24
Peak memory 213444 kb
Host smart-d8ca0d7c-9363-4a67-8702-afbd4882d707
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474844462 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3474844462
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3720030788
Short name T105
Test name
Test status
Simulation time 211173228 ps
CPU time 2.1 seconds
Started Jul 04 05:11:46 PM PDT 24
Finished Jul 04 05:11:48 PM PDT 24
Peak memory 213336 kb
Host smart-74a32ed1-4336-4446-90aa-fdf2918fcccc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720030788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3720030788
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3086922541
Short name T281
Test name
Test status
Simulation time 65034545591 ps
CPU time 166.77 seconds
Started Jul 04 05:11:46 PM PDT 24
Finished Jul 04 05:14:33 PM PDT 24
Peak memory 205028 kb
Host smart-7bc4359d-2e12-47d0-92b3-629770287d42
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086922541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3086922541
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.272745153
Short name T429
Test name
Test status
Simulation time 40689842870 ps
CPU time 31.38 seconds
Started Jul 04 05:11:47 PM PDT 24
Finished Jul 04 05:12:19 PM PDT 24
Peak memory 204984 kb
Host smart-ecefed93-c633-44a2-bbd7-5ccc8ee492ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272745153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
v_dm_jtag_dmi_csr_bit_bash.272745153
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.695096470
Short name T115
Test name
Test status
Simulation time 3286163216 ps
CPU time 5.93 seconds
Started Jul 04 05:11:42 PM PDT 24
Finished Jul 04 05:11:49 PM PDT 24
Peak memory 205124 kb
Host smart-ebbca09e-48de-4f38-b98b-ab90377ccd1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695096470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.695096470
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3992881241
Short name T283
Test name
Test status
Simulation time 1270201216 ps
CPU time 1.63 seconds
Started Jul 04 05:11:43 PM PDT 24
Finished Jul 04 05:11:45 PM PDT 24
Peak memory 204940 kb
Host smart-8a1b8f6c-cd67-47e9-aab6-51d8299a7051
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992881241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
992881241
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.3592953735
Short name T376
Test name
Test status
Simulation time 394381350 ps
CPU time 0.9 seconds
Started Jul 04 05:11:45 PM PDT 24
Finished Jul 04 05:11:47 PM PDT 24
Peak memory 204748 kb
Host smart-891cfd0c-2743-4ef1-89a9-4983ff830d20
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592953735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.3592953735
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2119882624
Short name T89
Test name
Test status
Simulation time 5053582789 ps
CPU time 3.91 seconds
Started Jul 04 05:11:44 PM PDT 24
Finished Jul 04 05:11:48 PM PDT 24
Peak memory 205004 kb
Host smart-b59b4c35-ea25-4e75-93de-52598b67f28c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119882624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2119882624
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.270062646
Short name T352
Test name
Test status
Simulation time 267331586 ps
CPU time 0.74 seconds
Started Jul 04 05:11:47 PM PDT 24
Finished Jul 04 05:11:48 PM PDT 24
Peak memory 204808 kb
Host smart-25b6b6ef-d0c7-4cd6-ae70-29e077f6ab1a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270062646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.270062646
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2253104254
Short name T296
Test name
Test status
Simulation time 91274450 ps
CPU time 0.91 seconds
Started Jul 04 05:11:44 PM PDT 24
Finished Jul 04 05:11:45 PM PDT 24
Peak memory 204756 kb
Host smart-3c269036-5d4b-4475-876e-e5175b2131d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253104254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
253104254
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2028754605
Short name T365
Test name
Test status
Simulation time 89650258 ps
CPU time 0.71 seconds
Started Jul 04 05:11:44 PM PDT 24
Finished Jul 04 05:11:45 PM PDT 24
Peak memory 204676 kb
Host smart-667e62d4-bfb2-4c64-9917-38fbd49ddd6c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028754605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2028754605
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.870759016
Short name T396
Test name
Test status
Simulation time 83194123 ps
CPU time 0.68 seconds
Started Jul 04 05:11:42 PM PDT 24
Finished Jul 04 05:11:43 PM PDT 24
Peak memory 204764 kb
Host smart-0b9d953a-031d-43c8-a5ab-de7caed8c47f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870759016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.870759016
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.919779752
Short name T122
Test name
Test status
Simulation time 270289254 ps
CPU time 6.69 seconds
Started Jul 04 05:11:45 PM PDT 24
Finished Jul 04 05:11:53 PM PDT 24
Peak memory 205132 kb
Host smart-b0a8d049-a8a7-4c48-b772-f457cd3a01a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919779752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.919779752
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.879703262
Short name T92
Test name
Test status
Simulation time 647662800 ps
CPU time 4.5 seconds
Started Jul 04 05:11:43 PM PDT 24
Finished Jul 04 05:11:48 PM PDT 24
Peak memory 213296 kb
Host smart-5178238f-2af9-4720-9589-f6acf925e71b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879703262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.879703262
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.194527417
Short name T391
Test name
Test status
Simulation time 2292270090 ps
CPU time 22.98 seconds
Started Jul 04 05:11:45 PM PDT 24
Finished Jul 04 05:12:08 PM PDT 24
Peak memory 213364 kb
Host smart-3acb5e2a-a77d-4829-8a31-844f8160a826
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194527417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.194527417
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.544189074
Short name T102
Test name
Test status
Simulation time 4315247976 ps
CPU time 61.26 seconds
Started Jul 04 05:11:53 PM PDT 24
Finished Jul 04 05:12:55 PM PDT 24
Peak memory 213432 kb
Host smart-7bedc15d-7d1c-42f4-935e-5ebb78ec92d7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544189074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.544189074
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4131799818
Short name T332
Test name
Test status
Simulation time 5145095238 ps
CPU time 67.91 seconds
Started Jul 04 05:11:52 PM PDT 24
Finished Jul 04 05:13:01 PM PDT 24
Peak memory 213388 kb
Host smart-a14c9a3d-b7db-464d-a5cd-e76c45e15d6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131799818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.4131799818
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1153570438
Short name T100
Test name
Test status
Simulation time 77908300 ps
CPU time 1.67 seconds
Started Jul 04 05:11:54 PM PDT 24
Finished Jul 04 05:11:56 PM PDT 24
Peak memory 213272 kb
Host smart-44b15e84-5802-4a73-825d-92d4fcad43d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153570438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1153570438
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3186932659
Short name T140
Test name
Test status
Simulation time 2927229208 ps
CPU time 5.42 seconds
Started Jul 04 05:11:57 PM PDT 24
Finished Jul 04 05:12:02 PM PDT 24
Peak memory 219204 kb
Host smart-8c42200b-4370-4e0e-8aa1-bc13ed3ca7e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186932659 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3186932659
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.373797119
Short name T128
Test name
Test status
Simulation time 263400183 ps
CPU time 2.32 seconds
Started Jul 04 05:11:53 PM PDT 24
Finished Jul 04 05:11:56 PM PDT 24
Peak memory 213380 kb
Host smart-55326d5c-9dcb-46e3-85d5-77275a00e6fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373797119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.373797119
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1964659678
Short name T312
Test name
Test status
Simulation time 24233745832 ps
CPU time 21.77 seconds
Started Jul 04 05:11:52 PM PDT 24
Finished Jul 04 05:12:15 PM PDT 24
Peak memory 205076 kb
Host smart-60de46ef-5be0-48a4-b132-13e33eb54894
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964659678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1964659678
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.927953611
Short name T354
Test name
Test status
Simulation time 23456454414 ps
CPU time 66.3 seconds
Started Jul 04 05:11:51 PM PDT 24
Finished Jul 04 05:12:58 PM PDT 24
Peak memory 205024 kb
Host smart-5d705de9-4ed2-4648-a2a7-e521cce72a65
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927953611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.927953611
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1628499858
Short name T297
Test name
Test status
Simulation time 5109107562 ps
CPU time 4.42 seconds
Started Jul 04 05:12:00 PM PDT 24
Finished Jul 04 05:12:04 PM PDT 24
Peak memory 205000 kb
Host smart-c9805a49-923d-438c-830f-beff1bdbddba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628499858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1628499858
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1362755743
Short name T328
Test name
Test status
Simulation time 1983264971 ps
CPU time 1.46 seconds
Started Jul 04 05:11:58 PM PDT 24
Finished Jul 04 05:12:00 PM PDT 24
Peak memory 204952 kb
Host smart-c3766dac-c5f9-4f37-bcbf-328588838c1b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362755743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
362755743
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3480330256
Short name T308
Test name
Test status
Simulation time 412292775 ps
CPU time 0.88 seconds
Started Jul 04 05:11:51 PM PDT 24
Finished Jul 04 05:11:53 PM PDT 24
Peak memory 204736 kb
Host smart-ffdf1067-2758-4b03-9c9f-1525042ce4dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480330256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3480330256
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.338138380
Short name T291
Test name
Test status
Simulation time 3181484379 ps
CPU time 5.36 seconds
Started Jul 04 05:11:52 PM PDT 24
Finished Jul 04 05:11:57 PM PDT 24
Peak memory 205000 kb
Host smart-aea5eda4-ef6a-401c-97f8-ea1056332384
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338138380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.338138380
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2760330426
Short name T372
Test name
Test status
Simulation time 322093973 ps
CPU time 1.46 seconds
Started Jul 04 05:11:58 PM PDT 24
Finished Jul 04 05:11:59 PM PDT 24
Peak memory 204816 kb
Host smart-51dd1208-3b6e-4ecb-afd5-63dec3ac63e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760330426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2760330426
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1932919289
Short name T90
Test name
Test status
Simulation time 133012037 ps
CPU time 1 seconds
Started Jul 04 05:11:54 PM PDT 24
Finished Jul 04 05:11:55 PM PDT 24
Peak memory 204776 kb
Host smart-6adfa6cc-623c-481a-acdd-a5f7e90787b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932919289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
932919289
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.305103733
Short name T370
Test name
Test status
Simulation time 36732377 ps
CPU time 0.72 seconds
Started Jul 04 05:11:56 PM PDT 24
Finished Jul 04 05:11:57 PM PDT 24
Peak memory 204632 kb
Host smart-f9c5d28a-9c7c-4820-9e47-184e000957a5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305103733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.305103733
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1078001851
Short name T286
Test name
Test status
Simulation time 33563609 ps
CPU time 0.67 seconds
Started Jul 04 05:11:56 PM PDT 24
Finished Jul 04 05:11:57 PM PDT 24
Peak memory 204704 kb
Host smart-a7d4c807-d883-4082-9504-630782e8f41b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078001851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1078001851
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1623418404
Short name T373
Test name
Test status
Simulation time 236992951 ps
CPU time 6.43 seconds
Started Jul 04 05:11:53 PM PDT 24
Finished Jul 04 05:12:00 PM PDT 24
Peak memory 205196 kb
Host smart-fa4b7bb6-75f9-443b-a01f-8d848ba68b88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623418404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1623418404
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1216842546
Short name T301
Test name
Test status
Simulation time 194024447 ps
CPU time 3.33 seconds
Started Jul 04 05:11:52 PM PDT 24
Finished Jul 04 05:11:56 PM PDT 24
Peak memory 213352 kb
Host smart-693633c4-5c2b-46a4-8e40-69d895c0ac17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216842546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1216842546
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.259078485
Short name T397
Test name
Test status
Simulation time 3109803485 ps
CPU time 22.41 seconds
Started Jul 04 05:11:56 PM PDT 24
Finished Jul 04 05:12:19 PM PDT 24
Peak memory 213384 kb
Host smart-e14b11af-ecdd-4353-997f-3badcb8d689a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259078485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.259078485
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1458281340
Short name T406
Test name
Test status
Simulation time 261066574 ps
CPU time 2.55 seconds
Started Jul 04 05:11:54 PM PDT 24
Finished Jul 04 05:11:57 PM PDT 24
Peak memory 213428 kb
Host smart-88f3fc5c-1df1-440e-86fd-ec69c3ef5ea0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458281340 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1458281340
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.347509141
Short name T119
Test name
Test status
Simulation time 93754009 ps
CPU time 1.34 seconds
Started Jul 04 05:11:54 PM PDT 24
Finished Jul 04 05:11:56 PM PDT 24
Peak memory 213272 kb
Host smart-14dee165-8b01-496c-beac-713d0fe18368
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347509141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.347509141
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.651792543
Short name T402
Test name
Test status
Simulation time 47858900360 ps
CPU time 24.99 seconds
Started Jul 04 05:11:53 PM PDT 24
Finished Jul 04 05:12:18 PM PDT 24
Peak memory 205272 kb
Host smart-b4253959-397c-4d98-a591-78b88139a19c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651792543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r
v_dm_jtag_dmi_csr_bit_bash.651792543
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2664955173
Short name T316
Test name
Test status
Simulation time 5761422692 ps
CPU time 15.34 seconds
Started Jul 04 05:12:02 PM PDT 24
Finished Jul 04 05:12:18 PM PDT 24
Peak memory 204940 kb
Host smart-f9b80124-0fe7-4bcb-b1b4-4828be24d208
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664955173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
664955173
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1125117658
Short name T351
Test name
Test status
Simulation time 202202826 ps
CPU time 0.97 seconds
Started Jul 04 05:11:54 PM PDT 24
Finished Jul 04 05:11:56 PM PDT 24
Peak memory 204756 kb
Host smart-39b39bb5-8783-4387-b815-1f5a1ac19eba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125117658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
125117658
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1181958788
Short name T123
Test name
Test status
Simulation time 513736276 ps
CPU time 7.88 seconds
Started Jul 04 05:11:54 PM PDT 24
Finished Jul 04 05:12:02 PM PDT 24
Peak memory 205164 kb
Host smart-c0f6d15f-1b9c-42de-a506-b961bb0dd7ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181958788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1181958788
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1125019400
Short name T371
Test name
Test status
Simulation time 1247627201 ps
CPU time 5.8 seconds
Started Jul 04 05:11:52 PM PDT 24
Finished Jul 04 05:11:58 PM PDT 24
Peak memory 213328 kb
Host smart-477c29ce-c588-4eb0-a690-f2e07d8c93cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125019400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1125019400
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2701681199
Short name T378
Test name
Test status
Simulation time 171706310 ps
CPU time 5.09 seconds
Started Jul 04 05:11:52 PM PDT 24
Finished Jul 04 05:11:58 PM PDT 24
Peak memory 219528 kb
Host smart-d02f117a-c244-4386-8a68-6a2da27467ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701681199 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2701681199
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1119816985
Short name T367
Test name
Test status
Simulation time 171336540 ps
CPU time 1.76 seconds
Started Jul 04 05:11:57 PM PDT 24
Finished Jul 04 05:11:59 PM PDT 24
Peak memory 213388 kb
Host smart-10c1adc1-a8c6-41ed-ae97-457ac5673267
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119816985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1119816985
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.130514911
Short name T309
Test name
Test status
Simulation time 40539348197 ps
CPU time 100.47 seconds
Started Jul 04 05:11:52 PM PDT 24
Finished Jul 04 05:13:34 PM PDT 24
Peak memory 205028 kb
Host smart-bdae2155-838e-4eb7-9768-5e362cef64e7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130514911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
v_dm_jtag_dmi_csr_bit_bash.130514911
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1285355377
Short name T399
Test name
Test status
Simulation time 6856284690 ps
CPU time 10.25 seconds
Started Jul 04 05:11:56 PM PDT 24
Finished Jul 04 05:12:07 PM PDT 24
Peak memory 205008 kb
Host smart-e457d0e1-0bd4-4e65-977c-d9335ca68236
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285355377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
285355377
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1934995199
Short name T414
Test name
Test status
Simulation time 828164029 ps
CPU time 1.47 seconds
Started Jul 04 05:11:51 PM PDT 24
Finished Jul 04 05:11:53 PM PDT 24
Peak memory 204792 kb
Host smart-ff21de54-86ea-41fe-85d2-0df2c98ec077
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934995199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
934995199
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3627603831
Short name T369
Test name
Test status
Simulation time 1415850152 ps
CPU time 7.41 seconds
Started Jul 04 05:12:02 PM PDT 24
Finished Jul 04 05:12:10 PM PDT 24
Peak memory 205116 kb
Host smart-4e9be379-37b3-4e96-ab7f-578a4b2f82b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627603831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3627603831
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2861873134
Short name T409
Test name
Test status
Simulation time 415136803 ps
CPU time 2.64 seconds
Started Jul 04 05:11:52 PM PDT 24
Finished Jul 04 05:11:56 PM PDT 24
Peak memory 213592 kb
Host smart-75d9c231-2a2c-4f14-bbf3-b5d36504d26c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861873134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2861873134
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2606517145
Short name T64
Test name
Test status
Simulation time 931634228 ps
CPU time 10.61 seconds
Started Jul 04 05:11:51 PM PDT 24
Finished Jul 04 05:12:02 PM PDT 24
Peak memory 213372 kb
Host smart-7c723f44-8f1b-413b-8b09-96381c7e163d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606517145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2606517145
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1669411558
Short name T317
Test name
Test status
Simulation time 1077753339 ps
CPU time 3.68 seconds
Started Jul 04 05:12:00 PM PDT 24
Finished Jul 04 05:12:04 PM PDT 24
Peak memory 219184 kb
Host smart-edaca379-7680-4f12-9e19-45a3bdf85bec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669411558 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1669411558
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.119389299
Short name T104
Test name
Test status
Simulation time 180885824 ps
CPU time 2.31 seconds
Started Jul 04 05:12:01 PM PDT 24
Finished Jul 04 05:12:03 PM PDT 24
Peak memory 213332 kb
Host smart-d46d22b9-ce4f-4b9c-a131-d10c38d86235
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119389299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.119389299
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.610668760
Short name T310
Test name
Test status
Simulation time 1577548369 ps
CPU time 2.07 seconds
Started Jul 04 05:11:58 PM PDT 24
Finished Jul 04 05:12:01 PM PDT 24
Peak memory 204948 kb
Host smart-ef9cb5e4-444f-40ec-9d18-13612ebe544a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610668760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r
v_dm_jtag_dmi_csr_bit_bash.610668760
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3696890090
Short name T313
Test name
Test status
Simulation time 2799330244 ps
CPU time 6.61 seconds
Started Jul 04 05:12:02 PM PDT 24
Finished Jul 04 05:12:09 PM PDT 24
Peak memory 204944 kb
Host smart-af53de1a-a2da-436e-b15c-e2946093b888
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696890090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
696890090
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1681563270
Short name T424
Test name
Test status
Simulation time 233500399 ps
CPU time 0.84 seconds
Started Jul 04 05:11:53 PM PDT 24
Finished Jul 04 05:11:54 PM PDT 24
Peak memory 204796 kb
Host smart-6ac02679-2059-4bb2-a299-e8baba9b055b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681563270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
681563270
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1869868387
Short name T121
Test name
Test status
Simulation time 263040432 ps
CPU time 4.13 seconds
Started Jul 04 05:12:06 PM PDT 24
Finished Jul 04 05:12:11 PM PDT 24
Peak memory 205020 kb
Host smart-2d3c6966-854b-4e4f-937d-84736b8de063
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869868387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1869868387
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.362978547
Short name T357
Test name
Test status
Simulation time 555769036 ps
CPU time 3.44 seconds
Started Jul 04 05:11:58 PM PDT 24
Finished Jul 04 05:12:02 PM PDT 24
Peak memory 213404 kb
Host smart-ef0e3121-c58e-424d-838e-6b091942f313
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362978547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.362978547
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3514843043
Short name T191
Test name
Test status
Simulation time 8020247299 ps
CPU time 22.23 seconds
Started Jul 04 05:11:56 PM PDT 24
Finished Jul 04 05:12:19 PM PDT 24
Peak memory 213396 kb
Host smart-dc877360-e3f7-4400-9aae-e51b361e26f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514843043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3514843043
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.676735957
Short name T374
Test name
Test status
Simulation time 2480424025 ps
CPU time 5.55 seconds
Started Jul 04 05:12:01 PM PDT 24
Finished Jul 04 05:12:07 PM PDT 24
Peak memory 213384 kb
Host smart-e06fa32d-2070-4625-99c0-1b39dafc94de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676735957 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.676735957
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2023467115
Short name T315
Test name
Test status
Simulation time 291074737 ps
CPU time 2.44 seconds
Started Jul 04 05:12:06 PM PDT 24
Finished Jul 04 05:12:09 PM PDT 24
Peak memory 213188 kb
Host smart-d3d9e425-0e88-4433-8c20-0b9d6276dc7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023467115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2023467115
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2322085860
Short name T412
Test name
Test status
Simulation time 23771020334 ps
CPU time 25.7 seconds
Started Jul 04 05:12:02 PM PDT 24
Finished Jul 04 05:12:28 PM PDT 24
Peak memory 205004 kb
Host smart-14674a3e-1187-48da-8288-f9e7da1e95b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322085860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.2322085860
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3039355942
Short name T284
Test name
Test status
Simulation time 13341435211 ps
CPU time 13.27 seconds
Started Jul 04 05:12:01 PM PDT 24
Finished Jul 04 05:12:15 PM PDT 24
Peak memory 205032 kb
Host smart-3c152d6d-eca9-4083-a960-2e7c7c8f4f31
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039355942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
039355942
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1350904112
Short name T326
Test name
Test status
Simulation time 131832095 ps
CPU time 1.12 seconds
Started Jul 04 05:12:02 PM PDT 24
Finished Jul 04 05:12:03 PM PDT 24
Peak memory 204704 kb
Host smart-a422c1dd-df0e-4842-a3fc-7ebdd4698484
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350904112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1
350904112
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3976226359
Short name T137
Test name
Test status
Simulation time 979606577 ps
CPU time 7.74 seconds
Started Jul 04 05:12:06 PM PDT 24
Finished Jul 04 05:12:14 PM PDT 24
Peak memory 205000 kb
Host smart-391af0ec-d3f6-422e-8c9f-be9095fcfe3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976226359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.3976226359
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2267267777
Short name T359
Test name
Test status
Simulation time 554253372 ps
CPU time 6.19 seconds
Started Jul 04 05:12:04 PM PDT 24
Finished Jul 04 05:12:10 PM PDT 24
Peak memory 213332 kb
Host smart-7271fd0f-e9c6-495f-8915-45c0985064cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267267777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2267267777
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.753634275
Short name T189
Test name
Test status
Simulation time 3796093686 ps
CPU time 10.26 seconds
Started Jul 04 05:12:06 PM PDT 24
Finished Jul 04 05:12:17 PM PDT 24
Peak memory 213424 kb
Host smart-58f3c604-36e6-4f18-865d-969a90e83594
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753634275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.753634275
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.323465503
Short name T336
Test name
Test status
Simulation time 1020841384 ps
CPU time 4.83 seconds
Started Jul 04 05:12:01 PM PDT 24
Finished Jul 04 05:12:07 PM PDT 24
Peak memory 221424 kb
Host smart-e22ea62a-3c5e-40d1-bf6b-5d467ab737a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323465503 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.323465503
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1103862790
Short name T101
Test name
Test status
Simulation time 371233160 ps
CPU time 2.37 seconds
Started Jul 04 05:12:02 PM PDT 24
Finished Jul 04 05:12:05 PM PDT 24
Peak memory 213288 kb
Host smart-5c814f84-08bc-421b-a49f-0bd12ddee8f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103862790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1103862790
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2955278738
Short name T344
Test name
Test status
Simulation time 60080031819 ps
CPU time 25.59 seconds
Started Jul 04 05:12:00 PM PDT 24
Finished Jul 04 05:12:26 PM PDT 24
Peak memory 205004 kb
Host smart-b2e7da4a-c7d9-4677-b41a-e89bc5c291a0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955278738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2955278738
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.567169442
Short name T423
Test name
Test status
Simulation time 6215222104 ps
CPU time 9.39 seconds
Started Jul 04 05:12:02 PM PDT 24
Finished Jul 04 05:12:12 PM PDT 24
Peak memory 204980 kb
Host smart-2515fb44-091f-44b0-b5bd-5e14e56d51b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567169442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.567169442
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1265978734
Short name T405
Test name
Test status
Simulation time 179739307 ps
CPU time 1.17 seconds
Started Jul 04 05:12:01 PM PDT 24
Finished Jul 04 05:12:03 PM PDT 24
Peak memory 204720 kb
Host smart-5485dac4-9b89-4547-9807-69c2c560b4dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265978734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
265978734
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3396729718
Short name T67
Test name
Test status
Simulation time 349643012 ps
CPU time 3.77 seconds
Started Jul 04 05:12:03 PM PDT 24
Finished Jul 04 05:12:07 PM PDT 24
Peak memory 205000 kb
Host smart-04eac5c9-be70-4081-aaaa-e809b25d9343
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396729718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3396729718
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.875347975
Short name T422
Test name
Test status
Simulation time 16864474855 ps
CPU time 45.68 seconds
Started Jul 04 05:12:04 PM PDT 24
Finished Jul 04 05:12:50 PM PDT 24
Peak memory 221584 kb
Host smart-c3b21903-9792-4083-bbb7-588c30cad161
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875347975 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.875347975
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2589433536
Short name T331
Test name
Test status
Simulation time 54690830 ps
CPU time 2.37 seconds
Started Jul 04 05:12:03 PM PDT 24
Finished Jul 04 05:12:05 PM PDT 24
Peak memory 213300 kb
Host smart-25a0cb73-bab1-4d9f-9147-bc5bf39670c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589433536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2589433536
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.733927958
Short name T392
Test name
Test status
Simulation time 1924029336 ps
CPU time 17.86 seconds
Started Jul 04 05:12:02 PM PDT 24
Finished Jul 04 05:12:21 PM PDT 24
Peak memory 213360 kb
Host smart-d8b274b1-e635-4563-b92a-814bb6e903d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733927958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.733927958
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2257662498
Short name T62
Test name
Test status
Simulation time 50467845 ps
CPU time 0.79 seconds
Started Jul 04 05:13:11 PM PDT 24
Finished Jul 04 05:13:12 PM PDT 24
Peak memory 205052 kb
Host smart-9b23f621-47d4-401a-bd8a-7acfc0c254c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257662498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2257662498
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.588776463
Short name T11
Test name
Test status
Simulation time 389079090 ps
CPU time 0.97 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:12:52 PM PDT 24
Peak memory 205000 kb
Host smart-5f381eeb-4945-4fb8-a58a-5d93dccc8533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588776463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.588776463
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2559979214
Short name T34
Test name
Test status
Simulation time 132640172 ps
CPU time 0.98 seconds
Started Jul 04 05:12:49 PM PDT 24
Finished Jul 04 05:12:50 PM PDT 24
Peak memory 204996 kb
Host smart-cc562c2e-2295-4356-a63b-cd8dbfcabdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559979214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2559979214
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1170724377
Short name T224
Test name
Test status
Simulation time 389159612 ps
CPU time 1.22 seconds
Started Jul 04 05:12:54 PM PDT 24
Finished Jul 04 05:12:55 PM PDT 24
Peak memory 204984 kb
Host smart-62364cba-34f9-426f-ac1e-3fadb10630b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170724377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1170724377
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.4147905174
Short name T157
Test name
Test status
Simulation time 12251797994 ps
CPU time 21.37 seconds
Started Jul 04 05:12:50 PM PDT 24
Finished Jul 04 05:13:12 PM PDT 24
Peak memory 221744 kb
Host smart-3675e941-4753-429e-813c-af480cb01cd0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147905174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.4147905174
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2514477283
Short name T165
Test name
Test status
Simulation time 586682007 ps
CPU time 1.21 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:12:53 PM PDT 24
Peak memory 204948 kb
Host smart-011810d6-73d4-411e-ba8c-512317138816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514477283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2514477283
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3086159633
Short name T212
Test name
Test status
Simulation time 279698657 ps
CPU time 1.2 seconds
Started Jul 04 05:12:54 PM PDT 24
Finished Jul 04 05:12:55 PM PDT 24
Peak memory 204980 kb
Host smart-fc4386b9-6517-4346-829b-a9f9d3cc7192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086159633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3086159633
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4143022239
Short name T254
Test name
Test status
Simulation time 1003278493 ps
CPU time 3.48 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:13:11 PM PDT 24
Peak memory 204960 kb
Host smart-ec9fc4a2-1d46-46d8-9c1d-0215029719f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143022239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.4143022239
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.959956783
Short name T82
Test name
Test status
Simulation time 2172834124 ps
CPU time 3.15 seconds
Started Jul 04 05:13:08 PM PDT 24
Finished Jul 04 05:13:12 PM PDT 24
Peak memory 204896 kb
Host smart-1d5c94a1-c857-4541-9eaa-e290bb39abf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959956783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.959956783
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.719055581
Short name T78
Test name
Test status
Simulation time 2290975822 ps
CPU time 5.8 seconds
Started Jul 04 05:13:04 PM PDT 24
Finished Jul 04 05:13:10 PM PDT 24
Peak memory 205104 kb
Host smart-edbfa9d8-d3e3-4d00-9e6c-53863e948bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719055581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.719055581
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.4147421967
Short name T164
Test name
Test status
Simulation time 313020794 ps
CPU time 0.87 seconds
Started Jul 04 05:13:04 PM PDT 24
Finished Jul 04 05:13:05 PM PDT 24
Peak memory 204976 kb
Host smart-4f04ea2a-3ec5-43a4-a642-a4611df40a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147421967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.4147421967
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2854377588
Short name T196
Test name
Test status
Simulation time 418710610 ps
CPU time 1.44 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:12:52 PM PDT 24
Peak memory 205060 kb
Host smart-398a2fa3-a2f6-4c46-bdd6-5bc267c9c422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854377588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2854377588
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.4280060355
Short name T29
Test name
Test status
Simulation time 146384923 ps
CPU time 0.77 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:13:09 PM PDT 24
Peak memory 205056 kb
Host smart-5599b442-c5d4-4085-ae8e-ff09608e2990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280060355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.4280060355
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3077497503
Short name T76
Test name
Test status
Simulation time 897849537 ps
CPU time 1.69 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:09 PM PDT 24
Peak memory 229556 kb
Host smart-e1591039-4db4-4af8-9505-707b084b4e7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077497503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3077497503
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3001955140
Short name T267
Test name
Test status
Simulation time 1390989191 ps
CPU time 1.5 seconds
Started Jul 04 05:12:49 PM PDT 24
Finished Jul 04 05:12:51 PM PDT 24
Peak memory 205016 kb
Host smart-0c4415e4-48e9-4d4f-990a-fc91dac3d399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001955140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3001955140
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1428946321
Short name T41
Test name
Test status
Simulation time 97635329 ps
CPU time 0.92 seconds
Started Jul 04 05:13:37 PM PDT 24
Finished Jul 04 05:13:38 PM PDT 24
Peak memory 205040 kb
Host smart-fdab5279-2a5d-48ea-b43a-d810e99acf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428946321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1428946321
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.108652827
Short name T239
Test name
Test status
Simulation time 38026064 ps
CPU time 0.81 seconds
Started Jul 04 05:13:37 PM PDT 24
Finished Jul 04 05:13:39 PM PDT 24
Peak memory 205056 kb
Host smart-9ea483b4-6b7d-482d-8929-e675b30f1907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108652827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.108652827
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2227022073
Short name T30
Test name
Test status
Simulation time 13300755600 ps
CPU time 39.08 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:46 PM PDT 24
Peak memory 213536 kb
Host smart-bfe43bb7-e124-46bf-9d35-b8359804a220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227022073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2227022073
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1453446750
Short name T21
Test name
Test status
Simulation time 1470155390 ps
CPU time 1.79 seconds
Started Jul 04 05:13:05 PM PDT 24
Finished Jul 04 05:13:07 PM PDT 24
Peak memory 205020 kb
Host smart-8d7e7162-5c50-4e0e-b83d-19a7768ab6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453446750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1453446750
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1333481989
Short name T9
Test name
Test status
Simulation time 326778056 ps
CPU time 1.44 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:08 PM PDT 24
Peak memory 205044 kb
Host smart-accd6a75-9469-4c0d-a1e1-fabdc24d8bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333481989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1333481989
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3367051471
Short name T192
Test name
Test status
Simulation time 229268426 ps
CPU time 0.98 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:07 PM PDT 24
Peak memory 205048 kb
Host smart-8083f278-c226-4b93-a080-4d5ce66a0c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367051471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3367051471
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.84544314
Short name T32
Test name
Test status
Simulation time 96371556 ps
CPU time 0.79 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:13:09 PM PDT 24
Peak memory 204928 kb
Host smart-f15bf5d1-1248-49fa-b650-5ff3d1e35507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84544314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.84544314
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2361262085
Short name T77
Test name
Test status
Simulation time 2986920967 ps
CPU time 2.56 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:09 PM PDT 24
Peak memory 213560 kb
Host smart-3969bbdc-8cf1-474b-9a5c-b82aeace6451
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2361262085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2361262085
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2736940628
Short name T193
Test name
Test status
Simulation time 2173920507 ps
CPU time 2.31 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:13:10 PM PDT 24
Peak memory 205100 kb
Host smart-54f21a31-8c02-4eaf-887e-7e8ec81439f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736940628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2736940628
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2115310252
Short name T269
Test name
Test status
Simulation time 767361193 ps
CPU time 2.49 seconds
Started Jul 04 05:13:05 PM PDT 24
Finished Jul 04 05:13:08 PM PDT 24
Peak memory 204968 kb
Host smart-29975bce-d055-43c2-8c97-2b5adcfcd645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115310252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2115310252
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2847453645
Short name T258
Test name
Test status
Simulation time 1603299878 ps
CPU time 4.92 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:13:13 PM PDT 24
Peak memory 204952 kb
Host smart-c1c3fcf7-8778-496f-ba41-5d59de5c3c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847453645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2847453645
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.4113775828
Short name T266
Test name
Test status
Simulation time 1641362984 ps
CPU time 2.07 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:10 PM PDT 24
Peak memory 204928 kb
Host smart-0a54f554-0cf2-47c6-8132-7e36578b87c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113775828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.4113775828
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.4221774318
Short name T277
Test name
Test status
Simulation time 6457783736 ps
CPU time 17.58 seconds
Started Jul 04 05:13:05 PM PDT 24
Finished Jul 04 05:13:22 PM PDT 24
Peak memory 205340 kb
Host smart-e40f9201-d02b-43db-80f3-a81d22071550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221774318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.4221774318
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1102067555
Short name T163
Test name
Test status
Simulation time 160688619 ps
CPU time 1.08 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:08 PM PDT 24
Peak memory 205040 kb
Host smart-1c4c5f5b-b200-4a29-bb9a-37cfdff5354a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102067555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1102067555
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2685935140
Short name T195
Test name
Test status
Simulation time 1208343089 ps
CPU time 3.74 seconds
Started Jul 04 05:13:05 PM PDT 24
Finished Jul 04 05:13:09 PM PDT 24
Peak memory 205052 kb
Host smart-b4154f64-2d41-4604-a72e-e1960649d24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685935140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2685935140
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1254750160
Short name T275
Test name
Test status
Simulation time 1052721989 ps
CPU time 1.56 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:08 PM PDT 24
Peak memory 205232 kb
Host smart-e46ccf26-254e-428f-ae77-bfefc8dc3227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254750160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1254750160
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3000360949
Short name T20
Test name
Test status
Simulation time 3082985919 ps
CPU time 2.92 seconds
Started Jul 04 05:13:05 PM PDT 24
Finished Jul 04 05:13:08 PM PDT 24
Peak memory 205116 kb
Host smart-faabbf7f-da80-463e-a217-2ca0bfaf6711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000360949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3000360949
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.2614734381
Short name T47
Test name
Test status
Simulation time 1200145180 ps
CPU time 4.01 seconds
Started Jul 04 05:13:34 PM PDT 24
Finished Jul 04 05:13:38 PM PDT 24
Peak memory 205012 kb
Host smart-ae7687fa-0589-408a-94ec-e47bdc8bd9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614734381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.2614734381
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1084730123
Short name T36
Test name
Test status
Simulation time 110852208 ps
CPU time 0.79 seconds
Started Jul 04 05:13:34 PM PDT 24
Finished Jul 04 05:13:35 PM PDT 24
Peak memory 213280 kb
Host smart-d933af1b-5f54-4a7f-bb44-9710bf0223f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084730123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1084730123
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1243069135
Short name T240
Test name
Test status
Simulation time 3474283531 ps
CPU time 6.03 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:13 PM PDT 24
Peak memory 205564 kb
Host smart-50b572ea-2a81-484f-8e7c-397fb6b8f0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243069135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1243069135
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2731605518
Short name T270
Test name
Test status
Simulation time 829454988 ps
CPU time 3.14 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:10 PM PDT 24
Peak memory 204996 kb
Host smart-92bb1b22-9d70-443f-989c-d4ba563a93c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731605518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2731605518
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3123272218
Short name T209
Test name
Test status
Simulation time 197878672 ps
CPU time 0.98 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:13:51 PM PDT 24
Peak memory 205080 kb
Host smart-9d246678-e1dd-4968-839e-aa3a54180a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123272218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3123272218
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3594967075
Short name T71
Test name
Test status
Simulation time 5522728170 ps
CPU time 3.66 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:13:54 PM PDT 24
Peak memory 215112 kb
Host smart-12890044-f873-4f4e-a66b-3a8424728bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594967075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3594967075
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2927487526
Short name T264
Test name
Test status
Simulation time 75765040 ps
CPU time 0.72 seconds
Started Jul 04 05:13:53 PM PDT 24
Finished Jul 04 05:13:55 PM PDT 24
Peak memory 205028 kb
Host smart-1d6740c2-3d30-4571-be3e-c3ec979a576c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927487526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2927487526
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.437392190
Short name T216
Test name
Test status
Simulation time 9545091229 ps
CPU time 15.81 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:14:10 PM PDT 24
Peak memory 213520 kb
Host smart-f7b8044c-4bfd-4995-8aa0-bc0515980293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437392190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.437392190
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1279075388
Short name T207
Test name
Test status
Simulation time 1296818890 ps
CPU time 1.78 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:13:50 PM PDT 24
Peak memory 205364 kb
Host smart-32171c2d-8cb5-4cc8-934d-757581e4e06e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279075388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1279075388
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1895616799
Short name T147
Test name
Test status
Simulation time 1732644062 ps
CPU time 2.9 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:54 PM PDT 24
Peak memory 205304 kb
Host smart-0d909dae-c7f7-4eb0-a8d7-437e2a49a791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895616799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1895616799
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.1689907978
Short name T98
Test name
Test status
Simulation time 6227081505 ps
CPU time 4.65 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:13:58 PM PDT 24
Peak memory 205312 kb
Host smart-3becdcb8-f4bc-4147-bebe-290cc93c983b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689907978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1689907978
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.397630276
Short name T70
Test name
Test status
Simulation time 65890961 ps
CPU time 0.69 seconds
Started Jul 04 05:13:45 PM PDT 24
Finished Jul 04 05:13:46 PM PDT 24
Peak memory 205032 kb
Host smart-e53bf214-5d90-4ed0-95ea-88ff570f5524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397630276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.397630276
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2914235227
Short name T214
Test name
Test status
Simulation time 7300617244 ps
CPU time 7.67 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:14:02 PM PDT 24
Peak memory 213532 kb
Host smart-46ff41b8-73b7-46fd-9962-a7eb44b0501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914235227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2914235227
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.746119052
Short name T25
Test name
Test status
Simulation time 3527605564 ps
CPU time 6.04 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:13:54 PM PDT 24
Peak memory 213516 kb
Host smart-ad283c63-d7ce-4ff8-aa00-99f22320f653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746119052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.746119052
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3471941965
Short name T272
Test name
Test status
Simulation time 3985214136 ps
CPU time 6.24 seconds
Started Jul 04 05:13:53 PM PDT 24
Finished Jul 04 05:14:01 PM PDT 24
Peak memory 205400 kb
Host smart-a032952f-4473-4611-88a0-67c8083b25a2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471941965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3471941965
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.856215356
Short name T22
Test name
Test status
Simulation time 3359377489 ps
CPU time 8.69 seconds
Started Jul 04 05:13:54 PM PDT 24
Finished Jul 04 05:14:03 PM PDT 24
Peak memory 205284 kb
Host smart-d348f145-a8a5-45de-bc40-0288e1739bb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856215356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.856215356
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1214282264
Short name T263
Test name
Test status
Simulation time 42054372 ps
CPU time 0.76 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:13:49 PM PDT 24
Peak memory 205048 kb
Host smart-ee35b959-c3a3-46ca-bbc0-0c134abd3ae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214282264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1214282264
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2664232528
Short name T217
Test name
Test status
Simulation time 11209574396 ps
CPU time 28.9 seconds
Started Jul 04 05:13:45 PM PDT 24
Finished Jul 04 05:14:15 PM PDT 24
Peak memory 213620 kb
Host smart-f1a0f2d7-8fb8-4d7f-bb24-1836cfcd712c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664232528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2664232528
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.249938147
Short name T251
Test name
Test status
Simulation time 5444127858 ps
CPU time 3.68 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:13:51 PM PDT 24
Peak memory 215848 kb
Host smart-07661265-2dd6-4e65-b688-5e10b44d28d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249938147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.249938147
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3989002695
Short name T72
Test name
Test status
Simulation time 2598873262 ps
CPU time 4.81 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:13:54 PM PDT 24
Peak memory 213584 kb
Host smart-39601ce5-39f5-4ad1-9c6e-58b56d54c84f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3989002695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3989002695
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2118801795
Short name T271
Test name
Test status
Simulation time 2398198229 ps
CPU time 2.76 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:54 PM PDT 24
Peak memory 213592 kb
Host smart-0b772f60-b01b-4f72-b24f-5d5d89309f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118801795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2118801795
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.1564691735
Short name T51
Test name
Test status
Simulation time 1272067411 ps
CPU time 1.38 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:13:51 PM PDT 24
Peak memory 205204 kb
Host smart-5127751c-9f86-4cc0-b514-d5566722cd42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564691735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1564691735
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3342809952
Short name T244
Test name
Test status
Simulation time 90579245 ps
CPU time 0.86 seconds
Started Jul 04 05:13:59 PM PDT 24
Finished Jul 04 05:14:00 PM PDT 24
Peak memory 205044 kb
Host smart-28cc3995-c84c-4fbe-887d-f344ef5e6b9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342809952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3342809952
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1490113210
Short name T159
Test name
Test status
Simulation time 10382712292 ps
CPU time 6.5 seconds
Started Jul 04 05:13:58 PM PDT 24
Finished Jul 04 05:14:05 PM PDT 24
Peak memory 213492 kb
Host smart-3a10e8d9-e098-45cd-9df9-0a1e4b6743f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490113210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1490113210
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1122428820
Short name T202
Test name
Test status
Simulation time 2706907897 ps
CPU time 3.49 seconds
Started Jul 04 05:13:57 PM PDT 24
Finished Jul 04 05:14:01 PM PDT 24
Peak memory 214568 kb
Host smart-240eb1bf-807e-47af-8bc9-f5c394851d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122428820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1122428820
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2209098185
Short name T221
Test name
Test status
Simulation time 5548370857 ps
CPU time 15.72 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:14:09 PM PDT 24
Peak memory 213588 kb
Host smart-2748397f-cdaf-480e-916a-1f1dd79f0381
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2209098185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.2209098185
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3262559252
Short name T203
Test name
Test status
Simulation time 47026041 ps
CPU time 0.7 seconds
Started Jul 04 05:13:59 PM PDT 24
Finished Jul 04 05:13:59 PM PDT 24
Peak memory 204992 kb
Host smart-f7ca6a4f-c5f0-496b-841b-c87fdd71dd96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262559252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3262559252
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2536793037
Short name T247
Test name
Test status
Simulation time 4517918895 ps
CPU time 4.86 seconds
Started Jul 04 05:14:06 PM PDT 24
Finished Jul 04 05:14:11 PM PDT 24
Peak memory 215600 kb
Host smart-a791d6f8-e5d2-403c-8dbd-295ad36049f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536793037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2536793037
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2637352826
Short name T237
Test name
Test status
Simulation time 5056134307 ps
CPU time 8.14 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:14:02 PM PDT 24
Peak memory 213568 kb
Host smart-1c309b5b-fc1c-436d-94cb-afcb919227d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637352826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2637352826
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.4134598743
Short name T158
Test name
Test status
Simulation time 1289286411 ps
CPU time 1.29 seconds
Started Jul 04 05:14:01 PM PDT 24
Finished Jul 04 05:14:02 PM PDT 24
Peak memory 205228 kb
Host smart-3431d6e7-f24f-4e1a-a4c1-db66f4d97151
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4134598743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.4134598743
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.4185288198
Short name T256
Test name
Test status
Simulation time 3103059291 ps
CPU time 6.86 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:58 PM PDT 24
Peak memory 205340 kb
Host smart-39316155-cadb-4248-a954-87d49166b148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185288198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.4185288198
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.3128259567
Short name T168
Test name
Test status
Simulation time 1014648485 ps
CPU time 3.26 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:55 PM PDT 24
Peak memory 205212 kb
Host smart-8e93e459-892e-4dc0-baeb-aa744ab5f778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128259567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3128259567
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3626541745
Short name T210
Test name
Test status
Simulation time 165929500 ps
CPU time 0.76 seconds
Started Jul 04 05:14:09 PM PDT 24
Finished Jul 04 05:14:10 PM PDT 24
Peak memory 204988 kb
Host smart-8a806475-da82-46b5-85a5-1c46c96777b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626541745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3626541745
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.34880675
Short name T245
Test name
Test status
Simulation time 4709590329 ps
CPU time 13.28 seconds
Started Jul 04 05:13:59 PM PDT 24
Finished Jul 04 05:14:13 PM PDT 24
Peak memory 205396 kb
Host smart-3aec5f1e-f454-4539-a0eb-92995dc7d0d9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34880675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl
_access.34880675
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.513625287
Short name T1
Test name
Test status
Simulation time 4978643611 ps
CPU time 14.25 seconds
Started Jul 04 05:13:53 PM PDT 24
Finished Jul 04 05:14:09 PM PDT 24
Peak memory 205368 kb
Host smart-c52a4778-668c-4461-a53f-f9b1bb6d1b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513625287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.513625287
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.341610586
Short name T45
Test name
Test status
Simulation time 4313346729 ps
CPU time 11.04 seconds
Started Jul 04 05:13:54 PM PDT 24
Finished Jul 04 05:14:06 PM PDT 24
Peak memory 213440 kb
Host smart-b15c7432-0f80-4609-ba24-8e97dfb78f50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341610586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.341610586
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3987878537
Short name T206
Test name
Test status
Simulation time 71882183 ps
CPU time 0.74 seconds
Started Jul 04 05:13:53 PM PDT 24
Finished Jul 04 05:13:55 PM PDT 24
Peak memory 205008 kb
Host smart-de683423-c7dc-4422-9601-7c4958a6b8f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987878537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3987878537
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.482151557
Short name T227
Test name
Test status
Simulation time 1511227127 ps
CPU time 1.52 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:53 PM PDT 24
Peak memory 213532 kb
Host smart-ed1920d1-6f13-4962-8042-e39123f23ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482151557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.482151557
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.789339966
Short name T238
Test name
Test status
Simulation time 3672847251 ps
CPU time 4.28 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:13:54 PM PDT 24
Peak memory 213524 kb
Host smart-13715763-b77a-4576-9c40-f4d83181ebf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789339966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.789339966
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1711955515
Short name T79
Test name
Test status
Simulation time 1862524422 ps
CPU time 6 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:14:00 PM PDT 24
Peak memory 205328 kb
Host smart-fb75250d-5e6b-480a-9217-615ad05b72be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711955515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1711955515
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.124768616
Short name T260
Test name
Test status
Simulation time 130047177 ps
CPU time 0.92 seconds
Started Jul 04 05:14:06 PM PDT 24
Finished Jul 04 05:14:07 PM PDT 24
Peak memory 205048 kb
Host smart-fa70aaa5-d1fa-4aaa-924b-df8cf84fe786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124768616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.124768616
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.4028459076
Short name T276
Test name
Test status
Simulation time 2288179528 ps
CPU time 4.16 seconds
Started Jul 04 05:13:56 PM PDT 24
Finished Jul 04 05:14:00 PM PDT 24
Peak memory 213544 kb
Host smart-3d8054f6-2e02-45eb-a356-2f439ebddca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028459076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.4028459076
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1001992416
Short name T142
Test name
Test status
Simulation time 1104885204 ps
CPU time 1.81 seconds
Started Jul 04 05:14:01 PM PDT 24
Finished Jul 04 05:14:03 PM PDT 24
Peak memory 213392 kb
Host smart-563abfa9-389f-4c20-96c4-b00f88fa2ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001992416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1001992416
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3582072140
Short name T108
Test name
Test status
Simulation time 4998588144 ps
CPU time 5.94 seconds
Started Jul 04 05:13:59 PM PDT 24
Finished Jul 04 05:14:05 PM PDT 24
Peak memory 213580 kb
Host smart-6ebdbfbf-c965-4773-b5b5-b8df84c745c0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3582072140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.3582072140
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1828115304
Short name T223
Test name
Test status
Simulation time 1680579859 ps
CPU time 1.91 seconds
Started Jul 04 05:14:09 PM PDT 24
Finished Jul 04 05:14:11 PM PDT 24
Peak memory 213488 kb
Host smart-258c1496-b49a-4794-9b39-e5793b2edb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828115304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1828115304
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.481843506
Short name T201
Test name
Test status
Simulation time 62271945 ps
CPU time 0.8 seconds
Started Jul 04 05:13:57 PM PDT 24
Finished Jul 04 05:13:58 PM PDT 24
Peak memory 204964 kb
Host smart-a2799dbe-fbd8-4f2c-9ab3-4faa1928eae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481843506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.481843506
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1861858424
Short name T154
Test name
Test status
Simulation time 2254797606 ps
CPU time 4.24 seconds
Started Jul 04 05:13:58 PM PDT 24
Finished Jul 04 05:14:02 PM PDT 24
Peak memory 213900 kb
Host smart-128725eb-b96f-44be-b69c-2eb5d9196179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861858424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1861858424
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.414740411
Short name T166
Test name
Test status
Simulation time 5565295510 ps
CPU time 15.98 seconds
Started Jul 04 05:14:09 PM PDT 24
Finished Jul 04 05:14:25 PM PDT 24
Peak memory 213580 kb
Host smart-4aaf2881-b16d-4a18-bb71-e7ce593432d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414740411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.414740411
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2336467402
Short name T252
Test name
Test status
Simulation time 939551434 ps
CPU time 1.57 seconds
Started Jul 04 05:14:09 PM PDT 24
Finished Jul 04 05:14:11 PM PDT 24
Peak memory 205264 kb
Host smart-fc4ccb12-d0ce-47fe-bb6d-5ea8ce29ca52
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2336467402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.2336467402
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2192139110
Short name T233
Test name
Test status
Simulation time 5857740673 ps
CPU time 15.23 seconds
Started Jul 04 05:13:58 PM PDT 24
Finished Jul 04 05:14:14 PM PDT 24
Peak memory 213836 kb
Host smart-449de328-f411-4f14-9d48-f2114d7a3a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192139110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2192139110
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.929593413
Short name T278
Test name
Test status
Simulation time 45288564 ps
CPU time 0.76 seconds
Started Jul 04 05:13:35 PM PDT 24
Finished Jul 04 05:13:37 PM PDT 24
Peak memory 205044 kb
Host smart-186ad9be-4568-4733-9ac8-ad80edd92af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929593413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.929593413
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.544760229
Short name T199
Test name
Test status
Simulation time 32270348869 ps
CPU time 26.92 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:14:04 PM PDT 24
Peak memory 219924 kb
Host smart-289ff476-5d35-49e1-a8ae-f03ad53803b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544760229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.544760229
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.426830726
Short name T250
Test name
Test status
Simulation time 2919446071 ps
CPU time 5.92 seconds
Started Jul 04 05:13:35 PM PDT 24
Finished Jul 04 05:13:42 PM PDT 24
Peak memory 213476 kb
Host smart-5ae08b90-200c-48f9-8023-15a47c25e46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426830726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.426830726
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.4159637583
Short name T61
Test name
Test status
Simulation time 2371454883 ps
CPU time 2.94 seconds
Started Jul 04 05:13:37 PM PDT 24
Finished Jul 04 05:13:41 PM PDT 24
Peak memory 213608 kb
Host smart-5f59cb35-6736-41b4-bccb-013cb5b083c1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159637583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.4159637583
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3184118980
Short name T28
Test name
Test status
Simulation time 376948372 ps
CPU time 1.61 seconds
Started Jul 04 05:13:35 PM PDT 24
Finished Jul 04 05:13:38 PM PDT 24
Peak memory 205060 kb
Host smart-f4f630f1-a287-4e1f-b121-d503f9845284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184118980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3184118980
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.439954112
Short name T87
Test name
Test status
Simulation time 6896654505 ps
CPU time 11.31 seconds
Started Jul 04 05:13:35 PM PDT 24
Finished Jul 04 05:13:47 PM PDT 24
Peak memory 213580 kb
Host smart-1441b84e-9010-404e-81a8-e3f910658899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439954112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.439954112
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2284752914
Short name T57
Test name
Test status
Simulation time 404262432 ps
CPU time 1.3 seconds
Started Jul 04 05:13:37 PM PDT 24
Finished Jul 04 05:13:39 PM PDT 24
Peak memory 229560 kb
Host smart-32411ddf-d36a-4959-8bd4-24dc37a781be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284752914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2284752914
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2222585299
Short name T261
Test name
Test status
Simulation time 67871336 ps
CPU time 0.86 seconds
Started Jul 04 05:14:02 PM PDT 24
Finished Jul 04 05:14:03 PM PDT 24
Peak memory 204964 kb
Host smart-e2d939a2-ca50-4eb8-a5f6-d7f3a83cef61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222585299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2222585299
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1128895281
Short name T236
Test name
Test status
Simulation time 154071702 ps
CPU time 1.03 seconds
Started Jul 04 05:14:03 PM PDT 24
Finished Jul 04 05:14:04 PM PDT 24
Peak memory 205044 kb
Host smart-12a953c9-7010-4488-b52c-bba48c879b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128895281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1128895281
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.3946181462
Short name T170
Test name
Test status
Simulation time 1141384779 ps
CPU time 4.2 seconds
Started Jul 04 05:14:00 PM PDT 24
Finished Jul 04 05:14:04 PM PDT 24
Peak memory 205180 kb
Host smart-10ef335a-76fe-4ccf-9bcc-e7191341a56f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946181462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3946181462
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3406696760
Short name T231
Test name
Test status
Simulation time 117020425 ps
CPU time 0.74 seconds
Started Jul 04 05:14:06 PM PDT 24
Finished Jul 04 05:14:07 PM PDT 24
Peak memory 205028 kb
Host smart-044bc8ca-31d9-460f-9a8f-259b504584c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406696760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3406696760
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.4079236657
Short name T213
Test name
Test status
Simulation time 128633027 ps
CPU time 0.72 seconds
Started Jul 04 05:14:12 PM PDT 24
Finished Jul 04 05:14:13 PM PDT 24
Peak memory 205028 kb
Host smart-d7c70bbd-0225-4f5f-965f-fca0749b7c0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079236657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.4079236657
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.2147572818
Short name T177
Test name
Test status
Simulation time 2895229213 ps
CPU time 4.96 seconds
Started Jul 04 05:14:12 PM PDT 24
Finished Jul 04 05:14:17 PM PDT 24
Peak memory 205252 kb
Host smart-8c7ab905-fe6d-4bc6-93c9-79096998562a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147572818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2147572818
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3798831539
Short name T54
Test name
Test status
Simulation time 26977231 ps
CPU time 0.76 seconds
Started Jul 04 05:14:12 PM PDT 24
Finished Jul 04 05:14:13 PM PDT 24
Peak memory 205024 kb
Host smart-65685b71-cebc-490b-b675-110165852bdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798831539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3798831539
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1367885334
Short name T200
Test name
Test status
Simulation time 47471180 ps
CPU time 0.81 seconds
Started Jul 04 05:14:12 PM PDT 24
Finished Jul 04 05:14:13 PM PDT 24
Peak memory 205028 kb
Host smart-2716317a-cec8-48fe-9c50-c173b4abb918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367885334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1367885334
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.320436166
Short name T111
Test name
Test status
Simulation time 37640931 ps
CPU time 0.75 seconds
Started Jul 04 05:14:16 PM PDT 24
Finished Jul 04 05:14:16 PM PDT 24
Peak memory 205052 kb
Host smart-ce499df7-abaa-483d-b8a6-f54057ef94cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320436166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.320436166
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1160963064
Short name T232
Test name
Test status
Simulation time 67220192 ps
CPU time 0.76 seconds
Started Jul 04 05:14:17 PM PDT 24
Finished Jul 04 05:14:18 PM PDT 24
Peak memory 205052 kb
Host smart-5dd80661-dc66-4cf2-8215-891a3d08e0d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160963064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1160963064
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.4104553016
Short name T109
Test name
Test status
Simulation time 133174930 ps
CPU time 0.79 seconds
Started Jul 04 05:14:16 PM PDT 24
Finished Jul 04 05:14:17 PM PDT 24
Peak memory 205024 kb
Host smart-400f2918-5918-4383-808e-d039846bf559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104553016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4104553016
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.985033717
Short name T229
Test name
Test status
Simulation time 143755666 ps
CPU time 1.03 seconds
Started Jul 04 05:14:20 PM PDT 24
Finished Jul 04 05:14:21 PM PDT 24
Peak memory 205052 kb
Host smart-35a6a422-e345-4a72-9706-c0a9925b89dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985033717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.985033717
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.2860947616
Short name T172
Test name
Test status
Simulation time 3683186839 ps
CPU time 5.75 seconds
Started Jul 04 05:14:17 PM PDT 24
Finished Jul 04 05:14:23 PM PDT 24
Peak memory 213404 kb
Host smart-c954e5de-8d8f-4e60-97b5-9ef4119b030f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860947616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.2860947616
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1123458936
Short name T255
Test name
Test status
Simulation time 46576860 ps
CPU time 0.79 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:13:50 PM PDT 24
Peak memory 205064 kb
Host smart-987e8fc2-7521-46bc-95c8-259928d398ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123458936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1123458936
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3645602675
Short name T59
Test name
Test status
Simulation time 49977600601 ps
CPU time 73 seconds
Started Jul 04 05:13:37 PM PDT 24
Finished Jul 04 05:14:51 PM PDT 24
Peak memory 213500 kb
Host smart-9bf8debc-b515-4188-927a-a0237eba46b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645602675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3645602675
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1949236882
Short name T230
Test name
Test status
Simulation time 1914868879 ps
CPU time 3.69 seconds
Started Jul 04 05:13:35 PM PDT 24
Finished Jul 04 05:13:39 PM PDT 24
Peak memory 213500 kb
Host smart-9d514d01-94af-48c7-8428-f6db2ff222a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949236882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1949236882
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2342918000
Short name T226
Test name
Test status
Simulation time 5639013850 ps
CPU time 11.92 seconds
Started Jul 04 05:13:37 PM PDT 24
Finished Jul 04 05:13:50 PM PDT 24
Peak memory 213592 kb
Host smart-30efcc89-872b-49c6-bfa8-e4c57fe519e8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2342918000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2342918000
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.671764872
Short name T215
Test name
Test status
Simulation time 73958395 ps
CPU time 0.86 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:13:38 PM PDT 24
Peak memory 205040 kb
Host smart-7a1816c6-a2ce-4659-9b06-14b4aab08e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671764872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.671764872
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.59234726
Short name T218
Test name
Test status
Simulation time 3870103362 ps
CPU time 3.66 seconds
Started Jul 04 05:13:35 PM PDT 24
Finished Jul 04 05:13:40 PM PDT 24
Peak memory 205444 kb
Host smart-bf185995-2b46-4bdf-93fb-b215391c531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59234726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.59234726
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2606433744
Short name T58
Test name
Test status
Simulation time 2293218745 ps
CPU time 1.4 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:13:38 PM PDT 24
Peak memory 229216 kb
Host smart-9e612671-4c30-4e3d-9d92-d668f3c7f8c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606433744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2606433744
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.1817991984
Short name T15
Test name
Test status
Simulation time 9006053600 ps
CPU time 8.33 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:13:45 PM PDT 24
Peak memory 213456 kb
Host smart-be22b00a-57ed-4a55-827e-f2ca51d2cd24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817991984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.1817991984
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.799393822
Short name T38
Test name
Test status
Simulation time 115861285 ps
CPU time 0.74 seconds
Started Jul 04 05:14:17 PM PDT 24
Finished Jul 04 05:14:18 PM PDT 24
Peak memory 205036 kb
Host smart-e64a23c4-c860-46a0-b76c-3e3fdacdccd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799393822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.799393822
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1807536551
Short name T234
Test name
Test status
Simulation time 109442424 ps
CPU time 0.78 seconds
Started Jul 04 05:14:17 PM PDT 24
Finished Jul 04 05:14:18 PM PDT 24
Peak memory 205028 kb
Host smart-230a3db8-84ee-44c1-9db8-9d608241b45d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807536551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1807536551
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.3384787129
Short name T35
Test name
Test status
Simulation time 15234412176 ps
CPU time 19.76 seconds
Started Jul 04 05:14:17 PM PDT 24
Finished Jul 04 05:14:37 PM PDT 24
Peak memory 205288 kb
Host smart-9d33dec5-18ff-4ff6-a3e0-43fe75f55324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384787129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3384787129
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3011524714
Short name T197
Test name
Test status
Simulation time 63802001 ps
CPU time 0.82 seconds
Started Jul 04 05:14:17 PM PDT 24
Finished Jul 04 05:14:18 PM PDT 24
Peak memory 205060 kb
Host smart-66140975-81b3-46dc-92c3-544d84f3bbf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011524714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3011524714
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1042443632
Short name T107
Test name
Test status
Simulation time 64393909 ps
CPU time 0.74 seconds
Started Jul 04 05:14:18 PM PDT 24
Finished Jul 04 05:14:19 PM PDT 24
Peak memory 204960 kb
Host smart-5650dfa7-c79c-425b-b339-31760b0433d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042443632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1042443632
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1566225249
Short name T222
Test name
Test status
Simulation time 67828735 ps
CPU time 0.74 seconds
Started Jul 04 05:14:29 PM PDT 24
Finished Jul 04 05:14:30 PM PDT 24
Peak memory 204988 kb
Host smart-bbda1201-775c-40b8-9ab0-95ec7d8405fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566225249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1566225249
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.3525793910
Short name T85
Test name
Test status
Simulation time 12073461920 ps
CPU time 10.58 seconds
Started Jul 04 05:14:26 PM PDT 24
Finished Jul 04 05:14:37 PM PDT 24
Peak memory 213504 kb
Host smart-bad783d5-fa07-43a6-a783-d9d5dcd89999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525793910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3525793910
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3681764317
Short name T274
Test name
Test status
Simulation time 79154833 ps
CPU time 0.88 seconds
Started Jul 04 05:14:26 PM PDT 24
Finished Jul 04 05:14:27 PM PDT 24
Peak memory 205044 kb
Host smart-09d343a4-e62e-4cb0-9082-4b05dd04adb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681764317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3681764317
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2838428118
Short name T6
Test name
Test status
Simulation time 9351104057 ps
CPU time 14.38 seconds
Started Jul 04 05:14:26 PM PDT 24
Finished Jul 04 05:14:41 PM PDT 24
Peak memory 213416 kb
Host smart-3851bdf7-6eb6-454d-abc1-d3fbc3f2436d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838428118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2838428118
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.4293433399
Short name T84
Test name
Test status
Simulation time 63807972 ps
CPU time 0.77 seconds
Started Jul 04 05:14:25 PM PDT 24
Finished Jul 04 05:14:26 PM PDT 24
Peak memory 205052 kb
Host smart-11cc6495-e74c-46c1-aeaf-5bdcffa1ece0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293433399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.4293433399
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3370275715
Short name T268
Test name
Test status
Simulation time 188555090 ps
CPU time 0.69 seconds
Started Jul 04 05:14:25 PM PDT 24
Finished Jul 04 05:14:26 PM PDT 24
Peak memory 205072 kb
Host smart-52785294-7779-4f21-b143-cc28e34e3148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370275715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3370275715
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.3319680320
Short name T219
Test name
Test status
Simulation time 101667533 ps
CPU time 0.73 seconds
Started Jul 04 05:14:26 PM PDT 24
Finished Jul 04 05:14:27 PM PDT 24
Peak memory 205024 kb
Host smart-71ff307b-6e1d-4063-a599-0d740004a35c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319680320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3319680320
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.2817155579
Short name T80
Test name
Test status
Simulation time 15849808868 ps
CPU time 17.16 seconds
Started Jul 04 05:14:29 PM PDT 24
Finished Jul 04 05:14:46 PM PDT 24
Peak memory 205244 kb
Host smart-fc1a5f4a-edc5-47ec-baba-364448791292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817155579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.2817155579
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3967848695
Short name T262
Test name
Test status
Simulation time 67531159 ps
CPU time 0.71 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:47 PM PDT 24
Peak memory 205020 kb
Host smart-38aaf78f-6d8c-4865-ac69-69e51686f1d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967848695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3967848695
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.4292914010
Short name T153
Test name
Test status
Simulation time 5865914036 ps
CPU time 7.31 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:54 PM PDT 24
Peak memory 213524 kb
Host smart-1ae2287f-68cc-4900-99a5-cb821fd56a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292914010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.4292914010
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1743893168
Short name T40
Test name
Test status
Simulation time 1021911833 ps
CPU time 2.46 seconds
Started Jul 04 05:13:44 PM PDT 24
Finished Jul 04 05:13:47 PM PDT 24
Peak memory 205244 kb
Host smart-e4f14b07-2926-41a9-a767-e0b7d5b2ebf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743893168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1743893168
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.4080566081
Short name T2
Test name
Test status
Simulation time 3163949289 ps
CPU time 2.23 seconds
Started Jul 04 05:13:42 PM PDT 24
Finished Jul 04 05:13:44 PM PDT 24
Peak memory 213568 kb
Host smart-33af1d7c-12d9-409d-afe6-08fd6a38ef9d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4080566081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.4080566081
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1813841582
Short name T7
Test name
Test status
Simulation time 441130275 ps
CPU time 0.85 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:13:51 PM PDT 24
Peak memory 205056 kb
Host smart-1d7c7438-6022-44b9-ab09-2bc3e8ba2a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813841582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1813841582
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2622179050
Short name T257
Test name
Test status
Simulation time 1087111634 ps
CPU time 4.04 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:51 PM PDT 24
Peak memory 213528 kb
Host smart-6e87f4bf-eb60-4570-a060-417379160988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622179050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2622179050
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2178264015
Short name T56
Test name
Test status
Simulation time 1836378875 ps
CPU time 2.11 seconds
Started Jul 04 05:13:44 PM PDT 24
Finished Jul 04 05:13:47 PM PDT 24
Peak memory 229472 kb
Host smart-dd72f6e2-8f53-4197-af36-184146c8be5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178264015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2178264015
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1429754254
Short name T83
Test name
Test status
Simulation time 63810362 ps
CPU time 0.77 seconds
Started Jul 04 05:14:25 PM PDT 24
Finished Jul 04 05:14:27 PM PDT 24
Peak memory 205024 kb
Host smart-9ec4cd78-d4c6-45e2-8b41-58d1f7639c69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429754254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1429754254
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.4020398452
Short name T273
Test name
Test status
Simulation time 81377626 ps
CPU time 0.75 seconds
Started Jul 04 05:14:25 PM PDT 24
Finished Jul 04 05:14:26 PM PDT 24
Peak memory 205084 kb
Host smart-d47b52da-c20c-40c8-8e18-726162c6f87c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020398452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.4020398452
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3220587333
Short name T225
Test name
Test status
Simulation time 47099082 ps
CPU time 0.79 seconds
Started Jul 04 05:14:33 PM PDT 24
Finished Jul 04 05:14:33 PM PDT 24
Peak memory 205072 kb
Host smart-79f58c50-5348-412a-8e6f-8f1da603f63e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220587333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3220587333
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.3956391720
Short name T243
Test name
Test status
Simulation time 9730858867 ps
CPU time 6.64 seconds
Started Jul 04 05:14:29 PM PDT 24
Finished Jul 04 05:14:36 PM PDT 24
Peak memory 213440 kb
Host smart-d51a254c-09b7-4f0e-9767-c422f2a9df18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956391720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3956391720
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1047592871
Short name T74
Test name
Test status
Simulation time 177915042 ps
CPU time 1.09 seconds
Started Jul 04 05:14:32 PM PDT 24
Finished Jul 04 05:14:33 PM PDT 24
Peak memory 205056 kb
Host smart-2d34a21d-6c83-4378-919f-1806aa3363f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047592871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1047592871
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.1114085171
Short name T13
Test name
Test status
Simulation time 16728101425 ps
CPU time 49.46 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:15:24 PM PDT 24
Peak memory 213528 kb
Host smart-548ac5c7-95fe-4424-9959-d6b8e760093b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114085171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1114085171
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.853654022
Short name T259
Test name
Test status
Simulation time 91603656 ps
CPU time 0.89 seconds
Started Jul 04 05:14:33 PM PDT 24
Finished Jul 04 05:14:34 PM PDT 24
Peak memory 205052 kb
Host smart-be2bc6b6-1dd2-447f-bda5-59aedf1a49b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853654022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.853654022
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.687459280
Short name T174
Test name
Test status
Simulation time 11717964706 ps
CPU time 30.13 seconds
Started Jul 04 05:14:37 PM PDT 24
Finished Jul 04 05:15:07 PM PDT 24
Peak memory 213548 kb
Host smart-0635ae1b-1c56-4aac-b885-2cb421e389af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687459280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.687459280
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2285058525
Short name T204
Test name
Test status
Simulation time 73931236 ps
CPU time 0.68 seconds
Started Jul 04 05:14:37 PM PDT 24
Finished Jul 04 05:14:38 PM PDT 24
Peak memory 205028 kb
Host smart-38689735-a2b3-4322-9887-6744dd6a3d66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285058525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2285058525
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.3972874773
Short name T194
Test name
Test status
Simulation time 3527471123 ps
CPU time 10.35 seconds
Started Jul 04 05:14:34 PM PDT 24
Finished Jul 04 05:14:45 PM PDT 24
Peak memory 205288 kb
Host smart-368e8d95-3605-46f8-92d7-8cab3acdd926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972874773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3972874773
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3479829422
Short name T198
Test name
Test status
Simulation time 136593169 ps
CPU time 0.77 seconds
Started Jul 04 05:14:32 PM PDT 24
Finished Jul 04 05:14:33 PM PDT 24
Peak memory 205060 kb
Host smart-caec7024-020b-4681-8016-71a117245914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479829422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3479829422
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.2323227504
Short name T23
Test name
Test status
Simulation time 4118687699 ps
CPU time 4.77 seconds
Started Jul 04 05:14:40 PM PDT 24
Finished Jul 04 05:14:46 PM PDT 24
Peak memory 205224 kb
Host smart-7aac8705-15e4-414e-8a07-2b99e9d5f0c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323227504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2323227504
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.161480956
Short name T235
Test name
Test status
Simulation time 58248283 ps
CPU time 0.72 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:14:37 PM PDT 24
Peak memory 205056 kb
Host smart-e02d4d9f-3c54-4b35-8670-f9c3770115b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161480956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.161480956
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2290422665
Short name T55
Test name
Test status
Simulation time 68560979 ps
CPU time 0.72 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:14:36 PM PDT 24
Peak memory 205048 kb
Host smart-2513840e-2554-42bb-80e2-2c47ac528980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290422665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2290422665
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.3383831974
Short name T176
Test name
Test status
Simulation time 13965854586 ps
CPU time 9.89 seconds
Started Jul 04 05:14:32 PM PDT 24
Finished Jul 04 05:14:42 PM PDT 24
Peak memory 205236 kb
Host smart-c0f9527d-668e-4380-8c0e-a87b0245ceda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383831974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3383831974
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3991679275
Short name T208
Test name
Test status
Simulation time 79635484 ps
CPU time 0.92 seconds
Started Jul 04 05:14:39 PM PDT 24
Finished Jul 04 05:14:40 PM PDT 24
Peak memory 205020 kb
Host smart-b6e82c26-585f-4507-a046-4f6ab9813d08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991679275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3991679275
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.998268933
Short name T211
Test name
Test status
Simulation time 128430702 ps
CPU time 0.71 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:47 PM PDT 24
Peak memory 205072 kb
Host smart-561c2b82-d78a-4684-8bc1-2b9a9587b7a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998268933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.998268933
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3793697856
Short name T53
Test name
Test status
Simulation time 2041621608 ps
CPU time 5.84 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:57 PM PDT 24
Peak memory 205284 kb
Host smart-3b0e9741-08d8-4d84-8287-ac658f1ccdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793697856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3793697856
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.814429056
Short name T3
Test name
Test status
Simulation time 1291673920 ps
CPU time 1.84 seconds
Started Jul 04 05:13:44 PM PDT 24
Finished Jul 04 05:13:46 PM PDT 24
Peak memory 213504 kb
Host smart-4789678a-95c7-475f-8e0b-7ebb87ef4746
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814429056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.814429056
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3341776883
Short name T248
Test name
Test status
Simulation time 2504579808 ps
CPU time 7.65 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:13:57 PM PDT 24
Peak memory 213548 kb
Host smart-f579cf95-e0ed-414b-a5ec-70416ce77bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341776883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3341776883
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1660133100
Short name T73
Test name
Test status
Simulation time 149791256 ps
CPU time 0.74 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:13:49 PM PDT 24
Peak memory 205040 kb
Host smart-30752191-500b-404c-845b-818cf1021c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660133100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1660133100
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.385097638
Short name T31
Test name
Test status
Simulation time 20190556931 ps
CPU time 28.29 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:14:14 PM PDT 24
Peak memory 217232 kb
Host smart-19da21f2-a67d-4777-8648-6633d85fe730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385097638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.385097638
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.4174547622
Short name T228
Test name
Test status
Simulation time 5881883160 ps
CPU time 10.78 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:58 PM PDT 24
Peak memory 213616 kb
Host smart-8e976593-c3f7-439d-a23f-34f537e13636
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4174547622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.4174547622
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1078912050
Short name T60
Test name
Test status
Simulation time 8827783356 ps
CPU time 20.89 seconds
Started Jul 04 05:13:45 PM PDT 24
Finished Jul 04 05:14:07 PM PDT 24
Peak memory 213660 kb
Host smart-a09bfa86-fbea-4601-b02d-8d1f652ba19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078912050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1078912050
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.4210666131
Short name T205
Test name
Test status
Simulation time 73885043 ps
CPU time 0.78 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:52 PM PDT 24
Peak memory 205064 kb
Host smart-8b66b4fb-0135-4b16-be03-0de06a21e190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210666131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.4210666131
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.731988826
Short name T160
Test name
Test status
Simulation time 15358420169 ps
CPU time 15.03 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:14:04 PM PDT 24
Peak memory 213608 kb
Host smart-eb399cc1-5eb8-44da-aaf4-29c88bc46340
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731988826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl
_access.731988826
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2478095847
Short name T253
Test name
Test status
Simulation time 45956880 ps
CPU time 0.7 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:13:55 PM PDT 24
Peak memory 205032 kb
Host smart-574fab3c-a917-4880-8d45-d21255eca1b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478095847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2478095847
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2417861943
Short name T246
Test name
Test status
Simulation time 9244772876 ps
CPU time 3.45 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:13:53 PM PDT 24
Peak memory 213660 kb
Host smart-4d1108c0-e66b-407d-b39a-64133e2080a6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2417861943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2417861943
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.421920356
Short name T241
Test name
Test status
Simulation time 12116098889 ps
CPU time 5.72 seconds
Started Jul 04 05:13:45 PM PDT 24
Finished Jul 04 05:13:51 PM PDT 24
Peak memory 213612 kb
Host smart-0ae0ad69-234e-4fa7-a11a-18e606f09c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421920356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.421920356
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.3707832497
Short name T169
Test name
Test status
Simulation time 5336769992 ps
CPU time 14.95 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:14:09 PM PDT 24
Peak memory 213448 kb
Host smart-112de7d2-f448-4f1c-b0fa-3adf53d8c046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707832497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3707832497
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.434200093
Short name T220
Test name
Test status
Simulation time 134951275 ps
CPU time 0.87 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:13:55 PM PDT 24
Peak memory 205068 kb
Host smart-33c1f296-d8d8-4b06-87fd-b4534f43ba6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434200093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.434200093
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.2053817236
Short name T27
Test name
Test status
Simulation time 10875051164 ps
CPU time 10.05 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:14:04 PM PDT 24
Peak memory 213604 kb
Host smart-7ce0e360-3dfa-47ac-8908-e64a215a191f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053817236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2053817236
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1173594851
Short name T249
Test name
Test status
Simulation time 1799501272 ps
CPU time 6.14 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:53 PM PDT 24
Peak memory 213452 kb
Host smart-1eda22f1-4882-4d0c-b25f-e77be167b091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173594851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1173594851
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1701701920
Short name T86
Test name
Test status
Simulation time 7954096848 ps
CPU time 23.14 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:14:14 PM PDT 24
Peak memory 205412 kb
Host smart-c78270ef-b5fb-4ac8-a6f0-0d936236afe4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1701701920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1701701920
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.948012936
Short name T265
Test name
Test status
Simulation time 3262015220 ps
CPU time 9.74 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:14:04 PM PDT 24
Peak memory 213596 kb
Host smart-b584e6bd-7774-4935-ba09-538e64ef745f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948012936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.948012936
Directory /workspace/9.rv_dm_sba_tl_access/latest
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