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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.46 95.27 79.45 89.42 74.36 85.50 98.32 54.88


Total test records in report: 433
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T90 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1569638068 Jul 06 05:29:32 PM PDT 24 Jul 06 05:29:36 PM PDT 24 224721699 ps
T91 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2767644023 Jul 06 05:29:48 PM PDT 24 Jul 06 05:30:00 PM PDT 24 1234230408 ps
T299 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3444018739 Jul 06 05:29:42 PM PDT 24 Jul 06 05:29:44 PM PDT 24 1780110756 ps
T92 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3597215518 Jul 06 05:29:32 PM PDT 24 Jul 06 05:29:37 PM PDT 24 1575881551 ps
T101 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3699586417 Jul 06 05:29:29 PM PDT 24 Jul 06 05:29:33 PM PDT 24 97714686 ps
T102 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1751920729 Jul 06 05:29:34 PM PDT 24 Jul 06 05:29:40 PM PDT 24 223649664 ps
T103 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3252212818 Jul 06 05:29:31 PM PDT 24 Jul 06 05:29:36 PM PDT 24 138700851 ps
T300 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.724321045 Jul 06 05:29:13 PM PDT 24 Jul 06 05:29:34 PM PDT 24 29328136555 ps
T301 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2819336553 Jul 06 05:29:49 PM PDT 24 Jul 06 05:29:59 PM PDT 24 12595732777 ps
T302 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3645811502 Jul 06 05:29:11 PM PDT 24 Jul 06 05:29:13 PM PDT 24 452972019 ps
T303 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2549104079 Jul 06 05:29:36 PM PDT 24 Jul 06 05:29:46 PM PDT 24 6920823641 ps
T109 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.413353511 Jul 06 05:29:46 PM PDT 24 Jul 06 05:30:49 PM PDT 24 7808747234 ps
T110 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.124498458 Jul 06 05:29:34 PM PDT 24 Jul 06 05:29:37 PM PDT 24 90414539 ps
T304 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2601982285 Jul 06 05:29:54 PM PDT 24 Jul 06 05:29:59 PM PDT 24 4977381911 ps
T305 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3201872082 Jul 06 05:29:50 PM PDT 24 Jul 06 05:29:56 PM PDT 24 1553369757 ps
T111 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3220916234 Jul 06 05:29:28 PM PDT 24 Jul 06 05:29:56 PM PDT 24 1066022797 ps
T104 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1291737521 Jul 06 05:29:48 PM PDT 24 Jul 06 05:29:53 PM PDT 24 334171212 ps
T306 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2884141678 Jul 06 05:29:32 PM PDT 24 Jul 06 05:29:34 PM PDT 24 64717793 ps
T307 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.46819306 Jul 06 05:29:14 PM PDT 24 Jul 06 05:30:26 PM PDT 24 88541998750 ps
T308 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.313616594 Jul 06 05:29:25 PM PDT 24 Jul 06 05:29:27 PM PDT 24 129920485 ps
T309 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3385594403 Jul 06 05:29:48 PM PDT 24 Jul 06 05:29:53 PM PDT 24 400574126 ps
T310 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3275744428 Jul 06 05:29:15 PM PDT 24 Jul 06 05:32:43 PM PDT 24 75341492137 ps
T311 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2976714487 Jul 06 05:30:11 PM PDT 24 Jul 06 05:30:17 PM PDT 24 4320632006 ps
T312 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1098908424 Jul 06 05:29:55 PM PDT 24 Jul 06 05:30:00 PM PDT 24 3582529170 ps
T313 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.820990634 Jul 06 05:29:42 PM PDT 24 Jul 06 05:29:51 PM PDT 24 9231577617 ps
T184 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1393455390 Jul 06 05:29:18 PM PDT 24 Jul 06 05:29:41 PM PDT 24 3314469160 ps
T130 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.554255592 Jul 06 05:29:50 PM PDT 24 Jul 06 05:29:55 PM PDT 24 1059530706 ps
T314 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2613727094 Jul 06 05:29:23 PM PDT 24 Jul 06 05:29:24 PM PDT 24 183178785 ps
T106 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2793733905 Jul 06 05:29:31 PM PDT 24 Jul 06 05:29:42 PM PDT 24 7908873096 ps
T131 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1875714282 Jul 06 05:29:34 PM PDT 24 Jul 06 05:29:39 PM PDT 24 798866089 ps
T112 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3170454766 Jul 06 05:29:47 PM PDT 24 Jul 06 05:29:50 PM PDT 24 443925187 ps
T315 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2158295196 Jul 06 05:29:23 PM PDT 24 Jul 06 05:29:57 PM PDT 24 13594326274 ps
T134 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2451578651 Jul 06 05:29:35 PM PDT 24 Jul 06 05:29:38 PM PDT 24 125315488 ps
T189 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.623101660 Jul 06 05:29:31 PM PDT 24 Jul 06 05:29:55 PM PDT 24 1205967497 ps
T316 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3009770274 Jul 06 05:29:26 PM PDT 24 Jul 06 05:29:27 PM PDT 24 323558546 ps
T317 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2707728010 Jul 06 05:29:25 PM PDT 24 Jul 06 05:29:28 PM PDT 24 778537141 ps
T48 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.550478174 Jul 06 05:29:14 PM PDT 24 Jul 06 05:29:33 PM PDT 24 23714414216 ps
T49 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3359232552 Jul 06 05:29:23 PM PDT 24 Jul 06 05:29:39 PM PDT 24 27056383800 ps
T318 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2500274449 Jul 06 05:29:25 PM PDT 24 Jul 06 05:32:52 PM PDT 24 174808405051 ps
T319 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2948422865 Jul 06 05:29:33 PM PDT 24 Jul 06 05:29:43 PM PDT 24 7251670124 ps
T320 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3803429111 Jul 06 05:29:29 PM PDT 24 Jul 06 05:30:03 PM PDT 24 43052102083 ps
T321 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1036591150 Jul 06 05:29:27 PM PDT 24 Jul 06 05:29:28 PM PDT 24 177613851 ps
T322 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3140202268 Jul 06 05:29:19 PM PDT 24 Jul 06 05:29:52 PM PDT 24 38458694503 ps
T183 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1654958046 Jul 06 05:29:54 PM PDT 24 Jul 06 05:29:59 PM PDT 24 383056440 ps
T323 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.4265127288 Jul 06 05:29:42 PM PDT 24 Jul 06 05:29:45 PM PDT 24 576771252 ps
T324 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.219837808 Jul 06 05:29:45 PM PDT 24 Jul 06 05:29:51 PM PDT 24 9128919514 ps
T113 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2275460502 Jul 06 05:29:41 PM PDT 24 Jul 06 05:30:58 PM PDT 24 17786691196 ps
T185 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.698318228 Jul 06 05:29:43 PM PDT 24 Jul 06 05:30:01 PM PDT 24 3002708210 ps
T325 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2032772964 Jul 06 05:29:20 PM PDT 24 Jul 06 05:29:23 PM PDT 24 93186093 ps
T190 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3286451338 Jul 06 05:29:56 PM PDT 24 Jul 06 05:30:09 PM PDT 24 1863346268 ps
T326 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2884145636 Jul 06 05:29:47 PM PDT 24 Jul 06 05:29:49 PM PDT 24 523815646 ps
T114 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.942029537 Jul 06 05:29:19 PM PDT 24 Jul 06 05:30:40 PM PDT 24 16102474834 ps
T327 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1026210779 Jul 06 05:29:47 PM PDT 24 Jul 06 05:29:53 PM PDT 24 836944723 ps
T328 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2131906808 Jul 06 05:29:35 PM PDT 24 Jul 06 05:29:43 PM PDT 24 8521715890 ps
T329 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1584277306 Jul 06 05:29:34 PM PDT 24 Jul 06 05:29:38 PM PDT 24 59176601 ps
T330 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1183226666 Jul 06 05:29:34 PM PDT 24 Jul 06 05:29:38 PM PDT 24 1247299104 ps
T331 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1270033737 Jul 06 05:29:29 PM PDT 24 Jul 06 05:29:33 PM PDT 24 3035543911 ps
T332 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3899543859 Jul 06 05:29:44 PM PDT 24 Jul 06 05:29:49 PM PDT 24 178263866 ps
T333 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2524534156 Jul 06 05:29:29 PM PDT 24 Jul 06 05:29:34 PM PDT 24 1236237632 ps
T334 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2429227679 Jul 06 05:29:31 PM PDT 24 Jul 06 05:29:34 PM PDT 24 116679702 ps
T335 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3056126975 Jul 06 05:29:30 PM PDT 24 Jul 06 05:29:40 PM PDT 24 431359428 ps
T336 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3708383429 Jul 06 05:29:24 PM PDT 24 Jul 06 05:29:28 PM PDT 24 3866592711 ps
T337 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.223651966 Jul 06 05:29:43 PM PDT 24 Jul 06 05:31:19 PM PDT 24 60892169122 ps
T107 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1505116024 Jul 06 05:29:13 PM PDT 24 Jul 06 05:29:16 PM PDT 24 2932908698 ps
T119 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3301672923 Jul 06 05:29:31 PM PDT 24 Jul 06 05:29:35 PM PDT 24 424894124 ps
T338 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4247565575 Jul 06 05:29:30 PM PDT 24 Jul 06 05:29:35 PM PDT 24 1026180114 ps
T339 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1472406568 Jul 06 05:29:32 PM PDT 24 Jul 06 05:29:41 PM PDT 24 5769313339 ps
T340 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.492637771 Jul 06 05:29:46 PM PDT 24 Jul 06 05:29:55 PM PDT 24 7542609920 ps
T115 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3954324349 Jul 06 05:29:41 PM PDT 24 Jul 06 05:29:48 PM PDT 24 563813622 ps
T341 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3531735833 Jul 06 05:29:29 PM PDT 24 Jul 06 05:29:31 PM PDT 24 105797808 ps
T342 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3298176095 Jul 06 05:29:33 PM PDT 24 Jul 06 05:29:39 PM PDT 24 585385073 ps
T120 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1909178986 Jul 06 05:29:44 PM PDT 24 Jul 06 05:29:46 PM PDT 24 166806635 ps
T343 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1692318354 Jul 06 05:29:19 PM PDT 24 Jul 06 05:30:00 PM PDT 24 21495932937 ps
T193 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2164686881 Jul 06 05:29:52 PM PDT 24 Jul 06 05:30:02 PM PDT 24 3056957530 ps
T344 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2854908789 Jul 06 05:29:43 PM PDT 24 Jul 06 05:29:53 PM PDT 24 1336616307 ps
T345 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1268623416 Jul 06 05:29:50 PM PDT 24 Jul 06 05:29:57 PM PDT 24 169767615 ps
T116 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1111723327 Jul 06 05:29:45 PM PDT 24 Jul 06 05:29:54 PM PDT 24 2246416907 ps
T346 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4195866529 Jul 06 05:29:43 PM PDT 24 Jul 06 05:29:45 PM PDT 24 171684408 ps
T121 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1116546062 Jul 06 05:29:15 PM PDT 24 Jul 06 05:30:25 PM PDT 24 6609597681 ps
T122 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.201780883 Jul 06 05:29:35 PM PDT 24 Jul 06 05:30:36 PM PDT 24 5644544827 ps
T347 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.4241128685 Jul 06 05:29:35 PM PDT 24 Jul 06 05:31:12 PM PDT 24 43256379427 ps
T348 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2897836669 Jul 06 05:29:50 PM PDT 24 Jul 06 05:29:56 PM PDT 24 2134303856 ps
T349 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2530379460 Jul 06 05:29:34 PM PDT 24 Jul 06 05:29:39 PM PDT 24 120010776 ps
T350 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2832610804 Jul 06 05:29:45 PM PDT 24 Jul 06 05:29:51 PM PDT 24 3886832890 ps
T351 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.60110269 Jul 06 05:29:24 PM PDT 24 Jul 06 05:29:26 PM PDT 24 356537845 ps
T352 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1626437010 Jul 06 05:29:49 PM PDT 24 Jul 06 05:29:51 PM PDT 24 663339037 ps
T353 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3529670155 Jul 06 05:29:50 PM PDT 24 Jul 06 05:29:59 PM PDT 24 3498233095 ps
T354 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2333452888 Jul 06 05:29:22 PM PDT 24 Jul 06 05:29:30 PM PDT 24 2956946628 ps
T187 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2865025340 Jul 06 05:29:51 PM PDT 24 Jul 06 05:30:09 PM PDT 24 1802404067 ps
T355 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.4127539635 Jul 06 05:29:29 PM PDT 24 Jul 06 05:29:34 PM PDT 24 157588679 ps
T356 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2056581636 Jul 06 05:29:31 PM PDT 24 Jul 06 05:30:34 PM PDT 24 27733989413 ps
T357 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3803183454 Jul 06 05:29:56 PM PDT 24 Jul 06 05:30:00 PM PDT 24 196291546 ps
T358 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.516300641 Jul 06 05:29:47 PM PDT 24 Jul 06 05:29:50 PM PDT 24 2895565513 ps
T359 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3393286327 Jul 06 05:29:39 PM PDT 24 Jul 06 05:29:41 PM PDT 24 1049887287 ps
T360 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3250084487 Jul 06 05:29:56 PM PDT 24 Jul 06 05:29:58 PM PDT 24 297677201 ps
T117 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2726992628 Jul 06 05:29:51 PM PDT 24 Jul 06 05:30:05 PM PDT 24 570140333 ps
T361 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3255401018 Jul 06 05:29:49 PM PDT 24 Jul 06 05:30:04 PM PDT 24 4573960062 ps
T108 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1552659635 Jul 06 05:29:24 PM PDT 24 Jul 06 05:29:29 PM PDT 24 1351337361 ps
T362 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2539228505 Jul 06 05:29:20 PM PDT 24 Jul 06 05:29:21 PM PDT 24 881839238 ps
T363 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2193027807 Jul 06 05:29:13 PM PDT 24 Jul 06 05:29:17 PM PDT 24 3470589381 ps
T123 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.207317906 Jul 06 05:29:51 PM PDT 24 Jul 06 05:29:54 PM PDT 24 183948989 ps
T364 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.60268546 Jul 06 05:29:23 PM PDT 24 Jul 06 05:29:52 PM PDT 24 100876261647 ps
T365 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1022158083 Jul 06 05:29:30 PM PDT 24 Jul 06 05:29:34 PM PDT 24 2609395005 ps
T366 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1659635134 Jul 06 05:29:24 PM PDT 24 Jul 06 05:29:30 PM PDT 24 7097064767 ps
T367 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2380771467 Jul 06 05:29:55 PM PDT 24 Jul 06 05:31:08 PM PDT 24 26219816086 ps
T368 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2795001556 Jul 06 05:29:28 PM PDT 24 Jul 06 05:29:31 PM PDT 24 423452501 ps
T369 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1266527074 Jul 06 05:29:19 PM PDT 24 Jul 06 05:29:46 PM PDT 24 34491136679 ps
T370 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1731681534 Jul 06 05:29:29 PM PDT 24 Jul 06 05:29:36 PM PDT 24 1846943793 ps
T127 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1568932582 Jul 06 05:29:42 PM PDT 24 Jul 06 05:29:44 PM PDT 24 180571528 ps
T371 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2945486860 Jul 06 05:29:45 PM PDT 24 Jul 06 05:29:49 PM PDT 24 474164573 ps
T372 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.460388789 Jul 06 05:29:47 PM PDT 24 Jul 06 05:29:50 PM PDT 24 173644154 ps
T373 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.4629955 Jul 06 05:29:57 PM PDT 24 Jul 06 05:30:24 PM PDT 24 9176368641 ps
T374 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3279402844 Jul 06 05:29:49 PM PDT 24 Jul 06 05:29:51 PM PDT 24 1369037473 ps
T375 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2299780537 Jul 06 05:29:52 PM PDT 24 Jul 06 05:30:00 PM PDT 24 2616004158 ps
T191 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2063547685 Jul 06 05:29:15 PM PDT 24 Jul 06 05:29:24 PM PDT 24 2953246500 ps
T376 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2214750111 Jul 06 05:29:43 PM PDT 24 Jul 06 05:29:50 PM PDT 24 1892460611 ps
T128 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3261290930 Jul 06 05:29:33 PM PDT 24 Jul 06 05:29:36 PM PDT 24 75046387 ps
T129 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1159945340 Jul 06 05:29:23 PM PDT 24 Jul 06 05:29:26 PM PDT 24 78604167 ps
T377 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.650034949 Jul 06 05:29:48 PM PDT 24 Jul 06 05:29:49 PM PDT 24 163402365 ps
T378 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2377822253 Jul 06 05:29:49 PM PDT 24 Jul 06 05:29:53 PM PDT 24 3163663530 ps
T379 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4056606310 Jul 06 05:29:43 PM PDT 24 Jul 06 05:30:19 PM PDT 24 13688148898 ps
T380 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4149892164 Jul 06 05:29:49 PM PDT 24 Jul 06 05:29:53 PM PDT 24 365305890 ps
T186 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2862961741 Jul 06 05:29:36 PM PDT 24 Jul 06 05:29:56 PM PDT 24 2986386421 ps
T381 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.4141109973 Jul 06 05:29:46 PM PDT 24 Jul 06 05:29:49 PM PDT 24 206176888 ps
T118 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4118866216 Jul 06 05:29:24 PM PDT 24 Jul 06 05:30:32 PM PDT 24 3301065944 ps
T382 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2630543370 Jul 06 05:29:37 PM PDT 24 Jul 06 05:29:39 PM PDT 24 516493410 ps
T383 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1100057520 Jul 06 05:29:28 PM PDT 24 Jul 06 05:29:37 PM PDT 24 17206022302 ps
T384 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.67693015 Jul 06 05:29:44 PM PDT 24 Jul 06 05:29:48 PM PDT 24 824990773 ps
T385 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3409871754 Jul 06 05:29:26 PM PDT 24 Jul 06 05:29:27 PM PDT 24 247548156 ps
T386 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1891630912 Jul 06 05:29:50 PM PDT 24 Jul 06 05:30:44 PM PDT 24 62721321980 ps
T387 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3470009253 Jul 06 05:29:29 PM PDT 24 Jul 06 05:29:35 PM PDT 24 255900158 ps
T388 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1844101676 Jul 06 05:29:49 PM PDT 24 Jul 06 05:29:53 PM PDT 24 187564779 ps
T389 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.235764525 Jul 06 05:29:24 PM PDT 24 Jul 06 05:29:35 PM PDT 24 3941394961 ps
T124 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1642153998 Jul 06 05:29:32 PM PDT 24 Jul 06 05:30:05 PM PDT 24 6978777110 ps
T390 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3266805524 Jul 06 05:29:49 PM PDT 24 Jul 06 05:29:54 PM PDT 24 5062013579 ps
T391 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1599428674 Jul 06 05:29:51 PM PDT 24 Jul 06 05:29:57 PM PDT 24 327718184 ps
T392 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2559379111 Jul 06 05:29:23 PM PDT 24 Jul 06 05:29:24 PM PDT 24 170933939 ps
T393 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1945909239 Jul 06 05:29:33 PM PDT 24 Jul 06 05:29:39 PM PDT 24 172904126 ps
T394 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3461567806 Jul 06 05:29:15 PM PDT 24 Jul 06 05:29:16 PM PDT 24 547651001 ps
T395 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2568949205 Jul 06 05:29:22 PM PDT 24 Jul 06 05:30:36 PM PDT 24 14960242374 ps
T396 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2903202788 Jul 06 05:29:43 PM PDT 24 Jul 06 05:29:50 PM PDT 24 189004195 ps
T397 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1694478990 Jul 06 05:30:00 PM PDT 24 Jul 06 05:30:12 PM PDT 24 4161055357 ps
T188 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3093763166 Jul 06 05:29:38 PM PDT 24 Jul 06 05:29:56 PM PDT 24 4268248908 ps
T398 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.213831587 Jul 06 05:29:29 PM PDT 24 Jul 06 05:29:32 PM PDT 24 142152728 ps
T399 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2533888186 Jul 06 05:30:06 PM PDT 24 Jul 06 05:30:13 PM PDT 24 179825746 ps
T400 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3304009635 Jul 06 05:29:13 PM PDT 24 Jul 06 05:29:28 PM PDT 24 4546992849 ps
T401 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3361110144 Jul 06 05:29:46 PM PDT 24 Jul 06 05:29:48 PM PDT 24 173602220 ps
T402 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3474876210 Jul 06 05:29:28 PM PDT 24 Jul 06 05:29:31 PM PDT 24 257737993 ps
T403 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1938556561 Jul 06 05:29:47 PM PDT 24 Jul 06 05:29:49 PM PDT 24 1130123129 ps
T404 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2687076830 Jul 06 05:29:23 PM PDT 24 Jul 06 05:29:24 PM PDT 24 785730670 ps
T405 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1780811378 Jul 06 05:29:31 PM PDT 24 Jul 06 05:29:36 PM PDT 24 432619813 ps
T406 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2332712814 Jul 06 05:29:19 PM PDT 24 Jul 06 05:29:20 PM PDT 24 139451762 ps
T192 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3821947310 Jul 06 05:29:13 PM PDT 24 Jul 06 05:29:31 PM PDT 24 1610134624 ps
T407 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3637090051 Jul 06 05:29:23 PM PDT 24 Jul 06 05:29:30 PM PDT 24 202415234 ps
T408 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3605930368 Jul 06 05:29:14 PM PDT 24 Jul 06 05:29:18 PM PDT 24 3790983793 ps
T409 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2059231209 Jul 06 05:29:45 PM PDT 24 Jul 06 05:29:47 PM PDT 24 275488993 ps
T410 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3090963946 Jul 06 05:29:23 PM PDT 24 Jul 06 05:29:25 PM PDT 24 90562143 ps
T411 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4009128638 Jul 06 05:29:42 PM PDT 24 Jul 06 05:29:44 PM PDT 24 192000864 ps
T412 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2101363365 Jul 06 05:29:34 PM PDT 24 Jul 06 05:29:38 PM PDT 24 154344787 ps
T413 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2252540956 Jul 06 05:29:29 PM PDT 24 Jul 06 05:29:32 PM PDT 24 147932826 ps
T414 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1238095985 Jul 06 05:29:33 PM PDT 24 Jul 06 05:30:05 PM PDT 24 58608625141 ps
T415 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3899395212 Jul 06 05:29:48 PM PDT 24 Jul 06 05:30:10 PM PDT 24 25842723012 ps
T416 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1626637196 Jul 06 05:29:33 PM PDT 24 Jul 06 05:29:36 PM PDT 24 324416080 ps
T417 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2828561335 Jul 06 05:29:43 PM PDT 24 Jul 06 05:29:50 PM PDT 24 13038340341 ps
T418 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.555290248 Jul 06 05:29:46 PM PDT 24 Jul 06 05:29:54 PM PDT 24 3722194519 ps
T419 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2112944384 Jul 06 05:29:25 PM PDT 24 Jul 06 05:29:28 PM PDT 24 187219803 ps
T420 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2424266191 Jul 06 05:29:29 PM PDT 24 Jul 06 05:30:09 PM PDT 24 23115360619 ps
T421 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4175075846 Jul 06 05:29:36 PM PDT 24 Jul 06 05:29:37 PM PDT 24 91964326 ps
T422 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2955542494 Jul 06 05:29:46 PM PDT 24 Jul 06 05:29:54 PM PDT 24 230281265 ps
T125 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2762549502 Jul 06 05:29:46 PM PDT 24 Jul 06 05:30:13 PM PDT 24 2449668155 ps
T423 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1236952311 Jul 06 05:29:49 PM PDT 24 Jul 06 05:30:10 PM PDT 24 6641913644 ps
T424 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3349136763 Jul 06 05:29:19 PM PDT 24 Jul 06 05:29:24 PM PDT 24 4084318914 ps
T425 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4146586378 Jul 06 05:29:46 PM PDT 24 Jul 06 05:29:49 PM PDT 24 174366703 ps
T426 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1281516390 Jul 06 05:29:52 PM PDT 24 Jul 06 05:29:55 PM PDT 24 2542026028 ps
T427 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.234901226 Jul 06 05:29:49 PM PDT 24 Jul 06 05:29:56 PM PDT 24 3503515072 ps
T194 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2692531961 Jul 06 05:29:33 PM PDT 24 Jul 06 05:29:44 PM PDT 24 1786680396 ps
T428 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.190222057 Jul 06 05:29:49 PM PDT 24 Jul 06 05:29:51 PM PDT 24 43842347 ps
T429 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.875790840 Jul 06 05:29:25 PM PDT 24 Jul 06 05:32:34 PM PDT 24 72889934118 ps
T430 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2621463077 Jul 06 05:29:47 PM PDT 24 Jul 06 05:29:48 PM PDT 24 74930216 ps
T431 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2695585442 Jul 06 05:29:51 PM PDT 24 Jul 06 05:29:53 PM PDT 24 96642946 ps
T432 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3197228669 Jul 06 05:29:36 PM PDT 24 Jul 06 05:29:39 PM PDT 24 91202090 ps
T126 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3600785974 Jul 06 05:29:31 PM PDT 24 Jul 06 05:29:35 PM PDT 24 120380431 ps
T433 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1277388988 Jul 06 05:29:57 PM PDT 24 Jul 06 05:30:00 PM PDT 24 317703714 ps

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.406901125
Short name T1
Test name
Test status
Simulation time 9917456583 ps
CPU time 13.95 seconds
Started Jul 06 05:30:11 PM PDT 24
Finished Jul 06 05:30:25 PM PDT 24
Peak memory 213652 kb
Host smart-19ad88c4-f3af-4e18-a40b-ccbbed40b43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406901125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.406901125
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.832711377
Short name T5
Test name
Test status
Simulation time 5930910592 ps
CPU time 15.75 seconds
Started Jul 06 05:30:37 PM PDT 24
Finished Jul 06 05:30:54 PM PDT 24
Peak memory 213516 kb
Host smart-450ee80e-2b67-4c56-9a7f-7b6b2456fe54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832711377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.832711377
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.1446584037
Short name T47
Test name
Test status
Simulation time 28994101684 ps
CPU time 41.34 seconds
Started Jul 06 05:29:21 PM PDT 24
Finished Jul 06 05:30:02 PM PDT 24
Peak memory 220596 kb
Host smart-4bae78cc-8cb0-4f9b-9f09-4e537004e308
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446584037 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.1446584037
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2060880101
Short name T59
Test name
Test status
Simulation time 2831957988 ps
CPU time 9.35 seconds
Started Jul 06 05:29:34 PM PDT 24
Finished Jul 06 05:29:45 PM PDT 24
Peak memory 213452 kb
Host smart-a7e4b6b4-1f89-440a-aec3-aabbdec76e60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060880101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
060880101
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.3722901309
Short name T30
Test name
Test status
Simulation time 4264755915 ps
CPU time 7.23 seconds
Started Jul 06 05:30:19 PM PDT 24
Finished Jul 06 05:30:26 PM PDT 24
Peak memory 205276 kb
Host smart-2b5c91d5-6e3d-48bd-9b4b-6bdfe55681c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722901309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3722901309
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2526348273
Short name T28
Test name
Test status
Simulation time 9246217233 ps
CPU time 24.63 seconds
Started Jul 06 05:30:13 PM PDT 24
Finished Jul 06 05:30:38 PM PDT 24
Peak memory 205384 kb
Host smart-88d8e547-4750-4a37-96c1-3fcb9ff6744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526348273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2526348273
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.2040953970
Short name T6
Test name
Test status
Simulation time 2648269988 ps
CPU time 8.13 seconds
Started Jul 06 05:30:27 PM PDT 24
Finished Jul 06 05:30:35 PM PDT 24
Peak memory 205256 kb
Host smart-f1ccc07c-1217-4cfa-982e-3cc781630c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040953970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.2040953970
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.187144785
Short name T157
Test name
Test status
Simulation time 152248391976 ps
CPU time 137.32 seconds
Started Jul 06 05:30:02 PM PDT 24
Finished Jul 06 05:32:20 PM PDT 24
Peak memory 221744 kb
Host smart-2f8f34da-7d00-42a3-87f0-0277bc71d2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187144785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.187144785
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1645849461
Short name T93
Test name
Test status
Simulation time 168149921 ps
CPU time 0.79 seconds
Started Jul 06 05:29:59 PM PDT 24
Finished Jul 06 05:30:00 PM PDT 24
Peak memory 205072 kb
Host smart-149faaab-ce6a-40e5-83ae-e212dcbd9060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645849461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1645849461
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.826361534
Short name T52
Test name
Test status
Simulation time 48536933 ps
CPU time 0.95 seconds
Started Jul 06 05:30:14 PM PDT 24
Finished Jul 06 05:30:16 PM PDT 24
Peak memory 215648 kb
Host smart-bc09d020-3e17-486c-8dbf-fe32103df5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826361534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.826361534
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.4037898148
Short name T11
Test name
Test status
Simulation time 4717546014 ps
CPU time 8.29 seconds
Started Jul 06 05:30:16 PM PDT 24
Finished Jul 06 05:30:25 PM PDT 24
Peak memory 213536 kb
Host smart-d0d3a5fd-05c8-49fe-8011-e112ef30635c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037898148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.4037898148
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.828035751
Short name T40
Test name
Test status
Simulation time 334577923 ps
CPU time 0.98 seconds
Started Jul 06 05:29:59 PM PDT 24
Finished Jul 06 05:30:00 PM PDT 24
Peak memory 205032 kb
Host smart-42264091-892e-4961-9025-5d2ccc785c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828035751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.828035751
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2552487667
Short name T89
Test name
Test status
Simulation time 5541255178 ps
CPU time 22.68 seconds
Started Jul 06 05:29:36 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 213460 kb
Host smart-1062de19-dc1e-4db4-8d27-0571f5bd6bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552487667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2552487667
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.2901471363
Short name T23
Test name
Test status
Simulation time 11749894940 ps
CPU time 31.53 seconds
Started Jul 06 05:30:25 PM PDT 24
Finished Jul 06 05:30:57 PM PDT 24
Peak memory 213576 kb
Host smart-fd9dbe42-fcc0-4696-aff2-cea9ee8bc65b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901471363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2901471363
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.469774053
Short name T39
Test name
Test status
Simulation time 201676458 ps
CPU time 1.17 seconds
Started Jul 06 05:29:48 PM PDT 24
Finished Jul 06 05:29:50 PM PDT 24
Peak memory 205104 kb
Host smart-3f69be5a-4bd1-4b71-bedc-f50857b39390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469774053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.469774053
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3220916234
Short name T111
Test name
Test status
Simulation time 1066022797 ps
CPU time 27.32 seconds
Started Jul 06 05:29:28 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 205260 kb
Host smart-acd4773c-5d6c-4427-9269-fb15302ee9ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220916234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3220916234
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3042876835
Short name T56
Test name
Test status
Simulation time 376147103 ps
CPU time 1.15 seconds
Started Jul 06 05:30:06 PM PDT 24
Finished Jul 06 05:30:07 PM PDT 24
Peak memory 229540 kb
Host smart-d574d774-77e6-4b90-b330-2f4f6f084771
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042876835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3042876835
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2618179304
Short name T36
Test name
Test status
Simulation time 177830780 ps
CPU time 0.86 seconds
Started Jul 06 05:29:54 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 213364 kb
Host smart-d49518d1-8b85-4522-845d-b1a971425ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618179304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2618179304
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.477905699
Short name T151
Test name
Test status
Simulation time 11370668823 ps
CPU time 18.06 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:30:09 PM PDT 24
Peak memory 205408 kb
Host smart-df05138a-7438-4f5f-bf68-36a57e5f9b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477905699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.477905699
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4118866216
Short name T118
Test name
Test status
Simulation time 3301065944 ps
CPU time 67.66 seconds
Started Jul 06 05:29:24 PM PDT 24
Finished Jul 06 05:30:32 PM PDT 24
Peak memory 213396 kb
Host smart-cfc2006e-81bb-48d6-9f0d-6dc4bd613ba5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118866216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.4118866216
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1207863881
Short name T86
Test name
Test status
Simulation time 3004361488 ps
CPU time 20.62 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:30:09 PM PDT 24
Peak memory 213492 kb
Host smart-f6b7bbb8-3d71-4674-8eaa-cc7a5a3b89ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207863881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
207863881
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2195497167
Short name T147
Test name
Test status
Simulation time 17323709871 ps
CPU time 47.24 seconds
Started Jul 06 05:30:06 PM PDT 24
Finished Jul 06 05:30:54 PM PDT 24
Peak memory 213588 kb
Host smart-e9bfd17e-58da-411e-8a14-538189ca2c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195497167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2195497167
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2901805340
Short name T63
Test name
Test status
Simulation time 431624942 ps
CPU time 3.92 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:55 PM PDT 24
Peak memory 205184 kb
Host smart-6a99f596-1b94-4b8d-9226-3eecdced52f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901805340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2901805340
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3168829241
Short name T42
Test name
Test status
Simulation time 346960442 ps
CPU time 1.64 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:52 PM PDT 24
Peak memory 204980 kb
Host smart-1e569a4a-7081-4bca-b535-627ea79069b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168829241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3168829241
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.2507033057
Short name T9
Test name
Test status
Simulation time 6353813315 ps
CPU time 10.3 seconds
Started Jul 06 05:30:06 PM PDT 24
Finished Jul 06 05:30:17 PM PDT 24
Peak memory 205408 kb
Host smart-3921166b-1b13-44e5-8fa4-a5e36c69ff2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507033057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2507033057
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1970574733
Short name T135
Test name
Test status
Simulation time 2065155604 ps
CPU time 2.66 seconds
Started Jul 06 05:30:02 PM PDT 24
Finished Jul 06 05:30:05 PM PDT 24
Peak memory 213552 kb
Host smart-11da3c95-52c2-407b-8e09-f0defdfdc12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970574733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1970574733
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3522809677
Short name T18
Test name
Test status
Simulation time 531662477 ps
CPU time 1.99 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:50 PM PDT 24
Peak memory 205092 kb
Host smart-51616fea-386e-4500-bc67-ec19e6e8ecfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522809677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3522809677
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.2005466438
Short name T164
Test name
Test status
Simulation time 5304249094 ps
CPU time 4.62 seconds
Started Jul 06 05:30:32 PM PDT 24
Finished Jul 06 05:30:37 PM PDT 24
Peak memory 205396 kb
Host smart-cfe7ccb0-89f1-482e-8bae-c4e4f45b4827
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005466438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2005466438
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2862961741
Short name T186
Test name
Test status
Simulation time 2986386421 ps
CPU time 19.73 seconds
Started Jul 06 05:29:36 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 213468 kb
Host smart-1728ef17-4444-4ec9-8951-6bea5f5c2ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862961741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2862961741
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.820949852
Short name T178
Test name
Test status
Simulation time 3944347256 ps
CPU time 9.35 seconds
Started Jul 06 05:30:14 PM PDT 24
Finished Jul 06 05:30:24 PM PDT 24
Peak memory 213628 kb
Host smart-70237ca9-a76c-4925-bc98-df30e82b80c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820949852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.820949852
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.3979121176
Short name T22
Test name
Test status
Simulation time 8490923255 ps
CPU time 21.04 seconds
Started Jul 06 05:30:34 PM PDT 24
Finished Jul 06 05:30:57 PM PDT 24
Peak memory 205380 kb
Host smart-f915a2fc-7687-4bca-8443-f534152cde0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979121176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3979121176
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.531736107
Short name T136
Test name
Test status
Simulation time 15074214452 ps
CPU time 8.03 seconds
Started Jul 06 05:30:04 PM PDT 24
Finished Jul 06 05:30:12 PM PDT 24
Peak memory 213656 kb
Host smart-a7eb4ccf-1fb9-48b4-a4cc-29404723466c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531736107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.531736107
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3419753897
Short name T33
Test name
Test status
Simulation time 165636587 ps
CPU time 0.89 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 205048 kb
Host smart-ae7966cd-4b74-4ba2-ba2e-9833dec4d1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419753897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3419753897
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3609897756
Short name T170
Test name
Test status
Simulation time 6944457476 ps
CPU time 11.7 seconds
Started Jul 06 05:30:13 PM PDT 24
Finished Jul 06 05:30:25 PM PDT 24
Peak memory 205332 kb
Host smart-e15f7b19-d1a3-44eb-85c7-b94f3d56f149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609897756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3609897756
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.443360665
Short name T25
Test name
Test status
Simulation time 3421480066 ps
CPU time 4.79 seconds
Started Jul 06 05:30:02 PM PDT 24
Finished Jul 06 05:30:07 PM PDT 24
Peak memory 215160 kb
Host smart-5582d9b2-f1c9-492d-95b2-246928e28f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443360665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.443360665
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2034322244
Short name T10
Test name
Test status
Simulation time 13412927868 ps
CPU time 36.55 seconds
Started Jul 06 05:30:09 PM PDT 24
Finished Jul 06 05:30:46 PM PDT 24
Peak memory 205292 kb
Host smart-8e9064be-6fe1-4e2d-b0ac-541c74f0a980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034322244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2034322244
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2259474936
Short name T138
Test name
Test status
Simulation time 2010558315 ps
CPU time 5.79 seconds
Started Jul 06 05:30:31 PM PDT 24
Finished Jul 06 05:30:37 PM PDT 24
Peak memory 205356 kb
Host smart-a5446fec-e406-4a6f-bf6e-08cd3594f7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259474936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2259474936
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.1274833327
Short name T175
Test name
Test status
Simulation time 14038663586 ps
CPU time 16.31 seconds
Started Jul 06 05:30:16 PM PDT 24
Finished Jul 06 05:30:32 PM PDT 24
Peak memory 213472 kb
Host smart-c8db186b-43c8-4d71-9f7f-07205b216b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274833327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1274833327
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.724321045
Short name T300
Test name
Test status
Simulation time 29328136555 ps
CPU time 20.75 seconds
Started Jul 06 05:29:13 PM PDT 24
Finished Jul 06 05:29:34 PM PDT 24
Peak memory 205020 kb
Host smart-f2a10640-da19-49e0-88d9-a53220159ca7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724321045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.724321045
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1505116024
Short name T107
Test name
Test status
Simulation time 2932908698 ps
CPU time 2.31 seconds
Started Jul 06 05:29:13 PM PDT 24
Finished Jul 06 05:29:16 PM PDT 24
Peak memory 205188 kb
Host smart-54a26f44-be4c-4861-8f68-45d40b7b4dc9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505116024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1505116024
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2333452888
Short name T354
Test name
Test status
Simulation time 2956946628 ps
CPU time 7.87 seconds
Started Jul 06 05:29:22 PM PDT 24
Finished Jul 06 05:29:30 PM PDT 24
Peak memory 221348 kb
Host smart-27b1936d-5dfc-4c0c-bcb5-38d7b4417fde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333452888 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2333452888
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1498030907
Short name T4
Test name
Test status
Simulation time 413706961 ps
CPU time 1.29 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 205072 kb
Host smart-fbc05a5d-d79f-49c9-90b0-145392eec2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498030907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1498030907
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2661454208
Short name T88
Test name
Test status
Simulation time 2433015858 ps
CPU time 13.43 seconds
Started Jul 06 05:29:45 PM PDT 24
Finished Jul 06 05:29:58 PM PDT 24
Peak memory 213412 kb
Host smart-2472b711-b527-494b-9694-f0a413d0ed4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661454208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
661454208
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3093763166
Short name T188
Test name
Test status
Simulation time 4268248908 ps
CPU time 17.57 seconds
Started Jul 06 05:29:38 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 213440 kb
Host smart-3a1f5d9c-cb1a-4548-9f64-f1cbc82ac5b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093763166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
093763166
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1180125478
Short name T21
Test name
Test status
Simulation time 244960751 ps
CPU time 1.28 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:48 PM PDT 24
Peak memory 205028 kb
Host smart-db499647-0c22-450f-9aab-b3d6ecfdc410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180125478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1180125478
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.766774736
Short name T159
Test name
Test status
Simulation time 688501229 ps
CPU time 1.82 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:29:58 PM PDT 24
Peak memory 205028 kb
Host smart-bdee508f-5f17-4a55-a49d-119e6a1fc46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766774736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.766774736
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.4264529957
Short name T140
Test name
Test status
Simulation time 1301970563 ps
CPU time 1.68 seconds
Started Jul 06 05:29:53 PM PDT 24
Finished Jul 06 05:29:55 PM PDT 24
Peak memory 205080 kb
Host smart-8cd8ef36-1634-4526-b237-35822d6dc4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264529957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.4264529957
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.4139590913
Short name T142
Test name
Test status
Simulation time 4573596237 ps
CPU time 5.47 seconds
Started Jul 06 05:29:57 PM PDT 24
Finished Jul 06 05:30:03 PM PDT 24
Peak memory 213604 kb
Host smart-9f03f944-f2cb-4fd3-a1c1-dc9647df2cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139590913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.4139590913
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1694581340
Short name T15
Test name
Test status
Simulation time 329343360 ps
CPU time 0.83 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:52 PM PDT 24
Peak memory 205092 kb
Host smart-47b5f32c-2599-4aff-89c6-d991ec617887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694581340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1694581340
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1436926616
Short name T152
Test name
Test status
Simulation time 2659830044 ps
CPU time 2.88 seconds
Started Jul 06 05:30:08 PM PDT 24
Finished Jul 06 05:30:11 PM PDT 24
Peak memory 205400 kb
Host smart-9d14b1c4-32b9-4cc4-937b-5c5caf3caa59
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1436926616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.1436926616
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.729596086
Short name T8
Test name
Test status
Simulation time 1505802842 ps
CPU time 4.88 seconds
Started Jul 06 05:30:03 PM PDT 24
Finished Jul 06 05:30:08 PM PDT 24
Peak memory 205004 kb
Host smart-5e14e068-096f-4e34-afcd-0b72502fe4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729596086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.729596086
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.954675764
Short name T148
Test name
Test status
Simulation time 6848972793 ps
CPU time 6.55 seconds
Started Jul 06 05:30:02 PM PDT 24
Finished Jul 06 05:30:09 PM PDT 24
Peak memory 215848 kb
Host smart-ebd03873-c8c3-41d7-90b8-5182311c51ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954675764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.954675764
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.663170372
Short name T154
Test name
Test status
Simulation time 2906472079 ps
CPU time 9.13 seconds
Started Jul 06 05:30:04 PM PDT 24
Finished Jul 06 05:30:13 PM PDT 24
Peak memory 205396 kb
Host smart-f9cbe8f8-78f1-41e2-b7f0-f89ab84b8963
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=663170372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.663170372
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.577946542
Short name T78
Test name
Test status
Simulation time 2267241317 ps
CPU time 2.99 seconds
Started Jul 06 05:30:31 PM PDT 24
Finished Jul 06 05:30:34 PM PDT 24
Peak memory 213628 kb
Host smart-a3dcd8cb-8af7-486b-8b1a-06039722f5a9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=577946542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.577946542
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1820474846
Short name T180
Test name
Test status
Simulation time 3092567481 ps
CPU time 9.26 seconds
Started Jul 06 05:30:23 PM PDT 24
Finished Jul 06 05:30:33 PM PDT 24
Peak memory 205436 kb
Host smart-0da5224d-f57e-4ade-9b8a-6c912196ea6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820474846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1820474846
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2568727423
Short name T179
Test name
Test status
Simulation time 14241375885 ps
CPU time 11.1 seconds
Started Jul 06 05:30:32 PM PDT 24
Finished Jul 06 05:30:43 PM PDT 24
Peak memory 205240 kb
Host smart-b9cc9f57-20ca-4988-bcb5-48ecfdff6a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568727423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2568727423
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1530101867
Short name T181
Test name
Test status
Simulation time 2384505466 ps
CPU time 2.09 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 205388 kb
Host smart-ef311b53-dc4b-404a-ba99-f1c6605c5892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530101867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1530101867
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.3489440765
Short name T17
Test name
Test status
Simulation time 4645189646 ps
CPU time 3.6 seconds
Started Jul 06 05:30:19 PM PDT 24
Finished Jul 06 05:30:23 PM PDT 24
Peak memory 213556 kb
Host smart-f5297177-c0cc-414e-af4f-2128f0e8680f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489440765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.3489440765
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.3936807919
Short name T29
Test name
Test status
Simulation time 10674010054 ps
CPU time 10.97 seconds
Started Jul 06 05:29:57 PM PDT 24
Finished Jul 06 05:30:09 PM PDT 24
Peak memory 205284 kb
Host smart-d97e97d4-b69f-4ac8-b43d-ee4e5c2dcad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936807919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3936807919
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3757329503
Short name T168
Test name
Test status
Simulation time 6617734442 ps
CPU time 20.64 seconds
Started Jul 06 05:30:12 PM PDT 24
Finished Jul 06 05:30:34 PM PDT 24
Peak memory 213556 kb
Host smart-6ee703b0-0000-42ba-a9dd-0beb4aae180b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757329503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3757329503
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.480922532
Short name T34
Test name
Test status
Simulation time 5836354086 ps
CPU time 5.3 seconds
Started Jul 06 05:30:37 PM PDT 24
Finished Jul 06 05:30:43 PM PDT 24
Peak memory 205348 kb
Host smart-bae4fc66-05f5-4813-84fd-47d358aab948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480922532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.480922532
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.942029537
Short name T114
Test name
Test status
Simulation time 16102474834 ps
CPU time 80.93 seconds
Started Jul 06 05:29:19 PM PDT 24
Finished Jul 06 05:30:40 PM PDT 24
Peak memory 213372 kb
Host smart-97fd2493-150f-4140-8ecc-d3517e0e480d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942029537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.942029537
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1116546062
Short name T121
Test name
Test status
Simulation time 6609597681 ps
CPU time 70.1 seconds
Started Jul 06 05:29:15 PM PDT 24
Finished Jul 06 05:30:25 PM PDT 24
Peak memory 205320 kb
Host smart-e9bad417-17d5-47ff-862b-9b6fb35d5c57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116546062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1116546062
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2252540956
Short name T413
Test name
Test status
Simulation time 147932826 ps
CPU time 2.56 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:29:32 PM PDT 24
Peak memory 213428 kb
Host smart-7b4ef383-b177-4ab5-9592-62d14eb32e9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252540956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2252540956
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3597215518
Short name T92
Test name
Test status
Simulation time 1575881551 ps
CPU time 3.77 seconds
Started Jul 06 05:29:32 PM PDT 24
Finished Jul 06 05:29:37 PM PDT 24
Peak memory 221568 kb
Host smart-f35f63af-a6d6-4ad3-aa66-a2f84e5509d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597215518 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3597215518
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1626637196
Short name T416
Test name
Test status
Simulation time 324416080 ps
CPU time 1.62 seconds
Started Jul 06 05:29:33 PM PDT 24
Finished Jul 06 05:29:36 PM PDT 24
Peak memory 213400 kb
Host smart-0985a8ab-41d5-401b-b48d-11e95a4d593f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626637196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1626637196
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3275744428
Short name T310
Test name
Test status
Simulation time 75341492137 ps
CPU time 207.24 seconds
Started Jul 06 05:29:15 PM PDT 24
Finished Jul 06 05:32:43 PM PDT 24
Peak memory 205144 kb
Host smart-6724c76e-34fc-484f-ae13-df8e5265163d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275744428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3275744428
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1266527074
Short name T369
Test name
Test status
Simulation time 34491136679 ps
CPU time 26.17 seconds
Started Jul 06 05:29:19 PM PDT 24
Finished Jul 06 05:29:46 PM PDT 24
Peak memory 205040 kb
Host smart-dd8f0190-5a45-4721-8881-ea7f13edc340
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266527074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.1266527074
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3605930368
Short name T408
Test name
Test status
Simulation time 3790983793 ps
CPU time 3.88 seconds
Started Jul 06 05:29:14 PM PDT 24
Finished Jul 06 05:29:18 PM PDT 24
Peak memory 205040 kb
Host smart-c12a1e6b-e24f-4d53-a09b-1619fd0897eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605930368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
605930368
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1022158083
Short name T365
Test name
Test status
Simulation time 2609395005 ps
CPU time 2.81 seconds
Started Jul 06 05:29:30 PM PDT 24
Finished Jul 06 05:29:34 PM PDT 24
Peak memory 204924 kb
Host smart-abc7b9ec-0507-479e-a4ae-1a1a0d6fede7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022158083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.1022158083
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3393286327
Short name T359
Test name
Test status
Simulation time 1049887287 ps
CPU time 1.58 seconds
Started Jul 06 05:29:39 PM PDT 24
Finished Jul 06 05:29:41 PM PDT 24
Peak memory 204892 kb
Host smart-d812a2a8-499d-4f8c-a3a4-7c2e55f8105e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393286327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3393286327
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4247565575
Short name T338
Test name
Test status
Simulation time 1026180114 ps
CPU time 3.14 seconds
Started Jul 06 05:29:30 PM PDT 24
Finished Jul 06 05:29:35 PM PDT 24
Peak memory 204776 kb
Host smart-690bf887-86d2-4ef8-9720-a6c496cc0a0b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247565575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.4
247565575
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.940319185
Short name T288
Test name
Test status
Simulation time 61163328 ps
CPU time 0.82 seconds
Started Jul 06 05:29:14 PM PDT 24
Finished Jul 06 05:29:15 PM PDT 24
Peak memory 204772 kb
Host smart-36f4cb57-0694-4494-9351-ea28b415ba6e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940319185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.940319185
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1036591150
Short name T321
Test name
Test status
Simulation time 177613851 ps
CPU time 0.78 seconds
Started Jul 06 05:29:27 PM PDT 24
Finished Jul 06 05:29:28 PM PDT 24
Peak memory 204804 kb
Host smart-da4c33ef-9eb7-4771-83a6-52d8a5a55dff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036591150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1036591150
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3056126975
Short name T335
Test name
Test status
Simulation time 431359428 ps
CPU time 3.99 seconds
Started Jul 06 05:29:30 PM PDT 24
Finished Jul 06 05:29:40 PM PDT 24
Peak memory 205176 kb
Host smart-80eda7e6-1dfe-43e0-b168-c900aa0148a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056126975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3056126975
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.550478174
Short name T48
Test name
Test status
Simulation time 23714414216 ps
CPU time 19.23 seconds
Started Jul 06 05:29:14 PM PDT 24
Finished Jul 06 05:29:33 PM PDT 24
Peak memory 220424 kb
Host smart-d3058b15-0426-4e26-9c34-b04cb5993f7d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550478174 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.550478174
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1569638068
Short name T90
Test name
Test status
Simulation time 224721699 ps
CPU time 2.6 seconds
Started Jul 06 05:29:32 PM PDT 24
Finished Jul 06 05:29:36 PM PDT 24
Peak memory 213236 kb
Host smart-1377fdc0-2d65-4e6d-843a-887d6b071b73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569638068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1569638068
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3821947310
Short name T192
Test name
Test status
Simulation time 1610134624 ps
CPU time 17.65 seconds
Started Jul 06 05:29:13 PM PDT 24
Finished Jul 06 05:29:31 PM PDT 24
Peak memory 221596 kb
Host smart-53db22f8-3124-403f-bd8d-42213026cc5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821947310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3821947310
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1642153998
Short name T124
Test name
Test status
Simulation time 6978777110 ps
CPU time 32.15 seconds
Started Jul 06 05:29:32 PM PDT 24
Finished Jul 06 05:30:05 PM PDT 24
Peak memory 213444 kb
Host smart-df9ef933-7a21-4bcb-8b67-13750831abae
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642153998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1642153998
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.201780883
Short name T122
Test name
Test status
Simulation time 5644544827 ps
CPU time 60.15 seconds
Started Jul 06 05:29:35 PM PDT 24
Finished Jul 06 05:30:36 PM PDT 24
Peak memory 205284 kb
Host smart-3d70c6d1-5231-4c13-a263-67b63ea44e93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201780883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.201780883
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1159945340
Short name T129
Test name
Test status
Simulation time 78604167 ps
CPU time 2.43 seconds
Started Jul 06 05:29:23 PM PDT 24
Finished Jul 06 05:29:26 PM PDT 24
Peak memory 213460 kb
Host smart-4597d1b9-484d-424e-bd58-4d8c3af52dd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159945340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1159945340
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2112944384
Short name T419
Test name
Test status
Simulation time 187219803 ps
CPU time 2.43 seconds
Started Jul 06 05:29:25 PM PDT 24
Finished Jul 06 05:29:28 PM PDT 24
Peak memory 213292 kb
Host smart-fad95ffc-49f6-4b8c-ac06-f9e39362dd4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112944384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2112944384
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.46819306
Short name T307
Test name
Test status
Simulation time 88541998750 ps
CPU time 71.19 seconds
Started Jul 06 05:29:14 PM PDT 24
Finished Jul 06 05:30:26 PM PDT 24
Peak memory 205100 kb
Host smart-71090d4c-c034-408e-ba4e-ff4f81d331b4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46819306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_
aliasing.46819306
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4175075846
Short name T421
Test name
Test status
Simulation time 91964326 ps
CPU time 0.68 seconds
Started Jul 06 05:29:36 PM PDT 24
Finished Jul 06 05:29:37 PM PDT 24
Peak memory 204812 kb
Host smart-da7841e9-3d56-46ab-aa0c-d0ce1a165f0e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175075846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.4175075846
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3304009635
Short name T400
Test name
Test status
Simulation time 4546992849 ps
CPU time 15.01 seconds
Started Jul 06 05:29:13 PM PDT 24
Finished Jul 06 05:29:28 PM PDT 24
Peak memory 205104 kb
Host smart-05cf7e5c-2480-414c-b807-3c11f343776f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304009635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3304009635
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2193027807
Short name T363
Test name
Test status
Simulation time 3470589381 ps
CPU time 4.33 seconds
Started Jul 06 05:29:13 PM PDT 24
Finished Jul 06 05:29:17 PM PDT 24
Peak memory 205056 kb
Host smart-ea2bbfe0-e239-4c3a-9fea-df69f71945d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193027807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
193027807
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3645811502
Short name T302
Test name
Test status
Simulation time 452972019 ps
CPU time 1.02 seconds
Started Jul 06 05:29:11 PM PDT 24
Finished Jul 06 05:29:13 PM PDT 24
Peak memory 204836 kb
Host smart-ee29b90f-94ef-4848-95db-f385cb87f87d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645811502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3645811502
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1692318354
Short name T343
Test name
Test status
Simulation time 21495932937 ps
CPU time 40.12 seconds
Started Jul 06 05:29:19 PM PDT 24
Finished Jul 06 05:30:00 PM PDT 24
Peak memory 205016 kb
Host smart-78f3bd9a-51d0-40a1-9eee-8875473f1b68
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692318354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1692318354
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3461567806
Short name T394
Test name
Test status
Simulation time 547651001 ps
CPU time 1.05 seconds
Started Jul 06 05:29:15 PM PDT 24
Finished Jul 06 05:29:16 PM PDT 24
Peak memory 204856 kb
Host smart-300df7f9-481d-4523-9a7d-298ab7d4c5ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461567806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3461567806
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2539228505
Short name T362
Test name
Test status
Simulation time 881839238 ps
CPU time 0.89 seconds
Started Jul 06 05:29:20 PM PDT 24
Finished Jul 06 05:29:21 PM PDT 24
Peak memory 204820 kb
Host smart-f158da8b-a490-4589-ae29-aa1cecad9b86
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539228505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
539228505
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2621463077
Short name T430
Test name
Test status
Simulation time 74930216 ps
CPU time 0.71 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:48 PM PDT 24
Peak memory 204588 kb
Host smart-bf277a7a-1627-4db9-aa43-aa9745c76d6b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621463077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2621463077
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2332712814
Short name T406
Test name
Test status
Simulation time 139451762 ps
CPU time 0.7 seconds
Started Jul 06 05:29:19 PM PDT 24
Finished Jul 06 05:29:20 PM PDT 24
Peak memory 204812 kb
Host smart-6122720d-c02d-4672-a71b-20aaabaeb4c4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332712814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2332712814
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3637090051
Short name T407
Test name
Test status
Simulation time 202415234 ps
CPU time 6.58 seconds
Started Jul 06 05:29:23 PM PDT 24
Finished Jul 06 05:29:30 PM PDT 24
Peak memory 205208 kb
Host smart-a24c3a81-6ed7-400b-a71c-17feb5ed83b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637090051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3637090051
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1238095985
Short name T414
Test name
Test status
Simulation time 58608625141 ps
CPU time 30.41 seconds
Started Jul 06 05:29:33 PM PDT 24
Finished Jul 06 05:30:05 PM PDT 24
Peak memory 229844 kb
Host smart-5f086769-7d1b-48cb-8215-26924541be0a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238095985 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1238095985
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1492291580
Short name T61
Test name
Test status
Simulation time 2574103232 ps
CPU time 5.62 seconds
Started Jul 06 05:29:19 PM PDT 24
Finished Jul 06 05:29:25 PM PDT 24
Peak memory 213404 kb
Host smart-270fb1f8-c283-4342-a394-f06cb1872102
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492291580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1492291580
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2063547685
Short name T191
Test name
Test status
Simulation time 2953246500 ps
CPU time 8.65 seconds
Started Jul 06 05:29:15 PM PDT 24
Finished Jul 06 05:29:24 PM PDT 24
Peak memory 221608 kb
Host smart-5f77e308-3929-4d98-a76b-30ce1b43830b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063547685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2063547685
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2429227679
Short name T334
Test name
Test status
Simulation time 116679702 ps
CPU time 2.34 seconds
Started Jul 06 05:29:31 PM PDT 24
Finished Jul 06 05:29:34 PM PDT 24
Peak memory 217144 kb
Host smart-7c1b8b57-20cb-45fe-875e-25287461d843
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429227679 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2429227679
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3600785974
Short name T126
Test name
Test status
Simulation time 120380431 ps
CPU time 2.45 seconds
Started Jul 06 05:29:31 PM PDT 24
Finished Jul 06 05:29:35 PM PDT 24
Peak memory 213424 kb
Host smart-249486ca-406e-409b-9488-f2c9c129fe2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600785974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3600785974
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3803429111
Short name T320
Test name
Test status
Simulation time 43052102083 ps
CPU time 32.75 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:30:03 PM PDT 24
Peak memory 205088 kb
Host smart-03001b8e-57f1-4a84-a163-a643a210ac89
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803429111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.3803429111
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2214750111
Short name T376
Test name
Test status
Simulation time 1892460611 ps
CPU time 6.11 seconds
Started Jul 06 05:29:43 PM PDT 24
Finished Jul 06 05:29:50 PM PDT 24
Peak memory 205000 kb
Host smart-ce580558-8e6f-4c47-b7e6-cbac4f7ab9a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214750111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2214750111
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1938556561
Short name T403
Test name
Test status
Simulation time 1130123129 ps
CPU time 2 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:49 PM PDT 24
Peak memory 204820 kb
Host smart-3e08e5ec-f9aa-499f-9cc0-45a2a7ff45d9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938556561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1938556561
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2726992628
Short name T117
Test name
Test status
Simulation time 570140333 ps
CPU time 7.67 seconds
Started Jul 06 05:29:51 PM PDT 24
Finished Jul 06 05:30:05 PM PDT 24
Peak memory 205192 kb
Host smart-c96676e7-d5e5-49ea-80bc-df839fe91a43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726992628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2726992628
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3474876210
Short name T402
Test name
Test status
Simulation time 257737993 ps
CPU time 2.6 seconds
Started Jul 06 05:29:28 PM PDT 24
Finished Jul 06 05:29:31 PM PDT 24
Peak memory 213432 kb
Host smart-57bfb15e-d12c-4cf6-87c0-52f067636bbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474876210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3474876210
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3529670155
Short name T353
Test name
Test status
Simulation time 3498233095 ps
CPU time 8.63 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 217668 kb
Host smart-29c0de47-9969-4fc8-8f88-386efaad1820
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529670155 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3529670155
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1773306563
Short name T98
Test name
Test status
Simulation time 168020345 ps
CPU time 1.6 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 213400 kb
Host smart-bae1ffe8-4c29-4235-8068-7c82fd444e56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773306563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1773306563
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4053479250
Short name T297
Test name
Test status
Simulation time 25759086233 ps
CPU time 73.64 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:30:43 PM PDT 24
Peak memory 205092 kb
Host smart-f9262ef0-ccfc-4d62-8b88-899548ec4bf9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053479250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.4053479250
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3041227351
Short name T287
Test name
Test status
Simulation time 2362816747 ps
CPU time 4.21 seconds
Started Jul 06 05:29:28 PM PDT 24
Finished Jul 06 05:29:33 PM PDT 24
Peak memory 205020 kb
Host smart-ccfb3bef-f4aa-4ae1-a107-05002bebaa35
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041227351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3041227351
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2573890739
Short name T295
Test name
Test status
Simulation time 638643270 ps
CPU time 1.16 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:29:32 PM PDT 24
Peak memory 204764 kb
Host smart-ae2b5c21-3c27-480b-9c28-0778e20da3a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573890739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2573890739
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.4265127288
Short name T323
Test name
Test status
Simulation time 576771252 ps
CPU time 3.45 seconds
Started Jul 06 05:29:42 PM PDT 24
Finished Jul 06 05:29:45 PM PDT 24
Peak memory 213360 kb
Host smart-6e5f27a5-cce2-4034-a318-6006202f4756
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265127288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.4265127288
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3385594403
Short name T309
Test name
Test status
Simulation time 400574126 ps
CPU time 4.28 seconds
Started Jul 06 05:29:48 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 219764 kb
Host smart-3608d8bf-20e0-4ed5-8e00-3221a7cccac6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385594403 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3385594403
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1109023423
Short name T100
Test name
Test status
Simulation time 167793437 ps
CPU time 2.39 seconds
Started Jul 06 05:29:43 PM PDT 24
Finished Jul 06 05:29:46 PM PDT 24
Peak memory 213400 kb
Host smart-5a778333-e525-4547-ae46-9f2bef6bced7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109023423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1109023423
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2131906808
Short name T328
Test name
Test status
Simulation time 8521715890 ps
CPU time 7.68 seconds
Started Jul 06 05:29:35 PM PDT 24
Finished Jul 06 05:29:43 PM PDT 24
Peak memory 205052 kb
Host smart-9095a7ae-e1a9-4d2b-bcb1-047152e7abae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131906808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2131906808
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.516300641
Short name T358
Test name
Test status
Simulation time 2895565513 ps
CPU time 3.36 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:50 PM PDT 24
Peak memory 205024 kb
Host smart-c2522d26-56d2-416f-a1f6-c630fff5d520
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516300641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.516300641
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3250084487
Short name T360
Test name
Test status
Simulation time 297677201 ps
CPU time 1.16 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:29:58 PM PDT 24
Peak memory 204816 kb
Host smart-1363b8ff-301b-40c2-8b48-e9e52fab5120
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250084487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3250084487
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1599428674
Short name T391
Test name
Test status
Simulation time 327718184 ps
CPU time 4.24 seconds
Started Jul 06 05:29:51 PM PDT 24
Finished Jul 06 05:29:57 PM PDT 24
Peak memory 205200 kb
Host smart-1546246a-ac7d-4f60-bd4f-6d6352492016
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599428674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1599428674
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2945486860
Short name T371
Test name
Test status
Simulation time 474164573 ps
CPU time 2.83 seconds
Started Jul 06 05:29:45 PM PDT 24
Finished Jul 06 05:29:49 PM PDT 24
Peak memory 213400 kb
Host smart-dc23b1bf-bc3a-42d7-8900-c263ab78b178
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945486860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2945486860
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2164686881
Short name T193
Test name
Test status
Simulation time 3056957530 ps
CPU time 9.48 seconds
Started Jul 06 05:29:52 PM PDT 24
Finished Jul 06 05:30:02 PM PDT 24
Peak memory 213448 kb
Host smart-a4259374-16f6-4bf3-870d-b95161038dc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164686881 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
164686881
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4149892164
Short name T380
Test name
Test status
Simulation time 365305890 ps
CPU time 3.81 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 218904 kb
Host smart-bfa5ce6d-500e-4eab-be13-c15de130264f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149892164 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.4149892164
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.460388789
Short name T372
Test name
Test status
Simulation time 173644154 ps
CPU time 2.37 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:50 PM PDT 24
Peak memory 213416 kb
Host smart-91ea0224-907c-4e2c-aad5-797c41370e0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460388789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.460388789
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2380771467
Short name T367
Test name
Test status
Simulation time 26219816086 ps
CPU time 72.46 seconds
Started Jul 06 05:29:55 PM PDT 24
Finished Jul 06 05:31:08 PM PDT 24
Peak memory 205044 kb
Host smart-a3441210-f99e-4760-b6c9-f3a79902dee7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380771467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2380771467
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3279402844
Short name T374
Test name
Test status
Simulation time 1369037473 ps
CPU time 1.94 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:29:51 PM PDT 24
Peak memory 204960 kb
Host smart-8d3e01ff-1228-402f-b75b-e5bb730b5a26
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279402844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3279402844
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.382530303
Short name T81
Test name
Test status
Simulation time 859802851 ps
CPU time 1.25 seconds
Started Jul 06 05:29:45 PM PDT 24
Finished Jul 06 05:29:47 PM PDT 24
Peak memory 204808 kb
Host smart-334e1216-cd0d-4b59-95b7-8c23e912ce8c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382530303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.382530303
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2903202788
Short name T396
Test name
Test status
Simulation time 189004195 ps
CPU time 6.65 seconds
Started Jul 06 05:29:43 PM PDT 24
Finished Jul 06 05:29:50 PM PDT 24
Peak memory 205196 kb
Host smart-cc70d01d-46db-4f3b-8a1d-6da0abc00dd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903202788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2903202788
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3197228669
Short name T432
Test name
Test status
Simulation time 91202090 ps
CPU time 2.65 seconds
Started Jul 06 05:29:36 PM PDT 24
Finished Jul 06 05:29:39 PM PDT 24
Peak memory 213408 kb
Host smart-3c4d3d21-2405-4d08-85b8-017bf49c7a41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197228669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3197228669
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.492637771
Short name T340
Test name
Test status
Simulation time 7542609920 ps
CPU time 8.66 seconds
Started Jul 06 05:29:46 PM PDT 24
Finished Jul 06 05:29:55 PM PDT 24
Peak memory 221736 kb
Host smart-043407bb-b642-419f-95e5-13e13537fd80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492637771 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.492637771
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3170454766
Short name T112
Test name
Test status
Simulation time 443925187 ps
CPU time 2.29 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:50 PM PDT 24
Peak memory 213292 kb
Host smart-583a64de-6a22-4c42-9b01-271c3f184fd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170454766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3170454766
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.4056606310
Short name T379
Test name
Test status
Simulation time 13688148898 ps
CPU time 35.36 seconds
Started Jul 06 05:29:43 PM PDT 24
Finished Jul 06 05:30:19 PM PDT 24
Peak memory 205064 kb
Host smart-40ae6925-e15b-4390-824a-69a795d9a7d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056606310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.4056606310
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1236952311
Short name T423
Test name
Test status
Simulation time 6641913644 ps
CPU time 20.04 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:30:10 PM PDT 24
Peak memory 204876 kb
Host smart-6f3ec2b5-f4c2-4669-9074-b091dd4cdae4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236952311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1236952311
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2550532746
Short name T291
Test name
Test status
Simulation time 988810531 ps
CPU time 3.04 seconds
Started Jul 06 05:29:44 PM PDT 24
Finished Jul 06 05:29:48 PM PDT 24
Peak memory 204812 kb
Host smart-5057e71e-7221-4372-83f7-57fe2a281a07
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550532746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2550532746
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2533888186
Short name T399
Test name
Test status
Simulation time 179825746 ps
CPU time 6.57 seconds
Started Jul 06 05:30:06 PM PDT 24
Finished Jul 06 05:30:13 PM PDT 24
Peak memory 205240 kb
Host smart-1a8bdfaa-2d86-4c28-9485-4e91069462ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533888186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2533888186
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2451578651
Short name T134
Test name
Test status
Simulation time 125315488 ps
CPU time 2.47 seconds
Started Jul 06 05:29:35 PM PDT 24
Finished Jul 06 05:29:38 PM PDT 24
Peak memory 213364 kb
Host smart-f6e706d6-31be-4b57-9e31-5f33d5ae8382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451578651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2451578651
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.698318228
Short name T185
Test name
Test status
Simulation time 3002708210 ps
CPU time 17.1 seconds
Started Jul 06 05:29:43 PM PDT 24
Finished Jul 06 05:30:01 PM PDT 24
Peak memory 213460 kb
Host smart-980513b5-00c9-4a37-a104-3788661f7e71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698318228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.698318228
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.555290248
Short name T418
Test name
Test status
Simulation time 3722194519 ps
CPU time 7.54 seconds
Started Jul 06 05:29:46 PM PDT 24
Finished Jul 06 05:29:54 PM PDT 24
Peak memory 213400 kb
Host smart-502a7924-7660-4ae0-b5f0-0d7801cc4e6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555290248 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.555290248
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.4146586378
Short name T425
Test name
Test status
Simulation time 174366703 ps
CPU time 2.4 seconds
Started Jul 06 05:29:46 PM PDT 24
Finished Jul 06 05:29:49 PM PDT 24
Peak memory 213404 kb
Host smart-752ed4e1-c23e-4e8c-893d-84569d97a80b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146586378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.4146586378
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.219837808
Short name T324
Test name
Test status
Simulation time 9128919514 ps
CPU time 4.82 seconds
Started Jul 06 05:29:45 PM PDT 24
Finished Jul 06 05:29:51 PM PDT 24
Peak memory 205092 kb
Host smart-68d697c8-3bba-4272-b26d-b3ec4e7a55af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219837808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rv_dm_jtag_dmi_csr_bit_bash.219837808
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3201872082
Short name T305
Test name
Test status
Simulation time 1553369757 ps
CPU time 3.99 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 204992 kb
Host smart-33c1e3b4-cb9f-4edf-a349-c5fba15a83fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201872082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3201872082
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1589458550
Short name T293
Test name
Test status
Simulation time 126861433 ps
CPU time 1.04 seconds
Started Jul 06 05:29:37 PM PDT 24
Finished Jul 06 05:29:39 PM PDT 24
Peak memory 204772 kb
Host smart-2c52e764-c6b4-452c-b432-b0d9806b4f8f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589458550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1589458550
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3954324349
Short name T115
Test name
Test status
Simulation time 563813622 ps
CPU time 6.85 seconds
Started Jul 06 05:29:41 PM PDT 24
Finished Jul 06 05:29:48 PM PDT 24
Peak memory 205180 kb
Host smart-f718b39e-8494-4db4-b8ea-1a76390d1b74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954324349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3954324349
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3899543859
Short name T332
Test name
Test status
Simulation time 178263866 ps
CPU time 4.64 seconds
Started Jul 06 05:29:44 PM PDT 24
Finished Jul 06 05:29:49 PM PDT 24
Peak memory 213396 kb
Host smart-759b5b02-e476-4928-8a7d-f0713604d8e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899543859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3899543859
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2767644023
Short name T91
Test name
Test status
Simulation time 1234230408 ps
CPU time 10.87 seconds
Started Jul 06 05:29:48 PM PDT 24
Finished Jul 06 05:30:00 PM PDT 24
Peak memory 213396 kb
Host smart-394aed74-2c0c-41b9-9206-930c268676eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767644023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
767644023
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2897836669
Short name T348
Test name
Test status
Simulation time 2134303856 ps
CPU time 3.9 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 215172 kb
Host smart-8c55c45d-a394-49d7-bb7d-a095f87ee8c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897836669 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2897836669
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2955542494
Short name T422
Test name
Test status
Simulation time 230281265 ps
CPU time 2.25 seconds
Started Jul 06 05:29:46 PM PDT 24
Finished Jul 06 05:29:54 PM PDT 24
Peak memory 213412 kb
Host smart-9a475d9a-2e57-4189-bc62-8b5e48efd341
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955542494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2955542494
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3266805524
Short name T390
Test name
Test status
Simulation time 5062013579 ps
CPU time 4.46 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:29:54 PM PDT 24
Peak memory 205072 kb
Host smart-f0516cfc-d774-43a5-a633-a4465760eace
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266805524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.3266805524
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.50573035
Short name T290
Test name
Test status
Simulation time 2181400735 ps
CPU time 7.23 seconds
Started Jul 06 05:29:57 PM PDT 24
Finished Jul 06 05:30:05 PM PDT 24
Peak memory 205036 kb
Host smart-295bff23-38bb-419f-ac2e-9e127db488bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50573035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.50573035
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2695585442
Short name T431
Test name
Test status
Simulation time 96642946 ps
CPU time 0.96 seconds
Started Jul 06 05:29:51 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 204828 kb
Host smart-bfa16447-dbab-4993-9fd5-d806105e4ef3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695585442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2695585442
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.559247130
Short name T62
Test name
Test status
Simulation time 932677492 ps
CPU time 7.81 seconds
Started Jul 06 05:29:45 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 205180 kb
Host smart-eeb6b17b-5d6c-4a48-ae4d-f2396f9bb048
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559247130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.559247130
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1584277306
Short name T329
Test name
Test status
Simulation time 59176601 ps
CPU time 2.78 seconds
Started Jul 06 05:29:34 PM PDT 24
Finished Jul 06 05:29:38 PM PDT 24
Peak memory 213440 kb
Host smart-e168c228-3d68-49b5-a425-085b2dc764ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584277306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1584277306
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2865025340
Short name T187
Test name
Test status
Simulation time 1802404067 ps
CPU time 17.19 seconds
Started Jul 06 05:29:51 PM PDT 24
Finished Jul 06 05:30:09 PM PDT 24
Peak memory 213408 kb
Host smart-10f0c2d5-10a4-4a3c-8b1b-43a0e02d4c58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865025340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
865025340
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1098908424
Short name T312
Test name
Test status
Simulation time 3582529170 ps
CPU time 4.7 seconds
Started Jul 06 05:29:55 PM PDT 24
Finished Jul 06 05:30:00 PM PDT 24
Peak memory 221564 kb
Host smart-2c7032f2-e173-4d7f-b7f1-9752ec7debca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098908424 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1098908424
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3361110144
Short name T401
Test name
Test status
Simulation time 173602220 ps
CPU time 1.55 seconds
Started Jul 06 05:29:46 PM PDT 24
Finished Jul 06 05:29:48 PM PDT 24
Peak memory 213408 kb
Host smart-1b409837-4e43-4207-b7ac-4120ee673795
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361110144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3361110144
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3899395212
Short name T415
Test name
Test status
Simulation time 25842723012 ps
CPU time 21.97 seconds
Started Jul 06 05:29:48 PM PDT 24
Finished Jul 06 05:30:10 PM PDT 24
Peak memory 205120 kb
Host smart-b609f27b-e5eb-4315-98c0-465f7dddfe4a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899395212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.3899395212
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2832610804
Short name T350
Test name
Test status
Simulation time 3886832890 ps
CPU time 6 seconds
Started Jul 06 05:29:45 PM PDT 24
Finished Jul 06 05:29:51 PM PDT 24
Peak memory 205000 kb
Host smart-ded3c471-9541-40d1-a4da-f9b465572162
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832610804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2832610804
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2884145636
Short name T326
Test name
Test status
Simulation time 523815646 ps
CPU time 1.59 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:49 PM PDT 24
Peak memory 204796 kb
Host smart-3fb83c6d-c35d-4e1f-b356-3340cc0b6e2c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884145636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2884145636
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2356774313
Short name T94
Test name
Test status
Simulation time 392261661 ps
CPU time 3.85 seconds
Started Jul 06 05:29:51 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 205180 kb
Host smart-191cb8b8-c1f7-4a91-a8ee-7efabd781084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356774313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2356774313
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1026210779
Short name T327
Test name
Test status
Simulation time 836944723 ps
CPU time 5.71 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 213356 kb
Host smart-ec03b278-bda1-4a0d-a262-9aff89d818ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026210779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1026210779
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2299780537
Short name T375
Test name
Test status
Simulation time 2616004158 ps
CPU time 7.62 seconds
Started Jul 06 05:29:52 PM PDT 24
Finished Jul 06 05:30:00 PM PDT 24
Peak memory 219180 kb
Host smart-53378dac-b4b6-4066-a8a8-60de1528c7d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299780537 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2299780537
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2059231209
Short name T409
Test name
Test status
Simulation time 275488993 ps
CPU time 1.62 seconds
Started Jul 06 05:29:45 PM PDT 24
Finished Jul 06 05:29:47 PM PDT 24
Peak memory 213256 kb
Host smart-904177b7-accd-46b3-a118-4b8ba8850074
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059231209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2059231209
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2601982285
Short name T304
Test name
Test status
Simulation time 4977381911 ps
CPU time 4.71 seconds
Started Jul 06 05:29:54 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 205060 kb
Host smart-f57cddf8-aea8-497c-9c9a-d55532ea1e6b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601982285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2601982285
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.4629955
Short name T373
Test name
Test status
Simulation time 9176368641 ps
CPU time 26.75 seconds
Started Jul 06 05:29:57 PM PDT 24
Finished Jul 06 05:30:24 PM PDT 24
Peak memory 205052 kb
Host smart-65bd5038-f00c-46ce-8659-95979b560822
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4629955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.4629955
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1268623416
Short name T345
Test name
Test status
Simulation time 169767615 ps
CPU time 0.91 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:57 PM PDT 24
Peak memory 204828 kb
Host smart-d5941c19-cc1e-4de7-af0f-7311405df429
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268623416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1268623416
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1321897764
Short name T99
Test name
Test status
Simulation time 150537618 ps
CPU time 6.6 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:58 PM PDT 24
Peak memory 205176 kb
Host smart-9cb7361f-8aab-4a58-9bda-4ec0b9b67a22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321897764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1321897764
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1291737521
Short name T104
Test name
Test status
Simulation time 334171212 ps
CPU time 3.99 seconds
Started Jul 06 05:29:48 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 213408 kb
Host smart-f829614a-3ad3-4812-b861-80e9d95a95c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291737521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1291737521
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3286451338
Short name T190
Test name
Test status
Simulation time 1863346268 ps
CPU time 12.35 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:30:09 PM PDT 24
Peak memory 213376 kb
Host smart-58f46185-3ccb-453b-a477-b33c45f16a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286451338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
286451338
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2976714487
Short name T311
Test name
Test status
Simulation time 4320632006 ps
CPU time 5.09 seconds
Started Jul 06 05:30:11 PM PDT 24
Finished Jul 06 05:30:17 PM PDT 24
Peak memory 221704 kb
Host smart-0f5311f7-f152-4c69-a36b-0553e748b38f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976714487 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2976714487
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.207317906
Short name T123
Test name
Test status
Simulation time 183948989 ps
CPU time 2.16 seconds
Started Jul 06 05:29:51 PM PDT 24
Finished Jul 06 05:29:54 PM PDT 24
Peak memory 213432 kb
Host smart-9b42441b-4e3d-4221-85fe-c13582897ec4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207317906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.207317906
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2819336553
Short name T301
Test name
Test status
Simulation time 12595732777 ps
CPU time 8.68 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 205068 kb
Host smart-8d80d4bf-0ad6-458f-b9df-cf7bcd5f6b9b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819336553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2819336553
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1694478990
Short name T397
Test name
Test status
Simulation time 4161055357 ps
CPU time 11.34 seconds
Started Jul 06 05:30:00 PM PDT 24
Finished Jul 06 05:30:12 PM PDT 24
Peak memory 205056 kb
Host smart-9e4b94cf-eed0-48d1-9dde-d6ce03e92c2e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694478990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1694478990
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.4195866529
Short name T346
Test name
Test status
Simulation time 171684408 ps
CPU time 1.04 seconds
Started Jul 06 05:29:43 PM PDT 24
Finished Jul 06 05:29:45 PM PDT 24
Peak memory 204828 kb
Host smart-064d9e7e-5631-47c6-9779-0226b2c91875
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195866529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
4195866529
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1111723327
Short name T116
Test name
Test status
Simulation time 2246416907 ps
CPU time 8 seconds
Started Jul 06 05:29:45 PM PDT 24
Finished Jul 06 05:29:54 PM PDT 24
Peak memory 205288 kb
Host smart-ebb0f269-c651-4ad5-a04e-f00f63bb077e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111723327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1111723327
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1844101676
Short name T388
Test name
Test status
Simulation time 187564779 ps
CPU time 2.8 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 213224 kb
Host smart-792973b9-6938-403e-8f58-a83fb4380cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844101676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1844101676
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3314719600
Short name T84
Test name
Test status
Simulation time 3771405196 ps
CPU time 22.59 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:30:13 PM PDT 24
Peak memory 213404 kb
Host smart-c083a06a-35fa-4f83-9625-48f399e4fa8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314719600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
314719600
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2762549502
Short name T125
Test name
Test status
Simulation time 2449668155 ps
CPU time 26.88 seconds
Started Jul 06 05:29:46 PM PDT 24
Finished Jul 06 05:30:13 PM PDT 24
Peak memory 213512 kb
Host smart-463c2324-77d9-476d-a79b-43cb937f2a7f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762549502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2762549502
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2568949205
Short name T395
Test name
Test status
Simulation time 14960242374 ps
CPU time 73.57 seconds
Started Jul 06 05:29:22 PM PDT 24
Finished Jul 06 05:30:36 PM PDT 24
Peak memory 213440 kb
Host smart-83955f5b-cf92-4189-be8a-e244554e3fee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568949205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2568949205
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.313616594
Short name T308
Test name
Test status
Simulation time 129920485 ps
CPU time 1.55 seconds
Started Jul 06 05:29:25 PM PDT 24
Finished Jul 06 05:29:27 PM PDT 24
Peak memory 213280 kb
Host smart-8e3cd748-4b65-448b-990c-f64b2963e2d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313616594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.313616594
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3252212818
Short name T103
Test name
Test status
Simulation time 138700851 ps
CPU time 3.5 seconds
Started Jul 06 05:29:31 PM PDT 24
Finished Jul 06 05:29:36 PM PDT 24
Peak memory 221612 kb
Host smart-152d89bb-79f8-4607-bcd3-c434fc5c6593
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252212818 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3252212818
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1568932582
Short name T127
Test name
Test status
Simulation time 180571528 ps
CPU time 1.47 seconds
Started Jul 06 05:29:42 PM PDT 24
Finished Jul 06 05:29:44 PM PDT 24
Peak memory 213368 kb
Host smart-7e7380e3-7724-451e-baec-2c046208d5d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568932582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1568932582
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.60268546
Short name T364
Test name
Test status
Simulation time 100876261647 ps
CPU time 29.1 seconds
Started Jul 06 05:29:23 PM PDT 24
Finished Jul 06 05:29:52 PM PDT 24
Peak memory 205060 kb
Host smart-57f20d53-bc74-4d19-b6e2-e6a36e844243
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60268546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_
aliasing.60268546
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2158295196
Short name T315
Test name
Test status
Simulation time 13594326274 ps
CPU time 33.45 seconds
Started Jul 06 05:29:23 PM PDT 24
Finished Jul 06 05:29:57 PM PDT 24
Peak memory 205056 kb
Host smart-d6cb2690-96ba-4a0c-b842-02d8d6a6389c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158295196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.2158295196
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1552659635
Short name T108
Test name
Test status
Simulation time 1351337361 ps
CPU time 4.72 seconds
Started Jul 06 05:29:24 PM PDT 24
Finished Jul 06 05:29:29 PM PDT 24
Peak memory 205160 kb
Host smart-913d3c07-9669-4520-862f-b3862ec82231
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552659635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1552659635
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1731681534
Short name T370
Test name
Test status
Simulation time 1846943793 ps
CPU time 6.31 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:29:36 PM PDT 24
Peak memory 204964 kb
Host smart-e0575660-a944-46a1-a4c1-63d651ee882d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731681534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
731681534
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3009770274
Short name T316
Test name
Test status
Simulation time 323558546 ps
CPU time 0.95 seconds
Started Jul 06 05:29:26 PM PDT 24
Finished Jul 06 05:29:27 PM PDT 24
Peak memory 204756 kb
Host smart-b8a34895-1954-451e-a0a4-a0c182816a60
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009770274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3009770274
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.235764525
Short name T389
Test name
Test status
Simulation time 3941394961 ps
CPU time 10.61 seconds
Started Jul 06 05:29:24 PM PDT 24
Finished Jul 06 05:29:35 PM PDT 24
Peak memory 205056 kb
Host smart-581aed4c-bf01-4e20-be5e-fb78ace40a4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235764525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.235764525
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2630543370
Short name T382
Test name
Test status
Simulation time 516493410 ps
CPU time 1.83 seconds
Started Jul 06 05:29:37 PM PDT 24
Finished Jul 06 05:29:39 PM PDT 24
Peak memory 204888 kb
Host smart-1784867e-6434-4b9a-bb1d-785cde92e1f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630543370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2630543370
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2795001556
Short name T368
Test name
Test status
Simulation time 423452501 ps
CPU time 1.64 seconds
Started Jul 06 05:29:28 PM PDT 24
Finished Jul 06 05:29:31 PM PDT 24
Peak memory 204864 kb
Host smart-118d3383-21d6-4070-af0c-bc6f7c6db31f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795001556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
795001556
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.1346532928
Short name T298
Test name
Test status
Simulation time 89745915 ps
CPU time 0.7 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:48 PM PDT 24
Peak memory 204572 kb
Host smart-b2f222a7-388e-4b12-8b98-5ac890c9326b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346532928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.1346532928
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3090963946
Short name T410
Test name
Test status
Simulation time 90562143 ps
CPU time 0.77 seconds
Started Jul 06 05:29:23 PM PDT 24
Finished Jul 06 05:29:25 PM PDT 24
Peak memory 204788 kb
Host smart-60fe2755-e112-4908-836c-1a20fb9e774c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090963946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3090963946
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3470009253
Short name T387
Test name
Test status
Simulation time 255900158 ps
CPU time 4.1 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:29:35 PM PDT 24
Peak memory 205236 kb
Host smart-86eebeb2-29ef-46ec-ab13-99ea482f33ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470009253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3470009253
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.875790840
Short name T429
Test name
Test status
Simulation time 72889934118 ps
CPU time 188.61 seconds
Started Jul 06 05:29:25 PM PDT 24
Finished Jul 06 05:32:34 PM PDT 24
Peak memory 224556 kb
Host smart-8e66d65b-3e32-4cc5-814d-ca7c319499d7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875790840 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.875790840
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1780811378
Short name T405
Test name
Test status
Simulation time 432619813 ps
CPU time 4.02 seconds
Started Jul 06 05:29:31 PM PDT 24
Finished Jul 06 05:29:36 PM PDT 24
Peak memory 213444 kb
Host smart-20193ace-70ba-4b8e-ab8a-fd94be2dd1fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780811378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1780811378
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2275460502
Short name T113
Test name
Test status
Simulation time 17786691196 ps
CPU time 76.56 seconds
Started Jul 06 05:29:41 PM PDT 24
Finished Jul 06 05:30:58 PM PDT 24
Peak memory 213456 kb
Host smart-337d5a4b-2161-4d3f-9c95-8e1a954eeb2b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275460502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2275460502
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.413353511
Short name T109
Test name
Test status
Simulation time 7808747234 ps
CPU time 56.93 seconds
Started Jul 06 05:29:46 PM PDT 24
Finished Jul 06 05:30:49 PM PDT 24
Peak memory 213492 kb
Host smart-19abd2d1-eb08-4d3d-a7ef-bf26393ea6d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413353511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.413353511
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.60110269
Short name T351
Test name
Test status
Simulation time 356537845 ps
CPU time 1.61 seconds
Started Jul 06 05:29:24 PM PDT 24
Finished Jul 06 05:29:26 PM PDT 24
Peak memory 213404 kb
Host smart-743e6ca2-3ae5-44b5-a77c-4133eb207e3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60110269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.60110269
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2377822253
Short name T378
Test name
Test status
Simulation time 3163663530 ps
CPU time 3.67 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 213352 kb
Host smart-d689c038-9545-4262-a0e3-208caa8eeeec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377822253 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2377822253
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1909178986
Short name T120
Test name
Test status
Simulation time 166806635 ps
CPU time 1.64 seconds
Started Jul 06 05:29:44 PM PDT 24
Finished Jul 06 05:29:46 PM PDT 24
Peak memory 213324 kb
Host smart-799e2a18-abd6-4170-b204-788767561dab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909178986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1909178986
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1100057520
Short name T383
Test name
Test status
Simulation time 17206022302 ps
CPU time 8.02 seconds
Started Jul 06 05:29:28 PM PDT 24
Finished Jul 06 05:29:37 PM PDT 24
Peak memory 205164 kb
Host smart-1a912be7-55cd-498b-8730-080e6d9e81a9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100057520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1100057520
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3140202268
Short name T322
Test name
Test status
Simulation time 38458694503 ps
CPU time 32.56 seconds
Started Jul 06 05:29:19 PM PDT 24
Finished Jul 06 05:29:52 PM PDT 24
Peak memory 205096 kb
Host smart-cfaa50f1-e68d-481c-a900-ddf62fd2f35a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140202268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.3140202268
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2793733905
Short name T106
Test name
Test status
Simulation time 7908873096 ps
CPU time 10.01 seconds
Started Jul 06 05:29:31 PM PDT 24
Finished Jul 06 05:29:42 PM PDT 24
Peak memory 205240 kb
Host smart-5600193c-2f36-4aa0-9473-1986ab799ac6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793733905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2793733905
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1472406568
Short name T339
Test name
Test status
Simulation time 5769313339 ps
CPU time 8.03 seconds
Started Jul 06 05:29:32 PM PDT 24
Finished Jul 06 05:29:41 PM PDT 24
Peak memory 205024 kb
Host smart-cee0a5ae-6948-4958-b144-efa31238a15a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472406568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
472406568
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2687076830
Short name T404
Test name
Test status
Simulation time 785730670 ps
CPU time 1.13 seconds
Started Jul 06 05:29:23 PM PDT 24
Finished Jul 06 05:29:24 PM PDT 24
Peak memory 204796 kb
Host smart-fc8df3f9-5559-403f-ba48-cf53a607319c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687076830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2687076830
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3349136763
Short name T424
Test name
Test status
Simulation time 4084318914 ps
CPU time 4.74 seconds
Started Jul 06 05:29:19 PM PDT 24
Finished Jul 06 05:29:24 PM PDT 24
Peak memory 205084 kb
Host smart-a965d311-28ad-427a-914f-36a533cf818a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349136763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3349136763
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.397397196
Short name T82
Test name
Test status
Simulation time 845732706 ps
CPU time 1.89 seconds
Started Jul 06 05:29:32 PM PDT 24
Finished Jul 06 05:29:35 PM PDT 24
Peak memory 204884 kb
Host smart-c6e6f925-225c-45a9-8be9-d4e358d79307
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397397196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.397397196
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2613727094
Short name T314
Test name
Test status
Simulation time 183178785 ps
CPU time 0.95 seconds
Started Jul 06 05:29:23 PM PDT 24
Finished Jul 06 05:29:24 PM PDT 24
Peak memory 204836 kb
Host smart-4ed5823a-0424-4ffe-a7cf-fbd143f4da39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613727094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
613727094
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3210127377
Short name T289
Test name
Test status
Simulation time 103371855 ps
CPU time 0.93 seconds
Started Jul 06 05:29:37 PM PDT 24
Finished Jul 06 05:29:39 PM PDT 24
Peak memory 204744 kb
Host smart-dc62a363-4886-48ed-a37d-50f24839a6a1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210127377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3210127377
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2884141678
Short name T306
Test name
Test status
Simulation time 64717793 ps
CPU time 0.68 seconds
Started Jul 06 05:29:32 PM PDT 24
Finished Jul 06 05:29:34 PM PDT 24
Peak memory 204820 kb
Host smart-3a075cc1-f847-4384-8ab8-71c1e3736de5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884141678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2884141678
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3728663906
Short name T95
Test name
Test status
Simulation time 1998856690 ps
CPU time 4.3 seconds
Started Jul 06 05:29:30 PM PDT 24
Finished Jul 06 05:29:36 PM PDT 24
Peak memory 205200 kb
Host smart-55b614f9-c94f-41af-a7b6-d8a64542a99b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728663906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3728663906
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2032772964
Short name T325
Test name
Test status
Simulation time 93186093 ps
CPU time 2.7 seconds
Started Jul 06 05:29:20 PM PDT 24
Finished Jul 06 05:29:23 PM PDT 24
Peak memory 213376 kb
Host smart-f4c56f29-9d07-49b6-83ab-d045aa43afb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032772964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2032772964
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1393455390
Short name T184
Test name
Test status
Simulation time 3314469160 ps
CPU time 22.11 seconds
Started Jul 06 05:29:18 PM PDT 24
Finished Jul 06 05:29:41 PM PDT 24
Peak memory 213412 kb
Host smart-3e88233a-fdca-4726-bdbc-17b03f4d4fd3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393455390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1393455390
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.213831587
Short name T398
Test name
Test status
Simulation time 142152728 ps
CPU time 1.67 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:29:32 PM PDT 24
Peak memory 213320 kb
Host smart-bb7f7e9b-73a8-4643-bf73-5e9d9c513209
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213831587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.213831587
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.234901226
Short name T427
Test name
Test status
Simulation time 3503515072 ps
CPU time 5.71 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 220232 kb
Host smart-302990de-23ce-4184-b9e1-b2da7d0ac563
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234901226 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.234901226
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2707728010
Short name T317
Test name
Test status
Simulation time 778537141 ps
CPU time 2.51 seconds
Started Jul 06 05:29:25 PM PDT 24
Finished Jul 06 05:29:28 PM PDT 24
Peak memory 213260 kb
Host smart-cd8f0189-38f3-4b53-a1be-f0ab5e15f208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707728010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2707728010
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2500274449
Short name T318
Test name
Test status
Simulation time 174808405051 ps
CPU time 206.01 seconds
Started Jul 06 05:29:25 PM PDT 24
Finished Jul 06 05:32:52 PM PDT 24
Peak memory 207744 kb
Host smart-148f1afb-3656-4be0-95b0-dc0f97ee012e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500274449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2500274449
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2948422865
Short name T319
Test name
Test status
Simulation time 7251670124 ps
CPU time 8.75 seconds
Started Jul 06 05:29:33 PM PDT 24
Finished Jul 06 05:29:43 PM PDT 24
Peak memory 205044 kb
Host smart-a77102a6-55c3-4317-b8dc-7e1d59975385
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948422865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.2948422865
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3862446581
Short name T105
Test name
Test status
Simulation time 9197509516 ps
CPU time 12.75 seconds
Started Jul 06 05:29:24 PM PDT 24
Finished Jul 06 05:29:38 PM PDT 24
Peak memory 205164 kb
Host smart-799524e2-260f-4976-ace5-285272710b55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862446581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3862446581
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1659635134
Short name T366
Test name
Test status
Simulation time 7097064767 ps
CPU time 5.64 seconds
Started Jul 06 05:29:24 PM PDT 24
Finished Jul 06 05:29:30 PM PDT 24
Peak memory 205032 kb
Host smart-317ae256-40e8-4240-ab47-d5840ff40301
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659635134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
659635134
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2524534156
Short name T333
Test name
Test status
Simulation time 1236237632 ps
CPU time 3.97 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:29:34 PM PDT 24
Peak memory 204788 kb
Host smart-25d05958-5d40-4a2d-baa9-5cfd8783a3b4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524534156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2524534156
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3708383429
Short name T336
Test name
Test status
Simulation time 3866592711 ps
CPU time 3.21 seconds
Started Jul 06 05:29:24 PM PDT 24
Finished Jul 06 05:29:28 PM PDT 24
Peak memory 205096 kb
Host smart-e7b0ccdc-520c-482c-b824-6b6e5565635c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708383429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3708383429
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2312543602
Short name T294
Test name
Test status
Simulation time 433351365 ps
CPU time 0.95 seconds
Started Jul 06 05:29:31 PM PDT 24
Finished Jul 06 05:29:33 PM PDT 24
Peak memory 204856 kb
Host smart-c6257741-2dcc-4ba3-a45c-fabaa96f7c19
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312543602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2312543602
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1626437010
Short name T352
Test name
Test status
Simulation time 663339037 ps
CPU time 1.12 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:29:51 PM PDT 24
Peak memory 204832 kb
Host smart-fd34a713-6b5e-469e-aa53-56ee1836783b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626437010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
626437010
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.190222057
Short name T428
Test name
Test status
Simulation time 43842347 ps
CPU time 0.71 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:29:51 PM PDT 24
Peak memory 204724 kb
Host smart-1e581597-f95e-427a-8094-08b0dcdc6e6d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190222057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.190222057
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1583603798
Short name T292
Test name
Test status
Simulation time 111634170 ps
CPU time 0.78 seconds
Started Jul 06 05:29:24 PM PDT 24
Finished Jul 06 05:29:26 PM PDT 24
Peak memory 204832 kb
Host smart-3d8354bc-7876-4901-b390-0d9a0d09d536
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583603798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1583603798
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3298176095
Short name T342
Test name
Test status
Simulation time 585385073 ps
CPU time 4.52 seconds
Started Jul 06 05:29:33 PM PDT 24
Finished Jul 06 05:29:39 PM PDT 24
Peak memory 205208 kb
Host smart-aa8f6860-9b1a-42a7-acd0-f47f09386079
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298176095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3298176095
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2424266191
Short name T420
Test name
Test status
Simulation time 23115360619 ps
CPU time 38.07 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:30:09 PM PDT 24
Peak memory 219856 kb
Host smart-a9b6bfb8-7b59-44ca-b589-82d0b3bfeb12
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424266191 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2424266191
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2101363365
Short name T412
Test name
Test status
Simulation time 154344787 ps
CPU time 2.67 seconds
Started Jul 06 05:29:34 PM PDT 24
Finished Jul 06 05:29:38 PM PDT 24
Peak memory 213360 kb
Host smart-23724c0c-be29-4a16-8a3b-17fb620bb8d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101363365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2101363365
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3269996484
Short name T83
Test name
Test status
Simulation time 4336318151 ps
CPU time 7.14 seconds
Started Jul 06 05:29:45 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 221592 kb
Host smart-4996f19d-e0bd-4be3-8823-ddf817272dcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269996484 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3269996484
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.124498458
Short name T110
Test name
Test status
Simulation time 90414539 ps
CPU time 2.27 seconds
Started Jul 06 05:29:34 PM PDT 24
Finished Jul 06 05:29:37 PM PDT 24
Peak memory 213316 kb
Host smart-f2e773f2-e8ef-4734-9db0-681c5e11e15d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124498458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.124498458
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3836878815
Short name T296
Test name
Test status
Simulation time 2649001188 ps
CPU time 7.94 seconds
Started Jul 06 05:29:39 PM PDT 24
Finished Jul 06 05:29:48 PM PDT 24
Peak memory 205080 kb
Host smart-0a78a812-e639-4f34-9fb9-8dc04cf7dfa3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836878815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3836878815
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.820990634
Short name T313
Test name
Test status
Simulation time 9231577617 ps
CPU time 8.72 seconds
Started Jul 06 05:29:42 PM PDT 24
Finished Jul 06 05:29:51 PM PDT 24
Peak memory 205008 kb
Host smart-2cfb64df-f8eb-449b-a704-6c6b9bb369ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820990634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.820990634
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3409871754
Short name T385
Test name
Test status
Simulation time 247548156 ps
CPU time 0.97 seconds
Started Jul 06 05:29:26 PM PDT 24
Finished Jul 06 05:29:27 PM PDT 24
Peak memory 204776 kb
Host smart-46e17880-5115-4ecd-9130-0e794d6f6295
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409871754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
409871754
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1336328937
Short name T96
Test name
Test status
Simulation time 1891113321 ps
CPU time 7.9 seconds
Started Jul 06 05:29:39 PM PDT 24
Finished Jul 06 05:29:47 PM PDT 24
Peak memory 205180 kb
Host smart-9650ed89-19c0-4f1e-8d4c-0f29316e65db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336328937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1336328937
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3359232552
Short name T49
Test name
Test status
Simulation time 27056383800 ps
CPU time 14.9 seconds
Started Jul 06 05:29:23 PM PDT 24
Finished Jul 06 05:29:39 PM PDT 24
Peak memory 220856 kb
Host smart-b581c0f9-0b6d-4d8c-b288-f78c8f24314f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359232552 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3359232552
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1945909239
Short name T393
Test name
Test status
Simulation time 172904126 ps
CPU time 4.48 seconds
Started Jul 06 05:29:33 PM PDT 24
Finished Jul 06 05:29:39 PM PDT 24
Peak memory 213332 kb
Host smart-5fd1ac4e-e437-42bc-8473-092a9d5adadc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945909239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1945909239
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2854908789
Short name T344
Test name
Test status
Simulation time 1336616307 ps
CPU time 9.42 seconds
Started Jul 06 05:29:43 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 213388 kb
Host smart-c9f41185-6b08-4648-befa-b50776c15a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854908789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2854908789
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.4141109973
Short name T381
Test name
Test status
Simulation time 206176888 ps
CPU time 2.57 seconds
Started Jul 06 05:29:46 PM PDT 24
Finished Jul 06 05:29:49 PM PDT 24
Peak memory 218704 kb
Host smart-1acd4d5b-37ad-4063-a5c6-b50d1e1e3ea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141109973 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.4141109973
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1277388988
Short name T433
Test name
Test status
Simulation time 317703714 ps
CPU time 2.53 seconds
Started Jul 06 05:29:57 PM PDT 24
Finished Jul 06 05:30:00 PM PDT 24
Peak memory 213456 kb
Host smart-0bada7f4-b068-43c5-86a5-ae13349e3656
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277388988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1277388988
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2549104079
Short name T303
Test name
Test status
Simulation time 6920823641 ps
CPU time 8.79 seconds
Started Jul 06 05:29:36 PM PDT 24
Finished Jul 06 05:29:46 PM PDT 24
Peak memory 205028 kb
Host smart-bdd0d867-d8a2-4745-8be8-170ebceea3e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549104079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.2549104079
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1270033737
Short name T331
Test name
Test status
Simulation time 3035543911 ps
CPU time 2.81 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:29:33 PM PDT 24
Peak memory 204988 kb
Host smart-b3ba02a9-53e4-400a-950f-5ee63a7e09e7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270033737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
270033737
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2424560991
Short name T80
Test name
Test status
Simulation time 543940559 ps
CPU time 1.42 seconds
Started Jul 06 05:29:38 PM PDT 24
Finished Jul 06 05:29:40 PM PDT 24
Peak memory 204772 kb
Host smart-530e789e-1345-4cb2-b009-0cb0752dd9be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424560991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
424560991
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.554255592
Short name T130
Test name
Test status
Simulation time 1059530706 ps
CPU time 4.07 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:55 PM PDT 24
Peak memory 205156 kb
Host smart-0adb0da2-773b-4cfd-89f8-17edcfba2766
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554255592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c
sr_outstanding.554255592
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1654958046
Short name T183
Test name
Test status
Simulation time 383056440 ps
CPU time 4.75 seconds
Started Jul 06 05:29:54 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 213352 kb
Host smart-c4974f34-87ca-41ce-a321-0d44129bd7af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654958046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1654958046
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.4020899964
Short name T87
Test name
Test status
Simulation time 2921634499 ps
CPU time 10.95 seconds
Started Jul 06 05:29:37 PM PDT 24
Finished Jul 06 05:29:48 PM PDT 24
Peak memory 213452 kb
Host smart-4b681299-c7ee-42eb-8e46-296f2c6e32bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020899964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.4020899964
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2530379460
Short name T349
Test name
Test status
Simulation time 120010776 ps
CPU time 3.97 seconds
Started Jul 06 05:29:34 PM PDT 24
Finished Jul 06 05:29:39 PM PDT 24
Peak memory 213404 kb
Host smart-091fea0e-eb04-40f8-9116-ac44ce431819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530379460 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2530379460
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3261290930
Short name T128
Test name
Test status
Simulation time 75046387 ps
CPU time 1.46 seconds
Started Jul 06 05:29:33 PM PDT 24
Finished Jul 06 05:29:36 PM PDT 24
Peak memory 213392 kb
Host smart-47261694-9a6a-4661-b9b7-47548643880d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261290930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3261290930
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.4241128685
Short name T347
Test name
Test status
Simulation time 43256379427 ps
CPU time 96.23 seconds
Started Jul 06 05:29:35 PM PDT 24
Finished Jul 06 05:31:12 PM PDT 24
Peak memory 205036 kb
Host smart-6b2eb0b2-644f-4a4a-96eb-2536eda77830
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241128685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.4241128685
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1183226666
Short name T330
Test name
Test status
Simulation time 1247299104 ps
CPU time 2.49 seconds
Started Jul 06 05:29:34 PM PDT 24
Finished Jul 06 05:29:38 PM PDT 24
Peak memory 204964 kb
Host smart-b6ec2964-4123-43e1-a908-623d733635ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183226666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
183226666
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4009128638
Short name T411
Test name
Test status
Simulation time 192000864 ps
CPU time 1.07 seconds
Started Jul 06 05:29:42 PM PDT 24
Finished Jul 06 05:29:44 PM PDT 24
Peak memory 204772 kb
Host smart-2ff70ac7-72ec-405a-af88-7ba450d6176d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009128638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.4
009128638
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1875714282
Short name T131
Test name
Test status
Simulation time 798866089 ps
CPU time 4.16 seconds
Started Jul 06 05:29:34 PM PDT 24
Finished Jul 06 05:29:39 PM PDT 24
Peak memory 205140 kb
Host smart-60135bd8-26e6-4de4-be25-10837df7a9be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875714282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1875714282
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.223651966
Short name T337
Test name
Test status
Simulation time 60892169122 ps
CPU time 96.38 seconds
Started Jul 06 05:29:43 PM PDT 24
Finished Jul 06 05:31:19 PM PDT 24
Peak memory 221996 kb
Host smart-8c5b90f3-8a28-4012-b10b-ccb9e4b01e23
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223651966 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.223651966
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1751920729
Short name T102
Test name
Test status
Simulation time 223649664 ps
CPU time 5.24 seconds
Started Jul 06 05:29:34 PM PDT 24
Finished Jul 06 05:29:40 PM PDT 24
Peak memory 213332 kb
Host smart-08363297-836d-4e2a-b541-bc005c9c36e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751920729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1751920729
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2933002215
Short name T60
Test name
Test status
Simulation time 1180946721 ps
CPU time 10.59 seconds
Started Jul 06 05:29:36 PM PDT 24
Finished Jul 06 05:29:47 PM PDT 24
Peak memory 221504 kb
Host smart-2ef35b3d-969f-4069-8616-0ad599e26840
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933002215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2933002215
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.67693015
Short name T384
Test name
Test status
Simulation time 824990773 ps
CPU time 4.27 seconds
Started Jul 06 05:29:44 PM PDT 24
Finished Jul 06 05:29:48 PM PDT 24
Peak memory 221636 kb
Host smart-e990359f-b7df-4e64-88fc-f9e3c64e71cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67693015 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.67693015
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3531735833
Short name T341
Test name
Test status
Simulation time 105797808 ps
CPU time 1.43 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:29:31 PM PDT 24
Peak memory 213412 kb
Host smart-24f0ab0c-003f-4946-9312-b25f60340d2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531735833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3531735833
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3255401018
Short name T361
Test name
Test status
Simulation time 4573960062 ps
CPU time 13.86 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:30:04 PM PDT 24
Peak memory 205036 kb
Host smart-f761a091-d3ef-403a-9a2a-034c6dd9272d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255401018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.3255401018
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3444018739
Short name T299
Test name
Test status
Simulation time 1780110756 ps
CPU time 2.51 seconds
Started Jul 06 05:29:42 PM PDT 24
Finished Jul 06 05:29:44 PM PDT 24
Peak memory 204948 kb
Host smart-e74fcb73-e2c1-4c88-83c0-6e67f20f2cdf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444018739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
444018739
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2559379111
Short name T392
Test name
Test status
Simulation time 170933939 ps
CPU time 0.83 seconds
Started Jul 06 05:29:23 PM PDT 24
Finished Jul 06 05:29:24 PM PDT 24
Peak memory 204848 kb
Host smart-f304acee-8a6c-423d-9006-4d4ff53cfa50
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559379111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
559379111
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.485924071
Short name T97
Test name
Test status
Simulation time 1180588246 ps
CPU time 7.8 seconds
Started Jul 06 05:29:30 PM PDT 24
Finished Jul 06 05:29:39 PM PDT 24
Peak memory 205184 kb
Host smart-1b74b62a-7d92-42f9-bb14-de3361da4228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485924071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.485924071
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1891630912
Short name T386
Test name
Test status
Simulation time 62721321980 ps
CPU time 53.08 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:30:44 PM PDT 24
Peak memory 229816 kb
Host smart-938e69ab-5019-40f9-a30c-d82c86d84569
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891630912 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1891630912
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3803183454
Short name T357
Test name
Test status
Simulation time 196291546 ps
CPU time 3.91 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:30:00 PM PDT 24
Peak memory 213476 kb
Host smart-de61df58-d806-4a6e-874e-513e255260ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803183454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3803183454
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2692531961
Short name T194
Test name
Test status
Simulation time 1786680396 ps
CPU time 9.49 seconds
Started Jul 06 05:29:33 PM PDT 24
Finished Jul 06 05:29:44 PM PDT 24
Peak memory 213408 kb
Host smart-b8aed600-1858-4c80-96e5-d0c902d00457
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692531961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2692531961
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3423377485
Short name T58
Test name
Test status
Simulation time 340700625 ps
CPU time 2.44 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:50 PM PDT 24
Peak memory 213408 kb
Host smart-1a76b3c0-360d-47e0-bf4c-1b59070a73e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423377485 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3423377485
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3301672923
Short name T119
Test name
Test status
Simulation time 424894124 ps
CPU time 2.41 seconds
Started Jul 06 05:29:31 PM PDT 24
Finished Jul 06 05:29:35 PM PDT 24
Peak memory 213400 kb
Host smart-bfdccf62-98d8-4110-b27d-09af5356f182
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301672923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3301672923
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2828561335
Short name T417
Test name
Test status
Simulation time 13038340341 ps
CPU time 6.56 seconds
Started Jul 06 05:29:43 PM PDT 24
Finished Jul 06 05:29:50 PM PDT 24
Peak memory 205060 kb
Host smart-83ba7903-afb5-432a-a97b-5a95d216a811
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828561335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2828561335
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1281516390
Short name T426
Test name
Test status
Simulation time 2542026028 ps
CPU time 2.6 seconds
Started Jul 06 05:29:52 PM PDT 24
Finished Jul 06 05:29:55 PM PDT 24
Peak memory 204972 kb
Host smart-b35df924-da9a-4617-b0cc-cc742290a9f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281516390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
281516390
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.650034949
Short name T377
Test name
Test status
Simulation time 163402365 ps
CPU time 0.85 seconds
Started Jul 06 05:29:48 PM PDT 24
Finished Jul 06 05:29:49 PM PDT 24
Peak memory 204864 kb
Host smart-eb085b94-f882-405a-922c-8ab89433f3f0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650034949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.650034949
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3699586417
Short name T101
Test name
Test status
Simulation time 97714686 ps
CPU time 3.61 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:29:33 PM PDT 24
Peak memory 205280 kb
Host smart-66f4452a-3db4-480c-9cd3-aeeda508777a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699586417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3699586417
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2056581636
Short name T356
Test name
Test status
Simulation time 27733989413 ps
CPU time 62.06 seconds
Started Jul 06 05:29:31 PM PDT 24
Finished Jul 06 05:30:34 PM PDT 24
Peak memory 221624 kb
Host smart-aa8c2d08-b76a-4e6a-ac48-7efdf3951370
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056581636 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2056581636
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.4127539635
Short name T355
Test name
Test status
Simulation time 157588679 ps
CPU time 4.03 seconds
Started Jul 06 05:29:29 PM PDT 24
Finished Jul 06 05:29:34 PM PDT 24
Peak memory 221524 kb
Host smart-3d5c517b-1117-407d-8044-f4d489aa8e20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127539635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.4127539635
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.623101660
Short name T189
Test name
Test status
Simulation time 1205967497 ps
CPU time 18.18 seconds
Started Jul 06 05:29:31 PM PDT 24
Finished Jul 06 05:29:55 PM PDT 24
Peak memory 213416 kb
Host smart-f4589ab7-db7d-4c29-9c4d-26f3b78806e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623101660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.623101660
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3435983978
Short name T285
Test name
Test status
Simulation time 109071016 ps
CPU time 0.76 seconds
Started Jul 06 05:29:51 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 205120 kb
Host smart-dabdab38-814e-4ef0-88e7-b031eb91e66d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435983978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3435983978
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3942992628
Short name T156
Test name
Test status
Simulation time 16697289971 ps
CPU time 13.14 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:30:02 PM PDT 24
Peak memory 213612 kb
Host smart-057ea6c3-e062-4203-a50c-1521a2700703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942992628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3942992628
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3990129630
Short name T283
Test name
Test status
Simulation time 4176933430 ps
CPU time 4.72 seconds
Started Jul 06 05:29:57 PM PDT 24
Finished Jul 06 05:30:03 PM PDT 24
Peak memory 213596 kb
Host smart-f268ec53-6cae-4410-ab1f-a162fd9e3766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990129630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3990129630
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2899044922
Short name T198
Test name
Test status
Simulation time 181245330 ps
CPU time 1.15 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:29:51 PM PDT 24
Peak memory 205128 kb
Host smart-a096a263-0868-49f8-be20-248b480a90e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899044922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2899044922
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3596433632
Short name T199
Test name
Test status
Simulation time 498356047 ps
CPU time 0.77 seconds
Started Jul 06 05:29:48 PM PDT 24
Finished Jul 06 05:29:49 PM PDT 24
Peak memory 205104 kb
Host smart-42dd7b56-21b8-4956-a663-c17e8c1b0467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596433632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3596433632
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1009750577
Short name T64
Test name
Test status
Simulation time 2115898839 ps
CPU time 7.12 seconds
Started Jul 06 05:29:57 PM PDT 24
Finished Jul 06 05:30:05 PM PDT 24
Peak memory 213584 kb
Host smart-2d8bf4f7-0562-4a69-8aab-43a61c300137
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1009750577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1009750577
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2556165678
Short name T26
Test name
Test status
Simulation time 440793163 ps
CPU time 1.91 seconds
Started Jul 06 05:29:55 PM PDT 24
Finished Jul 06 05:29:57 PM PDT 24
Peak memory 205108 kb
Host smart-3bcf7765-e8bf-4925-ac63-31a65179e453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556165678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2556165678
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.626723924
Short name T280
Test name
Test status
Simulation time 907349713 ps
CPU time 2.09 seconds
Started Jul 06 05:29:48 PM PDT 24
Finished Jul 06 05:29:51 PM PDT 24
Peak memory 204988 kb
Host smart-82b6b91e-4b7b-489d-803b-45bbae104fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626723924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.626723924
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2966901363
Short name T281
Test name
Test status
Simulation time 2844979054 ps
CPU time 8.44 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 205096 kb
Host smart-739f08f0-73a9-4e3e-a99a-6ab7b98e808f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966901363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2966901363
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2772101666
Short name T144
Test name
Test status
Simulation time 283757966 ps
CPU time 1.26 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:49 PM PDT 24
Peak memory 205068 kb
Host smart-73603866-93d4-4172-afc0-fa930ab68e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772101666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2772101666
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3559313292
Short name T71
Test name
Test status
Simulation time 1437671583 ps
CPU time 1.85 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:29:51 PM PDT 24
Peak memory 205080 kb
Host smart-ca2f4e5c-fdab-49a1-a580-3d64ece5e94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559313292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3559313292
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.477349862
Short name T3
Test name
Test status
Simulation time 191124404 ps
CPU time 1.02 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:49 PM PDT 24
Peak memory 205072 kb
Host smart-c20b66b6-e762-4d10-807f-a49bab283801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477349862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.477349862
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1670923221
Short name T43
Test name
Test status
Simulation time 646797981 ps
CPU time 1.5 seconds
Started Jul 06 05:29:59 PM PDT 24
Finished Jul 06 05:30:01 PM PDT 24
Peak memory 205096 kb
Host smart-c483121b-02ae-4edf-a83c-cc53f11f6d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670923221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1670923221
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2613289642
Short name T35
Test name
Test status
Simulation time 184605937 ps
CPU time 0.86 seconds
Started Jul 06 05:29:57 PM PDT 24
Finished Jul 06 05:29:58 PM PDT 24
Peak memory 213380 kb
Host smart-14586ec2-1b3b-4c22-a03c-e5da3d530d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613289642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2613289642
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3762209427
Short name T207
Test name
Test status
Simulation time 2291405412 ps
CPU time 8 seconds
Started Jul 06 05:29:44 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 205620 kb
Host smart-1b303f5c-e29d-4e4b-9077-ade0cb7efe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762209427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3762209427
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1577884106
Short name T41
Test name
Test status
Simulation time 2513287647 ps
CPU time 5.12 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:57 PM PDT 24
Peak memory 205148 kb
Host smart-9dad449b-3d61-4928-a13c-165ad9e35fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577884106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1577884106
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.3838970059
Short name T160
Test name
Test status
Simulation time 10422373070 ps
CPU time 9.21 seconds
Started Jul 06 05:29:57 PM PDT 24
Finished Jul 06 05:30:07 PM PDT 24
Peak memory 213580 kb
Host smart-065e280e-15e9-4485-aac3-58d06523c749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838970059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.3838970059
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3830485715
Short name T38
Test name
Test status
Simulation time 496870689 ps
CPU time 2.14 seconds
Started Jul 06 05:29:51 PM PDT 24
Finished Jul 06 05:29:55 PM PDT 24
Peak memory 205104 kb
Host smart-43f3ab7c-fc81-458a-a571-e7c2ada6b1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830485715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3830485715
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.544013447
Short name T206
Test name
Test status
Simulation time 65298540 ps
CPU time 0.74 seconds
Started Jul 06 05:30:04 PM PDT 24
Finished Jul 06 05:30:10 PM PDT 24
Peak memory 205064 kb
Host smart-590f8135-569c-444d-9657-af7c2793966b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544013447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.544013447
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.834791121
Short name T20
Test name
Test status
Simulation time 5288417063 ps
CPU time 15.27 seconds
Started Jul 06 05:29:53 PM PDT 24
Finished Jul 06 05:30:09 PM PDT 24
Peak memory 205396 kb
Host smart-45a93cac-6751-43ae-ad76-dfeaea8ac34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834791121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.834791121
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3677860904
Short name T32
Test name
Test status
Simulation time 1252022239 ps
CPU time 1.41 seconds
Started Jul 06 05:29:51 PM PDT 24
Finished Jul 06 05:29:54 PM PDT 24
Peak memory 205052 kb
Host smart-1b2db5b4-0f9d-4550-8b00-a232573048eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677860904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3677860904
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3305225222
Short name T7
Test name
Test status
Simulation time 255953669 ps
CPU time 0.85 seconds
Started Jul 06 05:29:51 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 205108 kb
Host smart-e8a9308c-1f1f-4954-9c31-aeb95198e069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305225222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3305225222
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.227834245
Short name T31
Test name
Test status
Simulation time 70365083 ps
CPU time 0.86 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:29:57 PM PDT 24
Peak memory 205024 kb
Host smart-5ba74d25-19a1-4e60-8593-a89c9e424ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227834245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.227834245
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.2048602572
Short name T53
Test name
Test status
Simulation time 31152694 ps
CPU time 0.89 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:57 PM PDT 24
Peak memory 215700 kb
Host smart-02e99e4c-95e7-4891-881d-80ea98884f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048602572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2048602572
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.4189549504
Short name T67
Test name
Test status
Simulation time 739150662 ps
CPU time 1.7 seconds
Started Jul 06 05:29:53 PM PDT 24
Finished Jul 06 05:30:00 PM PDT 24
Peak memory 205032 kb
Host smart-97571b9a-dce8-46a4-b934-750de4f24d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189549504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.4189549504
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.608161801
Short name T273
Test name
Test status
Simulation time 91697109 ps
CPU time 0.72 seconds
Started Jul 06 05:29:58 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 205088 kb
Host smart-966022d9-d048-4c51-9473-594214c9cb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608161801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.608161801
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.708108483
Short name T276
Test name
Test status
Simulation time 1085954471 ps
CPU time 2.01 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:54 PM PDT 24
Peak memory 204940 kb
Host smart-3b0d7410-fe4f-4b95-aa73-f2c9b5ce05ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708108483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.708108483
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.590630784
Short name T27
Test name
Test status
Simulation time 1094197253 ps
CPU time 0.85 seconds
Started Jul 06 05:29:57 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 205008 kb
Host smart-2b1acfe1-2498-42d2-a312-128ac2f0ea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590630784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.590630784
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1825864455
Short name T229
Test name
Test status
Simulation time 140624724 ps
CPU time 0.73 seconds
Started Jul 06 05:29:47 PM PDT 24
Finished Jul 06 05:29:48 PM PDT 24
Peak memory 205108 kb
Host smart-31939f8c-1875-4498-a2fa-2242f8048c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825864455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1825864455
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1877803794
Short name T257
Test name
Test status
Simulation time 178477065 ps
CPU time 1.17 seconds
Started Jul 06 05:29:58 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 205108 kb
Host smart-0ce14134-e502-4648-965a-4be9718618ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877803794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1877803794
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2385794756
Short name T149
Test name
Test status
Simulation time 781790973 ps
CPU time 2.55 seconds
Started Jul 06 05:29:49 PM PDT 24
Finished Jul 06 05:29:52 PM PDT 24
Peak memory 205036 kb
Host smart-9bd3a807-d4c3-4c3d-921a-8610d3c88906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385794756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2385794756
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.808321452
Short name T19
Test name
Test status
Simulation time 979867897 ps
CPU time 1.38 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 205044 kb
Host smart-95725451-e97d-4f57-875c-fa4c6699346c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808321452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.808321452
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1498511439
Short name T215
Test name
Test status
Simulation time 1385786813 ps
CPU time 4.64 seconds
Started Jul 06 05:29:51 PM PDT 24
Finished Jul 06 05:29:57 PM PDT 24
Peak memory 205556 kb
Host smart-a2c146ce-ba83-477e-a691-15c6238e8ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498511439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1498511439
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2179680230
Short name T55
Test name
Test status
Simulation time 461744023 ps
CPU time 2.01 seconds
Started Jul 06 05:29:57 PM PDT 24
Finished Jul 06 05:30:00 PM PDT 24
Peak memory 229572 kb
Host smart-06ba2c7a-5f23-4c7b-bddf-70ea67c53cf0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179680230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2179680230
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.4235766560
Short name T51
Test name
Test status
Simulation time 1670996177 ps
CPU time 4.92 seconds
Started Jul 06 05:29:50 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 205292 kb
Host smart-d4570b3f-fadf-44fb-8b99-7855e19d9553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235766560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.4235766560
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.2703095451
Short name T24
Test name
Test status
Simulation time 6021119890 ps
CPU time 10.86 seconds
Started Jul 06 05:30:03 PM PDT 24
Finished Jul 06 05:30:14 PM PDT 24
Peak memory 205252 kb
Host smart-560d12d0-030f-4f06-9cb3-bd4ab4fae8b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703095451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2703095451
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3455469462
Short name T231
Test name
Test status
Simulation time 148076916 ps
CPU time 0.72 seconds
Started Jul 06 05:30:05 PM PDT 24
Finished Jul 06 05:30:06 PM PDT 24
Peak memory 205124 kb
Host smart-2ccb8658-248c-497c-aa39-dabe8140732e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455469462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3455469462
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3073375766
Short name T203
Test name
Test status
Simulation time 8100801075 ps
CPU time 21.79 seconds
Started Jul 06 05:30:13 PM PDT 24
Finished Jul 06 05:30:35 PM PDT 24
Peak memory 213628 kb
Host smart-a216737a-a6ed-4ddd-9ab7-b21b47e1bec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073375766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3073375766
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.4290943843
Short name T247
Test name
Test status
Simulation time 3755692935 ps
CPU time 5.81 seconds
Started Jul 06 05:30:03 PM PDT 24
Finished Jul 06 05:30:09 PM PDT 24
Peak memory 213664 kb
Host smart-daae806b-8b81-4e6d-ab90-aa91e0cdb617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290943843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.4290943843
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1332258434
Short name T225
Test name
Test status
Simulation time 16005374527 ps
CPU time 6.25 seconds
Started Jul 06 05:30:18 PM PDT 24
Finished Jul 06 05:30:25 PM PDT 24
Peak memory 213596 kb
Host smart-75d123ee-3ddc-4c57-97d9-9b87950f7af7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332258434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1332258434
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.689650016
Short name T227
Test name
Test status
Simulation time 13458729315 ps
CPU time 33.11 seconds
Started Jul 06 05:30:09 PM PDT 24
Finished Jul 06 05:30:43 PM PDT 24
Peak memory 205372 kb
Host smart-62978e46-2dc6-4666-915a-ee9a66863f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689650016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.689650016
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.2467247366
Short name T69
Test name
Test status
Simulation time 2813680919 ps
CPU time 8.26 seconds
Started Jul 06 05:30:15 PM PDT 24
Finished Jul 06 05:30:24 PM PDT 24
Peak memory 213576 kb
Host smart-4cf9f541-794b-4e70-a423-562fa5a67153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467247366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2467247366
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.490268358
Short name T44
Test name
Test status
Simulation time 78060034 ps
CPU time 0.74 seconds
Started Jul 06 05:30:09 PM PDT 24
Finished Jul 06 05:30:10 PM PDT 24
Peak memory 205084 kb
Host smart-c6043b5a-24f6-4e7b-aa39-b283303c4a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490268358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.490268358
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1582782918
Short name T137
Test name
Test status
Simulation time 78132888110 ps
CPU time 49.63 seconds
Started Jul 06 05:30:00 PM PDT 24
Finished Jul 06 05:30:50 PM PDT 24
Peak memory 216892 kb
Host smart-5a228a71-52f7-4a6e-939a-2ed5f9e7484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582782918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1582782918
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.420791522
Short name T262
Test name
Test status
Simulation time 6317453741 ps
CPU time 17.3 seconds
Started Jul 06 05:30:03 PM PDT 24
Finished Jul 06 05:30:20 PM PDT 24
Peak memory 205396 kb
Host smart-6fb90e7c-97b9-4084-8713-20e5963889d5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=420791522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.420791522
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3033192691
Short name T73
Test name
Test status
Simulation time 828805184 ps
CPU time 3.06 seconds
Started Jul 06 05:30:20 PM PDT 24
Finished Jul 06 05:30:24 PM PDT 24
Peak memory 205316 kb
Host smart-03f36dc7-5e3c-44de-bb73-72e898eed17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033192691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3033192691
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.630597650
Short name T169
Test name
Test status
Simulation time 7755655519 ps
CPU time 20.18 seconds
Started Jul 06 05:30:06 PM PDT 24
Finished Jul 06 05:30:26 PM PDT 24
Peak memory 205276 kb
Host smart-1dbe5b7a-16be-4a0b-b561-2f59a6718040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630597650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.630597650
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3987450931
Short name T76
Test name
Test status
Simulation time 227914960 ps
CPU time 0.76 seconds
Started Jul 06 05:30:18 PM PDT 24
Finished Jul 06 05:30:19 PM PDT 24
Peak memory 204904 kb
Host smart-e66ef92f-3076-4751-a466-8158a19a41a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987450931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3987450931
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2144561592
Short name T145
Test name
Test status
Simulation time 6393604716 ps
CPU time 13.01 seconds
Started Jul 06 05:30:05 PM PDT 24
Finished Jul 06 05:30:19 PM PDT 24
Peak memory 213704 kb
Host smart-e612d999-1004-4e09-bcf3-d49f62ab8bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144561592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2144561592
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1772137243
Short name T155
Test name
Test status
Simulation time 4360755751 ps
CPU time 6.17 seconds
Started Jul 06 05:30:09 PM PDT 24
Finished Jul 06 05:30:15 PM PDT 24
Peak memory 213632 kb
Host smart-0b3096df-b384-466b-b63d-066a78553eaf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1772137243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1772137243
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2804846741
Short name T177
Test name
Test status
Simulation time 8583529561 ps
CPU time 15.65 seconds
Started Jul 06 05:30:14 PM PDT 24
Finished Jul 06 05:30:31 PM PDT 24
Peak memory 213472 kb
Host smart-9e6f4d46-1b22-4bb0-8f10-ddec0ced4140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804846741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2804846741
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.6532198
Short name T174
Test name
Test status
Simulation time 11000307415 ps
CPU time 21.7 seconds
Started Jul 06 05:30:21 PM PDT 24
Finished Jul 06 05:30:43 PM PDT 24
Peak memory 213372 kb
Host smart-69f04a20-ecf0-4eca-bed6-cbf5f575cbc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6532198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.6532198
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.752839543
Short name T265
Test name
Test status
Simulation time 79864251 ps
CPU time 0.86 seconds
Started Jul 06 05:30:07 PM PDT 24
Finished Jul 06 05:30:08 PM PDT 24
Peak memory 205116 kb
Host smart-887ddc45-87e7-478d-a267-c1ccd627d170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752839543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.752839543
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2332178195
Short name T254
Test name
Test status
Simulation time 1550958669 ps
CPU time 2.4 seconds
Started Jul 06 05:30:14 PM PDT 24
Finished Jul 06 05:30:17 PM PDT 24
Peak memory 213608 kb
Host smart-a498d3a0-0c57-4a28-82a6-b5355aab96ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332178195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2332178195
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.555016507
Short name T277
Test name
Test status
Simulation time 1743268774 ps
CPU time 2.92 seconds
Started Jul 06 05:30:23 PM PDT 24
Finished Jul 06 05:30:26 PM PDT 24
Peak memory 213588 kb
Host smart-8bfd14eb-0c85-466a-a1fd-80d357c2b947
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=555016507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_t
l_access.555016507
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.156288127
Short name T284
Test name
Test status
Simulation time 3412040698 ps
CPU time 2.46 seconds
Started Jul 06 05:30:08 PM PDT 24
Finished Jul 06 05:30:11 PM PDT 24
Peak memory 213628 kb
Host smart-b8ca8056-35eb-4e6d-b148-bd188961114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156288127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.156288127
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.215427529
Short name T50
Test name
Test status
Simulation time 9529237710 ps
CPU time 14.07 seconds
Started Jul 06 05:30:09 PM PDT 24
Finished Jul 06 05:30:24 PM PDT 24
Peak memory 213468 kb
Host smart-5f3eca5a-b528-4b50-a4b9-dcfb3a7d54c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215427529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.215427529
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1842495336
Short name T267
Test name
Test status
Simulation time 54247750 ps
CPU time 0.73 seconds
Started Jul 06 05:30:11 PM PDT 24
Finished Jul 06 05:30:12 PM PDT 24
Peak memory 205092 kb
Host smart-5dc4aed3-44f5-4de1-a3f7-87e566cf52b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842495336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1842495336
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2800254808
Short name T150
Test name
Test status
Simulation time 13289843824 ps
CPU time 36.82 seconds
Started Jul 06 05:30:18 PM PDT 24
Finished Jul 06 05:30:56 PM PDT 24
Peak memory 213608 kb
Host smart-8cc17e66-d5c8-4a2e-a1f6-86db6f816ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800254808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2800254808
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2112559174
Short name T279
Test name
Test status
Simulation time 1663855757 ps
CPU time 2.66 seconds
Started Jul 06 05:30:06 PM PDT 24
Finished Jul 06 05:30:09 PM PDT 24
Peak memory 213464 kb
Host smart-d8f9f229-3721-4b88-9083-80dceb27317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112559174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2112559174
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1970880376
Short name T182
Test name
Test status
Simulation time 1863902355 ps
CPU time 2.37 seconds
Started Jul 06 05:30:24 PM PDT 24
Finished Jul 06 05:30:27 PM PDT 24
Peak memory 205472 kb
Host smart-00e03648-9687-46a8-8a84-3d2611af6e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970880376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1970880376
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.2833555165
Short name T16
Test name
Test status
Simulation time 3486524151 ps
CPU time 5.91 seconds
Started Jul 06 05:30:05 PM PDT 24
Finished Jul 06 05:30:12 PM PDT 24
Peak memory 205324 kb
Host smart-54295f74-6c57-4778-a439-744a1b37efca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833555165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.2833555165
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2605126489
Short name T216
Test name
Test status
Simulation time 45297872 ps
CPU time 0.79 seconds
Started Jul 06 05:30:28 PM PDT 24
Finished Jul 06 05:30:29 PM PDT 24
Peak memory 205084 kb
Host smart-339d01e6-0c7e-413e-86b9-5a6f93c3a4ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605126489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2605126489
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2805124570
Short name T74
Test name
Test status
Simulation time 6437077826 ps
CPU time 16.18 seconds
Started Jul 06 05:30:09 PM PDT 24
Finished Jul 06 05:30:25 PM PDT 24
Peak memory 215708 kb
Host smart-0bee347f-fa22-40ee-972e-65cecab0ca4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805124570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2805124570
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.364622552
Short name T143
Test name
Test status
Simulation time 4862119442 ps
CPU time 9.28 seconds
Started Jul 06 05:30:15 PM PDT 24
Finished Jul 06 05:30:25 PM PDT 24
Peak memory 213592 kb
Host smart-30b1364c-68f5-45f6-af5f-62a8b27e43e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364622552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.364622552
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2540729334
Short name T250
Test name
Test status
Simulation time 8422316524 ps
CPU time 14.63 seconds
Started Jul 06 05:30:05 PM PDT 24
Finished Jul 06 05:30:20 PM PDT 24
Peak memory 205428 kb
Host smart-05ed42ce-1258-47ab-b17a-e2d48fc11862
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540729334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2540729334
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1960427887
Short name T176
Test name
Test status
Simulation time 5040627721 ps
CPU time 12.26 seconds
Started Jul 06 05:30:10 PM PDT 24
Finished Jul 06 05:30:23 PM PDT 24
Peak memory 205368 kb
Host smart-b27de940-e210-4d73-b8d0-f2f98f2d74f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960427887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1960427887
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.4207431083
Short name T228
Test name
Test status
Simulation time 69398186 ps
CPU time 0.74 seconds
Started Jul 06 05:30:28 PM PDT 24
Finished Jul 06 05:30:29 PM PDT 24
Peak memory 205096 kb
Host smart-a622d686-c2bd-4714-a558-5165c6645e94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207431083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.4207431083
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1950159254
Short name T70
Test name
Test status
Simulation time 7493647463 ps
CPU time 6.23 seconds
Started Jul 06 05:30:16 PM PDT 24
Finished Jul 06 05:30:23 PM PDT 24
Peak memory 213600 kb
Host smart-5f027310-6ee3-4ad9-81a1-79fdf83b8bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950159254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1950159254
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1341739162
Short name T258
Test name
Test status
Simulation time 9717861612 ps
CPU time 27.47 seconds
Started Jul 06 05:30:10 PM PDT 24
Finished Jul 06 05:30:38 PM PDT 24
Peak memory 214940 kb
Host smart-6d131ad7-c584-48a1-8f9e-92ccf990a114
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1341739162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1341739162
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.4234502806
Short name T259
Test name
Test status
Simulation time 31067933 ps
CPU time 0.76 seconds
Started Jul 06 05:30:41 PM PDT 24
Finished Jul 06 05:30:44 PM PDT 24
Peak memory 205084 kb
Host smart-1582d2e7-6f48-42b0-84b0-d03c39729633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234502806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.4234502806
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1421823828
Short name T214
Test name
Test status
Simulation time 9955362540 ps
CPU time 5.74 seconds
Started Jul 06 05:30:26 PM PDT 24
Finished Jul 06 05:30:32 PM PDT 24
Peak memory 213588 kb
Host smart-1992d5a7-e762-4f9a-9d61-b416d1fab6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421823828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1421823828
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.257374767
Short name T251
Test name
Test status
Simulation time 2704346408 ps
CPU time 8 seconds
Started Jul 06 05:30:10 PM PDT 24
Finished Jul 06 05:30:18 PM PDT 24
Peak memory 213620 kb
Host smart-eb2c3450-e29d-4f87-8a81-956836506a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257374767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.257374767
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.787553766
Short name T13
Test name
Test status
Simulation time 2623501547 ps
CPU time 2.47 seconds
Started Jul 06 05:30:08 PM PDT 24
Finished Jul 06 05:30:10 PM PDT 24
Peak memory 213688 kb
Host smart-32c1d10e-e7ec-4e9e-a829-cfd7a2f5a2d7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787553766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.787553766
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.2993423531
Short name T263
Test name
Test status
Simulation time 2205501550 ps
CPU time 4.53 seconds
Started Jul 06 05:30:17 PM PDT 24
Finished Jul 06 05:30:22 PM PDT 24
Peak memory 213616 kb
Host smart-d5e91ccd-80c2-4112-bbe6-d5781545cd63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993423531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2993423531
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2833292236
Short name T72
Test name
Test status
Simulation time 37881328 ps
CPU time 0.8 seconds
Started Jul 06 05:30:13 PM PDT 24
Finished Jul 06 05:30:14 PM PDT 24
Peak memory 205120 kb
Host smart-d992a380-ae7a-4b57-9b8d-d68580155de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833292236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2833292236
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1865714133
Short name T210
Test name
Test status
Simulation time 6308614019 ps
CPU time 10.26 seconds
Started Jul 06 05:30:30 PM PDT 24
Finished Jul 06 05:30:40 PM PDT 24
Peak memory 213652 kb
Host smart-444a1728-d359-41b2-9d2d-078de68fc212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865714133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1865714133
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1376065612
Short name T271
Test name
Test status
Simulation time 2500921723 ps
CPU time 7.56 seconds
Started Jul 06 05:30:08 PM PDT 24
Finished Jul 06 05:30:17 PM PDT 24
Peak memory 213596 kb
Host smart-7e0bf1d4-cf2d-47f0-b120-65f707aa432b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376065612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1376065612
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3429633092
Short name T201
Test name
Test status
Simulation time 60119710 ps
CPU time 0.82 seconds
Started Jul 06 05:30:11 PM PDT 24
Finished Jul 06 05:30:13 PM PDT 24
Peak memory 205072 kb
Host smart-0980a4b5-bea3-488f-bc7e-11d70c852a27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429633092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3429633092
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.813417323
Short name T208
Test name
Test status
Simulation time 8383068633 ps
CPU time 12.38 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:30:09 PM PDT 24
Peak memory 213652 kb
Host smart-411eb258-74b1-495a-b56d-ae29b6f63f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813417323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.813417323
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3002305535
Short name T141
Test name
Test status
Simulation time 13883592639 ps
CPU time 14.95 seconds
Started Jul 06 05:29:58 PM PDT 24
Finished Jul 06 05:30:14 PM PDT 24
Peak memory 213628 kb
Host smart-0fe33070-29cf-4249-bcb7-090e299e7029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002305535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3002305535
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3546887996
Short name T146
Test name
Test status
Simulation time 1230219344 ps
CPU time 2.4 seconds
Started Jul 06 05:29:58 PM PDT 24
Finished Jul 06 05:30:01 PM PDT 24
Peak memory 205332 kb
Host smart-6c275098-1456-4911-af68-f4f8dae6e64a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546887996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3546887996
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.144395301
Short name T236
Test name
Test status
Simulation time 140680026 ps
CPU time 1.08 seconds
Started Jul 06 05:30:13 PM PDT 24
Finished Jul 06 05:30:14 PM PDT 24
Peak memory 205104 kb
Host smart-17204200-b993-4f6b-8614-530db449edab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144395301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.144395301
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.4053421991
Short name T54
Test name
Test status
Simulation time 2948866260 ps
CPU time 8.96 seconds
Started Jul 06 05:30:00 PM PDT 24
Finished Jul 06 05:30:09 PM PDT 24
Peak memory 229648 kb
Host smart-2a99d1c9-2224-46dd-8b29-836e8978841f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053421991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.4053421991
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.3385464844
Short name T200
Test name
Test status
Simulation time 149379954 ps
CPU time 0.81 seconds
Started Jul 06 05:30:34 PM PDT 24
Finished Jul 06 05:30:35 PM PDT 24
Peak memory 205136 kb
Host smart-f3264a7c-d2c0-453d-864a-5dd461060a22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385464844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3385464844
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2330616141
Short name T12
Test name
Test status
Simulation time 3927826232 ps
CPU time 10.83 seconds
Started Jul 06 05:30:29 PM PDT 24
Finished Jul 06 05:30:40 PM PDT 24
Peak memory 213544 kb
Host smart-26e0f95b-6a67-4918-b056-8a19725a18d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330616141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2330616141
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1264850855
Short name T222
Test name
Test status
Simulation time 33026853 ps
CPU time 0.79 seconds
Started Jul 06 05:30:15 PM PDT 24
Finished Jul 06 05:30:16 PM PDT 24
Peak memory 205092 kb
Host smart-a67d4f8e-745e-415e-8d49-e533940860d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264850855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1264850855
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2298471471
Short name T237
Test name
Test status
Simulation time 42645213 ps
CPU time 0.8 seconds
Started Jul 06 05:30:14 PM PDT 24
Finished Jul 06 05:30:15 PM PDT 24
Peak memory 205120 kb
Host smart-c7c87e8c-21c4-45e4-9c4c-97fca84b7bce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298471471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2298471471
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.347459777
Short name T246
Test name
Test status
Simulation time 72949896 ps
CPU time 0.74 seconds
Started Jul 06 05:30:35 PM PDT 24
Finished Jul 06 05:30:36 PM PDT 24
Peak memory 205064 kb
Host smart-0d9607ba-6d86-443e-9748-9eb3204d568b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347459777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.347459777
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.4082845669
Short name T240
Test name
Test status
Simulation time 89274214 ps
CPU time 0.79 seconds
Started Jul 06 05:30:17 PM PDT 24
Finished Jul 06 05:30:18 PM PDT 24
Peak memory 205128 kb
Host smart-55378a78-2a9e-4404-8532-36c281692b6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082845669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.4082845669
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.635472065
Short name T197
Test name
Test status
Simulation time 7854881608 ps
CPU time 12.1 seconds
Started Jul 06 05:30:34 PM PDT 24
Finished Jul 06 05:30:47 PM PDT 24
Peak memory 221660 kb
Host smart-0a4bcc6a-a2bd-4eee-b836-e69da0f6feea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635472065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.635472065
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1297181114
Short name T218
Test name
Test status
Simulation time 46957185 ps
CPU time 0.8 seconds
Started Jul 06 05:30:27 PM PDT 24
Finished Jul 06 05:30:28 PM PDT 24
Peak memory 205080 kb
Host smart-53d075d5-4c3c-4ddc-92a4-06a2763516b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297181114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1297181114
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2668384864
Short name T172
Test name
Test status
Simulation time 3218196710 ps
CPU time 3.23 seconds
Started Jul 06 05:30:28 PM PDT 24
Finished Jul 06 05:30:37 PM PDT 24
Peak memory 205292 kb
Host smart-22a1bff0-24f2-4bca-82aa-fa57bcad0cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668384864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2668384864
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.3297518910
Short name T211
Test name
Test status
Simulation time 40184996 ps
CPU time 0.77 seconds
Started Jul 06 05:30:26 PM PDT 24
Finished Jul 06 05:30:27 PM PDT 24
Peak memory 205012 kb
Host smart-37b2021a-d651-41c4-b64e-dddd8d7e1c13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297518910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.3297518910
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.711769248
Short name T158
Test name
Test status
Simulation time 8431527269 ps
CPU time 11.48 seconds
Started Jul 06 05:30:22 PM PDT 24
Finished Jul 06 05:30:34 PM PDT 24
Peak memory 213568 kb
Host smart-0b1ecae6-3cb0-45ac-ae57-6a2b6f919f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711769248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.711769248
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.628322478
Short name T46
Test name
Test status
Simulation time 302842686 ps
CPU time 0.74 seconds
Started Jul 06 05:30:18 PM PDT 24
Finished Jul 06 05:30:19 PM PDT 24
Peak memory 205068 kb
Host smart-01ac90bc-dd0f-4abc-8e4f-27d15061a236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628322478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.628322478
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3821229102
Short name T221
Test name
Test status
Simulation time 105110525 ps
CPU time 0.71 seconds
Started Jul 06 05:30:23 PM PDT 24
Finished Jul 06 05:30:24 PM PDT 24
Peak memory 205104 kb
Host smart-6590f1e4-01cf-4cbe-a665-0b383f5fb7ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821229102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3821229102
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.248436455
Short name T269
Test name
Test status
Simulation time 89273308 ps
CPU time 0.88 seconds
Started Jul 06 05:30:14 PM PDT 24
Finished Jul 06 05:30:16 PM PDT 24
Peak memory 205092 kb
Host smart-9fd65a9f-9b82-43b6-b576-79864f905556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248436455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.248436455
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.584411600
Short name T213
Test name
Test status
Simulation time 36961303 ps
CPU time 0.76 seconds
Started Jul 06 05:29:55 PM PDT 24
Finished Jul 06 05:29:56 PM PDT 24
Peak memory 205128 kb
Host smart-669740be-c8bd-4d0f-9652-22b7975df6c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584411600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.584411600
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.272298600
Short name T85
Test name
Test status
Simulation time 12741704535 ps
CPU time 15.88 seconds
Started Jul 06 05:29:57 PM PDT 24
Finished Jul 06 05:30:13 PM PDT 24
Peak memory 213640 kb
Host smart-3b1296cc-69fe-4b1e-aeaf-cb2e6412f3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272298600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.272298600
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.593979157
Short name T282
Test name
Test status
Simulation time 3651527282 ps
CPU time 6.14 seconds
Started Jul 06 05:29:51 PM PDT 24
Finished Jul 06 05:29:58 PM PDT 24
Peak memory 205428 kb
Host smart-bb344d14-6e75-4f99-a08f-1d5f62b465b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593979157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.593979157
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3458397720
Short name T242
Test name
Test status
Simulation time 3363795925 ps
CPU time 3.41 seconds
Started Jul 06 05:30:18 PM PDT 24
Finished Jul 06 05:30:22 PM PDT 24
Peak memory 213488 kb
Host smart-bdc413ce-1112-4430-a38b-60b067a5eb8e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458397720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3458397720
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2056514888
Short name T268
Test name
Test status
Simulation time 821373463 ps
CPU time 0.88 seconds
Started Jul 06 05:29:51 PM PDT 24
Finished Jul 06 05:29:53 PM PDT 24
Peak memory 205060 kb
Host smart-68737ee4-cfc0-427d-a0d4-020395fa0e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056514888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2056514888
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1352822225
Short name T252
Test name
Test status
Simulation time 3277825340 ps
CPU time 5.14 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:30:02 PM PDT 24
Peak memory 213524 kb
Host smart-7c5d9694-1499-49d0-bf29-25bfe33ba6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352822225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1352822225
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.963024343
Short name T65
Test name
Test status
Simulation time 564289888 ps
CPU time 2.51 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 229180 kb
Host smart-f58f8729-cd35-493a-9d17-a29974287e95
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963024343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.963024343
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.1957075536
Short name T241
Test name
Test status
Simulation time 124783374 ps
CPU time 0.99 seconds
Started Jul 06 05:30:27 PM PDT 24
Finished Jul 06 05:30:29 PM PDT 24
Peak memory 205004 kb
Host smart-e82d3cc7-aa91-404c-ac0e-a01f91487b40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957075536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1957075536
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.306052945
Short name T233
Test name
Test status
Simulation time 120642894 ps
CPU time 0.94 seconds
Started Jul 06 05:30:28 PM PDT 24
Finished Jul 06 05:30:29 PM PDT 24
Peak memory 205096 kb
Host smart-ab6d129e-2d06-46e5-8e0f-b0d171c90fc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306052945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.306052945
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1903133335
Short name T249
Test name
Test status
Simulation time 76652222 ps
CPU time 0.8 seconds
Started Jul 06 05:30:37 PM PDT 24
Finished Jul 06 05:30:38 PM PDT 24
Peak memory 205048 kb
Host smart-7d9f2bcd-14ab-4c29-844e-c1130e8177eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903133335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1903133335
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2586724114
Short name T274
Test name
Test status
Simulation time 149165574 ps
CPU time 1.13 seconds
Started Jul 06 05:30:26 PM PDT 24
Finished Jul 06 05:30:28 PM PDT 24
Peak memory 204940 kb
Host smart-7fcdee9a-56c2-496f-8d0c-77eee1209738
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586724114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2586724114
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.4097826280
Short name T45
Test name
Test status
Simulation time 49070158 ps
CPU time 0.81 seconds
Started Jul 06 05:30:17 PM PDT 24
Finished Jul 06 05:30:18 PM PDT 24
Peak memory 205116 kb
Host smart-80e14d80-88ac-4d29-b127-6bd9ee246f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097826280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.4097826280
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.702945657
Short name T230
Test name
Test status
Simulation time 71885206 ps
CPU time 0.83 seconds
Started Jul 06 05:30:14 PM PDT 24
Finished Jul 06 05:30:15 PM PDT 24
Peak memory 205108 kb
Host smart-f5107483-7ae6-41c8-9e92-ea4b45cc1abb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702945657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.702945657
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.1897289932
Short name T165
Test name
Test status
Simulation time 3689094462 ps
CPU time 2.43 seconds
Started Jul 06 05:30:36 PM PDT 24
Finished Jul 06 05:30:39 PM PDT 24
Peak memory 213344 kb
Host smart-7f2353bd-acea-4a0e-bf45-5d967894ca92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897289932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1897289932
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.465683613
Short name T77
Test name
Test status
Simulation time 103561395 ps
CPU time 0.76 seconds
Started Jul 06 05:30:14 PM PDT 24
Finished Jul 06 05:30:15 PM PDT 24
Peak memory 205096 kb
Host smart-eecc5771-7ec3-41a7-97b4-4fa1e45f0bbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465683613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.465683613
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.617475227
Short name T217
Test name
Test status
Simulation time 221895285 ps
CPU time 0.68 seconds
Started Jul 06 05:30:15 PM PDT 24
Finished Jul 06 05:30:16 PM PDT 24
Peak memory 205116 kb
Host smart-98d92158-0d3d-467b-ba0c-54a998cd49af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617475227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.617475227
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2045531646
Short name T57
Test name
Test status
Simulation time 144909018 ps
CPU time 0.92 seconds
Started Jul 06 05:30:31 PM PDT 24
Finished Jul 06 05:30:33 PM PDT 24
Peak memory 205088 kb
Host smart-7df49930-ac3c-46ae-a311-3361d7ca5844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045531646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2045531646
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.3244396851
Short name T162
Test name
Test status
Simulation time 5493164432 ps
CPU time 13.15 seconds
Started Jul 06 05:30:17 PM PDT 24
Finished Jul 06 05:30:31 PM PDT 24
Peak memory 213516 kb
Host smart-e71c4aff-1f86-499c-999b-0ec2e92e9006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244396851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3244396851
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1503630795
Short name T205
Test name
Test status
Simulation time 118133696 ps
CPU time 0.95 seconds
Started Jul 06 05:30:36 PM PDT 24
Finished Jul 06 05:30:37 PM PDT 24
Peak memory 205092 kb
Host smart-e884dc11-7670-4dcd-8297-82f5bbbeccae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503630795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1503630795
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.1161799271
Short name T255
Test name
Test status
Simulation time 100999078 ps
CPU time 0.95 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:29:58 PM PDT 24
Peak memory 205124 kb
Host smart-5b5345dc-acf0-45c6-9f84-48754a17ae7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161799271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.1161799271
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1541948687
Short name T256
Test name
Test status
Simulation time 2957888814 ps
CPU time 2.03 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 213532 kb
Host smart-5de973fc-027a-48c1-9fa1-2e4ed16d91a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541948687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1541948687
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.4263081394
Short name T226
Test name
Test status
Simulation time 5886686961 ps
CPU time 15.02 seconds
Started Jul 06 05:29:59 PM PDT 24
Finished Jul 06 05:30:14 PM PDT 24
Peak memory 213620 kb
Host smart-75930eec-ecdc-493b-8202-fa434c2a660f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263081394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.4263081394
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3844431494
Short name T272
Test name
Test status
Simulation time 4431191488 ps
CPU time 10.47 seconds
Started Jul 06 05:30:00 PM PDT 24
Finished Jul 06 05:30:11 PM PDT 24
Peak memory 205408 kb
Host smart-7cc4632b-15a8-4ed9-907b-fabc034f85a8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3844431494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3844431494
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.231705317
Short name T270
Test name
Test status
Simulation time 220118213 ps
CPU time 1.2 seconds
Started Jul 06 05:30:11 PM PDT 24
Finished Jul 06 05:30:13 PM PDT 24
Peak memory 205112 kb
Host smart-0a44bc86-b968-4494-ba0e-5c76424584e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231705317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.231705317
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.573121541
Short name T204
Test name
Test status
Simulation time 2824685250 ps
CPU time 9.53 seconds
Started Jul 06 05:29:54 PM PDT 24
Finished Jul 06 05:30:03 PM PDT 24
Peak memory 205648 kb
Host smart-f8c97542-8e6f-4da1-aa7d-976dcab42e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573121541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.573121541
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2694213520
Short name T66
Test name
Test status
Simulation time 642501112 ps
CPU time 2.68 seconds
Started Jul 06 05:30:05 PM PDT 24
Finished Jul 06 05:30:09 PM PDT 24
Peak memory 229604 kb
Host smart-674c9462-055b-46df-b7d2-754935bfb1c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694213520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2694213520
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.3912358583
Short name T161
Test name
Test status
Simulation time 1852674121 ps
CPU time 2.99 seconds
Started Jul 06 05:30:06 PM PDT 24
Finished Jul 06 05:30:10 PM PDT 24
Peak memory 205312 kb
Host smart-17c8d083-74b8-4887-b8de-c375dd94bd7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912358583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3912358583
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3386862962
Short name T234
Test name
Test status
Simulation time 80171267 ps
CPU time 0.88 seconds
Started Jul 06 05:30:32 PM PDT 24
Finished Jul 06 05:30:33 PM PDT 24
Peak memory 205104 kb
Host smart-4c597b61-c7d9-454d-b45a-c7e4e4abf642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386862962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3386862962
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.639146772
Short name T224
Test name
Test status
Simulation time 31491310 ps
CPU time 0.72 seconds
Started Jul 06 05:30:43 PM PDT 24
Finished Jul 06 05:30:45 PM PDT 24
Peak memory 204960 kb
Host smart-09afb993-5c90-49a6-85ee-ddaaf75823b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639146772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.639146772
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.4208076006
Short name T266
Test name
Test status
Simulation time 83096687 ps
CPU time 0.73 seconds
Started Jul 06 05:30:19 PM PDT 24
Finished Jul 06 05:30:20 PM PDT 24
Peak memory 205072 kb
Host smart-e0ff1e28-2cca-448a-95a9-6ba3811dc388
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208076006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.4208076006
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.2594322223
Short name T166
Test name
Test status
Simulation time 6145946698 ps
CPU time 13.38 seconds
Started Jul 06 05:30:32 PM PDT 24
Finished Jul 06 05:30:46 PM PDT 24
Peak memory 213520 kb
Host smart-71b33c18-60cb-425a-b8ae-7219e6f115f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594322223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2594322223
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1843933314
Short name T253
Test name
Test status
Simulation time 46784665 ps
CPU time 0.76 seconds
Started Jul 06 05:30:44 PM PDT 24
Finished Jul 06 05:30:46 PM PDT 24
Peak memory 204960 kb
Host smart-2ac9e623-988d-4862-a3f9-4c899f31b1a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843933314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1843933314
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2331293908
Short name T248
Test name
Test status
Simulation time 159263659 ps
CPU time 0.74 seconds
Started Jul 06 05:30:39 PM PDT 24
Finished Jul 06 05:30:40 PM PDT 24
Peak memory 205100 kb
Host smart-cd2b9bcb-e8af-48c2-98a9-b2357de22c88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331293908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2331293908
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1713822287
Short name T220
Test name
Test status
Simulation time 64852199 ps
CPU time 0.72 seconds
Started Jul 06 05:30:18 PM PDT 24
Finished Jul 06 05:30:19 PM PDT 24
Peak memory 205044 kb
Host smart-b480d4d6-c241-4f42-a3b4-b51f71b6919f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713822287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1713822287
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.3861418026
Short name T173
Test name
Test status
Simulation time 16157685266 ps
CPU time 19.63 seconds
Started Jul 06 05:30:19 PM PDT 24
Finished Jul 06 05:30:39 PM PDT 24
Peak memory 213440 kb
Host smart-e6a09c39-9c23-44f6-ae62-06ca412b3fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861418026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3861418026
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.946181037
Short name T209
Test name
Test status
Simulation time 49724300 ps
CPU time 0.74 seconds
Started Jul 06 05:30:22 PM PDT 24
Finished Jul 06 05:30:23 PM PDT 24
Peak memory 205072 kb
Host smart-9faf5f58-9d10-4ae1-8c36-758179a18825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946181037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.946181037
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.1815817279
Short name T163
Test name
Test status
Simulation time 11097921127 ps
CPU time 11.35 seconds
Started Jul 06 05:30:19 PM PDT 24
Finished Jul 06 05:30:31 PM PDT 24
Peak memory 213512 kb
Host smart-ce9f3e96-3ac4-48f8-92ed-8e8ff2ced80b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815817279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.1815817279
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2543401472
Short name T132
Test name
Test status
Simulation time 57835368 ps
CPU time 0.74 seconds
Started Jul 06 05:30:21 PM PDT 24
Finished Jul 06 05:30:22 PM PDT 24
Peak memory 205092 kb
Host smart-fe94561e-2439-442f-8321-b8608068761a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543401472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2543401472
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.217312281
Short name T75
Test name
Test status
Simulation time 117904062 ps
CPU time 0.87 seconds
Started Jul 06 05:30:21 PM PDT 24
Finished Jul 06 05:30:23 PM PDT 24
Peak memory 205092 kb
Host smart-325a1574-48ad-458a-bd1a-f50687680082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217312281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.217312281
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.219380825
Short name T167
Test name
Test status
Simulation time 10653620782 ps
CPU time 12.56 seconds
Started Jul 06 05:30:17 PM PDT 24
Finished Jul 06 05:30:30 PM PDT 24
Peak memory 213520 kb
Host smart-7d7ade1b-6db4-446f-b586-714ca08d295e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219380825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.219380825
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.4092782887
Short name T238
Test name
Test status
Simulation time 39404432 ps
CPU time 0.75 seconds
Started Jul 06 05:30:20 PM PDT 24
Finished Jul 06 05:30:21 PM PDT 24
Peak memory 205116 kb
Host smart-08cb5ecf-e19b-48bd-ab9a-f230f3dba641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092782887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.4092782887
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3068859306
Short name T239
Test name
Test status
Simulation time 87812375 ps
CPU time 0.72 seconds
Started Jul 06 05:30:15 PM PDT 24
Finished Jul 06 05:30:16 PM PDT 24
Peak memory 205092 kb
Host smart-d7d3516a-4cd8-4e5f-892f-cedf61aeabeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068859306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3068859306
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3586192104
Short name T244
Test name
Test status
Simulation time 2506158199 ps
CPU time 3.09 seconds
Started Jul 06 05:30:12 PM PDT 24
Finished Jul 06 05:30:16 PM PDT 24
Peak memory 213640 kb
Host smart-1d0eec08-8ca9-4c6f-b49c-219b2bd3a39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586192104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3586192104
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2722333720
Short name T68
Test name
Test status
Simulation time 7552164161 ps
CPU time 20.79 seconds
Started Jul 06 05:30:08 PM PDT 24
Finished Jul 06 05:30:29 PM PDT 24
Peak memory 213616 kb
Host smart-6288a458-02f7-41d4-8603-54b810443314
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722333720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2722333720
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2085064502
Short name T260
Test name
Test status
Simulation time 1307437789 ps
CPU time 1.48 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:29:59 PM PDT 24
Peak memory 205300 kb
Host smart-2467c742-7df6-4498-a28a-8516d1734f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085064502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2085064502
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.3632760204
Short name T195
Test name
Test status
Simulation time 3411408368 ps
CPU time 4.18 seconds
Started Jul 06 05:30:08 PM PDT 24
Finished Jul 06 05:30:13 PM PDT 24
Peak memory 205296 kb
Host smart-115ee76f-a994-4237-b6d2-584f6168de11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632760204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3632760204
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2103371974
Short name T133
Test name
Test status
Simulation time 31173683 ps
CPU time 0.75 seconds
Started Jul 06 05:29:58 PM PDT 24
Finished Jul 06 05:30:00 PM PDT 24
Peak memory 205096 kb
Host smart-f45e8640-546e-439f-af77-891eb430cbb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103371974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2103371974
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2711065597
Short name T275
Test name
Test status
Simulation time 2737372322 ps
CPU time 9.05 seconds
Started Jul 06 05:30:26 PM PDT 24
Finished Jul 06 05:30:35 PM PDT 24
Peak memory 213612 kb
Host smart-30dbfde1-70e8-4184-8fd6-e97fcdb87231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711065597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2711065597
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.4277560065
Short name T278
Test name
Test status
Simulation time 4416776847 ps
CPU time 4.38 seconds
Started Jul 06 05:30:12 PM PDT 24
Finished Jul 06 05:30:16 PM PDT 24
Peak memory 205392 kb
Host smart-b31cb763-3493-47cf-978e-2eb6a4ec911a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277560065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.4277560065
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2381205757
Short name T79
Test name
Test status
Simulation time 7001417590 ps
CPU time 19.6 seconds
Started Jul 06 05:30:15 PM PDT 24
Finished Jul 06 05:30:35 PM PDT 24
Peak memory 213628 kb
Host smart-766eb642-3af9-47c6-acfb-929e1484acdb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2381205757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2381205757
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.4033277889
Short name T261
Test name
Test status
Simulation time 2699385770 ps
CPU time 8.82 seconds
Started Jul 06 05:30:35 PM PDT 24
Finished Jul 06 05:30:44 PM PDT 24
Peak memory 213560 kb
Host smart-d866ec54-fa5f-48ec-b8e7-2d3eb24fdef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033277889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.4033277889
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.3734318033
Short name T14
Test name
Test status
Simulation time 8851806007 ps
CPU time 6.06 seconds
Started Jul 06 05:30:27 PM PDT 24
Finished Jul 06 05:30:33 PM PDT 24
Peak memory 213492 kb
Host smart-f63c86d0-1145-4a21-b4ad-954d96ebf444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734318033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3734318033
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3695269561
Short name T219
Test name
Test status
Simulation time 72292651 ps
CPU time 0.84 seconds
Started Jul 06 05:30:02 PM PDT 24
Finished Jul 06 05:30:04 PM PDT 24
Peak memory 205116 kb
Host smart-34656de5-405f-4e14-842a-e6128f2ac0be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695269561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3695269561
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.2166382631
Short name T2
Test name
Test status
Simulation time 19924678621 ps
CPU time 27.06 seconds
Started Jul 06 05:30:16 PM PDT 24
Finished Jul 06 05:30:44 PM PDT 24
Peak memory 213592 kb
Host smart-23aebc71-69dd-4630-95a8-62d99be2f776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166382631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.2166382631
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1584675275
Short name T139
Test name
Test status
Simulation time 2850589550 ps
CPU time 6.45 seconds
Started Jul 06 05:30:13 PM PDT 24
Finished Jul 06 05:30:20 PM PDT 24
Peak memory 213564 kb
Host smart-59c6c8e9-6d53-44d2-8733-f93ac27f2d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584675275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1584675275
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3773072064
Short name T153
Test name
Test status
Simulation time 838784897 ps
CPU time 1.42 seconds
Started Jul 06 05:30:00 PM PDT 24
Finished Jul 06 05:30:01 PM PDT 24
Peak memory 205332 kb
Host smart-cbaca302-3462-446f-9632-0da961683ec2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3773072064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3773072064
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1571664679
Short name T202
Test name
Test status
Simulation time 7110171743 ps
CPU time 14.65 seconds
Started Jul 06 05:29:57 PM PDT 24
Finished Jul 06 05:30:12 PM PDT 24
Peak memory 205460 kb
Host smart-5628f0f2-d0a7-4246-a3f3-6b1ac23c8a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571664679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1571664679
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2285160786
Short name T223
Test name
Test status
Simulation time 102641985 ps
CPU time 0.76 seconds
Started Jul 06 05:29:56 PM PDT 24
Finished Jul 06 05:29:57 PM PDT 24
Peak memory 205036 kb
Host smart-fc749d4c-5fec-4772-8800-3e2c11a2b9e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285160786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2285160786
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.528322541
Short name T212
Test name
Test status
Simulation time 2605974599 ps
CPU time 5.13 seconds
Started Jul 06 05:30:11 PM PDT 24
Finished Jul 06 05:30:17 PM PDT 24
Peak memory 213616 kb
Host smart-1db3956b-0945-48d9-b639-82ba82fe0b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528322541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.528322541
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.909096890
Short name T243
Test name
Test status
Simulation time 3380755922 ps
CPU time 6.82 seconds
Started Jul 06 05:30:05 PM PDT 24
Finished Jul 06 05:30:13 PM PDT 24
Peak memory 213660 kb
Host smart-a9babe1e-5993-4ff7-9b30-644bed11582e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=909096890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.909096890
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.227302535
Short name T286
Test name
Test status
Simulation time 2208761318 ps
CPU time 2.45 seconds
Started Jul 06 05:29:55 PM PDT 24
Finished Jul 06 05:29:58 PM PDT 24
Peak memory 213648 kb
Host smart-9f193b54-87e6-400f-9874-919a542d3d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227302535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.227302535
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.1665005306
Short name T171
Test name
Test status
Simulation time 2891145694 ps
CPU time 2.87 seconds
Started Jul 06 05:30:05 PM PDT 24
Finished Jul 06 05:30:08 PM PDT 24
Peak memory 205268 kb
Host smart-30f1294e-8946-4dc5-b7dd-791c0757dbcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665005306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.1665005306
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3772309193
Short name T264
Test name
Test status
Simulation time 77968480 ps
CPU time 0.73 seconds
Started Jul 06 05:30:02 PM PDT 24
Finished Jul 06 05:30:03 PM PDT 24
Peak memory 205120 kb
Host smart-3e621d26-4fa1-4341-aa97-30a54d3b30de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772309193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3772309193
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.380984009
Short name T232
Test name
Test status
Simulation time 5946850605 ps
CPU time 7.49 seconds
Started Jul 06 05:30:08 PM PDT 24
Finished Jul 06 05:30:16 PM PDT 24
Peak memory 213592 kb
Host smart-77578c96-84a7-47dc-bd24-d1057cecaf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380984009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.380984009
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.343041366
Short name T235
Test name
Test status
Simulation time 4319230768 ps
CPU time 10.18 seconds
Started Jul 06 05:30:17 PM PDT 24
Finished Jul 06 05:30:28 PM PDT 24
Peak memory 213588 kb
Host smart-88f82866-8c99-4852-b2b5-4d6b8b8f201d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343041366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.343041366
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.785487926
Short name T37
Test name
Test status
Simulation time 13326926681 ps
CPU time 10.32 seconds
Started Jul 06 05:30:16 PM PDT 24
Finished Jul 06 05:30:27 PM PDT 24
Peak memory 213672 kb
Host smart-e21dea20-2d30-4d52-ae48-91f0712f5d8d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=785487926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.785487926
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3539281990
Short name T245
Test name
Test status
Simulation time 2258801745 ps
CPU time 6.97 seconds
Started Jul 06 05:30:20 PM PDT 24
Finished Jul 06 05:30:27 PM PDT 24
Peak memory 205616 kb
Host smart-7e60caa7-eb4d-4cc5-9f2c-0e5a34432ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539281990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3539281990
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.3870210987
Short name T196
Test name
Test status
Simulation time 5298994953 ps
CPU time 15.24 seconds
Started Jul 06 05:30:06 PM PDT 24
Finished Jul 06 05:30:22 PM PDT 24
Peak memory 214232 kb
Host smart-593f8cd4-ef56-4383-b4a5-15a1419ac4cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870210987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3870210987
Directory /workspace/9.rv_dm_stress_all/latest
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