Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.52 95.12 79.31 89.42 74.36 85.33 98.42 55.65


Total test records in report: 426
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T131 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1493368234 Jul 07 06:11:15 PM PDT 24 Jul 07 06:11:21 PM PDT 24 3299029952 ps
T289 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1576132395 Jul 07 06:10:36 PM PDT 24 Jul 07 06:11:01 PM PDT 24 17053684581 ps
T290 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1518911918 Jul 07 06:11:27 PM PDT 24 Jul 07 06:11:32 PM PDT 24 698180126 ps
T133 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2167956907 Jul 07 06:10:56 PM PDT 24 Jul 07 06:11:05 PM PDT 24 718754839 ps
T291 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4268092818 Jul 07 06:10:49 PM PDT 24 Jul 07 06:10:51 PM PDT 24 271747217 ps
T292 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3241463829 Jul 07 06:10:28 PM PDT 24 Jul 07 06:10:44 PM PDT 24 27223742798 ps
T126 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2464693742 Jul 07 06:10:49 PM PDT 24 Jul 07 06:10:51 PM PDT 24 81464288 ps
T293 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2288053362 Jul 07 06:10:01 PM PDT 24 Jul 07 06:10:03 PM PDT 24 5541483930 ps
T294 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2831745590 Jul 07 06:11:35 PM PDT 24 Jul 07 06:11:47 PM PDT 24 3900693847 ps
T110 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1890837132 Jul 07 06:11:08 PM PDT 24 Jul 07 06:11:10 PM PDT 24 731186627 ps
T116 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1292114432 Jul 07 06:11:29 PM PDT 24 Jul 07 06:11:31 PM PDT 24 221379487 ps
T295 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.965007082 Jul 07 06:10:25 PM PDT 24 Jul 07 06:10:34 PM PDT 24 3356981065 ps
T296 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3911444143 Jul 07 06:11:26 PM PDT 24 Jul 07 06:11:37 PM PDT 24 4180028714 ps
T111 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1057803230 Jul 07 06:10:33 PM PDT 24 Jul 07 06:11:49 PM PDT 24 5685670152 ps
T297 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2790963145 Jul 07 06:11:16 PM PDT 24 Jul 07 06:11:49 PM PDT 24 11347202065 ps
T298 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.155622867 Jul 07 06:10:53 PM PDT 24 Jul 07 06:11:04 PM PDT 24 12117668188 ps
T299 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.616357761 Jul 07 06:11:25 PM PDT 24 Jul 07 06:11:35 PM PDT 24 23140988801 ps
T44 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3275882261 Jul 07 06:10:06 PM PDT 24 Jul 07 06:10:58 PM PDT 24 30955897308 ps
T112 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1983862848 Jul 07 06:11:16 PM PDT 24 Jul 07 06:11:18 PM PDT 24 114490786 ps
T300 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.711249100 Jul 07 06:11:24 PM PDT 24 Jul 07 06:11:26 PM PDT 24 231109048 ps
T132 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3702871447 Jul 07 06:10:47 PM PDT 24 Jul 07 06:10:57 PM PDT 24 1648977129 ps
T301 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1800130678 Jul 07 06:10:51 PM PDT 24 Jul 07 06:10:53 PM PDT 24 972402920 ps
T117 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.850427305 Jul 07 06:11:22 PM PDT 24 Jul 07 06:11:24 PM PDT 24 292593530 ps
T118 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2312622977 Jul 07 06:10:22 PM PDT 24 Jul 07 06:11:36 PM PDT 24 9525673749 ps
T113 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1028498000 Jul 07 06:10:22 PM PDT 24 Jul 07 06:10:27 PM PDT 24 465514557 ps
T179 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1506832601 Jul 07 06:11:31 PM PDT 24 Jul 07 06:11:46 PM PDT 24 2923325319 ps
T121 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.680970922 Jul 07 06:10:54 PM PDT 24 Jul 07 06:11:03 PM PDT 24 1286859644 ps
T302 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2770231905 Jul 07 06:10:33 PM PDT 24 Jul 07 06:10:39 PM PDT 24 1722029471 ps
T180 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3556894360 Jul 07 06:11:11 PM PDT 24 Jul 07 06:11:22 PM PDT 24 3419321606 ps
T45 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.587422568 Jul 07 06:11:01 PM PDT 24 Jul 07 06:11:37 PM PDT 24 12826241079 ps
T303 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2557609270 Jul 07 06:10:19 PM PDT 24 Jul 07 06:10:51 PM PDT 24 3449711176 ps
T185 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2549596154 Jul 07 06:11:10 PM PDT 24 Jul 07 06:11:21 PM PDT 24 2609093568 ps
T122 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2639376081 Jul 07 06:10:14 PM PDT 24 Jul 07 06:10:19 PM PDT 24 1335643772 ps
T114 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3173819695 Jul 07 06:11:09 PM PDT 24 Jul 07 06:11:14 PM PDT 24 312823792 ps
T304 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.301555314 Jul 07 06:11:26 PM PDT 24 Jul 07 06:11:28 PM PDT 24 84070923 ps
T123 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2111419033 Jul 07 06:11:36 PM PDT 24 Jul 07 06:11:41 PM PDT 24 201680772 ps
T305 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1064685207 Jul 07 06:11:00 PM PDT 24 Jul 07 06:11:04 PM PDT 24 1130608845 ps
T306 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3154617424 Jul 07 06:11:10 PM PDT 24 Jul 07 06:11:12 PM PDT 24 268551617 ps
T307 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.898251190 Jul 07 06:10:41 PM PDT 24 Jul 07 06:10:42 PM PDT 24 82412838 ps
T308 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2122963186 Jul 07 06:10:40 PM PDT 24 Jul 07 06:10:53 PM PDT 24 13964669813 ps
T309 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.612010766 Jul 07 06:11:00 PM PDT 24 Jul 07 06:11:05 PM PDT 24 1588645714 ps
T119 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2599561741 Jul 07 06:11:10 PM PDT 24 Jul 07 06:11:11 PM PDT 24 523225505 ps
T310 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3627970325 Jul 07 06:11:32 PM PDT 24 Jul 07 06:12:16 PM PDT 24 24892837943 ps
T311 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1894945563 Jul 07 06:10:40 PM PDT 24 Jul 07 06:10:42 PM PDT 24 493029366 ps
T312 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.483263427 Jul 07 06:11:07 PM PDT 24 Jul 07 06:11:13 PM PDT 24 952168304 ps
T313 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3953467913 Jul 07 06:10:28 PM PDT 24 Jul 07 06:10:30 PM PDT 24 79242284 ps
T314 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1694279116 Jul 07 06:10:41 PM PDT 24 Jul 07 06:11:46 PM PDT 24 5051283612 ps
T315 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3600751583 Jul 07 06:10:57 PM PDT 24 Jul 07 06:11:00 PM PDT 24 185513565 ps
T316 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2538653666 Jul 07 06:10:19 PM PDT 24 Jul 07 06:10:20 PM PDT 24 32842799 ps
T317 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.405543063 Jul 07 06:11:33 PM PDT 24 Jul 07 06:12:02 PM PDT 24 11259088991 ps
T175 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3678052937 Jul 07 06:10:31 PM PDT 24 Jul 07 06:10:49 PM PDT 24 1012421677 ps
T318 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1295181278 Jul 07 06:10:37 PM PDT 24 Jul 07 06:10:39 PM PDT 24 1359465773 ps
T319 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3289806828 Jul 07 06:10:35 PM PDT 24 Jul 07 06:10:40 PM PDT 24 2594309745 ps
T320 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3180052489 Jul 07 06:11:01 PM PDT 24 Jul 07 06:11:02 PM PDT 24 256230549 ps
T321 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3869492405 Jul 07 06:10:23 PM PDT 24 Jul 07 06:10:24 PM PDT 24 820781385 ps
T322 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1916125007 Jul 07 06:10:02 PM PDT 24 Jul 07 06:10:04 PM PDT 24 595118517 ps
T323 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.173828350 Jul 07 06:10:18 PM PDT 24 Jul 07 06:10:19 PM PDT 24 48426761 ps
T174 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4092946726 Jul 07 06:10:53 PM PDT 24 Jul 07 06:11:44 PM PDT 24 64272172964 ps
T324 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1802760948 Jul 07 06:11:33 PM PDT 24 Jul 07 06:11:36 PM PDT 24 178764445 ps
T120 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.237744583 Jul 07 06:10:30 PM PDT 24 Jul 07 06:11:25 PM PDT 24 5872762292 ps
T325 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1928856537 Jul 07 06:10:05 PM PDT 24 Jul 07 06:10:46 PM PDT 24 44094002751 ps
T183 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3766234391 Jul 07 06:10:50 PM PDT 24 Jul 07 06:10:59 PM PDT 24 775045859 ps
T326 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2116318291 Jul 07 06:10:55 PM PDT 24 Jul 07 06:11:19 PM PDT 24 9181226519 ps
T327 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.990053989 Jul 07 06:10:20 PM PDT 24 Jul 07 06:10:23 PM PDT 24 58696111 ps
T328 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2770510431 Jul 07 06:11:30 PM PDT 24 Jul 07 06:11:31 PM PDT 24 490030560 ps
T329 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3873094210 Jul 07 06:11:18 PM PDT 24 Jul 07 06:11:24 PM PDT 24 4923375152 ps
T330 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.908213249 Jul 07 06:10:33 PM PDT 24 Jul 07 06:10:55 PM PDT 24 12421841656 ps
T331 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1463229286 Jul 07 06:10:24 PM PDT 24 Jul 07 06:10:25 PM PDT 24 403975365 ps
T124 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3783358177 Jul 07 06:10:36 PM PDT 24 Jul 07 06:10:43 PM PDT 24 2717305410 ps
T332 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1674342709 Jul 07 06:10:05 PM PDT 24 Jul 07 06:10:11 PM PDT 24 9880623466 ps
T333 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.96217450 Jul 07 06:10:37 PM PDT 24 Jul 07 06:10:40 PM PDT 24 654231887 ps
T334 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1670169394 Jul 07 06:11:10 PM PDT 24 Jul 07 06:11:15 PM PDT 24 3149732259 ps
T335 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3279660956 Jul 07 06:10:49 PM PDT 24 Jul 07 06:10:55 PM PDT 24 1098250450 ps
T336 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3510216369 Jul 07 06:10:20 PM PDT 24 Jul 07 06:10:23 PM PDT 24 1245108569 ps
T337 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.140189367 Jul 07 06:11:08 PM PDT 24 Jul 07 06:11:14 PM PDT 24 1696754842 ps
T178 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2830473920 Jul 07 06:10:37 PM PDT 24 Jul 07 06:10:49 PM PDT 24 1898697596 ps
T176 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3662025290 Jul 07 06:11:08 PM PDT 24 Jul 07 06:11:19 PM PDT 24 1089546748 ps
T338 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2498139211 Jul 07 06:11:25 PM PDT 24 Jul 07 06:11:29 PM PDT 24 599872614 ps
T339 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1389594106 Jul 07 06:11:26 PM PDT 24 Jul 07 06:11:27 PM PDT 24 125810204 ps
T340 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4278290582 Jul 07 06:10:36 PM PDT 24 Jul 07 06:10:37 PM PDT 24 74021528 ps
T341 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2613168834 Jul 07 06:10:14 PM PDT 24 Jul 07 06:10:16 PM PDT 24 874442566 ps
T342 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1638557908 Jul 07 06:10:45 PM PDT 24 Jul 07 06:10:46 PM PDT 24 202022574 ps
T343 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.259512020 Jul 07 06:10:40 PM PDT 24 Jul 07 06:10:50 PM PDT 24 6071775967 ps
T181 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.569469802 Jul 07 06:11:31 PM PDT 24 Jul 07 06:11:48 PM PDT 24 2162202916 ps
T344 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.451306593 Jul 07 06:10:47 PM PDT 24 Jul 07 06:10:50 PM PDT 24 722492356 ps
T345 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1351225780 Jul 07 06:10:15 PM PDT 24 Jul 07 06:10:17 PM PDT 24 142536613 ps
T346 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1241366459 Jul 07 06:11:30 PM PDT 24 Jul 07 06:11:38 PM PDT 24 562663769 ps
T347 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.616931626 Jul 07 06:10:42 PM PDT 24 Jul 07 06:11:18 PM PDT 24 21010655968 ps
T348 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2067744466 Jul 07 06:10:50 PM PDT 24 Jul 07 06:11:56 PM PDT 24 20505751755 ps
T349 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1836514979 Jul 07 06:11:04 PM PDT 24 Jul 07 06:11:07 PM PDT 24 104852790 ps
T125 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1986472073 Jul 07 06:11:22 PM PDT 24 Jul 07 06:11:29 PM PDT 24 304254432 ps
T350 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1915250492 Jul 07 06:10:53 PM PDT 24 Jul 07 06:10:58 PM PDT 24 429421448 ps
T351 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4208738664 Jul 07 06:11:08 PM PDT 24 Jul 07 06:11:09 PM PDT 24 361124291 ps
T352 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2732407206 Jul 07 06:11:21 PM PDT 24 Jul 07 06:11:28 PM PDT 24 2260737934 ps
T353 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.924709167 Jul 07 06:11:21 PM PDT 24 Jul 07 06:11:26 PM PDT 24 1791251961 ps
T186 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1533637174 Jul 07 06:11:05 PM PDT 24 Jul 07 06:11:14 PM PDT 24 495144666 ps
T115 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.112515525 Jul 07 06:10:29 PM PDT 24 Jul 07 06:10:36 PM PDT 24 321958966 ps
T354 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.943452440 Jul 07 06:10:01 PM PDT 24 Jul 07 06:10:02 PM PDT 24 113164556 ps
T355 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.480921181 Jul 07 06:10:53 PM PDT 24 Jul 07 06:10:58 PM PDT 24 3577520894 ps
T356 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3691754848 Jul 07 06:10:29 PM PDT 24 Jul 07 06:10:35 PM PDT 24 2919436173 ps
T357 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3866861379 Jul 07 06:11:26 PM PDT 24 Jul 07 06:11:29 PM PDT 24 208875444 ps
T182 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2356009974 Jul 07 06:11:25 PM PDT 24 Jul 07 06:11:46 PM PDT 24 1816985229 ps
T358 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.28467661 Jul 07 06:11:32 PM PDT 24 Jul 07 06:11:41 PM PDT 24 1631213485 ps
T359 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1721921419 Jul 07 06:11:28 PM PDT 24 Jul 07 06:11:34 PM PDT 24 211093329 ps
T105 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4180952036 Jul 07 06:10:22 PM PDT 24 Jul 07 06:11:14 PM PDT 24 18656256221 ps
T360 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2404756779 Jul 07 06:10:57 PM PDT 24 Jul 07 06:11:17 PM PDT 24 19151413747 ps
T361 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2338377452 Jul 07 06:11:30 PM PDT 24 Jul 07 06:11:36 PM PDT 24 2621025155 ps
T362 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.529266511 Jul 07 06:10:36 PM PDT 24 Jul 07 06:10:41 PM PDT 24 3643485139 ps
T363 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1457483862 Jul 07 06:11:29 PM PDT 24 Jul 07 06:11:31 PM PDT 24 152281234 ps
T364 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.704714099 Jul 07 06:10:03 PM PDT 24 Jul 07 06:10:04 PM PDT 24 405499041 ps
T365 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4088016803 Jul 07 06:11:09 PM PDT 24 Jul 07 06:11:18 PM PDT 24 11615837724 ps
T366 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1039944347 Jul 07 06:10:56 PM PDT 24 Jul 07 06:10:59 PM PDT 24 1120437246 ps
T367 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1859102852 Jul 07 06:11:13 PM PDT 24 Jul 07 06:11:16 PM PDT 24 1197362176 ps
T368 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3645201852 Jul 07 06:10:17 PM PDT 24 Jul 07 06:10:19 PM PDT 24 485832029 ps
T369 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2818091609 Jul 07 06:11:28 PM PDT 24 Jul 07 06:12:08 PM PDT 24 58204019583 ps
T370 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.279169562 Jul 07 06:11:05 PM PDT 24 Jul 07 06:11:07 PM PDT 24 1045124526 ps
T371 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2218814172 Jul 07 06:10:02 PM PDT 24 Jul 07 06:10:48 PM PDT 24 43719840342 ps
T372 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3367382850 Jul 07 06:11:13 PM PDT 24 Jul 07 06:11:15 PM PDT 24 417625228 ps
T373 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.344539491 Jul 07 06:11:30 PM PDT 24 Jul 07 06:11:32 PM PDT 24 224590040 ps
T374 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3248046385 Jul 07 06:10:55 PM PDT 24 Jul 07 06:11:10 PM PDT 24 25514909559 ps
T375 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1567041529 Jul 07 06:11:19 PM PDT 24 Jul 07 06:11:24 PM PDT 24 200168195 ps
T376 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.243220206 Jul 07 06:10:58 PM PDT 24 Jul 07 06:11:01 PM PDT 24 163565636 ps
T377 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1662132356 Jul 07 06:10:08 PM PDT 24 Jul 07 06:10:19 PM PDT 24 1337227253 ps
T378 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2992885889 Jul 07 06:10:19 PM PDT 24 Jul 07 06:10:21 PM PDT 24 334502346 ps
T184 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2125566451 Jul 07 06:11:15 PM PDT 24 Jul 07 06:11:26 PM PDT 24 8636040825 ps
T379 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2053599735 Jul 07 06:10:48 PM PDT 24 Jul 07 06:10:49 PM PDT 24 67736419 ps
T380 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3034506613 Jul 07 06:11:20 PM PDT 24 Jul 07 06:12:16 PM PDT 24 40143534463 ps
T381 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2219431165 Jul 07 06:10:16 PM PDT 24 Jul 07 06:10:23 PM PDT 24 4217909907 ps
T382 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2491330463 Jul 07 06:11:11 PM PDT 24 Jul 07 06:11:12 PM PDT 24 275686318 ps
T383 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.79237201 Jul 07 06:11:08 PM PDT 24 Jul 07 06:11:16 PM PDT 24 441217020 ps
T384 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4048442628 Jul 07 06:10:37 PM PDT 24 Jul 07 06:10:40 PM PDT 24 127792845 ps
T385 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.983734692 Jul 07 06:11:11 PM PDT 24 Jul 07 06:11:16 PM PDT 24 432443990 ps
T386 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2108823703 Jul 07 06:11:31 PM PDT 24 Jul 07 06:11:35 PM PDT 24 393752421 ps
T387 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2960126859 Jul 07 06:10:55 PM PDT 24 Jul 07 06:10:59 PM PDT 24 1905401141 ps
T388 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1440682768 Jul 07 06:11:32 PM PDT 24 Jul 07 06:11:33 PM PDT 24 227759522 ps
T389 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3068618733 Jul 07 06:10:52 PM PDT 24 Jul 07 06:12:16 PM PDT 24 65128366381 ps
T390 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2530998439 Jul 07 06:10:24 PM PDT 24 Jul 07 06:10:25 PM PDT 24 83171328 ps
T391 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.83796765 Jul 07 06:11:28 PM PDT 24 Jul 07 06:11:35 PM PDT 24 2736184750 ps
T392 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.709485289 Jul 07 06:10:30 PM PDT 24 Jul 07 06:10:32 PM PDT 24 174619915 ps
T393 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.684628051 Jul 07 06:11:15 PM PDT 24 Jul 07 06:11:32 PM PDT 24 11404424042 ps
T394 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2714630703 Jul 07 06:10:15 PM PDT 24 Jul 07 06:10:37 PM PDT 24 17806810999 ps
T395 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.4235227692 Jul 07 06:11:19 PM PDT 24 Jul 07 06:11:26 PM PDT 24 361725435 ps
T396 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1446624500 Jul 07 06:11:20 PM PDT 24 Jul 07 06:11:21 PM PDT 24 911279114 ps
T397 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1228533055 Jul 07 06:10:39 PM PDT 24 Jul 07 06:10:41 PM PDT 24 1834841525 ps
T398 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.4212205623 Jul 07 06:11:08 PM PDT 24 Jul 07 06:12:19 PM PDT 24 25266115713 ps
T399 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3069448226 Jul 07 06:11:03 PM PDT 24 Jul 07 06:11:05 PM PDT 24 453075077 ps
T400 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4270458933 Jul 07 06:10:36 PM PDT 24 Jul 07 06:10:43 PM PDT 24 2162299650 ps
T401 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1641611644 Jul 07 06:11:29 PM PDT 24 Jul 07 06:11:33 PM PDT 24 244206261 ps
T402 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3892594130 Jul 07 06:11:05 PM PDT 24 Jul 07 06:11:10 PM PDT 24 2290517079 ps
T177 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.163016278 Jul 07 06:11:00 PM PDT 24 Jul 07 06:11:35 PM PDT 24 6637260961 ps
T403 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2693630213 Jul 07 06:10:57 PM PDT 24 Jul 07 06:11:04 PM PDT 24 2803098218 ps
T404 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1521187755 Jul 07 06:11:34 PM PDT 24 Jul 07 06:11:39 PM PDT 24 605322255 ps
T405 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3513195479 Jul 07 06:11:26 PM PDT 24 Jul 07 06:11:39 PM PDT 24 1916592058 ps
T406 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2406546293 Jul 07 06:11:13 PM PDT 24 Jul 07 06:11:26 PM PDT 24 5920455451 ps
T407 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3534768156 Jul 07 06:10:25 PM PDT 24 Jul 07 06:10:37 PM PDT 24 4424571675 ps
T408 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2272452837 Jul 07 06:10:27 PM PDT 24 Jul 07 06:10:30 PM PDT 24 503394742 ps
T409 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.229085879 Jul 07 06:10:43 PM PDT 24 Jul 07 06:12:26 PM PDT 24 37500675556 ps
T410 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1561793487 Jul 07 06:10:54 PM PDT 24 Jul 07 06:11:01 PM PDT 24 214128448 ps
T411 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4051061580 Jul 07 06:11:04 PM PDT 24 Jul 07 06:11:08 PM PDT 24 569550008 ps
T412 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1116390811 Jul 07 06:10:07 PM PDT 24 Jul 07 06:10:09 PM PDT 24 52494524 ps
T413 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2555384519 Jul 07 06:11:28 PM PDT 24 Jul 07 06:11:30 PM PDT 24 139817844 ps
T414 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3631453799 Jul 07 06:10:20 PM PDT 24 Jul 07 06:10:22 PM PDT 24 257819416 ps
T106 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2593570843 Jul 07 06:10:01 PM PDT 24 Jul 07 06:10:06 PM PDT 24 5824208626 ps
T415 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3724180212 Jul 07 06:11:29 PM PDT 24 Jul 07 06:11:30 PM PDT 24 146912417 ps
T416 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3006346332 Jul 07 06:10:17 PM PDT 24 Jul 07 06:10:24 PM PDT 24 618616607 ps
T417 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1568708337 Jul 07 06:10:15 PM PDT 24 Jul 07 06:10:26 PM PDT 24 2151931824 ps
T418 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.818217425 Jul 07 06:10:48 PM PDT 24 Jul 07 06:10:52 PM PDT 24 276428309 ps
T419 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.389215142 Jul 07 06:10:47 PM PDT 24 Jul 07 06:10:48 PM PDT 24 74566187 ps
T420 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1611928762 Jul 07 06:10:43 PM PDT 24 Jul 07 06:10:45 PM PDT 24 1255134906 ps
T421 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3468643429 Jul 07 06:11:04 PM PDT 24 Jul 07 06:11:12 PM PDT 24 23313648264 ps
T422 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1855043865 Jul 07 06:11:30 PM PDT 24 Jul 07 06:11:33 PM PDT 24 109680907 ps
T423 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3838688454 Jul 07 06:10:26 PM PDT 24 Jul 07 06:10:55 PM PDT 24 11225483431 ps
T424 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3924285181 Jul 07 06:10:48 PM PDT 24 Jul 07 06:10:51 PM PDT 24 235138680 ps
T107 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3870527370 Jul 07 06:10:16 PM PDT 24 Jul 07 06:10:34 PM PDT 24 13306488105 ps
T425 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1325828842 Jul 07 06:11:15 PM PDT 24 Jul 07 06:11:26 PM PDT 24 13798705571 ps
T426 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3597587706 Jul 07 06:10:48 PM PDT 24 Jul 07 06:10:52 PM PDT 24 2744348075 ps

Test location /workspace/coverage/default/43.rv_dm_stress_all.2890123505
Short name T4
Test name
Test status
Simulation time 1879729294 ps
CPU time 1.86 seconds
Started Jul 07 06:12:26 PM PDT 24
Finished Jul 07 06:12:29 PM PDT 24
Peak memory 205252 kb
Host smart-465d4427-fc02-4b72-ac60-29ea17a9cf94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890123505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2890123505
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1609165181
Short name T11
Test name
Test status
Simulation time 7096165600 ps
CPU time 18.63 seconds
Started Jul 07 06:12:17 PM PDT 24
Finished Jul 07 06:12:36 PM PDT 24
Peak memory 214448 kb
Host smart-94349ee7-4dc0-4e64-b627-deb2ee4440ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609165181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1609165181
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.438827068
Short name T89
Test name
Test status
Simulation time 371768508 ps
CPU time 4.94 seconds
Started Jul 07 06:11:22 PM PDT 24
Finished Jul 07 06:11:27 PM PDT 24
Peak memory 221660 kb
Host smart-17838397-a22c-48ba-b497-e0ec9fc0d1a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438827068 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.438827068
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.3676135545
Short name T5
Test name
Test status
Simulation time 6906689170 ps
CPU time 11.22 seconds
Started Jul 07 06:11:57 PM PDT 24
Finished Jul 07 06:12:08 PM PDT 24
Peak memory 205284 kb
Host smart-37f72dcf-b630-4ac6-aab2-c724f0f5e096
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676135545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3676135545
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.388796250
Short name T9
Test name
Test status
Simulation time 5204324303 ps
CPU time 2.33 seconds
Started Jul 07 06:12:29 PM PDT 24
Finished Jul 07 06:12:31 PM PDT 24
Peak memory 205332 kb
Host smart-ee682386-37a2-4d1d-919c-c030a0524cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388796250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.388796250
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1224863423
Short name T103
Test name
Test status
Simulation time 13941186047 ps
CPU time 76.37 seconds
Started Jul 07 06:10:04 PM PDT 24
Finished Jul 07 06:11:21 PM PDT 24
Peak memory 213412 kb
Host smart-87ad9217-f280-476f-b5ec-2aece2f6e7ab
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224863423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1224863423
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3275882261
Short name T44
Test name
Test status
Simulation time 30955897308 ps
CPU time 51.27 seconds
Started Jul 07 06:10:06 PM PDT 24
Finished Jul 07 06:10:58 PM PDT 24
Peak memory 221556 kb
Host smart-599489f3-ef2f-4190-b00c-49a54240f2f8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275882261 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3275882261
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3133113450
Short name T27
Test name
Test status
Simulation time 25125841324 ps
CPU time 8.18 seconds
Started Jul 07 06:11:52 PM PDT 24
Finished Jul 07 06:12:00 PM PDT 24
Peak memory 213584 kb
Host smart-4ce75ee1-f3a3-4635-8f39-7ad2673b51ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133113450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3133113450
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2817841834
Short name T91
Test name
Test status
Simulation time 2881447590 ps
CPU time 15.63 seconds
Started Jul 07 06:11:31 PM PDT 24
Finished Jul 07 06:11:47 PM PDT 24
Peak memory 213348 kb
Host smart-88f57275-79a1-44e4-8453-aae010ab9c35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817841834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
817841834
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1775680579
Short name T128
Test name
Test status
Simulation time 46431625 ps
CPU time 0.85 seconds
Started Jul 07 06:12:17 PM PDT 24
Finished Jul 07 06:12:18 PM PDT 24
Peak memory 205076 kb
Host smart-4ea35309-3998-4201-9516-12b44a0b9b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775680579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1775680579
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.3944514228
Short name T47
Test name
Test status
Simulation time 132558727 ps
CPU time 0.84 seconds
Started Jul 07 06:11:37 PM PDT 24
Finished Jul 07 06:11:38 PM PDT 24
Peak memory 215740 kb
Host smart-40249500-5976-41b5-a491-a9704e0180cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944514228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3944514228
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1026821630
Short name T15
Test name
Test status
Simulation time 2060824993 ps
CPU time 3.37 seconds
Started Jul 07 06:11:37 PM PDT 24
Finished Jul 07 06:11:40 PM PDT 24
Peak memory 205196 kb
Host smart-3bd1a77b-3650-42ff-992b-039ce61c3291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026821630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1026821630
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1756155742
Short name T153
Test name
Test status
Simulation time 32197355537 ps
CPU time 86.57 seconds
Started Jul 07 06:12:06 PM PDT 24
Finished Jul 07 06:13:33 PM PDT 24
Peak memory 213632 kb
Host smart-eaf8547b-a9b4-4455-9158-6041ed10c109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756155742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1756155742
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1518911918
Short name T290
Test name
Test status
Simulation time 698180126 ps
CPU time 4.62 seconds
Started Jul 07 06:11:27 PM PDT 24
Finished Jul 07 06:11:32 PM PDT 24
Peak memory 213356 kb
Host smart-25b1a81e-30d6-4b51-9398-43363bc4e20a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518911918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1518911918
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3473622190
Short name T36
Test name
Test status
Simulation time 190959153 ps
CPU time 0.91 seconds
Started Jul 07 06:11:39 PM PDT 24
Finished Jul 07 06:11:41 PM PDT 24
Peak memory 205068 kb
Host smart-a702c17d-f7b3-41cd-8e95-5f2a0501cc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473622190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3473622190
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.341067915
Short name T24
Test name
Test status
Simulation time 10366214136 ps
CPU time 26.14 seconds
Started Jul 07 06:12:26 PM PDT 24
Finished Jul 07 06:12:52 PM PDT 24
Peak memory 205340 kb
Host smart-f149b164-44c4-444e-9431-fa603f001f7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341067915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.341067915
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3322166914
Short name T65
Test name
Test status
Simulation time 401868621 ps
CPU time 2.02 seconds
Started Jul 07 06:11:51 PM PDT 24
Finished Jul 07 06:11:53 PM PDT 24
Peak memory 229248 kb
Host smart-9eb85186-f36f-4767-b654-9a8d631bad43
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322166914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3322166914
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2462649254
Short name T26
Test name
Test status
Simulation time 16897315200 ps
CPU time 23.11 seconds
Started Jul 07 06:12:04 PM PDT 24
Finished Jul 07 06:12:27 PM PDT 24
Peak memory 213620 kb
Host smart-56d70271-52f8-4d61-a935-00c209921ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462649254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2462649254
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2635817168
Short name T35
Test name
Test status
Simulation time 56638829 ps
CPU time 0.89 seconds
Started Jul 07 06:11:36 PM PDT 24
Finished Jul 07 06:11:37 PM PDT 24
Peak memory 213360 kb
Host smart-546e2090-4092-4ef7-b11b-989cf43287c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635817168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2635817168
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3678052937
Short name T175
Test name
Test status
Simulation time 1012421677 ps
CPU time 17.27 seconds
Started Jul 07 06:10:31 PM PDT 24
Finished Jul 07 06:10:49 PM PDT 24
Peak memory 213380 kb
Host smart-8cb669cb-622c-44fd-b557-e76301e38eb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678052937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3678052937
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.181445679
Short name T22
Test name
Test status
Simulation time 15682067390 ps
CPU time 43.22 seconds
Started Jul 07 06:11:48 PM PDT 24
Finished Jul 07 06:12:31 PM PDT 24
Peak memory 213520 kb
Host smart-d5448858-a71d-4df4-8a68-af6df477ec86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181445679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.181445679
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.429881618
Short name T18
Test name
Test status
Simulation time 9908135203 ps
CPU time 22.19 seconds
Started Jul 07 06:12:20 PM PDT 24
Finished Jul 07 06:12:43 PM PDT 24
Peak memory 213492 kb
Host smart-9b26fca5-e2ff-4a36-9620-dddfb9433e29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429881618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.429881618
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2557416583
Short name T100
Test name
Test status
Simulation time 7528445884 ps
CPU time 74.57 seconds
Started Jul 07 06:10:16 PM PDT 24
Finished Jul 07 06:11:31 PM PDT 24
Peak memory 213488 kb
Host smart-a74888d1-3e05-4daa-96c8-98400a372b41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557416583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2557416583
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.924496465
Short name T149
Test name
Test status
Simulation time 9302886143 ps
CPU time 4.3 seconds
Started Jul 07 06:11:53 PM PDT 24
Finished Jul 07 06:11:58 PM PDT 24
Peak memory 213812 kb
Host smart-99e09a32-e086-4802-b7ae-7cdd210ee51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924496465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.924496465
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3426190416
Short name T38
Test name
Test status
Simulation time 1052903796 ps
CPU time 1.16 seconds
Started Jul 07 06:11:48 PM PDT 24
Finished Jul 07 06:11:49 PM PDT 24
Peak memory 205096 kb
Host smart-4a34f708-76fb-465d-a97d-01e9c32a31a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426190416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3426190416
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1997049977
Short name T150
Test name
Test status
Simulation time 4854322612 ps
CPU time 15.4 seconds
Started Jul 07 06:12:02 PM PDT 24
Finished Jul 07 06:12:18 PM PDT 24
Peak memory 213572 kb
Host smart-63b8beb8-39d6-4ef2-8784-9cd4922d24c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997049977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1997049977
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.858395442
Short name T17
Test name
Test status
Simulation time 1590900408 ps
CPU time 2.43 seconds
Started Jul 07 06:11:41 PM PDT 24
Finished Jul 07 06:11:44 PM PDT 24
Peak memory 205272 kb
Host smart-97ff20b4-002e-4956-8735-68013d65bf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858395442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.858395442
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2172057215
Short name T171
Test name
Test status
Simulation time 1891045203 ps
CPU time 5.29 seconds
Started Jul 07 06:11:31 PM PDT 24
Finished Jul 07 06:11:37 PM PDT 24
Peak memory 205372 kb
Host smart-e0e3cdb5-859c-455a-8bb9-0f3f0454ec2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172057215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2172057215
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2237427560
Short name T64
Test name
Test status
Simulation time 1462421401 ps
CPU time 2.94 seconds
Started Jul 07 06:12:06 PM PDT 24
Finished Jul 07 06:12:09 PM PDT 24
Peak memory 213596 kb
Host smart-ce378082-48aa-4dec-9113-343934d6545e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237427560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2237427560
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2972476678
Short name T163
Test name
Test status
Simulation time 2035812420 ps
CPU time 2.3 seconds
Started Jul 07 06:12:12 PM PDT 24
Finished Jul 07 06:12:15 PM PDT 24
Peak memory 205596 kb
Host smart-deda5e03-e7a5-42d2-924d-ab9223b10e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972476678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2972476678
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.2767069536
Short name T138
Test name
Test status
Simulation time 8392550991 ps
CPU time 6.14 seconds
Started Jul 07 06:12:30 PM PDT 24
Finished Jul 07 06:12:36 PM PDT 24
Peak memory 213508 kb
Host smart-61554b1d-7e2a-42cd-afb3-6e9dd42f89c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767069536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.2767069536
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2125566451
Short name T184
Test name
Test status
Simulation time 8636040825 ps
CPU time 10.27 seconds
Started Jul 07 06:11:15 PM PDT 24
Finished Jul 07 06:11:26 PM PDT 24
Peak memory 213444 kb
Host smart-7c25dd5d-6d79-4d6a-a329-887612e846b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125566451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
125566451
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1194607953
Short name T161
Test name
Test status
Simulation time 2037233271 ps
CPU time 2.76 seconds
Started Jul 07 06:12:06 PM PDT 24
Finished Jul 07 06:12:09 PM PDT 24
Peak memory 213768 kb
Host smart-4a98f1b6-4c81-4c1a-b19c-1d0c2ea99713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194607953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1194607953
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.219474813
Short name T148
Test name
Test status
Simulation time 18139542996 ps
CPU time 26.45 seconds
Started Jul 07 06:12:12 PM PDT 24
Finished Jul 07 06:12:39 PM PDT 24
Peak memory 213584 kb
Host smart-c74cbca0-6531-4c97-9444-765cacc7b87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219474813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.219474813
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.901316031
Short name T158
Test name
Test status
Simulation time 99378889771 ps
CPU time 196.65 seconds
Started Jul 07 06:12:11 PM PDT 24
Finished Jul 07 06:15:28 PM PDT 24
Peak memory 217764 kb
Host smart-1b079e8a-4358-42ce-bc09-84eeca55bb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901316031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.901316031
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3781203765
Short name T162
Test name
Test status
Simulation time 7024614544 ps
CPU time 11.11 seconds
Started Jul 07 06:12:14 PM PDT 24
Finished Jul 07 06:12:25 PM PDT 24
Peak memory 213516 kb
Host smart-dd1ad709-9d32-40e2-ac41-ea55384c96a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781203765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3781203765
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.3827020000
Short name T136
Test name
Test status
Simulation time 7196142853 ps
CPU time 19.62 seconds
Started Jul 07 06:12:24 PM PDT 24
Finished Jul 07 06:12:44 PM PDT 24
Peak memory 205300 kb
Host smart-dcc91c5a-56e5-405c-97e1-e5a03dda393d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827020000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3827020000
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.597282872
Short name T160
Test name
Test status
Simulation time 3831245141 ps
CPU time 7.27 seconds
Started Jul 07 06:11:52 PM PDT 24
Finished Jul 07 06:12:00 PM PDT 24
Peak memory 213652 kb
Host smart-cceb574b-7a96-49a3-bdbd-99a25384ada1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597282872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.597282872
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3834589731
Short name T159
Test name
Test status
Simulation time 5266536777 ps
CPU time 2.03 seconds
Started Jul 07 06:11:59 PM PDT 24
Finished Jul 07 06:12:01 PM PDT 24
Peak memory 213604 kb
Host smart-35ae4406-0bcb-452f-922f-ed47b8a09fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834589731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3834589731
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3154617424
Short name T306
Test name
Test status
Simulation time 268551617 ps
CPU time 1.31 seconds
Started Jul 07 06:11:10 PM PDT 24
Finished Jul 07 06:11:12 PM PDT 24
Peak memory 204800 kb
Host smart-46875bad-3bec-4c48-a386-2aee7601f304
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154617424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3154617424
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2593570843
Short name T106
Test name
Test status
Simulation time 5824208626 ps
CPU time 4.81 seconds
Started Jul 07 06:10:01 PM PDT 24
Finished Jul 07 06:10:06 PM PDT 24
Peak memory 205196 kb
Host smart-76e21776-fceb-47c0-b153-7b8ef8cca002
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593570843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2593570843
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2639376081
Short name T122
Test name
Test status
Simulation time 1335643772 ps
CPU time 4.41 seconds
Started Jul 07 06:10:14 PM PDT 24
Finished Jul 07 06:10:19 PM PDT 24
Peak memory 205096 kb
Host smart-d3306f73-beb7-4a0a-9adf-93334aa18a01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639376081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2639376081
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.871602464
Short name T32
Test name
Test status
Simulation time 534169873 ps
CPU time 2.08 seconds
Started Jul 07 06:11:34 PM PDT 24
Finished Jul 07 06:11:36 PM PDT 24
Peak memory 205084 kb
Host smart-39978370-2e27-412a-b6af-6385763a07cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871602464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.871602464
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3766234391
Short name T183
Test name
Test status
Simulation time 775045859 ps
CPU time 9.01 seconds
Started Jul 07 06:10:50 PM PDT 24
Finished Jul 07 06:10:59 PM PDT 24
Peak memory 213400 kb
Host smart-d6645d45-507e-4009-aeda-f8500dcfd745
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766234391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3766234391
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4092946726
Short name T174
Test name
Test status
Simulation time 64272172964 ps
CPU time 50.62 seconds
Started Jul 07 06:10:53 PM PDT 24
Finished Jul 07 06:11:44 PM PDT 24
Peak memory 226092 kb
Host smart-06174d5a-70a4-46d2-a10f-b077aa7b65da
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092946726 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.4092946726
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1690891707
Short name T30
Test name
Test status
Simulation time 81914113892 ps
CPU time 196.58 seconds
Started Jul 07 06:11:34 PM PDT 24
Finished Jul 07 06:14:51 PM PDT 24
Peak memory 215816 kb
Host smart-d18906ad-c6bd-4fad-b83f-cfede02e2829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690891707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1690891707
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.4003933640
Short name T164
Test name
Test status
Simulation time 2207358366 ps
CPU time 3.13 seconds
Started Jul 07 06:11:36 PM PDT 24
Finished Jul 07 06:11:39 PM PDT 24
Peak memory 213588 kb
Host smart-f3429be3-54c5-4cd1-85a1-625943925122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003933640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.4003933640
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.688540626
Short name T10
Test name
Test status
Simulation time 366840034 ps
CPU time 1.72 seconds
Started Jul 07 06:11:36 PM PDT 24
Finished Jul 07 06:11:39 PM PDT 24
Peak memory 205104 kb
Host smart-3d207927-a473-46b9-bb46-2c1c8b484b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688540626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.688540626
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.1320977747
Short name T37
Test name
Test status
Simulation time 580110932 ps
CPU time 2.15 seconds
Started Jul 07 06:11:46 PM PDT 24
Finished Jul 07 06:11:49 PM PDT 24
Peak memory 205080 kb
Host smart-bab32d35-7e2c-4296-9dff-0ef97ffd9fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320977747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.1320977747
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.3754056029
Short name T46
Test name
Test status
Simulation time 158449424 ps
CPU time 0.96 seconds
Started Jul 07 06:11:55 PM PDT 24
Finished Jul 07 06:11:56 PM PDT 24
Peak memory 215676 kb
Host smart-52d3e444-f983-4dd1-a076-f193e5bddbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754056029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3754056029
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3031821437
Short name T28
Test name
Test status
Simulation time 1092597850 ps
CPU time 3.24 seconds
Started Jul 07 06:11:44 PM PDT 24
Finished Jul 07 06:11:48 PM PDT 24
Peak memory 205072 kb
Host smart-5ef9deb1-db61-4756-a708-d69a01542de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031821437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3031821437
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2089939681
Short name T156
Test name
Test status
Simulation time 624012385 ps
CPU time 1.39 seconds
Started Jul 07 06:11:43 PM PDT 24
Finished Jul 07 06:11:45 PM PDT 24
Peak memory 205108 kb
Host smart-15b2aaa0-a202-46df-82ab-7f404d71caf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089939681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2089939681
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2912451959
Short name T41
Test name
Test status
Simulation time 2778971910 ps
CPU time 7.83 seconds
Started Jul 07 06:11:45 PM PDT 24
Finished Jul 07 06:11:53 PM PDT 24
Peak memory 205456 kb
Host smart-1f7da041-f225-4123-b17b-8f14f818031a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912451959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2912451959
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.4102655705
Short name T141
Test name
Test status
Simulation time 5512121001 ps
CPU time 9.76 seconds
Started Jul 07 06:11:48 PM PDT 24
Finished Jul 07 06:11:58 PM PDT 24
Peak memory 213484 kb
Host smart-9af33ac7-7eba-4955-a165-a26144bc2d33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102655705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.4102655705
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3266308637
Short name T172
Test name
Test status
Simulation time 5916123453 ps
CPU time 11.93 seconds
Started Jul 07 06:12:13 PM PDT 24
Finished Jul 07 06:12:25 PM PDT 24
Peak memory 213600 kb
Host smart-8f15190e-178b-4138-914f-6cd8ee58adad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266308637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3266308637
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.2206384292
Short name T147
Test name
Test status
Simulation time 9836137821 ps
CPU time 4.7 seconds
Started Jul 07 06:12:13 PM PDT 24
Finished Jul 07 06:12:18 PM PDT 24
Peak memory 213468 kb
Host smart-12c79ae7-a9f1-4dc0-a093-90e6ef28f21b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206384292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2206384292
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.1246042338
Short name T137
Test name
Test status
Simulation time 8829518659 ps
CPU time 22 seconds
Started Jul 07 06:12:28 PM PDT 24
Finished Jul 07 06:12:50 PM PDT 24
Peak memory 213356 kb
Host smart-5b8e75bc-0062-44f7-a75a-840fe44ef33e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246042338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1246042338
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3781191444
Short name T167
Test name
Test status
Simulation time 3742484240 ps
CPU time 2.75 seconds
Started Jul 07 06:12:01 PM PDT 24
Finished Jul 07 06:12:04 PM PDT 24
Peak memory 205460 kb
Host smart-c52a5300-0f3f-499e-86da-6658222299bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781191444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3781191444
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3197708644
Short name T170
Test name
Test status
Simulation time 4697382056 ps
CPU time 6.42 seconds
Started Jul 07 06:12:03 PM PDT 24
Finished Jul 07 06:12:09 PM PDT 24
Peak memory 205408 kb
Host smart-563b129c-11cd-44ab-baad-4b62e1f1a934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197708644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3197708644
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.3041934021
Short name T146
Test name
Test status
Simulation time 4033464236 ps
CPU time 7.42 seconds
Started Jul 07 06:12:04 PM PDT 24
Finished Jul 07 06:12:12 PM PDT 24
Peak memory 205204 kb
Host smart-50b385a6-1a39-4e7a-b9cf-fa5cd50b8479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041934021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3041934021
Directory /workspace/9.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1890837132
Short name T110
Test name
Test status
Simulation time 731186627 ps
CPU time 2.35 seconds
Started Jul 07 06:11:08 PM PDT 24
Finished Jul 07 06:11:10 PM PDT 24
Peak memory 213560 kb
Host smart-bb9c405a-235d-4e88-841c-b0272a29d8a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890837132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1890837132
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1351225780
Short name T345
Test name
Test status
Simulation time 142536613 ps
CPU time 1.7 seconds
Started Jul 07 06:10:15 PM PDT 24
Finished Jul 07 06:10:17 PM PDT 24
Peak memory 213388 kb
Host smart-27f2b178-3280-44c2-a46d-4e0732162990
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351225780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1351225780
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2219431165
Short name T381
Test name
Test status
Simulation time 4217909907 ps
CPU time 6.67 seconds
Started Jul 07 06:10:16 PM PDT 24
Finished Jul 07 06:10:23 PM PDT 24
Peak memory 221688 kb
Host smart-94557711-6f39-43d9-bda8-4c1b6d1c4619
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219431165 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2219431165
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.560624753
Short name T63
Test name
Test status
Simulation time 78398844 ps
CPU time 1.58 seconds
Started Jul 07 06:10:08 PM PDT 24
Finished Jul 07 06:10:10 PM PDT 24
Peak memory 213636 kb
Host smart-2aac29cb-5cc5-496b-ba52-cc98c71902dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560624753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.560624753
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1928856537
Short name T325
Test name
Test status
Simulation time 44094002751 ps
CPU time 40.15 seconds
Started Jul 07 06:10:05 PM PDT 24
Finished Jul 07 06:10:46 PM PDT 24
Peak memory 205056 kb
Host smart-e2077e45-d971-406e-8e22-ebc4c6538230
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928856537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1928856537
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1674342709
Short name T332
Test name
Test status
Simulation time 9880623466 ps
CPU time 5.64 seconds
Started Jul 07 06:10:05 PM PDT 24
Finished Jul 07 06:10:11 PM PDT 24
Peak memory 205016 kb
Host smart-20b0f7af-72e5-4173-b440-5dcb00843880
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674342709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.1674342709
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2288053362
Short name T293
Test name
Test status
Simulation time 5541483930 ps
CPU time 2.51 seconds
Started Jul 07 06:10:01 PM PDT 24
Finished Jul 07 06:10:03 PM PDT 24
Peak memory 205012 kb
Host smart-5ef8ca6b-bc3f-4257-992b-e436335b435e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288053362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
288053362
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.1916125007
Short name T322
Test name
Test status
Simulation time 595118517 ps
CPU time 1.23 seconds
Started Jul 07 06:10:02 PM PDT 24
Finished Jul 07 06:10:04 PM PDT 24
Peak memory 204756 kb
Host smart-56a0a313-7987-4aee-924f-a210fd3e552e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916125007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.1916125007
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2218814172
Short name T371
Test name
Test status
Simulation time 43719840342 ps
CPU time 45.44 seconds
Started Jul 07 06:10:02 PM PDT 24
Finished Jul 07 06:10:48 PM PDT 24
Peak memory 205068 kb
Host smart-4cd8d1d2-48a2-4acc-bcf8-0e3b12b6cf94
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218814172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2218814172
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.704714099
Short name T364
Test name
Test status
Simulation time 405499041 ps
CPU time 1.22 seconds
Started Jul 07 06:10:03 PM PDT 24
Finished Jul 07 06:10:04 PM PDT 24
Peak memory 204856 kb
Host smart-ffa60fd9-c2b5-4f10-a3dd-29f47e303a9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704714099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_hw_reset.704714099
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.943452440
Short name T354
Test name
Test status
Simulation time 113164556 ps
CPU time 0.78 seconds
Started Jul 07 06:10:01 PM PDT 24
Finished Jul 07 06:10:02 PM PDT 24
Peak memory 204796 kb
Host smart-811527e2-9ca9-4b74-ba1c-63a79529b892
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943452440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.943452440
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.173828350
Short name T323
Test name
Test status
Simulation time 48426761 ps
CPU time 0.72 seconds
Started Jul 07 06:10:18 PM PDT 24
Finished Jul 07 06:10:19 PM PDT 24
Peak memory 204728 kb
Host smart-b5f429ad-b27f-4666-9ab6-3d794b07c93f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173828350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.173828350
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3847979249
Short name T283
Test name
Test status
Simulation time 129032229 ps
CPU time 0.97 seconds
Started Jul 07 06:10:05 PM PDT 24
Finished Jul 07 06:10:06 PM PDT 24
Peak memory 205056 kb
Host smart-98355681-6708-4716-b095-d75abdece8ec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847979249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3847979249
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1116390811
Short name T412
Test name
Test status
Simulation time 52494524 ps
CPU time 2.31 seconds
Started Jul 07 06:10:07 PM PDT 24
Finished Jul 07 06:10:09 PM PDT 24
Peak memory 213348 kb
Host smart-ad25cb53-1f86-47b5-8138-62883bff2d8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116390811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1116390811
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1662132356
Short name T377
Test name
Test status
Simulation time 1337227253 ps
CPU time 10.78 seconds
Started Jul 07 06:10:08 PM PDT 24
Finished Jul 07 06:10:19 PM PDT 24
Peak memory 213416 kb
Host smart-8cd132bf-bf2e-462f-8a20-5ff755740800
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662132356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1662132356
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4242256068
Short name T98
Test name
Test status
Simulation time 2424770566 ps
CPU time 64.02 seconds
Started Jul 07 06:10:18 PM PDT 24
Finished Jul 07 06:11:23 PM PDT 24
Peak memory 213476 kb
Host smart-3f626476-532f-4091-93a7-2af2d7c18628
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242256068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.4242256068
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2312622977
Short name T118
Test name
Test status
Simulation time 9525673749 ps
CPU time 73.63 seconds
Started Jul 07 06:10:22 PM PDT 24
Finished Jul 07 06:11:36 PM PDT 24
Peak memory 213496 kb
Host smart-ed9da880-b96c-4b81-b999-ce32c2ed155d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312622977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2312622977
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2992885889
Short name T378
Test name
Test status
Simulation time 334502346 ps
CPU time 1.89 seconds
Started Jul 07 06:10:19 PM PDT 24
Finished Jul 07 06:10:21 PM PDT 24
Peak memory 213380 kb
Host smart-ab35e003-99b3-4632-b23a-4c51402bd2bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992885889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2992885889
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.990053989
Short name T327
Test name
Test status
Simulation time 58696111 ps
CPU time 2.07 seconds
Started Jul 07 06:10:20 PM PDT 24
Finished Jul 07 06:10:23 PM PDT 24
Peak memory 221464 kb
Host smart-87aab5eb-12d7-4ce9-a05d-8d7b38ad9a4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990053989 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.990053989
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3631453799
Short name T414
Test name
Test status
Simulation time 257819416 ps
CPU time 1.57 seconds
Started Jul 07 06:10:20 PM PDT 24
Finished Jul 07 06:10:22 PM PDT 24
Peak memory 213356 kb
Host smart-dac4f098-27b1-4ca4-b361-edfe334327c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631453799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3631453799
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.638456100
Short name T287
Test name
Test status
Simulation time 46561926077 ps
CPU time 125.49 seconds
Started Jul 07 06:10:20 PM PDT 24
Finished Jul 07 06:12:25 PM PDT 24
Peak memory 204888 kb
Host smart-9aa17781-e128-4fbd-b28a-a2e37d4a87aa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638456100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.638456100
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4003421355
Short name T285
Test name
Test status
Simulation time 7704894957 ps
CPU time 8.03 seconds
Started Jul 07 06:10:20 PM PDT 24
Finished Jul 07 06:10:29 PM PDT 24
Peak memory 204240 kb
Host smart-ba053760-2c6f-4111-8704-d77c682d6d8d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003421355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.4003421355
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3870527370
Short name T107
Test name
Test status
Simulation time 13306488105 ps
CPU time 17.41 seconds
Started Jul 07 06:10:16 PM PDT 24
Finished Jul 07 06:10:34 PM PDT 24
Peak memory 205196 kb
Host smart-41a838c7-ba0b-4fd6-a946-84e3d1ccb820
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870527370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3870527370
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1606390231
Short name T282
Test name
Test status
Simulation time 2497255027 ps
CPU time 7.07 seconds
Started Jul 07 06:10:13 PM PDT 24
Finished Jul 07 06:10:21 PM PDT 24
Peak memory 205044 kb
Host smart-244f6135-a5d6-4dd8-a1c8-69fa84ac98b4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606390231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
606390231
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3510216369
Short name T336
Test name
Test status
Simulation time 1245108569 ps
CPU time 2.37 seconds
Started Jul 07 06:10:20 PM PDT 24
Finished Jul 07 06:10:23 PM PDT 24
Peak memory 203968 kb
Host smart-a89d5950-3bef-4c6d-9ad6-e67f5c6227ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510216369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3510216369
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2714630703
Short name T394
Test name
Test status
Simulation time 17806810999 ps
CPU time 22.66 seconds
Started Jul 07 06:10:15 PM PDT 24
Finished Jul 07 06:10:37 PM PDT 24
Peak memory 205068 kb
Host smart-559e28b8-14ae-4952-830e-a26017401b92
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714630703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2714630703
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2613168834
Short name T341
Test name
Test status
Simulation time 874442566 ps
CPU time 1.89 seconds
Started Jul 07 06:10:14 PM PDT 24
Finished Jul 07 06:10:16 PM PDT 24
Peak memory 204864 kb
Host smart-c5ec6a5e-0da7-42fb-8d13-e1b482103639
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613168834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2613168834
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3645201852
Short name T368
Test name
Test status
Simulation time 485832029 ps
CPU time 1.22 seconds
Started Jul 07 06:10:17 PM PDT 24
Finished Jul 07 06:10:19 PM PDT 24
Peak memory 204816 kb
Host smart-729eb6ab-0b62-4c1e-ae94-19ee99cde296
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645201852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
645201852
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1636429560
Short name T277
Test name
Test status
Simulation time 149232895 ps
CPU time 0.77 seconds
Started Jul 07 06:10:20 PM PDT 24
Finished Jul 07 06:10:21 PM PDT 24
Peak memory 204640 kb
Host smart-d1ac072d-cc20-4e8f-9ce9-8006eecb8c34
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636429560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1636429560
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2538653666
Short name T316
Test name
Test status
Simulation time 32842799 ps
CPU time 0.7 seconds
Started Jul 07 06:10:19 PM PDT 24
Finished Jul 07 06:10:20 PM PDT 24
Peak memory 204792 kb
Host smart-1bcd9fdc-40eb-4af3-a2d6-0dd82a870c3c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538653666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2538653666
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1028498000
Short name T113
Test name
Test status
Simulation time 465514557 ps
CPU time 4.28 seconds
Started Jul 07 06:10:22 PM PDT 24
Finished Jul 07 06:10:27 PM PDT 24
Peak memory 205244 kb
Host smart-2c3b4914-fba0-4faa-a1a2-b96ca027dd48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028498000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1028498000
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3006346332
Short name T416
Test name
Test status
Simulation time 618616607 ps
CPU time 6.72 seconds
Started Jul 07 06:10:17 PM PDT 24
Finished Jul 07 06:10:24 PM PDT 24
Peak memory 213316 kb
Host smart-10f66d08-bca8-43e3-9277-3689f9234fa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006346332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3006346332
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1568708337
Short name T417
Test name
Test status
Simulation time 2151931824 ps
CPU time 10.41 seconds
Started Jul 07 06:10:15 PM PDT 24
Finished Jul 07 06:10:26 PM PDT 24
Peak memory 213452 kb
Host smart-733ac6d0-2f2c-4fbc-b77a-0f9f7a7af9aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568708337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1568708337
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1605106580
Short name T59
Test name
Test status
Simulation time 6599177827 ps
CPU time 6.06 seconds
Started Jul 07 06:11:08 PM PDT 24
Finished Jul 07 06:11:15 PM PDT 24
Peak memory 221588 kb
Host smart-6c79ba1f-d7e1-48a7-b0dd-ca5fce2c047d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605106580 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1605106580
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.140189367
Short name T337
Test name
Test status
Simulation time 1696754842 ps
CPU time 5.52 seconds
Started Jul 07 06:11:08 PM PDT 24
Finished Jul 07 06:11:14 PM PDT 24
Peak memory 204968 kb
Host smart-28ea48fc-85d5-4bd2-8939-961c5e70ade4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140189367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rv_dm_jtag_dmi_csr_bit_bash.140189367
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2406546293
Short name T406
Test name
Test status
Simulation time 5920455451 ps
CPU time 12.94 seconds
Started Jul 07 06:11:13 PM PDT 24
Finished Jul 07 06:11:26 PM PDT 24
Peak memory 205036 kb
Host smart-2f79efd9-d5c2-4846-8c3a-ab069e279853
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406546293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2406546293
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4208738664
Short name T351
Test name
Test status
Simulation time 361124291 ps
CPU time 1.54 seconds
Started Jul 07 06:11:08 PM PDT 24
Finished Jul 07 06:11:09 PM PDT 24
Peak memory 204800 kb
Host smart-a0845851-3db4-4c40-8715-747a8b7781f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208738664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
4208738664
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3173819695
Short name T114
Test name
Test status
Simulation time 312823792 ps
CPU time 4.54 seconds
Started Jul 07 06:11:09 PM PDT 24
Finished Jul 07 06:11:14 PM PDT 24
Peak memory 205164 kb
Host smart-62786e27-8904-4a1c-87d1-59b11f973c81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173819695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3173819695
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.483263427
Short name T312
Test name
Test status
Simulation time 952168304 ps
CPU time 5.72 seconds
Started Jul 07 06:11:07 PM PDT 24
Finished Jul 07 06:11:13 PM PDT 24
Peak memory 213376 kb
Host smart-4f05644d-3694-410b-ba19-43c2be0742b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483263427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.483263427
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2549596154
Short name T185
Test name
Test status
Simulation time 2609093568 ps
CPU time 11.1 seconds
Started Jul 07 06:11:10 PM PDT 24
Finished Jul 07 06:11:21 PM PDT 24
Peak memory 213512 kb
Host smart-adfdfc61-a10f-41f4-b8e4-64b879d15a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549596154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
549596154
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3367382850
Short name T372
Test name
Test status
Simulation time 417625228 ps
CPU time 2.49 seconds
Started Jul 07 06:11:13 PM PDT 24
Finished Jul 07 06:11:15 PM PDT 24
Peak memory 221540 kb
Host smart-311a669a-a69e-40e7-97c2-517cfbffd313
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367382850 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3367382850
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.755358547
Short name T108
Test name
Test status
Simulation time 409072494 ps
CPU time 1.59 seconds
Started Jul 07 06:11:12 PM PDT 24
Finished Jul 07 06:11:13 PM PDT 24
Peak memory 213360 kb
Host smart-a048af35-f8ba-43c0-adee-20798dfbf416
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755358547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.755358547
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1670169394
Short name T334
Test name
Test status
Simulation time 3149732259 ps
CPU time 5.21 seconds
Started Jul 07 06:11:10 PM PDT 24
Finished Jul 07 06:11:15 PM PDT 24
Peak memory 205040 kb
Host smart-9bade2dd-07ca-4a1e-aab5-1cbbba500f97
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670169394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1670169394
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1859102852
Short name T367
Test name
Test status
Simulation time 1197362176 ps
CPU time 2.96 seconds
Started Jul 07 06:11:13 PM PDT 24
Finished Jul 07 06:11:16 PM PDT 24
Peak memory 204976 kb
Host smart-485f974d-5d1a-44c0-a958-c304f25724f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859102852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1859102852
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.983734692
Short name T385
Test name
Test status
Simulation time 432443990 ps
CPU time 4.1 seconds
Started Jul 07 06:11:11 PM PDT 24
Finished Jul 07 06:11:16 PM PDT 24
Peak memory 205188 kb
Host smart-509361a5-f6d0-4864-89b2-ae4b0ba3e2f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983734692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.983734692
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1004319509
Short name T93
Test name
Test status
Simulation time 327780784 ps
CPU time 3.83 seconds
Started Jul 07 06:11:18 PM PDT 24
Finished Jul 07 06:11:22 PM PDT 24
Peak memory 213376 kb
Host smart-0284cad9-a0d0-4c64-8e65-b97d1e42496e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004319509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1004319509
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3556894360
Short name T180
Test name
Test status
Simulation time 3419321606 ps
CPU time 10.83 seconds
Started Jul 07 06:11:11 PM PDT 24
Finished Jul 07 06:11:22 PM PDT 24
Peak memory 213420 kb
Host smart-b131760f-8c91-430e-a6c6-b777d2913e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556894360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
556894360
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1493368234
Short name T131
Test name
Test status
Simulation time 3299029952 ps
CPU time 5.57 seconds
Started Jul 07 06:11:15 PM PDT 24
Finished Jul 07 06:11:21 PM PDT 24
Peak memory 219828 kb
Host smart-8ed75071-ea45-4186-b5a9-3d10a8927356
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493368234 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1493368234
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1983862848
Short name T112
Test name
Test status
Simulation time 114490786 ps
CPU time 2.33 seconds
Started Jul 07 06:11:16 PM PDT 24
Finished Jul 07 06:11:18 PM PDT 24
Peak memory 213352 kb
Host smart-ee7da717-5015-40c3-b2ef-872bb6743561
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983862848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1983862848
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.684628051
Short name T393
Test name
Test status
Simulation time 11404424042 ps
CPU time 17.03 seconds
Started Jul 07 06:11:15 PM PDT 24
Finished Jul 07 06:11:32 PM PDT 24
Peak memory 205028 kb
Host smart-17bec359-5981-434a-9e59-9ed52f29eac1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684628051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rv_dm_jtag_dmi_csr_bit_bash.684628051
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2201688764
Short name T278
Test name
Test status
Simulation time 7626234377 ps
CPU time 2.98 seconds
Started Jul 07 06:11:15 PM PDT 24
Finished Jul 07 06:11:19 PM PDT 24
Peak memory 205036 kb
Host smart-b8f1fb73-0340-4813-94aa-65c55ea848a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201688764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2201688764
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2491330463
Short name T382
Test name
Test status
Simulation time 275686318 ps
CPU time 0.99 seconds
Started Jul 07 06:11:11 PM PDT 24
Finished Jul 07 06:11:12 PM PDT 24
Peak memory 204796 kb
Host smart-f5d30941-d49f-4002-b761-5413e77d8c9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491330463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2491330463
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1332858344
Short name T109
Test name
Test status
Simulation time 781417691 ps
CPU time 7.21 seconds
Started Jul 07 06:11:17 PM PDT 24
Finished Jul 07 06:11:25 PM PDT 24
Peak memory 205208 kb
Host smart-d685244c-63bf-4859-aa3e-bdc96946817b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332858344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1332858344
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3113840122
Short name T90
Test name
Test status
Simulation time 431476860 ps
CPU time 2.48 seconds
Started Jul 07 06:11:15 PM PDT 24
Finished Jul 07 06:11:18 PM PDT 24
Peak memory 213416 kb
Host smart-d233e6c5-5dc1-4667-8280-71aa2d6a848f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113840122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3113840122
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3873094210
Short name T329
Test name
Test status
Simulation time 4923375152 ps
CPU time 5.18 seconds
Started Jul 07 06:11:18 PM PDT 24
Finished Jul 07 06:11:24 PM PDT 24
Peak memory 221448 kb
Host smart-557b59cc-91fd-4580-8a8e-8e1f6a43c3d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873094210 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3873094210
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.301555314
Short name T304
Test name
Test status
Simulation time 84070923 ps
CPU time 1.61 seconds
Started Jul 07 06:11:26 PM PDT 24
Finished Jul 07 06:11:28 PM PDT 24
Peak memory 213292 kb
Host smart-38dbb7ed-67d0-46a0-aa58-9918c69d5b3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301555314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.301555314
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2790963145
Short name T297
Test name
Test status
Simulation time 11347202065 ps
CPU time 32.02 seconds
Started Jul 07 06:11:16 PM PDT 24
Finished Jul 07 06:11:49 PM PDT 24
Peak memory 205068 kb
Host smart-f0c36b26-d0f1-4934-9ebe-d97b2cf4f16c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790963145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2790963145
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1325828842
Short name T425
Test name
Test status
Simulation time 13798705571 ps
CPU time 10.2 seconds
Started Jul 07 06:11:15 PM PDT 24
Finished Jul 07 06:11:26 PM PDT 24
Peak memory 205040 kb
Host smart-de7588ba-9764-4d54-b139-c344bbe18cee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325828842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1325828842
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2911778706
Short name T87
Test name
Test status
Simulation time 1092353099 ps
CPU time 3.56 seconds
Started Jul 07 06:11:18 PM PDT 24
Finished Jul 07 06:11:22 PM PDT 24
Peak memory 204836 kb
Host smart-d06a8b81-a597-43d7-8641-0610a36926ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911778706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2911778706
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.472079865
Short name T96
Test name
Test status
Simulation time 1301462945 ps
CPU time 4.06 seconds
Started Jul 07 06:11:20 PM PDT 24
Finished Jul 07 06:11:25 PM PDT 24
Peak memory 205236 kb
Host smart-05a199c3-b8e7-4117-b294-4cbbd14a7a72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472079865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.472079865
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3866861379
Short name T357
Test name
Test status
Simulation time 208875444 ps
CPU time 3.4 seconds
Started Jul 07 06:11:26 PM PDT 24
Finished Jul 07 06:11:29 PM PDT 24
Peak memory 213276 kb
Host smart-886cb46f-fb9e-4a93-be7e-6d5c0ed940ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866861379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3866861379
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3513195479
Short name T405
Test name
Test status
Simulation time 1916592058 ps
CPU time 12.56 seconds
Started Jul 07 06:11:26 PM PDT 24
Finished Jul 07 06:11:39 PM PDT 24
Peak memory 213308 kb
Host smart-181fac92-cd22-424f-9ca2-3d1128f41181
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513195479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
513195479
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2397789136
Short name T94
Test name
Test status
Simulation time 3158953318 ps
CPU time 8.04 seconds
Started Jul 07 06:11:24 PM PDT 24
Finished Jul 07 06:11:32 PM PDT 24
Peak memory 220496 kb
Host smart-9b1a232f-3745-4f64-841c-da2d2c643dd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397789136 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2397789136
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.850427305
Short name T117
Test name
Test status
Simulation time 292593530 ps
CPU time 2.39 seconds
Started Jul 07 06:11:22 PM PDT 24
Finished Jul 07 06:11:24 PM PDT 24
Peak memory 213280 kb
Host smart-4f29225b-bc08-4f08-a073-cd3bb61d8cb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850427305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.850427305
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3034506613
Short name T380
Test name
Test status
Simulation time 40143534463 ps
CPU time 56.16 seconds
Started Jul 07 06:11:20 PM PDT 24
Finished Jul 07 06:12:16 PM PDT 24
Peak memory 205084 kb
Host smart-df1d8026-ffc0-4315-bae3-5ee2fcadacdd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034506613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.3034506613
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3911444143
Short name T296
Test name
Test status
Simulation time 4180028714 ps
CPU time 10.99 seconds
Started Jul 07 06:11:26 PM PDT 24
Finished Jul 07 06:11:37 PM PDT 24
Peak memory 204964 kb
Host smart-b23cdc77-2900-4de1-b1fd-d31e829e78c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911444143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3911444143
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1446624500
Short name T396
Test name
Test status
Simulation time 911279114 ps
CPU time 1.21 seconds
Started Jul 07 06:11:20 PM PDT 24
Finished Jul 07 06:11:21 PM PDT 24
Peak memory 204796 kb
Host smart-8144a869-82cc-4d9c-8c70-e965a6b0868f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446624500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1446624500
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.4235227692
Short name T395
Test name
Test status
Simulation time 361725435 ps
CPU time 6.57 seconds
Started Jul 07 06:11:19 PM PDT 24
Finished Jul 07 06:11:26 PM PDT 24
Peak memory 205160 kb
Host smart-99cd638d-7d04-4cff-b0fe-c0673b8d503f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235227692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.4235227692
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1567041529
Short name T375
Test name
Test status
Simulation time 200168195 ps
CPU time 4.98 seconds
Started Jul 07 06:11:19 PM PDT 24
Finished Jul 07 06:11:24 PM PDT 24
Peak memory 213444 kb
Host smart-a5dc584d-fd42-49db-a8ca-7ccc68d5be11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567041529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1567041529
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.767933687
Short name T130
Test name
Test status
Simulation time 1922300835 ps
CPU time 20.45 seconds
Started Jul 07 06:11:19 PM PDT 24
Finished Jul 07 06:11:40 PM PDT 24
Peak memory 221484 kb
Host smart-2fb7d909-f2bf-471e-af3f-419a68797d52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767933687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.767933687
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2577355954
Short name T99
Test name
Test status
Simulation time 196168252 ps
CPU time 1.46 seconds
Started Jul 07 06:11:25 PM PDT 24
Finished Jul 07 06:11:27 PM PDT 24
Peak memory 213348 kb
Host smart-a8292cf9-ee50-470a-948d-2e2779856af1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577355954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2577355954
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3627970325
Short name T310
Test name
Test status
Simulation time 24892837943 ps
CPU time 44.31 seconds
Started Jul 07 06:11:32 PM PDT 24
Finished Jul 07 06:12:16 PM PDT 24
Peak memory 204900 kb
Host smart-94c5225c-aaf1-4ae4-940a-d4bcda6880f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627970325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.3627970325
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1904057741
Short name T284
Test name
Test status
Simulation time 12982259524 ps
CPU time 34.36 seconds
Started Jul 07 06:11:24 PM PDT 24
Finished Jul 07 06:11:59 PM PDT 24
Peak memory 205076 kb
Host smart-197df1a9-46d4-46d5-841b-7019c1a941a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904057741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1904057741
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2770510431
Short name T328
Test name
Test status
Simulation time 490030560 ps
CPU time 1.22 seconds
Started Jul 07 06:11:30 PM PDT 24
Finished Jul 07 06:11:31 PM PDT 24
Peak memory 204784 kb
Host smart-7ad0d59b-53ec-4ee6-b06c-5edb29945da1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770510431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2770510431
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1986472073
Short name T125
Test name
Test status
Simulation time 304254432 ps
CPU time 6.58 seconds
Started Jul 07 06:11:22 PM PDT 24
Finished Jul 07 06:11:29 PM PDT 24
Peak memory 205140 kb
Host smart-11f5af3a-8445-4ec7-8b8e-84e89b60f952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986472073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1986472073
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.924709167
Short name T353
Test name
Test status
Simulation time 1791251961 ps
CPU time 4.88 seconds
Started Jul 07 06:11:21 PM PDT 24
Finished Jul 07 06:11:26 PM PDT 24
Peak memory 221572 kb
Host smart-c9fff664-a47e-48ef-89f1-f8e2b0519f13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924709167 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.924709167
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.711249100
Short name T300
Test name
Test status
Simulation time 231109048 ps
CPU time 2.25 seconds
Started Jul 07 06:11:24 PM PDT 24
Finished Jul 07 06:11:26 PM PDT 24
Peak memory 213360 kb
Host smart-739d6cf4-5348-4bd4-a095-ea57184d918e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711249100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.711249100
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2818091609
Short name T369
Test name
Test status
Simulation time 58204019583 ps
CPU time 40.06 seconds
Started Jul 07 06:11:28 PM PDT 24
Finished Jul 07 06:12:08 PM PDT 24
Peak memory 205040 kb
Host smart-fc78c0e3-102e-4c10-9a10-b1a22523b602
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818091609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.2818091609
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2732407206
Short name T352
Test name
Test status
Simulation time 2260737934 ps
CPU time 6.5 seconds
Started Jul 07 06:11:21 PM PDT 24
Finished Jul 07 06:11:28 PM PDT 24
Peak memory 205040 kb
Host smart-9a3aa4ee-1bd6-4638-b018-cd49968ab60c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732407206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2732407206
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3724180212
Short name T415
Test name
Test status
Simulation time 146912417 ps
CPU time 0.83 seconds
Started Jul 07 06:11:29 PM PDT 24
Finished Jul 07 06:11:30 PM PDT 24
Peak memory 204800 kb
Host smart-4b2ac57d-a610-4a2a-a19a-647d47b4b104
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724180212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3724180212
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2108823703
Short name T386
Test name
Test status
Simulation time 393752421 ps
CPU time 4.34 seconds
Started Jul 07 06:11:31 PM PDT 24
Finished Jul 07 06:11:35 PM PDT 24
Peak memory 205036 kb
Host smart-4b8b51a7-7f95-4f7a-9eb5-aaa203a9b6e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108823703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.2108823703
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1241366459
Short name T346
Test name
Test status
Simulation time 562663769 ps
CPU time 6.91 seconds
Started Jul 07 06:11:30 PM PDT 24
Finished Jul 07 06:11:38 PM PDT 24
Peak memory 213280 kb
Host smart-733268cd-4902-4a94-a9d4-e99884a0ce57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241366459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1241366459
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1506832601
Short name T179
Test name
Test status
Simulation time 2923325319 ps
CPU time 14.94 seconds
Started Jul 07 06:11:31 PM PDT 24
Finished Jul 07 06:11:46 PM PDT 24
Peak memory 213296 kb
Host smart-bfbd415d-1b9e-498e-978b-b7c01159523c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506832601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
506832601
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2498139211
Short name T338
Test name
Test status
Simulation time 599872614 ps
CPU time 3.42 seconds
Started Jul 07 06:11:25 PM PDT 24
Finished Jul 07 06:11:29 PM PDT 24
Peak memory 218372 kb
Host smart-f320a881-8a9f-4a79-979f-822045b66a4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498139211 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2498139211
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1457483862
Short name T363
Test name
Test status
Simulation time 152281234 ps
CPU time 1.73 seconds
Started Jul 07 06:11:29 PM PDT 24
Finished Jul 07 06:11:31 PM PDT 24
Peak memory 213428 kb
Host smart-8abddce7-17bb-4992-9d7e-cd5d1daacbda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457483862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1457483862
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.616357761
Short name T299
Test name
Test status
Simulation time 23140988801 ps
CPU time 10.05 seconds
Started Jul 07 06:11:25 PM PDT 24
Finished Jul 07 06:11:35 PM PDT 24
Peak memory 205028 kb
Host smart-7b3e7220-2133-4614-a745-99471ac1a746
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616357761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.616357761
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.373047139
Short name T276
Test name
Test status
Simulation time 2894537177 ps
CPU time 2.06 seconds
Started Jul 07 06:11:26 PM PDT 24
Finished Jul 07 06:11:28 PM PDT 24
Peak memory 205052 kb
Host smart-9fe78682-0b2c-464a-a05b-5a1ddd9ffe45
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373047139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.373047139
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1389594106
Short name T339
Test name
Test status
Simulation time 125810204 ps
CPU time 0.76 seconds
Started Jul 07 06:11:26 PM PDT 24
Finished Jul 07 06:11:27 PM PDT 24
Peak memory 204792 kb
Host smart-1b8d1996-a9ed-4552-9648-be23ba23c302
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389594106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
1389594106
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1641611644
Short name T401
Test name
Test status
Simulation time 244206261 ps
CPU time 3.39 seconds
Started Jul 07 06:11:29 PM PDT 24
Finished Jul 07 06:11:33 PM PDT 24
Peak memory 205116 kb
Host smart-f7b8c496-2ddd-485c-aaa1-31c5d3383065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641611644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1641611644
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.3600208334
Short name T61
Test name
Test status
Simulation time 1226443619 ps
CPU time 4.55 seconds
Started Jul 07 06:11:27 PM PDT 24
Finished Jul 07 06:11:32 PM PDT 24
Peak memory 213356 kb
Host smart-3855ca01-701f-4e81-b801-1fe2605cb5b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600208334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.3600208334
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2356009974
Short name T182
Test name
Test status
Simulation time 1816985229 ps
CPU time 20 seconds
Started Jul 07 06:11:25 PM PDT 24
Finished Jul 07 06:11:46 PM PDT 24
Peak memory 213396 kb
Host smart-7fbb8166-34b8-4136-b4e2-f838453e7384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356009974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
356009974
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1802760948
Short name T324
Test name
Test status
Simulation time 178764445 ps
CPU time 2.34 seconds
Started Jul 07 06:11:33 PM PDT 24
Finished Jul 07 06:11:36 PM PDT 24
Peak memory 216736 kb
Host smart-b9cb767e-3b38-4b5b-b442-f4c4baef47b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802760948 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1802760948
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1292114432
Short name T116
Test name
Test status
Simulation time 221379487 ps
CPU time 2.48 seconds
Started Jul 07 06:11:29 PM PDT 24
Finished Jul 07 06:11:31 PM PDT 24
Peak memory 213368 kb
Host smart-3da87634-831b-46dd-9920-45981e61589e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292114432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1292114432
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.405543063
Short name T317
Test name
Test status
Simulation time 11259088991 ps
CPU time 29.6 seconds
Started Jul 07 06:11:33 PM PDT 24
Finished Jul 07 06:12:02 PM PDT 24
Peak memory 205036 kb
Host smart-cc2b1756-f7d1-407b-afc7-e3a404d988fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405543063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rv_dm_jtag_dmi_csr_bit_bash.405543063
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.83796765
Short name T391
Test name
Test status
Simulation time 2736184750 ps
CPU time 6.22 seconds
Started Jul 07 06:11:28 PM PDT 24
Finished Jul 07 06:11:35 PM PDT 24
Peak memory 205024 kb
Host smart-eb4cf5b8-b4db-434c-94da-327cca82360c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83796765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.83796765
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2555384519
Short name T413
Test name
Test status
Simulation time 139817844 ps
CPU time 1.03 seconds
Started Jul 07 06:11:28 PM PDT 24
Finished Jul 07 06:11:30 PM PDT 24
Peak memory 204712 kb
Host smart-2824b63e-71ce-46b7-8b09-10b081815353
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555384519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2555384519
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1721921419
Short name T359
Test name
Test status
Simulation time 211093329 ps
CPU time 6.55 seconds
Started Jul 07 06:11:28 PM PDT 24
Finished Jul 07 06:11:34 PM PDT 24
Peak memory 205160 kb
Host smart-f26535fd-fad4-4ba1-9874-885643e6e191
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721921419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1721921419
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1664036145
Short name T92
Test name
Test status
Simulation time 97969879 ps
CPU time 4.95 seconds
Started Jul 07 06:11:32 PM PDT 24
Finished Jul 07 06:11:37 PM PDT 24
Peak memory 213364 kb
Host smart-cc20b0e1-8cca-4d20-a25c-f3e6d8423403
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664036145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1664036145
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.28467661
Short name T358
Test name
Test status
Simulation time 1631213485 ps
CPU time 8.58 seconds
Started Jul 07 06:11:32 PM PDT 24
Finished Jul 07 06:11:41 PM PDT 24
Peak memory 213376 kb
Host smart-b57e71d5-8646-4c45-9381-2729fbbaaf18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28467661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.28467661
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1521187755
Short name T404
Test name
Test status
Simulation time 605322255 ps
CPU time 4.23 seconds
Started Jul 07 06:11:34 PM PDT 24
Finished Jul 07 06:11:39 PM PDT 24
Peak memory 219120 kb
Host smart-3948298f-bd92-452b-9fdd-06b2653f479d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521187755 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1521187755
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.344539491
Short name T373
Test name
Test status
Simulation time 224590040 ps
CPU time 1.58 seconds
Started Jul 07 06:11:30 PM PDT 24
Finished Jul 07 06:11:32 PM PDT 24
Peak memory 213304 kb
Host smart-b40822bd-ba81-41a0-9afc-3538e1d86d0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344539491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.344539491
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2831745590
Short name T294
Test name
Test status
Simulation time 3900693847 ps
CPU time 11.88 seconds
Started Jul 07 06:11:35 PM PDT 24
Finished Jul 07 06:11:47 PM PDT 24
Peak memory 205036 kb
Host smart-457927a7-2fdf-416a-9cf0-79bbd7665e49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831745590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2831745590
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2338377452
Short name T361
Test name
Test status
Simulation time 2621025155 ps
CPU time 4.76 seconds
Started Jul 07 06:11:30 PM PDT 24
Finished Jul 07 06:11:36 PM PDT 24
Peak memory 205040 kb
Host smart-aa2f0e86-d474-404a-ace6-0f046c3855fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338377452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2338377452
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1440682768
Short name T388
Test name
Test status
Simulation time 227759522 ps
CPU time 1.17 seconds
Started Jul 07 06:11:32 PM PDT 24
Finished Jul 07 06:11:33 PM PDT 24
Peak memory 204836 kb
Host smart-1e96cb2b-c846-4a4d-9d60-387a401ec7d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440682768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1440682768
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2111419033
Short name T123
Test name
Test status
Simulation time 201680772 ps
CPU time 3.93 seconds
Started Jul 07 06:11:36 PM PDT 24
Finished Jul 07 06:11:41 PM PDT 24
Peak memory 205120 kb
Host smart-6e2c77b2-e248-4a4f-93d2-83caeea0389f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111419033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2111419033
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1855043865
Short name T422
Test name
Test status
Simulation time 109680907 ps
CPU time 2.67 seconds
Started Jul 07 06:11:30 PM PDT 24
Finished Jul 07 06:11:33 PM PDT 24
Peak memory 213368 kb
Host smart-52a13769-2aa8-4b68-9db6-1b9b5586ec4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855043865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1855043865
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.569469802
Short name T181
Test name
Test status
Simulation time 2162202916 ps
CPU time 16.7 seconds
Started Jul 07 06:11:31 PM PDT 24
Finished Jul 07 06:11:48 PM PDT 24
Peak memory 213480 kb
Host smart-c025694d-9d86-48c9-b7da-b83523f7cfe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569469802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.569469802
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2557609270
Short name T303
Test name
Test status
Simulation time 3449711176 ps
CPU time 31.44 seconds
Started Jul 07 06:10:19 PM PDT 24
Finished Jul 07 06:10:51 PM PDT 24
Peak memory 213468 kb
Host smart-16509047-12b3-4669-8747-67374646a40a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557609270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2557609270
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.237744583
Short name T120
Test name
Test status
Simulation time 5872762292 ps
CPU time 54.32 seconds
Started Jul 07 06:10:30 PM PDT 24
Finished Jul 07 06:11:25 PM PDT 24
Peak memory 205252 kb
Host smart-3f1e33fa-18fc-4ae3-98b3-d618fa6ac1d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237744583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.237744583
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2426490249
Short name T101
Test name
Test status
Simulation time 733702480 ps
CPU time 2.62 seconds
Started Jul 07 06:10:26 PM PDT 24
Finished Jul 07 06:10:29 PM PDT 24
Peak memory 213468 kb
Host smart-0eb7d54d-6988-4819-8e4c-6809942e8e2e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426490249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2426490249
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3691754848
Short name T356
Test name
Test status
Simulation time 2919436173 ps
CPU time 6.46 seconds
Started Jul 07 06:10:29 PM PDT 24
Finished Jul 07 06:10:35 PM PDT 24
Peak memory 220464 kb
Host smart-91ede70f-6127-423c-b93e-56b1032dc4a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691754848 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3691754848
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.709485289
Short name T392
Test name
Test status
Simulation time 174619915 ps
CPU time 1.57 seconds
Started Jul 07 06:10:30 PM PDT 24
Finished Jul 07 06:10:32 PM PDT 24
Peak memory 213300 kb
Host smart-a62a4165-1e0e-4088-92ab-52947c06cce9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709485289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.709485289
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3241463829
Short name T292
Test name
Test status
Simulation time 27223742798 ps
CPU time 16.02 seconds
Started Jul 07 06:10:28 PM PDT 24
Finished Jul 07 06:10:44 PM PDT 24
Peak memory 205088 kb
Host smart-ea55deec-d4ce-42e3-9754-f9274264811a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241463829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3241463829
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3838688454
Short name T423
Test name
Test status
Simulation time 11225483431 ps
CPU time 28.38 seconds
Started Jul 07 06:10:26 PM PDT 24
Finished Jul 07 06:10:55 PM PDT 24
Peak memory 205000 kb
Host smart-23afa61b-fa73-4af7-b8db-ecde176780e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838688454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.3838688454
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4180952036
Short name T105
Test name
Test status
Simulation time 18656256221 ps
CPU time 51.78 seconds
Started Jul 07 06:10:22 PM PDT 24
Finished Jul 07 06:11:14 PM PDT 24
Peak memory 213408 kb
Host smart-25284332-9dad-4de3-a447-cda417359fba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180952036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.4180952036
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3534768156
Short name T407
Test name
Test status
Simulation time 4424571675 ps
CPU time 12.25 seconds
Started Jul 07 06:10:25 PM PDT 24
Finished Jul 07 06:10:37 PM PDT 24
Peak memory 205008 kb
Host smart-1fd9a5b3-5972-4421-a271-06c4d43a1458
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534768156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
534768156
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2685234122
Short name T88
Test name
Test status
Simulation time 2096187796 ps
CPU time 2.06 seconds
Started Jul 07 06:10:25 PM PDT 24
Finished Jul 07 06:10:28 PM PDT 24
Peak memory 204800 kb
Host smart-2077f765-5918-485a-a712-43f4eb5ab12b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685234122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2685234122
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.965007082
Short name T295
Test name
Test status
Simulation time 3356981065 ps
CPU time 9.18 seconds
Started Jul 07 06:10:25 PM PDT 24
Finished Jul 07 06:10:34 PM PDT 24
Peak memory 205304 kb
Host smart-bab06da8-d85c-481c-a5df-d322027ce291
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965007082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.965007082
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3869492405
Short name T321
Test name
Test status
Simulation time 820781385 ps
CPU time 1.13 seconds
Started Jul 07 06:10:23 PM PDT 24
Finished Jul 07 06:10:24 PM PDT 24
Peak memory 204856 kb
Host smart-456b7d32-977a-47f6-bcaf-21c1b4d6a8b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869492405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3869492405
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1463229286
Short name T331
Test name
Test status
Simulation time 403975365 ps
CPU time 1.29 seconds
Started Jul 07 06:10:24 PM PDT 24
Finished Jul 07 06:10:25 PM PDT 24
Peak memory 204724 kb
Host smart-1367753d-5fe8-435a-9ac4-b1bace26b2be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463229286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
463229286
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3953467913
Short name T313
Test name
Test status
Simulation time 79242284 ps
CPU time 0.87 seconds
Started Jul 07 06:10:28 PM PDT 24
Finished Jul 07 06:10:30 PM PDT 24
Peak memory 204756 kb
Host smart-f922bf35-42a6-4d58-942d-d2134ca006e9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953467913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3953467913
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2530998439
Short name T390
Test name
Test status
Simulation time 83171328 ps
CPU time 0.69 seconds
Started Jul 07 06:10:24 PM PDT 24
Finished Jul 07 06:10:25 PM PDT 24
Peak memory 204792 kb
Host smart-b34020c6-49ee-4354-9940-5b585b104181
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530998439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2530998439
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.112515525
Short name T115
Test name
Test status
Simulation time 321958966 ps
CPU time 6.14 seconds
Started Jul 07 06:10:29 PM PDT 24
Finished Jul 07 06:10:36 PM PDT 24
Peak memory 205176 kb
Host smart-2eeadd3e-3d76-4ca7-8598-6ae59e92d339
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112515525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.112515525
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2272452837
Short name T408
Test name
Test status
Simulation time 503394742 ps
CPU time 2.76 seconds
Started Jul 07 06:10:27 PM PDT 24
Finished Jul 07 06:10:30 PM PDT 24
Peak memory 213352 kb
Host smart-1e7a6a9c-5670-4701-b168-cd8ed9bfd045
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272452837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2272452837
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1057803230
Short name T111
Test name
Test status
Simulation time 5685670152 ps
CPU time 76.2 seconds
Started Jul 07 06:10:33 PM PDT 24
Finished Jul 07 06:11:49 PM PDT 24
Peak memory 213452 kb
Host smart-b483ba35-c308-4498-80bc-790d72f7709c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057803230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1057803230
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1694279116
Short name T314
Test name
Test status
Simulation time 5051283612 ps
CPU time 64.38 seconds
Started Jul 07 06:10:41 PM PDT 24
Finished Jul 07 06:11:46 PM PDT 24
Peak memory 205264 kb
Host smart-4b29da91-c4c0-40e4-aa52-27229ba88b4b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694279116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1694279116
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2732743362
Short name T97
Test name
Test status
Simulation time 261963263 ps
CPU time 1.62 seconds
Started Jul 07 06:10:37 PM PDT 24
Finished Jul 07 06:10:39 PM PDT 24
Peak memory 213404 kb
Host smart-31bac16e-919e-4f1f-8573-ae5dbc9341b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732743362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2732743362
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.529266511
Short name T362
Test name
Test status
Simulation time 3643485139 ps
CPU time 4.59 seconds
Started Jul 07 06:10:36 PM PDT 24
Finished Jul 07 06:10:41 PM PDT 24
Peak memory 219560 kb
Host smart-0c1f7bd2-b33d-42e0-a4a0-2c9f58effb82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529266511 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.529266511
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4048442628
Short name T384
Test name
Test status
Simulation time 127792845 ps
CPU time 2.42 seconds
Started Jul 07 06:10:37 PM PDT 24
Finished Jul 07 06:10:40 PM PDT 24
Peak memory 213268 kb
Host smart-552b3d7a-c82e-4ecd-a199-20a3216340c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048442628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.4048442628
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2122963186
Short name T308
Test name
Test status
Simulation time 13964669813 ps
CPU time 13.1 seconds
Started Jul 07 06:10:40 PM PDT 24
Finished Jul 07 06:10:53 PM PDT 24
Peak memory 205120 kb
Host smart-baa9e4d1-5e24-4c2b-9522-0b95f5712398
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122963186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2122963186
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1576132395
Short name T289
Test name
Test status
Simulation time 17053684581 ps
CPU time 24.73 seconds
Started Jul 07 06:10:36 PM PDT 24
Finished Jul 07 06:11:01 PM PDT 24
Peak memory 205040 kb
Host smart-b9477fb5-74ca-4453-bb16-2fc4c1fc600e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576132395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.1576132395
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3289806828
Short name T319
Test name
Test status
Simulation time 2594309745 ps
CPU time 4.89 seconds
Started Jul 07 06:10:35 PM PDT 24
Finished Jul 07 06:10:40 PM PDT 24
Peak memory 205092 kb
Host smart-2556260c-837c-48dd-97e1-bea1c5944367
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289806828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3289806828
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4270458933
Short name T400
Test name
Test status
Simulation time 2162299650 ps
CPU time 6.79 seconds
Started Jul 07 06:10:36 PM PDT 24
Finished Jul 07 06:10:43 PM PDT 24
Peak memory 205016 kb
Host smart-5b73bb5b-aad4-42ee-90aa-cec38d730516
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270458933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.4
270458933
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2770231905
Short name T302
Test name
Test status
Simulation time 1722029471 ps
CPU time 4.84 seconds
Started Jul 07 06:10:33 PM PDT 24
Finished Jul 07 06:10:39 PM PDT 24
Peak memory 204716 kb
Host smart-8415e9a6-d99e-464b-95c3-e9d40eadb2ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770231905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2770231905
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.908213249
Short name T330
Test name
Test status
Simulation time 12421841656 ps
CPU time 22.18 seconds
Started Jul 07 06:10:33 PM PDT 24
Finished Jul 07 06:10:55 PM PDT 24
Peak memory 205032 kb
Host smart-1360b706-5d4e-45c0-890b-65b0c0c94653
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908213249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.908213249
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1295181278
Short name T318
Test name
Test status
Simulation time 1359465773 ps
CPU time 1.26 seconds
Started Jul 07 06:10:37 PM PDT 24
Finished Jul 07 06:10:39 PM PDT 24
Peak memory 204876 kb
Host smart-9e052a35-da60-46b3-b48c-6fabfaf25e3e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295181278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1295181278
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4176345003
Short name T286
Test name
Test status
Simulation time 867806217 ps
CPU time 1.25 seconds
Started Jul 07 06:10:35 PM PDT 24
Finished Jul 07 06:10:37 PM PDT 24
Peak memory 204796 kb
Host smart-3e40a400-02ee-4a72-adc1-8b907ac39d72
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176345003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.4
176345003
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4278290582
Short name T340
Test name
Test status
Simulation time 74021528 ps
CPU time 0.69 seconds
Started Jul 07 06:10:36 PM PDT 24
Finished Jul 07 06:10:37 PM PDT 24
Peak memory 204728 kb
Host smart-57921f7d-67fc-44d2-b7bd-150683c6a8a9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278290582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.4278290582
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.898251190
Short name T307
Test name
Test status
Simulation time 82412838 ps
CPU time 0.75 seconds
Started Jul 07 06:10:41 PM PDT 24
Finished Jul 07 06:10:42 PM PDT 24
Peak memory 204780 kb
Host smart-441218ea-3d41-4ef2-8f00-cf713ce9cab0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898251190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.898251190
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3783358177
Short name T124
Test name
Test status
Simulation time 2717305410 ps
CPU time 6.52 seconds
Started Jul 07 06:10:36 PM PDT 24
Finished Jul 07 06:10:43 PM PDT 24
Peak memory 205236 kb
Host smart-5f804ed3-d809-4423-be72-8091e1ac4339
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783358177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3783358177
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.96217450
Short name T333
Test name
Test status
Simulation time 654231887 ps
CPU time 3.06 seconds
Started Jul 07 06:10:37 PM PDT 24
Finished Jul 07 06:10:40 PM PDT 24
Peak memory 213372 kb
Host smart-2594b36f-0e39-475b-bde7-0ca3c3507892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96217450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.96217450
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2830473920
Short name T178
Test name
Test status
Simulation time 1898697596 ps
CPU time 11.63 seconds
Started Jul 07 06:10:37 PM PDT 24
Finished Jul 07 06:10:49 PM PDT 24
Peak memory 213368 kb
Host smart-e174eaff-3a5b-4fe9-b387-7caae5be58d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830473920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2830473920
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.616931626
Short name T347
Test name
Test status
Simulation time 21010655968 ps
CPU time 35.65 seconds
Started Jul 07 06:10:42 PM PDT 24
Finished Jul 07 06:11:18 PM PDT 24
Peak memory 205436 kb
Host smart-f86ecaf6-49ed-4142-9811-f5b80072fb16
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616931626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.616931626
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2067744466
Short name T348
Test name
Test status
Simulation time 20505751755 ps
CPU time 65.4 seconds
Started Jul 07 06:10:50 PM PDT 24
Finished Jul 07 06:11:56 PM PDT 24
Peak memory 213480 kb
Host smart-6c7c879d-7356-47bb-a16a-f79c4eeeb32d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067744466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2067744466
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2126789341
Short name T62
Test name
Test status
Simulation time 239571019 ps
CPU time 1.59 seconds
Started Jul 07 06:10:46 PM PDT 24
Finished Jul 07 06:10:48 PM PDT 24
Peak memory 213340 kb
Host smart-32354436-2ff9-429f-b45f-a182de42275a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126789341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2126789341
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3924285181
Short name T424
Test name
Test status
Simulation time 235138680 ps
CPU time 2.78 seconds
Started Jul 07 06:10:48 PM PDT 24
Finished Jul 07 06:10:51 PM PDT 24
Peak memory 213436 kb
Host smart-688c8267-5b49-4192-83fe-5d22c5601258
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924285181 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3924285181
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4221531521
Short name T102
Test name
Test status
Simulation time 163042692 ps
CPU time 2.37 seconds
Started Jul 07 06:10:46 PM PDT 24
Finished Jul 07 06:10:49 PM PDT 24
Peak memory 213316 kb
Host smart-ff9066de-d63a-4772-955f-28976ef1b0aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221531521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.4221531521
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2780548151
Short name T279
Test name
Test status
Simulation time 48390353919 ps
CPU time 125.54 seconds
Started Jul 07 06:10:43 PM PDT 24
Finished Jul 07 06:12:49 PM PDT 24
Peak memory 205364 kb
Host smart-39856103-2acd-4de2-9ef7-44dec6e084fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780548151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2780548151
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3703232756
Short name T281
Test name
Test status
Simulation time 17610266731 ps
CPU time 49.81 seconds
Started Jul 07 06:10:47 PM PDT 24
Finished Jul 07 06:11:37 PM PDT 24
Peak memory 205048 kb
Host smart-6aa1cedb-0177-4508-9521-4de6d41fbdc5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703232756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.3703232756
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1611928762
Short name T420
Test name
Test status
Simulation time 1255134906 ps
CPU time 2.01 seconds
Started Jul 07 06:10:43 PM PDT 24
Finished Jul 07 06:10:45 PM PDT 24
Peak memory 205048 kb
Host smart-b6f0f129-7617-4edb-8107-49488ffda851
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611928762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1611928762
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3597587706
Short name T426
Test name
Test status
Simulation time 2744348075 ps
CPU time 4.15 seconds
Started Jul 07 06:10:48 PM PDT 24
Finished Jul 07 06:10:52 PM PDT 24
Peak memory 205036 kb
Host smart-2ff56996-b448-4cb2-80af-af00700a1812
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597587706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
597587706
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1228533055
Short name T397
Test name
Test status
Simulation time 1834841525 ps
CPU time 1.6 seconds
Started Jul 07 06:10:39 PM PDT 24
Finished Jul 07 06:10:41 PM PDT 24
Peak memory 204840 kb
Host smart-23b5178c-9519-43ac-9838-8da38b741b4f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228533055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1228533055
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.259512020
Short name T343
Test name
Test status
Simulation time 6071775967 ps
CPU time 9.17 seconds
Started Jul 07 06:10:40 PM PDT 24
Finished Jul 07 06:10:50 PM PDT 24
Peak memory 205072 kb
Host smart-7b79eb7a-4e20-4be2-8a2e-29bdd82a8202
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259512020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.259512020
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1638557908
Short name T342
Test name
Test status
Simulation time 202022574 ps
CPU time 0.78 seconds
Started Jul 07 06:10:45 PM PDT 24
Finished Jul 07 06:10:46 PM PDT 24
Peak memory 204856 kb
Host smart-06347483-3fb1-48fc-83a7-0abcfdeb6164
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638557908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1638557908
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1894945563
Short name T311
Test name
Test status
Simulation time 493029366 ps
CPU time 1.37 seconds
Started Jul 07 06:10:40 PM PDT 24
Finished Jul 07 06:10:42 PM PDT 24
Peak memory 204828 kb
Host smart-11402e0b-1ad1-4fcb-a129-2277c667295c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894945563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
894945563
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2053599735
Short name T379
Test name
Test status
Simulation time 67736419 ps
CPU time 0.72 seconds
Started Jul 07 06:10:48 PM PDT 24
Finished Jul 07 06:10:49 PM PDT 24
Peak memory 204720 kb
Host smart-962e7a8c-a944-46d3-87db-33a95d30c907
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053599735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2053599735
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.389215142
Short name T419
Test name
Test status
Simulation time 74566187 ps
CPU time 0.69 seconds
Started Jul 07 06:10:47 PM PDT 24
Finished Jul 07 06:10:48 PM PDT 24
Peak memory 204776 kb
Host smart-cb978d82-aae7-4da6-87a9-f391cb4b3a54
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389215142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.389215142
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.818217425
Short name T418
Test name
Test status
Simulation time 276428309 ps
CPU time 4.28 seconds
Started Jul 07 06:10:48 PM PDT 24
Finished Jul 07 06:10:52 PM PDT 24
Peak memory 205092 kb
Host smart-e55e66e8-2d98-4f3a-8c90-b3a69b201b84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818217425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.818217425
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.229085879
Short name T409
Test name
Test status
Simulation time 37500675556 ps
CPU time 102.65 seconds
Started Jul 07 06:10:43 PM PDT 24
Finished Jul 07 06:12:26 PM PDT 24
Peak memory 221416 kb
Host smart-074a81d4-5836-4756-8990-ad24d685c2dd
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229085879 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.229085879
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.451306593
Short name T344
Test name
Test status
Simulation time 722492356 ps
CPU time 3.11 seconds
Started Jul 07 06:10:47 PM PDT 24
Finished Jul 07 06:10:50 PM PDT 24
Peak memory 213396 kb
Host smart-ced0d391-6683-4505-a179-e3b5cc0fecf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451306593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.451306593
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3702871447
Short name T132
Test name
Test status
Simulation time 1648977129 ps
CPU time 9.88 seconds
Started Jul 07 06:10:47 PM PDT 24
Finished Jul 07 06:10:57 PM PDT 24
Peak memory 213384 kb
Host smart-689cbd62-6a00-46b0-a436-45a833febb55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702871447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3702871447
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.480921181
Short name T355
Test name
Test status
Simulation time 3577520894 ps
CPU time 4.79 seconds
Started Jul 07 06:10:53 PM PDT 24
Finished Jul 07 06:10:58 PM PDT 24
Peak memory 218172 kb
Host smart-cbfbd79a-4101-455c-aa6a-e14670f2f379
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480921181 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.480921181
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2464693742
Short name T126
Test name
Test status
Simulation time 81464288 ps
CPU time 1.52 seconds
Started Jul 07 06:10:49 PM PDT 24
Finished Jul 07 06:10:51 PM PDT 24
Peak memory 213324 kb
Host smart-8a3b070b-02f4-4a0d-840c-d1c2e8812830
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464693742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2464693742
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3068618733
Short name T389
Test name
Test status
Simulation time 65128366381 ps
CPU time 84.69 seconds
Started Jul 07 06:10:52 PM PDT 24
Finished Jul 07 06:12:16 PM PDT 24
Peak memory 205044 kb
Host smart-831b21d3-7059-49e9-8435-faab41528015
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068618733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3068618733
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.155622867
Short name T298
Test name
Test status
Simulation time 12117668188 ps
CPU time 10.36 seconds
Started Jul 07 06:10:53 PM PDT 24
Finished Jul 07 06:11:04 PM PDT 24
Peak memory 205036 kb
Host smart-e7cc0f06-3aec-45e5-809e-8c6726f49c08
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155622867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.155622867
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1800130678
Short name T301
Test name
Test status
Simulation time 972402920 ps
CPU time 1.36 seconds
Started Jul 07 06:10:51 PM PDT 24
Finished Jul 07 06:10:53 PM PDT 24
Peak memory 204836 kb
Host smart-cd946d98-dc13-4be9-b7bb-725c304b25f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800130678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
800130678
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.680970922
Short name T121
Test name
Test status
Simulation time 1286859644 ps
CPU time 8.22 seconds
Started Jul 07 06:10:54 PM PDT 24
Finished Jul 07 06:11:03 PM PDT 24
Peak memory 205236 kb
Host smart-93d63fd8-c0d3-43a2-9690-cc3177ce87c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680970922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.680970922
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3248046385
Short name T374
Test name
Test status
Simulation time 25514909559 ps
CPU time 14.92 seconds
Started Jul 07 06:10:55 PM PDT 24
Finished Jul 07 06:11:10 PM PDT 24
Peak memory 221628 kb
Host smart-6717e310-848f-4108-bc09-09b6daafa291
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248046385 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3248046385
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3279660956
Short name T335
Test name
Test status
Simulation time 1098250450 ps
CPU time 5.29 seconds
Started Jul 07 06:10:49 PM PDT 24
Finished Jul 07 06:10:55 PM PDT 24
Peak memory 213424 kb
Host smart-54d5fe34-e129-48e2-99c7-eb077cf3ebf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279660956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3279660956
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.828380581
Short name T104
Test name
Test status
Simulation time 2109700779 ps
CPU time 5.17 seconds
Started Jul 07 06:10:53 PM PDT 24
Finished Jul 07 06:10:59 PM PDT 24
Peak memory 218844 kb
Host smart-89359771-d3ec-42f9-b162-08923c36b1a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828380581 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.828380581
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1039944347
Short name T366
Test name
Test status
Simulation time 1120437246 ps
CPU time 2.58 seconds
Started Jul 07 06:10:56 PM PDT 24
Finished Jul 07 06:10:59 PM PDT 24
Peak memory 213328 kb
Host smart-86fe2a36-ba85-415a-a0dd-9c633af29de7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039944347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1039944347
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2116318291
Short name T326
Test name
Test status
Simulation time 9181226519 ps
CPU time 23.51 seconds
Started Jul 07 06:10:55 PM PDT 24
Finished Jul 07 06:11:19 PM PDT 24
Peak memory 205040 kb
Host smart-f074b92d-9552-4717-a8fc-494a76eed5df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116318291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.2116318291
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1698788569
Short name T280
Test name
Test status
Simulation time 3498469606 ps
CPU time 5.17 seconds
Started Jul 07 06:10:51 PM PDT 24
Finished Jul 07 06:10:56 PM PDT 24
Peak memory 205088 kb
Host smart-521c21d6-5451-4c7a-a4ba-e3bd3176d0cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698788569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
698788569
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.4268092818
Short name T291
Test name
Test status
Simulation time 271747217 ps
CPU time 1.31 seconds
Started Jul 07 06:10:49 PM PDT 24
Finished Jul 07 06:10:51 PM PDT 24
Peak memory 204800 kb
Host smart-37867b6f-5fa0-4ec9-8736-b1c2da34e182
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268092818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.4
268092818
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1561793487
Short name T410
Test name
Test status
Simulation time 214128448 ps
CPU time 6.5 seconds
Started Jul 07 06:10:54 PM PDT 24
Finished Jul 07 06:11:01 PM PDT 24
Peak memory 205140 kb
Host smart-6b39d4a2-ac9e-46b5-956a-ebf7f59d6f6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561793487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1561793487
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1915250492
Short name T350
Test name
Test status
Simulation time 429421448 ps
CPU time 4.93 seconds
Started Jul 07 06:10:53 PM PDT 24
Finished Jul 07 06:10:58 PM PDT 24
Peak memory 213312 kb
Host smart-5cce951a-2e46-4e50-93da-94543a9b6377
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915250492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1915250492
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2167956907
Short name T133
Test name
Test status
Simulation time 718754839 ps
CPU time 8.33 seconds
Started Jul 07 06:10:56 PM PDT 24
Finished Jul 07 06:11:05 PM PDT 24
Peak memory 213276 kb
Host smart-446d65eb-c913-4aab-a2e1-daa14d86155a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167956907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2167956907
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3642366280
Short name T60
Test name
Test status
Simulation time 4318658512 ps
CPU time 8.16 seconds
Started Jul 07 06:10:59 PM PDT 24
Finished Jul 07 06:11:07 PM PDT 24
Peak memory 217724 kb
Host smart-09e0f74c-a32f-4c83-9219-1c9c83c7fa76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642366280 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3642366280
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.243220206
Short name T376
Test name
Test status
Simulation time 163565636 ps
CPU time 2.25 seconds
Started Jul 07 06:10:58 PM PDT 24
Finished Jul 07 06:11:01 PM PDT 24
Peak memory 213384 kb
Host smart-1d8e7b85-145f-430f-98e3-3f1734f86867
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243220206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.243220206
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2404756779
Short name T360
Test name
Test status
Simulation time 19151413747 ps
CPU time 19.63 seconds
Started Jul 07 06:10:57 PM PDT 24
Finished Jul 07 06:11:17 PM PDT 24
Peak memory 205080 kb
Host smart-f21caa86-7711-464f-9ade-d30a99f7f208
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404756779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2404756779
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2960126859
Short name T387
Test name
Test status
Simulation time 1905401141 ps
CPU time 3.53 seconds
Started Jul 07 06:10:55 PM PDT 24
Finished Jul 07 06:10:59 PM PDT 24
Peak memory 204984 kb
Host smart-fffb5b68-a5a3-46a0-ac0d-4ae10b19b803
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960126859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
960126859
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2708556027
Short name T86
Test name
Test status
Simulation time 221358976 ps
CPU time 0.99 seconds
Started Jul 07 06:10:56 PM PDT 24
Finished Jul 07 06:10:58 PM PDT 24
Peak memory 204792 kb
Host smart-af48b819-6483-43f5-9eb7-1924338b13b0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708556027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
708556027
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2693630213
Short name T403
Test name
Test status
Simulation time 2803098218 ps
CPU time 6.52 seconds
Started Jul 07 06:10:57 PM PDT 24
Finished Jul 07 06:11:04 PM PDT 24
Peak memory 205212 kb
Host smart-04044eb7-b6ab-473f-bd21-cbe4be1f0abd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693630213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2693630213
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3600751583
Short name T315
Test name
Test status
Simulation time 185513565 ps
CPU time 3.07 seconds
Started Jul 07 06:10:57 PM PDT 24
Finished Jul 07 06:11:00 PM PDT 24
Peak memory 213656 kb
Host smart-277dc521-7283-4ad4-80d1-e3e7a8cbdac5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600751583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3600751583
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.163016278
Short name T177
Test name
Test status
Simulation time 6637260961 ps
CPU time 34.32 seconds
Started Jul 07 06:11:00 PM PDT 24
Finished Jul 07 06:11:35 PM PDT 24
Peak memory 213388 kb
Host smart-e9413f31-26e5-4daf-9048-cebd98ad9e3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163016278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.163016278
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3892594130
Short name T402
Test name
Test status
Simulation time 2290517079 ps
CPU time 4.07 seconds
Started Jul 07 06:11:05 PM PDT 24
Finished Jul 07 06:11:10 PM PDT 24
Peak memory 220156 kb
Host smart-fea70d37-0792-4771-b4b6-89e71f8e653f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892594130 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3892594130
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3069448226
Short name T399
Test name
Test status
Simulation time 453075077 ps
CPU time 1.44 seconds
Started Jul 07 06:11:03 PM PDT 24
Finished Jul 07 06:11:05 PM PDT 24
Peak memory 213368 kb
Host smart-f83842d9-ed2f-42b0-9c61-92ca68cc0ad3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069448226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3069448226
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3468643429
Short name T421
Test name
Test status
Simulation time 23313648264 ps
CPU time 7.26 seconds
Started Jul 07 06:11:04 PM PDT 24
Finished Jul 07 06:11:12 PM PDT 24
Peak memory 205060 kb
Host smart-6d6e63f6-c114-4876-a401-0547e44e0288
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468643429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.3468643429
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.612010766
Short name T309
Test name
Test status
Simulation time 1588645714 ps
CPU time 4.86 seconds
Started Jul 07 06:11:00 PM PDT 24
Finished Jul 07 06:11:05 PM PDT 24
Peak memory 204884 kb
Host smart-7dcce0b6-b53e-4f9e-8805-c771b8af812b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612010766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.612010766
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3180052489
Short name T320
Test name
Test status
Simulation time 256230549 ps
CPU time 1.21 seconds
Started Jul 07 06:11:01 PM PDT 24
Finished Jul 07 06:11:02 PM PDT 24
Peak memory 204792 kb
Host smart-3fa74807-7195-4090-ad53-c1a0a2c23580
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180052489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
180052489
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4051061580
Short name T411
Test name
Test status
Simulation time 569550008 ps
CPU time 3.49 seconds
Started Jul 07 06:11:04 PM PDT 24
Finished Jul 07 06:11:08 PM PDT 24
Peak memory 205192 kb
Host smart-19944ee7-ceb7-416d-a34f-2c6e236246e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051061580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.4051061580
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.587422568
Short name T45
Test name
Test status
Simulation time 12826241079 ps
CPU time 35.88 seconds
Started Jul 07 06:11:01 PM PDT 24
Finished Jul 07 06:11:37 PM PDT 24
Peak memory 221092 kb
Host smart-6f663593-b3d1-4fac-a2bb-996c860c9fab
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587422568 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.587422568
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1064685207
Short name T305
Test name
Test status
Simulation time 1130608845 ps
CPU time 3.19 seconds
Started Jul 07 06:11:00 PM PDT 24
Finished Jul 07 06:11:04 PM PDT 24
Peak memory 213352 kb
Host smart-b1c32990-c3ce-4126-8fdc-653d9188c69f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064685207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1064685207
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1533637174
Short name T186
Test name
Test status
Simulation time 495144666 ps
CPU time 8.83 seconds
Started Jul 07 06:11:05 PM PDT 24
Finished Jul 07 06:11:14 PM PDT 24
Peak memory 213336 kb
Host smart-2d18bc1f-3f26-46b6-8160-0d6d592ce4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533637174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1533637174
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1958925503
Short name T58
Test name
Test status
Simulation time 438113042 ps
CPU time 3.94 seconds
Started Jul 07 06:11:07 PM PDT 24
Finished Jul 07 06:11:11 PM PDT 24
Peak memory 216840 kb
Host smart-6601cb48-0bcd-4f18-8757-227302050874
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958925503 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1958925503
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2599561741
Short name T119
Test name
Test status
Simulation time 523225505 ps
CPU time 1.58 seconds
Started Jul 07 06:11:10 PM PDT 24
Finished Jul 07 06:11:11 PM PDT 24
Peak memory 213360 kb
Host smart-798d244a-e7c0-4771-9ad9-53046819a083
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599561741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2599561741
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2203839436
Short name T288
Test name
Test status
Simulation time 18747405899 ps
CPU time 26.67 seconds
Started Jul 07 06:11:04 PM PDT 24
Finished Jul 07 06:11:31 PM PDT 24
Peak memory 204944 kb
Host smart-416fa53b-bc63-434b-8168-adb40095b4c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203839436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2203839436
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.4088016803
Short name T365
Test name
Test status
Simulation time 11615837724 ps
CPU time 9.2 seconds
Started Jul 07 06:11:09 PM PDT 24
Finished Jul 07 06:11:18 PM PDT 24
Peak memory 205064 kb
Host smart-c42fe140-d15a-4edc-8e02-74bd65e3a1f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088016803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.4
088016803
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.279169562
Short name T370
Test name
Test status
Simulation time 1045124526 ps
CPU time 0.96 seconds
Started Jul 07 06:11:05 PM PDT 24
Finished Jul 07 06:11:07 PM PDT 24
Peak memory 204824 kb
Host smart-87048c86-c2be-4973-9820-140b0024eff9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279169562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.279169562
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.79237201
Short name T383
Test name
Test status
Simulation time 441217020 ps
CPU time 7.4 seconds
Started Jul 07 06:11:08 PM PDT 24
Finished Jul 07 06:11:16 PM PDT 24
Peak memory 205224 kb
Host smart-5215adf1-b26c-4e42-8ba6-c26c3c51aa0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79237201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_cs
r_outstanding.79237201
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.4212205623
Short name T398
Test name
Test status
Simulation time 25266115713 ps
CPU time 70.97 seconds
Started Jul 07 06:11:08 PM PDT 24
Finished Jul 07 06:12:19 PM PDT 24
Peak memory 220516 kb
Host smart-46842448-3bf9-4a22-89c7-cc232941ff3c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212205623 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.4212205623
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1836514979
Short name T349
Test name
Test status
Simulation time 104852790 ps
CPU time 2.18 seconds
Started Jul 07 06:11:04 PM PDT 24
Finished Jul 07 06:11:07 PM PDT 24
Peak memory 213356 kb
Host smart-ce6f99ee-9a28-4ecb-982c-1082f32aa029
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836514979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1836514979
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3662025290
Short name T176
Test name
Test status
Simulation time 1089546748 ps
CPU time 10.81 seconds
Started Jul 07 06:11:08 PM PDT 24
Finished Jul 07 06:11:19 PM PDT 24
Peak memory 213376 kb
Host smart-0b459f71-23e7-4b81-9b80-43602ffb9bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662025290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3662025290
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1622649986
Short name T57
Test name
Test status
Simulation time 40813823 ps
CPU time 0.76 seconds
Started Jul 07 06:11:39 PM PDT 24
Finished Jul 07 06:11:40 PM PDT 24
Peak memory 205076 kb
Host smart-97174a9a-1e3e-4c53-9e6d-4def89df5b16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622649986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1622649986
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.956240988
Short name T166
Test name
Test status
Simulation time 475873833 ps
CPU time 1.89 seconds
Started Jul 07 06:11:34 PM PDT 24
Finished Jul 07 06:11:36 PM PDT 24
Peak memory 205088 kb
Host smart-383c4c1c-1789-46ff-bc93-449988eb8374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956240988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.956240988
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2739739359
Short name T165
Test name
Test status
Simulation time 66665529 ps
CPU time 0.81 seconds
Started Jul 07 06:11:32 PM PDT 24
Finished Jul 07 06:11:33 PM PDT 24
Peak memory 205324 kb
Host smart-2842de30-1cfd-4e0c-95f0-e4c9eda5a198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739739359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2739739359
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1427440524
Short name T272
Test name
Test status
Simulation time 1711556120 ps
CPU time 3.5 seconds
Started Jul 07 06:11:34 PM PDT 24
Finished Jul 07 06:11:38 PM PDT 24
Peak memory 205320 kb
Host smart-321f237b-a8ef-4ecf-acf1-17d96c851490
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1427440524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1427440524
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2141570164
Short name T187
Test name
Test status
Simulation time 364670091 ps
CPU time 1 seconds
Started Jul 07 06:11:39 PM PDT 24
Finished Jul 07 06:11:41 PM PDT 24
Peak memory 205020 kb
Host smart-12143499-1f98-4b6f-8b54-062fabf49b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141570164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2141570164
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.992718667
Short name T250
Test name
Test status
Simulation time 227019397 ps
CPU time 0.8 seconds
Started Jul 07 06:11:35 PM PDT 24
Finished Jul 07 06:11:36 PM PDT 24
Peak memory 205076 kb
Host smart-48c4f744-c93a-46e7-9cf1-a1227d7d77a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992718667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.992718667
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2108400924
Short name T214
Test name
Test status
Simulation time 482694015 ps
CPU time 1.37 seconds
Started Jul 07 06:11:38 PM PDT 24
Finished Jul 07 06:11:39 PM PDT 24
Peak memory 205060 kb
Host smart-965d0ca2-6b51-4f9b-a436-179d5aadf984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108400924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2108400924
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4139108765
Short name T3
Test name
Test status
Simulation time 890710973 ps
CPU time 2.06 seconds
Started Jul 07 06:11:38 PM PDT 24
Finished Jul 07 06:11:40 PM PDT 24
Peak memory 204960 kb
Host smart-058aabb8-0ae0-4ec2-a628-f0ab448a8f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139108765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4139108765
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.781706293
Short name T255
Test name
Test status
Simulation time 2038076005 ps
CPU time 1.84 seconds
Started Jul 07 06:11:36 PM PDT 24
Finished Jul 07 06:11:39 PM PDT 24
Peak memory 204984 kb
Host smart-d34ba7b0-8df0-4fc9-955f-1ec44dcde10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781706293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.781706293
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.764466864
Short name T80
Test name
Test status
Simulation time 85515908 ps
CPU time 0.86 seconds
Started Jul 07 06:11:41 PM PDT 24
Finished Jul 07 06:11:42 PM PDT 24
Peak memory 205056 kb
Host smart-4e43725c-00f0-437c-8761-a5eb796e56c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764466864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.764466864
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2537810023
Short name T190
Test name
Test status
Simulation time 988318739 ps
CPU time 3.21 seconds
Started Jul 07 06:11:36 PM PDT 24
Finished Jul 07 06:11:40 PM PDT 24
Peak memory 205052 kb
Host smart-a6c6b238-7741-4e1b-86d2-82d485c498d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537810023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2537810023
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1828616616
Short name T189
Test name
Test status
Simulation time 244219638 ps
CPU time 0.99 seconds
Started Jul 07 06:11:40 PM PDT 24
Finished Jul 07 06:11:42 PM PDT 24
Peak memory 204948 kb
Host smart-92ca28bc-e9f0-4b66-8aa1-26bb207f2030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828616616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1828616616
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2532706241
Short name T39
Test name
Test status
Simulation time 814417800 ps
CPU time 1.28 seconds
Started Jul 07 06:11:37 PM PDT 24
Finished Jul 07 06:11:39 PM PDT 24
Peak memory 205060 kb
Host smart-e729c6ee-4ceb-4af7-a5a4-630bf44a51b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532706241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2532706241
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.447700747
Short name T51
Test name
Test status
Simulation time 765273766 ps
CPU time 1.12 seconds
Started Jul 07 06:11:39 PM PDT 24
Finished Jul 07 06:11:41 PM PDT 24
Peak memory 228624 kb
Host smart-24b2fa90-b776-4504-abdf-c6643bf4ac87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447700747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.447700747
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.773729306
Short name T134
Test name
Test status
Simulation time 813654822 ps
CPU time 1.86 seconds
Started Jul 07 06:11:34 PM PDT 24
Finished Jul 07 06:11:36 PM PDT 24
Peak memory 205048 kb
Host smart-e9bdd84d-be69-4625-97b8-3e7faf0077b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773729306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.773729306
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2674424301
Short name T14
Test name
Test status
Simulation time 4412331666 ps
CPU time 4.02 seconds
Started Jul 07 06:11:39 PM PDT 24
Finished Jul 07 06:11:44 PM PDT 24
Peak memory 213516 kb
Host smart-2c122b23-2158-4c73-bab7-3878e75ec951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674424301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2674424301
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1423578267
Short name T43
Test name
Test status
Simulation time 9602509725 ps
CPU time 22.61 seconds
Started Jul 07 06:11:36 PM PDT 24
Finished Jul 07 06:11:59 PM PDT 24
Peak memory 205344 kb
Host smart-23caab00-c108-42cb-b6da-d3719b9068ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423578267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1423578267
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1426213693
Short name T213
Test name
Test status
Simulation time 48979780 ps
CPU time 0.75 seconds
Started Jul 07 06:11:50 PM PDT 24
Finished Jul 07 06:11:51 PM PDT 24
Peak memory 205024 kb
Host smart-08bc3b60-33dc-4627-89bf-9f0270e28148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426213693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1426213693
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1881596002
Short name T71
Test name
Test status
Simulation time 1658797575 ps
CPU time 1.35 seconds
Started Jul 07 06:11:41 PM PDT 24
Finished Jul 07 06:11:43 PM PDT 24
Peak memory 213568 kb
Host smart-3c1cd1ad-5e1a-41fd-a158-337a058e3179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881596002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1881596002
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.646788168
Short name T236
Test name
Test status
Simulation time 1065567095 ps
CPU time 1.82 seconds
Started Jul 07 06:11:53 PM PDT 24
Finished Jul 07 06:11:55 PM PDT 24
Peak memory 213524 kb
Host smart-3d7024eb-71dd-4649-9488-c4bb8fffd1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646788168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.646788168
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1257253452
Short name T19
Test name
Test status
Simulation time 1425334949 ps
CPU time 1.1 seconds
Started Jul 07 06:11:46 PM PDT 24
Finished Jul 07 06:11:47 PM PDT 24
Peak memory 205100 kb
Host smart-a920a62b-8a8a-4b6c-87cd-8f8165736421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257253452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1257253452
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.4153557326
Short name T16
Test name
Test status
Simulation time 784736040 ps
CPU time 1.23 seconds
Started Jul 07 06:11:56 PM PDT 24
Finished Jul 07 06:11:57 PM PDT 24
Peak memory 205084 kb
Host smart-fff14c55-752b-4335-b5b3-8a1eb692c13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153557326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.4153557326
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2815709644
Short name T33
Test name
Test status
Simulation time 1505708499 ps
CPU time 1.25 seconds
Started Jul 07 06:11:43 PM PDT 24
Finished Jul 07 06:11:44 PM PDT 24
Peak memory 205020 kb
Host smart-ab648dea-8ee5-41cb-9b52-841b3da5bc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815709644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2815709644
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1415063962
Short name T129
Test name
Test status
Simulation time 411192230 ps
CPU time 1.58 seconds
Started Jul 07 06:11:40 PM PDT 24
Finished Jul 07 06:11:42 PM PDT 24
Peak memory 204996 kb
Host smart-247e6718-2124-40b9-a0bf-21856059ed6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415063962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1415063962
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2239166590
Short name T31
Test name
Test status
Simulation time 153322013 ps
CPU time 0.85 seconds
Started Jul 07 06:11:48 PM PDT 24
Finished Jul 07 06:11:49 PM PDT 24
Peak memory 205020 kb
Host smart-ee0729f9-c309-4a89-9172-a3cfd7fb7169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239166590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2239166590
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2249208212
Short name T260
Test name
Test status
Simulation time 5816217371 ps
CPU time 8.65 seconds
Started Jul 07 06:11:43 PM PDT 24
Finished Jul 07 06:11:52 PM PDT 24
Peak memory 213496 kb
Host smart-609a621c-2f72-41e2-ba48-041ec68059e2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249208212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2249208212
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1400867404
Short name T188
Test name
Test status
Simulation time 383168312 ps
CPU time 1.24 seconds
Started Jul 07 06:11:54 PM PDT 24
Finished Jul 07 06:11:55 PM PDT 24
Peak memory 205088 kb
Host smart-537e9ffd-8427-43be-951e-5a8aa873c62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400867404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1400867404
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.210044509
Short name T7
Test name
Test status
Simulation time 300821592 ps
CPU time 1.5 seconds
Started Jul 07 06:11:42 PM PDT 24
Finished Jul 07 06:11:44 PM PDT 24
Peak memory 205080 kb
Host smart-1eab91cc-6959-400b-8adc-e641309ad460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210044509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.210044509
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3213551444
Short name T262
Test name
Test status
Simulation time 899442809 ps
CPU time 2.5 seconds
Started Jul 07 06:11:43 PM PDT 24
Finished Jul 07 06:11:46 PM PDT 24
Peak memory 205000 kb
Host smart-237bc2a5-c785-4ed3-8476-18edebe7ad41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213551444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3213551444
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.425033690
Short name T270
Test name
Test status
Simulation time 3605762544 ps
CPU time 2.9 seconds
Started Jul 07 06:11:54 PM PDT 24
Finished Jul 07 06:11:58 PM PDT 24
Peak memory 205144 kb
Host smart-7f656e24-8a41-454d-a4ba-98882007818c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425033690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.425033690
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2111738247
Short name T200
Test name
Test status
Simulation time 808623288 ps
CPU time 1.17 seconds
Started Jul 07 06:11:43 PM PDT 24
Finished Jul 07 06:11:45 PM PDT 24
Peak memory 205340 kb
Host smart-edc81397-ce79-447c-80ab-8849b6c122e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111738247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2111738247
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3091569541
Short name T191
Test name
Test status
Simulation time 201568339 ps
CPU time 0.78 seconds
Started Jul 07 06:11:42 PM PDT 24
Finished Jul 07 06:11:43 PM PDT 24
Peak memory 205072 kb
Host smart-4986abbb-7146-47d5-a649-ae5e6ffdadf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091569541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3091569541
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.636400670
Short name T23
Test name
Test status
Simulation time 725353308 ps
CPU time 2.4 seconds
Started Jul 07 06:11:47 PM PDT 24
Finished Jul 07 06:11:49 PM PDT 24
Peak memory 205116 kb
Host smart-ace6f0be-cca2-4b17-a014-af54a672df16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636400670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.636400670
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2639414648
Short name T34
Test name
Test status
Simulation time 40149675 ps
CPU time 0.87 seconds
Started Jul 07 06:11:50 PM PDT 24
Finished Jul 07 06:11:51 PM PDT 24
Peak memory 213316 kb
Host smart-69ca9a80-e401-4fae-ae58-670985a7d271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639414648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2639414648
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3528801847
Short name T76
Test name
Test status
Simulation time 3190870816 ps
CPU time 2.48 seconds
Started Jul 07 06:11:40 PM PDT 24
Finished Jul 07 06:11:43 PM PDT 24
Peak memory 205112 kb
Host smart-96ae0e8f-f8ff-4ecc-943b-719bac6c18b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528801847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3528801847
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.4288066522
Short name T273
Test name
Test status
Simulation time 92030413 ps
CPU time 0.72 seconds
Started Jul 07 06:12:08 PM PDT 24
Finished Jul 07 06:12:09 PM PDT 24
Peak memory 205080 kb
Host smart-a5e10221-0b5b-4c51-8f83-81f92676d73a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288066522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.4288066522
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3863934955
Short name T152
Test name
Test status
Simulation time 8890897012 ps
CPU time 26 seconds
Started Jul 07 06:12:10 PM PDT 24
Finished Jul 07 06:12:37 PM PDT 24
Peak memory 213628 kb
Host smart-239f0783-2df2-4556-af99-243191e155ab
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3863934955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3863934955
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1702446193
Short name T271
Test name
Test status
Simulation time 1818565218 ps
CPU time 3.29 seconds
Started Jul 07 06:12:05 PM PDT 24
Finished Jul 07 06:12:08 PM PDT 24
Peak memory 213556 kb
Host smart-b822080e-ef71-490e-be75-c7884c71fadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702446193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1702446193
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.429488177
Short name T218
Test name
Test status
Simulation time 148926762 ps
CPU time 0.86 seconds
Started Jul 07 06:12:11 PM PDT 24
Finished Jul 07 06:12:13 PM PDT 24
Peak memory 205096 kb
Host smart-470caade-7f6f-4ca1-a6ca-d2e589a3319f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429488177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.429488177
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.4237524245
Short name T199
Test name
Test status
Simulation time 9903826420 ps
CPU time 12.61 seconds
Started Jul 07 06:12:11 PM PDT 24
Finished Jul 07 06:12:24 PM PDT 24
Peak memory 213568 kb
Host smart-73812a52-5854-41a3-89c1-880029636795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237524245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.4237524245
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.319067731
Short name T239
Test name
Test status
Simulation time 2667795396 ps
CPU time 2.78 seconds
Started Jul 07 06:12:15 PM PDT 24
Finished Jul 07 06:12:19 PM PDT 24
Peak memory 213640 kb
Host smart-5c0695bc-7815-4b6b-8429-50c3569cf222
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=319067731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.319067731
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1211523771
Short name T266
Test name
Test status
Simulation time 3399411513 ps
CPU time 8.96 seconds
Started Jul 07 06:12:06 PM PDT 24
Finished Jul 07 06:12:15 PM PDT 24
Peak memory 205376 kb
Host smart-2f49ce95-d082-4728-8d4d-7227fe400565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211523771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1211523771
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.1712970473
Short name T6
Test name
Test status
Simulation time 7362151569 ps
CPU time 4.69 seconds
Started Jul 07 06:12:09 PM PDT 24
Finished Jul 07 06:12:14 PM PDT 24
Peak memory 205296 kb
Host smart-6535e6b3-9c23-427f-9d9a-ec89d04cf760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712970473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.1712970473
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2235434586
Short name T210
Test name
Test status
Simulation time 76608492 ps
CPU time 0.67 seconds
Started Jul 07 06:12:07 PM PDT 24
Finished Jul 07 06:12:07 PM PDT 24
Peak memory 205072 kb
Host smart-33530bb3-fcab-4aa6-b680-b8b7623a2f1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235434586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2235434586
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3231662647
Short name T155
Test name
Test status
Simulation time 11915983974 ps
CPU time 4.88 seconds
Started Jul 07 06:12:15 PM PDT 24
Finished Jul 07 06:12:20 PM PDT 24
Peak memory 213640 kb
Host smart-dc9cce8b-ae28-4016-ba92-a67980312192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231662647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3231662647
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.231868491
Short name T274
Test name
Test status
Simulation time 19159740634 ps
CPU time 31.18 seconds
Started Jul 07 06:12:06 PM PDT 24
Finished Jul 07 06:12:37 PM PDT 24
Peak memory 213488 kb
Host smart-5209b310-a31d-4d80-b53a-c90b5c190f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231868491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.231868491
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3280363434
Short name T234
Test name
Test status
Simulation time 1909002112 ps
CPU time 2.79 seconds
Started Jul 07 06:12:15 PM PDT 24
Finished Jul 07 06:12:18 PM PDT 24
Peak memory 213508 kb
Host smart-3eb48eb5-2e53-4a24-b3c8-95d4c5ad878c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3280363434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3280363434
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.711782814
Short name T246
Test name
Test status
Simulation time 3295403540 ps
CPU time 3.04 seconds
Started Jul 07 06:12:06 PM PDT 24
Finished Jul 07 06:12:09 PM PDT 24
Peak memory 213612 kb
Host smart-bf082e4e-8813-40bc-a48e-39e0c16e637f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711782814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.711782814
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2633140395
Short name T221
Test name
Test status
Simulation time 45713871 ps
CPU time 0.78 seconds
Started Jul 07 06:12:08 PM PDT 24
Finished Jul 07 06:12:09 PM PDT 24
Peak memory 205060 kb
Host smart-c3511de5-ca94-4087-9fd2-c73d3192ce00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633140395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2633140395
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3755595470
Short name T240
Test name
Test status
Simulation time 2424620612 ps
CPU time 1.35 seconds
Started Jul 07 06:12:10 PM PDT 24
Finished Jul 07 06:12:12 PM PDT 24
Peak memory 205432 kb
Host smart-f19ddf59-b6f5-443d-a036-21b930600bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755595470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3755595470
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2008637240
Short name T256
Test name
Test status
Simulation time 3287248308 ps
CPU time 6.66 seconds
Started Jul 07 06:12:09 PM PDT 24
Finished Jul 07 06:12:16 PM PDT 24
Peak memory 205400 kb
Host smart-55720f52-661f-49b2-aa69-09b50888cd19
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2008637240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2008637240
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3327602522
Short name T79
Test name
Test status
Simulation time 4443519220 ps
CPU time 5.96 seconds
Started Jul 07 06:12:05 PM PDT 24
Finished Jul 07 06:12:11 PM PDT 24
Peak memory 205412 kb
Host smart-c5337f8e-af28-49a0-9fa3-7df87c23b15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327602522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3327602522
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.1577032917
Short name T135
Test name
Test status
Simulation time 4052753348 ps
CPU time 6.26 seconds
Started Jul 07 06:12:11 PM PDT 24
Finished Jul 07 06:12:17 PM PDT 24
Peak memory 213520 kb
Host smart-c6a5ef0a-6093-40c8-abb0-cc4a42ad8932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577032917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1577032917
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1542309491
Short name T211
Test name
Test status
Simulation time 162025404 ps
CPU time 0.78 seconds
Started Jul 07 06:12:11 PM PDT 24
Finished Jul 07 06:12:13 PM PDT 24
Peak memory 205120 kb
Host smart-4b9cf68a-fcc1-4e1c-92d2-0abd7a75601e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542309491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1542309491
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3730733008
Short name T224
Test name
Test status
Simulation time 4842274701 ps
CPU time 6.45 seconds
Started Jul 07 06:12:14 PM PDT 24
Finished Jul 07 06:12:20 PM PDT 24
Peak memory 213680 kb
Host smart-93d9bba1-081a-461e-ab18-70f7267f11e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730733008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3730733008
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1631039851
Short name T248
Test name
Test status
Simulation time 3037688957 ps
CPU time 4.89 seconds
Started Jul 07 06:12:09 PM PDT 24
Finished Jul 07 06:12:15 PM PDT 24
Peak memory 205408 kb
Host smart-2b60c483-7fb3-488a-8ca5-dc79a74484a0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1631039851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1631039851
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2054504704
Short name T247
Test name
Test status
Simulation time 2127544734 ps
CPU time 2.9 seconds
Started Jul 07 06:12:11 PM PDT 24
Finished Jul 07 06:12:14 PM PDT 24
Peak memory 205332 kb
Host smart-c55c6f4d-338f-4fa1-bc76-f4339546977b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054504704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2054504704
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.1271086333
Short name T13
Test name
Test status
Simulation time 12837246435 ps
CPU time 22.16 seconds
Started Jul 07 06:12:12 PM PDT 24
Finished Jul 07 06:12:34 PM PDT 24
Peak memory 205364 kb
Host smart-c78942c9-afc2-47a4-a123-0144614aeafc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271086333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1271086333
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3166681784
Short name T215
Test name
Test status
Simulation time 108061175 ps
CPU time 0.72 seconds
Started Jul 07 06:12:09 PM PDT 24
Finished Jul 07 06:12:11 PM PDT 24
Peak memory 205100 kb
Host smart-6c20f650-7f26-47f7-a551-e317309bae6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166681784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3166681784
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3822107593
Short name T77
Test name
Test status
Simulation time 14218144128 ps
CPU time 20.01 seconds
Started Jul 07 06:12:12 PM PDT 24
Finished Jul 07 06:12:33 PM PDT 24
Peak memory 213588 kb
Host smart-51303a96-4a15-42ff-b4ab-8a6817641539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822107593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3822107593
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1323911847
Short name T257
Test name
Test status
Simulation time 6649754573 ps
CPU time 5.49 seconds
Started Jul 07 06:12:09 PM PDT 24
Finished Jul 07 06:12:14 PM PDT 24
Peak memory 213624 kb
Host smart-874dd4a1-38c8-486e-bcc6-5ebe36d5e642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323911847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1323911847
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.4285509756
Short name T154
Test name
Test status
Simulation time 1459290068 ps
CPU time 4.83 seconds
Started Jul 07 06:12:15 PM PDT 24
Finished Jul 07 06:12:20 PM PDT 24
Peak memory 213584 kb
Host smart-2994b3ec-c663-47e3-b716-a80ecf21302d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285509756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.4285509756
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.394906900
Short name T173
Test name
Test status
Simulation time 4658908913 ps
CPU time 13.5 seconds
Started Jul 07 06:12:14 PM PDT 24
Finished Jul 07 06:12:28 PM PDT 24
Peak memory 205452 kb
Host smart-9714dda4-f9ed-4f53-86b5-bfa5d513aceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394906900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.394906900
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2489338961
Short name T195
Test name
Test status
Simulation time 130683613 ps
CPU time 0.85 seconds
Started Jul 07 06:12:08 PM PDT 24
Finished Jul 07 06:12:10 PM PDT 24
Peak memory 205084 kb
Host smart-d47a8ba8-932f-4bca-885a-2bfdbe8300f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489338961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2489338961
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1515015674
Short name T151
Test name
Test status
Simulation time 3332419451 ps
CPU time 1.6 seconds
Started Jul 07 06:12:09 PM PDT 24
Finished Jul 07 06:12:11 PM PDT 24
Peak memory 205344 kb
Host smart-664e2dfe-e6bb-42dc-afe7-16239a93f4cb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515015674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1515015674
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.837015523
Short name T168
Test name
Test status
Simulation time 881614378 ps
CPU time 1.23 seconds
Started Jul 07 06:12:15 PM PDT 24
Finished Jul 07 06:12:16 PM PDT 24
Peak memory 205192 kb
Host smart-92bb27bc-6a83-48ad-a04a-37019c55ec59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837015523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.837015523
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.537780342
Short name T75
Test name
Test status
Simulation time 2493856743 ps
CPU time 5.1 seconds
Started Jul 07 06:12:15 PM PDT 24
Finished Jul 07 06:12:20 PM PDT 24
Peak memory 205184 kb
Host smart-55f7aba9-a27b-4959-8d97-cca598fd0e1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537780342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.537780342
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.4163103494
Short name T205
Test name
Test status
Simulation time 71893344 ps
CPU time 0.71 seconds
Started Jul 07 06:12:13 PM PDT 24
Finished Jul 07 06:12:14 PM PDT 24
Peak memory 205108 kb
Host smart-cde8b18f-e6bd-4400-a20f-f63c2d671fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163103494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.4163103494
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2184785276
Short name T193
Test name
Test status
Simulation time 5706069379 ps
CPU time 6.18 seconds
Started Jul 07 06:12:14 PM PDT 24
Finished Jul 07 06:12:21 PM PDT 24
Peak memory 213616 kb
Host smart-df27c2ad-17a3-4958-80c8-ab8db1910ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184785276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2184785276
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.6730805
Short name T201
Test name
Test status
Simulation time 1043324119 ps
CPU time 2.86 seconds
Started Jul 07 06:12:12 PM PDT 24
Finished Jul 07 06:12:15 PM PDT 24
Peak memory 205356 kb
Host smart-aa4f8a6d-3078-44e5-8386-5c738d2e7a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6730805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.6730805
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3323071806
Short name T253
Test name
Test status
Simulation time 5521687614 ps
CPU time 8.24 seconds
Started Jul 07 06:12:14 PM PDT 24
Finished Jul 07 06:12:22 PM PDT 24
Peak memory 213604 kb
Host smart-a5d1f283-d7d9-4332-a4ac-6d19e1a3ad2d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323071806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3323071806
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1676303624
Short name T219
Test name
Test status
Simulation time 8528588618 ps
CPU time 8.38 seconds
Started Jul 07 06:12:14 PM PDT 24
Finished Jul 07 06:12:23 PM PDT 24
Peak memory 213612 kb
Host smart-7052b290-d8c8-422e-950f-dfaed9e77c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676303624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1676303624
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1654766551
Short name T54
Test name
Test status
Simulation time 3129944076 ps
CPU time 5.05 seconds
Started Jul 07 06:12:18 PM PDT 24
Finished Jul 07 06:12:23 PM PDT 24
Peak memory 213472 kb
Host smart-f84d90ec-2fa5-4ca6-8fda-84fbfee42c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654766551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1654766551
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.560116722
Short name T55
Test name
Test status
Simulation time 2424508240 ps
CPU time 7.33 seconds
Started Jul 07 06:12:15 PM PDT 24
Finished Jul 07 06:12:23 PM PDT 24
Peak memory 213608 kb
Host smart-2998a1b9-54db-4e68-84f3-f246fe1087dc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=560116722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.560116722
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1084692837
Short name T40
Test name
Test status
Simulation time 1948113132 ps
CPU time 3.58 seconds
Started Jul 07 06:12:16 PM PDT 24
Finished Jul 07 06:12:20 PM PDT 24
Peak memory 213592 kb
Host smart-2ce964bc-841c-4c1e-b640-352be92d4c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084692837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1084692837
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3030105392
Short name T254
Test name
Test status
Simulation time 101576672 ps
CPU time 0.8 seconds
Started Jul 07 06:12:14 PM PDT 24
Finished Jul 07 06:12:15 PM PDT 24
Peak memory 205120 kb
Host smart-8971d0e7-da70-4da2-a300-319412af07cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030105392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3030105392
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.217807559
Short name T29
Test name
Test status
Simulation time 12844418289 ps
CPU time 30.32 seconds
Started Jul 07 06:12:18 PM PDT 24
Finished Jul 07 06:12:49 PM PDT 24
Peak memory 213864 kb
Host smart-f6be8f9c-7e5d-4638-8036-949dc872a1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217807559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.217807559
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3012697559
Short name T235
Test name
Test status
Simulation time 2497337987 ps
CPU time 5.43 seconds
Started Jul 07 06:12:16 PM PDT 24
Finished Jul 07 06:12:22 PM PDT 24
Peak memory 213500 kb
Host smart-14ae98cf-27a8-45d3-9ca7-d8dc3c147861
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3012697559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3012697559
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.3865572412
Short name T242
Test name
Test status
Simulation time 3019896176 ps
CPU time 5 seconds
Started Jul 07 06:12:18 PM PDT 24
Finished Jul 07 06:12:23 PM PDT 24
Peak memory 213652 kb
Host smart-e5aa8134-cb14-42d3-a546-94dfd3830efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865572412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3865572412
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1409222160
Short name T252
Test name
Test status
Simulation time 43870615 ps
CPU time 0.76 seconds
Started Jul 07 06:11:46 PM PDT 24
Finished Jul 07 06:11:47 PM PDT 24
Peak memory 205076 kb
Host smart-3594b2cb-284c-4cc4-9d3e-e5cccff8e7d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409222160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1409222160
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3340555200
Short name T220
Test name
Test status
Simulation time 14406339895 ps
CPU time 14.48 seconds
Started Jul 07 06:11:55 PM PDT 24
Finished Jul 07 06:12:10 PM PDT 24
Peak memory 213656 kb
Host smart-ec6bea56-bc9e-4d47-a3a9-65c03ea9dc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340555200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3340555200
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.2802135165
Short name T204
Test name
Test status
Simulation time 4338054994 ps
CPU time 3.96 seconds
Started Jul 07 06:11:50 PM PDT 24
Finished Jul 07 06:11:54 PM PDT 24
Peak memory 213620 kb
Host smart-d0ecc4d8-29f1-4e94-b67e-bf586bb513cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802135165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2802135165
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2510484498
Short name T275
Test name
Test status
Simulation time 986199395 ps
CPU time 3.83 seconds
Started Jul 07 06:11:51 PM PDT 24
Finished Jul 07 06:11:55 PM PDT 24
Peak memory 205376 kb
Host smart-8640cf73-11c5-46b3-8812-bf3a2f962707
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2510484498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2510484498
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1879201355
Short name T229
Test name
Test status
Simulation time 237727794 ps
CPU time 1.13 seconds
Started Jul 07 06:11:51 PM PDT 24
Finished Jul 07 06:11:52 PM PDT 24
Peak memory 205056 kb
Host smart-d501f8c4-6ea2-48e6-bed5-6df0ad1cabb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879201355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1879201355
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.3518379309
Short name T244
Test name
Test status
Simulation time 1210758965 ps
CPU time 2.87 seconds
Started Jul 07 06:11:51 PM PDT 24
Finished Jul 07 06:11:54 PM PDT 24
Peak memory 205372 kb
Host smart-1b33476e-9256-4207-8629-add7504d590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518379309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.3518379309
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.245726401
Short name T53
Test name
Test status
Simulation time 880257139 ps
CPU time 2.43 seconds
Started Jul 07 06:11:49 PM PDT 24
Finished Jul 07 06:11:52 PM PDT 24
Peak memory 229424 kb
Host smart-88360073-604d-44e7-bec3-4c081ff5fbcf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245726401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.245726401
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.576258568
Short name T232
Test name
Test status
Simulation time 180466333 ps
CPU time 0.82 seconds
Started Jul 07 06:12:16 PM PDT 24
Finished Jul 07 06:12:17 PM PDT 24
Peak memory 205072 kb
Host smart-ffd7ca06-4bfd-4b08-90cc-fedf0a264562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576258568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.576258568
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.1878686588
Short name T70
Test name
Test status
Simulation time 6202992700 ps
CPU time 17.06 seconds
Started Jul 07 06:12:19 PM PDT 24
Finished Jul 07 06:12:36 PM PDT 24
Peak memory 205292 kb
Host smart-2b401930-0ad2-4228-a97b-a1775db240ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878686588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.1878686588
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2854332117
Short name T72
Test name
Test status
Simulation time 211793808 ps
CPU time 0.71 seconds
Started Jul 07 06:12:13 PM PDT 24
Finished Jul 07 06:12:14 PM PDT 24
Peak memory 205088 kb
Host smart-7d7f09b7-e483-4409-91d6-907cfac0405e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854332117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2854332117
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2602514721
Short name T230
Test name
Test status
Simulation time 165378908 ps
CPU time 0.75 seconds
Started Jul 07 06:12:18 PM PDT 24
Finished Jul 07 06:12:19 PM PDT 24
Peak memory 205072 kb
Host smart-61e00a57-518e-40c3-a210-50adcb8334e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602514721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2602514721
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.553008748
Short name T42
Test name
Test status
Simulation time 7773644159 ps
CPU time 11.7 seconds
Started Jul 07 06:12:20 PM PDT 24
Finished Jul 07 06:12:32 PM PDT 24
Peak memory 213508 kb
Host smart-3bddfdee-0772-42ad-90d6-16e1f4916a97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553008748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.553008748
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.21600681
Short name T237
Test name
Test status
Simulation time 106280224 ps
CPU time 0.71 seconds
Started Jul 07 06:12:25 PM PDT 24
Finished Jul 07 06:12:26 PM PDT 24
Peak memory 204944 kb
Host smart-7f8c909b-ef77-4775-9906-ade1686fe58b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21600681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.21600681
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.1147744085
Short name T145
Test name
Test status
Simulation time 12612580097 ps
CPU time 20.1 seconds
Started Jul 07 06:12:23 PM PDT 24
Finished Jul 07 06:12:43 PM PDT 24
Peak memory 213512 kb
Host smart-fe177fe0-bcd8-4238-9341-d8b8e40f0905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147744085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1147744085
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.194030778
Short name T222
Test name
Test status
Simulation time 84749270 ps
CPU time 0.76 seconds
Started Jul 07 06:12:20 PM PDT 24
Finished Jul 07 06:12:21 PM PDT 24
Peak memory 205056 kb
Host smart-3233457f-4e53-4e6b-a90b-9b3eaaaed6af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194030778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.194030778
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.41064642
Short name T245
Test name
Test status
Simulation time 68644845 ps
CPU time 0.79 seconds
Started Jul 07 06:12:19 PM PDT 24
Finished Jul 07 06:12:20 PM PDT 24
Peak memory 205100 kb
Host smart-1416d483-fc80-43f4-81f7-33bfab72a9f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41064642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.41064642
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1420749114
Short name T207
Test name
Test status
Simulation time 43573197 ps
CPU time 0.76 seconds
Started Jul 07 06:12:21 PM PDT 24
Finished Jul 07 06:12:21 PM PDT 24
Peak memory 205036 kb
Host smart-bb94bfb2-2dd3-468a-864c-95a897c408c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420749114 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1420749114
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.356661141
Short name T8
Test name
Test status
Simulation time 7732323956 ps
CPU time 3.82 seconds
Started Jul 07 06:12:21 PM PDT 24
Finished Jul 07 06:12:25 PM PDT 24
Peak memory 213500 kb
Host smart-dc2bd76f-b32c-4af1-b9f9-5994c3066e80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356661141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.356661141
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3889079917
Short name T268
Test name
Test status
Simulation time 50181548 ps
CPU time 0.73 seconds
Started Jul 07 06:12:22 PM PDT 24
Finished Jul 07 06:12:23 PM PDT 24
Peak memory 205080 kb
Host smart-2d75a9c2-ad24-4eae-89b3-23a64c5c09d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889079917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3889079917
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2037932221
Short name T227
Test name
Test status
Simulation time 28421640 ps
CPU time 0.78 seconds
Started Jul 07 06:12:21 PM PDT 24
Finished Jul 07 06:12:22 PM PDT 24
Peak memory 205068 kb
Host smart-c51f10a4-b746-41fa-bb3a-ad225caaba8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037932221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2037932221
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2517634039
Short name T203
Test name
Test status
Simulation time 178727949 ps
CPU time 0.82 seconds
Started Jul 07 06:12:21 PM PDT 24
Finished Jul 07 06:12:22 PM PDT 24
Peak memory 205072 kb
Host smart-a8c7931e-fc44-497c-8995-f14528aa1854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517634039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2517634039
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2268280148
Short name T197
Test name
Test status
Simulation time 41035119 ps
CPU time 0.78 seconds
Started Jul 07 06:11:54 PM PDT 24
Finished Jul 07 06:11:56 PM PDT 24
Peak memory 205028 kb
Host smart-ce9643c4-19f7-4e22-b363-a870dbf58d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268280148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2268280148
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2902122824
Short name T223
Test name
Test status
Simulation time 15458418850 ps
CPU time 37.97 seconds
Started Jul 07 06:11:51 PM PDT 24
Finished Jul 07 06:12:30 PM PDT 24
Peak memory 213612 kb
Host smart-1f8a04d4-ca8b-47f3-b9a3-c029cdaf2383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902122824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2902122824
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1733020634
Short name T226
Test name
Test status
Simulation time 2613012723 ps
CPU time 8.8 seconds
Started Jul 07 06:11:57 PM PDT 24
Finished Jul 07 06:12:06 PM PDT 24
Peak memory 213452 kb
Host smart-ba113e88-89ef-446e-aba9-c0b93c6b0216
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1733020634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1733020634
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1185302093
Short name T74
Test name
Test status
Simulation time 416387808 ps
CPU time 1.86 seconds
Started Jul 07 06:11:50 PM PDT 24
Finished Jul 07 06:11:52 PM PDT 24
Peak memory 205056 kb
Host smart-baaff0bc-0715-4586-b93f-1f50a62250c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185302093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1185302093
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.4240085766
Short name T84
Test name
Test status
Simulation time 2925647845 ps
CPU time 5.17 seconds
Started Jul 07 06:11:52 PM PDT 24
Finished Jul 07 06:11:58 PM PDT 24
Peak memory 205692 kb
Host smart-3a172148-969d-447e-ac53-1f39bc4406a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240085766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.4240085766
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2469804514
Short name T66
Test name
Test status
Simulation time 435428734 ps
CPU time 1.12 seconds
Started Jul 07 06:11:53 PM PDT 24
Finished Jul 07 06:11:55 PM PDT 24
Peak memory 229580 kb
Host smart-e090b7ee-6e68-43a2-bcb2-1b345cef66b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469804514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2469804514
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.471935952
Short name T49
Test name
Test status
Simulation time 38035871 ps
CPU time 0.76 seconds
Started Jul 07 06:12:21 PM PDT 24
Finished Jul 07 06:12:22 PM PDT 24
Peak memory 205032 kb
Host smart-c067e0c7-73bd-4780-8ae1-6112e00064bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471935952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.471935952
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3275393920
Short name T20
Test name
Test status
Simulation time 7945071874 ps
CPU time 20.47 seconds
Started Jul 07 06:12:19 PM PDT 24
Finished Jul 07 06:12:40 PM PDT 24
Peak memory 213472 kb
Host smart-fc68cca9-d079-423b-bec2-2ea8821a2caa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275393920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3275393920
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2542767839
Short name T241
Test name
Test status
Simulation time 136274491 ps
CPU time 0.98 seconds
Started Jul 07 06:12:20 PM PDT 24
Finished Jul 07 06:12:21 PM PDT 24
Peak memory 205120 kb
Host smart-a099a36b-5865-451a-a336-111343807e7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542767839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2542767839
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1121329927
Short name T21
Test name
Test status
Simulation time 5186789422 ps
CPU time 3.35 seconds
Started Jul 07 06:12:19 PM PDT 24
Finished Jul 07 06:12:22 PM PDT 24
Peak memory 213520 kb
Host smart-f9a3391f-a462-4adf-bf8d-5805c5ef64e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121329927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1121329927
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1717929874
Short name T83
Test name
Test status
Simulation time 168636117 ps
CPU time 0.75 seconds
Started Jul 07 06:12:26 PM PDT 24
Finished Jul 07 06:12:27 PM PDT 24
Peak memory 205080 kb
Host smart-5491d331-73d2-4673-b225-0d9576e7897d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717929874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1717929874
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.3795613860
Short name T140
Test name
Test status
Simulation time 5906009199 ps
CPU time 6.97 seconds
Started Jul 07 06:12:22 PM PDT 24
Finished Jul 07 06:12:29 PM PDT 24
Peak memory 213556 kb
Host smart-55682220-0ae0-40a2-909a-3010beef27d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795613860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3795613860
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1195013797
Short name T69
Test name
Test status
Simulation time 197887226 ps
CPU time 0.77 seconds
Started Jul 07 06:12:31 PM PDT 24
Finished Jul 07 06:12:32 PM PDT 24
Peak memory 205080 kb
Host smart-d14d4217-b580-418b-b2d7-b117a97dd89f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195013797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1195013797
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2933719952
Short name T194
Test name
Test status
Simulation time 130839662 ps
CPU time 0.9 seconds
Started Jul 07 06:12:24 PM PDT 24
Finished Jul 07 06:12:25 PM PDT 24
Peak memory 205108 kb
Host smart-2f1c49da-8e7d-43a9-bcf5-e080c56578c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933719952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2933719952
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2998290344
Short name T81
Test name
Test status
Simulation time 6078985050 ps
CPU time 9.56 seconds
Started Jul 07 06:12:26 PM PDT 24
Finished Jul 07 06:12:36 PM PDT 24
Peak memory 205440 kb
Host smart-633503eb-8a72-43ef-b04f-19341ce753f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998290344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2998290344
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3281426457
Short name T78
Test name
Test status
Simulation time 104310285 ps
CPU time 0.74 seconds
Started Jul 07 06:12:26 PM PDT 24
Finished Jul 07 06:12:27 PM PDT 24
Peak memory 205084 kb
Host smart-f6a098a1-be1d-43ff-b9d6-3fb79555c0c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281426457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3281426457
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.14676976
Short name T208
Test name
Test status
Simulation time 55510289 ps
CPU time 0.87 seconds
Started Jul 07 06:12:24 PM PDT 24
Finished Jul 07 06:12:25 PM PDT 24
Peak memory 205108 kb
Host smart-a9e9125a-dacc-4d9d-85a5-0a66dd974afb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14676976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.14676976
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.4233117703
Short name T144
Test name
Test status
Simulation time 7276617953 ps
CPU time 20.61 seconds
Started Jul 07 06:12:24 PM PDT 24
Finished Jul 07 06:12:44 PM PDT 24
Peak memory 213480 kb
Host smart-f2bf3174-b7c3-4d49-a6a4-fd2af0b8b9f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233117703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.4233117703
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3877537070
Short name T50
Test name
Test status
Simulation time 82258647 ps
CPU time 0.87 seconds
Started Jul 07 06:12:29 PM PDT 24
Finished Jul 07 06:12:30 PM PDT 24
Peak memory 205092 kb
Host smart-55f9d62c-8386-448f-a5ec-3bc59c334a56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877537070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3877537070
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.380815869
Short name T217
Test name
Test status
Simulation time 197516955 ps
CPU time 0.81 seconds
Started Jul 07 06:12:24 PM PDT 24
Finished Jul 07 06:12:25 PM PDT 24
Peak memory 205104 kb
Host smart-deba01c9-f81a-4bfb-bdea-004ab912b686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380815869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.380815869
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.988547358
Short name T68
Test name
Test status
Simulation time 55473561 ps
CPU time 0.82 seconds
Started Jul 07 06:12:27 PM PDT 24
Finished Jul 07 06:12:28 PM PDT 24
Peak memory 205068 kb
Host smart-80ec5529-a06e-453b-a717-f0e435e3fda0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988547358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.988547358
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3375959397
Short name T127
Test name
Test status
Simulation time 118906262 ps
CPU time 0.82 seconds
Started Jul 07 06:11:54 PM PDT 24
Finished Jul 07 06:11:55 PM PDT 24
Peak memory 205068 kb
Host smart-b99a049d-31a2-4c1d-aa45-e47269b06849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375959397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3375959397
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2140207965
Short name T269
Test name
Test status
Simulation time 7631843905 ps
CPU time 5.65 seconds
Started Jul 07 06:11:51 PM PDT 24
Finished Jul 07 06:11:57 PM PDT 24
Peak memory 213552 kb
Host smart-00b9d9f9-05d6-49b3-a7ee-16714760eea7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2140207965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2140207965
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.4128042740
Short name T258
Test name
Test status
Simulation time 107945439 ps
CPU time 0.86 seconds
Started Jul 07 06:11:57 PM PDT 24
Finished Jul 07 06:11:58 PM PDT 24
Peak memory 205060 kb
Host smart-a09bbd2b-5560-47f7-8edb-0a71c4df9c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128042740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.4128042740
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3272473950
Short name T169
Test name
Test status
Simulation time 1781255807 ps
CPU time 5.75 seconds
Started Jul 07 06:11:56 PM PDT 24
Finished Jul 07 06:12:02 PM PDT 24
Peak memory 205312 kb
Host smart-8c7a54f6-b118-45c7-a581-b63daffda70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272473950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3272473950
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3024836849
Short name T52
Test name
Test status
Simulation time 1235117585 ps
CPU time 4.28 seconds
Started Jul 07 06:11:54 PM PDT 24
Finished Jul 07 06:11:59 PM PDT 24
Peak memory 229136 kb
Host smart-fe5eec64-b8a6-4051-86c6-5d0a68b4e06d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024836849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3024836849
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.340292719
Short name T82
Test name
Test status
Simulation time 51469007 ps
CPU time 0.76 seconds
Started Jul 07 06:12:28 PM PDT 24
Finished Jul 07 06:12:29 PM PDT 24
Peak memory 204940 kb
Host smart-6d6dc03a-4037-4764-a717-cc450b06989b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340292719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.340292719
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.381171217
Short name T259
Test name
Test status
Simulation time 179980933 ps
CPU time 0.74 seconds
Started Jul 07 06:12:30 PM PDT 24
Finished Jul 07 06:12:31 PM PDT 24
Peak memory 204988 kb
Host smart-b9a52f99-95b6-4157-8158-1ad3579e614f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381171217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.381171217
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.3502574032
Short name T139
Test name
Test status
Simulation time 10185553889 ps
CPU time 14.42 seconds
Started Jul 07 06:12:25 PM PDT 24
Finished Jul 07 06:12:40 PM PDT 24
Peak memory 213496 kb
Host smart-81dab452-f322-41d4-ba18-1c979f366840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502574032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3502574032
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.2278306573
Short name T48
Test name
Test status
Simulation time 144832807 ps
CPU time 1 seconds
Started Jul 07 06:12:31 PM PDT 24
Finished Jul 07 06:12:32 PM PDT 24
Peak memory 205080 kb
Host smart-f740701b-9ef9-42d1-bc13-f8fc0487e2fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278306573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2278306573
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.225273599
Short name T233
Test name
Test status
Simulation time 87385771 ps
CPU time 0.75 seconds
Started Jul 07 06:12:27 PM PDT 24
Finished Jul 07 06:12:28 PM PDT 24
Peak memory 205104 kb
Host smart-dc748ce6-108e-4a28-95bc-c1fd72666ff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225273599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.225273599
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.618434425
Short name T196
Test name
Test status
Simulation time 78167922 ps
CPU time 0.86 seconds
Started Jul 07 06:12:29 PM PDT 24
Finished Jul 07 06:12:30 PM PDT 24
Peak memory 205076 kb
Host smart-f86160e8-6ffd-4a43-aca7-bce9935f2e16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618434425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.618434425
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.1873095210
Short name T95
Test name
Test status
Simulation time 10146848658 ps
CPU time 20.78 seconds
Started Jul 07 06:12:32 PM PDT 24
Finished Jul 07 06:12:54 PM PDT 24
Peak memory 213536 kb
Host smart-f059bea9-98a0-425c-b8b3-3aed98ebc6cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873095210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.1873095210
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3335542958
Short name T198
Test name
Test status
Simulation time 57744495 ps
CPU time 0.87 seconds
Started Jul 07 06:12:30 PM PDT 24
Finished Jul 07 06:12:31 PM PDT 24
Peak memory 205012 kb
Host smart-7085ac34-f951-4752-846a-24b518e4d77a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335542958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3335542958
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3161289569
Short name T264
Test name
Test status
Simulation time 41127018 ps
CPU time 0.78 seconds
Started Jul 07 06:12:29 PM PDT 24
Finished Jul 07 06:12:30 PM PDT 24
Peak memory 205072 kb
Host smart-ac69fa6c-9ca8-485a-9453-e554cd5c7f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161289569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3161289569
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.445856093
Short name T238
Test name
Test status
Simulation time 58614312 ps
CPU time 0.78 seconds
Started Jul 07 06:12:30 PM PDT 24
Finished Jul 07 06:12:31 PM PDT 24
Peak memory 205012 kb
Host smart-65aab737-5802-41ad-bde2-8ce929859720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445856093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.445856093
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.1320808450
Short name T12
Test name
Test status
Simulation time 1466684412 ps
CPU time 4.47 seconds
Started Jul 07 06:12:30 PM PDT 24
Finished Jul 07 06:12:35 PM PDT 24
Peak memory 205192 kb
Host smart-5cef7869-1239-4214-9ee4-d016d758197e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320808450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1320808450
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2020185673
Short name T206
Test name
Test status
Simulation time 44188460 ps
CPU time 0.7 seconds
Started Jul 07 06:12:33 PM PDT 24
Finished Jul 07 06:12:34 PM PDT 24
Peak memory 205116 kb
Host smart-a4356c41-b322-43e0-bbfa-df6b242c49f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020185673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2020185673
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.3002240768
Short name T142
Test name
Test status
Simulation time 9698072132 ps
CPU time 22.77 seconds
Started Jul 07 06:12:31 PM PDT 24
Finished Jul 07 06:12:54 PM PDT 24
Peak memory 213572 kb
Host smart-24de630c-af7d-452a-b7d9-532539136236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002240768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3002240768
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.705462409
Short name T249
Test name
Test status
Simulation time 119376014 ps
CPU time 0.75 seconds
Started Jul 07 06:12:30 PM PDT 24
Finished Jul 07 06:12:31 PM PDT 24
Peak memory 205148 kb
Host smart-571e903f-8379-467f-970e-20c56bf819f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705462409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.705462409
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.2108339932
Short name T192
Test name
Test status
Simulation time 6037333471 ps
CPU time 5.45 seconds
Started Jul 07 06:12:34 PM PDT 24
Finished Jul 07 06:12:40 PM PDT 24
Peak memory 213516 kb
Host smart-e4af9664-13b8-482d-9c5c-fb231c0b28d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108339932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2108339932
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2796527857
Short name T228
Test name
Test status
Simulation time 144101721 ps
CPU time 0.94 seconds
Started Jul 07 06:11:57 PM PDT 24
Finished Jul 07 06:11:59 PM PDT 24
Peak memory 205072 kb
Host smart-586835b1-9b9e-4f4c-89c0-75815d6343d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796527857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2796527857
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3252768192
Short name T209
Test name
Test status
Simulation time 17578913585 ps
CPU time 50.16 seconds
Started Jul 07 06:11:57 PM PDT 24
Finished Jul 07 06:12:47 PM PDT 24
Peak memory 213572 kb
Host smart-a1efe8f2-2f54-4f70-920b-a6c42003e2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252768192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3252768192
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3939430751
Short name T267
Test name
Test status
Simulation time 1630516538 ps
CPU time 2.35 seconds
Started Jul 07 06:11:55 PM PDT 24
Finished Jul 07 06:11:57 PM PDT 24
Peak memory 205380 kb
Host smart-fcecef78-fe20-44c8-9ce1-0141944614ff
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3939430751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3939430751
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.420115188
Short name T263
Test name
Test status
Simulation time 14319353415 ps
CPU time 11.58 seconds
Started Jul 07 06:11:54 PM PDT 24
Finished Jul 07 06:12:06 PM PDT 24
Peak memory 205388 kb
Host smart-198f185e-ffb9-4339-97ee-e6a25c735410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420115188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.420115188
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.1384459070
Short name T143
Test name
Test status
Simulation time 5241845893 ps
CPU time 7.11 seconds
Started Jul 07 06:11:54 PM PDT 24
Finished Jul 07 06:12:02 PM PDT 24
Peak memory 214160 kb
Host smart-76f2bedb-cc87-4cc7-bdc9-8b0012abed0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384459070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1384459070
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3829821878
Short name T73
Test name
Test status
Simulation time 82646776 ps
CPU time 0.7 seconds
Started Jul 07 06:11:58 PM PDT 24
Finished Jul 07 06:11:59 PM PDT 24
Peak memory 205040 kb
Host smart-8e66825f-b1e6-41ec-b29f-0e2fd2b4f2f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829821878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3829821878
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1287577771
Short name T225
Test name
Test status
Simulation time 37409825850 ps
CPU time 29.51 seconds
Started Jul 07 06:12:00 PM PDT 24
Finished Jul 07 06:12:30 PM PDT 24
Peak memory 213596 kb
Host smart-283da6bf-7d3e-4046-8f1c-ead0f3effa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287577771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1287577771
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3259221143
Short name T243
Test name
Test status
Simulation time 9225934218 ps
CPU time 21.55 seconds
Started Jul 07 06:12:00 PM PDT 24
Finished Jul 07 06:12:22 PM PDT 24
Peak memory 213624 kb
Host smart-6151477c-73bc-4dd9-a973-db15e0bd206c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259221143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3259221143
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.937899907
Short name T265
Test name
Test status
Simulation time 2353697684 ps
CPU time 2.46 seconds
Started Jul 07 06:11:57 PM PDT 24
Finished Jul 07 06:12:00 PM PDT 24
Peak memory 205464 kb
Host smart-52bbebf4-5f60-4c20-bc86-6928bd257583
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=937899907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.937899907
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2794142261
Short name T251
Test name
Test status
Simulation time 3474230468 ps
CPU time 1.89 seconds
Started Jul 07 06:12:01 PM PDT 24
Finished Jul 07 06:12:03 PM PDT 24
Peak memory 205368 kb
Host smart-5c1424dc-e366-452d-8249-f72d2606e678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794142261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2794142261
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.100522164
Short name T202
Test name
Test status
Simulation time 42071919 ps
CPU time 0.73 seconds
Started Jul 07 06:11:58 PM PDT 24
Finished Jul 07 06:12:00 PM PDT 24
Peak memory 205080 kb
Host smart-62f62d74-f950-42a6-be40-06c3082ae689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100522164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.100522164
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.909395645
Short name T212
Test name
Test status
Simulation time 2755660465 ps
CPU time 4.62 seconds
Started Jul 07 06:12:03 PM PDT 24
Finished Jul 07 06:12:08 PM PDT 24
Peak memory 213564 kb
Host smart-05d76a3a-0b1a-4f81-a594-8174435a2ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909395645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.909395645
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1596863806
Short name T85
Test name
Test status
Simulation time 3049108649 ps
CPU time 9.28 seconds
Started Jul 07 06:11:57 PM PDT 24
Finished Jul 07 06:12:07 PM PDT 24
Peak memory 213600 kb
Host smart-ce6c9028-033f-4ad4-86f9-b9931cab0c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596863806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1596863806
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.214548579
Short name T2
Test name
Test status
Simulation time 3380942113 ps
CPU time 6.08 seconds
Started Jul 07 06:11:58 PM PDT 24
Finished Jul 07 06:12:04 PM PDT 24
Peak memory 213612 kb
Host smart-048cb9d9-9213-4333-8334-63604f0e6aa4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=214548579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl
_access.214548579
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.1268173011
Short name T25
Test name
Test status
Simulation time 4365680115 ps
CPU time 6.98 seconds
Started Jul 07 06:11:57 PM PDT 24
Finished Jul 07 06:12:05 PM PDT 24
Peak memory 213532 kb
Host smart-2faa9c2d-1467-450d-b20a-82cb1832bc82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268173011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1268173011
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.310559996
Short name T231
Test name
Test status
Simulation time 127021779 ps
CPU time 0.81 seconds
Started Jul 07 06:12:03 PM PDT 24
Finished Jul 07 06:12:04 PM PDT 24
Peak memory 205076 kb
Host smart-bb282da3-fa81-4171-9bc0-b911a910f8f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310559996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.310559996
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.4116831967
Short name T261
Test name
Test status
Simulation time 128045610724 ps
CPU time 57.77 seconds
Started Jul 07 06:12:03 PM PDT 24
Finished Jul 07 06:13:01 PM PDT 24
Peak memory 219568 kb
Host smart-b9ee4454-91e8-407b-b5c5-6e8edb25f9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116831967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.4116831967
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1508072145
Short name T56
Test name
Test status
Simulation time 1334425824 ps
CPU time 1.34 seconds
Started Jul 07 06:12:03 PM PDT 24
Finished Jul 07 06:12:05 PM PDT 24
Peak memory 205380 kb
Host smart-d2c2f042-03e0-49cd-8244-a21126837a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508072145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1508072145
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2773090976
Short name T157
Test name
Test status
Simulation time 9253987217 ps
CPU time 13.44 seconds
Started Jul 07 06:12:03 PM PDT 24
Finished Jul 07 06:12:17 PM PDT 24
Peak memory 205356 kb
Host smart-f82c23f3-c488-45bf-801f-359fbfc914d7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2773090976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2773090976
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3111021226
Short name T216
Test name
Test status
Simulation time 104377749 ps
CPU time 0.74 seconds
Started Jul 07 06:12:10 PM PDT 24
Finished Jul 07 06:12:11 PM PDT 24
Peak memory 205068 kb
Host smart-89795c8b-a989-4c0b-878b-914eb1ef1603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111021226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3111021226
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2259818576
Short name T67
Test name
Test status
Simulation time 5391300740 ps
CPU time 8.87 seconds
Started Jul 07 06:12:02 PM PDT 24
Finished Jul 07 06:12:12 PM PDT 24
Peak memory 213564 kb
Host smart-5df5738d-195c-482a-804f-9e233d34281c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2259818576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2259818576
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.517775281
Short name T1
Test name
Test status
Simulation time 9696071069 ps
CPU time 27.51 seconds
Started Jul 07 06:12:04 PM PDT 24
Finished Jul 07 06:12:31 PM PDT 24
Peak memory 213560 kb
Host smart-b2aa6d44-a900-41e6-b1b5-cca9d16d96fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517775281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.517775281
Directory /workspace/9.rv_dm_sba_tl_access/latest
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