SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
82.42 | 95.57 | 80.14 | 89.42 | 74.36 | 86.17 | 98.32 | 52.94 |
T92 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.962139402 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:31 PM PDT 24 | 164073774 ps | ||
T312 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1798874973 | Jul 10 05:05:22 PM PDT 24 | Jul 10 05:05:25 PM PDT 24 | 30086979 ps | ||
T93 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1270393586 | Jul 10 05:06:03 PM PDT 24 | Jul 10 05:06:26 PM PDT 24 | 2647309111 ps | ||
T102 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.868164398 | Jul 10 05:06:00 PM PDT 24 | Jul 10 05:06:09 PM PDT 24 | 203609688 ps | ||
T313 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3992055649 | Jul 10 05:06:00 PM PDT 24 | Jul 10 05:06:12 PM PDT 24 | 3865961359 ps | ||
T314 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2771546796 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:05:33 PM PDT 24 | 38133518 ps | ||
T94 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1107149854 | Jul 10 05:06:11 PM PDT 24 | Jul 10 05:06:20 PM PDT 24 | 161897041 ps | ||
T82 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2417681790 | Jul 10 05:05:20 PM PDT 24 | Jul 10 05:05:42 PM PDT 24 | 26182257012 ps | ||
T95 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2466244218 | Jul 10 05:06:01 PM PDT 24 | Jul 10 05:06:09 PM PDT 24 | 364814581 ps | ||
T103 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2869509703 | Jul 10 05:05:53 PM PDT 24 | Jul 10 05:06:02 PM PDT 24 | 2074422791 ps | ||
T315 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.159256416 | Jul 10 05:05:32 PM PDT 24 | Jul 10 05:06:57 PM PDT 24 | 44870635278 ps | ||
T109 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2518593512 | Jul 10 05:05:17 PM PDT 24 | Jul 10 05:05:33 PM PDT 24 | 4886939496 ps | ||
T83 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2089700223 | Jul 10 05:05:52 PM PDT 24 | Jul 10 05:05:54 PM PDT 24 | 277082680 ps | ||
T44 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1079988895 | Jul 10 05:05:35 PM PDT 24 | Jul 10 05:06:03 PM PDT 24 | 36232281267 ps | ||
T107 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2135237260 | Jul 10 05:05:28 PM PDT 24 | Jul 10 05:05:42 PM PDT 24 | 3389080944 ps | ||
T108 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1723862142 | Jul 10 05:06:04 PM PDT 24 | Jul 10 05:06:11 PM PDT 24 | 274498112 ps | ||
T316 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3603099353 | Jul 10 05:06:11 PM PDT 24 | Jul 10 05:06:18 PM PDT 24 | 197246378 ps | ||
T104 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.698327762 | Jul 10 05:06:03 PM PDT 24 | Jul 10 05:06:14 PM PDT 24 | 1749006313 ps | ||
T191 | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.4026978353 | Jul 10 05:05:35 PM PDT 24 | Jul 10 05:06:07 PM PDT 24 | 37063475105 ps | ||
T105 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2764702667 | Jul 10 05:05:33 PM PDT 24 | Jul 10 05:05:42 PM PDT 24 | 2208508547 ps | ||
T317 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3071769994 | Jul 10 05:06:05 PM PDT 24 | Jul 10 05:06:09 PM PDT 24 | 675961910 ps | ||
T106 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3876110141 | Jul 10 05:05:33 PM PDT 24 | Jul 10 05:05:39 PM PDT 24 | 323241413 ps | ||
T137 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3919785408 | Jul 10 05:06:08 PM PDT 24 | Jul 10 05:06:13 PM PDT 24 | 93633257 ps | ||
T318 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3908509168 | Jul 10 05:05:52 PM PDT 24 | Jul 10 05:05:56 PM PDT 24 | 503652368 ps | ||
T110 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2654854265 | Jul 10 05:05:30 PM PDT 24 | Jul 10 05:05:38 PM PDT 24 | 3675572723 ps | ||
T319 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.380968479 | Jul 10 05:05:52 PM PDT 24 | Jul 10 05:05:57 PM PDT 24 | 2812569019 ps | ||
T320 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3473912283 | Jul 10 05:05:51 PM PDT 24 | Jul 10 05:06:07 PM PDT 24 | 6556968227 ps | ||
T196 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3570571996 | Jul 10 05:05:52 PM PDT 24 | Jul 10 05:06:15 PM PDT 24 | 5590490966 ps | ||
T321 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.891611290 | Jul 10 05:06:01 PM PDT 24 | Jul 10 05:06:10 PM PDT 24 | 1656104365 ps | ||
T322 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2598693797 | Jul 10 05:05:59 PM PDT 24 | Jul 10 05:06:03 PM PDT 24 | 75599476 ps | ||
T139 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2140518581 | Jul 10 05:05:28 PM PDT 24 | Jul 10 05:05:35 PM PDT 24 | 301292655 ps | ||
T240 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.454850015 | Jul 10 05:05:35 PM PDT 24 | Jul 10 05:05:51 PM PDT 24 | 5681659948 ps | ||
T323 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1180350276 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:05:50 PM PDT 24 | 16390352137 ps | ||
T324 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3380815433 | Jul 10 05:06:07 PM PDT 24 | Jul 10 05:06:18 PM PDT 24 | 2772201727 ps | ||
T114 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.172829480 | Jul 10 05:05:52 PM PDT 24 | Jul 10 05:05:55 PM PDT 24 | 78184453 ps | ||
T325 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3168825100 | Jul 10 05:05:51 PM PDT 24 | Jul 10 05:06:07 PM PDT 24 | 5935676054 ps | ||
T326 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.67274236 | Jul 10 05:05:30 PM PDT 24 | Jul 10 05:06:40 PM PDT 24 | 27319964534 ps | ||
T239 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3270443320 | Jul 10 05:06:14 PM PDT 24 | Jul 10 05:06:26 PM PDT 24 | 3123830773 ps | ||
T327 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.219958826 | Jul 10 05:05:29 PM PDT 24 | Jul 10 05:06:31 PM PDT 24 | 37278167241 ps | ||
T115 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1515582749 | Jul 10 05:05:52 PM PDT 24 | Jul 10 05:05:58 PM PDT 24 | 344987540 ps | ||
T328 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.376118600 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:31 PM PDT 24 | 468136969 ps | ||
T140 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2005813024 | Jul 10 05:05:52 PM PDT 24 | Jul 10 05:07:06 PM PDT 24 | 24660986713 ps | ||
T134 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1776608850 | Jul 10 05:05:34 PM PDT 24 | Jul 10 05:05:42 PM PDT 24 | 475254921 ps | ||
T141 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3244045567 | Jul 10 05:06:10 PM PDT 24 | Jul 10 05:06:27 PM PDT 24 | 1178462343 ps | ||
T142 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3524710348 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:32 PM PDT 24 | 639050421 ps | ||
T329 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3943305864 | Jul 10 05:05:28 PM PDT 24 | Jul 10 05:05:34 PM PDT 24 | 55888705 ps | ||
T330 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3573869620 | Jul 10 05:06:09 PM PDT 24 | Jul 10 05:08:44 PM PDT 24 | 68297091245 ps | ||
T331 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1159853445 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:05:34 PM PDT 24 | 130655229 ps | ||
T332 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.548478674 | Jul 10 05:05:29 PM PDT 24 | Jul 10 05:05:36 PM PDT 24 | 501862910 ps | ||
T116 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1764108816 | Jul 10 05:06:08 PM PDT 24 | Jul 10 05:06:15 PM PDT 24 | 942094290 ps | ||
T333 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2811056440 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:05:33 PM PDT 24 | 93361362 ps | ||
T117 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.106398266 | Jul 10 05:05:56 PM PDT 24 | Jul 10 05:06:00 PM PDT 24 | 217273217 ps | ||
T334 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.548593766 | Jul 10 05:05:41 PM PDT 24 | Jul 10 05:05:52 PM PDT 24 | 3770563973 ps | ||
T335 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.772280484 | Jul 10 05:05:58 PM PDT 24 | Jul 10 05:06:09 PM PDT 24 | 5407574267 ps | ||
T336 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3695150576 | Jul 10 05:05:54 PM PDT 24 | Jul 10 05:05:56 PM PDT 24 | 514635343 ps | ||
T111 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2118079411 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:06:06 PM PDT 24 | 13149884911 ps | ||
T337 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1568436191 | Jul 10 05:05:41 PM PDT 24 | Jul 10 05:05:49 PM PDT 24 | 4706125425 ps | ||
T199 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3129619164 | Jul 10 05:06:09 PM PDT 24 | Jul 10 05:06:24 PM PDT 24 | 761962582 ps | ||
T126 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1640231341 | Jul 10 05:06:08 PM PDT 24 | Jul 10 05:06:13 PM PDT 24 | 184506432 ps | ||
T338 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3938612904 | Jul 10 05:06:10 PM PDT 24 | Jul 10 05:06:21 PM PDT 24 | 2517401066 ps | ||
T135 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1553950218 | Jul 10 05:06:06 PM PDT 24 | Jul 10 05:06:12 PM PDT 24 | 536259153 ps | ||
T192 | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.966794619 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:06:00 PM PDT 24 | 29691812935 ps | ||
T339 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2634038919 | Jul 10 05:05:34 PM PDT 24 | Jul 10 05:05:39 PM PDT 24 | 96541680 ps | ||
T340 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4002296299 | Jul 10 05:05:28 PM PDT 24 | Jul 10 05:05:35 PM PDT 24 | 468817883 ps | ||
T200 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2352802113 | Jul 10 05:05:53 PM PDT 24 | Jul 10 05:06:04 PM PDT 24 | 1256322555 ps | ||
T193 | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2482266210 | Jul 10 05:05:24 PM PDT 24 | Jul 10 05:06:50 PM PDT 24 | 27962352770 ps | ||
T341 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4077747838 | Jul 10 05:06:00 PM PDT 24 | Jul 10 05:06:08 PM PDT 24 | 3767794687 ps | ||
T118 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.945062237 | Jul 10 05:05:35 PM PDT 24 | Jul 10 05:05:40 PM PDT 24 | 494155845 ps | ||
T342 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3063017435 | Jul 10 05:06:02 PM PDT 24 | Jul 10 05:06:16 PM PDT 24 | 13969452476 ps | ||
T119 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.374911366 | Jul 10 05:05:18 PM PDT 24 | Jul 10 05:05:27 PM PDT 24 | 241781790 ps | ||
T343 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3595041636 | Jul 10 05:05:41 PM PDT 24 | Jul 10 05:08:06 PM PDT 24 | 49032794842 ps | ||
T344 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.888016948 | Jul 10 05:06:10 PM PDT 24 | Jul 10 05:06:20 PM PDT 24 | 464248338 ps | ||
T345 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2029444673 | Jul 10 05:05:19 PM PDT 24 | Jul 10 05:05:25 PM PDT 24 | 273703323 ps | ||
T346 | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.189071775 | Jul 10 05:05:39 PM PDT 24 | Jul 10 05:05:43 PM PDT 24 | 211932948 ps | ||
T136 | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4212286710 | Jul 10 05:06:01 PM PDT 24 | Jul 10 05:06:08 PM PDT 24 | 330954370 ps | ||
T347 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3232295797 | Jul 10 05:05:22 PM PDT 24 | Jul 10 05:05:26 PM PDT 24 | 266819829 ps | ||
T348 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1514971137 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:29 PM PDT 24 | 93786142 ps | ||
T349 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1439390869 | Jul 10 05:06:04 PM PDT 24 | Jul 10 05:06:11 PM PDT 24 | 1053412841 ps | ||
T350 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4040370633 | Jul 10 05:06:02 PM PDT 24 | Jul 10 05:06:26 PM PDT 24 | 15485309770 ps | ||
T120 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3198098552 | Jul 10 05:05:53 PM PDT 24 | Jul 10 05:05:59 PM PDT 24 | 239262133 ps | ||
T351 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.490094611 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:05:39 PM PDT 24 | 21607374008 ps | ||
T121 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3900675535 | Jul 10 05:06:00 PM PDT 24 | Jul 10 05:06:08 PM PDT 24 | 989639865 ps | ||
T352 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1682748970 | Jul 10 05:06:09 PM PDT 24 | Jul 10 05:06:20 PM PDT 24 | 2509449210 ps | ||
T353 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.949663850 | Jul 10 05:05:34 PM PDT 24 | Jul 10 05:05:41 PM PDT 24 | 3117772590 ps | ||
T354 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3403259154 | Jul 10 05:05:48 PM PDT 24 | Jul 10 05:05:58 PM PDT 24 | 5977860653 ps | ||
T355 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4087724708 | Jul 10 05:05:40 PM PDT 24 | Jul 10 05:05:44 PM PDT 24 | 332483293 ps | ||
T194 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2526624561 | Jul 10 05:05:35 PM PDT 24 | Jul 10 05:05:57 PM PDT 24 | 4323473039 ps | ||
T356 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2105318718 | Jul 10 05:05:40 PM PDT 24 | Jul 10 05:05:45 PM PDT 24 | 184199776 ps | ||
T357 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1467277466 | Jul 10 05:05:40 PM PDT 24 | Jul 10 05:05:44 PM PDT 24 | 235387925 ps | ||
T358 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.556842950 | Jul 10 05:05:53 PM PDT 24 | Jul 10 05:06:09 PM PDT 24 | 5678133556 ps | ||
T359 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.620043358 | Jul 10 05:05:52 PM PDT 24 | Jul 10 05:06:00 PM PDT 24 | 468270159 ps | ||
T360 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1937207358 | Jul 10 05:05:40 PM PDT 24 | Jul 10 05:05:45 PM PDT 24 | 4852572431 ps | ||
T361 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1830170862 | Jul 10 05:05:29 PM PDT 24 | Jul 10 05:05:51 PM PDT 24 | 11422784101 ps | ||
T362 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2143657383 | Jul 10 05:05:28 PM PDT 24 | Jul 10 05:05:35 PM PDT 24 | 310422218 ps | ||
T363 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2543374330 | Jul 10 05:06:00 PM PDT 24 | Jul 10 05:06:09 PM PDT 24 | 295501176 ps | ||
T364 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1044487017 | Jul 10 05:05:28 PM PDT 24 | Jul 10 05:05:42 PM PDT 24 | 472196106 ps | ||
T201 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3016934936 | Jul 10 05:05:25 PM PDT 24 | Jul 10 05:05:35 PM PDT 24 | 1022739036 ps | ||
T365 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3061606698 | Jul 10 05:06:01 PM PDT 24 | Jul 10 05:06:15 PM PDT 24 | 2228257233 ps | ||
T366 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1246851532 | Jul 10 05:05:28 PM PDT 24 | Jul 10 05:05:39 PM PDT 24 | 6057810773 ps | ||
T367 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2595454765 | Jul 10 05:06:09 PM PDT 24 | Jul 10 05:06:17 PM PDT 24 | 382716318 ps | ||
T368 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.312218662 | Jul 10 05:05:33 PM PDT 24 | Jul 10 05:05:41 PM PDT 24 | 498346772 ps | ||
T369 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2986247053 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:05:38 PM PDT 24 | 531214100 ps | ||
T370 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.784442460 | Jul 10 05:05:23 PM PDT 24 | Jul 10 05:05:26 PM PDT 24 | 1867625711 ps | ||
T371 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1900270295 | Jul 10 05:05:24 PM PDT 24 | Jul 10 05:05:27 PM PDT 24 | 352031102 ps | ||
T372 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3148594112 | Jul 10 05:05:16 PM PDT 24 | Jul 10 05:05:53 PM PDT 24 | 3942316635 ps | ||
T373 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4095332515 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:56 PM PDT 24 | 30149166715 ps | ||
T374 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1346590789 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:05:33 PM PDT 24 | 232054880 ps | ||
T375 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3212022385 | Jul 10 05:05:40 PM PDT 24 | Jul 10 05:06:20 PM PDT 24 | 13533329852 ps | ||
T376 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1322661910 | Jul 10 05:05:23 PM PDT 24 | Jul 10 05:05:26 PM PDT 24 | 295142888 ps | ||
T127 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3092340446 | Jul 10 05:05:29 PM PDT 24 | Jul 10 05:06:31 PM PDT 24 | 1965010973 ps | ||
T377 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2587030182 | Jul 10 05:06:10 PM PDT 24 | Jul 10 05:06:18 PM PDT 24 | 2138513375 ps | ||
T378 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.917646713 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:31 PM PDT 24 | 845176845 ps | ||
T128 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2093073965 | Jul 10 05:06:01 PM PDT 24 | Jul 10 05:06:07 PM PDT 24 | 207544362 ps | ||
T379 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4183235271 | Jul 10 05:05:59 PM PDT 24 | Jul 10 05:06:05 PM PDT 24 | 306702492 ps | ||
T198 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.397301139 | Jul 10 05:06:00 PM PDT 24 | Jul 10 05:06:32 PM PDT 24 | 5432437540 ps | ||
T380 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1165167060 | Jul 10 05:06:12 PM PDT 24 | Jul 10 05:06:18 PM PDT 24 | 221904832 ps | ||
T381 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.55974557 | Jul 10 05:05:53 PM PDT 24 | Jul 10 05:05:58 PM PDT 24 | 451948620 ps | ||
T382 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.276978231 | Jul 10 05:05:25 PM PDT 24 | Jul 10 05:05:32 PM PDT 24 | 616798370 ps | ||
T383 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.496989571 | Jul 10 05:05:24 PM PDT 24 | Jul 10 05:05:29 PM PDT 24 | 2293552898 ps | ||
T384 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3148644896 | Jul 10 05:06:10 PM PDT 24 | Jul 10 05:06:18 PM PDT 24 | 377853190 ps | ||
T385 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.95865710 | Jul 10 05:06:07 PM PDT 24 | Jul 10 05:06:12 PM PDT 24 | 129154232 ps | ||
T386 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1558470703 | Jul 10 05:06:05 PM PDT 24 | Jul 10 05:06:10 PM PDT 24 | 297210250 ps | ||
T387 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2410944873 | Jul 10 05:06:08 PM PDT 24 | Jul 10 05:06:14 PM PDT 24 | 259151435 ps | ||
T132 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2221408317 | Jul 10 05:05:19 PM PDT 24 | Jul 10 05:05:23 PM PDT 24 | 119563182 ps | ||
T133 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3962399357 | Jul 10 05:05:59 PM PDT 24 | Jul 10 05:06:04 PM PDT 24 | 902305272 ps | ||
T195 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.540546122 | Jul 10 05:06:10 PM PDT 24 | Jul 10 05:06:24 PM PDT 24 | 608611818 ps | ||
T388 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.757837613 | Jul 10 05:05:51 PM PDT 24 | Jul 10 05:05:53 PM PDT 24 | 610685668 ps | ||
T389 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1212174058 | Jul 10 05:05:25 PM PDT 24 | Jul 10 05:05:41 PM PDT 24 | 6183708386 ps | ||
T390 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.10687183 | Jul 10 05:05:34 PM PDT 24 | Jul 10 05:05:39 PM PDT 24 | 226641104 ps | ||
T391 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4260539909 | Jul 10 05:05:17 PM PDT 24 | Jul 10 05:05:18 PM PDT 24 | 280310029 ps | ||
T392 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3494239699 | Jul 10 05:05:53 PM PDT 24 | Jul 10 05:05:57 PM PDT 24 | 3008590760 ps | ||
T122 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.516363147 | Jul 10 05:05:28 PM PDT 24 | Jul 10 05:06:37 PM PDT 24 | 1178455472 ps | ||
T393 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2955800245 | Jul 10 05:06:09 PM PDT 24 | Jul 10 05:07:34 PM PDT 24 | 29355216913 ps | ||
T394 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1350685406 | Jul 10 05:05:56 PM PDT 24 | Jul 10 05:06:01 PM PDT 24 | 1800580923 ps | ||
T395 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3545749076 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:30 PM PDT 24 | 664616652 ps | ||
T396 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2462003346 | Jul 10 05:05:33 PM PDT 24 | Jul 10 05:05:47 PM PDT 24 | 2960306826 ps | ||
T397 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3023748528 | Jul 10 05:06:06 PM PDT 24 | Jul 10 05:06:14 PM PDT 24 | 6481621242 ps | ||
T398 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2002208411 | Jul 10 05:05:32 PM PDT 24 | Jul 10 05:06:44 PM PDT 24 | 10220699459 ps | ||
T399 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.691889788 | Jul 10 05:05:32 PM PDT 24 | Jul 10 05:06:37 PM PDT 24 | 23907181084 ps | ||
T400 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3235061918 | Jul 10 05:06:05 PM PDT 24 | Jul 10 05:06:12 PM PDT 24 | 214768199 ps | ||
T401 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3236387472 | Jul 10 05:05:18 PM PDT 24 | Jul 10 05:06:47 PM PDT 24 | 32721788960 ps | ||
T130 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1719721978 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:05:35 PM PDT 24 | 280768840 ps | ||
T402 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1125571710 | Jul 10 05:05:34 PM PDT 24 | Jul 10 05:05:40 PM PDT 24 | 347453640 ps | ||
T403 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1324075831 | Jul 10 05:06:02 PM PDT 24 | Jul 10 05:06:06 PM PDT 24 | 373948308 ps | ||
T404 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3471675070 | Jul 10 05:05:50 PM PDT 24 | Jul 10 05:05:54 PM PDT 24 | 77670848 ps | ||
T405 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3748862865 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:06:21 PM PDT 24 | 31168433001 ps | ||
T406 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3023967501 | Jul 10 05:06:01 PM PDT 24 | Jul 10 05:06:06 PM PDT 24 | 986465866 ps | ||
T407 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3121284919 | Jul 10 05:06:08 PM PDT 24 | Jul 10 05:06:14 PM PDT 24 | 68359195 ps | ||
T408 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2702428815 | Jul 10 05:06:01 PM PDT 24 | Jul 10 05:06:09 PM PDT 24 | 922964086 ps | ||
T409 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3529939812 | Jul 10 05:05:19 PM PDT 24 | Jul 10 05:05:23 PM PDT 24 | 413987553 ps | ||
T410 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.958065203 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:33 PM PDT 24 | 235781458 ps | ||
T411 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1005719539 | Jul 10 05:06:03 PM PDT 24 | Jul 10 05:06:07 PM PDT 24 | 178643613 ps | ||
T131 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.694970742 | Jul 10 05:06:00 PM PDT 24 | Jul 10 05:06:06 PM PDT 24 | 120541603 ps | ||
T412 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2022946110 | Jul 10 05:05:33 PM PDT 24 | Jul 10 05:05:40 PM PDT 24 | 212159119 ps | ||
T413 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.347541686 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:05:41 PM PDT 24 | 3098422083 ps | ||
T414 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.213004558 | Jul 10 05:05:33 PM PDT 24 | Jul 10 05:05:45 PM PDT 24 | 847229242 ps | ||
T415 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1201497706 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:06:05 PM PDT 24 | 8436491081 ps | ||
T416 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1720161784 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:05:34 PM PDT 24 | 1942624253 ps | ||
T417 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2167788122 | Jul 10 05:05:20 PM PDT 24 | Jul 10 05:05:44 PM PDT 24 | 8023308505 ps | ||
T123 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.18152074 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:06:49 PM PDT 24 | 14666642167 ps | ||
T124 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.220981311 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:32 PM PDT 24 | 360031327 ps | ||
T418 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.135804597 | Jul 10 05:05:28 PM PDT 24 | Jul 10 05:05:43 PM PDT 24 | 5434022561 ps | ||
T419 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2769368874 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:06:06 PM PDT 24 | 4265259578 ps | ||
T420 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2604385413 | Jul 10 05:05:31 PM PDT 24 | Jul 10 05:05:38 PM PDT 24 | 199906995 ps | ||
T421 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2791661593 | Jul 10 05:06:08 PM PDT 24 | Jul 10 05:06:15 PM PDT 24 | 259485566 ps | ||
T422 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1214703249 | Jul 10 05:05:21 PM PDT 24 | Jul 10 05:05:24 PM PDT 24 | 462981871 ps | ||
T423 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3888366019 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:58 PM PDT 24 | 1839276933 ps | ||
T424 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.6915878 | Jul 10 05:05:29 PM PDT 24 | Jul 10 05:05:42 PM PDT 24 | 2975351521 ps | ||
T202 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1381515192 | Jul 10 05:05:40 PM PDT 24 | Jul 10 05:06:05 PM PDT 24 | 5859427775 ps | ||
T425 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2459088090 | Jul 10 05:05:54 PM PDT 24 | Jul 10 05:06:02 PM PDT 24 | 301500570 ps | ||
T112 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1040487038 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:46 PM PDT 24 | 15413413242 ps | ||
T426 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2210768923 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:52 PM PDT 24 | 4438997452 ps | ||
T197 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2082275687 | Jul 10 05:05:42 PM PDT 24 | Jul 10 05:06:04 PM PDT 24 | 2407561176 ps | ||
T427 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2450473907 | Jul 10 05:06:08 PM PDT 24 | Jul 10 05:06:28 PM PDT 24 | 46292006522 ps | ||
T125 | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3440649836 | Jul 10 05:06:09 PM PDT 24 | Jul 10 05:06:21 PM PDT 24 | 1729516821 ps | ||
T428 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3050850473 | Jul 10 05:06:03 PM PDT 24 | Jul 10 05:06:09 PM PDT 24 | 2092127017 ps | ||
T429 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4228071677 | Jul 10 05:06:08 PM PDT 24 | Jul 10 05:06:12 PM PDT 24 | 140792031 ps | ||
T430 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2415629640 | Jul 10 05:06:03 PM PDT 24 | Jul 10 05:06:15 PM PDT 24 | 756031069 ps | ||
T431 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2828491215 | Jul 10 05:05:25 PM PDT 24 | Jul 10 05:05:35 PM PDT 24 | 3625444493 ps | ||
T432 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3340237623 | Jul 10 05:06:04 PM PDT 24 | Jul 10 05:06:12 PM PDT 24 | 1456177203 ps | ||
T433 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1284965072 | Jul 10 05:05:34 PM PDT 24 | Jul 10 05:05:38 PM PDT 24 | 187138710 ps | ||
T434 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4029781016 | Jul 10 05:06:10 PM PDT 24 | Jul 10 05:06:18 PM PDT 24 | 639725549 ps | ||
T435 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3713866825 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:33 PM PDT 24 | 194000017 ps | ||
T436 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.37110912 | Jul 10 05:05:19 PM PDT 24 | Jul 10 05:05:29 PM PDT 24 | 718921143 ps | ||
T437 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4213110070 | Jul 10 05:06:08 PM PDT 24 | Jul 10 05:06:17 PM PDT 24 | 310808732 ps | ||
T438 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.327091797 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:34 PM PDT 24 | 88006129 ps | ||
T439 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.222764294 | Jul 10 05:05:18 PM PDT 24 | Jul 10 05:06:15 PM PDT 24 | 62076132321 ps | ||
T440 | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.930252265 | Jul 10 05:05:51 PM PDT 24 | Jul 10 05:07:55 PM PDT 24 | 61446437423 ps | ||
T113 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1704710390 | Jul 10 05:05:28 PM PDT 24 | Jul 10 05:05:42 PM PDT 24 | 2908205617 ps | ||
T441 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2766084397 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:06:42 PM PDT 24 | 15003314682 ps | ||
T442 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3229998247 | Jul 10 05:06:05 PM PDT 24 | Jul 10 05:06:35 PM PDT 24 | 35637592281 ps | ||
T129 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3935771493 | Jul 10 05:05:28 PM PDT 24 | Jul 10 05:06:01 PM PDT 24 | 760352372 ps | ||
T443 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.794601992 | Jul 10 05:05:27 PM PDT 24 | Jul 10 05:05:32 PM PDT 24 | 173050241 ps | ||
T444 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3798680264 | Jul 10 05:05:39 PM PDT 24 | Jul 10 05:05:41 PM PDT 24 | 61161633 ps | ||
T445 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4103294817 | Jul 10 05:05:59 PM PDT 24 | Jul 10 05:06:02 PM PDT 24 | 80767914 ps | ||
T446 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4079500533 | Jul 10 05:06:10 PM PDT 24 | Jul 10 05:06:43 PM PDT 24 | 13290354078 ps | ||
T447 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3406456687 | Jul 10 05:05:59 PM PDT 24 | Jul 10 05:06:03 PM PDT 24 | 338909980 ps | ||
T448 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4016252300 | Jul 10 05:05:26 PM PDT 24 | Jul 10 05:05:29 PM PDT 24 | 52481492 ps |
Test location | /workspace/coverage/default/18.rv_dm_stress_all.3423440460 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 6427525457 ps |
CPU time | 6.13 seconds |
Started | Jul 10 05:51:16 PM PDT 24 |
Finished | Jul 10 05:51:28 PM PDT 24 |
Peak memory | 213752 kb |
Host | smart-ddf7d93f-dd4e-48e1-ab17-b3ac89f4a7ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423440460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.3423440460 |
Directory | /workspace/18.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2276313888 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 8868025970 ps |
CPU time | 4.86 seconds |
Started | Jul 10 05:51:19 PM PDT 24 |
Finished | Jul 10 05:51:28 PM PDT 24 |
Peak memory | 213896 kb |
Host | smart-ec1e07ee-404e-4628-af73-523e57b3faef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276313888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2276313888 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2346479610 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 15354012748 ps |
CPU time | 13.17 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:05:46 PM PDT 24 |
Peak memory | 221416 kb |
Host | smart-0ceca559-7a1b-4de6-9211-5928187ab46f |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346479610 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2346479610 |
Directory | /workspace/2.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.3265798816 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 10758455882 ps |
CPU time | 28.8 seconds |
Started | Jul 10 05:51:11 PM PDT 24 |
Finished | Jul 10 05:51:43 PM PDT 24 |
Peak memory | 222008 kb |
Host | smart-b88eafaa-41cb-4d3a-8b5a-300c07022661 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265798816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3265798816 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.879450457 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 2582365089 ps |
CPU time | 9.15 seconds |
Started | Jul 10 05:05:50 PM PDT 24 |
Finished | Jul 10 05:06:00 PM PDT 24 |
Peak memory | 213284 kb |
Host | smart-b4152f8f-fda5-42f9-89ef-a6ff4fce5937 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879450457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.879450457 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1079988895 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 36232281267 ps |
CPU time | 25.39 seconds |
Started | Jul 10 05:05:35 PM PDT 24 |
Finished | Jul 10 05:06:03 PM PDT 24 |
Peak memory | 216848 kb |
Host | smart-5ce77cc5-6c96-494a-a037-ca6a5f49ed5d |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079988895 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.1079988895 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.2973272538 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 138350973 ps |
CPU time | 0.98 seconds |
Started | Jul 10 05:51:03 PM PDT 24 |
Finished | Jul 10 05:51:09 PM PDT 24 |
Peak memory | 215688 kb |
Host | smart-93ade066-770b-4fdf-bb24-e9411fac05c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2973272538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2973272538 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.1323177930 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 123682782 ps |
CPU time | 0.81 seconds |
Started | Jul 10 05:51:36 PM PDT 24 |
Finished | Jul 10 05:51:38 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-567d3037-c368-4bd6-a913-4e9617f75988 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323177930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1323177930 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.4294913457 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 7211380871 ps |
CPU time | 7.27 seconds |
Started | Jul 10 05:51:11 PM PDT 24 |
Finished | Jul 10 05:51:22 PM PDT 24 |
Peak memory | 213896 kb |
Host | smart-e2847ff2-2800-41b5-98a5-b45fbf84f852 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4294913457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.4294913457 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_stress_all.3056578810 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 5465257237 ps |
CPU time | 3.18 seconds |
Started | Jul 10 05:51:12 PM PDT 24 |
Finished | Jul 10 05:51:20 PM PDT 24 |
Peak memory | 205652 kb |
Host | smart-7553765b-e6a3-4244-ab65-e72ab0f82b3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056578810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3056578810 |
Directory | /workspace/15.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.3586419823 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 80263268718 ps |
CPU time | 39.07 seconds |
Started | Jul 10 05:51:17 PM PDT 24 |
Finished | Jul 10 05:52:01 PM PDT 24 |
Peak memory | 214060 kb |
Host | smart-b39a7972-df6f-43c6-b8a8-1e869f0c78b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3586419823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3586419823 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.1869034416 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 1054082542 ps |
CPU time | 1.49 seconds |
Started | Jul 10 05:50:57 PM PDT 24 |
Finished | Jul 10 05:51:03 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-62fc8592-dc1b-4683-83a9-ed31c88b0214 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1869034416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1869034416 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3611583110 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 125891993 ps |
CPU time | 2.43 seconds |
Started | Jul 10 05:05:35 PM PDT 24 |
Finished | Jul 10 05:05:41 PM PDT 24 |
Peak memory | 213096 kb |
Host | smart-36b17e3f-5d86-45c9-8f81-3d791855b94e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611583110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3611583110 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/default/26.rv_dm_stress_all.190101278 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 8254053550 ps |
CPU time | 12.26 seconds |
Started | Jul 10 05:51:21 PM PDT 24 |
Finished | Jul 10 05:51:37 PM PDT 24 |
Peak memory | 205556 kb |
Host | smart-0387c00e-d7a4-460f-b7bb-e349d5345c3f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190101278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.190101278 |
Directory | /workspace/26.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.3363244914 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 639189674 ps |
CPU time | 2.51 seconds |
Started | Jul 10 05:50:53 PM PDT 24 |
Finished | Jul 10 05:50:57 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-fc9f349c-1aa0-4170-9d96-3bbc020696d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363244914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3363244914 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.4276149495 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 202179741 ps |
CPU time | 0.86 seconds |
Started | Jul 10 05:50:55 PM PDT 24 |
Finished | Jul 10 05:50:57 PM PDT 24 |
Peak memory | 213628 kb |
Host | smart-d172e246-72de-455e-9288-27dd2cf49438 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4276149495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.4276149495 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.119331308 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 659325879 ps |
CPU time | 2.01 seconds |
Started | Jul 10 05:50:59 PM PDT 24 |
Finished | Jul 10 05:51:06 PM PDT 24 |
Peak memory | 229008 kb |
Host | smart-60f3d712-e4e0-4b03-8a4b-cc675c9fdae9 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119331308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.119331308 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1270393586 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 2647309111 ps |
CPU time | 19.76 seconds |
Started | Jul 10 05:06:03 PM PDT 24 |
Finished | Jul 10 05:06:26 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-93ac88be-a394-4958-b218-48d90c25d0fc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270393586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1 270393586 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/21.rv_dm_stress_all.4004534424 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 3642477520 ps |
CPU time | 6.13 seconds |
Started | Jul 10 05:51:14 PM PDT 24 |
Finished | Jul 10 05:51:25 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-ca8e1164-f46d-4c4c-9067-3a88dba6ef0f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004534424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.4004534424 |
Directory | /workspace/21.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.1900941145 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 4758851477 ps |
CPU time | 7.12 seconds |
Started | Jul 10 05:51:24 PM PDT 24 |
Finished | Jul 10 05:51:33 PM PDT 24 |
Peak memory | 205624 kb |
Host | smart-a900b9d1-b6a3-4183-8843-2d07d9784efd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900941145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1900941145 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.2219152359 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 564575506 ps |
CPU time | 1.96 seconds |
Started | Jul 10 05:50:53 PM PDT 24 |
Finished | Jul 10 05:50:57 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-aaee7caa-14f3-443b-ad12-9f4dc8de065d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219152359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2219152359 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3357638672 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 3898173467 ps |
CPU time | 4.65 seconds |
Started | Jul 10 05:51:12 PM PDT 24 |
Finished | Jul 10 05:51:21 PM PDT 24 |
Peak memory | 213788 kb |
Host | smart-8f4635dd-0495-443f-9858-b98f97b7322d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3357638672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3357638672 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.516363147 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 1178455472 ps |
CPU time | 64.39 seconds |
Started | Jul 10 05:05:28 PM PDT 24 |
Finished | Jul 10 05:06:37 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-4ebb8227-b341-46f8-9c4b-79d5eb811b30 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516363147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 4.rv_dm_csr_aliasing.516363147 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1834776894 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 6709779442 ps |
CPU time | 5.96 seconds |
Started | Jul 10 05:51:15 PM PDT 24 |
Finished | Jul 10 05:51:26 PM PDT 24 |
Peak memory | 215580 kb |
Host | smart-b54f1578-b85e-4eb8-ba2d-e472eee524d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834776894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1834776894 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2134233291 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 3004052683 ps |
CPU time | 6.37 seconds |
Started | Jul 10 05:51:16 PM PDT 24 |
Finished | Jul 10 05:51:27 PM PDT 24 |
Peak memory | 213860 kb |
Host | smart-02da9fe7-1c4a-4339-a051-ed248eaf3a48 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2134233291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2134233291 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.3916019342 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 434215770 ps |
CPU time | 2 seconds |
Started | Jul 10 05:51:00 PM PDT 24 |
Finished | Jul 10 05:51:08 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-16f1f504-7e7f-4fc4-8ac4-1fc30e47389c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3916019342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.3916019342 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3492302353 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 1671224793 ps |
CPU time | 2.33 seconds |
Started | Jul 10 05:51:14 PM PDT 24 |
Finished | Jul 10 05:51:21 PM PDT 24 |
Peak memory | 213760 kb |
Host | smart-b756438a-02b2-4eea-8654-227b0e09da08 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492302353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3492302353 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2082275687 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 2407561176 ps |
CPU time | 20.47 seconds |
Started | Jul 10 05:05:42 PM PDT 24 |
Finished | Jul 10 05:06:04 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-a7a800dd-8d35-4b5f-b6ee-5b81fcf48d01 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082275687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2082275687 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.2318844468 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 7967629558 ps |
CPU time | 5.16 seconds |
Started | Jul 10 05:51:19 PM PDT 24 |
Finished | Jul 10 05:51:28 PM PDT 24 |
Peak memory | 205560 kb |
Host | smart-67cc171e-7f2b-4054-b68d-8091ed728bec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318844468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2318844468 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.211605801 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 12576523735 ps |
CPU time | 16.51 seconds |
Started | Jul 10 05:51:23 PM PDT 24 |
Finished | Jul 10 05:51:42 PM PDT 24 |
Peak memory | 205576 kb |
Host | smart-19f8a917-fb3f-47f7-bba1-f889e3a69166 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211605801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.211605801 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.930013243 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 1721054463 ps |
CPU time | 5.32 seconds |
Started | Jul 10 05:51:05 PM PDT 24 |
Finished | Jul 10 05:51:15 PM PDT 24 |
Peak memory | 213884 kb |
Host | smart-7f23b2c2-6527-4e3f-87c5-aaab3bfce322 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930013243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.930013243 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.868164398 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 203609688 ps |
CPU time | 6.6 seconds |
Started | Jul 10 05:06:00 PM PDT 24 |
Finished | Jul 10 05:06:09 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-3ced190a-dd12-4e9e-829c-d6f0136744bc |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868164398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_ csr_outstanding.868164398 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2417681790 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 26182257012 ps |
CPU time | 19.73 seconds |
Started | Jul 10 05:05:20 PM PDT 24 |
Finished | Jul 10 05:05:42 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-d9380311-ea3d-4431-a4b8-b861f475ee0a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417681790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.2417681790 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2518593512 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 4886939496 ps |
CPU time | 14.57 seconds |
Started | Jul 10 05:05:17 PM PDT 24 |
Finished | Jul 10 05:05:33 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-c5c55c1a-bd79-4fb0-86a2-66f7d650c0eb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518593512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.2518593512 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.906626160 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 7649237079 ps |
CPU time | 21.92 seconds |
Started | Jul 10 05:50:59 PM PDT 24 |
Finished | Jul 10 05:51:27 PM PDT 24 |
Peak memory | 205552 kb |
Host | smart-9704229a-3526-47dc-ac40-3e02637f260b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=906626160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.906626160 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.1743838771 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 2333770458 ps |
CPU time | 7.13 seconds |
Started | Jul 10 05:51:14 PM PDT 24 |
Finished | Jul 10 05:51:26 PM PDT 24 |
Peak memory | 205700 kb |
Host | smart-385eb396-fe7e-4636-925d-494a7f157c45 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1743838771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1743838771 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.903774680 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 10284833351 ps |
CPU time | 3.79 seconds |
Started | Jul 10 05:51:15 PM PDT 24 |
Finished | Jul 10 05:51:23 PM PDT 24 |
Peak memory | 213872 kb |
Host | smart-4a8a05e3-ac95-4526-a5a1-5488a57ce75b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=903774680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.903774680 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.2861890501 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 2871235359 ps |
CPU time | 5.35 seconds |
Started | Jul 10 05:51:14 PM PDT 24 |
Finished | Jul 10 05:51:25 PM PDT 24 |
Peak memory | 205560 kb |
Host | smart-8af46f9b-1abb-42ab-834a-41511f149547 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861890501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2861890501 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_stress_all.636994747 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 12389079369 ps |
CPU time | 13.72 seconds |
Started | Jul 10 05:51:36 PM PDT 24 |
Finished | Jul 10 05:51:51 PM PDT 24 |
Peak memory | 205524 kb |
Host | smart-3e3eb4c2-cb51-42f2-ae9d-163e4897f8fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636994747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.636994747 |
Directory | /workspace/29.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/41.rv_dm_stress_all.1972751789 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 8122024948 ps |
CPU time | 7.4 seconds |
Started | Jul 10 05:51:30 PM PDT 24 |
Finished | Jul 10 05:51:39 PM PDT 24 |
Peak memory | 213752 kb |
Host | smart-55711111-807f-46fb-bcd7-dd59000c3b75 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972751789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1972751789 |
Directory | /workspace/41.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1658031684 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 26049673160 ps |
CPU time | 77.43 seconds |
Started | Jul 10 05:51:05 PM PDT 24 |
Finished | Jul 10 05:52:27 PM PDT 24 |
Peak memory | 213928 kb |
Host | smart-7da6d42c-85e9-4cc7-9519-dccd9a5a43b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1658031684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1658031684 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3770058231 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 2846809199 ps |
CPU time | 2.07 seconds |
Started | Jul 10 05:51:11 PM PDT 24 |
Finished | Jul 10 05:51:17 PM PDT 24 |
Peak memory | 213876 kb |
Host | smart-0b6b7160-8aa6-4371-b7d8-1c015b9006e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770058231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3770058231 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3485886331 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 107761816 ps |
CPU time | 0.96 seconds |
Started | Jul 10 05:50:57 PM PDT 24 |
Finished | Jul 10 05:51:02 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-b1f37c69-bff6-47dd-aae9-188835eba92a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3485886331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3485886331 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_busy.276903606 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 3893046582 ps |
CPU time | 1.81 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:05 PM PDT 24 |
Peak memory | 205624 kb |
Host | smart-1bcae999-0017-42e7-bcf1-f8abcb398295 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=276903606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.276903606 |
Directory | /workspace/0.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.222764294 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 62076132321 ps |
CPU time | 54.9 seconds |
Started | Jul 10 05:05:18 PM PDT 24 |
Finished | Jul 10 05:06:15 PM PDT 24 |
Peak memory | 221472 kb |
Host | smart-fd68086e-d19a-4680-87ce-a7822da9a0c6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222764294 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.222764294 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.3016934936 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 1022739036 ps |
CPU time | 8.92 seconds |
Started | Jul 10 05:05:25 PM PDT 24 |
Finished | Jul 10 05:05:35 PM PDT 24 |
Peak memory | 213180 kb |
Host | smart-1fd55863-c06e-48c6-96fc-c009cb40262c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016934936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.3016934936 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.812295418 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 6552697296 ps |
CPU time | 6.93 seconds |
Started | Jul 10 05:50:53 PM PDT 24 |
Finished | Jul 10 05:51:02 PM PDT 24 |
Peak memory | 214084 kb |
Host | smart-2d2db1b9-38c6-4e59-8bd8-128a4d9cadfb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=812295418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.812295418 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1929280315 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 456180159 ps |
CPU time | 0.82 seconds |
Started | Jul 10 05:50:51 PM PDT 24 |
Finished | Jul 10 05:50:52 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-3fac22e9-66b8-4a0e-ab40-ef5c1f6f4769 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1929280315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1929280315 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.503855777 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 1121910281 ps |
CPU time | 2.27 seconds |
Started | Jul 10 05:51:03 PM PDT 24 |
Finished | Jul 10 05:51:11 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-6e727ce1-8772-4c30-8d0a-83e7424c9abe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=503855777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.503855777 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.744169085 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 609078340 ps |
CPU time | 1.04 seconds |
Started | Jul 10 05:51:01 PM PDT 24 |
Finished | Jul 10 05:51:08 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-b9851f8b-4e88-4a6b-b764-1eba44c9eb1b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744169085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.744169085 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.436239747 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 151864392 ps |
CPU time | 1.04 seconds |
Started | Jul 10 05:50:55 PM PDT 24 |
Finished | Jul 10 05:50:58 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-30069c45-47ba-4538-bc1a-dbb18585fe1c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436239747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.436239747 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2662304786 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 856401208 ps |
CPU time | 0.89 seconds |
Started | Jul 10 05:50:55 PM PDT 24 |
Finished | Jul 10 05:50:58 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-4a9ec81f-abaa-44cc-8e29-bf5dc3d0a52f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662304786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2662304786 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.307240311 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 1202371736 ps |
CPU time | 2.54 seconds |
Started | Jul 10 05:50:55 PM PDT 24 |
Finished | Jul 10 05:51:00 PM PDT 24 |
Peak memory | 205560 kb |
Host | smart-9f51cd0f-422d-45da-a7be-659acda46208 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=307240311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.307240311 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.3668139743 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 3531502275 ps |
CPU time | 5.77 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:09 PM PDT 24 |
Peak memory | 213888 kb |
Host | smart-c1e80aa3-628b-4960-bb1e-b3dcd5fe5b7d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3668139743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3668139743 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all.1304425279 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 10540111310 ps |
CPU time | 6.9 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:10 PM PDT 24 |
Peak memory | 213788 kb |
Host | smart-aa1d8b27-5924-4e37-8a45-20273905728c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304425279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.1304425279 |
Directory | /workspace/0.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3456848884 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 2273002320 ps |
CPU time | 2.23 seconds |
Started | Jul 10 05:50:57 PM PDT 24 |
Finished | Jul 10 05:51:04 PM PDT 24 |
Peak memory | 213812 kb |
Host | smart-29cb1d9f-019a-4c22-a016-83044c759b5d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456848884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3456848884 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.3681982021 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 1042935430 ps |
CPU time | 3.72 seconds |
Started | Jul 10 05:50:59 PM PDT 24 |
Finished | Jul 10 05:51:08 PM PDT 24 |
Peak memory | 205636 kb |
Host | smart-d1ee52a7-2216-4419-bfc4-7c1cc230f003 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3681982021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3681982021 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.3270607507 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 7574661124 ps |
CPU time | 10.89 seconds |
Started | Jul 10 05:51:12 PM PDT 24 |
Finished | Jul 10 05:51:26 PM PDT 24 |
Peak memory | 205548 kb |
Host | smart-8d691712-aa72-455f-b55a-2f08a1acbc8f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3270607507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3270607507 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2383097181 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 2080289092 ps |
CPU time | 2.39 seconds |
Started | Jul 10 05:51:26 PM PDT 24 |
Finished | Jul 10 05:51:30 PM PDT 24 |
Peak memory | 213780 kb |
Host | smart-4bf009ec-50d6-42bd-92f5-f7329713b516 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2383097181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_ tl_access.2383097181 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.275435817 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 2701049869 ps |
CPU time | 4.95 seconds |
Started | Jul 10 05:51:17 PM PDT 24 |
Finished | Jul 10 05:51:27 PM PDT 24 |
Peak memory | 213912 kb |
Host | smart-65a14024-0ddc-4415-b2e4-b6f3c669455b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275435817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.275435817 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.4204085382 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 13159201861 ps |
CPU time | 13.49 seconds |
Started | Jul 10 05:51:17 PM PDT 24 |
Finished | Jul 10 05:51:36 PM PDT 24 |
Peak memory | 213904 kb |
Host | smart-67852d31-609a-47d5-a02f-66780116908f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4204085382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.4204085382 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.2670663849 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 4552726815 ps |
CPU time | 12.47 seconds |
Started | Jul 10 05:51:03 PM PDT 24 |
Finished | Jul 10 05:51:20 PM PDT 24 |
Peak memory | 213800 kb |
Host | smart-84db989c-c867-4e18-9e36-3d5ed8250f05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670663849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2670663849 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.2560420813 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 4695461584 ps |
CPU time | 4.19 seconds |
Started | Jul 10 05:51:10 PM PDT 24 |
Finished | Jul 10 05:51:18 PM PDT 24 |
Peak memory | 213912 kb |
Host | smart-4650cd05-8528-4811-8c6c-4c1e926772f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560420813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2560420813 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.3387633806 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 1731473253 ps |
CPU time | 5.33 seconds |
Started | Jul 10 05:51:04 PM PDT 24 |
Finished | Jul 10 05:51:15 PM PDT 24 |
Peak memory | 205640 kb |
Host | smart-7c236f08-8d91-4185-a7c8-7924a466e989 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3387633806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3387633806 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.3531391537 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 1701628032 ps |
CPU time | 1.91 seconds |
Started | Jul 10 05:51:13 PM PDT 24 |
Finished | Jul 10 05:51:19 PM PDT 24 |
Peak memory | 213800 kb |
Host | smart-88a8f5b8-4392-4190-957c-2c6d0924a924 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3531391537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3531391537 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.2769368874 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 4265259578 ps |
CPU time | 32.72 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:06:06 PM PDT 24 |
Peak memory | 213244 kb |
Host | smart-0f112e7e-5c0f-4acb-ad82-ecfe0a958d9b |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769368874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.rv_dm_csr_aliasing.2769368874 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.3148594112 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 3942316635 ps |
CPU time | 36.28 seconds |
Started | Jul 10 05:05:16 PM PDT 24 |
Finished | Jul 10 05:05:53 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-c67abee0-0676-4d0e-97bc-f9c7130e2cc0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148594112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.3148594112 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3232295797 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 266819829 ps |
CPU time | 1.73 seconds |
Started | Jul 10 05:05:22 PM PDT 24 |
Finished | Jul 10 05:05:26 PM PDT 24 |
Peak memory | 213276 kb |
Host | smart-5b3ac6a2-5cef-46be-a79f-275a722dae3d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232295797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3232295797 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2029444673 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 273703323 ps |
CPU time | 4.12 seconds |
Started | Jul 10 05:05:19 PM PDT 24 |
Finished | Jul 10 05:05:25 PM PDT 24 |
Peak memory | 221684 kb |
Host | smart-b85499ac-20fc-4c69-b84c-bd3116050334 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029444673 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2029444673 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2221408317 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 119563182 ps |
CPU time | 1.56 seconds |
Started | Jul 10 05:05:19 PM PDT 24 |
Finished | Jul 10 05:05:23 PM PDT 24 |
Peak memory | 213196 kb |
Host | smart-983af1b5-cc1a-4eaa-b02f-e1f571d96454 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221408317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2221408317 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3236387472 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 32721788960 ps |
CPU time | 87.49 seconds |
Started | Jul 10 05:05:18 PM PDT 24 |
Finished | Jul 10 05:06:47 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-a4dc0ca8-e666-42ac-b07b-0467d1bd0b93 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236387472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.3236387472 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.784442460 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 1867625711 ps |
CPU time | 1.82 seconds |
Started | Jul 10 05:05:23 PM PDT 24 |
Finished | Jul 10 05:05:26 PM PDT 24 |
Peak memory | 204928 kb |
Host | smart-27778a86-ed35-4b20-b4f5-3406d6a80009 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784442460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r v_dm_jtag_dmi_csr_bit_bash.784442460 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1246851532 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 6057810773 ps |
CPU time | 4.7 seconds |
Started | Jul 10 05:05:28 PM PDT 24 |
Finished | Jul 10 05:05:39 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-f79bba09-91f3-45fe-8152-595da8bfc6e9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246851532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1 246851532 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4260539909 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 280310029 ps |
CPU time | 0.81 seconds |
Started | Jul 10 05:05:17 PM PDT 24 |
Finished | Jul 10 05:05:18 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-4b5ccf06-2374-4316-9063-23305029652c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260539909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.4260539909 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1214703249 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 462981871 ps |
CPU time | 0.95 seconds |
Started | Jul 10 05:05:21 PM PDT 24 |
Finished | Jul 10 05:05:24 PM PDT 24 |
Peak memory | 204756 kb |
Host | smart-406687d1-8e28-43b1-b4a4-5a6e5fcc3faa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214703249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.1214703249 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3529939812 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 413987553 ps |
CPU time | 1.74 seconds |
Started | Jul 10 05:05:19 PM PDT 24 |
Finished | Jul 10 05:05:23 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-d81656d9-9e83-424f-bd7b-92214ac21301 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529939812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3 529939812 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2969693637 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 67710234 ps |
CPU time | 0.71 seconds |
Started | Jul 10 05:05:17 PM PDT 24 |
Finished | Jul 10 05:05:19 PM PDT 24 |
Peak memory | 204596 kb |
Host | smart-93544f61-7ffd-4188-969b-beadfc4edcc3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969693637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par tial_access.2969693637 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.1798874973 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 30086979 ps |
CPU time | 0.71 seconds |
Started | Jul 10 05:05:22 PM PDT 24 |
Finished | Jul 10 05:05:25 PM PDT 24 |
Peak memory | 204736 kb |
Host | smart-4218b600-4d9a-478d-9ac6-d075648b8ba5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798874973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.1798874973 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.374911366 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 241781790 ps |
CPU time | 6.89 seconds |
Started | Jul 10 05:05:18 PM PDT 24 |
Finished | Jul 10 05:05:27 PM PDT 24 |
Peak memory | 204992 kb |
Host | smart-73430874-9051-4599-9fa1-2814f7294590 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374911366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c sr_outstanding.374911366 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.962139402 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 164073774 ps |
CPU time | 2.72 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:31 PM PDT 24 |
Peak memory | 213212 kb |
Host | smart-045d732c-e465-414b-aac5-5d220b1f4fad |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962139402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.962139402 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.37110912 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 718921143 ps |
CPU time | 8.88 seconds |
Started | Jul 10 05:05:19 PM PDT 24 |
Finished | Jul 10 05:05:29 PM PDT 24 |
Peak memory | 213216 kb |
Host | smart-236a60bd-43fb-4888-9b19-d75a49926c0e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37110912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.37110912 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3935771493 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 760352372 ps |
CPU time | 26.66 seconds |
Started | Jul 10 05:05:28 PM PDT 24 |
Finished | Jul 10 05:06:01 PM PDT 24 |
Peak memory | 214264 kb |
Host | smart-a5b58e0b-0654-4f3b-a62e-ae57bdc2d9d4 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935771493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.3935771493 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3888366019 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 1839276933 ps |
CPU time | 26.95 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:58 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-39902c45-981d-4b34-9631-7f3d23100158 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888366019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3888366019 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.220981311 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 360031327 ps |
CPU time | 3.06 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:32 PM PDT 24 |
Peak memory | 213344 kb |
Host | smart-0a50b5cc-8c4d-49d4-9c31-7cf96ce88ce6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220981311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.220981311 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2828491215 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 3625444493 ps |
CPU time | 7.31 seconds |
Started | Jul 10 05:05:25 PM PDT 24 |
Finished | Jul 10 05:05:35 PM PDT 24 |
Peak memory | 220140 kb |
Host | smart-f745db32-2c44-48ec-a58d-0c5156e5e3d6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828491215 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2828491215 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3713866825 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 194000017 ps |
CPU time | 2.36 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:33 PM PDT 24 |
Peak memory | 213140 kb |
Host | smart-fa932e8b-473f-4b30-9d67-a9f5277a4c45 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713866825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3713866825 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4095332515 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 30149166715 ps |
CPU time | 27.5 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:56 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-0dc19276-af0f-4f0e-b4fe-68ef60f50539 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095332515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_aliasing.4095332515 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1830170862 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 11422784101 ps |
CPU time | 16.37 seconds |
Started | Jul 10 05:05:29 PM PDT 24 |
Finished | Jul 10 05:05:51 PM PDT 24 |
Peak memory | 204504 kb |
Host | smart-b4ce6566-c2ed-405f-8ce6-533f53792f43 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830170862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.1830170862 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2118079411 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 13149884911 ps |
CPU time | 34.79 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:06:06 PM PDT 24 |
Peak memory | 205184 kb |
Host | smart-af97ec2c-0063-4dad-a20d-06384360e8bf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118079411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs r_hw_reset.2118079411 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1212174058 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 6183708386 ps |
CPU time | 14.99 seconds |
Started | Jul 10 05:05:25 PM PDT 24 |
Finished | Jul 10 05:05:41 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-c46b4f83-d7d5-410b-9b5b-e45edde2f10d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212174058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1 212174058 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1900270295 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 352031102 ps |
CPU time | 1.43 seconds |
Started | Jul 10 05:05:24 PM PDT 24 |
Finished | Jul 10 05:05:27 PM PDT 24 |
Peak memory | 204764 kb |
Host | smart-700b6052-3ca7-42c1-8b26-8abbdd5bd374 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900270295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_aliasing.1900270295 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2167788122 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 8023308505 ps |
CPU time | 22.26 seconds |
Started | Jul 10 05:05:20 PM PDT 24 |
Finished | Jul 10 05:05:44 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-aa8e4b8e-51f5-4ef2-a5e8-a57ee6b21aa3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167788122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_bit_bash.2167788122 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1322661910 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 295142888 ps |
CPU time | 1.01 seconds |
Started | Jul 10 05:05:23 PM PDT 24 |
Finished | Jul 10 05:05:26 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-b1c5fa5e-cb8f-4ae2-a408-f2340431f9ba |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322661910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs r_hw_reset.1322661910 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3545749076 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 664616652 ps |
CPU time | 1.14 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:30 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-2715dd88-291b-4975-bc31-dfab54c12356 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545749076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3 545749076 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4016252300 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 52481492 ps |
CPU time | 0.68 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:29 PM PDT 24 |
Peak memory | 204604 kb |
Host | smart-bd344042-e8fe-4a77-9d72-d49f02647e36 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016252300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.4016252300 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1831286258 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 81468671 ps |
CPU time | 0.68 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:31 PM PDT 24 |
Peak memory | 204636 kb |
Host | smart-ccb8f7bc-d815-4a4a-9a3c-6b290fe7411d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831286258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1831286258 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2764702667 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 2208508547 ps |
CPU time | 4.82 seconds |
Started | Jul 10 05:05:33 PM PDT 24 |
Finished | Jul 10 05:05:42 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-70d6d6d3-07d3-4e94-ac54-a5ad3e271d8a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764702667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_ csr_outstanding.2764702667 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.966794619 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 29691812935 ps |
CPU time | 29.21 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:06:00 PM PDT 24 |
Peak memory | 221124 kb |
Host | smart-f32906f7-bcde-48be-935f-5231a9906061 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966794619 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.966794619 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2986247053 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 531214100 ps |
CPU time | 5.22 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:05:38 PM PDT 24 |
Peak memory | 213204 kb |
Host | smart-4cb6b26f-7e72-4ef1-899c-2e823900bbfd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986247053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2986247053 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.347541686 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 3098422083 ps |
CPU time | 10.08 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:05:41 PM PDT 24 |
Peak memory | 213204 kb |
Host | smart-25552e78-c1fa-435c-b1d7-d75fc33e7eb1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347541686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.347541686 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3403259154 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 5977860653 ps |
CPU time | 8.4 seconds |
Started | Jul 10 05:05:48 PM PDT 24 |
Finished | Jul 10 05:05:58 PM PDT 24 |
Peak memory | 217052 kb |
Host | smart-caf4d97f-856a-429a-8089-4477877cd57f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403259154 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3403259154 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.172829480 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 78184453 ps |
CPU time | 1.53 seconds |
Started | Jul 10 05:05:52 PM PDT 24 |
Finished | Jul 10 05:05:55 PM PDT 24 |
Peak memory | 213232 kb |
Host | smart-c2f0d7f8-a80e-41f2-85ff-1ec2e4c02e70 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172829480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.172829480 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3168825100 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 5935676054 ps |
CPU time | 14.74 seconds |
Started | Jul 10 05:05:51 PM PDT 24 |
Finished | Jul 10 05:06:07 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-1a2ae655-6349-425f-aa25-87f2a817b368 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168825100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.3168825100 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.380968479 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 2812569019 ps |
CPU time | 3.67 seconds |
Started | Jul 10 05:05:52 PM PDT 24 |
Finished | Jul 10 05:05:57 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-6e3f12b8-81c2-4b53-a06b-665d14e87980 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380968479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.380968479 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2089700223 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 277082680 ps |
CPU time | 0.87 seconds |
Started | Jul 10 05:05:52 PM PDT 24 |
Finished | Jul 10 05:05:54 PM PDT 24 |
Peak memory | 204624 kb |
Host | smart-fb8240ee-b85d-430e-9812-350d6db944c0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089700223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 2089700223 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.620043358 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 468270159 ps |
CPU time | 7.13 seconds |
Started | Jul 10 05:05:52 PM PDT 24 |
Finished | Jul 10 05:06:00 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-610251a1-e8d2-42c3-a44e-87fd1fad3ca5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620043358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_ csr_outstanding.620043358 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.55974557 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 451948620 ps |
CPU time | 3.29 seconds |
Started | Jul 10 05:05:53 PM PDT 24 |
Finished | Jul 10 05:05:58 PM PDT 24 |
Peak memory | 213176 kb |
Host | smart-b25c4f16-ac00-4179-80ae-c80b6a03ee7c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55974557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.55974557 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3570571996 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 5590490966 ps |
CPU time | 21.15 seconds |
Started | Jul 10 05:05:52 PM PDT 24 |
Finished | Jul 10 05:06:15 PM PDT 24 |
Peak memory | 213292 kb |
Host | smart-8b97794f-53df-446b-af2b-221f5bc9288e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570571996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3 570571996 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1439390869 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 1053412841 ps |
CPU time | 3.82 seconds |
Started | Jul 10 05:06:04 PM PDT 24 |
Finished | Jul 10 05:06:11 PM PDT 24 |
Peak memory | 217196 kb |
Host | smart-80e82203-747e-494a-94ce-02a45d5b59f8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439390869 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1439390869 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.694970742 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 120541603 ps |
CPU time | 2.44 seconds |
Started | Jul 10 05:06:00 PM PDT 24 |
Finished | Jul 10 05:06:06 PM PDT 24 |
Peak memory | 213208 kb |
Host | smart-84c985a8-04dd-4c0e-ae0f-67c51afd8f19 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694970742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.694970742 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.4040370633 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 15485309770 ps |
CPU time | 20.82 seconds |
Started | Jul 10 05:06:02 PM PDT 24 |
Finished | Jul 10 05:06:26 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-561f0f91-503d-4897-9d9a-8e673e77d0ac |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040370633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .rv_dm_jtag_dmi_csr_bit_bash.4040370633 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4077747838 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 3767794687 ps |
CPU time | 5.19 seconds |
Started | Jul 10 05:06:00 PM PDT 24 |
Finished | Jul 10 05:06:08 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-5905d47d-18b6-46bb-b5ca-4b849210ebcb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077747838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 4077747838 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3023967501 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 986465866 ps |
CPU time | 1.36 seconds |
Started | Jul 10 05:06:01 PM PDT 24 |
Finished | Jul 10 05:06:06 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-dff769dd-20eb-4d1a-a5bf-e0283adc79bf |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023967501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw. 3023967501 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.4212286710 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 330954370 ps |
CPU time | 3.29 seconds |
Started | Jul 10 05:06:01 PM PDT 24 |
Finished | Jul 10 05:06:08 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-19b2d8bb-5518-4cf1-8067-dbca84e8ff79 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212286710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same _csr_outstanding.4212286710 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2702428815 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 922964086 ps |
CPU time | 4.92 seconds |
Started | Jul 10 05:06:01 PM PDT 24 |
Finished | Jul 10 05:06:09 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-5cc7911a-d69e-4cf8-8625-f65d02b6dc0c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702428815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2702428815 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.397301139 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 5432437540 ps |
CPU time | 29.01 seconds |
Started | Jul 10 05:06:00 PM PDT 24 |
Finished | Jul 10 05:06:32 PM PDT 24 |
Peak memory | 213220 kb |
Host | smart-d8ab64a6-f0af-4336-aaf2-81908082ca6c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397301139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.397301139 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1558470703 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 297210250 ps |
CPU time | 2.15 seconds |
Started | Jul 10 05:06:05 PM PDT 24 |
Finished | Jul 10 05:06:10 PM PDT 24 |
Peak memory | 213176 kb |
Host | smart-e55d277a-d5a4-487e-aa16-ba6e5e1fd46f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558470703 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1558470703 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3962399357 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 902305272 ps |
CPU time | 2.34 seconds |
Started | Jul 10 05:05:59 PM PDT 24 |
Finished | Jul 10 05:06:04 PM PDT 24 |
Peak memory | 213324 kb |
Host | smart-c8d9957b-10c9-4d8c-8e18-af66b13418e5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962399357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3962399357 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.891611290 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 1656104365 ps |
CPU time | 5.93 seconds |
Started | Jul 10 05:06:01 PM PDT 24 |
Finished | Jul 10 05:06:10 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-3a76ce3b-ddef-4615-8b75-8df83c9e8e33 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891611290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. rv_dm_jtag_dmi_csr_bit_bash.891611290 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3340237623 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 1456177203 ps |
CPU time | 4.74 seconds |
Started | Jul 10 05:06:04 PM PDT 24 |
Finished | Jul 10 05:06:12 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-fa475c19-833e-4b38-b233-d02579f22deb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340237623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 3340237623 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1324075831 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 373948308 ps |
CPU time | 0.91 seconds |
Started | Jul 10 05:06:02 PM PDT 24 |
Finished | Jul 10 05:06:06 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-be6289b4-da3b-42c7-a33b-a59e8c8f54d1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324075831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw. 1324075831 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3900675535 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 989639865 ps |
CPU time | 4.62 seconds |
Started | Jul 10 05:06:00 PM PDT 24 |
Finished | Jul 10 05:06:08 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-46d4370a-eddc-4145-b28a-59bd2eeb8e03 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900675535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.3900675535 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4183235271 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 306702492 ps |
CPU time | 4.77 seconds |
Started | Jul 10 05:05:59 PM PDT 24 |
Finished | Jul 10 05:06:05 PM PDT 24 |
Peak memory | 213240 kb |
Host | smart-b38a38ac-db9e-4672-a93b-8ebac38e6e3f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183235271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.4183235271 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3061606698 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 2228257233 ps |
CPU time | 10.59 seconds |
Started | Jul 10 05:06:01 PM PDT 24 |
Finished | Jul 10 05:06:15 PM PDT 24 |
Peak memory | 213276 kb |
Host | smart-359093f9-4a60-40d9-ac17-5af98ec62371 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061606698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3 061606698 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3235061918 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 214768199 ps |
CPU time | 3.91 seconds |
Started | Jul 10 05:06:05 PM PDT 24 |
Finished | Jul 10 05:06:12 PM PDT 24 |
Peak memory | 220920 kb |
Host | smart-4b1dcee6-1cfa-41fd-85c6-a83efc860c54 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235061918 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3235061918 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2093073965 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 207544362 ps |
CPU time | 2.49 seconds |
Started | Jul 10 05:06:01 PM PDT 24 |
Finished | Jul 10 05:06:07 PM PDT 24 |
Peak memory | 213224 kb |
Host | smart-d56df896-978f-4b6f-9e2a-e54521132650 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093073965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2093073965 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2598693797 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 75599476 ps |
CPU time | 0.8 seconds |
Started | Jul 10 05:05:59 PM PDT 24 |
Finished | Jul 10 05:06:03 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-1b243685-8c78-49ba-bd73-16dab4ff6c28 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598693797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.2598693797 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.772280484 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 5407574267 ps |
CPU time | 8.7 seconds |
Started | Jul 10 05:05:58 PM PDT 24 |
Finished | Jul 10 05:06:09 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-f1ad27ac-e636-49f1-b853-21683c0170d7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772280484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.772280484 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3071769994 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 675961910 ps |
CPU time | 1.21 seconds |
Started | Jul 10 05:06:05 PM PDT 24 |
Finished | Jul 10 05:06:09 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-95ff2622-7c9c-4dea-83c6-14fa2f31bb93 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071769994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 3071769994 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2466244218 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 364814581 ps |
CPU time | 5.21 seconds |
Started | Jul 10 05:06:01 PM PDT 24 |
Finished | Jul 10 05:06:09 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-84907d92-48af-409e-8ddd-335cc1ed6982 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466244218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2466244218 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1960123351 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 350890275 ps |
CPU time | 3.16 seconds |
Started | Jul 10 05:05:59 PM PDT 24 |
Finished | Jul 10 05:06:04 PM PDT 24 |
Peak memory | 221484 kb |
Host | smart-98558744-6edb-4af6-a922-c863552b429d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960123351 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1960123351 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3406456687 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 338909980 ps |
CPU time | 2.14 seconds |
Started | Jul 10 05:05:59 PM PDT 24 |
Finished | Jul 10 05:06:03 PM PDT 24 |
Peak memory | 213164 kb |
Host | smart-5d684844-28a5-4455-b667-ee570192727d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406456687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3406456687 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3063017435 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 13969452476 ps |
CPU time | 10.94 seconds |
Started | Jul 10 05:06:02 PM PDT 24 |
Finished | Jul 10 05:06:16 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-3da31959-ca84-4213-b08f-498455bd47f4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063017435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .rv_dm_jtag_dmi_csr_bit_bash.3063017435 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3992055649 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 3865961359 ps |
CPU time | 10.29 seconds |
Started | Jul 10 05:06:00 PM PDT 24 |
Finished | Jul 10 05:06:12 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-6a0ba5c0-31e5-47ca-acbd-139fa9199118 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992055649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 3992055649 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.4103294817 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 80767914 ps |
CPU time | 0.87 seconds |
Started | Jul 10 05:05:59 PM PDT 24 |
Finished | Jul 10 05:06:02 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-a42f94e3-d4d2-435f-b13c-e2af0cfea19e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103294817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 4103294817 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.698327762 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 1749006313 ps |
CPU time | 7.84 seconds |
Started | Jul 10 05:06:03 PM PDT 24 |
Finished | Jul 10 05:06:14 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-e9bb1a40-d25d-4c02-a77e-d7a6b2fbfc5d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698327762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_ csr_outstanding.698327762 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1723862142 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 274498112 ps |
CPU time | 3.22 seconds |
Started | Jul 10 05:06:04 PM PDT 24 |
Finished | Jul 10 05:06:11 PM PDT 24 |
Peak memory | 213240 kb |
Host | smart-138e98ce-d95e-40f1-b406-6e668cdf51d4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723862142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1723862142 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2415629640 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 756031069 ps |
CPU time | 8.48 seconds |
Started | Jul 10 05:06:03 PM PDT 24 |
Finished | Jul 10 05:06:15 PM PDT 24 |
Peak memory | 213152 kb |
Host | smart-7d7a9ed5-3fbd-411e-ad07-8d5f39b922f9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415629640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2 415629640 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3148644896 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 377853190 ps |
CPU time | 2.69 seconds |
Started | Jul 10 05:06:10 PM PDT 24 |
Finished | Jul 10 05:06:18 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-d8e803e8-27fe-4328-a22c-a0308e2bf1db |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148644896 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3148644896 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1764108816 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 942094290 ps |
CPU time | 2.5 seconds |
Started | Jul 10 05:06:08 PM PDT 24 |
Finished | Jul 10 05:06:15 PM PDT 24 |
Peak memory | 213172 kb |
Host | smart-5ab853d7-16f8-4ef8-bc30-c62f8e69dcc4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764108816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1764108816 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3229998247 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 35637592281 ps |
CPU time | 27.54 seconds |
Started | Jul 10 05:06:05 PM PDT 24 |
Finished | Jul 10 05:06:35 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-f3e7edbe-c5c7-401c-9dfa-f7739bdc2975 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229998247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.3229998247 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3050850473 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 2092127017 ps |
CPU time | 2.56 seconds |
Started | Jul 10 05:06:03 PM PDT 24 |
Finished | Jul 10 05:06:09 PM PDT 24 |
Peak memory | 204824 kb |
Host | smart-33535ef4-1d4c-4a1f-b155-3b97ecece880 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050850473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw. 3050850473 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1005719539 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 178643613 ps |
CPU time | 1.2 seconds |
Started | Jul 10 05:06:03 PM PDT 24 |
Finished | Jul 10 05:06:07 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-9552846f-904b-4c38-91ae-fd5caeca425b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005719539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 1005719539 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1553950218 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 536259153 ps |
CPU time | 3.74 seconds |
Started | Jul 10 05:06:06 PM PDT 24 |
Finished | Jul 10 05:06:12 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-e4682047-ed12-4fcb-8e20-c232b29ae320 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553950218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same _csr_outstanding.1553950218 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2543374330 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 295501176 ps |
CPU time | 5.03 seconds |
Started | Jul 10 05:06:00 PM PDT 24 |
Finished | Jul 10 05:06:09 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-25f7cbbd-3ad9-4a6a-8f7f-0875f740fd4b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543374330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2543374330 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2699340291 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 2568826966 ps |
CPU time | 10.87 seconds |
Started | Jul 10 05:06:08 PM PDT 24 |
Finished | Jul 10 05:06:22 PM PDT 24 |
Peak memory | 221392 kb |
Host | smart-f0c265a3-d132-4b9e-907c-550fda53107f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699340291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2 699340291 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3270443320 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 3123830773 ps |
CPU time | 6.18 seconds |
Started | Jul 10 05:06:14 PM PDT 24 |
Finished | Jul 10 05:06:26 PM PDT 24 |
Peak memory | 221336 kb |
Host | smart-d4a46b65-a16d-4819-b15e-a857d72e1d52 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270443320 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3270443320 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1640231341 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 184506432 ps |
CPU time | 1.65 seconds |
Started | Jul 10 05:06:08 PM PDT 24 |
Finished | Jul 10 05:06:13 PM PDT 24 |
Peak memory | 213148 kb |
Host | smart-1afb9fd9-fcad-473c-baa3-df6b56a79c2f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640231341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1640231341 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2955800245 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 29355216913 ps |
CPU time | 79.37 seconds |
Started | Jul 10 05:06:09 PM PDT 24 |
Finished | Jul 10 05:07:34 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-6fdeccdd-84ce-493d-bf2d-e5ea4f458122 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955800245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .rv_dm_jtag_dmi_csr_bit_bash.2955800245 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3023748528 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 6481621242 ps |
CPU time | 5.02 seconds |
Started | Jul 10 05:06:06 PM PDT 24 |
Finished | Jul 10 05:06:14 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-05adea6d-e726-4b05-aeae-3571c347e8d0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023748528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw. 3023748528 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4029781016 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 639725549 ps |
CPU time | 2.2 seconds |
Started | Jul 10 05:06:10 PM PDT 24 |
Finished | Jul 10 05:06:18 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-5cf726b5-4a44-42ba-a8d0-74bd0a79f4e8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029781016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 4029781016 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2595454765 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 382716318 ps |
CPU time | 3.56 seconds |
Started | Jul 10 05:06:09 PM PDT 24 |
Finished | Jul 10 05:06:17 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-ea151402-e8d6-4bd4-b65a-f454e1bd1b09 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595454765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.2595454765 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3938612904 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 2517401066 ps |
CPU time | 6.5 seconds |
Started | Jul 10 05:06:10 PM PDT 24 |
Finished | Jul 10 05:06:21 PM PDT 24 |
Peak memory | 213500 kb |
Host | smart-b895591a-ebd6-43a0-99f3-911f83fc062e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938612904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3938612904 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2461626937 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 1387451560 ps |
CPU time | 9.2 seconds |
Started | Jul 10 05:06:08 PM PDT 24 |
Finished | Jul 10 05:06:21 PM PDT 24 |
Peak memory | 213220 kb |
Host | smart-1f311d37-d8fe-43c7-b108-9b62fc7a6047 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461626937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2 461626937 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.888016948 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 464248338 ps |
CPU time | 4.64 seconds |
Started | Jul 10 05:06:10 PM PDT 24 |
Finished | Jul 10 05:06:20 PM PDT 24 |
Peak memory | 221448 kb |
Host | smart-d02ff010-7a0d-4fb4-a182-79fafcf82f3d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888016948 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.888016948 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2410944873 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 259151435 ps |
CPU time | 2.46 seconds |
Started | Jul 10 05:06:08 PM PDT 24 |
Finished | Jul 10 05:06:14 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-0410304c-c73f-44ec-922d-925df7bd030c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410944873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2410944873 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.3573869620 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 68297091245 ps |
CPU time | 150.4 seconds |
Started | Jul 10 05:06:09 PM PDT 24 |
Finished | Jul 10 05:08:44 PM PDT 24 |
Peak memory | 204920 kb |
Host | smart-84b9709e-2b7e-44bc-a756-81c26429c157 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573869620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.3573869620 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.4079500533 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 13290354078 ps |
CPU time | 26.52 seconds |
Started | Jul 10 05:06:10 PM PDT 24 |
Finished | Jul 10 05:06:43 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-e8b27eba-a82e-43bc-b5d2-6269e9c87c4e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079500533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 4079500533 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.1165167060 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 221904832 ps |
CPU time | 0.95 seconds |
Started | Jul 10 05:06:12 PM PDT 24 |
Finished | Jul 10 05:06:18 PM PDT 24 |
Peak memory | 204656 kb |
Host | smart-0cd69e3f-603c-477f-bc6c-b664be000fbc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165167060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 1165167060 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4213110070 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 310808732 ps |
CPU time | 4.6 seconds |
Started | Jul 10 05:06:08 PM PDT 24 |
Finished | Jul 10 05:06:17 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-87d0daa3-fa5b-422d-a719-3980d0b19ccf |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213110070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.4213110070 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2791661593 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 259485566 ps |
CPU time | 2.5 seconds |
Started | Jul 10 05:06:08 PM PDT 24 |
Finished | Jul 10 05:06:15 PM PDT 24 |
Peak memory | 221416 kb |
Host | smart-0df0b29d-a1c0-439b-b97b-9313dfabd186 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791661593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2791661593 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3129619164 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 761962582 ps |
CPU time | 9 seconds |
Started | Jul 10 05:06:09 PM PDT 24 |
Finished | Jul 10 05:06:24 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-3ec14c10-3ba8-4108-8da4-0e1589f69dfe |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129619164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3 129619164 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2587030182 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 2138513375 ps |
CPU time | 3.52 seconds |
Started | Jul 10 05:06:10 PM PDT 24 |
Finished | Jul 10 05:06:18 PM PDT 24 |
Peak memory | 213188 kb |
Host | smart-35b4da7c-47b4-4f5d-87ab-d18625b3bcd1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587030182 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2587030182 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3121284919 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 68359195 ps |
CPU time | 1.53 seconds |
Started | Jul 10 05:06:08 PM PDT 24 |
Finished | Jul 10 05:06:14 PM PDT 24 |
Peak memory | 213148 kb |
Host | smart-f847abe3-3d0f-47ea-a2fd-765dd284ae43 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121284919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3121284919 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2450473907 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 46292006522 ps |
CPU time | 15.39 seconds |
Started | Jul 10 05:06:08 PM PDT 24 |
Finished | Jul 10 05:06:28 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-31a1ae31-3d7b-418c-b565-8ab4d1fe13b2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450473907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.2450473907 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3380815433 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 2772201727 ps |
CPU time | 8.69 seconds |
Started | Jul 10 05:06:07 PM PDT 24 |
Finished | Jul 10 05:06:18 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-bdf87144-82c7-48e5-a4eb-7ff9ae28be09 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380815433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 3380815433 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4228071677 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 140792031 ps |
CPU time | 0.74 seconds |
Started | Jul 10 05:06:08 PM PDT 24 |
Finished | Jul 10 05:06:12 PM PDT 24 |
Peak memory | 204652 kb |
Host | smart-752d68fc-d020-48d2-9c67-9400168638ce |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228071677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 4228071677 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3440649836 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 1729516821 ps |
CPU time | 7.96 seconds |
Started | Jul 10 05:06:09 PM PDT 24 |
Finished | Jul 10 05:06:21 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-75ce50c7-96f9-43ac-b777-39a485497050 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440649836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.3440649836 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1314170514 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 621431147 ps |
CPU time | 2.52 seconds |
Started | Jul 10 05:06:07 PM PDT 24 |
Finished | Jul 10 05:06:14 PM PDT 24 |
Peak memory | 213232 kb |
Host | smart-98913ac7-c945-46f5-8961-7a89d2d078ca |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314170514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1314170514 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.540546122 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 608611818 ps |
CPU time | 8.57 seconds |
Started | Jul 10 05:06:10 PM PDT 24 |
Finished | Jul 10 05:06:24 PM PDT 24 |
Peak memory | 213168 kb |
Host | smart-e70106be-9d0f-4272-be90-ba354925ba02 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540546122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.540546122 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1107149854 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 161897041 ps |
CPU time | 2.29 seconds |
Started | Jul 10 05:06:11 PM PDT 24 |
Finished | Jul 10 05:06:20 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-7a3e468f-ea50-4011-beca-fc584483ea50 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107149854 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1107149854 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3919785408 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 93633257 ps |
CPU time | 1.44 seconds |
Started | Jul 10 05:06:08 PM PDT 24 |
Finished | Jul 10 05:06:13 PM PDT 24 |
Peak memory | 213084 kb |
Host | smart-badad758-d544-4b51-8048-ac915253e3af |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919785408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3919785408 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1277671433 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 26843465812 ps |
CPU time | 38.92 seconds |
Started | Jul 10 05:06:13 PM PDT 24 |
Finished | Jul 10 05:06:58 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-684e36f0-d6f2-4b14-8445-0d50966ec134 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277671433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .rv_dm_jtag_dmi_csr_bit_bash.1277671433 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1682748970 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 2509449210 ps |
CPU time | 6.6 seconds |
Started | Jul 10 05:06:09 PM PDT 24 |
Finished | Jul 10 05:06:20 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-7f72f75c-391a-4e85-84e8-5b302877c425 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682748970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw. 1682748970 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3603099353 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 197246378 ps |
CPU time | 1.13 seconds |
Started | Jul 10 05:06:11 PM PDT 24 |
Finished | Jul 10 05:06:18 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-858298fa-f54b-4ee9-8043-a6e3264ad193 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603099353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw. 3603099353 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2141264436 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 640714100 ps |
CPU time | 7.95 seconds |
Started | Jul 10 05:06:11 PM PDT 24 |
Finished | Jul 10 05:06:25 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-5b7402ac-4654-492d-9630-e8c90e9819c7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141264436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.2141264436 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.95865710 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 129154232 ps |
CPU time | 2.75 seconds |
Started | Jul 10 05:06:07 PM PDT 24 |
Finished | Jul 10 05:06:12 PM PDT 24 |
Peak memory | 213308 kb |
Host | smart-e501c008-7ed7-4f9f-afea-104cbb18915f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95865710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.95865710 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3244045567 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 1178462343 ps |
CPU time | 11.19 seconds |
Started | Jul 10 05:06:10 PM PDT 24 |
Finished | Jul 10 05:06:27 PM PDT 24 |
Peak memory | 213168 kb |
Host | smart-8000df15-5d23-4379-8cc4-073ff00adabd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244045567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3 244045567 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.18152074 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 14666642167 ps |
CPU time | 78.45 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:06:49 PM PDT 24 |
Peak memory | 213204 kb |
Host | smart-61285a06-bddb-4fa8-993c-6b80ada236cb |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18152074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.rv_dm_csr_aliasing.18152074 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2766084397 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 15003314682 ps |
CPU time | 72.29 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:06:42 PM PDT 24 |
Peak memory | 205152 kb |
Host | smart-9887df40-aea3-4327-a564-4bfaeb9939a1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766084397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2766084397 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1719721978 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 280768840 ps |
CPU time | 1.81 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:05:35 PM PDT 24 |
Peak memory | 213108 kb |
Host | smart-2690b1c5-8542-40f9-8474-be7e0646381e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719721978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1719721978 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.958065203 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 235781458 ps |
CPU time | 2.13 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:33 PM PDT 24 |
Peak memory | 214308 kb |
Host | smart-1bb1c500-50ed-4bad-abf1-4b31b01db13e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958065203 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.958065203 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2140518581 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 301292655 ps |
CPU time | 1.65 seconds |
Started | Jul 10 05:05:28 PM PDT 24 |
Finished | Jul 10 05:05:35 PM PDT 24 |
Peak memory | 213160 kb |
Host | smart-6439bdf9-0848-4f67-891e-1ca64c181cb2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140518581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2140518581 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.219958826 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 37278167241 ps |
CPU time | 56.41 seconds |
Started | Jul 10 05:05:29 PM PDT 24 |
Finished | Jul 10 05:06:31 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-5d56881a-2df3-4ab4-8bff-d6f0b9a01958 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219958826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr _aliasing.219958826 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1135128282 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 11049652868 ps |
CPU time | 11.35 seconds |
Started | Jul 10 05:05:24 PM PDT 24 |
Finished | Jul 10 05:05:37 PM PDT 24 |
Peak memory | 205116 kb |
Host | smart-d97fb8b2-7a7a-4eee-bba1-0205893b8638 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135128282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. rv_dm_jtag_dmi_csr_bit_bash.1135128282 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1704710390 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 2908205617 ps |
CPU time | 7.76 seconds |
Started | Jul 10 05:05:28 PM PDT 24 |
Finished | Jul 10 05:05:42 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-b17caed1-bcf7-4d5f-958c-21ffc4d8af7c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704710390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.1704710390 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3326673602 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 2632202062 ps |
CPU time | 4.35 seconds |
Started | Jul 10 05:05:29 PM PDT 24 |
Finished | Jul 10 05:05:38 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-be757591-c70a-42dc-af2c-11884cb5aa86 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326673602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3 326673602 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1720161784 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 1942624253 ps |
CPU time | 1.87 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:05:34 PM PDT 24 |
Peak memory | 204632 kb |
Host | smart-de34c31f-9241-4b08-8978-fd0ff840cca0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720161784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.1720161784 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.490094611 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 21607374008 ps |
CPU time | 7.49 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:05:39 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-7affc46d-0613-4c1a-8d51-de5b74593a60 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490094611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _bit_bash.490094611 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.376118600 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 468136969 ps |
CPU time | 1.24 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:31 PM PDT 24 |
Peak memory | 204648 kb |
Host | smart-738065a8-945e-433e-94ae-598e3e4902e1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376118600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr _hw_reset.376118600 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2311544069 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 650208505 ps |
CPU time | 1.39 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:32 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-8d8e9903-233f-433b-acb2-7d778132554a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311544069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2 311544069 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2771546796 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 38133518 ps |
CPU time | 0.75 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:05:33 PM PDT 24 |
Peak memory | 204592 kb |
Host | smart-a80c3f72-4ede-460f-b807-2a159c4485a9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771546796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.2771546796 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1514971137 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 93786142 ps |
CPU time | 0.68 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:29 PM PDT 24 |
Peak memory | 204676 kb |
Host | smart-8a983410-be91-4f35-8505-a50b53ce6465 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514971137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1514971137 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.327091797 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 88006129 ps |
CPU time | 3.36 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:34 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-b65e4d20-c51a-4cbf-8e1a-b0b9826d8bb9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327091797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c sr_outstanding.327091797 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.276978231 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 616798370 ps |
CPU time | 4.34 seconds |
Started | Jul 10 05:05:25 PM PDT 24 |
Finished | Jul 10 05:05:32 PM PDT 24 |
Peak memory | 213144 kb |
Host | smart-a76c0fc1-5bc7-4689-9f9d-2f45bb2eb855 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276978231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.276978231 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1201497706 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 8436491081 ps |
CPU time | 33.38 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:06:05 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-fff75cc2-0d45-4e37-a435-5bfc611c85a0 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201497706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 3.rv_dm_csr_aliasing.1201497706 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3092340446 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 1965010973 ps |
CPU time | 57.1 seconds |
Started | Jul 10 05:05:29 PM PDT 24 |
Finished | Jul 10 05:06:31 PM PDT 24 |
Peak memory | 204980 kb |
Host | smart-44df5da5-3166-4daf-9fed-27788e42211c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092340446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3092340446 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.4047144084 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 112162694 ps |
CPU time | 1.79 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:05:34 PM PDT 24 |
Peak memory | 213184 kb |
Host | smart-99b6c7f8-b8b6-4c17-bd17-b7cff2727311 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047144084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.4047144084 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2135237260 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 3389080944 ps |
CPU time | 7.56 seconds |
Started | Jul 10 05:05:28 PM PDT 24 |
Finished | Jul 10 05:05:42 PM PDT 24 |
Peak memory | 217796 kb |
Host | smart-390a86ef-f6b0-48a7-bbf7-ab645c258492 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135237260 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2135237260 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1159853445 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 130655229 ps |
CPU time | 1.62 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:05:34 PM PDT 24 |
Peak memory | 213192 kb |
Host | smart-cfb5c9c0-4099-4452-8814-d312937a6a76 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159853445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1159853445 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3748862865 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 31168433001 ps |
CPU time | 47.71 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:06:21 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-7291c9b1-eb7b-408e-8dea-573164d4d89f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748862865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.3748862865 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.998598124 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 9617152154 ps |
CPU time | 7.98 seconds |
Started | Jul 10 05:05:31 PM PDT 24 |
Finished | Jul 10 05:05:44 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-e57e71cf-1663-45be-bcbd-ecbb14ef14be |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998598124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r v_dm_jtag_dmi_csr_bit_bash.998598124 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1040487038 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 15413413242 ps |
CPU time | 17.67 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:46 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-ff7d6a0a-4b72-4ebc-9f47-a8ffbe057ac2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040487038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.1040487038 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.917646713 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 845176845 ps |
CPU time | 1.21 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:31 PM PDT 24 |
Peak memory | 204836 kb |
Host | smart-48f896bc-4048-4d3c-883a-0f174b2e4d75 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917646713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.917646713 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.548478674 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 501862910 ps |
CPU time | 1.34 seconds |
Started | Jul 10 05:05:29 PM PDT 24 |
Finished | Jul 10 05:05:36 PM PDT 24 |
Peak memory | 204428 kb |
Host | smart-d0ef6746-65d2-421a-ac05-5ed99be0f8a1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548478674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _aliasing.548478674 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1180350276 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 16390352137 ps |
CPU time | 18.07 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:05:50 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-99ce98b2-e0c9-4da6-9812-68b7fb134ea8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180350276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.1180350276 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4002296299 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 468817883 ps |
CPU time | 1.28 seconds |
Started | Jul 10 05:05:28 PM PDT 24 |
Finished | Jul 10 05:05:35 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-5bdd2967-993e-42ce-afcf-e2174bdeaa14 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002296299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_hw_reset.4002296299 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2143657383 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 310422218 ps |
CPU time | 1.51 seconds |
Started | Jul 10 05:05:28 PM PDT 24 |
Finished | Jul 10 05:05:35 PM PDT 24 |
Peak memory | 204740 kb |
Host | smart-41b2e8a0-d641-475b-8922-6f42542f34fc |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143657383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2 143657383 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2811056440 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 93361362 ps |
CPU time | 0.76 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:05:33 PM PDT 24 |
Peak memory | 204572 kb |
Host | smart-4937aee8-ca13-4e2b-97d7-5846d1d06116 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811056440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.2811056440 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3943305864 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 55888705 ps |
CPU time | 0.73 seconds |
Started | Jul 10 05:05:28 PM PDT 24 |
Finished | Jul 10 05:05:34 PM PDT 24 |
Peak memory | 204656 kb |
Host | smart-53150be8-9091-48a9-83b4-903aac3964a4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943305864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3943305864 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1044487017 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 472196106 ps |
CPU time | 7.87 seconds |
Started | Jul 10 05:05:28 PM PDT 24 |
Finished | Jul 10 05:05:42 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-3d6c908f-1eaf-474d-9e29-9b131a038604 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044487017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.1044487017 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2482266210 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 27962352770 ps |
CPU time | 84.83 seconds |
Started | Jul 10 05:05:24 PM PDT 24 |
Finished | Jul 10 05:06:50 PM PDT 24 |
Peak memory | 221468 kb |
Host | smart-aa0c5da0-2b08-4867-8bc0-96fa458a0c7e |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482266210 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2482266210 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3524710348 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 639050421 ps |
CPU time | 3.55 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:32 PM PDT 24 |
Peak memory | 213212 kb |
Host | smart-1530e0ce-3cb6-4087-9840-6033eb9b27db |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524710348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3524710348 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2210768923 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 4438997452 ps |
CPU time | 21.01 seconds |
Started | Jul 10 05:05:26 PM PDT 24 |
Finished | Jul 10 05:05:52 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-e11e0545-ab30-4199-aafb-96970d350531 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210768923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2210768923 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2002208411 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 10220699459 ps |
CPU time | 67.69 seconds |
Started | Jul 10 05:05:32 PM PDT 24 |
Finished | Jul 10 05:06:44 PM PDT 24 |
Peak memory | 213348 kb |
Host | smart-fc3176e3-0c64-4e61-954f-4a470711612b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002208411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2002208411 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.945062237 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 494155845 ps |
CPU time | 2.54 seconds |
Started | Jul 10 05:05:35 PM PDT 24 |
Finished | Jul 10 05:05:40 PM PDT 24 |
Peak memory | 214240 kb |
Host | smart-87e50690-7845-478e-97b9-51f22a94f611 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945062237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.945062237 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.454850015 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 5681659948 ps |
CPU time | 12.77 seconds |
Started | Jul 10 05:05:35 PM PDT 24 |
Finished | Jul 10 05:05:51 PM PDT 24 |
Peak memory | 213296 kb |
Host | smart-da19bac1-fc49-431f-a11f-e26142521c4f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454850015 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.454850015 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.159256416 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 44870635278 ps |
CPU time | 80.35 seconds |
Started | Jul 10 05:05:32 PM PDT 24 |
Finished | Jul 10 05:06:57 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-355feb5b-561a-48aa-944d-55c5863c2060 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159256416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr _aliasing.159256416 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.67274236 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 27319964534 ps |
CPU time | 64.59 seconds |
Started | Jul 10 05:05:30 PM PDT 24 |
Finished | Jul 10 05:06:40 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-ae18a27e-1970-4604-9d6d-7bfd525d9ea1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67274236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv _dm_jtag_dmi_csr_bit_bash.67274236 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2654854265 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 3675572723 ps |
CPU time | 2.91 seconds |
Started | Jul 10 05:05:30 PM PDT 24 |
Finished | Jul 10 05:05:38 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-4c410ca1-1324-4a40-a890-c60e1addd428 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654854265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.2654854265 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.6915878 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 2975351521 ps |
CPU time | 7.65 seconds |
Started | Jul 10 05:05:29 PM PDT 24 |
Finished | Jul 10 05:05:42 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-b4d94e4d-f7ed-4d69-8841-f0e3b40ec0c1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6915878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.6915878 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.496989571 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 2293552898 ps |
CPU time | 3.76 seconds |
Started | Jul 10 05:05:24 PM PDT 24 |
Finished | Jul 10 05:05:29 PM PDT 24 |
Peak memory | 204712 kb |
Host | smart-2de79c78-d3a2-4394-ad6d-4b7fb0969d65 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496989571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _aliasing.496989571 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.135804597 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 5434022561 ps |
CPU time | 9.2 seconds |
Started | Jul 10 05:05:28 PM PDT 24 |
Finished | Jul 10 05:05:43 PM PDT 24 |
Peak memory | 205164 kb |
Host | smart-b916754b-9ad5-484f-9ce4-72cb720d6aaa |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135804597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _bit_bash.135804597 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.794601992 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 173050241 ps |
CPU time | 1.1 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:05:32 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-e96f3296-8b14-4968-896e-fc9240428489 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794601992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr _hw_reset.794601992 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1346590789 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 232054880 ps |
CPU time | 0.95 seconds |
Started | Jul 10 05:05:27 PM PDT 24 |
Finished | Jul 10 05:05:33 PM PDT 24 |
Peak memory | 204648 kb |
Host | smart-5f16ef87-5140-4036-9cf8-0d35c3ae3eb6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346590789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1 346590789 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3541737210 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 196567477 ps |
CPU time | 0.72 seconds |
Started | Jul 10 05:05:34 PM PDT 24 |
Finished | Jul 10 05:05:38 PM PDT 24 |
Peak memory | 204668 kb |
Host | smart-0add7197-7874-45be-921a-319bcec9820e |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541737210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.3541737210 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3798680264 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 61161633 ps |
CPU time | 0.78 seconds |
Started | Jul 10 05:05:39 PM PDT 24 |
Finished | Jul 10 05:05:41 PM PDT 24 |
Peak memory | 204656 kb |
Host | smart-3114cd7a-d88a-48ad-9831-152f12a0bf0d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798680264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3798680264 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.312218662 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 498346772 ps |
CPU time | 4.18 seconds |
Started | Jul 10 05:05:33 PM PDT 24 |
Finished | Jul 10 05:05:41 PM PDT 24 |
Peak memory | 204860 kb |
Host | smart-d7f463f9-b78d-410f-9460-cedc7295f52e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312218662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c sr_outstanding.312218662 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.691889788 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 23907181084 ps |
CPU time | 60.49 seconds |
Started | Jul 10 05:05:32 PM PDT 24 |
Finished | Jul 10 05:06:37 PM PDT 24 |
Peak memory | 219452 kb |
Host | smart-dc906103-991b-48af-bfb5-dad7638d183f |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691889788 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.691889788 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2604385413 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 199906995 ps |
CPU time | 2.57 seconds |
Started | Jul 10 05:05:31 PM PDT 24 |
Finished | Jul 10 05:05:38 PM PDT 24 |
Peak memory | 213240 kb |
Host | smart-59267f58-9ae3-409e-83ad-9d0a018ace44 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604385413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2604385413 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2526624561 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 4323473039 ps |
CPU time | 18.56 seconds |
Started | Jul 10 05:05:35 PM PDT 24 |
Finished | Jul 10 05:05:57 PM PDT 24 |
Peak memory | 213224 kb |
Host | smart-fd9fd6bf-636b-4cc5-b793-9987f59c079c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526624561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2526624561 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1467277466 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 235387925 ps |
CPU time | 2.5 seconds |
Started | Jul 10 05:05:40 PM PDT 24 |
Finished | Jul 10 05:05:44 PM PDT 24 |
Peak memory | 218444 kb |
Host | smart-8d4bb32f-9b01-463e-82aa-3bf4c4c39fc5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467277466 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1467277466 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3876110141 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 323241413 ps |
CPU time | 2.4 seconds |
Started | Jul 10 05:05:33 PM PDT 24 |
Finished | Jul 10 05:05:39 PM PDT 24 |
Peak memory | 213176 kb |
Host | smart-8b70fc57-3bf0-4ccf-83e3-7f628951b4f6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876110141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3876110141 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3212022385 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 13533329852 ps |
CPU time | 38.57 seconds |
Started | Jul 10 05:05:40 PM PDT 24 |
Finished | Jul 10 05:06:20 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-500fed28-7dee-43d9-90e2-3d99667ac479 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212022385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. rv_dm_jtag_dmi_csr_bit_bash.3212022385 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.949663850 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 3117772590 ps |
CPU time | 3.19 seconds |
Started | Jul 10 05:05:34 PM PDT 24 |
Finished | Jul 10 05:05:41 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-97a0a0ec-2b62-4be1-a8b6-e5ccfac71bd7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949663850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.949663850 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1284965072 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 187138710 ps |
CPU time | 0.78 seconds |
Started | Jul 10 05:05:34 PM PDT 24 |
Finished | Jul 10 05:05:38 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-d2b41e8a-c33c-4211-ad51-7ce993beb8e1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284965072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1 284965072 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1776608850 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 475254921 ps |
CPU time | 4.48 seconds |
Started | Jul 10 05:05:34 PM PDT 24 |
Finished | Jul 10 05:05:42 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-770596a6-f300-4f59-86f7-cbf4511a3b11 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776608850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_ csr_outstanding.1776608850 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2022946110 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 212159119 ps |
CPU time | 2.96 seconds |
Started | Jul 10 05:05:33 PM PDT 24 |
Finished | Jul 10 05:05:40 PM PDT 24 |
Peak memory | 213244 kb |
Host | smart-5b0018df-31d7-4e4a-8416-cec014efc177 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022946110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2022946110 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1381515192 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 5859427775 ps |
CPU time | 24.14 seconds |
Started | Jul 10 05:05:40 PM PDT 24 |
Finished | Jul 10 05:06:05 PM PDT 24 |
Peak memory | 213268 kb |
Host | smart-1c176e36-b159-4f01-924a-55fd7c12ffa4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381515192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1381515192 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2634038919 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 96541680 ps |
CPU time | 2.34 seconds |
Started | Jul 10 05:05:34 PM PDT 24 |
Finished | Jul 10 05:05:39 PM PDT 24 |
Peak memory | 217828 kb |
Host | smart-a0d07c99-511c-49fd-a7ea-1623a6bfd33a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634038919 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2634038919 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1125571710 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 347453640 ps |
CPU time | 2.43 seconds |
Started | Jul 10 05:05:34 PM PDT 24 |
Finished | Jul 10 05:05:40 PM PDT 24 |
Peak memory | 213160 kb |
Host | smart-2b4bb82b-3af7-4f0e-ac31-e149fcea3758 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125571710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1125571710 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1937207358 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 4852572431 ps |
CPU time | 3.08 seconds |
Started | Jul 10 05:05:40 PM PDT 24 |
Finished | Jul 10 05:05:45 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-63bf2244-f9ed-4fc8-8e26-0eea814dd80d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937207358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.1937207358 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2462003346 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 2960306826 ps |
CPU time | 9.81 seconds |
Started | Jul 10 05:05:33 PM PDT 24 |
Finished | Jul 10 05:05:47 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-8d13f58c-e720-4603-afd7-bbbc82c0ba45 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462003346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2 462003346 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.10687183 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 226641104 ps |
CPU time | 0.86 seconds |
Started | Jul 10 05:05:34 PM PDT 24 |
Finished | Jul 10 05:05:39 PM PDT 24 |
Peak memory | 204732 kb |
Host | smart-9f22485c-70ef-4496-80fc-db784be22c2a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10687183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.10687183 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.213004558 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 847229242 ps |
CPU time | 7.93 seconds |
Started | Jul 10 05:05:33 PM PDT 24 |
Finished | Jul 10 05:05:45 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-26ba17c4-0eaf-49d0-b48f-409f31209248 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213004558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c sr_outstanding.213004558 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.4026978353 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 37063475105 ps |
CPU time | 29.22 seconds |
Started | Jul 10 05:05:35 PM PDT 24 |
Finished | Jul 10 05:06:07 PM PDT 24 |
Peak memory | 221404 kb |
Host | smart-f16f4bc1-687c-4485-9a78-a3677988ca58 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026978353 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.4026978353 |
Directory | /workspace/6.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.189071775 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 211932948 ps |
CPU time | 2.1 seconds |
Started | Jul 10 05:05:39 PM PDT 24 |
Finished | Jul 10 05:05:43 PM PDT 24 |
Peak memory | 213164 kb |
Host | smart-3a2b65fc-d9b3-4e43-8c56-646ab5dd7826 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189071775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.189071775 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.725968690 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 1544812376 ps |
CPU time | 19.26 seconds |
Started | Jul 10 05:05:34 PM PDT 24 |
Finished | Jul 10 05:05:57 PM PDT 24 |
Peak memory | 213184 kb |
Host | smart-602cd3ec-7496-40ef-9399-a3011ff0cdf9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725968690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.725968690 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2109454328 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 4280705294 ps |
CPU time | 7.3 seconds |
Started | Jul 10 05:05:50 PM PDT 24 |
Finished | Jul 10 05:05:58 PM PDT 24 |
Peak memory | 220164 kb |
Host | smart-6348cc46-ea53-44b6-96bf-3340788b3980 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109454328 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2109454328 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3785231700 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 122225488 ps |
CPU time | 1.77 seconds |
Started | Jul 10 05:05:42 PM PDT 24 |
Finished | Jul 10 05:05:45 PM PDT 24 |
Peak memory | 213140 kb |
Host | smart-169d14e6-407b-4118-bddd-62a5bfaa04c8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785231700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3785231700 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.548593766 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 3770563973 ps |
CPU time | 9.41 seconds |
Started | Jul 10 05:05:41 PM PDT 24 |
Finished | Jul 10 05:05:52 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-d7b61182-8362-4e54-84b0-d5e1ddc3ec5e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548593766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r v_dm_jtag_dmi_csr_bit_bash.548593766 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1568436191 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 4706125425 ps |
CPU time | 7.01 seconds |
Started | Jul 10 05:05:41 PM PDT 24 |
Finished | Jul 10 05:05:49 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-dc42e03f-2351-4494-9aee-32152190f6bd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568436191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1 568436191 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.4087724708 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 332483293 ps |
CPU time | 1.51 seconds |
Started | Jul 10 05:05:40 PM PDT 24 |
Finished | Jul 10 05:05:44 PM PDT 24 |
Peak memory | 204652 kb |
Host | smart-3b56954c-cbb9-4040-ba8d-11159949cdf2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087724708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.4 087724708 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1515582749 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 344987540 ps |
CPU time | 4.32 seconds |
Started | Jul 10 05:05:52 PM PDT 24 |
Finished | Jul 10 05:05:58 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-eca032f5-1c2e-478e-95ba-1fd5e08259c2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515582749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.1515582749 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3595041636 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 49032794842 ps |
CPU time | 143.78 seconds |
Started | Jul 10 05:05:41 PM PDT 24 |
Finished | Jul 10 05:08:06 PM PDT 24 |
Peak memory | 221540 kb |
Host | smart-865260ea-14a1-466e-85ff-315ea85620f5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595041636 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3595041636 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2105318718 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 184199776 ps |
CPU time | 3.27 seconds |
Started | Jul 10 05:05:40 PM PDT 24 |
Finished | Jul 10 05:05:45 PM PDT 24 |
Peak memory | 213332 kb |
Host | smart-aaff56eb-7846-40d0-b157-5f6e1f1cde7a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105318718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2105318718 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3908509168 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 503652368 ps |
CPU time | 2.36 seconds |
Started | Jul 10 05:05:52 PM PDT 24 |
Finished | Jul 10 05:05:56 PM PDT 24 |
Peak memory | 215480 kb |
Host | smart-8cb30da7-dffd-4322-9314-1bff13160f30 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908509168 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3908509168 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2009287973 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 239363749 ps |
CPU time | 1.57 seconds |
Started | Jul 10 05:05:54 PM PDT 24 |
Finished | Jul 10 05:05:57 PM PDT 24 |
Peak memory | 213112 kb |
Host | smart-76c3a920-b624-4e59-8a39-41b5a29259be |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009287973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2009287973 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.556842950 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 5678133556 ps |
CPU time | 14.78 seconds |
Started | Jul 10 05:05:53 PM PDT 24 |
Finished | Jul 10 05:06:09 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-b3731662-8075-4c43-ac09-dd53de8e6803 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556842950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r v_dm_jtag_dmi_csr_bit_bash.556842950 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3494239699 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 3008590760 ps |
CPU time | 2.85 seconds |
Started | Jul 10 05:05:53 PM PDT 24 |
Finished | Jul 10 05:05:57 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-822446c1-d379-45ab-b283-ff02f6696195 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494239699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3 494239699 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3695150576 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 514635343 ps |
CPU time | 1.04 seconds |
Started | Jul 10 05:05:54 PM PDT 24 |
Finished | Jul 10 05:05:56 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-1170007d-bdee-41f9-bb73-24065e57f8c0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695150576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3 695150576 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2869509703 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 2074422791 ps |
CPU time | 7.51 seconds |
Started | Jul 10 05:05:53 PM PDT 24 |
Finished | Jul 10 05:06:02 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-b39ccef4-f3b8-4fac-b233-1e768a46779e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869509703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.2869509703 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.930252265 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 61446437423 ps |
CPU time | 123.16 seconds |
Started | Jul 10 05:05:51 PM PDT 24 |
Finished | Jul 10 05:07:55 PM PDT 24 |
Peak memory | 221408 kb |
Host | smart-37aff8e4-8e9b-463a-9d77-ba0f169f2db3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930252265 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.930252265 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2459088090 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 301500570 ps |
CPU time | 6.01 seconds |
Started | Jul 10 05:05:54 PM PDT 24 |
Finished | Jul 10 05:06:02 PM PDT 24 |
Peak memory | 213236 kb |
Host | smart-520b6fce-4252-4b81-89d3-338b8d2e9b3c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459088090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2459088090 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2352802113 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 1256322555 ps |
CPU time | 9.05 seconds |
Started | Jul 10 05:05:53 PM PDT 24 |
Finished | Jul 10 05:06:04 PM PDT 24 |
Peak memory | 213164 kb |
Host | smart-8df81b0b-284c-44a6-9685-6c994fdae3a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352802113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2352802113 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.1350685406 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 1800580923 ps |
CPU time | 3.41 seconds |
Started | Jul 10 05:05:56 PM PDT 24 |
Finished | Jul 10 05:06:01 PM PDT 24 |
Peak memory | 218132 kb |
Host | smart-df781751-95b7-456d-8c36-5b0c8c4886aa |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350685406 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.1350685406 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.106398266 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 217273217 ps |
CPU time | 2.37 seconds |
Started | Jul 10 05:05:56 PM PDT 24 |
Finished | Jul 10 05:06:00 PM PDT 24 |
Peak memory | 213256 kb |
Host | smart-f153da71-d58a-4345-a8fa-9b3b7589ea1e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106398266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.106398266 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3473912283 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 6556968227 ps |
CPU time | 14.37 seconds |
Started | Jul 10 05:05:51 PM PDT 24 |
Finished | Jul 10 05:06:07 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-55e3cd5b-2044-4248-af6b-e098654e2362 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473912283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.3473912283 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.320390494 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 4677221913 ps |
CPU time | 10.25 seconds |
Started | Jul 10 05:05:50 PM PDT 24 |
Finished | Jul 10 05:06:01 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-ad3b2673-8d67-4bb6-a70c-3156ade4a54d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320390494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.320390494 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.757837613 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 610685668 ps |
CPU time | 1.03 seconds |
Started | Jul 10 05:05:51 PM PDT 24 |
Finished | Jul 10 05:05:53 PM PDT 24 |
Peak memory | 204664 kb |
Host | smart-6bd98253-33c1-48d1-9aa7-92de4030ba2f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757837613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.757837613 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3198098552 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 239262133 ps |
CPU time | 4.1 seconds |
Started | Jul 10 05:05:53 PM PDT 24 |
Finished | Jul 10 05:05:59 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-80156f6d-7a39-41af-a9b5-f713723c8c4e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198098552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.3198098552 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2005813024 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 24660986713 ps |
CPU time | 73.37 seconds |
Started | Jul 10 05:05:52 PM PDT 24 |
Finished | Jul 10 05:07:06 PM PDT 24 |
Peak memory | 221544 kb |
Host | smart-e693b9c3-ef0c-4dc5-99ce-70dc58d8cc07 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005813024 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2005813024 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3471675070 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 77670848 ps |
CPU time | 2.57 seconds |
Started | Jul 10 05:05:50 PM PDT 24 |
Finished | Jul 10 05:05:54 PM PDT 24 |
Peak memory | 213156 kb |
Host | smart-5cb26e21-1fb1-46d2-a571-a357d5ccab07 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471675070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3471675070 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.1588911173 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 59079288 ps |
CPU time | 0.81 seconds |
Started | Jul 10 05:50:57 PM PDT 24 |
Finished | Jul 10 05:51:02 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-4524c548-cc0c-4202-816c-c7d4702cdd89 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588911173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1588911173 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2271878263 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 2371425428 ps |
CPU time | 4.51 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:07 PM PDT 24 |
Peak memory | 213928 kb |
Host | smart-474df07f-b6f1-4389-bb4c-356b2ecaa01d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2271878263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2271878263 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.172879945 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 1413636872 ps |
CPU time | 4.28 seconds |
Started | Jul 10 05:50:59 PM PDT 24 |
Finished | Jul 10 05:51:09 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-571594e8-ba64-4597-9d42-fb74c753d348 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=172879945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.172879945 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1231832012 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 177748965 ps |
CPU time | 0.87 seconds |
Started | Jul 10 05:51:08 PM PDT 24 |
Finished | Jul 10 05:51:13 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-689481e8-7ff1-44fd-893d-9377c0837b4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231832012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1231832012 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.198322019 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 64060447 ps |
CPU time | 0.89 seconds |
Started | Jul 10 05:50:55 PM PDT 24 |
Finished | Jul 10 05:50:58 PM PDT 24 |
Peak memory | 215708 kb |
Host | smart-6ff100c1-1ecc-4b62-bc49-5e93fe839f77 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=198322019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.198322019 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.529885947 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 1043623529 ps |
CPU time | 2.55 seconds |
Started | Jul 10 05:50:53 PM PDT 24 |
Finished | Jul 10 05:50:57 PM PDT 24 |
Peak memory | 205604 kb |
Host | smart-bddeff9a-b1b5-4165-b731-e72fe7db5de3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=529885947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl _access.529885947 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2044802614 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 688203550 ps |
CPU time | 1.16 seconds |
Started | Jul 10 05:50:57 PM PDT 24 |
Finished | Jul 10 05:51:02 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-fa1f0af1-51c5-401c-9f50-68019caa0287 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2044802614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2044802614 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.1764273321 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 205873524 ps |
CPU time | 0.99 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:04 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-812eb65b-4de7-43a6-8f0e-2062f7553cf1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764273321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1764273321 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.738757677 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 462983609 ps |
CPU time | 1.13 seconds |
Started | Jul 10 05:50:53 PM PDT 24 |
Finished | Jul 10 05:50:57 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-0873ab11-c77c-4532-8b67-d5a5afa11a42 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738757677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.738757677 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.3081325449 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 142985773 ps |
CPU time | 1.05 seconds |
Started | Jul 10 05:50:59 PM PDT 24 |
Finished | Jul 10 05:51:06 PM PDT 24 |
Peak memory | 204792 kb |
Host | smart-b3aa0978-a912-4f34-be18-90db3b590b31 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081325449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3081325449 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.2756396119 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 1442930898 ps |
CPU time | 4.97 seconds |
Started | Jul 10 05:50:59 PM PDT 24 |
Finished | Jul 10 05:51:09 PM PDT 24 |
Peak memory | 205208 kb |
Host | smart-eeb27ffc-0fd8-48ff-b2c3-587a79e0d9f6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756396119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2756396119 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.651805912 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 200195873 ps |
CPU time | 1.21 seconds |
Started | Jul 10 05:50:57 PM PDT 24 |
Finished | Jul 10 05:51:03 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-fbcd5172-5e11-4a03-906f-4f40ba413602 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=651805912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.651805912 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.1890179685 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 41509357 ps |
CPU time | 0.73 seconds |
Started | Jul 10 05:51:03 PM PDT 24 |
Finished | Jul 10 05:51:08 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-709d180c-7168-4b6b-b33e-26eff05ccefc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890179685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1890179685 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.3057195062 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 6754297893 ps |
CPU time | 3.55 seconds |
Started | Jul 10 05:50:59 PM PDT 24 |
Finished | Jul 10 05:51:09 PM PDT 24 |
Peak memory | 213852 kb |
Host | smart-bcbe4d87-fcfa-4700-b120-dc54191b1356 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057195062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3057195062 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.2199810111 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 231204541 ps |
CPU time | 0.87 seconds |
Started | Jul 10 05:50:57 PM PDT 24 |
Finished | Jul 10 05:51:02 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-6f468c73-1f86-40be-b510-bf443007cc2f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2199810111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2199810111 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.2442681283 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 696973857 ps |
CPU time | 1.27 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:05 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-4438969a-9c89-4d1d-b1fa-7c08287bd4cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442681283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2442681283 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.190042455 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 679385843 ps |
CPU time | 1.62 seconds |
Started | Jul 10 05:51:01 PM PDT 24 |
Finished | Jul 10 05:51:09 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-d021d62d-e036-4593-b488-c8cf3ba2ca62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=190042455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.190042455 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3509896692 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 324703777 ps |
CPU time | 1.06 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:05 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-a9ffcb9c-c8bf-474e-9ff3-fbf618c5786a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3509896692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3509896692 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.299751785 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 481775743 ps |
CPU time | 0.98 seconds |
Started | Jul 10 05:50:57 PM PDT 24 |
Finished | Jul 10 05:51:03 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-3cfebcd3-a015-4108-9681-abc51b938117 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=299751785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.299751785 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3169445820 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 1001921816 ps |
CPU time | 3.65 seconds |
Started | Jul 10 05:51:00 PM PDT 24 |
Finished | Jul 10 05:51:10 PM PDT 24 |
Peak memory | 205636 kb |
Host | smart-9eaaedec-5c4d-48ac-9868-263d0c47203b |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3169445820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t l_access.3169445820 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3061945536 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 1305545743 ps |
CPU time | 4.34 seconds |
Started | Jul 10 05:51:01 PM PDT 24 |
Finished | Jul 10 05:51:11 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-1e3a8466-f746-40f4-b912-e347ca4cfeed |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3061945536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3061945536 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.3587376656 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 83382432 ps |
CPU time | 0.81 seconds |
Started | Jul 10 05:50:56 PM PDT 24 |
Finished | Jul 10 05:51:00 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-0fe7299e-e997-4e34-aae4-7c8f9c726e17 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3587376656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3587376656 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.751039575 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 1662472298 ps |
CPU time | 1.28 seconds |
Started | Jul 10 05:51:03 PM PDT 24 |
Finished | Jul 10 05:51:09 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-c56cf4d3-3c8c-46e0-bc41-d20c86f373d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=751039575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.751039575 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.762197269 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 783115364 ps |
CPU time | 1.47 seconds |
Started | Jul 10 05:51:02 PM PDT 24 |
Finished | Jul 10 05:51:09 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-f8cd1e0c-f0ea-4305-b9b9-2bd0c148f1f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762197269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.762197269 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1700223981 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 529858077 ps |
CPU time | 1.51 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:04 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-b543d92b-24d5-4559-a802-fa023754b0a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700223981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1700223981 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.332227126 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 423911292 ps |
CPU time | 1.25 seconds |
Started | Jul 10 05:51:00 PM PDT 24 |
Finished | Jul 10 05:51:07 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-4dc683ba-63a3-405f-9c76-d7ad612955d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=332227126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.332227126 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2657476613 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 322698672 ps |
CPU time | 1.44 seconds |
Started | Jul 10 05:51:00 PM PDT 24 |
Finished | Jul 10 05:51:07 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-399ebf82-273e-414e-86d9-d83767ad9ad7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2657476613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2657476613 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.956938136 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 357331160 ps |
CPU time | 1.58 seconds |
Started | Jul 10 05:50:59 PM PDT 24 |
Finished | Jul 10 05:51:06 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-82d01835-31ca-4b97-a446-3f18a786cea8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956938136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.956938136 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.2899335649 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 603332086 ps |
CPU time | 0.89 seconds |
Started | Jul 10 05:51:03 PM PDT 24 |
Finished | Jul 10 05:51:09 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-b8588a42-5afa-45a2-8e39-49e0f5b9c7a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899335649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2899335649 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_busy.2550503892 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 130040137 ps |
CPU time | 1.05 seconds |
Started | Jul 10 05:51:00 PM PDT 24 |
Finished | Jul 10 05:51:07 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-172fd3c3-2f6f-47b6-89d3-b061a1b2ca00 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2550503892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2550503892 |
Directory | /workspace/1.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1162428508 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 547676167 ps |
CPU time | 1.55 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:04 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-f8280d85-4cbb-471d-bf53-d3538063699c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1162428508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1162428508 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.1061296374 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 86686601 ps |
CPU time | 0.8 seconds |
Started | Jul 10 05:51:03 PM PDT 24 |
Finished | Jul 10 05:51:09 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-d7c63746-eecd-46e9-b83a-d90fb31d4690 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1061296374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1061296374 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2731527987 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 2411278694 ps |
CPU time | 7.39 seconds |
Started | Jul 10 05:51:00 PM PDT 24 |
Finished | Jul 10 05:51:13 PM PDT 24 |
Peak memory | 205604 kb |
Host | smart-0c0f8184-faec-4f04-9f75-a228bbef1e26 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2731527987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2731527987 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.4054105521 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 1300745898 ps |
CPU time | 1.8 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:05 PM PDT 24 |
Peak memory | 229128 kb |
Host | smart-ca285f0d-d749-4bc9-a698-fd90bf98eafd |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054105521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.4054105521 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.104138641 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 2450165408 ps |
CPU time | 3.45 seconds |
Started | Jul 10 05:50:57 PM PDT 24 |
Finished | Jul 10 05:51:05 PM PDT 24 |
Peak memory | 205624 kb |
Host | smart-2f671c87-954d-45eb-8c4a-5b9574d2f1f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104138641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.104138641 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/1.rv_dm_stress_all.2702717189 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 1905399583 ps |
CPU time | 3.69 seconds |
Started | Jul 10 05:50:59 PM PDT 24 |
Finished | Jul 10 05:51:08 PM PDT 24 |
Peak memory | 205508 kb |
Host | smart-07aab7a2-2b15-4913-b65e-821b14bf3cc7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702717189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2702717189 |
Directory | /workspace/1.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.1109487395 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 61722687 ps |
CPU time | 0.85 seconds |
Started | Jul 10 05:51:16 PM PDT 24 |
Finished | Jul 10 05:51:22 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-2652385a-fa02-4e11-8c8f-dbf5fa3ec2f6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109487395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1109487395 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.981756112 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 3909835194 ps |
CPU time | 7.14 seconds |
Started | Jul 10 05:51:11 PM PDT 24 |
Finished | Jul 10 05:51:22 PM PDT 24 |
Peak memory | 222124 kb |
Host | smart-dc3352aa-b363-4c2b-ba93-12302b8b7925 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=981756112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.981756112 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.267095050 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 2434667572 ps |
CPU time | 4.13 seconds |
Started | Jul 10 05:51:12 PM PDT 24 |
Finished | Jul 10 05:51:20 PM PDT 24 |
Peak memory | 205648 kb |
Host | smart-eba1cd2a-ff83-4089-8e0a-a105287cbcf1 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=267095050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t l_access.267095050 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.3970384163 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 9095876822 ps |
CPU time | 8.94 seconds |
Started | Jul 10 05:51:15 PM PDT 24 |
Finished | Jul 10 05:51:29 PM PDT 24 |
Peak memory | 205496 kb |
Host | smart-2de33bf7-9ed7-441e-b7ff-f7c019c5f878 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970384163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3970384163 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.1837672365 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 43507138 ps |
CPU time | 0.79 seconds |
Started | Jul 10 05:51:14 PM PDT 24 |
Finished | Jul 10 05:51:20 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-eb228250-43b5-4477-9f17-86091fae6217 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837672365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1837672365 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1915599210 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 6865751129 ps |
CPU time | 4.91 seconds |
Started | Jul 10 05:51:19 PM PDT 24 |
Finished | Jul 10 05:51:28 PM PDT 24 |
Peak memory | 205644 kb |
Host | smart-b936c8db-2459-41b2-b08d-6e7794d8fe09 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915599210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1915599210 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1379480062 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 5061624744 ps |
CPU time | 2.58 seconds |
Started | Jul 10 05:51:11 PM PDT 24 |
Finished | Jul 10 05:51:17 PM PDT 24 |
Peak memory | 205684 kb |
Host | smart-60233cfe-d5ce-4761-99ce-5b2e8393cfea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1379480062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1379480062 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3184999696 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 1779014489 ps |
CPU time | 3.27 seconds |
Started | Jul 10 05:51:13 PM PDT 24 |
Finished | Jul 10 05:51:21 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-f9ac455f-d64f-4dfc-8318-a7a0ff5ae43c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3184999696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.3184999696 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.2686849409 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 9004508744 ps |
CPU time | 23.66 seconds |
Started | Jul 10 05:51:12 PM PDT 24 |
Finished | Jul 10 05:51:39 PM PDT 24 |
Peak memory | 213748 kb |
Host | smart-2f06c86c-cc7a-4e2d-9f4a-708a3f3b4f14 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2686849409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2686849409 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.2441600641 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 69638676 ps |
CPU time | 0.73 seconds |
Started | Jul 10 05:51:15 PM PDT 24 |
Finished | Jul 10 05:51:21 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-6019ba79-420d-433b-a710-416813205b1b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441600641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2441600641 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3316799928 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 5958218267 ps |
CPU time | 16.57 seconds |
Started | Jul 10 05:51:11 PM PDT 24 |
Finished | Jul 10 05:51:32 PM PDT 24 |
Peak memory | 213792 kb |
Host | smart-8e42199d-a08b-45d2-9c09-b925dffbf26b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3316799928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3316799928 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3155778251 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 1041050818 ps |
CPU time | 1.35 seconds |
Started | Jul 10 05:51:11 PM PDT 24 |
Finished | Jul 10 05:51:16 PM PDT 24 |
Peak memory | 214072 kb |
Host | smart-f578b388-9136-412c-baea-e63107f27e6e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3155778251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3155778251 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.712557913 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 3119627272 ps |
CPU time | 2.8 seconds |
Started | Jul 10 05:51:12 PM PDT 24 |
Finished | Jul 10 05:51:19 PM PDT 24 |
Peak memory | 213936 kb |
Host | smart-eee859db-1d38-4be5-8c10-65de9a7ebdcf |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=712557913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t l_access.712557913 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.3541964059 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 11945938967 ps |
CPU time | 8.16 seconds |
Started | Jul 10 05:51:10 PM PDT 24 |
Finished | Jul 10 05:51:22 PM PDT 24 |
Peak memory | 213912 kb |
Host | smart-3fbfcc26-0c54-4d1e-8ca0-63ec16302fa9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541964059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3541964059 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_stress_all.1781882309 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 13637784264 ps |
CPU time | 18.58 seconds |
Started | Jul 10 05:51:11 PM PDT 24 |
Finished | Jul 10 05:51:33 PM PDT 24 |
Peak memory | 216188 kb |
Host | smart-04eb3559-96e7-491f-b43c-f71e6b6666ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781882309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1781882309 |
Directory | /workspace/12.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.1789810687 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 181452493 ps |
CPU time | 1.17 seconds |
Started | Jul 10 05:51:16 PM PDT 24 |
Finished | Jul 10 05:51:22 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-485a218c-1afe-4b8d-8e8e-de744fb53c0b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789810687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1789810687 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.442243763 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 3999243279 ps |
CPU time | 6.72 seconds |
Started | Jul 10 05:51:13 PM PDT 24 |
Finished | Jul 10 05:51:25 PM PDT 24 |
Peak memory | 213900 kb |
Host | smart-5b0d1ac5-88ff-4702-9e0d-58c3328000e1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=442243763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.442243763 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.238781088 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 2014833325 ps |
CPU time | 3.23 seconds |
Started | Jul 10 05:51:12 PM PDT 24 |
Finished | Jul 10 05:51:19 PM PDT 24 |
Peak memory | 205612 kb |
Host | smart-cc73d224-b74d-4d72-a86c-2806420d495a |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=238781088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t l_access.238781088 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.4143080134 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 193855376 ps |
CPU time | 0.84 seconds |
Started | Jul 10 05:51:12 PM PDT 24 |
Finished | Jul 10 05:51:16 PM PDT 24 |
Peak memory | 205356 kb |
Host | smart-a4fac019-f390-429a-8bf2-9126e631d47b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143080134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.4143080134 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1132189295 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 10710534957 ps |
CPU time | 13.23 seconds |
Started | Jul 10 05:51:13 PM PDT 24 |
Finished | Jul 10 05:51:31 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-118950e4-66dd-414b-a09b-e3ac9f7940e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132189295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1132189295 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4128234867 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 1311859671 ps |
CPU time | 2.86 seconds |
Started | Jul 10 05:51:12 PM PDT 24 |
Finished | Jul 10 05:51:20 PM PDT 24 |
Peak memory | 205640 kb |
Host | smart-ebd902d6-8d7b-4fee-8247-616ae75c8aa0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4128234867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4128234867 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3115102776 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 2423120462 ps |
CPU time | 8.55 seconds |
Started | Jul 10 05:51:18 PM PDT 24 |
Finished | Jul 10 05:51:31 PM PDT 24 |
Peak memory | 205740 kb |
Host | smart-9718b987-ad78-4a28-8de0-764499ea961d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3115102776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.3115102776 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.106705573 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 3713168000 ps |
CPU time | 2.69 seconds |
Started | Jul 10 05:51:11 PM PDT 24 |
Finished | Jul 10 05:51:17 PM PDT 24 |
Peak memory | 213872 kb |
Host | smart-04d1c18f-e5ef-44dd-8d55-612f3a0ab827 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=106705573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.106705573 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_stress_all.2386462812 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 1302826704 ps |
CPU time | 2.65 seconds |
Started | Jul 10 05:51:10 PM PDT 24 |
Finished | Jul 10 05:51:16 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-9b03323c-3410-46f9-b81a-c683f531509d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386462812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2386462812 |
Directory | /workspace/14.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.1473665127 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 71564702 ps |
CPU time | 0.75 seconds |
Started | Jul 10 05:51:15 PM PDT 24 |
Finished | Jul 10 05:51:21 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-f1cc7cd4-0dfd-40a8-98dd-6091e27af326 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473665127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1473665127 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.627439721 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 1284187644 ps |
CPU time | 1.59 seconds |
Started | Jul 10 05:51:18 PM PDT 24 |
Finished | Jul 10 05:51:24 PM PDT 24 |
Peak memory | 205644 kb |
Host | smart-90b6dfe9-25ff-4730-8b5d-baa3caab0384 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=627439721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t l_access.627439721 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.4122659792 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 2302246405 ps |
CPU time | 6.78 seconds |
Started | Jul 10 05:51:16 PM PDT 24 |
Finished | Jul 10 05:51:28 PM PDT 24 |
Peak memory | 205644 kb |
Host | smart-fc35f7c9-0840-41da-872c-801b8b961bdb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4122659792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.4122659792 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.3818625651 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 84017590 ps |
CPU time | 0.78 seconds |
Started | Jul 10 05:51:15 PM PDT 24 |
Finished | Jul 10 05:51:21 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-69558684-3925-47b3-a0c2-127d4f9df2df |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818625651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3818625651 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.680515312 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 5342184609 ps |
CPU time | 4.46 seconds |
Started | Jul 10 05:51:10 PM PDT 24 |
Finished | Jul 10 05:51:18 PM PDT 24 |
Peak memory | 214620 kb |
Host | smart-fd1d5962-4fe8-48a7-85b6-5e42dff83280 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=680515312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t l_access.680515312 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.1671939351 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 1044439316 ps |
CPU time | 3.67 seconds |
Started | Jul 10 05:51:12 PM PDT 24 |
Finished | Jul 10 05:51:20 PM PDT 24 |
Peak memory | 205704 kb |
Host | smart-097d5e66-0acf-4362-be3f-f316ab091601 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671939351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1671939351 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.1338203865 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 11979163410 ps |
CPU time | 15.56 seconds |
Started | Jul 10 05:51:16 PM PDT 24 |
Finished | Jul 10 05:51:36 PM PDT 24 |
Peak memory | 213800 kb |
Host | smart-b0e5a088-036d-408f-8fad-c3b3885b9eee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338203865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1338203865 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.3145498268 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 45267459 ps |
CPU time | 0.78 seconds |
Started | Jul 10 05:51:15 PM PDT 24 |
Finished | Jul 10 05:51:21 PM PDT 24 |
Peak memory | 205244 kb |
Host | smart-b1c82025-646e-4216-be7f-db8e88c7ca01 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145498268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3145498268 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3129757642 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 1911815289 ps |
CPU time | 6.34 seconds |
Started | Jul 10 05:51:13 PM PDT 24 |
Finished | Jul 10 05:51:24 PM PDT 24 |
Peak memory | 205868 kb |
Host | smart-7bc07d0a-5fce-490c-919c-6506b833b77e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3129757642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3129757642 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_stress_all.282011799 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 4661160312 ps |
CPU time | 12.67 seconds |
Started | Jul 10 05:51:14 PM PDT 24 |
Finished | Jul 10 05:51:32 PM PDT 24 |
Peak memory | 205612 kb |
Host | smart-b412f511-ef13-4ef2-87b0-ef21bf138ef9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282011799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.282011799 |
Directory | /workspace/17.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.4257744628 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 95788303 ps |
CPU time | 0.79 seconds |
Started | Jul 10 05:51:15 PM PDT 24 |
Finished | Jul 10 05:51:21 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-49640831-89de-4573-b1f9-da671d3f76cd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257744628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.4257744628 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1720234868 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 2614157554 ps |
CPU time | 1.58 seconds |
Started | Jul 10 05:51:13 PM PDT 24 |
Finished | Jul 10 05:51:20 PM PDT 24 |
Peak memory | 215400 kb |
Host | smart-fcebeafb-7d78-4950-8316-a3bd79d773c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1720234868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1720234868 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.801594481 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 2692273773 ps |
CPU time | 6.82 seconds |
Started | Jul 10 05:51:14 PM PDT 24 |
Finished | Jul 10 05:51:25 PM PDT 24 |
Peak memory | 213880 kb |
Host | smart-1d7ab871-3686-4bc5-b5d7-e52e3593943c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=801594481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.801594481 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.580580821 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 3336741358 ps |
CPU time | 4.23 seconds |
Started | Jul 10 05:51:20 PM PDT 24 |
Finished | Jul 10 05:51:28 PM PDT 24 |
Peak memory | 213888 kb |
Host | smart-5bdb8409-07bb-40dd-8e7e-877cf2bfc531 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=580580821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t l_access.580580821 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.2233553109 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 4189637327 ps |
CPU time | 5.05 seconds |
Started | Jul 10 05:51:14 PM PDT 24 |
Finished | Jul 10 05:51:24 PM PDT 24 |
Peak memory | 213824 kb |
Host | smart-ef220018-faa1-47a7-ab3a-1dfe9b8b071e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2233553109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2233553109 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.2229561147 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 93572370 ps |
CPU time | 0.96 seconds |
Started | Jul 10 05:51:16 PM PDT 24 |
Finished | Jul 10 05:51:22 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-ccfd6b84-7d85-448d-8123-6805f9af3b01 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229561147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2229561147 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.149506257 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 2042046401 ps |
CPU time | 2.79 seconds |
Started | Jul 10 05:51:16 PM PDT 24 |
Finished | Jul 10 05:51:24 PM PDT 24 |
Peak memory | 213856 kb |
Host | smart-25ad2ea0-c199-472c-ad02-e833f38f4de4 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=149506257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t l_access.149506257 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.3599408981 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 1212364757 ps |
CPU time | 1.74 seconds |
Started | Jul 10 05:51:13 PM PDT 24 |
Finished | Jul 10 05:51:20 PM PDT 24 |
Peak memory | 213808 kb |
Host | smart-519933da-ab6b-4402-b188-a2aed1f1e7c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599408981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.3599408981 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.4071631360 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 151638817 ps |
CPU time | 0.74 seconds |
Started | Jul 10 05:51:00 PM PDT 24 |
Finished | Jul 10 05:51:07 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-bf476900-3f38-4258-a19f-402ae132c57c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071631360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.4071631360 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3091098943 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 20832065878 ps |
CPU time | 50.74 seconds |
Started | Jul 10 05:51:00 PM PDT 24 |
Finished | Jul 10 05:51:57 PM PDT 24 |
Peak memory | 213880 kb |
Host | smart-48f565f9-516d-4b8e-9599-7649570c79b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091098943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3091098943 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.2078446009 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 1726564209 ps |
CPU time | 4.43 seconds |
Started | Jul 10 05:50:59 PM PDT 24 |
Finished | Jul 10 05:51:10 PM PDT 24 |
Peak memory | 213780 kb |
Host | smart-e36ece57-49a4-42f2-8db5-355d222bed30 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2078446009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.2078446009 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3008904187 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 1726053661 ps |
CPU time | 1.62 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:05 PM PDT 24 |
Peak memory | 205644 kb |
Host | smart-fd6499b2-d422-4199-b195-cb73f75d0423 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3008904187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t l_access.3008904187 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.2416706710 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 176132682 ps |
CPU time | 0.77 seconds |
Started | Jul 10 05:50:59 PM PDT 24 |
Finished | Jul 10 05:51:06 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-c7d3d88c-825f-49a7-850d-fdf50c8f9b10 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2416706710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2416706710 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.4074555960 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 639668089 ps |
CPU time | 1.3 seconds |
Started | Jul 10 05:51:03 PM PDT 24 |
Finished | Jul 10 05:51:09 PM PDT 24 |
Peak memory | 229428 kb |
Host | smart-d35d5233-0cf6-428c-9b1e-cf6d11dd3149 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074555960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.4074555960 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all.3400665042 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 6145236428 ps |
CPU time | 3.61 seconds |
Started | Jul 10 05:51:04 PM PDT 24 |
Finished | Jul 10 05:51:13 PM PDT 24 |
Peak memory | 213696 kb |
Host | smart-7f52b140-9edf-42e0-9cba-f20cfa93774e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400665042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3400665042 |
Directory | /workspace/2.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.3146845763 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 77794463 ps |
CPU time | 0.76 seconds |
Started | Jul 10 05:51:13 PM PDT 24 |
Finished | Jul 10 05:51:19 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-382eae55-10c2-4ebd-8c71-43288d693c9e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146845763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.3146845763 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/20.rv_dm_stress_all.3467159353 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 8274252985 ps |
CPU time | 7.48 seconds |
Started | Jul 10 05:51:33 PM PDT 24 |
Finished | Jul 10 05:51:42 PM PDT 24 |
Peak memory | 213744 kb |
Host | smart-66a555d7-c2d0-4880-9e92-290224f6ca2d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467159353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3467159353 |
Directory | /workspace/20.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.2179921808 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 76896325 ps |
CPU time | 0.79 seconds |
Started | Jul 10 05:51:14 PM PDT 24 |
Finished | Jul 10 05:51:19 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-fa41dcaf-1342-4af4-bb83-400c60300c7c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179921808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2179921808 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.577217704 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 126810855 ps |
CPU time | 0.72 seconds |
Started | Jul 10 05:51:15 PM PDT 24 |
Finished | Jul 10 05:51:20 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-f5c7f3f7-d712-408f-aa6b-453f58b4b7d6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577217704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.577217704 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_stress_all.2836093052 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 12608716148 ps |
CPU time | 4.68 seconds |
Started | Jul 10 05:51:17 PM PDT 24 |
Finished | Jul 10 05:51:27 PM PDT 24 |
Peak memory | 213812 kb |
Host | smart-62441cc6-1d1b-453e-8b7d-52e429d5f852 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836093052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2836093052 |
Directory | /workspace/22.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.4200847861 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 141730165 ps |
CPU time | 0.98 seconds |
Started | Jul 10 05:51:21 PM PDT 24 |
Finished | Jul 10 05:51:25 PM PDT 24 |
Peak memory | 205336 kb |
Host | smart-369f8cb4-3669-4ac0-a613-01c155446e69 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200847861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.4200847861 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.2683884628 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 4262563947 ps |
CPU time | 11.44 seconds |
Started | Jul 10 05:51:15 PM PDT 24 |
Finished | Jul 10 05:51:31 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-290ef509-a213-4526-9264-64f4c81ccc92 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683884628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2683884628 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.2035694044 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 52215264 ps |
CPU time | 0.75 seconds |
Started | Jul 10 05:51:23 PM PDT 24 |
Finished | Jul 10 05:51:26 PM PDT 24 |
Peak memory | 205372 kb |
Host | smart-853ae20e-3495-40cc-a502-2b20e589f7d6 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035694044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2035694044 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/24.rv_dm_stress_all.1770818718 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 11531659968 ps |
CPU time | 14.99 seconds |
Started | Jul 10 05:51:24 PM PDT 24 |
Finished | Jul 10 05:51:41 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-b62510d9-83e9-4b19-aac1-959bcae0287b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770818718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1770818718 |
Directory | /workspace/24.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.3976392326 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 159357032 ps |
CPU time | 0.8 seconds |
Started | Jul 10 05:51:22 PM PDT 24 |
Finished | Jul 10 05:51:26 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-24ef55cf-afd5-47fa-b383-9acf399db8eb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976392326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3976392326 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.1347905597 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 9011831516 ps |
CPU time | 9.31 seconds |
Started | Jul 10 05:51:20 PM PDT 24 |
Finished | Jul 10 05:51:33 PM PDT 24 |
Peak memory | 205584 kb |
Host | smart-19dd846a-7e4e-4e46-b8e7-f9888f331eb8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347905597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.1347905597 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.2986550320 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 33194685 ps |
CPU time | 0.76 seconds |
Started | Jul 10 05:51:20 PM PDT 24 |
Finished | Jul 10 05:51:25 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-72477f9f-d0a4-4be3-89f9-e8f6d1f6e0cf |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986550320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2986550320 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.1479334230 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 62612065 ps |
CPU time | 0.74 seconds |
Started | Jul 10 05:51:20 PM PDT 24 |
Finished | Jul 10 05:51:25 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-0f9c7c85-b21a-4c51-953d-34ffb68f7169 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479334230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1479334230 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_stress_all.1706812235 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 12834573272 ps |
CPU time | 17.24 seconds |
Started | Jul 10 05:51:24 PM PDT 24 |
Finished | Jul 10 05:51:43 PM PDT 24 |
Peak memory | 213392 kb |
Host | smart-657f7006-beb8-4a6d-8129-05a66752be15 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706812235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1706812235 |
Directory | /workspace/27.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.2270211788 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 46254950 ps |
CPU time | 0.72 seconds |
Started | Jul 10 05:51:29 PM PDT 24 |
Finished | Jul 10 05:51:32 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-d848c2cd-0d6d-440d-ac15-6a69a15b87a1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270211788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2270211788 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.2258735814 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 5501974544 ps |
CPU time | 14.04 seconds |
Started | Jul 10 05:51:22 PM PDT 24 |
Finished | Jul 10 05:51:39 PM PDT 24 |
Peak memory | 205588 kb |
Host | smart-3f39fc02-6d6f-4408-b439-16a6bcfc7b35 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258735814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2258735814 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.3676566654 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 56392044 ps |
CPU time | 0.73 seconds |
Started | Jul 10 05:51:22 PM PDT 24 |
Finished | Jul 10 05:51:25 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-8acbee05-73fe-42d5-be16-97dd76685e81 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676566654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3676566654 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.326842149 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 65431748 ps |
CPU time | 0.84 seconds |
Started | Jul 10 05:51:10 PM PDT 24 |
Finished | Jul 10 05:51:14 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-ec164463-742e-4303-b594-89a3b582a33a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326842149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.326842149 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3595468149 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 31981903083 ps |
CPU time | 55.68 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:59 PM PDT 24 |
Peak memory | 213872 kb |
Host | smart-08987514-737d-45b1-b9ca-45cfcceb5a1c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3595468149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3595468149 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.309874827 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 2493042016 ps |
CPU time | 2.06 seconds |
Started | Jul 10 05:50:56 PM PDT 24 |
Finished | Jul 10 05:51:00 PM PDT 24 |
Peak memory | 214888 kb |
Host | smart-ed544be9-b027-4d93-aa51-a23d1b4fb8f6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=309874827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.309874827 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2741008754 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 8324550693 ps |
CPU time | 12.57 seconds |
Started | Jul 10 05:51:06 PM PDT 24 |
Finished | Jul 10 05:51:23 PM PDT 24 |
Peak memory | 213848 kb |
Host | smart-88b6e739-ce8b-416d-991f-5ea23d4c724f |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2741008754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.2741008754 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.1869270565 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 112407922 ps |
CPU time | 1 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:04 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-0da21ac9-b2ad-44aa-84d2-74338044e313 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1869270565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1869270565 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.1144664049 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 2323182803 ps |
CPU time | 4.78 seconds |
Started | Jul 10 05:50:58 PM PDT 24 |
Finished | Jul 10 05:51:08 PM PDT 24 |
Peak memory | 214060 kb |
Host | smart-dd62cbdc-61a2-4fe2-89ec-053be166314a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1144664049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1144664049 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.3046988193 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 1067968127 ps |
CPU time | 1.7 seconds |
Started | Jul 10 05:51:04 PM PDT 24 |
Finished | Jul 10 05:51:11 PM PDT 24 |
Peak memory | 229400 kb |
Host | smart-b0dea633-99c8-4e43-87d0-e8579e9753a8 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046988193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3046988193 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.260175051 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 90936755 ps |
CPU time | 0.82 seconds |
Started | Jul 10 05:51:26 PM PDT 24 |
Finished | Jul 10 05:51:28 PM PDT 24 |
Peak memory | 205320 kb |
Host | smart-7359aca9-3c37-4d11-9cb2-6105a367472e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260175051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.260175051 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/30.rv_dm_stress_all.3087171417 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 2089745065 ps |
CPU time | 6.18 seconds |
Started | Jul 10 05:51:22 PM PDT 24 |
Finished | Jul 10 05:51:32 PM PDT 24 |
Peak memory | 213664 kb |
Host | smart-fe4e6933-a4c9-4c28-acc0-bebc28886b90 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087171417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3087171417 |
Directory | /workspace/30.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.1309085905 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 61687329 ps |
CPU time | 0.74 seconds |
Started | Jul 10 05:51:36 PM PDT 24 |
Finished | Jul 10 05:51:38 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-660f20a6-59de-4dd3-8cd1-adc1564d5b23 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309085905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1309085905 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.2684384284 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 104304865 ps |
CPU time | 0.73 seconds |
Started | Jul 10 05:51:21 PM PDT 24 |
Finished | Jul 10 05:51:25 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-773beb93-502d-42f9-93c7-8c96394d1d63 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684384284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2684384284 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.3074942508 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 13698526707 ps |
CPU time | 24.37 seconds |
Started | Jul 10 05:51:20 PM PDT 24 |
Finished | Jul 10 05:51:48 PM PDT 24 |
Peak memory | 213828 kb |
Host | smart-408ca55b-b15e-4acc-988b-9b3e98e72b80 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074942508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3074942508 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.1914509763 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 66078591 ps |
CPU time | 0.74 seconds |
Started | Jul 10 05:51:23 PM PDT 24 |
Finished | Jul 10 05:51:26 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-87e7e90e-959f-4308-a1b1-ad84e8732298 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914509763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1914509763 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.628477463 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 114456848 ps |
CPU time | 0.97 seconds |
Started | Jul 10 05:51:28 PM PDT 24 |
Finished | Jul 10 05:51:31 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-8f00fd8a-3d68-4711-88cd-ec55b5d48d11 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628477463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.628477463 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.1524591050 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 2809156466 ps |
CPU time | 5.88 seconds |
Started | Jul 10 05:51:23 PM PDT 24 |
Finished | Jul 10 05:51:32 PM PDT 24 |
Peak memory | 213820 kb |
Host | smart-f94def85-c722-41ee-bbf0-0501b0fb7465 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524591050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1524591050 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.340608702 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 147913680 ps |
CPU time | 0.83 seconds |
Started | Jul 10 05:51:22 PM PDT 24 |
Finished | Jul 10 05:51:26 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-1b4ec90b-8578-4bea-ba28-a39ffffe63b4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340608702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.340608702 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.3923840691 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 6042139678 ps |
CPU time | 3.61 seconds |
Started | Jul 10 05:51:36 PM PDT 24 |
Finished | Jul 10 05:51:40 PM PDT 24 |
Peak memory | 213800 kb |
Host | smart-bb8d61f0-0c35-402d-9935-355901c81b11 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923840691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.3923840691 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.1909734558 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 51295201 ps |
CPU time | 0.77 seconds |
Started | Jul 10 05:51:28 PM PDT 24 |
Finished | Jul 10 05:51:31 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-a1c01e2c-cafe-4075-bc92-ea2247b97240 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909734558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1909734558 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_stress_all.2936711503 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 10812146992 ps |
CPU time | 9.51 seconds |
Started | Jul 10 05:51:20 PM PDT 24 |
Finished | Jul 10 05:51:33 PM PDT 24 |
Peak memory | 213768 kb |
Host | smart-4cf07066-9e6c-47ae-a49e-e8197567c7b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936711503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2936711503 |
Directory | /workspace/36.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.3322762138 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 85513354 ps |
CPU time | 0.89 seconds |
Started | Jul 10 05:51:24 PM PDT 24 |
Finished | Jul 10 05:51:27 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-acd74985-2d06-4ecc-83c6-8be2bfc1e536 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322762138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3322762138 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.2665213178 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 2006930875 ps |
CPU time | 2.09 seconds |
Started | Jul 10 05:51:32 PM PDT 24 |
Finished | Jul 10 05:51:36 PM PDT 24 |
Peak memory | 205424 kb |
Host | smart-ee379bf5-6452-445f-ade2-218a01f5ab6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665213178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2665213178 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.469869676 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 256343364 ps |
CPU time | 0.73 seconds |
Started | Jul 10 05:51:22 PM PDT 24 |
Finished | Jul 10 05:51:26 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-8838c8d5-a612-46fb-8139-b165c85cde27 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469869676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.469869676 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/38.rv_dm_stress_all.3996746085 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 10843384121 ps |
CPU time | 26.36 seconds |
Started | Jul 10 05:51:21 PM PDT 24 |
Finished | Jul 10 05:51:51 PM PDT 24 |
Peak memory | 205624 kb |
Host | smart-f7bfed9e-d413-48e5-a3a4-58cc1930650a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996746085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3996746085 |
Directory | /workspace/38.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.538670260 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 92184804 ps |
CPU time | 0.75 seconds |
Started | Jul 10 05:51:21 PM PDT 24 |
Finished | Jul 10 05:51:25 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-40b5e949-8929-4200-af79-1765ad597501 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538670260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.538670260 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.2328563367 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 140773184 ps |
CPU time | 0.74 seconds |
Started | Jul 10 05:51:04 PM PDT 24 |
Finished | Jul 10 05:51:10 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-d7c3a022-6a36-4399-9cb2-cab11149c8dc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328563367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2328563367 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.454395094 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 24436493112 ps |
CPU time | 11.3 seconds |
Started | Jul 10 05:51:03 PM PDT 24 |
Finished | Jul 10 05:51:19 PM PDT 24 |
Peak memory | 213808 kb |
Host | smart-46effe46-dfff-46f3-86c6-2636e76c6c9f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=454395094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.454395094 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1442838692 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 1920403692 ps |
CPU time | 6.04 seconds |
Started | Jul 10 05:51:13 PM PDT 24 |
Finished | Jul 10 05:51:24 PM PDT 24 |
Peak memory | 213776 kb |
Host | smart-3a030b21-809d-4ae9-9486-2b7f54a434d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1442838692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1442838692 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3702171836 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 1966851230 ps |
CPU time | 6.07 seconds |
Started | Jul 10 05:51:10 PM PDT 24 |
Finished | Jul 10 05:51:20 PM PDT 24 |
Peak memory | 205632 kb |
Host | smart-fb04bdf2-f97e-40da-84d6-8c9abbb384c3 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3702171836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.3702171836 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.2318177338 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 168988182 ps |
CPU time | 0.81 seconds |
Started | Jul 10 05:51:04 PM PDT 24 |
Finished | Jul 10 05:51:10 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-b8a68bd9-51be-4a86-be80-0aeff5d4cd4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2318177338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2318177338 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.627927921 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 7989967197 ps |
CPU time | 6.6 seconds |
Started | Jul 10 05:51:03 PM PDT 24 |
Finished | Jul 10 05:51:15 PM PDT 24 |
Peak memory | 213792 kb |
Host | smart-6ff4b982-ac50-4f82-ac7e-3b4222c942e3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627927921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.627927921 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.609547403 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 449933300 ps |
CPU time | 1.73 seconds |
Started | Jul 10 05:51:07 PM PDT 24 |
Finished | Jul 10 05:51:14 PM PDT 24 |
Peak memory | 229172 kb |
Host | smart-f3d6a7cc-4cc5-47ca-90e5-b266a57d25d0 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609547403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.609547403 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/4.rv_dm_stress_all.3021225218 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 11584962808 ps |
CPU time | 30.91 seconds |
Started | Jul 10 05:51:05 PM PDT 24 |
Finished | Jul 10 05:51:41 PM PDT 24 |
Peak memory | 213752 kb |
Host | smart-eedff007-b003-413d-b1ee-1634f789e60f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021225218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3021225218 |
Directory | /workspace/4.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.2679106057 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 132476723 ps |
CPU time | 0.83 seconds |
Started | Jul 10 05:51:28 PM PDT 24 |
Finished | Jul 10 05:51:30 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-f11312c6-8ee2-452c-b63e-5fbcab1a3bd0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679106057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2679106057 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.2545382245 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 3888551372 ps |
CPU time | 9.94 seconds |
Started | Jul 10 05:51:31 PM PDT 24 |
Finished | Jul 10 05:51:42 PM PDT 24 |
Peak memory | 205620 kb |
Host | smart-637115dc-78d0-4c07-9553-e04f3729d522 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545382245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2545382245 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.3956455809 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 119594209 ps |
CPU time | 0.97 seconds |
Started | Jul 10 05:51:32 PM PDT 24 |
Finished | Jul 10 05:51:35 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-ad5a3bb8-68b8-4d6e-9c34-7ee4c1a9f881 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956455809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3956455809 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.3995175204 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 96798160 ps |
CPU time | 0.74 seconds |
Started | Jul 10 05:51:31 PM PDT 24 |
Finished | Jul 10 05:51:33 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-9051005e-eed2-45f1-8162-5269e9e5250f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995175204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3995175204 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.4142993101 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 5148644508 ps |
CPU time | 5.67 seconds |
Started | Jul 10 05:51:28 PM PDT 24 |
Finished | Jul 10 05:51:36 PM PDT 24 |
Peak memory | 213792 kb |
Host | smart-353534bc-49bb-4362-94f8-f52bc8ccc3b8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142993101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.4142993101 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.1617174661 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 39239320 ps |
CPU time | 0.72 seconds |
Started | Jul 10 05:51:29 PM PDT 24 |
Finished | Jul 10 05:51:31 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-8a918149-c580-4619-9602-6e5b1d956f36 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617174661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1617174661 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_stress_all.1714622892 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 7811028619 ps |
CPU time | 23.09 seconds |
Started | Jul 10 05:51:34 PM PDT 24 |
Finished | Jul 10 05:51:58 PM PDT 24 |
Peak memory | 205528 kb |
Host | smart-523e9798-1527-4019-b5da-d80315efad3a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714622892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1714622892 |
Directory | /workspace/43.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.2577811674 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 87333535 ps |
CPU time | 0.89 seconds |
Started | Jul 10 05:51:31 PM PDT 24 |
Finished | Jul 10 05:51:33 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-547513c0-e7d8-421c-a8d6-20ab62a31c65 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577811674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2577811674 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.3235510110 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 10756484831 ps |
CPU time | 29.92 seconds |
Started | Jul 10 05:51:31 PM PDT 24 |
Finished | Jul 10 05:52:03 PM PDT 24 |
Peak memory | 213704 kb |
Host | smart-f967314a-f56a-4d38-b09d-5e478cd3694a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235510110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3235510110 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.1209292960 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 104769593 ps |
CPU time | 0.72 seconds |
Started | Jul 10 05:51:32 PM PDT 24 |
Finished | Jul 10 05:51:35 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-9a513d2b-872d-490b-905a-69feeb458633 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209292960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1209292960 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.3286576219 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 50832803 ps |
CPU time | 0.75 seconds |
Started | Jul 10 05:51:31 PM PDT 24 |
Finished | Jul 10 05:51:34 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-dd25a254-2524-4741-a738-fa1fa3f79e59 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286576219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3286576219 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.2796243324 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 5732782907 ps |
CPU time | 8.21 seconds |
Started | Jul 10 05:51:28 PM PDT 24 |
Finished | Jul 10 05:51:38 PM PDT 24 |
Peak memory | 205556 kb |
Host | smart-947b0a31-74a1-46d0-ad9f-5affb71f78a6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796243324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2796243324 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.1166799940 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 232415632 ps |
CPU time | 0.76 seconds |
Started | Jul 10 05:51:28 PM PDT 24 |
Finished | Jul 10 05:51:31 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-6026b11a-3499-47ca-b55c-b9132bdacad7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166799940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1166799940 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_stress_all.3074477930 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 8921229145 ps |
CPU time | 14.64 seconds |
Started | Jul 10 05:51:31 PM PDT 24 |
Finished | Jul 10 05:51:47 PM PDT 24 |
Peak memory | 213808 kb |
Host | smart-b5bef145-87f2-4f7d-9fb0-c223e6a6bf05 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074477930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3074477930 |
Directory | /workspace/47.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.2955818047 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 3230532034 ps |
CPU time | 8.7 seconds |
Started | Jul 10 05:51:29 PM PDT 24 |
Finished | Jul 10 05:51:40 PM PDT 24 |
Peak memory | 213832 kb |
Host | smart-b2e622e4-65df-4f44-ba8c-d8403c236405 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955818047 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2955818047 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.3953675843 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 43149772 ps |
CPU time | 0.76 seconds |
Started | Jul 10 05:51:31 PM PDT 24 |
Finished | Jul 10 05:51:33 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-70b3459c-ff08-4f62-9532-dd1892157f15 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953675843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3953675843 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.2097517861 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 4132869915 ps |
CPU time | 10.31 seconds |
Started | Jul 10 05:51:31 PM PDT 24 |
Finished | Jul 10 05:51:43 PM PDT 24 |
Peak memory | 205616 kb |
Host | smart-4b831e1b-d0d4-4fe7-8eba-c7067d984dcf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097517861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2097517861 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.2378098642 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 74969241 ps |
CPU time | 0.8 seconds |
Started | Jul 10 05:51:03 PM PDT 24 |
Finished | Jul 10 05:51:09 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-4ad8c07e-c081-4938-9d6e-f52336478219 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378098642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2378098642 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3151123972 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 6767496657 ps |
CPU time | 10.41 seconds |
Started | Jul 10 05:51:16 PM PDT 24 |
Finished | Jul 10 05:51:31 PM PDT 24 |
Peak memory | 213896 kb |
Host | smart-2e136fc7-4a64-4d71-9153-2639dbb7f646 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3151123972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3151123972 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1100184731 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 622973918 ps |
CPU time | 1.6 seconds |
Started | Jul 10 05:51:04 PM PDT 24 |
Finished | Jul 10 05:51:11 PM PDT 24 |
Peak memory | 221988 kb |
Host | smart-b032dd88-0194-4a07-a96f-5f3998844c8c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1100184731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1100184731 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2232343924 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 1986651049 ps |
CPU time | 6.28 seconds |
Started | Jul 10 05:51:10 PM PDT 24 |
Finished | Jul 10 05:51:19 PM PDT 24 |
Peak memory | 213832 kb |
Host | smart-9446a775-0803-4fb7-8abf-fa0c73428597 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2232343924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t l_access.2232343924 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.1852934998 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 3374983610 ps |
CPU time | 5.84 seconds |
Started | Jul 10 05:51:08 PM PDT 24 |
Finished | Jul 10 05:51:18 PM PDT 24 |
Peak memory | 213796 kb |
Host | smart-490aa7e7-b882-4c04-baa0-ec6a4f46608e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1852934998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1852934998 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.464754643 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 2274291133 ps |
CPU time | 3.52 seconds |
Started | Jul 10 05:51:04 PM PDT 24 |
Finished | Jul 10 05:51:13 PM PDT 24 |
Peak memory | 205628 kb |
Host | smart-6429cdcb-c179-4fcd-a6e4-41496d49be2b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464754643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.464754643 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.1525072848 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 44366110 ps |
CPU time | 0.78 seconds |
Started | Jul 10 05:51:04 PM PDT 24 |
Finished | Jul 10 05:51:10 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-fa47efdc-8600-463c-acec-43ba698fdac5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525072848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1525072848 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.71683687 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 4171016426 ps |
CPU time | 12.45 seconds |
Started | Jul 10 05:51:02 PM PDT 24 |
Finished | Jul 10 05:51:20 PM PDT 24 |
Peak memory | 222004 kb |
Host | smart-2288c0fa-1fb6-4a82-b58d-fd00e6e02369 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=71683687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.71683687 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.624897186 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 2375659713 ps |
CPU time | 7.73 seconds |
Started | Jul 10 05:51:10 PM PDT 24 |
Finished | Jul 10 05:51:21 PM PDT 24 |
Peak memory | 205724 kb |
Host | smart-768d2d48-6a60-47a3-86a4-40304d9d352c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=624897186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl _access.624897186 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.90901280 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 12299424161 ps |
CPU time | 8.75 seconds |
Started | Jul 10 05:51:09 PM PDT 24 |
Finished | Jul 10 05:51:27 PM PDT 24 |
Peak memory | 205564 kb |
Host | smart-c4489504-c374-42f8-95ec-4329056f925f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90901280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.90901280 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.3994818541 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 68110431 ps |
CPU time | 0.74 seconds |
Started | Jul 10 05:51:11 PM PDT 24 |
Finished | Jul 10 05:51:15 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-aee65379-e1ae-48ca-984c-a007ff3dcdc4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994818541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3994818541 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3720745360 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 1162990338 ps |
CPU time | 1.99 seconds |
Started | Jul 10 05:51:10 PM PDT 24 |
Finished | Jul 10 05:51:16 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-a0a996b9-4f59-4855-9a75-cb3593cdff25 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720745360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3720745360 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.682857746 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 2283564138 ps |
CPU time | 2.26 seconds |
Started | Jul 10 05:51:19 PM PDT 24 |
Finished | Jul 10 05:51:25 PM PDT 24 |
Peak memory | 213904 kb |
Host | smart-8c959d58-3e73-4cf4-9489-1dca96560188 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=682857746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl _access.682857746 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.718697781 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 6685985811 ps |
CPU time | 5.9 seconds |
Started | Jul 10 05:51:09 PM PDT 24 |
Finished | Jul 10 05:51:19 PM PDT 24 |
Peak memory | 213808 kb |
Host | smart-1af2c8f7-c655-44bf-9eb5-4c875ed56660 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718697781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.718697781 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.380500873 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 81307312 ps |
CPU time | 0.76 seconds |
Started | Jul 10 05:51:11 PM PDT 24 |
Finished | Jul 10 05:51:16 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-29211154-3a35-4941-b2b9-4454ad873f0f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380500873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.380500873 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2716250483 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 2867190771 ps |
CPU time | 4.2 seconds |
Started | Jul 10 05:51:13 PM PDT 24 |
Finished | Jul 10 05:51:22 PM PDT 24 |
Peak memory | 213872 kb |
Host | smart-2c1c5a10-5ecd-4b28-9b29-9f6a0dca2263 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716250483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2716250483 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3633299112 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 1437582282 ps |
CPU time | 4.85 seconds |
Started | Jul 10 05:51:10 PM PDT 24 |
Finished | Jul 10 05:51:18 PM PDT 24 |
Peak memory | 205644 kb |
Host | smart-958d12dc-e0dc-4911-a324-d75cea7e8e35 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633299112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3633299112 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.4072650996 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 7337423643 ps |
CPU time | 20.45 seconds |
Started | Jul 10 05:51:12 PM PDT 24 |
Finished | Jul 10 05:51:36 PM PDT 24 |
Peak memory | 213740 kb |
Host | smart-90e20767-e9c1-4eee-9e05-1ec5920a3cfa |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4072650996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t l_access.4072650996 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.204678237 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 2502805887 ps |
CPU time | 4.57 seconds |
Started | Jul 10 05:51:10 PM PDT 24 |
Finished | Jul 10 05:51:18 PM PDT 24 |
Peak memory | 213904 kb |
Host | smart-6290cffd-b922-4581-91bf-45ee4b9f1d67 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=204678237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.204678237 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.3184807887 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 2463833307 ps |
CPU time | 7.94 seconds |
Started | Jul 10 05:51:16 PM PDT 24 |
Finished | Jul 10 05:51:29 PM PDT 24 |
Peak memory | 214708 kb |
Host | smart-6ef5852c-052c-43bc-a58c-73056d18d529 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184807887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3184807887 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.2254877478 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 58489451 ps |
CPU time | 0.75 seconds |
Started | Jul 10 05:51:12 PM PDT 24 |
Finished | Jul 10 05:51:16 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-1118734a-3544-4ecf-a15f-3c4f15ed92d8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254877478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2254877478 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1280667566 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 2562681045 ps |
CPU time | 7.38 seconds |
Started | Jul 10 05:51:12 PM PDT 24 |
Finished | Jul 10 05:51:23 PM PDT 24 |
Peak memory | 213864 kb |
Host | smart-963dbbe3-3c73-4425-b154-128afecef4c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1280667566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1280667566 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2225093288 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 2847767543 ps |
CPU time | 9.77 seconds |
Started | Jul 10 05:51:09 PM PDT 24 |
Finished | Jul 10 05:51:23 PM PDT 24 |
Peak memory | 213856 kb |
Host | smart-c95d1e1b-d1e1-4957-bed2-f3ed400d8630 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2225093288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.2225093288 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_stress_all.4136132249 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 7893736464 ps |
CPU time | 21.04 seconds |
Started | Jul 10 05:51:09 PM PDT 24 |
Finished | Jul 10 05:51:34 PM PDT 24 |
Peak memory | 205564 kb |
Host | smart-278929ec-7ac0-4781-9a93-b24fddd00e70 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136132249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.4136132249 |
Directory | /workspace/9.rv_dm_stress_all/latest |
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