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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.36 95.57 80.00 89.42 74.36 86.00 98.32 52.88


Total test records in report: 443
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T98 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2881226741 Jul 11 04:57:37 PM PDT 24 Jul 11 04:57:47 PM PDT 24 86021395 ps
T49 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3969415201 Jul 11 04:57:52 PM PDT 24 Jul 11 04:58:28 PM PDT 24 41175059199 ps
T295 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1238512650 Jul 11 04:57:55 PM PDT 24 Jul 11 04:59:37 PM PDT 24 67972043064 ps
T89 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.542107767 Jul 11 04:57:43 PM PDT 24 Jul 11 04:57:54 PM PDT 24 129157529 ps
T296 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1869460100 Jul 11 04:57:59 PM PDT 24 Jul 11 04:58:17 PM PDT 24 12735578932 ps
T99 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2192286119 Jul 11 04:58:12 PM PDT 24 Jul 11 04:58:26 PM PDT 24 157352653 ps
T297 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3365611691 Jul 11 04:58:07 PM PDT 24 Jul 11 04:58:18 PM PDT 24 1042194051 ps
T298 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3914997188 Jul 11 04:57:53 PM PDT 24 Jul 11 04:58:05 PM PDT 24 3510622484 ps
T299 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.4197311426 Jul 11 04:58:13 PM PDT 24 Jul 11 04:58:40 PM PDT 24 17644779543 ps
T300 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1269340808 Jul 11 04:57:42 PM PDT 24 Jul 11 04:57:52 PM PDT 24 92460265 ps
T301 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.864706946 Jul 11 04:58:02 PM PDT 24 Jul 11 04:58:11 PM PDT 24 404612696 ps
T90 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.278804399 Jul 11 04:58:06 PM PDT 24 Jul 11 04:58:18 PM PDT 24 305800663 ps
T107 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2905968287 Jul 11 04:57:56 PM PDT 24 Jul 11 04:58:06 PM PDT 24 139165378 ps
T302 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1260079834 Jul 11 04:57:55 PM PDT 24 Jul 11 04:58:06 PM PDT 24 189865850 ps
T303 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.441408373 Jul 11 04:58:04 PM PDT 24 Jul 11 04:58:15 PM PDT 24 2598304261 ps
T100 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1580639726 Jul 11 04:58:05 PM PDT 24 Jul 11 04:58:17 PM PDT 24 532170247 ps
T304 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4114497471 Jul 11 04:58:18 PM PDT 24 Jul 11 05:00:39 PM PDT 24 99260972165 ps
T305 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.357456072 Jul 11 04:58:03 PM PDT 24 Jul 11 04:58:14 PM PDT 24 868179427 ps
T306 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2802012217 Jul 11 04:57:47 PM PDT 24 Jul 11 04:57:59 PM PDT 24 554943880 ps
T307 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4032838755 Jul 11 04:58:10 PM PDT 24 Jul 11 04:58:24 PM PDT 24 1199235016 ps
T108 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4113441871 Jul 11 04:57:44 PM PDT 24 Jul 11 04:59:02 PM PDT 24 2289530529 ps
T128 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1328886177 Jul 11 04:57:41 PM PDT 24 Jul 11 04:58:09 PM PDT 24 3723586408 ps
T308 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2051973487 Jul 11 04:58:08 PM PDT 24 Jul 11 04:58:24 PM PDT 24 1290378327 ps
T309 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.864448958 Jul 11 04:57:42 PM PDT 24 Jul 11 04:57:53 PM PDT 24 376099601 ps
T119 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4016625765 Jul 11 04:58:13 PM PDT 24 Jul 11 04:58:30 PM PDT 24 878104924 ps
T109 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3725169699 Jul 11 04:57:55 PM PDT 24 Jul 11 04:58:06 PM PDT 24 57068713 ps
T310 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.161195500 Jul 11 04:58:01 PM PDT 24 Jul 11 04:58:09 PM PDT 24 463423453 ps
T110 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.32245682 Jul 11 04:57:43 PM PDT 24 Jul 11 04:58:28 PM PDT 24 3278778763 ps
T311 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.789020758 Jul 11 04:57:56 PM PDT 24 Jul 11 04:58:06 PM PDT 24 281501006 ps
T177 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.739680179 Jul 11 04:57:44 PM PDT 24 Jul 11 04:58:13 PM PDT 24 4420026634 ps
T125 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3168580368 Jul 11 04:58:13 PM PDT 24 Jul 11 04:58:42 PM PDT 24 8194269427 ps
T312 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2116508157 Jul 11 04:58:08 PM PDT 24 Jul 11 04:58:20 PM PDT 24 530868944 ps
T111 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3173921185 Jul 11 04:57:42 PM PDT 24 Jul 11 04:58:58 PM PDT 24 8793179378 ps
T313 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.4151339224 Jul 11 04:58:00 PM PDT 24 Jul 11 04:58:18 PM PDT 24 16230477565 ps
T118 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.90474204 Jul 11 04:57:44 PM PDT 24 Jul 11 04:57:56 PM PDT 24 630501977 ps
T314 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1462033500 Jul 11 04:57:59 PM PDT 24 Jul 11 04:58:08 PM PDT 24 1500255372 ps
T180 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1298491838 Jul 11 04:57:55 PM PDT 24 Jul 11 04:58:20 PM PDT 24 3902759761 ps
T315 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1587806539 Jul 11 04:57:49 PM PDT 24 Jul 11 04:58:00 PM PDT 24 586201731 ps
T316 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.128962492 Jul 11 04:57:57 PM PDT 24 Jul 11 04:58:12 PM PDT 24 21280049325 ps
T126 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.358295066 Jul 11 04:58:10 PM PDT 24 Jul 11 04:58:21 PM PDT 24 305671049 ps
T120 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.69621238 Jul 11 04:58:19 PM PDT 24 Jul 11 04:58:40 PM PDT 24 835574150 ps
T317 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1570121662 Jul 11 04:58:09 PM PDT 24 Jul 11 04:58:24 PM PDT 24 352054504 ps
T121 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2456343825 Jul 11 04:58:05 PM PDT 24 Jul 11 04:58:16 PM PDT 24 482799091 ps
T127 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.4280556291 Jul 11 04:57:30 PM PDT 24 Jul 11 04:57:39 PM PDT 24 84424226 ps
T181 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.728809992 Jul 11 04:58:01 PM PDT 24 Jul 11 04:58:25 PM PDT 24 2746242297 ps
T318 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1453673478 Jul 11 04:58:07 PM PDT 24 Jul 11 04:58:44 PM PDT 24 11509937609 ps
T122 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1190432101 Jul 11 04:58:08 PM PDT 24 Jul 11 04:58:24 PM PDT 24 413672712 ps
T319 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2563502489 Jul 11 04:58:01 PM PDT 24 Jul 11 04:58:10 PM PDT 24 127122724 ps
T320 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.867768698 Jul 11 04:57:55 PM PDT 24 Jul 11 04:58:05 PM PDT 24 174212406 ps
T321 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3659401122 Jul 11 04:58:16 PM PDT 24 Jul 11 04:58:38 PM PDT 24 12282382975 ps
T322 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1455129667 Jul 11 04:57:44 PM PDT 24 Jul 11 04:57:55 PM PDT 24 96976644 ps
T323 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.808964290 Jul 11 04:57:33 PM PDT 24 Jul 11 04:58:42 PM PDT 24 21976708073 ps
T324 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1931586932 Jul 11 04:57:41 PM PDT 24 Jul 11 04:57:54 PM PDT 24 3901732801 ps
T112 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1228808513 Jul 11 04:58:05 PM PDT 24 Jul 11 04:58:22 PM PDT 24 653097879 ps
T325 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3388974590 Jul 11 04:58:09 PM PDT 24 Jul 11 04:58:23 PM PDT 24 266416917 ps
T326 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2667307754 Jul 11 04:57:58 PM PDT 24 Jul 11 04:58:08 PM PDT 24 2258300527 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.301131653 Jul 11 04:57:43 PM PDT 24 Jul 11 04:58:16 PM PDT 24 23787351028 ps
T328 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1890054868 Jul 11 04:57:55 PM PDT 24 Jul 11 04:58:05 PM PDT 24 520268719 ps
T329 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2645676838 Jul 11 04:57:48 PM PDT 24 Jul 11 04:58:02 PM PDT 24 2868539184 ps
T174 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2548717194 Jul 11 04:58:11 PM PDT 24 Jul 11 04:58:25 PM PDT 24 498364356 ps
T175 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.611690145 Jul 11 04:57:42 PM PDT 24 Jul 11 04:57:53 PM PDT 24 68858561 ps
T330 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1146682309 Jul 11 04:58:11 PM PDT 24 Jul 11 04:58:31 PM PDT 24 1316857402 ps
T331 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.4114823857 Jul 11 04:58:01 PM PDT 24 Jul 11 04:58:14 PM PDT 24 379187113 ps
T332 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.38949409 Jul 11 04:57:59 PM PDT 24 Jul 11 04:58:06 PM PDT 24 275434876 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.980100638 Jul 11 04:57:37 PM PDT 24 Jul 11 04:57:46 PM PDT 24 608567872 ps
T334 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2312132110 Jul 11 04:57:43 PM PDT 24 Jul 11 04:57:53 PM PDT 24 235504896 ps
T335 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.855135564 Jul 11 04:58:03 PM PDT 24 Jul 11 04:58:25 PM PDT 24 5689565863 ps
T116 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1422762640 Jul 11 04:57:42 PM PDT 24 Jul 11 04:57:53 PM PDT 24 93708249 ps
T336 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2146411879 Jul 11 04:58:13 PM PDT 24 Jul 11 04:58:29 PM PDT 24 210682220 ps
T113 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.756343596 Jul 11 04:58:04 PM PDT 24 Jul 11 04:58:16 PM PDT 24 2291515782 ps
T337 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.625297053 Jul 11 04:57:54 PM PDT 24 Jul 11 04:59:18 PM PDT 24 7946043801 ps
T338 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1117575819 Jul 11 04:57:52 PM PDT 24 Jul 11 04:58:03 PM PDT 24 413383487 ps
T339 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3708846098 Jul 11 04:57:39 PM PDT 24 Jul 11 04:59:06 PM PDT 24 16385214899 ps
T185 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1404086668 Jul 11 04:58:08 PM PDT 24 Jul 11 04:58:39 PM PDT 24 8359431358 ps
T340 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4227029158 Jul 11 04:58:01 PM PDT 24 Jul 11 04:58:09 PM PDT 24 80463738 ps
T341 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.289081084 Jul 11 04:57:33 PM PDT 24 Jul 11 04:58:02 PM PDT 24 2199503830 ps
T101 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2066090753 Jul 11 04:57:30 PM PDT 24 Jul 11 04:57:49 PM PDT 24 5695207157 ps
T342 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2591008839 Jul 11 04:58:07 PM PDT 24 Jul 11 04:58:18 PM PDT 24 506362622 ps
T343 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3065910199 Jul 11 04:57:46 PM PDT 24 Jul 11 04:57:58 PM PDT 24 178357062 ps
T176 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.758176009 Jul 11 04:57:55 PM PDT 24 Jul 11 04:58:23 PM PDT 24 9540679117 ps
T344 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1021050078 Jul 11 04:57:41 PM PDT 24 Jul 11 04:57:59 PM PDT 24 13686785154 ps
T345 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1634620225 Jul 11 04:58:00 PM PDT 24 Jul 11 04:58:08 PM PDT 24 105954323 ps
T346 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3035566812 Jul 11 04:57:43 PM PDT 24 Jul 11 04:58:46 PM PDT 24 20511601838 ps
T347 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3600584581 Jul 11 04:57:43 PM PDT 24 Jul 11 04:57:53 PM PDT 24 1554356885 ps
T348 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1599852214 Jul 11 04:58:06 PM PDT 24 Jul 11 04:58:23 PM PDT 24 2752719384 ps
T349 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3122641465 Jul 11 04:57:48 PM PDT 24 Jul 11 05:03:07 PM PDT 24 115801927912 ps
T350 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1060382244 Jul 11 04:57:59 PM PDT 24 Jul 11 04:59:39 PM PDT 24 45774056099 ps
T351 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3549255179 Jul 11 04:57:43 PM PDT 24 Jul 11 04:57:53 PM PDT 24 469507350 ps
T352 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.681828971 Jul 11 04:57:39 PM PDT 24 Jul 11 04:57:59 PM PDT 24 10196619207 ps
T353 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1172852795 Jul 11 04:58:00 PM PDT 24 Jul 11 04:58:11 PM PDT 24 1495337259 ps
T102 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3263634851 Jul 11 04:58:01 PM PDT 24 Jul 11 04:58:10 PM PDT 24 1656361567 ps
T354 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2360980990 Jul 11 04:57:43 PM PDT 24 Jul 11 04:57:54 PM PDT 24 42177344 ps
T355 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2049348645 Jul 11 04:57:54 PM PDT 24 Jul 11 04:58:07 PM PDT 24 214897517 ps
T356 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3667233674 Jul 11 04:58:09 PM PDT 24 Jul 11 04:59:03 PM PDT 24 31057096761 ps
T357 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3874969049 Jul 11 04:58:08 PM PDT 24 Jul 11 04:58:36 PM PDT 24 6751921416 ps
T358 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3430098757 Jul 11 04:58:10 PM PDT 24 Jul 11 04:58:25 PM PDT 24 948024999 ps
T183 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2786918176 Jul 11 04:57:50 PM PDT 24 Jul 11 04:58:24 PM PDT 24 6769644661 ps
T186 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.123184055 Jul 11 04:57:40 PM PDT 24 Jul 11 04:59:34 PM PDT 24 69054892707 ps
T359 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1054797578 Jul 11 04:57:45 PM PDT 24 Jul 11 04:57:55 PM PDT 24 328398694 ps
T114 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.486636148 Jul 11 04:58:00 PM PDT 24 Jul 11 04:58:15 PM PDT 24 639840289 ps
T360 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1404868198 Jul 11 04:57:52 PM PDT 24 Jul 11 04:58:35 PM PDT 24 6181259978 ps
T361 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2943189216 Jul 11 04:58:11 PM PDT 24 Jul 11 04:58:28 PM PDT 24 2597610918 ps
T362 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.27194118 Jul 11 04:57:39 PM PDT 24 Jul 11 04:57:50 PM PDT 24 76849591 ps
T363 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2169538370 Jul 11 04:57:49 PM PDT 24 Jul 11 04:58:17 PM PDT 24 57641128071 ps
T364 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2734225894 Jul 11 04:57:41 PM PDT 24 Jul 11 04:57:51 PM PDT 24 1209734586 ps
T365 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2658569330 Jul 11 04:57:56 PM PDT 24 Jul 11 04:58:44 PM PDT 24 14101240059 ps
T366 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2186862060 Jul 11 04:57:43 PM PDT 24 Jul 11 04:58:51 PM PDT 24 60230223967 ps
T367 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1549483912 Jul 11 04:58:13 PM PDT 24 Jul 11 04:58:35 PM PDT 24 1572779754 ps
T368 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.883177789 Jul 11 04:57:55 PM PDT 24 Jul 11 04:58:12 PM PDT 24 615392685 ps
T369 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3576737834 Jul 11 04:57:44 PM PDT 24 Jul 11 04:57:54 PM PDT 24 54007196 ps
T115 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.349146335 Jul 11 04:57:59 PM PDT 24 Jul 11 04:58:07 PM PDT 24 140134715 ps
T370 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3739964650 Jul 11 04:58:12 PM PDT 24 Jul 11 04:58:29 PM PDT 24 2002107333 ps
T371 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1647528602 Jul 11 04:57:55 PM PDT 24 Jul 11 04:58:18 PM PDT 24 14041701935 ps
T372 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.131635916 Jul 11 04:57:56 PM PDT 24 Jul 11 04:58:13 PM PDT 24 9415810704 ps
T373 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2213477016 Jul 11 04:57:37 PM PDT 24 Jul 11 04:57:48 PM PDT 24 422277551 ps
T374 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3352945830 Jul 11 04:57:56 PM PDT 24 Jul 11 04:58:28 PM PDT 24 9803952896 ps
T375 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.795729942 Jul 11 04:58:08 PM PDT 24 Jul 11 04:58:19 PM PDT 24 122296148 ps
T376 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1191307259 Jul 11 04:57:48 PM PDT 24 Jul 11 04:58:09 PM PDT 24 15419440134 ps
T377 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1006195932 Jul 11 04:57:46 PM PDT 24 Jul 11 04:58:01 PM PDT 24 2266765571 ps
T378 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.967601945 Jul 11 04:58:13 PM PDT 24 Jul 11 04:58:27 PM PDT 24 352841645 ps
T379 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2557456439 Jul 11 04:58:00 PM PDT 24 Jul 11 04:59:24 PM PDT 24 44927845319 ps
T380 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.247863554 Jul 11 04:58:03 PM PDT 24 Jul 11 04:58:12 PM PDT 24 2420984299 ps
T381 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4206977282 Jul 11 04:57:38 PM PDT 24 Jul 11 05:07:54 PM PDT 24 233128497144 ps
T382 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.822615251 Jul 11 04:58:08 PM PDT 24 Jul 11 04:58:38 PM PDT 24 1894590453 ps
T383 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.656206762 Jul 11 04:58:08 PM PDT 24 Jul 11 04:59:23 PM PDT 24 9798723793 ps
T384 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2707055511 Jul 11 04:58:05 PM PDT 24 Jul 11 04:58:16 PM PDT 24 881572988 ps
T385 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1456203118 Jul 11 04:58:09 PM PDT 24 Jul 11 04:58:22 PM PDT 24 230660492 ps
T386 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2239559886 Jul 11 04:57:49 PM PDT 24 Jul 11 04:58:01 PM PDT 24 210386840 ps
T178 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.90525583 Jul 11 04:58:04 PM PDT 24 Jul 11 04:58:33 PM PDT 24 4645680178 ps
T387 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2509579077 Jul 11 04:57:36 PM PDT 24 Jul 11 04:57:46 PM PDT 24 164159943 ps
T388 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1466680569 Jul 11 04:58:02 PM PDT 24 Jul 11 04:58:16 PM PDT 24 764420185 ps
T389 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1652118464 Jul 11 04:58:03 PM PDT 24 Jul 11 04:58:11 PM PDT 24 818612142 ps
T390 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2314927248 Jul 11 04:58:01 PM PDT 24 Jul 11 04:58:12 PM PDT 24 574731366 ps
T391 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3342014890 Jul 11 04:57:47 PM PDT 24 Jul 11 04:57:57 PM PDT 24 102671506 ps
T392 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3166398491 Jul 11 04:57:44 PM PDT 24 Jul 11 04:58:04 PM PDT 24 2134974978 ps
T393 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2395854512 Jul 11 04:57:43 PM PDT 24 Jul 11 04:57:55 PM PDT 24 997192236 ps
T184 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1122540429 Jul 11 04:58:16 PM PDT 24 Jul 11 04:58:46 PM PDT 24 1673184502 ps
T394 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.435336882 Jul 11 04:57:39 PM PDT 24 Jul 11 04:59:24 PM PDT 24 52211308266 ps
T103 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.830765864 Jul 11 04:57:40 PM PDT 24 Jul 11 04:57:50 PM PDT 24 4154182707 ps
T395 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3415573870 Jul 11 04:57:35 PM PDT 24 Jul 11 04:58:24 PM PDT 24 15110979728 ps
T396 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.482454974 Jul 11 04:57:46 PM PDT 24 Jul 11 04:57:56 PM PDT 24 104214938 ps
T397 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2555557130 Jul 11 04:58:21 PM PDT 24 Jul 11 04:58:38 PM PDT 24 883908171 ps
T398 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.564735049 Jul 11 04:58:10 PM PDT 24 Jul 11 04:58:25 PM PDT 24 831395411 ps
T399 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4032518585 Jul 11 04:57:54 PM PDT 24 Jul 11 04:58:54 PM PDT 24 1434581050 ps
T179 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1991372747 Jul 11 04:58:06 PM PDT 24 Jul 11 04:58:26 PM PDT 24 2332304725 ps
T400 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3663055901 Jul 11 04:58:05 PM PDT 24 Jul 11 04:58:16 PM PDT 24 321129503 ps
T401 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2073467329 Jul 11 04:58:07 PM PDT 24 Jul 11 04:58:17 PM PDT 24 100150625 ps
T402 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2057507867 Jul 11 04:58:07 PM PDT 24 Jul 11 04:58:27 PM PDT 24 2612286962 ps
T403 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2856895072 Jul 11 04:57:58 PM PDT 24 Jul 11 04:58:38 PM PDT 24 1857472583 ps
T404 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2439044381 Jul 11 04:57:55 PM PDT 24 Jul 11 04:58:06 PM PDT 24 192042991 ps
T405 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4163279629 Jul 11 04:57:48 PM PDT 24 Jul 11 04:58:01 PM PDT 24 125225243 ps
T406 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2602803709 Jul 11 04:57:33 PM PDT 24 Jul 11 04:57:44 PM PDT 24 1080600498 ps
T407 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2215292941 Jul 11 04:57:48 PM PDT 24 Jul 11 04:57:59 PM PDT 24 557782264 ps
T104 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.620309680 Jul 11 04:58:08 PM PDT 24 Jul 11 04:58:31 PM PDT 24 5245322104 ps
T408 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3364697983 Jul 11 04:57:35 PM PDT 24 Jul 11 04:57:43 PM PDT 24 62140773 ps
T409 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.18359008 Jul 11 04:58:10 PM PDT 24 Jul 11 04:58:24 PM PDT 24 3203457154 ps
T410 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2861556868 Jul 11 04:58:05 PM PDT 24 Jul 11 04:58:13 PM PDT 24 33947797 ps
T411 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3105370230 Jul 11 04:57:53 PM PDT 24 Jul 11 04:58:06 PM PDT 24 229372633 ps
T412 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2406995204 Jul 11 04:57:41 PM PDT 24 Jul 11 04:58:05 PM PDT 24 9310946961 ps
T413 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3043935298 Jul 11 04:57:50 PM PDT 24 Jul 11 04:58:02 PM PDT 24 52009944 ps
T414 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2104354796 Jul 11 04:57:45 PM PDT 24 Jul 11 04:57:57 PM PDT 24 440523033 ps
T415 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3382916690 Jul 11 04:57:54 PM PDT 24 Jul 11 04:58:07 PM PDT 24 376941849 ps
T416 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.528512349 Jul 11 04:57:53 PM PDT 24 Jul 11 04:58:05 PM PDT 24 3513647640 ps
T417 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.20808562 Jul 11 04:57:55 PM PDT 24 Jul 11 04:58:05 PM PDT 24 1744446322 ps
T418 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.116021872 Jul 11 04:58:06 PM PDT 24 Jul 11 04:58:37 PM PDT 24 50177894903 ps
T419 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3490771808 Jul 11 04:58:04 PM PDT 24 Jul 11 04:58:13 PM PDT 24 278023102 ps
T420 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3735563658 Jul 11 04:57:41 PM PDT 24 Jul 11 04:57:51 PM PDT 24 180719428 ps
T117 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3124366631 Jul 11 04:58:02 PM PDT 24 Jul 11 04:58:12 PM PDT 24 107538048 ps
T421 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3774187008 Jul 11 04:57:29 PM PDT 24 Jul 11 04:58:48 PM PDT 24 27842391877 ps
T422 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.672908049 Jul 11 04:58:02 PM PDT 24 Jul 11 04:58:10 PM PDT 24 156684663 ps
T423 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.798499502 Jul 11 04:57:41 PM PDT 24 Jul 11 04:57:56 PM PDT 24 161460765 ps
T424 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3471878318 Jul 11 04:58:00 PM PDT 24 Jul 11 04:58:12 PM PDT 24 2465990939 ps
T425 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3592920313 Jul 11 04:57:43 PM PDT 24 Jul 11 04:57:53 PM PDT 24 60220856 ps
T426 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1740276365 Jul 11 04:58:09 PM PDT 24 Jul 11 04:58:28 PM PDT 24 1634055458 ps
T427 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1913866762 Jul 11 04:58:08 PM PDT 24 Jul 11 04:58:26 PM PDT 24 7077153105 ps
T428 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3278563330 Jul 11 04:58:04 PM PDT 24 Jul 11 04:58:28 PM PDT 24 15957762592 ps
T429 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.434910712 Jul 11 04:57:44 PM PDT 24 Jul 11 04:58:00 PM PDT 24 2088859614 ps
T105 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.311547361 Jul 11 04:57:51 PM PDT 24 Jul 11 04:58:08 PM PDT 24 2688096817 ps
T430 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4050846149 Jul 11 04:58:07 PM PDT 24 Jul 11 04:58:18 PM PDT 24 1870639006 ps
T182 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.705606617 Jul 11 04:58:07 PM PDT 24 Jul 11 04:58:29 PM PDT 24 3120342716 ps
T431 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3783916149 Jul 11 04:57:51 PM PDT 24 Jul 11 04:58:01 PM PDT 24 81409229 ps
T432 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4088892222 Jul 11 04:57:51 PM PDT 24 Jul 11 04:58:02 PM PDT 24 190698959 ps
T433 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1973370367 Jul 11 04:58:05 PM PDT 24 Jul 11 04:58:17 PM PDT 24 693923149 ps
T434 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.960920379 Jul 11 04:57:56 PM PDT 24 Jul 11 04:58:05 PM PDT 24 230590874 ps
T435 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2898552373 Jul 11 04:58:06 PM PDT 24 Jul 11 04:58:17 PM PDT 24 5852554549 ps
T436 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3013258689 Jul 11 04:58:10 PM PDT 24 Jul 11 04:58:24 PM PDT 24 866343829 ps
T437 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1856472331 Jul 11 04:58:09 PM PDT 24 Jul 11 04:58:22 PM PDT 24 123358435 ps
T438 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1133552409 Jul 11 04:58:08 PM PDT 24 Jul 11 04:58:20 PM PDT 24 103163280 ps
T439 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1787821730 Jul 11 04:58:00 PM PDT 24 Jul 11 04:58:12 PM PDT 24 2623768777 ps
T440 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3746623392 Jul 11 04:58:16 PM PDT 24 Jul 11 04:58:35 PM PDT 24 174014281 ps
T441 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4287454875 Jul 11 04:57:41 PM PDT 24 Jul 11 04:57:54 PM PDT 24 515903276 ps
T442 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4106156105 Jul 11 04:58:10 PM PDT 24 Jul 11 04:58:22 PM PDT 24 417777083 ps
T443 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3338914759 Jul 11 04:57:33 PM PDT 24 Jul 11 04:57:41 PM PDT 24 131152595 ps

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2785653514
Short name T1
Test name
Test status
Simulation time 12320359213 ps
CPU time 30.64 seconds
Started Jul 11 06:24:14 PM PDT 24
Finished Jul 11 06:24:51 PM PDT 24
Peak memory 213936 kb
Host smart-0f8a812a-af39-48f7-9cb4-c39f2936fdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785653514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2785653514
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.3831891556
Short name T5
Test name
Test status
Simulation time 10157009642 ps
CPU time 13.37 seconds
Started Jul 11 06:24:00 PM PDT 24
Finished Jul 11 06:24:23 PM PDT 24
Peak memory 205584 kb
Host smart-918c9e21-d48e-4463-bc35-48d8577ebc9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831891556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3831891556
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.841507604
Short name T47
Test name
Test status
Simulation time 27480413622 ps
CPU time 62.72 seconds
Started Jul 11 04:57:56 PM PDT 24
Finished Jul 11 04:59:07 PM PDT 24
Peak memory 221456 kb
Host smart-d2439149-4c13-4e11-9f1b-0693627a0d01
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841507604 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.841507604
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2805128295
Short name T43
Test name
Test status
Simulation time 6356980811 ps
CPU time 15.01 seconds
Started Jul 11 06:23:55 PM PDT 24
Finished Jul 11 06:24:18 PM PDT 24
Peak memory 205596 kb
Host smart-d84b4772-8957-449d-b0e8-9f2ad0143407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805128295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2805128295
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1325209445
Short name T60
Test name
Test status
Simulation time 4493861644 ps
CPU time 20.27 seconds
Started Jul 11 04:57:52 PM PDT 24
Finished Jul 11 04:58:21 PM PDT 24
Peak memory 213348 kb
Host smart-fba91d46-4d55-44da-a62e-7f283d324a58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325209445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1325209445
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2967966669
Short name T57
Test name
Test status
Simulation time 104471736 ps
CPU time 0.93 seconds
Started Jul 11 06:24:04 PM PDT 24
Finished Jul 11 06:24:14 PM PDT 24
Peak memory 205384 kb
Host smart-714f338f-6bf2-4e3b-89c3-d178e87ee299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967966669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2967966669
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2430016542
Short name T254
Test name
Test status
Simulation time 75393499597 ps
CPU time 73.41 seconds
Started Jul 11 06:24:03 PM PDT 24
Finished Jul 11 06:25:25 PM PDT 24
Peak memory 214852 kb
Host smart-5af8798e-3818-4aad-93a5-cb0a4df586bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430016542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2430016542
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.3726860611
Short name T51
Test name
Test status
Simulation time 133183114 ps
CPU time 1.01 seconds
Started Jul 11 06:23:56 PM PDT 24
Finished Jul 11 06:24:06 PM PDT 24
Peak memory 215608 kb
Host smart-78eca409-622c-4cac-b2bc-6b955c92e50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726860611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3726860611
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.1608554061
Short name T17
Test name
Test status
Simulation time 4241160477 ps
CPU time 5.99 seconds
Started Jul 11 06:24:25 PM PDT 24
Finished Jul 11 06:24:37 PM PDT 24
Peak memory 205636 kb
Host smart-9d8f3350-f777-4cac-9d26-7c9293498de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608554061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.1608554061
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1928616816
Short name T6
Test name
Test status
Simulation time 2128212693 ps
CPU time 3.63 seconds
Started Jul 11 06:23:54 PM PDT 24
Finished Jul 11 06:24:05 PM PDT 24
Peak memory 205324 kb
Host smart-604863e4-77f9-4f46-ae8f-7f57c14b052a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928616816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1928616816
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2192286119
Short name T99
Test name
Test status
Simulation time 157352653 ps
CPU time 2.18 seconds
Started Jul 11 04:58:12 PM PDT 24
Finished Jul 11 04:58:26 PM PDT 24
Peak memory 213188 kb
Host smart-6e930f04-ffbf-4f81-949d-2c033f0cf2ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192286119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2192286119
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.757276269
Short name T24
Test name
Test status
Simulation time 7763918856 ps
CPU time 19.45 seconds
Started Jul 11 06:24:38 PM PDT 24
Finished Jul 11 06:25:07 PM PDT 24
Peak memory 205548 kb
Host smart-d62a125c-ecc1-4da5-8570-a5201ca86cf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757276269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.757276269
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3134289062
Short name T46
Test name
Test status
Simulation time 1895201657 ps
CPU time 6.3 seconds
Started Jul 11 06:24:12 PM PDT 24
Finished Jul 11 06:24:26 PM PDT 24
Peak memory 213552 kb
Host smart-e254b340-b0c6-4f81-8e08-cac300034e2f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134289062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3134289062
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1105721089
Short name T56
Test name
Test status
Simulation time 2530136835 ps
CPU time 2.33 seconds
Started Jul 11 06:23:57 PM PDT 24
Finished Jul 11 06:24:09 PM PDT 24
Peak memory 229208 kb
Host smart-a4b715cf-7f96-426c-9d47-166d6f321b2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105721089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1105721089
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.567601193
Short name T85
Test name
Test status
Simulation time 1681530566 ps
CPU time 1.86 seconds
Started Jul 11 06:23:47 PM PDT 24
Finished Jul 11 06:23:55 PM PDT 24
Peak memory 205556 kb
Host smart-a3158731-4107-47ac-8c5b-c4491ca3ad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567601193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.567601193
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.866989599
Short name T16
Test name
Test status
Simulation time 13298134041 ps
CPU time 9.39 seconds
Started Jul 11 06:24:12 PM PDT 24
Finished Jul 11 06:24:28 PM PDT 24
Peak memory 205596 kb
Host smart-c605b642-7aa6-4b63-bb18-257aca94293b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866989599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.866989599
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3969415201
Short name T49
Test name
Test status
Simulation time 41175059199 ps
CPU time 26.78 seconds
Started Jul 11 04:57:52 PM PDT 24
Finished Jul 11 04:58:28 PM PDT 24
Peak memory 221304 kb
Host smart-983de53d-2af0-48d2-b40a-0beede9f01aa
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969415201 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3969415201
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.410728377
Short name T42
Test name
Test status
Simulation time 216196548 ps
CPU time 0.84 seconds
Started Jul 11 06:23:52 PM PDT 24
Finished Jul 11 06:24:00 PM PDT 24
Peak memory 205352 kb
Host smart-e7433278-75a7-4c86-ba6c-a499fe59c146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410728377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.410728377
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1208884355
Short name T76
Test name
Test status
Simulation time 3773657173 ps
CPU time 3.26 seconds
Started Jul 11 06:24:05 PM PDT 24
Finished Jul 11 06:24:16 PM PDT 24
Peak memory 222032 kb
Host smart-2f7067d9-a16e-413e-8480-7a242855806b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208884355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1208884355
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1847456869
Short name T38
Test name
Test status
Simulation time 47698821 ps
CPU time 0.81 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:23:59 PM PDT 24
Peak memory 213644 kb
Host smart-ee666974-60dc-4f26-86b8-da860e66f228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847456869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1847456869
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.200562663
Short name T133
Test name
Test status
Simulation time 13616843199 ps
CPU time 10.88 seconds
Started Jul 11 06:23:58 PM PDT 24
Finished Jul 11 06:24:19 PM PDT 24
Peak memory 213876 kb
Host smart-08295f73-035b-46df-86fa-dd550907f576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200562663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.200562663
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2568759240
Short name T33
Test name
Test status
Simulation time 3250070782 ps
CPU time 3.87 seconds
Started Jul 11 06:23:49 PM PDT 24
Finished Jul 11 06:24:00 PM PDT 24
Peak memory 215044 kb
Host smart-3351111e-124d-4031-ac38-6dd8ad08dc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568759240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2568759240
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1065399769
Short name T44
Test name
Test status
Simulation time 436806908 ps
CPU time 1.08 seconds
Started Jul 11 06:23:53 PM PDT 24
Finished Jul 11 06:24:02 PM PDT 24
Peak memory 205284 kb
Host smart-90d6490e-c183-4c3a-862a-c26cd4508299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065399769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1065399769
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2186929681
Short name T94
Test name
Test status
Simulation time 605228382 ps
CPU time 3.84 seconds
Started Jul 11 04:57:56 PM PDT 24
Finished Jul 11 04:58:08 PM PDT 24
Peak memory 204960 kb
Host smart-e2478509-520e-486a-b23e-abe009c42463
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186929681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2186929681
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.2531915737
Short name T23
Test name
Test status
Simulation time 7000136849 ps
CPU time 5.52 seconds
Started Jul 11 06:23:56 PM PDT 24
Finished Jul 11 06:24:10 PM PDT 24
Peak memory 205568 kb
Host smart-5494b753-b323-44b8-853b-5144a8a4ac1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531915737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2531915737
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1122540429
Short name T184
Test name
Test status
Simulation time 1673184502 ps
CPU time 17.85 seconds
Started Jul 11 04:58:16 PM PDT 24
Finished Jul 11 04:58:46 PM PDT 24
Peak memory 213240 kb
Host smart-c6e2dc15-8732-48b6-a740-a21c6e90dc4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122540429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
122540429
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.3307785754
Short name T136
Test name
Test status
Simulation time 5316104500 ps
CPU time 13.22 seconds
Started Jul 11 06:24:20 PM PDT 24
Finished Jul 11 06:24:40 PM PDT 24
Peak memory 205572 kb
Host smart-549aa5b0-27e2-4d5a-9a3e-589467266f51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307785754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3307785754
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3689965399
Short name T164
Test name
Test status
Simulation time 21719131186 ps
CPU time 18.45 seconds
Started Jul 11 06:24:09 PM PDT 24
Finished Jul 11 06:24:36 PM PDT 24
Peak memory 213868 kb
Host smart-4f120bd3-b1b3-4b56-894e-c9c74b0cc70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689965399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3689965399
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.3453806156
Short name T215
Test name
Test status
Simulation time 9335267432 ps
CPU time 4.12 seconds
Started Jul 11 06:23:58 PM PDT 24
Finished Jul 11 06:24:12 PM PDT 24
Peak memory 215088 kb
Host smart-247916e5-1f30-41e5-8622-e476c3e77e4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453806156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3453806156
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2802012217
Short name T306
Test name
Test status
Simulation time 554943880 ps
CPU time 2.32 seconds
Started Jul 11 04:57:47 PM PDT 24
Finished Jul 11 04:57:59 PM PDT 24
Peak memory 204740 kb
Host smart-eb01a55c-7401-4f61-a8a3-e2bbe8ffeec4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802012217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2802012217
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1328886177
Short name T128
Test name
Test status
Simulation time 3723586408 ps
CPU time 18.91 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:58:09 PM PDT 24
Peak memory 213508 kb
Host smart-7663d3de-9f33-4f97-b124-8cb5fb7be832
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328886177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1328886177
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.2533191069
Short name T139
Test name
Test status
Simulation time 3808668290 ps
CPU time 3.58 seconds
Started Jul 11 06:24:01 PM PDT 24
Finished Jul 11 06:24:13 PM PDT 24
Peak memory 213772 kb
Host smart-c809e8f4-9506-4372-b166-00cd38ff5a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533191069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2533191069
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.368506838
Short name T173
Test name
Test status
Simulation time 7503943684 ps
CPU time 21.83 seconds
Started Jul 11 06:24:07 PM PDT 24
Finished Jul 11 06:24:37 PM PDT 24
Peak memory 213932 kb
Host smart-20ebeb5c-750b-40f9-b9c1-0a611049ada4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368506838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.368506838
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3364281
Short name T131
Test name
Test status
Simulation time 5296260209 ps
CPU time 13.01 seconds
Started Jul 11 06:23:53 PM PDT 24
Finished Jul 11 06:24:15 PM PDT 24
Peak memory 213256 kb
Host smart-0a0cd3c3-ba19-4147-93b1-32c7530987a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3364281
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.3890357143
Short name T21
Test name
Test status
Simulation time 7856907820 ps
CPU time 3.98 seconds
Started Jul 11 06:24:12 PM PDT 24
Finished Jul 11 06:24:23 PM PDT 24
Peak memory 213836 kb
Host smart-a4d2f186-0258-4db4-998d-f86d926819ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890357143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3890357143
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.830765864
Short name T103
Test name
Test status
Simulation time 4154182707 ps
CPU time 2.71 seconds
Started Jul 11 04:57:40 PM PDT 24
Finished Jul 11 04:57:50 PM PDT 24
Peak memory 204976 kb
Host smart-42302021-21a4-4fc1-8055-7772aac2930d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830765864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.830765864
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3557383505
Short name T165
Test name
Test status
Simulation time 1492087146 ps
CPU time 5.02 seconds
Started Jul 11 06:24:14 PM PDT 24
Finished Jul 11 06:24:26 PM PDT 24
Peak memory 204964 kb
Host smart-77a3f7be-6b5f-42c3-b23e-17f8741d67ce
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557383505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3557383505
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3662896379
Short name T35
Test name
Test status
Simulation time 1354876184 ps
CPU time 1.24 seconds
Started Jul 11 06:23:52 PM PDT 24
Finished Jul 11 06:24:02 PM PDT 24
Peak memory 205320 kb
Host smart-bcf32460-2eea-4fb5-bece-23b9dc1736c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662896379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3662896379
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1006195932
Short name T377
Test name
Test status
Simulation time 2266765571 ps
CPU time 5.56 seconds
Started Jul 11 04:57:46 PM PDT 24
Finished Jul 11 04:58:01 PM PDT 24
Peak memory 220468 kb
Host smart-a15b34b5-67ec-4c4b-8edc-1369a73f2540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006195932 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1006195932
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.705606617
Short name T182
Test name
Test status
Simulation time 3120342716 ps
CPU time 12.55 seconds
Started Jul 11 04:58:07 PM PDT 24
Finished Jul 11 04:58:29 PM PDT 24
Peak memory 213320 kb
Host smart-99d68e70-8bf3-4efd-91d1-e9b243b90db5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705606617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.705606617
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.90525583
Short name T178
Test name
Test status
Simulation time 4645680178 ps
CPU time 21.27 seconds
Started Jul 11 04:58:04 PM PDT 24
Finished Jul 11 04:58:33 PM PDT 24
Peak memory 213212 kb
Host smart-f76af2f1-b20e-466a-b21b-7aa9f22692c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90525583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.90525583
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.4230995418
Short name T160
Test name
Test status
Simulation time 2385106692 ps
CPU time 7.14 seconds
Started Jul 11 06:23:50 PM PDT 24
Finished Jul 11 06:24:05 PM PDT 24
Peak memory 205416 kb
Host smart-4615eb40-ef44-4a4a-bd13-731901cd9a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230995418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.4230995418
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2668691992
Short name T266
Test name
Test status
Simulation time 2237124429 ps
CPU time 4.28 seconds
Started Jul 11 06:23:52 PM PDT 24
Finished Jul 11 06:24:05 PM PDT 24
Peak memory 205688 kb
Host smart-c696bf26-3ad8-4f16-9e6e-a55d75d2a3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668691992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2668691992
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.321315225
Short name T28
Test name
Test status
Simulation time 4712493137 ps
CPU time 4 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:02 PM PDT 24
Peak memory 213772 kb
Host smart-28c0879c-ba46-4537-992a-4b73329a9c14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321315225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.321315225
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1621352384
Short name T170
Test name
Test status
Simulation time 7137521959 ps
CPU time 8.23 seconds
Started Jul 11 06:23:59 PM PDT 24
Finished Jul 11 06:24:16 PM PDT 24
Peak memory 213932 kb
Host smart-47f5870a-b4f9-4c97-a667-f1d765cd2d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621352384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1621352384
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.3831228943
Short name T145
Test name
Test status
Simulation time 6964775987 ps
CPU time 8.06 seconds
Started Jul 11 06:24:04 PM PDT 24
Finished Jul 11 06:24:21 PM PDT 24
Peak memory 205776 kb
Host smart-87ed7d0b-6999-4ed1-8eec-dc82592bac94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831228943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3831228943
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1118427783
Short name T162
Test name
Test status
Simulation time 1316715642 ps
CPU time 2.64 seconds
Started Jul 11 06:24:05 PM PDT 24
Finished Jul 11 06:24:16 PM PDT 24
Peak memory 205624 kb
Host smart-c08c02a5-45c0-440a-8478-dd0b40205510
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118427783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1118427783
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3816633875
Short name T68
Test name
Test status
Simulation time 5755176218 ps
CPU time 5.07 seconds
Started Jul 11 06:24:04 PM PDT 24
Finished Jul 11 06:24:17 PM PDT 24
Peak memory 214084 kb
Host smart-0054bdff-18d4-4bc8-9567-bf292857a622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816633875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3816633875
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4195886318
Short name T135
Test name
Test status
Simulation time 3230336574 ps
CPU time 9.78 seconds
Started Jul 11 06:24:08 PM PDT 24
Finished Jul 11 06:24:27 PM PDT 24
Peak memory 213616 kb
Host smart-3aa6f307-47da-41cb-8acd-1088e00ede00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195886318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4195886318
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.3742090619
Short name T157
Test name
Test status
Simulation time 19776682498 ps
CPU time 29.76 seconds
Started Jul 11 06:24:08 PM PDT 24
Finished Jul 11 06:24:47 PM PDT 24
Peak memory 213892 kb
Host smart-8324a10b-b464-4364-a6c3-9acf13fb0b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742090619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.3742090619
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3827079988
Short name T155
Test name
Test status
Simulation time 3369467351 ps
CPU time 2.16 seconds
Started Jul 11 06:24:08 PM PDT 24
Finished Jul 11 06:24:19 PM PDT 24
Peak memory 213728 kb
Host smart-fbac7194-717a-47d8-92c5-29c1de0ca360
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3827079988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3827079988
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.3299056848
Short name T172
Test name
Test status
Simulation time 2468266262 ps
CPU time 7.03 seconds
Started Jul 11 06:24:13 PM PDT 24
Finished Jul 11 06:24:27 PM PDT 24
Peak memory 205708 kb
Host smart-22bbf4f4-79f4-41f1-89bf-b7a167d8784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299056848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3299056848
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1735801977
Short name T169
Test name
Test status
Simulation time 1396715176 ps
CPU time 2.57 seconds
Started Jul 11 06:24:12 PM PDT 24
Finished Jul 11 06:24:21 PM PDT 24
Peak memory 205856 kb
Host smart-29d63061-f330-4042-a9b2-2c91e07c212b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735801977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1735801977
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.113317138
Short name T143
Test name
Test status
Simulation time 7057899979 ps
CPU time 6.37 seconds
Started Jul 11 06:24:29 PM PDT 24
Finished Jul 11 06:24:42 PM PDT 24
Peak memory 205604 kb
Host smart-4b00f05e-5a50-4877-9dd2-a9873c184b31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113317138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.113317138
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3799165326
Short name T29
Test name
Test status
Simulation time 3634597967 ps
CPU time 1.87 seconds
Started Jul 11 06:24:16 PM PDT 24
Finished Jul 11 06:24:24 PM PDT 24
Peak memory 205700 kb
Host smart-6621a2ef-8607-4804-b88d-442fb7d89bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799165326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3799165326
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1797274082
Short name T159
Test name
Test status
Simulation time 2389806174 ps
CPU time 7.35 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:06 PM PDT 24
Peak memory 205728 kb
Host smart-3e6fa035-3ef2-47d2-9aa9-46020b5618ac
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797274082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1797274082
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.4122433252
Short name T9
Test name
Test status
Simulation time 3828794563 ps
CPU time 1.85 seconds
Started Jul 11 06:24:14 PM PDT 24
Finished Jul 11 06:24:23 PM PDT 24
Peak memory 205036 kb
Host smart-ffa333dd-7dd8-4b4a-9a72-fa34c359af37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122433252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.4122433252
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.248184280
Short name T154
Test name
Test status
Simulation time 1065853127 ps
CPU time 1.55 seconds
Started Jul 11 06:23:58 PM PDT 24
Finished Jul 11 06:24:09 PM PDT 24
Peak memory 205584 kb
Host smart-834c1d7f-a49d-4040-9b41-02f74a180396
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248184280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.248184280
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2040920352
Short name T152
Test name
Test status
Simulation time 262323477 ps
CPU time 0.91 seconds
Started Jul 11 06:23:56 PM PDT 24
Finished Jul 11 06:24:06 PM PDT 24
Peak memory 205368 kb
Host smart-279854f3-a51f-4315-b719-197a969a46c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040920352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2040920352
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.2518773843
Short name T141
Test name
Test status
Simulation time 12457863197 ps
CPU time 18.09 seconds
Started Jul 11 06:23:59 PM PDT 24
Finished Jul 11 06:24:26 PM PDT 24
Peak memory 213796 kb
Host smart-6a309274-858a-469d-9647-f2b48498249b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518773843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2518773843
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2561152053
Short name T166
Test name
Test status
Simulation time 11379259594 ps
CPU time 33.82 seconds
Started Jul 11 06:24:00 PM PDT 24
Finished Jul 11 06:24:43 PM PDT 24
Peak memory 213860 kb
Host smart-0f505a8d-f367-49ff-968f-0cb8c04c9e83
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2561152053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2561152053
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.1115596979
Short name T31
Test name
Test status
Simulation time 10509910897 ps
CPU time 5.82 seconds
Started Jul 11 06:24:24 PM PDT 24
Finished Jul 11 06:24:35 PM PDT 24
Peak memory 205660 kb
Host smart-e626762a-85cc-4a3b-912d-54e4796c94a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115596979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1115596979
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3255290187
Short name T158
Test name
Test status
Simulation time 9834569485 ps
CPU time 17.26 seconds
Started Jul 11 06:24:02 PM PDT 24
Finished Jul 11 06:24:28 PM PDT 24
Peak memory 213892 kb
Host smart-019c5d53-a548-4be6-ba5e-9e2526535199
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3255290187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3255290187
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4113441871
Short name T108
Test name
Test status
Simulation time 2289530529 ps
CPU time 67.84 seconds
Started Jul 11 04:57:44 PM PDT 24
Finished Jul 11 04:59:02 PM PDT 24
Peak memory 213280 kb
Host smart-7e88346e-fa35-463f-91a0-8c7641a9b419
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113441871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.4113441871
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1404868198
Short name T360
Test name
Test status
Simulation time 6181259978 ps
CPU time 34.65 seconds
Started Jul 11 04:57:52 PM PDT 24
Finished Jul 11 04:58:35 PM PDT 24
Peak memory 213324 kb
Host smart-37a3fe3d-67e6-45ba-a9c6-69d27d6a902c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404868198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1404868198
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2213477016
Short name T373
Test name
Test status
Simulation time 422277551 ps
CPU time 2.54 seconds
Started Jul 11 04:57:37 PM PDT 24
Finished Jul 11 04:57:48 PM PDT 24
Peak memory 213256 kb
Host smart-1aa917d0-2f82-4054-9e15-3682f6f6e78a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213477016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2213477016
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.4280556291
Short name T127
Test name
Test status
Simulation time 84424226 ps
CPU time 1.74 seconds
Started Jul 11 04:57:30 PM PDT 24
Finished Jul 11 04:57:39 PM PDT 24
Peak memory 213216 kb
Host smart-2b29cb61-15f1-4acc-9e90-b2c3625e6536
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280556291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.4280556291
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3122641465
Short name T349
Test name
Test status
Simulation time 115801927912 ps
CPU time 309.81 seconds
Started Jul 11 04:57:48 PM PDT 24
Finished Jul 11 05:03:07 PM PDT 24
Peak memory 204972 kb
Host smart-b05b4ca3-2f82-4b28-ab5c-5902270fb667
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122641465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3122641465
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.435336882
Short name T394
Test name
Test status
Simulation time 52211308266 ps
CPU time 97.45 seconds
Started Jul 11 04:57:39 PM PDT 24
Finished Jul 11 04:59:24 PM PDT 24
Peak memory 204912 kb
Host smart-3d1fb33f-ce02-410c-ae9c-4816cb39ade8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435336882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
v_dm_jtag_dmi_csr_bit_bash.435336882
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3415573870
Short name T395
Test name
Test status
Simulation time 15110979728 ps
CPU time 41.87 seconds
Started Jul 11 04:57:35 PM PDT 24
Finished Jul 11 04:58:24 PM PDT 24
Peak memory 204996 kb
Host smart-bbc09cd9-5c78-4257-801c-8cb60e50eeed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415573870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
415573870
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2734225894
Short name T364
Test name
Test status
Simulation time 1209734586 ps
CPU time 2.28 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:51 PM PDT 24
Peak memory 204720 kb
Host smart-42110a9d-244f-4984-a151-261926a69dc4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734225894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2734225894
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.681828971
Short name T352
Test name
Test status
Simulation time 10196619207 ps
CPU time 13.14 seconds
Started Jul 11 04:57:39 PM PDT 24
Finished Jul 11 04:57:59 PM PDT 24
Peak memory 204900 kb
Host smart-36b27a2d-856b-4248-a2f3-6dded4c9f791
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681828971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.681828971
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1117575819
Short name T338
Test name
Test status
Simulation time 413383487 ps
CPU time 1.78 seconds
Started Jul 11 04:57:52 PM PDT 24
Finished Jul 11 04:58:03 PM PDT 24
Peak memory 204740 kb
Host smart-2e33d4f2-5048-46e9-aaa2-edff89ab2fd3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117575819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1117575819
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1054797578
Short name T359
Test name
Test status
Simulation time 328398694 ps
CPU time 0.71 seconds
Started Jul 11 04:57:45 PM PDT 24
Finished Jul 11 04:57:55 PM PDT 24
Peak memory 204688 kb
Host smart-de12ade3-5e47-455b-b005-840645eb4130
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054797578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
054797578
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1269340808
Short name T300
Test name
Test status
Simulation time 92460265 ps
CPU time 0.76 seconds
Started Jul 11 04:57:42 PM PDT 24
Finished Jul 11 04:57:52 PM PDT 24
Peak memory 204664 kb
Host smart-05d121cf-dc68-40f1-9a11-88a9bcc9da20
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269340808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1269340808
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3338914759
Short name T443
Test name
Test status
Simulation time 131152595 ps
CPU time 0.93 seconds
Started Jul 11 04:57:33 PM PDT 24
Finished Jul 11 04:57:41 PM PDT 24
Peak memory 204740 kb
Host smart-4551db88-5e92-40ab-9464-bcf54b74f505
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338914759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3338914759
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1225904628
Short name T63
Test name
Test status
Simulation time 1719901820 ps
CPU time 7.67 seconds
Started Jul 11 04:57:55 PM PDT 24
Finished Jul 11 04:58:11 PM PDT 24
Peak memory 205036 kb
Host smart-9e6ff65e-23d5-4ed8-bc21-a9efbdf6dff3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225904628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1225904628
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1028255490
Short name T48
Test name
Test status
Simulation time 65443466039 ps
CPU time 59.97 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:58:49 PM PDT 24
Peak memory 221792 kb
Host smart-923858ea-401a-420e-b37c-f578911ffdc6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028255490 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1028255490
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.27194118
Short name T362
Test name
Test status
Simulation time 76849591 ps
CPU time 2.65 seconds
Started Jul 11 04:57:39 PM PDT 24
Finished Jul 11 04:57:50 PM PDT 24
Peak memory 213260 kb
Host smart-ec07c782-b5ac-48eb-ad87-930c30a70a01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27194118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.27194118
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1089248579
Short name T84
Test name
Test status
Simulation time 4237189062 ps
CPU time 21.15 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:58:13 PM PDT 24
Peak memory 221416 kb
Host smart-8c19dd4b-ecf3-434b-a904-afe358754cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089248579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1089248579
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3708846098
Short name T339
Test name
Test status
Simulation time 16385214899 ps
CPU time 79.46 seconds
Started Jul 11 04:57:39 PM PDT 24
Finished Jul 11 04:59:06 PM PDT 24
Peak memory 213272 kb
Host smart-3514f8b5-91fa-4008-a518-0e25239ae068
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708846098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3708846098
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.32245682
Short name T110
Test name
Test status
Simulation time 3278778763 ps
CPU time 35.67 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:58:28 PM PDT 24
Peak memory 205152 kb
Host smart-ab6f3dea-009a-4c14-a87a-2ec28adedeb5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32245682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.32245682
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2509579077
Short name T387
Test name
Test status
Simulation time 164159943 ps
CPU time 2.42 seconds
Started Jul 11 04:57:36 PM PDT 24
Finished Jul 11 04:57:46 PM PDT 24
Peak memory 213088 kb
Host smart-3556cecc-9026-4cc5-aae3-b2108c2396f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509579077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2509579077
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.542107767
Short name T89
Test name
Test status
Simulation time 129157529 ps
CPU time 2.61 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:57:54 PM PDT 24
Peak memory 218208 kb
Host smart-887ebb6d-4dbe-490c-91e5-7611a0971bdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542107767 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.542107767
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2881226741
Short name T98
Test name
Test status
Simulation time 86021395 ps
CPU time 1.6 seconds
Started Jul 11 04:57:37 PM PDT 24
Finished Jul 11 04:57:47 PM PDT 24
Peak memory 213124 kb
Host smart-3f469914-21b3-4505-b2e4-690fcda764a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881226741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2881226741
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4206977282
Short name T381
Test name
Test status
Simulation time 233128497144 ps
CPU time 608.24 seconds
Started Jul 11 04:57:38 PM PDT 24
Finished Jul 11 05:07:54 PM PDT 24
Peak memory 211472 kb
Host smart-9d750f78-76c3-48ac-b8fd-11b49a463873
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206977282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.4206977282
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3774187008
Short name T421
Test name
Test status
Simulation time 27842391877 ps
CPU time 71.71 seconds
Started Jul 11 04:57:29 PM PDT 24
Finished Jul 11 04:58:48 PM PDT 24
Peak memory 204904 kb
Host smart-c3919b50-d22a-4e97-ac8c-4fb968d0408b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774187008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.3774187008
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2066090753
Short name T101
Test name
Test status
Simulation time 5695207157 ps
CPU time 10.47 seconds
Started Jul 11 04:57:30 PM PDT 24
Finished Jul 11 04:57:49 PM PDT 24
Peak memory 204960 kb
Host smart-8a222a53-78dd-43f3-b38e-42c8b7307f64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066090753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2066090753
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2602803709
Short name T406
Test name
Test status
Simulation time 1080600498 ps
CPU time 3.65 seconds
Started Jul 11 04:57:33 PM PDT 24
Finished Jul 11 04:57:44 PM PDT 24
Peak memory 204808 kb
Host smart-bf952fd0-a7ca-4e9e-b655-c7a9b505f030
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602803709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
602803709
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2312132110
Short name T334
Test name
Test status
Simulation time 235504896 ps
CPU time 0.91 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:57:53 PM PDT 24
Peak memory 204668 kb
Host smart-8514b06a-bce0-4499-9b9b-d786f4e35756
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312132110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2312132110
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.808964290
Short name T323
Test name
Test status
Simulation time 21976708073 ps
CPU time 61.39 seconds
Started Jul 11 04:57:33 PM PDT 24
Finished Jul 11 04:58:42 PM PDT 24
Peak memory 204880 kb
Host smart-eff93aad-9540-408b-90e2-d01b3ecc97f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808964290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.808964290
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.980100638
Short name T333
Test name
Test status
Simulation time 608567872 ps
CPU time 1.45 seconds
Started Jul 11 04:57:37 PM PDT 24
Finished Jul 11 04:57:46 PM PDT 24
Peak memory 204724 kb
Host smart-7bb2a1a0-688e-480e-92d9-a561533090f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980100638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.980100638
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1455129667
Short name T322
Test name
Test status
Simulation time 96976644 ps
CPU time 0.7 seconds
Started Jul 11 04:57:44 PM PDT 24
Finished Jul 11 04:57:55 PM PDT 24
Peak memory 204596 kb
Host smart-f38889b8-ff78-4137-9123-a62670e75003
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455129667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1455129667
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3364697983
Short name T408
Test name
Test status
Simulation time 62140773 ps
CPU time 0.74 seconds
Started Jul 11 04:57:35 PM PDT 24
Finished Jul 11 04:57:43 PM PDT 24
Peak memory 204736 kb
Host smart-d2b9fabf-0a21-4269-ad71-c384287eeee8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364697983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3364697983
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.883177789
Short name T368
Test name
Test status
Simulation time 615392685 ps
CPU time 7.63 seconds
Started Jul 11 04:57:55 PM PDT 24
Finished Jul 11 04:58:12 PM PDT 24
Peak memory 204956 kb
Host smart-e6129ba5-1899-47fc-86fa-904cc7a587a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883177789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.883177789
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.123184055
Short name T186
Test name
Test status
Simulation time 69054892707 ps
CPU time 106.59 seconds
Started Jul 11 04:57:40 PM PDT 24
Finished Jul 11 04:59:34 PM PDT 24
Peak memory 224168 kb
Host smart-eb3cfd4c-0191-47cf-9920-4de6d658f6a7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123184055 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.123184055
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.611690145
Short name T175
Test name
Test status
Simulation time 68858561 ps
CPU time 2.53 seconds
Started Jul 11 04:57:42 PM PDT 24
Finished Jul 11 04:57:53 PM PDT 24
Peak memory 213236 kb
Host smart-9a751108-9c70-43bc-8abc-af385d6c2f2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611690145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.611690145
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.289081084
Short name T341
Test name
Test status
Simulation time 2199503830 ps
CPU time 21.32 seconds
Started Jul 11 04:57:33 PM PDT 24
Finished Jul 11 04:58:02 PM PDT 24
Peak memory 213216 kb
Host smart-f46798f7-d82d-480c-9dd9-731ea208408f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289081084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.289081084
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3471878318
Short name T424
Test name
Test status
Simulation time 2465990939 ps
CPU time 4.54 seconds
Started Jul 11 04:58:00 PM PDT 24
Finished Jul 11 04:58:12 PM PDT 24
Peak memory 217776 kb
Host smart-5ecdfe19-a0c9-4f64-944f-9998a95f6a48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471878318 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3471878318
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.128962492
Short name T316
Test name
Test status
Simulation time 21280049325 ps
CPU time 7.72 seconds
Started Jul 11 04:57:57 PM PDT 24
Finished Jul 11 04:58:12 PM PDT 24
Peak memory 204984 kb
Host smart-cb5ccf5c-4a89-419c-948e-810f689ea7d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128962492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
rv_dm_jtag_dmi_csr_bit_bash.128962492
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2667307754
Short name T326
Test name
Test status
Simulation time 2258300527 ps
CPU time 3.22 seconds
Started Jul 11 04:57:58 PM PDT 24
Finished Jul 11 04:58:08 PM PDT 24
Peak memory 204904 kb
Host smart-1a90678f-b9f2-4ffb-8ff2-f2bc86838a4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667307754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2667307754
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.38949409
Short name T332
Test name
Test status
Simulation time 275434876 ps
CPU time 1.3 seconds
Started Jul 11 04:57:59 PM PDT 24
Finished Jul 11 04:58:06 PM PDT 24
Peak memory 204736 kb
Host smart-91bdd692-e4fe-4d2d-a428-a1ef968da51f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38949409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.38949409
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.756343596
Short name T113
Test name
Test status
Simulation time 2291515782 ps
CPU time 4.67 seconds
Started Jul 11 04:58:04 PM PDT 24
Finished Jul 11 04:58:16 PM PDT 24
Peak memory 205024 kb
Host smart-225ccacd-7bf0-4de4-b14f-1e206594e85f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756343596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.756343596
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3065910199
Short name T343
Test name
Test status
Simulation time 178357062 ps
CPU time 3.58 seconds
Started Jul 11 04:57:46 PM PDT 24
Finished Jul 11 04:57:58 PM PDT 24
Peak memory 213208 kb
Host smart-4466012e-5702-4b65-b3ff-fa58f8cf5a53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065910199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3065910199
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.728809992
Short name T181
Test name
Test status
Simulation time 2746242297 ps
CPU time 16.24 seconds
Started Jul 11 04:58:01 PM PDT 24
Finished Jul 11 04:58:25 PM PDT 24
Peak memory 213300 kb
Host smart-dd61f1cb-505f-492f-8a1f-575dad179b9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728809992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.728809992
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2645676838
Short name T329
Test name
Test status
Simulation time 2868539184 ps
CPU time 4.95 seconds
Started Jul 11 04:57:48 PM PDT 24
Finished Jul 11 04:58:02 PM PDT 24
Peak memory 217812 kb
Host smart-febcc3bf-7e52-4df1-9379-80e528a374d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645676838 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2645676838
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2591008839
Short name T342
Test name
Test status
Simulation time 506362622 ps
CPU time 2.13 seconds
Started Jul 11 04:58:07 PM PDT 24
Finished Jul 11 04:58:18 PM PDT 24
Peak memory 213088 kb
Host smart-64142127-3435-4ff1-9a8c-97ad20ffb93b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591008839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2591008839
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2898552373
Short name T435
Test name
Test status
Simulation time 5852554549 ps
CPU time 2.83 seconds
Started Jul 11 04:58:06 PM PDT 24
Finished Jul 11 04:58:17 PM PDT 24
Peak memory 204976 kb
Host smart-ac0cb7f9-d7ce-4955-a74b-223b76505e32
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898552373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.2898552373
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1191307259
Short name T376
Test name
Test status
Simulation time 15419440134 ps
CPU time 11.64 seconds
Started Jul 11 04:57:48 PM PDT 24
Finished Jul 11 04:58:09 PM PDT 24
Peak memory 204848 kb
Host smart-ef3bcbcf-7e62-4227-a4fd-2dd25f17e57d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191307259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1191307259
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.960920379
Short name T434
Test name
Test status
Simulation time 230590874 ps
CPU time 0.97 seconds
Started Jul 11 04:57:56 PM PDT 24
Finished Jul 11 04:58:05 PM PDT 24
Peak memory 204752 kb
Host smart-7f678a22-12e5-4e77-b6a1-ac2c119533a7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960920379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.960920379
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.481635224
Short name T91
Test name
Test status
Simulation time 611826104 ps
CPU time 4.53 seconds
Started Jul 11 04:57:54 PM PDT 24
Finished Jul 11 04:58:07 PM PDT 24
Peak memory 204996 kb
Host smart-151cb1dc-6a76-4dba-b11d-de110a0f45e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481635224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.481635224
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.4114823857
Short name T331
Test name
Test status
Simulation time 379187113 ps
CPU time 5.88 seconds
Started Jul 11 04:58:01 PM PDT 24
Finished Jul 11 04:58:14 PM PDT 24
Peak memory 213232 kb
Host smart-189f67d4-89cd-40d4-b46c-2f3b621515a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114823857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.4114823857
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1549483912
Short name T367
Test name
Test status
Simulation time 1572779754 ps
CPU time 9.67 seconds
Started Jul 11 04:58:13 PM PDT 24
Finished Jul 11 04:58:35 PM PDT 24
Peak memory 213212 kb
Host smart-90301a4f-b323-46ad-96b6-119f7ef454a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549483912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
549483912
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1205167382
Short name T88
Test name
Test status
Simulation time 210848460 ps
CPU time 2.26 seconds
Started Jul 11 04:58:09 PM PDT 24
Finished Jul 11 04:58:21 PM PDT 24
Peak memory 213228 kb
Host smart-132664d4-fb78-4545-8be2-20d42e016444
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205167382 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1205167382
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1133552409
Short name T438
Test name
Test status
Simulation time 103163280 ps
CPU time 2.21 seconds
Started Jul 11 04:58:08 PM PDT 24
Finished Jul 11 04:58:20 PM PDT 24
Peak memory 213108 kb
Host smart-249e2975-b02d-464c-86a4-9a6503082fce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133552409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1133552409
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.131635916
Short name T372
Test name
Test status
Simulation time 9415810704 ps
CPU time 9.23 seconds
Started Jul 11 04:57:56 PM PDT 24
Finished Jul 11 04:58:13 PM PDT 24
Peak memory 204828 kb
Host smart-6c184031-fe1c-4daa-a82e-de7814c8755f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131635916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rv_dm_jtag_dmi_csr_bit_bash.131635916
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1462033500
Short name T314
Test name
Test status
Simulation time 1500255372 ps
CPU time 2.01 seconds
Started Jul 11 04:57:59 PM PDT 24
Finished Jul 11 04:58:08 PM PDT 24
Peak memory 204924 kb
Host smart-18ef5b9a-5a2a-455a-a803-409db0b35534
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462033500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1462033500
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1652118464
Short name T389
Test name
Test status
Simulation time 818612142 ps
CPU time 0.99 seconds
Started Jul 11 04:58:03 PM PDT 24
Finished Jul 11 04:58:11 PM PDT 24
Peak memory 204660 kb
Host smart-6f36115f-60d9-45f5-b8fe-264422158f31
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652118464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1652118464
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1993609420
Short name T96
Test name
Test status
Simulation time 654303739 ps
CPU time 6.24 seconds
Started Jul 11 04:58:06 PM PDT 24
Finished Jul 11 04:58:21 PM PDT 24
Peak memory 205048 kb
Host smart-058c4a71-a748-4bdf-b3d5-228f4e0daf28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993609420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1993609420
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.564735049
Short name T398
Test name
Test status
Simulation time 831395411 ps
CPU time 4.95 seconds
Started Jul 11 04:58:10 PM PDT 24
Finished Jul 11 04:58:25 PM PDT 24
Peak memory 215368 kb
Host smart-3f3b476f-ece4-4ec1-b8cf-f550f4442c2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564735049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.564735049
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.758176009
Short name T176
Test name
Test status
Simulation time 9540679117 ps
CPU time 19.71 seconds
Started Jul 11 04:57:55 PM PDT 24
Finished Jul 11 04:58:23 PM PDT 24
Peak memory 213280 kb
Host smart-760625f8-d2db-4c8f-9232-d558b131489f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758176009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.758176009
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2943189216
Short name T361
Test name
Test status
Simulation time 2597610918 ps
CPU time 6.7 seconds
Started Jul 11 04:58:11 PM PDT 24
Finished Jul 11 04:58:28 PM PDT 24
Peak memory 218652 kb
Host smart-ebd4882b-a76e-4e71-b2f9-0d6de1cf3ccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943189216 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2943189216
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.358295066
Short name T126
Test name
Test status
Simulation time 305671049 ps
CPU time 1.52 seconds
Started Jul 11 04:58:10 PM PDT 24
Finished Jul 11 04:58:21 PM PDT 24
Peak memory 213084 kb
Host smart-3b948261-0e3d-4518-a560-be5180ef0c18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358295066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.358295066
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.32664729
Short name T291
Test name
Test status
Simulation time 31814484136 ps
CPU time 18.62 seconds
Started Jul 11 04:57:57 PM PDT 24
Finished Jul 11 04:58:23 PM PDT 24
Peak memory 204976 kb
Host smart-600c4b3d-0200-482c-972c-3d0b1ec77524
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32664729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.r
v_dm_jtag_dmi_csr_bit_bash.32664729
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.161391260
Short name T293
Test name
Test status
Simulation time 1792168873 ps
CPU time 5.17 seconds
Started Jul 11 04:58:12 PM PDT 24
Finished Jul 11 04:58:29 PM PDT 24
Peak memory 204824 kb
Host smart-3ed7d4b8-3866-40a8-9af4-5227fb1b8fb1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161391260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.161391260
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3490771808
Short name T419
Test name
Test status
Simulation time 278023102 ps
CPU time 1.12 seconds
Started Jul 11 04:58:04 PM PDT 24
Finished Jul 11 04:58:13 PM PDT 24
Peak memory 204652 kb
Host smart-b4552790-3376-422d-8721-88ab37f22440
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490771808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3490771808
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2555557130
Short name T397
Test name
Test status
Simulation time 883908171 ps
CPU time 4.33 seconds
Started Jul 11 04:58:21 PM PDT 24
Finished Jul 11 04:58:38 PM PDT 24
Peak memory 205036 kb
Host smart-09f31a1d-3768-4511-98ef-c49d18f270e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555557130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2555557130
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1580639726
Short name T100
Test name
Test status
Simulation time 532170247 ps
CPU time 4.88 seconds
Started Jul 11 04:58:05 PM PDT 24
Finished Jul 11 04:58:17 PM PDT 24
Peak memory 213240 kb
Host smart-cbefb421-f759-4d82-8049-adc193d2eba3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580639726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1580639726
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.18359008
Short name T409
Test name
Test status
Simulation time 3203457154 ps
CPU time 4.05 seconds
Started Jul 11 04:58:10 PM PDT 24
Finished Jul 11 04:58:24 PM PDT 24
Peak memory 217532 kb
Host smart-a00a9b59-3611-4998-9f21-355118f3bf71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18359008 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.18359008
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2146411879
Short name T336
Test name
Test status
Simulation time 210682220 ps
CPU time 2.62 seconds
Started Jul 11 04:58:13 PM PDT 24
Finished Jul 11 04:58:29 PM PDT 24
Peak memory 213176 kb
Host smart-d5ba2156-a7a2-4352-8db9-8ff52cd447db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146411879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2146411879
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1060382244
Short name T350
Test name
Test status
Simulation time 45774056099 ps
CPU time 93.59 seconds
Started Jul 11 04:57:59 PM PDT 24
Finished Jul 11 04:59:39 PM PDT 24
Peak memory 204968 kb
Host smart-d39a1b4e-5f68-467a-88a8-fbccc6408b3f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060382244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.1060382244
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2658569330
Short name T365
Test name
Test status
Simulation time 14101240059 ps
CPU time 39.47 seconds
Started Jul 11 04:57:56 PM PDT 24
Finished Jul 11 04:58:44 PM PDT 24
Peak memory 204960 kb
Host smart-f741c1aa-dd89-4734-88a8-5791ba76118e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658569330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2658569330
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2116508157
Short name T312
Test name
Test status
Simulation time 530868944 ps
CPU time 1.85 seconds
Started Jul 11 04:58:08 PM PDT 24
Finished Jul 11 04:58:20 PM PDT 24
Peak memory 204732 kb
Host smart-c7a646d6-23d8-4fdc-9264-f6c38f96cc20
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116508157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2116508157
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.357456072
Short name T305
Test name
Test status
Simulation time 868179427 ps
CPU time 4.03 seconds
Started Jul 11 04:58:03 PM PDT 24
Finished Jul 11 04:58:14 PM PDT 24
Peak memory 213244 kb
Host smart-4c2c79c4-2771-435d-8183-aa0909575dc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357456072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.357456072
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1404086668
Short name T185
Test name
Test status
Simulation time 8359431358 ps
CPU time 20.87 seconds
Started Jul 11 04:58:08 PM PDT 24
Finished Jul 11 04:58:39 PM PDT 24
Peak memory 213332 kb
Host smart-3b629ec8-e301-4c8d-9852-57732145be1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404086668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
404086668
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3168580368
Short name T125
Test name
Test status
Simulation time 8194269427 ps
CPU time 16.44 seconds
Started Jul 11 04:58:13 PM PDT 24
Finished Jul 11 04:58:42 PM PDT 24
Peak memory 221204 kb
Host smart-26569fd6-aa73-45fd-a1bc-7217be4ba66b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168580368 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3168580368
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1856472331
Short name T437
Test name
Test status
Simulation time 123358435 ps
CPU time 1.72 seconds
Started Jul 11 04:58:09 PM PDT 24
Finished Jul 11 04:58:22 PM PDT 24
Peak memory 213168 kb
Host smart-38cefa5a-b2b3-49d0-b5cc-15dbb78d5cea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856472331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1856472331
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1453673478
Short name T318
Test name
Test status
Simulation time 11509937609 ps
CPU time 28.65 seconds
Started Jul 11 04:58:07 PM PDT 24
Finished Jul 11 04:58:44 PM PDT 24
Peak memory 204964 kb
Host smart-4822eb5a-8fed-439c-ba05-2f5442d7bb71
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453673478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.1453673478
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.441408373
Short name T303
Test name
Test status
Simulation time 2598304261 ps
CPU time 3.84 seconds
Started Jul 11 04:58:04 PM PDT 24
Finished Jul 11 04:58:15 PM PDT 24
Peak memory 204956 kb
Host smart-49562491-af8d-4db9-8970-22cf7a62ab40
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441408373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.441408373
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3618319290
Short name T81
Test name
Test status
Simulation time 131054286 ps
CPU time 0.99 seconds
Started Jul 11 04:58:09 PM PDT 24
Finished Jul 11 04:58:21 PM PDT 24
Peak memory 204744 kb
Host smart-129a46e9-a63d-424f-9a65-f61155ccd24d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618319290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3618319290
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.69621238
Short name T120
Test name
Test status
Simulation time 835574150 ps
CPU time 8.07 seconds
Started Jul 11 04:58:19 PM PDT 24
Finished Jul 11 04:58:40 PM PDT 24
Peak memory 205092 kb
Host smart-3e229826-b1a9-4328-8d78-52c3ffcd6686
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69621238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_c
sr_outstanding.69621238
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2314927248
Short name T390
Test name
Test status
Simulation time 574731366 ps
CPU time 3.37 seconds
Started Jul 11 04:58:01 PM PDT 24
Finished Jul 11 04:58:12 PM PDT 24
Peak memory 213156 kb
Host smart-00b96d7e-9929-49f7-a519-b70ee9afad9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314927248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2314927248
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4106156105
Short name T442
Test name
Test status
Simulation time 417777083 ps
CPU time 2.31 seconds
Started Jul 11 04:58:10 PM PDT 24
Finished Jul 11 04:58:22 PM PDT 24
Peak memory 214952 kb
Host smart-c37db8ed-82ed-49bf-b4f2-a36e6775d23a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106156105 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.4106156105
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2563502489
Short name T319
Test name
Test status
Simulation time 127122724 ps
CPU time 2.42 seconds
Started Jul 11 04:58:01 PM PDT 24
Finished Jul 11 04:58:10 PM PDT 24
Peak memory 213464 kb
Host smart-33228ea9-75f3-413f-8ed5-b323c57c5279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563502489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2563502489
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3659401122
Short name T321
Test name
Test status
Simulation time 12282382975 ps
CPU time 9.78 seconds
Started Jul 11 04:58:16 PM PDT 24
Finished Jul 11 04:58:38 PM PDT 24
Peak memory 204976 kb
Host smart-52f75e48-9477-429b-bb75-1a026e64995e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659401122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.3659401122
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.4032838755
Short name T307
Test name
Test status
Simulation time 1199235016 ps
CPU time 3.8 seconds
Started Jul 11 04:58:10 PM PDT 24
Finished Jul 11 04:58:24 PM PDT 24
Peak memory 204816 kb
Host smart-0666f9e5-66b9-49cb-a7d4-d6baf44f6443
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032838755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
4032838755
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.967601945
Short name T378
Test name
Test status
Simulation time 352841645 ps
CPU time 1.42 seconds
Started Jul 11 04:58:13 PM PDT 24
Finished Jul 11 04:58:27 PM PDT 24
Peak memory 204656 kb
Host smart-e1be7e59-ae6c-428b-b545-ac8ef3372650
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967601945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.967601945
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3746623392
Short name T440
Test name
Test status
Simulation time 174014281 ps
CPU time 6.42 seconds
Started Jul 11 04:58:16 PM PDT 24
Finished Jul 11 04:58:35 PM PDT 24
Peak memory 205036 kb
Host smart-27573a46-b7f4-4cbd-8bac-b740b662c076
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746623392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3746623392
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2548717194
Short name T174
Test name
Test status
Simulation time 498364356 ps
CPU time 3.83 seconds
Started Jul 11 04:58:11 PM PDT 24
Finished Jul 11 04:58:25 PM PDT 24
Peak memory 213172 kb
Host smart-40d6e948-829f-483e-acb0-54306328077a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548717194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2548717194
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3388974590
Short name T325
Test name
Test status
Simulation time 266416917 ps
CPU time 4.11 seconds
Started Jul 11 04:58:09 PM PDT 24
Finished Jul 11 04:58:23 PM PDT 24
Peak memory 221416 kb
Host smart-e83114b0-4751-4dc4-aeb9-bcb56526cc03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388974590 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3388974590
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.795729942
Short name T375
Test name
Test status
Simulation time 122296148 ps
CPU time 1.81 seconds
Started Jul 11 04:58:08 PM PDT 24
Finished Jul 11 04:58:19 PM PDT 24
Peak memory 213384 kb
Host smart-b221238e-0652-4faf-a646-262acf41735f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795729942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.795729942
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.116021872
Short name T418
Test name
Test status
Simulation time 50177894903 ps
CPU time 22.02 seconds
Started Jul 11 04:58:06 PM PDT 24
Finished Jul 11 04:58:37 PM PDT 24
Peak memory 204884 kb
Host smart-30553c3d-8298-45f2-859e-279186eed3ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116021872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.116021872
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3874969049
Short name T357
Test name
Test status
Simulation time 6751921416 ps
CPU time 18.08 seconds
Started Jul 11 04:58:08 PM PDT 24
Finished Jul 11 04:58:36 PM PDT 24
Peak memory 204968 kb
Host smart-fa0c217c-69a6-4d61-bd56-238c5b8d7924
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874969049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3874969049
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.161195500
Short name T310
Test name
Test status
Simulation time 463423453 ps
CPU time 1.13 seconds
Started Jul 11 04:58:01 PM PDT 24
Finished Jul 11 04:58:09 PM PDT 24
Peak memory 204688 kb
Host smart-3900344e-2293-4342-94ab-765856a11734
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161195500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.161195500
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4016625765
Short name T119
Test name
Test status
Simulation time 878104924 ps
CPU time 4.5 seconds
Started Jul 11 04:58:13 PM PDT 24
Finished Jul 11 04:58:30 PM PDT 24
Peak memory 205032 kb
Host smart-b16f34c1-adc9-46ca-b296-e24ec427c0c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016625765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.4016625765
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1456203118
Short name T385
Test name
Test status
Simulation time 230660492 ps
CPU time 3.49 seconds
Started Jul 11 04:58:09 PM PDT 24
Finished Jul 11 04:58:22 PM PDT 24
Peak memory 213228 kb
Host smart-c726d431-b89c-4953-a7d6-dbbc035301da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456203118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1456203118
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1146682309
Short name T330
Test name
Test status
Simulation time 1316857402 ps
CPU time 8.89 seconds
Started Jul 11 04:58:11 PM PDT 24
Finished Jul 11 04:58:31 PM PDT 24
Peak memory 213240 kb
Host smart-1f0eb302-fef1-4c02-9729-459b319c8b14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146682309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
146682309
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1973370367
Short name T433
Test name
Test status
Simulation time 693923149 ps
CPU time 4.01 seconds
Started Jul 11 04:58:05 PM PDT 24
Finished Jul 11 04:58:17 PM PDT 24
Peak memory 221296 kb
Host smart-14c9b7cd-b1ba-43b3-ab6d-79ebfcc8811c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973370367 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1973370367
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3124959096
Short name T93
Test name
Test status
Simulation time 150441119 ps
CPU time 2.45 seconds
Started Jul 11 04:58:16 PM PDT 24
Finished Jul 11 04:58:31 PM PDT 24
Peak memory 213240 kb
Host smart-4176920a-1a06-4134-9932-9d681b87c086
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124959096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3124959096
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.4197311426
Short name T299
Test name
Test status
Simulation time 17644779543 ps
CPU time 16.06 seconds
Started Jul 11 04:58:13 PM PDT 24
Finished Jul 11 04:58:40 PM PDT 24
Peak memory 204912 kb
Host smart-f659db77-cf01-4f6c-9ca9-0ea601a5b613
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197311426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.4197311426
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3739964650
Short name T370
Test name
Test status
Simulation time 2002107333 ps
CPU time 6.74 seconds
Started Jul 11 04:58:12 PM PDT 24
Finished Jul 11 04:58:29 PM PDT 24
Peak memory 204908 kb
Host smart-b64dbb02-6c93-4722-8aca-f0b6d7067981
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739964650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3739964650
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3334256741
Short name T83
Test name
Test status
Simulation time 381291720 ps
CPU time 1.12 seconds
Started Jul 11 04:58:10 PM PDT 24
Finished Jul 11 04:58:22 PM PDT 24
Peak memory 204664 kb
Host smart-e5e6a887-9a28-481a-973e-52c080499075
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334256741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3334256741
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1190432101
Short name T122
Test name
Test status
Simulation time 413672712 ps
CPU time 6.88 seconds
Started Jul 11 04:58:08 PM PDT 24
Finished Jul 11 04:58:24 PM PDT 24
Peak memory 205012 kb
Host smart-aa9eae1b-e2b5-47aa-96d0-0f72a31d6342
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190432101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1190432101
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3013258689
Short name T436
Test name
Test status
Simulation time 866343829 ps
CPU time 4.56 seconds
Started Jul 11 04:58:10 PM PDT 24
Finished Jul 11 04:58:24 PM PDT 24
Peak memory 213232 kb
Host smart-65b3e24f-d818-4ff8-ba2a-9e919cab629d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013258689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3013258689
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.822615251
Short name T382
Test name
Test status
Simulation time 1894590453 ps
CPU time 20.31 seconds
Started Jul 11 04:58:08 PM PDT 24
Finished Jul 11 04:58:38 PM PDT 24
Peak memory 213156 kb
Host smart-b3ca8799-cb33-442c-b209-a43ada9c379e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822615251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.822615251
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2051973487
Short name T308
Test name
Test status
Simulation time 1290378327 ps
CPU time 5.94 seconds
Started Jul 11 04:58:08 PM PDT 24
Finished Jul 11 04:58:24 PM PDT 24
Peak memory 219092 kb
Host smart-04147750-88ea-4038-abfa-eb074dea47c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051973487 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2051973487
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1563314561
Short name T97
Test name
Test status
Simulation time 91852425 ps
CPU time 1.46 seconds
Started Jul 11 04:58:06 PM PDT 24
Finished Jul 11 04:58:16 PM PDT 24
Peak memory 213236 kb
Host smart-c2bc7b35-40fa-4785-ba97-251e5400c679
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563314561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1563314561
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3667233674
Short name T356
Test name
Test status
Simulation time 31057096761 ps
CPU time 44.64 seconds
Started Jul 11 04:58:09 PM PDT 24
Finished Jul 11 04:59:03 PM PDT 24
Peak memory 204972 kb
Host smart-b6c0e05c-92de-4f26-96e2-64df1afc73f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667233674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.3667233674
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1599852214
Short name T348
Test name
Test status
Simulation time 2752719384 ps
CPU time 8.36 seconds
Started Jul 11 04:58:06 PM PDT 24
Finished Jul 11 04:58:23 PM PDT 24
Peak memory 204880 kb
Host smart-842f4919-e5b7-4b35-b101-15351bc19246
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599852214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1599852214
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3365611691
Short name T297
Test name
Test status
Simulation time 1042194051 ps
CPU time 1.81 seconds
Started Jul 11 04:58:07 PM PDT 24
Finished Jul 11 04:58:18 PM PDT 24
Peak memory 204664 kb
Host smart-565b1b30-e4c6-479b-b655-20b054a51208
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365611691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3365611691
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.2073978694
Short name T95
Test name
Test status
Simulation time 92599823 ps
CPU time 3.4 seconds
Started Jul 11 04:58:12 PM PDT 24
Finished Jul 11 04:58:27 PM PDT 24
Peak memory 205016 kb
Host smart-bb91aabe-19cd-498a-9cb3-fce318c945f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073978694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.2073978694
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2073467329
Short name T401
Test name
Test status
Simulation time 100150625 ps
CPU time 1.87 seconds
Started Jul 11 04:58:07 PM PDT 24
Finished Jul 11 04:58:17 PM PDT 24
Peak memory 213204 kb
Host smart-dcccfc17-ef21-487a-afee-33a5b714fad8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073467329 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2073467329
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2057507867
Short name T402
Test name
Test status
Simulation time 2612286962 ps
CPU time 11.14 seconds
Started Jul 11 04:58:07 PM PDT 24
Finished Jul 11 04:58:27 PM PDT 24
Peak memory 213208 kb
Host smart-01d7eeca-856e-4a61-8b6e-104f6db9f86f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057507867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
057507867
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2856895072
Short name T403
Test name
Test status
Simulation time 1857472583 ps
CPU time 33.15 seconds
Started Jul 11 04:57:58 PM PDT 24
Finished Jul 11 04:58:38 PM PDT 24
Peak memory 213460 kb
Host smart-bfa0c416-9bdb-41da-8a84-a9e716e2dc2e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856895072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2856895072
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.4032518585
Short name T399
Test name
Test status
Simulation time 1434581050 ps
CPU time 51.67 seconds
Started Jul 11 04:57:54 PM PDT 24
Finished Jul 11 04:58:54 PM PDT 24
Peak memory 213252 kb
Host smart-1a42d7ad-8b8b-436b-b14b-988d1e07efba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032518585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.4032518585
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1422762640
Short name T116
Test name
Test status
Simulation time 93708249 ps
CPU time 1.59 seconds
Started Jul 11 04:57:42 PM PDT 24
Finished Jul 11 04:57:53 PM PDT 24
Peak memory 213160 kb
Host smart-e3c4c533-e799-4a01-9b84-8751e864f328
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422762640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1422762640
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1260079834
Short name T302
Test name
Test status
Simulation time 189865850 ps
CPU time 2.54 seconds
Started Jul 11 04:57:55 PM PDT 24
Finished Jul 11 04:58:06 PM PDT 24
Peak memory 218304 kb
Host smart-1945cfb6-1c01-4ab2-9dd8-2bbdf984a2f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260079834 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1260079834
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2360980990
Short name T354
Test name
Test status
Simulation time 42177344 ps
CPU time 1.42 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:57:54 PM PDT 24
Peak memory 213252 kb
Host smart-7f3db3a2-5afc-4d70-b5b9-13af478b0cd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360980990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2360980990
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3035566812
Short name T346
Test name
Test status
Simulation time 20511601838 ps
CPU time 53.82 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:58:46 PM PDT 24
Peak memory 204988 kb
Host smart-a2bb0a6c-d18c-4b6a-ae7e-447a414336d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035566812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3035566812
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.855135564
Short name T335
Test name
Test status
Simulation time 5689565863 ps
CPU time 14.04 seconds
Started Jul 11 04:58:03 PM PDT 24
Finished Jul 11 04:58:25 PM PDT 24
Peak memory 204904 kb
Host smart-abc7a015-596b-46e5-a001-cdeb9f1fd058
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855135564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r
v_dm_jtag_dmi_csr_bit_bash.855135564
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.311547361
Short name T105
Test name
Test status
Simulation time 2688096817 ps
CPU time 8.22 seconds
Started Jul 11 04:57:51 PM PDT 24
Finished Jul 11 04:58:08 PM PDT 24
Peak memory 205080 kb
Host smart-60cfc966-d997-4076-b7d9-6fd127672213
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311547361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.311547361
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2786762475
Short name T292
Test name
Test status
Simulation time 8506677585 ps
CPU time 7.55 seconds
Started Jul 11 04:58:00 PM PDT 24
Finished Jul 11 04:58:15 PM PDT 24
Peak memory 204900 kb
Host smart-6d4e0350-e6a1-42f2-bdde-baa276fc8487
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786762475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
786762475
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.864448958
Short name T309
Test name
Test status
Simulation time 376099601 ps
CPU time 1.66 seconds
Started Jul 11 04:57:42 PM PDT 24
Finished Jul 11 04:57:53 PM PDT 24
Peak memory 204956 kb
Host smart-14dec86e-f2bf-4ee0-bc1c-cd217ada4c86
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864448958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.864448958
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1021050078
Short name T344
Test name
Test status
Simulation time 13686785154 ps
CPU time 9.95 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:59 PM PDT 24
Peak memory 204844 kb
Host smart-ca51f119-2aa3-463b-ac2e-9e0629a410e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021050078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1021050078
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3600584581
Short name T347
Test name
Test status
Simulation time 1554356885 ps
CPU time 1.38 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:57:53 PM PDT 24
Peak memory 204656 kb
Host smart-fcc8da7c-c2fc-4ff9-a13a-b2d184af1bdb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600584581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3600584581
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.864706946
Short name T301
Test name
Test status
Simulation time 404612696 ps
CPU time 0.99 seconds
Started Jul 11 04:58:02 PM PDT 24
Finished Jul 11 04:58:11 PM PDT 24
Peak memory 204684 kb
Host smart-5df2d69a-3bfb-47f1-a85a-eae2e30ce41b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864706946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.864706946
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3592920313
Short name T425
Test name
Test status
Simulation time 60220856 ps
CPU time 0.83 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:57:53 PM PDT 24
Peak memory 204580 kb
Host smart-7ac08603-5f34-46a3-a618-d3e736d8ddbf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592920313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3592920313
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4227029158
Short name T340
Test name
Test status
Simulation time 80463738 ps
CPU time 0.73 seconds
Started Jul 11 04:58:01 PM PDT 24
Finished Jul 11 04:58:09 PM PDT 24
Peak memory 204728 kb
Host smart-47490a3c-58a4-4006-9a2b-af59f95b00e5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227029158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.4227029158
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.798499502
Short name T423
Test name
Test status
Simulation time 161460765 ps
CPU time 6.52 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:56 PM PDT 24
Peak memory 204908 kb
Host smart-d030d8b2-53d7-4958-9987-4b82b26e1751
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798499502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.798499502
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2186862060
Short name T366
Test name
Test status
Simulation time 60230223967 ps
CPU time 58.28 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:58:51 PM PDT 24
Peak memory 224164 kb
Host smart-7d1a78be-08ba-45a2-9758-9e351fc7a6d9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186862060 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2186862060
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3735563658
Short name T420
Test name
Test status
Simulation time 180719428 ps
CPU time 2.22 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:51 PM PDT 24
Peak memory 213160 kb
Host smart-0e462ac7-7163-401e-ab4e-b0ab73a95b54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735563658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3735563658
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2236781716
Short name T106
Test name
Test status
Simulation time 4385467351 ps
CPU time 32.62 seconds
Started Jul 11 04:57:47 PM PDT 24
Finished Jul 11 04:58:28 PM PDT 24
Peak memory 213280 kb
Host smart-64f9dfc7-757f-43a7-968f-cae926cf9a33
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236781716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2236781716
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.625297053
Short name T337
Test name
Test status
Simulation time 7946043801 ps
CPU time 76.35 seconds
Started Jul 11 04:57:54 PM PDT 24
Finished Jul 11 04:59:18 PM PDT 24
Peak memory 213344 kb
Host smart-618d1e7e-df64-4223-a62f-314bd1625a7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625297053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.625297053
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.90474204
Short name T118
Test name
Test status
Simulation time 630501977 ps
CPU time 2.57 seconds
Started Jul 11 04:57:44 PM PDT 24
Finished Jul 11 04:57:56 PM PDT 24
Peak memory 213328 kb
Host smart-322c3cfb-1dd3-4432-86fa-c7fa1c8ee48b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90474204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.90474204
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1987201747
Short name T61
Test name
Test status
Simulation time 4400125166 ps
CPU time 5.83 seconds
Started Jul 11 04:57:51 PM PDT 24
Finished Jul 11 04:58:06 PM PDT 24
Peak memory 221528 kb
Host smart-1267237c-3413-4b55-9817-68f7305de181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987201747 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1987201747
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4088892222
Short name T432
Test name
Test status
Simulation time 190698959 ps
CPU time 2.27 seconds
Started Jul 11 04:57:51 PM PDT 24
Finished Jul 11 04:58:02 PM PDT 24
Peak memory 213248 kb
Host smart-eb52cae4-9d10-4ad9-bde8-c037d892d6d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088892222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.4088892222
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1647528602
Short name T371
Test name
Test status
Simulation time 14041701935 ps
CPU time 14.62 seconds
Started Jul 11 04:57:55 PM PDT 24
Finished Jul 11 04:58:18 PM PDT 24
Peak memory 204900 kb
Host smart-10b4eff9-4ed7-4dc4-bec3-aaecaf799af9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647528602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1647528602
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2406995204
Short name T412
Test name
Test status
Simulation time 9310946961 ps
CPU time 14.44 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:58:05 PM PDT 24
Peak memory 205200 kb
Host smart-2bffaf26-78f1-4db7-96af-ba62966cb980
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406995204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.2406995204
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3263634851
Short name T102
Test name
Test status
Simulation time 1656361567 ps
CPU time 2.02 seconds
Started Jul 11 04:58:01 PM PDT 24
Finished Jul 11 04:58:10 PM PDT 24
Peak memory 204980 kb
Host smart-60f530ef-1247-4806-8de2-1d5c5db4ae16
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263634851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3263634851
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1931586932
Short name T324
Test name
Test status
Simulation time 3901732801 ps
CPU time 4.64 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:54 PM PDT 24
Peak memory 205184 kb
Host smart-7e743606-ea10-48e0-bdd1-1bebdf6546ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931586932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
931586932
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2508584872
Short name T82
Test name
Test status
Simulation time 208510311 ps
CPU time 1.07 seconds
Started Jul 11 04:57:48 PM PDT 24
Finished Jul 11 04:57:58 PM PDT 24
Peak memory 204744 kb
Host smart-10dabb02-e4e7-40bc-be97-4e622ea875c9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508584872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2508584872
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3914997188
Short name T298
Test name
Test status
Simulation time 3510622484 ps
CPU time 3.58 seconds
Started Jul 11 04:57:53 PM PDT 24
Finished Jul 11 04:58:05 PM PDT 24
Peak memory 204944 kb
Host smart-cc58c579-3b97-4772-b1b4-cf970a468724
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914997188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3914997188
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1634620225
Short name T345
Test name
Test status
Simulation time 105954323 ps
CPU time 0.91 seconds
Started Jul 11 04:58:00 PM PDT 24
Finished Jul 11 04:58:08 PM PDT 24
Peak memory 204672 kb
Host smart-1539a4ef-acc7-4964-b39e-1477b7a86328
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634620225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1634620225
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1890054868
Short name T328
Test name
Test status
Simulation time 520268719 ps
CPU time 1.32 seconds
Started Jul 11 04:57:55 PM PDT 24
Finished Jul 11 04:58:05 PM PDT 24
Peak memory 204744 kb
Host smart-c46d1de6-6636-4837-81e3-cdb3da276393
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890054868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
890054868
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2861556868
Short name T410
Test name
Test status
Simulation time 33947797 ps
CPU time 0.71 seconds
Started Jul 11 04:58:05 PM PDT 24
Finished Jul 11 04:58:13 PM PDT 24
Peak memory 204600 kb
Host smart-45fc8362-45e8-4c48-99da-08567a32f223
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861556868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2861556868
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3783916149
Short name T431
Test name
Test status
Simulation time 81409229 ps
CPU time 0.7 seconds
Started Jul 11 04:57:51 PM PDT 24
Finished Jul 11 04:58:01 PM PDT 24
Peak memory 204712 kb
Host smart-544db520-94b9-4943-94d1-e0e43db0aafa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783916149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3783916149
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4163279629
Short name T405
Test name
Test status
Simulation time 125225243 ps
CPU time 3.62 seconds
Started Jul 11 04:57:48 PM PDT 24
Finished Jul 11 04:58:01 PM PDT 24
Peak memory 205040 kb
Host smart-107dc367-f0d1-4650-89dc-e3bc88c0a103
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163279629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.4163279629
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1571697134
Short name T87
Test name
Test status
Simulation time 234111364 ps
CPU time 5.16 seconds
Started Jul 11 04:57:54 PM PDT 24
Finished Jul 11 04:58:07 PM PDT 24
Peak memory 213232 kb
Host smart-f4da35d5-c06e-41cc-ae87-aaca1d57a4a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571697134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.1571697134
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3166398491
Short name T392
Test name
Test status
Simulation time 2134974978 ps
CPU time 11.11 seconds
Started Jul 11 04:57:44 PM PDT 24
Finished Jul 11 04:58:04 PM PDT 24
Peak memory 213216 kb
Host smart-d5561eeb-2b67-49ad-85a9-74c83b4004d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166398491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3166398491
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3173921185
Short name T111
Test name
Test status
Simulation time 8793179378 ps
CPU time 67.17 seconds
Started Jul 11 04:57:42 PM PDT 24
Finished Jul 11 04:58:58 PM PDT 24
Peak memory 205148 kb
Host smart-439ca01f-0354-48a6-ab98-39c5cfa89292
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173921185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3173921185
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.656206762
Short name T383
Test name
Test status
Simulation time 9798723793 ps
CPU time 65.12 seconds
Started Jul 11 04:58:08 PM PDT 24
Finished Jul 11 04:59:23 PM PDT 24
Peak memory 205148 kb
Host smart-fdc3bf25-1917-4943-bae2-283c23b4aa66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656206762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.656206762
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2104354796
Short name T414
Test name
Test status
Simulation time 440523033 ps
CPU time 2.51 seconds
Started Jul 11 04:57:45 PM PDT 24
Finished Jul 11 04:57:57 PM PDT 24
Peak memory 213276 kb
Host smart-82510749-f975-47e0-b21c-fdb0492d4c08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104354796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2104354796
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.789020758
Short name T311
Test name
Test status
Simulation time 281501006 ps
CPU time 2.33 seconds
Started Jul 11 04:57:56 PM PDT 24
Finished Jul 11 04:58:06 PM PDT 24
Peak memory 213224 kb
Host smart-1e2ffcf9-3cc8-4094-a85b-a57e401abfed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789020758 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.789020758
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1402331753
Short name T92
Test name
Test status
Simulation time 99041947 ps
CPU time 2.29 seconds
Started Jul 11 04:58:00 PM PDT 24
Finished Jul 11 04:58:10 PM PDT 24
Peak memory 213288 kb
Host smart-5fba9ff9-d709-4589-b978-9cb2a31614d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402331753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1402331753
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4114497471
Short name T304
Test name
Test status
Simulation time 99260972165 ps
CPU time 128.64 seconds
Started Jul 11 04:58:18 PM PDT 24
Finished Jul 11 05:00:39 PM PDT 24
Peak memory 204904 kb
Host smart-9fbffd2b-c3ef-416b-aa03-dda0c9aea47c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114497471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.4114497471
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.301131653
Short name T327
Test name
Test status
Simulation time 23787351028 ps
CPU time 18.21 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:58:16 PM PDT 24
Peak memory 204904 kb
Host smart-363163ba-07c9-4200-a6fd-f9100f3f7aaf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301131653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.301131653
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.620309680
Short name T104
Test name
Test status
Simulation time 5245322104 ps
CPU time 14.05 seconds
Started Jul 11 04:58:08 PM PDT 24
Finished Jul 11 04:58:31 PM PDT 24
Peak memory 204984 kb
Host smart-ed208342-78c5-4602-a149-2c7c3e858c6a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620309680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.620309680
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2395854512
Short name T393
Test name
Test status
Simulation time 997192236 ps
CPU time 3.5 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:57:55 PM PDT 24
Peak memory 204912 kb
Host smart-2c26565a-32d6-4bac-9574-fe021ae57e9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395854512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
395854512
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.247863554
Short name T380
Test name
Test status
Simulation time 2420984299 ps
CPU time 1.69 seconds
Started Jul 11 04:58:03 PM PDT 24
Finished Jul 11 04:58:12 PM PDT 24
Peak memory 204804 kb
Host smart-603f4178-65c0-4550-a70c-1acd90b2c715
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247863554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.247863554
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2388366365
Short name T294
Test name
Test status
Simulation time 12102332572 ps
CPU time 34.57 seconds
Started Jul 11 04:58:00 PM PDT 24
Finished Jul 11 04:58:42 PM PDT 24
Peak memory 204900 kb
Host smart-e5c08c08-3145-461f-b2ca-2766c616265f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388366365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2388366365
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1587806539
Short name T315
Test name
Test status
Simulation time 586201731 ps
CPU time 1.13 seconds
Started Jul 11 04:57:49 PM PDT 24
Finished Jul 11 04:58:00 PM PDT 24
Peak memory 204740 kb
Host smart-902aecb5-8e7c-4529-bb96-11360d814318
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587806539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1587806539
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2215292941
Short name T407
Test name
Test status
Simulation time 557782264 ps
CPU time 1.19 seconds
Started Jul 11 04:57:48 PM PDT 24
Finished Jul 11 04:57:59 PM PDT 24
Peak memory 204744 kb
Host smart-e990d0a7-de94-43ae-8ee2-04f53e64ef57
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215292941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
215292941
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3576737834
Short name T369
Test name
Test status
Simulation time 54007196 ps
CPU time 0.81 seconds
Started Jul 11 04:57:44 PM PDT 24
Finished Jul 11 04:57:54 PM PDT 24
Peak memory 204884 kb
Host smart-b5a7f1a2-1d36-4b39-aed1-b15552b4b6fc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576737834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3576737834
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3342014890
Short name T391
Test name
Test status
Simulation time 102671506 ps
CPU time 0.89 seconds
Started Jul 11 04:57:47 PM PDT 24
Finished Jul 11 04:57:57 PM PDT 24
Peak memory 204648 kb
Host smart-d54af1ac-2501-4991-9aa3-084e5300e781
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342014890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3342014890
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1466680569
Short name T388
Test name
Test status
Simulation time 764420185 ps
CPU time 6.74 seconds
Started Jul 11 04:58:02 PM PDT 24
Finished Jul 11 04:58:16 PM PDT 24
Peak memory 205088 kb
Host smart-02389a1a-ea1f-471a-a01d-673aef1ae7da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466680569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1466680569
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3043935298
Short name T413
Test name
Test status
Simulation time 52009944 ps
CPU time 2.45 seconds
Started Jul 11 04:57:50 PM PDT 24
Finished Jul 11 04:58:02 PM PDT 24
Peak memory 213240 kb
Host smart-229fd90d-bc97-4919-8248-91eea5eec015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043935298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3043935298
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.739680179
Short name T177
Test name
Test status
Simulation time 4420026634 ps
CPU time 19.87 seconds
Started Jul 11 04:57:44 PM PDT 24
Finished Jul 11 04:58:13 PM PDT 24
Peak memory 213368 kb
Host smart-bd9cbcd1-b31e-41c5-aa28-0a595e4c57e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739680179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.739680179
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4287454875
Short name T441
Test name
Test status
Simulation time 515903276 ps
CPU time 3.8 seconds
Started Jul 11 04:57:41 PM PDT 24
Finished Jul 11 04:57:54 PM PDT 24
Peak memory 219088 kb
Host smart-d3263abf-a001-43d3-82e0-9d2020af8356
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287454875 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.4287454875
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2239559886
Short name T386
Test name
Test status
Simulation time 210386840 ps
CPU time 1.98 seconds
Started Jul 11 04:57:49 PM PDT 24
Finished Jul 11 04:58:01 PM PDT 24
Peak memory 213152 kb
Host smart-6552fbc1-87ce-4d1e-806c-06d956e0ff2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239559886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2239559886
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1869460100
Short name T296
Test name
Test status
Simulation time 12735578932 ps
CPU time 12.26 seconds
Started Jul 11 04:57:59 PM PDT 24
Finished Jul 11 04:58:17 PM PDT 24
Peak memory 204908 kb
Host smart-ffb57ff6-9142-491f-ac07-742a5050e171
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869460100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.1869460100
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.434910712
Short name T429
Test name
Test status
Simulation time 2088859614 ps
CPU time 5.93 seconds
Started Jul 11 04:57:44 PM PDT 24
Finished Jul 11 04:58:00 PM PDT 24
Peak memory 205128 kb
Host smart-d808d61a-7825-4d66-b29d-00b99c786b1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434910712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.434910712
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.482454974
Short name T396
Test name
Test status
Simulation time 104214938 ps
CPU time 0.8 seconds
Started Jul 11 04:57:46 PM PDT 24
Finished Jul 11 04:57:56 PM PDT 24
Peak memory 204712 kb
Host smart-3339ee82-44ab-4be7-ab5d-3fca624f2d44
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482454974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.482454974
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3430098757
Short name T358
Test name
Test status
Simulation time 948024999 ps
CPU time 4.7 seconds
Started Jul 11 04:58:10 PM PDT 24
Finished Jul 11 04:58:25 PM PDT 24
Peak memory 205036 kb
Host smart-9e246265-e91e-4d9d-931f-14f1a7e0d6f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430098757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3430098757
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3382916690
Short name T415
Test name
Test status
Simulation time 376941849 ps
CPU time 4.64 seconds
Started Jul 11 04:57:54 PM PDT 24
Finished Jul 11 04:58:07 PM PDT 24
Peak memory 213240 kb
Host smart-60d89c0e-b2b3-4536-a391-6b8a622e728d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382916690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3382916690
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3105370230
Short name T411
Test name
Test status
Simulation time 229372633 ps
CPU time 4.14 seconds
Started Jul 11 04:57:53 PM PDT 24
Finished Jul 11 04:58:06 PM PDT 24
Peak memory 221416 kb
Host smart-ca3594cb-b668-49a4-96ed-892c10b548c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105370230 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3105370230
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3124366631
Short name T117
Test name
Test status
Simulation time 107538048 ps
CPU time 2.35 seconds
Started Jul 11 04:58:02 PM PDT 24
Finished Jul 11 04:58:12 PM PDT 24
Peak memory 213180 kb
Host smart-d99bd335-9efa-4d43-97f8-937547ea3954
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124366631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3124366631
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.20808562
Short name T417
Test name
Test status
Simulation time 1744446322 ps
CPU time 2.14 seconds
Started Jul 11 04:57:55 PM PDT 24
Finished Jul 11 04:58:05 PM PDT 24
Peak memory 204784 kb
Host smart-5253af35-a225-4258-9ba6-bdb1603e5a6f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20808562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv
_dm_jtag_dmi_csr_bit_bash.20808562
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.528512349
Short name T416
Test name
Test status
Simulation time 3513647640 ps
CPU time 2.9 seconds
Started Jul 11 04:57:53 PM PDT 24
Finished Jul 11 04:58:05 PM PDT 24
Peak memory 204900 kb
Host smart-ae2a3ed1-8d2b-49ca-ac8c-82faa363d066
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528512349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.528512349
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3549255179
Short name T351
Test name
Test status
Simulation time 469507350 ps
CPU time 1.74 seconds
Started Jul 11 04:57:43 PM PDT 24
Finished Jul 11 04:57:53 PM PDT 24
Peak memory 204636 kb
Host smart-4d1e5f50-d2ce-44ad-b7b9-dc8e8c73f4eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549255179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
549255179
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1787821730
Short name T439
Test name
Test status
Simulation time 2623768777 ps
CPU time 4.41 seconds
Started Jul 11 04:58:00 PM PDT 24
Finished Jul 11 04:58:12 PM PDT 24
Peak memory 205096 kb
Host smart-4c939b46-ee77-44d5-baae-bcb833184741
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787821730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1787821730
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.2557456439
Short name T379
Test name
Test status
Simulation time 44927845319 ps
CPU time 75.9 seconds
Started Jul 11 04:58:00 PM PDT 24
Finished Jul 11 04:59:24 PM PDT 24
Peak memory 221452 kb
Host smart-90cced97-2cbb-4426-ba6a-2b3e9cb94254
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557456439 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.2557456439
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2049348645
Short name T355
Test name
Test status
Simulation time 214897517 ps
CPU time 4.64 seconds
Started Jul 11 04:57:54 PM PDT 24
Finished Jul 11 04:58:07 PM PDT 24
Peak memory 213240 kb
Host smart-85faa59b-deb5-4fea-affa-325970b12533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049348645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2049348645
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2786918176
Short name T183
Test name
Test status
Simulation time 6769644661 ps
CPU time 24.72 seconds
Started Jul 11 04:57:50 PM PDT 24
Finished Jul 11 04:58:24 PM PDT 24
Peak memory 221452 kb
Host smart-8569edb3-265c-4975-961e-d680a6aeb6c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786918176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2786918176
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.278804399
Short name T90
Test name
Test status
Simulation time 305800663 ps
CPU time 4.63 seconds
Started Jul 11 04:58:06 PM PDT 24
Finished Jul 11 04:58:18 PM PDT 24
Peak memory 221128 kb
Host smart-89c1f0a7-b0d2-417b-894a-a18b5fddcbca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278804399 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.278804399
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.349146335
Short name T115
Test name
Test status
Simulation time 140134715 ps
CPU time 2.08 seconds
Started Jul 11 04:57:59 PM PDT 24
Finished Jul 11 04:58:07 PM PDT 24
Peak memory 213228 kb
Host smart-0f12beb9-4848-4d10-8f0b-573c63740f43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349146335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.349146335
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.4151339224
Short name T313
Test name
Test status
Simulation time 16230477565 ps
CPU time 10.72 seconds
Started Jul 11 04:58:00 PM PDT 24
Finished Jul 11 04:58:18 PM PDT 24
Peak memory 205180 kb
Host smart-def17bd5-438f-4b37-9454-c347e1802da4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151339224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.4151339224
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3352945830
Short name T374
Test name
Test status
Simulation time 9803952896 ps
CPU time 24.35 seconds
Started Jul 11 04:57:56 PM PDT 24
Finished Jul 11 04:58:28 PM PDT 24
Peak memory 204848 kb
Host smart-9c1d7732-7f95-4424-a410-a6981dcf0259
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352945830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
352945830
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2707055511
Short name T384
Test name
Test status
Simulation time 881572988 ps
CPU time 2.93 seconds
Started Jul 11 04:58:05 PM PDT 24
Finished Jul 11 04:58:16 PM PDT 24
Peak memory 204664 kb
Host smart-bb39780f-ac71-49d0-95d7-0bbc302bb26e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707055511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
707055511
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2456343825
Short name T121
Test name
Test status
Simulation time 482799091 ps
CPU time 3.75 seconds
Started Jul 11 04:58:05 PM PDT 24
Finished Jul 11 04:58:16 PM PDT 24
Peak memory 204960 kb
Host smart-fa173cc2-d6da-4142-8f15-da1b64c6bc60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456343825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2456343825
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1570121662
Short name T317
Test name
Test status
Simulation time 352054504 ps
CPU time 5.04 seconds
Started Jul 11 04:58:09 PM PDT 24
Finished Jul 11 04:58:24 PM PDT 24
Peak memory 213240 kb
Host smart-3259a748-ac09-4fa2-aa45-d273e94ad4cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570121662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1570121662
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1298491838
Short name T180
Test name
Test status
Simulation time 3902759761 ps
CPU time 11.78 seconds
Started Jul 11 04:57:55 PM PDT 24
Finished Jul 11 04:58:20 PM PDT 24
Peak memory 213192 kb
Host smart-268979bc-903a-4ccd-bfc5-ecde7358cead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298491838 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1298491838
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1172852795
Short name T353
Test name
Test status
Simulation time 1495337259 ps
CPU time 4.27 seconds
Started Jul 11 04:58:00 PM PDT 24
Finished Jul 11 04:58:11 PM PDT 24
Peak memory 213308 kb
Host smart-0a57993e-6d71-440c-9e75-07ed2fab9428
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172852795 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1172852795
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2905968287
Short name T107
Test name
Test status
Simulation time 139165378 ps
CPU time 1.7 seconds
Started Jul 11 04:57:56 PM PDT 24
Finished Jul 11 04:58:06 PM PDT 24
Peak memory 213464 kb
Host smart-5f69baf3-f5db-441f-8f87-4431b8199126
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905968287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2905968287
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2169538370
Short name T363
Test name
Test status
Simulation time 57641128071 ps
CPU time 19.2 seconds
Started Jul 11 04:57:49 PM PDT 24
Finished Jul 11 04:58:17 PM PDT 24
Peak memory 204940 kb
Host smart-3f7d8542-116a-43c8-a36c-4bd0bb287a7a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169538370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.2169538370
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4050846149
Short name T430
Test name
Test status
Simulation time 1870639006 ps
CPU time 2.31 seconds
Started Jul 11 04:58:07 PM PDT 24
Finished Jul 11 04:58:18 PM PDT 24
Peak memory 204908 kb
Host smart-eb68dc30-5e91-48ee-8915-7c3766104ba3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050846149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.4
050846149
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.672908049
Short name T422
Test name
Test status
Simulation time 156684663 ps
CPU time 0.84 seconds
Started Jul 11 04:58:02 PM PDT 24
Finished Jul 11 04:58:10 PM PDT 24
Peak memory 204740 kb
Host smart-7d1a3d95-469b-4a4c-8ea0-e4ba925f1168
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672908049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.672908049
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1228808513
Short name T112
Test name
Test status
Simulation time 653097879 ps
CPU time 7.96 seconds
Started Jul 11 04:58:05 PM PDT 24
Finished Jul 11 04:58:22 PM PDT 24
Peak memory 204944 kb
Host smart-c8f3c3c1-c0a6-4aa1-85cb-403bfe432317
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228808513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1228808513
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3278563330
Short name T428
Test name
Test status
Simulation time 15957762592 ps
CPU time 15.84 seconds
Started Jul 11 04:58:04 PM PDT 24
Finished Jul 11 04:58:28 PM PDT 24
Peak memory 221448 kb
Host smart-5d4fd52d-f065-4b0e-8a98-82e9b6e351f3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278563330 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3278563330
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1445684092
Short name T62
Test name
Test status
Simulation time 265702923 ps
CPU time 5.69 seconds
Started Jul 11 04:58:04 PM PDT 24
Finished Jul 11 04:58:17 PM PDT 24
Peak memory 213156 kb
Host smart-c36779ad-15ec-4736-958e-1a6e521bcf5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445684092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1445684092
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1740276365
Short name T426
Test name
Test status
Simulation time 1634055458 ps
CPU time 8.66 seconds
Started Jul 11 04:58:09 PM PDT 24
Finished Jul 11 04:58:28 PM PDT 24
Peak memory 213240 kb
Host smart-997ec695-65e5-4d2c-9dca-8eb631715e2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740276365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1740276365
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3663055901
Short name T400
Test name
Test status
Simulation time 321129503 ps
CPU time 2.45 seconds
Started Jul 11 04:58:05 PM PDT 24
Finished Jul 11 04:58:16 PM PDT 24
Peak memory 221380 kb
Host smart-acf896b4-9034-43b2-8d79-2ddd50fa8173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663055901 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3663055901
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3725169699
Short name T109
Test name
Test status
Simulation time 57068713 ps
CPU time 2.22 seconds
Started Jul 11 04:57:55 PM PDT 24
Finished Jul 11 04:58:06 PM PDT 24
Peak memory 213232 kb
Host smart-c2dc8487-08f3-40ff-b89a-47b64a3ee893
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725169699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3725169699
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1238512650
Short name T295
Test name
Test status
Simulation time 67972043064 ps
CPU time 93.38 seconds
Started Jul 11 04:57:55 PM PDT 24
Finished Jul 11 04:59:37 PM PDT 24
Peak memory 204904 kb
Host smart-d8f619f6-9a32-4343-8df9-efe7100ff23c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238512650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.1238512650
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1913866762
Short name T427
Test name
Test status
Simulation time 7077153105 ps
CPU time 8.3 seconds
Started Jul 11 04:58:08 PM PDT 24
Finished Jul 11 04:58:26 PM PDT 24
Peak memory 204868 kb
Host smart-050e8bc6-a7a0-460b-a400-8feb1daf5e2e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913866762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
913866762
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.867768698
Short name T320
Test name
Test status
Simulation time 174212406 ps
CPU time 1.14 seconds
Started Jul 11 04:57:55 PM PDT 24
Finished Jul 11 04:58:05 PM PDT 24
Peak memory 204656 kb
Host smart-d1606d8d-aa7f-4d0b-9ab4-92812ede469e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867768698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.867768698
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.486636148
Short name T114
Test name
Test status
Simulation time 639840289 ps
CPU time 7.78 seconds
Started Jul 11 04:58:00 PM PDT 24
Finished Jul 11 04:58:15 PM PDT 24
Peak memory 204952 kb
Host smart-5dfe1a4d-0813-474f-b39c-814eb4d8a657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486636148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.486636148
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2439044381
Short name T404
Test name
Test status
Simulation time 192042991 ps
CPU time 2.71 seconds
Started Jul 11 04:57:55 PM PDT 24
Finished Jul 11 04:58:06 PM PDT 24
Peak memory 213300 kb
Host smart-30781d1b-cd07-419a-b1a7-0e517308e825
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439044381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2439044381
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1991372747
Short name T179
Test name
Test status
Simulation time 2332304725 ps
CPU time 12.3 seconds
Started Jul 11 04:58:06 PM PDT 24
Finished Jul 11 04:58:26 PM PDT 24
Peak memory 213300 kb
Host smart-93d49a40-9b11-40e1-8ed5-821c7c9d968d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991372747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1991372747
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3666264197
Short name T201
Test name
Test status
Simulation time 128215495 ps
CPU time 1.03 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:00 PM PDT 24
Peak memory 205368 kb
Host smart-a5f1dbaf-4440-4c4e-980a-b1801a6d36c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666264197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3666264197
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1207486324
Short name T275
Test name
Test status
Simulation time 7063409536 ps
CPU time 19.17 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:18 PM PDT 24
Peak memory 213812 kb
Host smart-9d22a441-a2b3-40a3-8465-631dfa3a11d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207486324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1207486324
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.495761288
Short name T285
Test name
Test status
Simulation time 759438358 ps
CPU time 1.23 seconds
Started Jul 11 06:23:52 PM PDT 24
Finished Jul 11 06:24:01 PM PDT 24
Peak memory 205312 kb
Host smart-58fe3961-54ec-4af7-bbe0-d9405879722b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495761288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.495761288
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.4229846471
Short name T22
Test name
Test status
Simulation time 908203225 ps
CPU time 1.28 seconds
Started Jul 11 06:23:49 PM PDT 24
Finished Jul 11 06:23:58 PM PDT 24
Peak memory 205344 kb
Host smart-f3363132-73b5-4c4b-961b-6d1b8ad946ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229846471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.4229846471
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.432482776
Short name T284
Test name
Test status
Simulation time 198705779 ps
CPU time 1.21 seconds
Started Jul 11 06:23:47 PM PDT 24
Finished Jul 11 06:23:56 PM PDT 24
Peak memory 205376 kb
Host smart-e7f71db3-514d-49c3-82a6-48596423c373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432482776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.432482776
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2434196484
Short name T30
Test name
Test status
Simulation time 152750484 ps
CPU time 0.73 seconds
Started Jul 11 06:23:49 PM PDT 24
Finished Jul 11 06:23:57 PM PDT 24
Peak memory 205308 kb
Host smart-e70cc254-a0f8-4c7b-b46d-0ec14d737188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434196484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2434196484
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3287184076
Short name T234
Test name
Test status
Simulation time 918179013 ps
CPU time 2.34 seconds
Started Jul 11 06:23:49 PM PDT 24
Finished Jul 11 06:23:59 PM PDT 24
Peak memory 205576 kb
Host smart-a59c2922-25ea-4117-898a-88b8fe732472
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3287184076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3287184076
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3022106099
Short name T197
Test name
Test status
Simulation time 383373274 ps
CPU time 1.7 seconds
Started Jul 11 06:23:52 PM PDT 24
Finished Jul 11 06:24:01 PM PDT 24
Peak memory 205336 kb
Host smart-360afa5c-f955-4505-b929-3e8aaa57fea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022106099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3022106099
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3948566551
Short name T219
Test name
Test status
Simulation time 156746898 ps
CPU time 0.98 seconds
Started Jul 11 06:23:50 PM PDT 24
Finished Jul 11 06:23:58 PM PDT 24
Peak memory 205368 kb
Host smart-0896429f-4851-48c1-a439-f90435b399f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948566551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3948566551
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2374699913
Short name T276
Test name
Test status
Simulation time 1501962297 ps
CPU time 4.71 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:03 PM PDT 24
Peak memory 205384 kb
Host smart-e759434d-a655-4dfc-87e0-3b8c224e2fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374699913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2374699913
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.23709413
Short name T257
Test name
Test status
Simulation time 1033602323 ps
CPU time 1.09 seconds
Started Jul 11 06:23:52 PM PDT 24
Finished Jul 11 06:24:01 PM PDT 24
Peak memory 205348 kb
Host smart-2d8da765-cab2-435e-90c8-759baac44a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23709413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.23709413
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3296220818
Short name T211
Test name
Test status
Simulation time 219755736 ps
CPU time 0.76 seconds
Started Jul 11 06:23:45 PM PDT 24
Finished Jul 11 06:23:53 PM PDT 24
Peak memory 205348 kb
Host smart-a1cd680e-3f03-445c-be7d-a07beb0aad46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296220818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3296220818
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3369840792
Short name T196
Test name
Test status
Simulation time 643379077 ps
CPU time 2.15 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:01 PM PDT 24
Peak memory 205384 kb
Host smart-8afd0983-be5f-4259-b017-2de09d31370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369840792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3369840792
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3086888146
Short name T191
Test name
Test status
Simulation time 561047333 ps
CPU time 2.23 seconds
Started Jul 11 06:23:46 PM PDT 24
Finished Jul 11 06:23:56 PM PDT 24
Peak memory 205372 kb
Host smart-bc6f84f2-3c1f-40d8-b049-18b71afa8120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086888146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3086888146
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.979800830
Short name T255
Test name
Test status
Simulation time 213502864 ps
CPU time 0.97 seconds
Started Jul 11 06:23:52 PM PDT 24
Finished Jul 11 06:24:00 PM PDT 24
Peak memory 205336 kb
Host smart-f8aa977f-76a7-4d82-93dc-a8d817ca7dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979800830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.979800830
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.2832718759
Short name T41
Test name
Test status
Simulation time 581471917 ps
CPU time 1.5 seconds
Started Jul 11 06:23:49 PM PDT 24
Finished Jul 11 06:23:58 PM PDT 24
Peak memory 205364 kb
Host smart-c06b8bf0-a15c-4dee-85ac-c6b1ef20e53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832718759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2832718759
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3322927994
Short name T54
Test name
Test status
Simulation time 1640834489 ps
CPU time 1.97 seconds
Started Jul 11 06:23:52 PM PDT 24
Finished Jul 11 06:24:01 PM PDT 24
Peak memory 228752 kb
Host smart-4affc5ef-8346-45ca-b0e7-2dca771c0f7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322927994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3322927994
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3751088685
Short name T207
Test name
Test status
Simulation time 1719934075 ps
CPU time 3.02 seconds
Started Jul 11 06:23:49 PM PDT 24
Finished Jul 11 06:24:00 PM PDT 24
Peak memory 205332 kb
Host smart-a938d818-8d2e-41dc-9101-69d6071f5583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751088685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3751088685
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.117774255
Short name T7
Test name
Test status
Simulation time 569909234 ps
CPU time 2.13 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:01 PM PDT 24
Peak memory 205348 kb
Host smart-d1432e3f-f49e-4047-9fe3-1d25c33cd58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117774255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.117774255
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.412615151
Short name T256
Test name
Test status
Simulation time 118119971 ps
CPU time 0.71 seconds
Started Jul 11 06:23:50 PM PDT 24
Finished Jul 11 06:23:57 PM PDT 24
Peak memory 205340 kb
Host smart-014e3e57-822a-4f8e-b88a-4294a22e3e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412615151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.412615151
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2184965150
Short name T19
Test name
Test status
Simulation time 42848728503 ps
CPU time 113.52 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:25:52 PM PDT 24
Peak memory 213868 kb
Host smart-17ac0bac-f543-4013-8783-42dfb5e003eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184965150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2184965150
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2895435371
Short name T253
Test name
Test status
Simulation time 11682348833 ps
CPU time 29.25 seconds
Started Jul 11 06:23:55 PM PDT 24
Finished Jul 11 06:24:32 PM PDT 24
Peak memory 213912 kb
Host smart-f40364af-54f2-430d-9333-bce4f90854b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895435371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2895435371
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1926054841
Short name T193
Test name
Test status
Simulation time 203232584 ps
CPU time 1 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:23:59 PM PDT 24
Peak memory 205380 kb
Host smart-2a892f6e-790b-4272-a07d-4658973dd3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926054841 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1926054841
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2389327709
Short name T11
Test name
Test status
Simulation time 847237055 ps
CPU time 2.99 seconds
Started Jul 11 06:23:54 PM PDT 24
Finished Jul 11 06:24:05 PM PDT 24
Peak memory 205256 kb
Host smart-3cbb95b0-d1e6-47c3-9586-a25fb5e30c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389327709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2389327709
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.3786971551
Short name T34
Test name
Test status
Simulation time 225806388 ps
CPU time 0.85 seconds
Started Jul 11 06:23:56 PM PDT 24
Finished Jul 11 06:24:06 PM PDT 24
Peak memory 205380 kb
Host smart-a220590d-906b-4bef-a3aa-6c8fde695633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786971551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.3786971551
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2445751944
Short name T187
Test name
Test status
Simulation time 228385077 ps
CPU time 0.84 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:23:59 PM PDT 24
Peak memory 205324 kb
Host smart-847fb22d-5c2a-490e-84b9-631ebddbef9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445751944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2445751944
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.675229871
Short name T52
Test name
Test status
Simulation time 117251128 ps
CPU time 1.04 seconds
Started Jul 11 06:23:53 PM PDT 24
Finished Jul 11 06:24:02 PM PDT 24
Peak memory 215704 kb
Host smart-fbf7cd6e-09a5-4b8f-ba07-72426f53be68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675229871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.675229871
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1914914362
Short name T283
Test name
Test status
Simulation time 8728015340 ps
CPU time 7.69 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:06 PM PDT 24
Peak memory 213880 kb
Host smart-5afc1991-95a5-4bd3-b0b5-3d67735e8dc9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1914914362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.1914914362
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1423936319
Short name T40
Test name
Test status
Simulation time 565403961 ps
CPU time 0.95 seconds
Started Jul 11 06:23:56 PM PDT 24
Finished Jul 11 06:24:06 PM PDT 24
Peak memory 205384 kb
Host smart-683e810d-be18-4700-a4a6-ba07a11e62d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423936319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1423936319
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2919222126
Short name T71
Test name
Test status
Simulation time 972300011 ps
CPU time 2.78 seconds
Started Jul 11 06:23:52 PM PDT 24
Finished Jul 11 06:24:03 PM PDT 24
Peak memory 205376 kb
Host smart-69217a18-1a4d-4d1c-af23-5e6ec95a268c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919222126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2919222126
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1018679736
Short name T280
Test name
Test status
Simulation time 602074733 ps
CPU time 1.58 seconds
Started Jul 11 06:23:50 PM PDT 24
Finished Jul 11 06:23:59 PM PDT 24
Peak memory 205336 kb
Host smart-447d4bb4-87ad-4eeb-bee9-d5b013718332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018679736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1018679736
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.17175064
Short name T274
Test name
Test status
Simulation time 589888688 ps
CPU time 1.16 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:00 PM PDT 24
Peak memory 205368 kb
Host smart-19ace369-725b-4e00-bfd4-5efeeee7fe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17175064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.17175064
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2123345643
Short name T270
Test name
Test status
Simulation time 1529050360 ps
CPU time 1.97 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:01 PM PDT 24
Peak memory 205512 kb
Host smart-d32c20ee-e1c6-45f2-ad58-b9014ed042eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123345643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2123345643
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3208185027
Short name T50
Test name
Test status
Simulation time 681423276 ps
CPU time 1.33 seconds
Started Jul 11 06:23:53 PM PDT 24
Finished Jul 11 06:24:03 PM PDT 24
Peak memory 204684 kb
Host smart-c087d964-fdf2-484d-a2f8-c62c4c25f1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208185027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3208185027
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.760365660
Short name T134
Test name
Test status
Simulation time 1436461297 ps
CPU time 2.51 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:00 PM PDT 24
Peak memory 205368 kb
Host smart-39c2d40f-850b-48c2-8962-04b53b791415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760365660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.760365660
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1658244968
Short name T8
Test name
Test status
Simulation time 285709093 ps
CPU time 1.61 seconds
Started Jul 11 06:23:54 PM PDT 24
Finished Jul 11 06:24:03 PM PDT 24
Peak memory 205308 kb
Host smart-bd61406a-826d-449b-b49c-37419d07a22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658244968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1658244968
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3027030371
Short name T198
Test name
Test status
Simulation time 193848691 ps
CPU time 0.79 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:23:59 PM PDT 24
Peak memory 205368 kb
Host smart-ab6ad50c-2913-4108-8d14-4eb2d7d959dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027030371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3027030371
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.549801283
Short name T45
Test name
Test status
Simulation time 482512494 ps
CPU time 2.07 seconds
Started Jul 11 06:23:53 PM PDT 24
Finished Jul 11 06:24:03 PM PDT 24
Peak memory 205336 kb
Host smart-cc3c8592-b627-433f-9db0-347449ce4bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549801283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.549801283
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.361229987
Short name T39
Test name
Test status
Simulation time 208525933 ps
CPU time 0.97 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:00 PM PDT 24
Peak memory 213648 kb
Host smart-d7bc7724-e0e4-40f1-95eb-a82adefe3060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361229987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.361229987
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2017936848
Short name T86
Test name
Test status
Simulation time 2188071333 ps
CPU time 2.42 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:01 PM PDT 24
Peak memory 205588 kb
Host smart-8eaf54f9-03e5-4057-b678-61d1c400d6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017936848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2017936848
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2524788892
Short name T167
Test name
Test status
Simulation time 2672792692 ps
CPU time 7.37 seconds
Started Jul 11 06:23:55 PM PDT 24
Finished Jul 11 06:24:11 PM PDT 24
Peak memory 205596 kb
Host smart-8846d764-48b9-44de-8453-d9a901c2b47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524788892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2524788892
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3451674518
Short name T64
Test name
Test status
Simulation time 1402339846 ps
CPU time 2.76 seconds
Started Jul 11 06:23:53 PM PDT 24
Finished Jul 11 06:24:04 PM PDT 24
Peak memory 237328 kb
Host smart-ecd5b7dd-e173-4e08-8b17-4847a079a905
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451674518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3451674518
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1271448992
Short name T272
Test name
Test status
Simulation time 1317189422 ps
CPU time 1.55 seconds
Started Jul 11 06:23:54 PM PDT 24
Finished Jul 11 06:24:03 PM PDT 24
Peak memory 205464 kb
Host smart-5b9a11be-32a3-47db-a7d4-c94508e9080a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271448992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1271448992
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3806722600
Short name T203
Test name
Test status
Simulation time 94220846 ps
CPU time 0.84 seconds
Started Jul 11 06:24:02 PM PDT 24
Finished Jul 11 06:24:11 PM PDT 24
Peak memory 205280 kb
Host smart-b3c14f9b-6c7b-405c-acd1-12227822253b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806722600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3806722600
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3957912063
Short name T265
Test name
Test status
Simulation time 10476451310 ps
CPU time 7.64 seconds
Started Jul 11 06:24:07 PM PDT 24
Finished Jul 11 06:24:22 PM PDT 24
Peak memory 205660 kb
Host smart-485aa0e4-a929-4a62-9cde-261822f3ce79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957912063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3957912063
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3572241665
Short name T232
Test name
Test status
Simulation time 5780693101 ps
CPU time 15.57 seconds
Started Jul 11 06:24:03 PM PDT 24
Finished Jul 11 06:24:27 PM PDT 24
Peak memory 205720 kb
Host smart-200b59c8-ed45-4e32-847a-59e57a390993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572241665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3572241665
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.1741451248
Short name T3
Test name
Test status
Simulation time 88691581 ps
CPU time 0.77 seconds
Started Jul 11 06:24:02 PM PDT 24
Finished Jul 11 06:24:12 PM PDT 24
Peak memory 205368 kb
Host smart-8f05a7f6-a46a-401e-869f-c0de6c85b546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741451248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.1741451248
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3333759191
Short name T261
Test name
Test status
Simulation time 14246801020 ps
CPU time 40.74 seconds
Started Jul 11 06:24:02 PM PDT 24
Finished Jul 11 06:24:52 PM PDT 24
Peak memory 214000 kb
Host smart-2a991fe3-fc29-46a9-87e4-35856d65d28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333759191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3333759191
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1480953194
Short name T74
Test name
Test status
Simulation time 3124103629 ps
CPU time 2.42 seconds
Started Jul 11 06:24:01 PM PDT 24
Finished Jul 11 06:24:12 PM PDT 24
Peak memory 205624 kb
Host smart-bbc8ab6f-1864-4025-aa3c-547de22b7c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480953194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1480953194
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3152845462
Short name T205
Test name
Test status
Simulation time 97211127 ps
CPU time 0.84 seconds
Started Jul 11 06:24:03 PM PDT 24
Finished Jul 11 06:24:13 PM PDT 24
Peak memory 205364 kb
Host smart-84829309-cd92-43a5-9c44-a7e275a3f71b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152845462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3152845462
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3634974664
Short name T132
Test name
Test status
Simulation time 3196733815 ps
CPU time 5.81 seconds
Started Jul 11 06:24:01 PM PDT 24
Finished Jul 11 06:24:16 PM PDT 24
Peak memory 213876 kb
Host smart-a1c70a74-047d-49ce-9929-7450961390d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634974664 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3634974664
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2433993133
Short name T59
Test name
Test status
Simulation time 14514055327 ps
CPU time 11.26 seconds
Started Jul 11 06:24:12 PM PDT 24
Finished Jul 11 06:24:31 PM PDT 24
Peak memory 213676 kb
Host smart-8d81e296-e2fb-43f1-8019-363e99079813
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2433993133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2433993133
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3225734408
Short name T36
Test name
Test status
Simulation time 3360842388 ps
CPU time 3.88 seconds
Started Jul 11 06:24:02 PM PDT 24
Finished Jul 11 06:24:15 PM PDT 24
Peak memory 205596 kb
Host smart-3c6deecc-dd56-494f-bfd1-ce500452aa55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225734408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3225734408
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2513090801
Short name T251
Test name
Test status
Simulation time 134812906 ps
CPU time 0.75 seconds
Started Jul 11 06:24:06 PM PDT 24
Finished Jul 11 06:24:15 PM PDT 24
Peak memory 205364 kb
Host smart-896fc71a-db15-4260-80de-b2ef20d263bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513090801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2513090801
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.538620150
Short name T263
Test name
Test status
Simulation time 46777317871 ps
CPU time 105.16 seconds
Started Jul 11 06:24:17 PM PDT 24
Finished Jul 11 06:26:08 PM PDT 24
Peak memory 214188 kb
Host smart-1e5d74ac-04a0-4941-a54a-6bfbe01cc29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538620150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.538620150
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1138533157
Short name T286
Test name
Test status
Simulation time 5399091788 ps
CPU time 9.24 seconds
Started Jul 11 06:24:07 PM PDT 24
Finished Jul 11 06:24:24 PM PDT 24
Peak memory 215288 kb
Host smart-e69752fc-2dc3-44ba-b447-d641ed1bbf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138533157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1138533157
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.437841097
Short name T80
Test name
Test status
Simulation time 2330956296 ps
CPU time 4.52 seconds
Started Jul 11 06:24:07 PM PDT 24
Finished Jul 11 06:24:19 PM PDT 24
Peak memory 213872 kb
Host smart-b22aec42-5e77-44f1-8bca-7a9d0e948db1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=437841097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.437841097
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.1519319574
Short name T149
Test name
Test status
Simulation time 2618659134 ps
CPU time 4.54 seconds
Started Jul 11 06:24:05 PM PDT 24
Finished Jul 11 06:24:18 PM PDT 24
Peak memory 205572 kb
Host smart-3474e33a-f0fe-4236-8a4b-43dad339026d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519319574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.1519319574
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3489233672
Short name T161
Test name
Test status
Simulation time 18056831696 ps
CPU time 42.89 seconds
Started Jul 11 06:24:04 PM PDT 24
Finished Jul 11 06:24:56 PM PDT 24
Peak memory 205580 kb
Host smart-dbc18dd6-05b4-43b8-b2e0-8f5cb3b3af69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489233672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3489233672
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1427284963
Short name T260
Test name
Test status
Simulation time 14571601217 ps
CPU time 5.78 seconds
Started Jul 11 06:24:12 PM PDT 24
Finished Jul 11 06:24:25 PM PDT 24
Peak memory 213868 kb
Host smart-5a5ac6ac-77db-42cf-bacc-3f171c535649
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1427284963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1427284963
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.347143152
Short name T281
Test name
Test status
Simulation time 2687080731 ps
CPU time 2.88 seconds
Started Jul 11 06:24:07 PM PDT 24
Finished Jul 11 06:24:18 PM PDT 24
Peak memory 213860 kb
Host smart-520ee49b-d399-4661-9d0c-a278cd7fcf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347143152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.347143152
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.3421028080
Short name T192
Test name
Test status
Simulation time 5438180750 ps
CPU time 8.1 seconds
Started Jul 11 06:24:07 PM PDT 24
Finished Jul 11 06:24:27 PM PDT 24
Peak memory 214836 kb
Host smart-f8f26771-3836-4044-a44e-3da760e0a0c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421028080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.3421028080
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.386706183
Short name T246
Test name
Test status
Simulation time 42970499 ps
CPU time 0.71 seconds
Started Jul 11 06:24:07 PM PDT 24
Finished Jul 11 06:24:16 PM PDT 24
Peak memory 205368 kb
Host smart-d9bc7bc1-4a64-41bb-a2a0-a76c8cacbd4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386706183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.386706183
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.319865934
Short name T262
Test name
Test status
Simulation time 2852336387 ps
CPU time 8.76 seconds
Started Jul 11 06:24:08 PM PDT 24
Finished Jul 11 06:24:25 PM PDT 24
Peak memory 205680 kb
Host smart-3ee7fdf7-b3d2-4f53-bc46-3baec1c38b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319865934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.319865934
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.613550996
Short name T147
Test name
Test status
Simulation time 13693071322 ps
CPU time 18.98 seconds
Started Jul 11 06:24:09 PM PDT 24
Finished Jul 11 06:24:36 PM PDT 24
Peak memory 213828 kb
Host smart-f21e0d71-1b2d-4ca3-99f5-c4abd7daad9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613550996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.613550996
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1152355368
Short name T213
Test name
Test status
Simulation time 126369013 ps
CPU time 0.97 seconds
Started Jul 11 06:24:08 PM PDT 24
Finished Jul 11 06:24:17 PM PDT 24
Peak memory 205224 kb
Host smart-66fddd1b-3a54-43b8-a06e-f24aec172e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152355368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1152355368
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2290879687
Short name T70
Test name
Test status
Simulation time 8456887884 ps
CPU time 4.34 seconds
Started Jul 11 06:24:08 PM PDT 24
Finished Jul 11 06:24:21 PM PDT 24
Peak memory 213672 kb
Host smart-d7f28156-8d6e-4f2b-b2b6-f1b7917f9803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290879687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2290879687
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.12614944
Short name T156
Test name
Test status
Simulation time 3559519999 ps
CPU time 4.12 seconds
Started Jul 11 06:24:05 PM PDT 24
Finished Jul 11 06:24:17 PM PDT 24
Peak memory 213904 kb
Host smart-975834b4-79d3-4dae-904d-bdfb79d5b57d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=12614944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_tl
_access.12614944
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2861545719
Short name T144
Test name
Test status
Simulation time 8277279670 ps
CPU time 7.87 seconds
Started Jul 11 06:24:08 PM PDT 24
Finished Jul 11 06:24:24 PM PDT 24
Peak memory 205480 kb
Host smart-8beb4a9b-0283-471a-ba90-36ff33ac788d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861545719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2861545719
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1272493357
Short name T249
Test name
Test status
Simulation time 35114368 ps
CPU time 0.75 seconds
Started Jul 11 06:24:05 PM PDT 24
Finished Jul 11 06:24:14 PM PDT 24
Peak memory 205304 kb
Host smart-eb2af7cd-1469-4cf6-8850-067ac513881a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272493357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1272493357
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.909893595
Short name T229
Test name
Test status
Simulation time 8660434754 ps
CPU time 12.55 seconds
Started Jul 11 06:24:19 PM PDT 24
Finished Jul 11 06:24:38 PM PDT 24
Peak memory 216020 kb
Host smart-a8f1fcf0-ee57-4b61-be1e-5fe4378424b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909893595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.909893595
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1263334593
Short name T243
Test name
Test status
Simulation time 1747694912 ps
CPU time 5.09 seconds
Started Jul 11 06:24:09 PM PDT 24
Finished Jul 11 06:24:22 PM PDT 24
Peak memory 213804 kb
Host smart-af80b53d-7181-48d5-bab6-85d13c282499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263334593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1263334593
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1870306227
Short name T12
Test name
Test status
Simulation time 3005219485 ps
CPU time 5 seconds
Started Jul 11 06:24:08 PM PDT 24
Finished Jul 11 06:24:21 PM PDT 24
Peak memory 205692 kb
Host smart-8fb99633-68c3-4c7a-9b6b-96f94be30172
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1870306227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1870306227
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3427924897
Short name T238
Test name
Test status
Simulation time 2265471741 ps
CPU time 4.84 seconds
Started Jul 11 06:24:06 PM PDT 24
Finished Jul 11 06:24:18 PM PDT 24
Peak memory 213884 kb
Host smart-7a818f0e-101b-4480-abf0-ceecaf586a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427924897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3427924897
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.2003389437
Short name T37
Test name
Test status
Simulation time 7380230634 ps
CPU time 4.81 seconds
Started Jul 11 06:24:20 PM PDT 24
Finished Jul 11 06:24:31 PM PDT 24
Peak memory 214700 kb
Host smart-0f70fb00-e0ea-4115-accb-0417c64c0266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003389437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2003389437
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2978563146
Short name T53
Test name
Test status
Simulation time 67445907 ps
CPU time 0.72 seconds
Started Jul 11 06:24:20 PM PDT 24
Finished Jul 11 06:24:28 PM PDT 24
Peak memory 205344 kb
Host smart-ddced75c-06f1-4ff1-a9f5-aec84a02226d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978563146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2978563146
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.1825288570
Short name T228
Test name
Test status
Simulation time 4253226433 ps
CPU time 10.07 seconds
Started Jul 11 06:24:34 PM PDT 24
Finished Jul 11 06:24:52 PM PDT 24
Peak memory 222016 kb
Host smart-e34ee1bc-892d-4b71-b564-e8b936df63d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825288570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.1825288570
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.825996595
Short name T226
Test name
Test status
Simulation time 2793596661 ps
CPU time 3.23 seconds
Started Jul 11 06:24:20 PM PDT 24
Finished Jul 11 06:24:31 PM PDT 24
Peak memory 213908 kb
Host smart-b06d3992-fe3d-4f9e-828a-264c466aaacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825996595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.825996595
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.788358909
Short name T250
Test name
Test status
Simulation time 847075165 ps
CPU time 3.38 seconds
Started Jul 11 06:24:13 PM PDT 24
Finished Jul 11 06:24:23 PM PDT 24
Peak memory 213860 kb
Host smart-2c7f75cf-5bc9-4941-9257-c8e8f4ccf35c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=788358909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.788358909
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2977230038
Short name T242
Test name
Test status
Simulation time 137122889 ps
CPU time 0.85 seconds
Started Jul 11 06:24:36 PM PDT 24
Finished Jul 11 06:24:46 PM PDT 24
Peak memory 205344 kb
Host smart-20bdb146-cf77-42cb-b351-16addadfa288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977230038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2977230038
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.4252487626
Short name T73
Test name
Test status
Simulation time 16865820447 ps
CPU time 37.14 seconds
Started Jul 11 06:24:18 PM PDT 24
Finished Jul 11 06:25:02 PM PDT 24
Peak memory 213876 kb
Host smart-30a1d381-5a16-4c99-a0d7-4903ab946460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252487626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.4252487626
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2016001542
Short name T271
Test name
Test status
Simulation time 831754712 ps
CPU time 2.88 seconds
Started Jul 11 06:24:17 PM PDT 24
Finished Jul 11 06:24:27 PM PDT 24
Peak memory 213880 kb
Host smart-629784f1-1430-4f45-8037-4db9f32860c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016001542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2016001542
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.4251617063
Short name T14
Test name
Test status
Simulation time 10298319786 ps
CPU time 25.44 seconds
Started Jul 11 06:24:10 PM PDT 24
Finished Jul 11 06:24:43 PM PDT 24
Peak memory 213828 kb
Host smart-345cb1de-6fb7-4653-806c-f460f30e2c1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251617063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.4251617063
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.1603479583
Short name T123
Test name
Test status
Simulation time 139983254 ps
CPU time 0.85 seconds
Started Jul 11 06:23:56 PM PDT 24
Finished Jul 11 06:24:06 PM PDT 24
Peak memory 205380 kb
Host smart-7c143341-1037-4254-a14a-3f1ac62fd8e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603479583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.1603479583
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1304621701
Short name T287
Test name
Test status
Simulation time 39143173728 ps
CPU time 8.96 seconds
Started Jul 11 06:23:59 PM PDT 24
Finished Jul 11 06:24:17 PM PDT 24
Peak memory 213884 kb
Host smart-01e5d97e-4bc2-45be-84e7-0a49a939f453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304621701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1304621701
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1982717374
Short name T10
Test name
Test status
Simulation time 222124122 ps
CPU time 0.87 seconds
Started Jul 11 06:23:55 PM PDT 24
Finished Jul 11 06:24:04 PM PDT 24
Peak memory 205376 kb
Host smart-03d465ae-23ab-4c7f-81fc-1cf3599b6ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982717374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1982717374
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.4140725007
Short name T214
Test name
Test status
Simulation time 774053810 ps
CPU time 1.65 seconds
Started Jul 11 06:23:51 PM PDT 24
Finished Jul 11 06:24:00 PM PDT 24
Peak memory 213832 kb
Host smart-25c1ccf6-fd7f-4295-873c-51c2f06fae4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140725007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.4140725007
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2677969352
Short name T65
Test name
Test status
Simulation time 350732067 ps
CPU time 1.73 seconds
Started Jul 11 06:23:56 PM PDT 24
Finished Jul 11 06:24:07 PM PDT 24
Peak memory 229488 kb
Host smart-a52803ef-bcfb-4ae0-b3af-ec1c97687b47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677969352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2677969352
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.2142168616
Short name T140
Test name
Test status
Simulation time 2331052817 ps
CPU time 6.63 seconds
Started Jul 11 06:23:57 PM PDT 24
Finished Jul 11 06:24:13 PM PDT 24
Peak memory 213840 kb
Host smart-e6d750fd-51e5-4a46-9291-e15f0d521fb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142168616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2142168616
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1622326756
Short name T212
Test name
Test status
Simulation time 76787490 ps
CPU time 0.87 seconds
Started Jul 11 06:24:23 PM PDT 24
Finished Jul 11 06:24:30 PM PDT 24
Peak memory 205304 kb
Host smart-159aec28-dfc0-47bb-82ab-26ee1f5e45c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622326756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1622326756
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2578817293
Short name T290
Test name
Test status
Simulation time 67418872 ps
CPU time 0.82 seconds
Started Jul 11 06:24:17 PM PDT 24
Finished Jul 11 06:24:25 PM PDT 24
Peak memory 205364 kb
Host smart-7ec3adfe-814b-4ca4-99d7-dcf7e46d4157
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578817293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2578817293
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2291115795
Short name T204
Test name
Test status
Simulation time 68846381 ps
CPU time 0.73 seconds
Started Jul 11 06:24:33 PM PDT 24
Finished Jul 11 06:24:43 PM PDT 24
Peak memory 205296 kb
Host smart-e584d361-b844-4920-a32d-b4693c5d3a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291115795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2291115795
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2666547140
Short name T202
Test name
Test status
Simulation time 50541646 ps
CPU time 0.8 seconds
Started Jul 11 06:24:13 PM PDT 24
Finished Jul 11 06:24:21 PM PDT 24
Peak memory 205144 kb
Host smart-8030e7bf-cfed-4866-88c1-1947c6388f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666547140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2666547140
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3522932266
Short name T227
Test name
Test status
Simulation time 87943959 ps
CPU time 0.72 seconds
Started Jul 11 06:24:11 PM PDT 24
Finished Jul 11 06:24:19 PM PDT 24
Peak memory 205368 kb
Host smart-87c07fb5-c6c7-4c7d-aa81-98ca11fffa4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522932266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3522932266
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.2719675954
Short name T18
Test name
Test status
Simulation time 9111771657 ps
CPU time 5.05 seconds
Started Jul 11 06:24:10 PM PDT 24
Finished Jul 11 06:24:23 PM PDT 24
Peak memory 213784 kb
Host smart-d6c57d19-ffab-4c34-b128-8a4a26ca70bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719675954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2719675954
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2701716216
Short name T241
Test name
Test status
Simulation time 80720645 ps
CPU time 0.72 seconds
Started Jul 11 06:24:15 PM PDT 24
Finished Jul 11 06:24:22 PM PDT 24
Peak memory 205368 kb
Host smart-c086727b-f94a-4c44-913e-22db1b885ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701716216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2701716216
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2769159413
Short name T146
Test name
Test status
Simulation time 5067394565 ps
CPU time 8.47 seconds
Started Jul 11 06:24:21 PM PDT 24
Finished Jul 11 06:24:36 PM PDT 24
Peak memory 205608 kb
Host smart-0a88b2f6-6420-4997-9f03-b2095ebdaec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769159413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2769159413
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.282252617
Short name T210
Test name
Test status
Simulation time 189099514 ps
CPU time 0.8 seconds
Started Jul 11 06:24:13 PM PDT 24
Finished Jul 11 06:24:21 PM PDT 24
Peak memory 205292 kb
Host smart-51cb704c-967a-4760-bf14-111c0ccf9fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282252617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.282252617
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.4020511278
Short name T218
Test name
Test status
Simulation time 119230338 ps
CPU time 0.95 seconds
Started Jul 11 06:24:30 PM PDT 24
Finished Jul 11 06:24:38 PM PDT 24
Peak memory 205348 kb
Host smart-3ae9ceb1-401a-45cc-8d7f-e2f434c2ccb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020511278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.4020511278
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.2121956142
Short name T130
Test name
Test status
Simulation time 5396661795 ps
CPU time 17.27 seconds
Started Jul 11 06:24:16 PM PDT 24
Finished Jul 11 06:24:39 PM PDT 24
Peak memory 213808 kb
Host smart-82d64ad6-61b7-451d-b7ab-e34a529fe461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121956142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.2121956142
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.4092527039
Short name T129
Test name
Test status
Simulation time 39857440 ps
CPU time 0.69 seconds
Started Jul 11 06:24:19 PM PDT 24
Finished Jul 11 06:24:26 PM PDT 24
Peak memory 205364 kb
Host smart-f4437546-897e-419d-abcb-d169e260c985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092527039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4092527039
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1614604107
Short name T189
Test name
Test status
Simulation time 8751397869 ps
CPU time 16.41 seconds
Started Jul 11 06:24:15 PM PDT 24
Finished Jul 11 06:24:38 PM PDT 24
Peak memory 213756 kb
Host smart-80b3cccc-de83-4941-bb56-d8e4c434d7c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614604107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1614604107
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.374021302
Short name T252
Test name
Test status
Simulation time 34486018 ps
CPU time 0.8 seconds
Started Jul 11 06:24:09 PM PDT 24
Finished Jul 11 06:24:18 PM PDT 24
Peak memory 205368 kb
Host smart-7337b7a5-d324-4aa9-9e37-d78100e6e439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374021302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.374021302
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.570120750
Short name T58
Test name
Test status
Simulation time 91606169 ps
CPU time 0.92 seconds
Started Jul 11 06:24:01 PM PDT 24
Finished Jul 11 06:24:11 PM PDT 24
Peak memory 205376 kb
Host smart-62163133-d96c-4ea2-ba80-955e3dfb765d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570120750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.570120750
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2953705337
Short name T32
Test name
Test status
Simulation time 75380812733 ps
CPU time 77.88 seconds
Started Jul 11 06:23:56 PM PDT 24
Finished Jul 11 06:25:23 PM PDT 24
Peak memory 221396 kb
Host smart-38dcee31-7679-4b3e-a18b-26c42a5112a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953705337 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2953705337
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2279110648
Short name T269
Test name
Test status
Simulation time 13570141576 ps
CPU time 38.25 seconds
Started Jul 11 06:23:55 PM PDT 24
Finished Jul 11 06:24:42 PM PDT 24
Peak memory 221972 kb
Host smart-d5e7f0e2-f2d6-4ef0-b159-9f07587b3c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279110648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2279110648
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1806192131
Short name T67
Test name
Test status
Simulation time 6092145747 ps
CPU time 17.5 seconds
Started Jul 11 06:23:56 PM PDT 24
Finished Jul 11 06:24:23 PM PDT 24
Peak memory 213900 kb
Host smart-9a9a7abd-d7c5-4165-828c-bc1ced1dbe8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806192131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1806192131
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3376764024
Short name T55
Test name
Test status
Simulation time 709797445 ps
CPU time 1.92 seconds
Started Jul 11 06:23:58 PM PDT 24
Finished Jul 11 06:24:10 PM PDT 24
Peak memory 237760 kb
Host smart-abdac438-73b3-447f-a515-eb3b044eb59c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376764024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3376764024
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2094005940
Short name T230
Test name
Test status
Simulation time 71470739 ps
CPU time 0.76 seconds
Started Jul 11 06:24:33 PM PDT 24
Finished Jul 11 06:24:43 PM PDT 24
Peak memory 205292 kb
Host smart-3d30c700-f31d-478b-beba-24934bef50da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094005940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2094005940
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.2320313138
Short name T236
Test name
Test status
Simulation time 8690588984 ps
CPU time 5.29 seconds
Started Jul 11 06:24:18 PM PDT 24
Finished Jul 11 06:24:30 PM PDT 24
Peak memory 213960 kb
Host smart-42e16506-e4bd-430e-be10-de1d1f16cf60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320313138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.2320313138
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2148143631
Short name T264
Test name
Test status
Simulation time 82526875 ps
CPU time 0.71 seconds
Started Jul 11 06:24:20 PM PDT 24
Finished Jul 11 06:24:28 PM PDT 24
Peak memory 205368 kb
Host smart-f6bab252-0470-4258-a252-85bf8275cbf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148143631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2148143631
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.950206196
Short name T15
Test name
Test status
Simulation time 5747296900 ps
CPU time 5.23 seconds
Started Jul 11 06:24:22 PM PDT 24
Finished Jul 11 06:24:34 PM PDT 24
Peak memory 205580 kb
Host smart-a68f9b9c-329b-4e26-b2b0-e93f727f2ed1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950206196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.950206196
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.4124464641
Short name T220
Test name
Test status
Simulation time 124265081 ps
CPU time 0.74 seconds
Started Jul 11 06:24:17 PM PDT 24
Finished Jul 11 06:24:24 PM PDT 24
Peak memory 205344 kb
Host smart-88b61194-6ef1-461b-8800-1f4be47a9567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124464641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.4124464641
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.1121065780
Short name T190
Test name
Test status
Simulation time 5867761837 ps
CPU time 15.24 seconds
Started Jul 11 06:24:46 PM PDT 24
Finished Jul 11 06:25:17 PM PDT 24
Peak memory 205608 kb
Host smart-1bb3243d-3c55-4775-8c82-936afadcd15f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121065780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1121065780
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.93113754
Short name T221
Test name
Test status
Simulation time 102126671 ps
CPU time 0.76 seconds
Started Jul 11 06:24:21 PM PDT 24
Finished Jul 11 06:24:28 PM PDT 24
Peak memory 205364 kb
Host smart-41ff75db-87a9-46be-a3ff-fd09ad9adaf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93113754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.93113754
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.4226207769
Short name T209
Test name
Test status
Simulation time 76497552 ps
CPU time 0.79 seconds
Started Jul 11 06:24:29 PM PDT 24
Finished Jul 11 06:24:37 PM PDT 24
Peak memory 205356 kb
Host smart-d7258a52-cf85-491e-af2e-f9b8080ebb6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226207769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.4226207769
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.3343206778
Short name T150
Test name
Test status
Simulation time 9731062318 ps
CPU time 12.35 seconds
Started Jul 11 06:24:14 PM PDT 24
Finished Jul 11 06:24:33 PM PDT 24
Peak memory 213780 kb
Host smart-45a4f82f-a116-4f8a-9b5d-60078391fd08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343206778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3343206778
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3820875396
Short name T77
Test name
Test status
Simulation time 172751326 ps
CPU time 0.81 seconds
Started Jul 11 06:24:24 PM PDT 24
Finished Jul 11 06:24:31 PM PDT 24
Peak memory 205356 kb
Host smart-46eeef19-772e-4b95-a21c-0d9013bbb6db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820875396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3820875396
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.1993659147
Short name T195
Test name
Test status
Simulation time 8169678296 ps
CPU time 4.64 seconds
Started Jul 11 06:24:19 PM PDT 24
Finished Jul 11 06:24:30 PM PDT 24
Peak memory 215164 kb
Host smart-560da726-c94c-43a3-bbac-224c8eec0ecf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993659147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1993659147
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1642229141
Short name T245
Test name
Test status
Simulation time 35800134 ps
CPU time 0.72 seconds
Started Jul 11 06:24:20 PM PDT 24
Finished Jul 11 06:24:28 PM PDT 24
Peak memory 205368 kb
Host smart-c837cc88-f52e-417d-a343-940e308eca08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642229141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1642229141
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.1189521646
Short name T142
Test name
Test status
Simulation time 4008378444 ps
CPU time 6.66 seconds
Started Jul 11 06:24:14 PM PDT 24
Finished Jul 11 06:24:27 PM PDT 24
Peak memory 205584 kb
Host smart-ec6939b3-007b-4cac-8552-68b1efb19087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189521646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1189521646
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3896245562
Short name T225
Test name
Test status
Simulation time 130905868 ps
CPU time 0.97 seconds
Started Jul 11 06:24:17 PM PDT 24
Finished Jul 11 06:24:25 PM PDT 24
Peak memory 205344 kb
Host smart-b2f213da-4128-4398-a3ba-608e7f972883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896245562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3896245562
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.2462993244
Short name T20
Test name
Test status
Simulation time 11028314295 ps
CPU time 18.41 seconds
Started Jul 11 06:24:17 PM PDT 24
Finished Jul 11 06:24:42 PM PDT 24
Peak memory 213816 kb
Host smart-81fbc4b6-325e-4263-8c5f-95668645bc23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462993244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.2462993244
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2514721307
Short name T208
Test name
Test status
Simulation time 53820964 ps
CPU time 0.79 seconds
Started Jul 11 06:24:19 PM PDT 24
Finished Jul 11 06:24:26 PM PDT 24
Peak memory 205368 kb
Host smart-73bacdc2-f6de-4ec4-b52b-57a3e29d6c28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514721307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2514721307
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.2293839029
Short name T188
Test name
Test status
Simulation time 6470042976 ps
CPU time 9.18 seconds
Started Jul 11 06:24:31 PM PDT 24
Finished Jul 11 06:24:47 PM PDT 24
Peak memory 205628 kb
Host smart-a4b43577-6257-4b30-bd75-0231e18bc5cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293839029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.2293839029
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.4138904567
Short name T235
Test name
Test status
Simulation time 74564945 ps
CPU time 0.71 seconds
Started Jul 11 06:24:14 PM PDT 24
Finished Jul 11 06:24:22 PM PDT 24
Peak memory 205380 kb
Host smart-869ff4e5-4922-4ac4-868c-4e41b6ff4a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138904567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.4138904567
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.1501215024
Short name T151
Test name
Test status
Simulation time 1591188690 ps
CPU time 5.03 seconds
Started Jul 11 06:24:18 PM PDT 24
Finished Jul 11 06:24:29 PM PDT 24
Peak memory 205560 kb
Host smart-afb22697-ec01-40c6-9d28-b4d6bb4bf55f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501215024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.1501215024
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.810496552
Short name T244
Test name
Test status
Simulation time 56452535 ps
CPU time 0.7 seconds
Started Jul 11 06:23:58 PM PDT 24
Finished Jul 11 06:24:08 PM PDT 24
Peak memory 205292 kb
Host smart-43f9dd8a-487a-4811-96c0-8aa867d82642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810496552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.810496552
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3805694012
Short name T224
Test name
Test status
Simulation time 3071083294 ps
CPU time 3.9 seconds
Started Jul 11 06:23:59 PM PDT 24
Finished Jul 11 06:24:12 PM PDT 24
Peak memory 213744 kb
Host smart-04b91f6e-5952-4f7e-86c5-fb81b0a6771d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805694012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3805694012
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.314430816
Short name T233
Test name
Test status
Simulation time 1542788800 ps
CPU time 1.75 seconds
Started Jul 11 06:24:00 PM PDT 24
Finished Jul 11 06:24:11 PM PDT 24
Peak memory 205596 kb
Host smart-d729c2db-d5e7-4e59-98bb-cc8d8b80682c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314430816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.314430816
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.217199962
Short name T78
Test name
Test status
Simulation time 318988842 ps
CPU time 1.66 seconds
Started Jul 11 06:24:02 PM PDT 24
Finished Jul 11 06:24:13 PM PDT 24
Peak memory 205356 kb
Host smart-7164243b-4e1d-4315-89a6-00b97e4b88f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217199962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.217199962
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1159842945
Short name T171
Test name
Test status
Simulation time 3881129133 ps
CPU time 10.85 seconds
Started Jul 11 06:23:57 PM PDT 24
Finished Jul 11 06:24:17 PM PDT 24
Peak memory 213860 kb
Host smart-9b90293d-652a-4510-9251-ede29d039baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159842945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1159842945
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.997646605
Short name T25
Test name
Test status
Simulation time 11443812714 ps
CPU time 14.14 seconds
Started Jul 11 06:23:56 PM PDT 24
Finished Jul 11 06:24:19 PM PDT 24
Peak memory 205628 kb
Host smart-21a15cd6-a11a-4072-8067-50b6e80e86c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997646605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.997646605
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.4003679501
Short name T72
Test name
Test status
Simulation time 51098619 ps
CPU time 0.81 seconds
Started Jul 11 06:24:24 PM PDT 24
Finished Jul 11 06:24:30 PM PDT 24
Peak memory 205368 kb
Host smart-82cec80a-26a8-4bf9-907b-1bbdcc6b90af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003679501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.4003679501
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.1930573755
Short name T153
Test name
Test status
Simulation time 2441567727 ps
CPU time 6.35 seconds
Started Jul 11 06:24:17 PM PDT 24
Finished Jul 11 06:24:30 PM PDT 24
Peak memory 205572 kb
Host smart-a186198b-f774-4ae3-b00b-99a2a885bf13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930573755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1930573755
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3441203635
Short name T273
Test name
Test status
Simulation time 64475379 ps
CPU time 0.72 seconds
Started Jul 11 06:24:29 PM PDT 24
Finished Jul 11 06:24:37 PM PDT 24
Peak memory 205348 kb
Host smart-f8940531-475f-419e-b782-9b9cb475811f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441203635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3441203635
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.953576790
Short name T138
Test name
Test status
Simulation time 13673269360 ps
CPU time 7.29 seconds
Started Jul 11 06:24:21 PM PDT 24
Finished Jul 11 06:24:34 PM PDT 24
Peak memory 213748 kb
Host smart-d1b3647a-8860-41df-9129-afdb80f88275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953576790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.953576790
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.2700158314
Short name T268
Test name
Test status
Simulation time 88398438 ps
CPU time 0.74 seconds
Started Jul 11 06:24:23 PM PDT 24
Finished Jul 11 06:24:29 PM PDT 24
Peak memory 205336 kb
Host smart-50c385fc-f561-4b74-8609-4e537ac0ab4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700158314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2700158314
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1514420313
Short name T79
Test name
Test status
Simulation time 39740568 ps
CPU time 0.78 seconds
Started Jul 11 06:24:18 PM PDT 24
Finished Jul 11 06:24:25 PM PDT 24
Peak memory 205384 kb
Host smart-2d55a9aa-e7e9-4b78-b3b4-b6ef3002fc22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514420313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1514420313
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3065618357
Short name T279
Test name
Test status
Simulation time 93419516 ps
CPU time 0.8 seconds
Started Jul 11 06:24:23 PM PDT 24
Finished Jul 11 06:24:29 PM PDT 24
Peak memory 205368 kb
Host smart-95efb84c-0b83-41a5-9685-9a61a7e10989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065618357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3065618357
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.2589730126
Short name T13
Test name
Test status
Simulation time 5699085291 ps
CPU time 16.27 seconds
Started Jul 11 06:24:13 PM PDT 24
Finished Jul 11 06:24:36 PM PDT 24
Peak memory 213784 kb
Host smart-e05fd6a8-4991-4d41-9c63-7fa62bde79dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589730126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2589730126
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3961301429
Short name T222
Test name
Test status
Simulation time 81846629 ps
CPU time 0.8 seconds
Started Jul 11 06:24:16 PM PDT 24
Finished Jul 11 06:24:23 PM PDT 24
Peak memory 205564 kb
Host smart-2555b9e4-ae28-4da5-a05a-0c734a497b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961301429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3961301429
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.4204809073
Short name T278
Test name
Test status
Simulation time 150774219 ps
CPU time 1.07 seconds
Started Jul 11 06:24:36 PM PDT 24
Finished Jul 11 06:24:45 PM PDT 24
Peak memory 205368 kb
Host smart-d864bde6-2c4c-482f-a413-b465fc56c367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204809073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.4204809073
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.3543483422
Short name T137
Test name
Test status
Simulation time 4479348418 ps
CPU time 1.93 seconds
Started Jul 11 06:24:22 PM PDT 24
Finished Jul 11 06:24:30 PM PDT 24
Peak memory 205632 kb
Host smart-2991a6c8-aa21-4066-a8cc-267a55c8d935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543483422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.3543483422
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.200868722
Short name T75
Test name
Test status
Simulation time 142078499 ps
CPU time 0.83 seconds
Started Jul 11 06:24:32 PM PDT 24
Finished Jul 11 06:24:40 PM PDT 24
Peak memory 205344 kb
Host smart-2ed9ae7a-e5d2-4e61-a02c-7e8dfa6b69b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200868722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.200868722
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.591470909
Short name T27
Test name
Test status
Simulation time 8774118829 ps
CPU time 7.55 seconds
Started Jul 11 06:24:24 PM PDT 24
Finished Jul 11 06:24:37 PM PDT 24
Peak memory 205660 kb
Host smart-5f38657a-248b-4c8c-8569-a7200aa94190
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591470909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.591470909
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3052011727
Short name T2
Test name
Test status
Simulation time 46069646 ps
CPU time 0.81 seconds
Started Jul 11 06:24:20 PM PDT 24
Finished Jul 11 06:24:27 PM PDT 24
Peak memory 205348 kb
Host smart-64e5d183-0e98-4ede-b647-91e9c3a95edc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052011727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3052011727
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.3118454567
Short name T194
Test name
Test status
Simulation time 11183260686 ps
CPU time 14.16 seconds
Started Jul 11 06:24:25 PM PDT 24
Finished Jul 11 06:24:44 PM PDT 24
Peak memory 213780 kb
Host smart-02057b86-bfc9-437f-9c3e-98df6c486c6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118454567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3118454567
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.288342536
Short name T240
Test name
Test status
Simulation time 60897045 ps
CPU time 0.78 seconds
Started Jul 11 06:24:22 PM PDT 24
Finished Jul 11 06:24:29 PM PDT 24
Peak memory 205368 kb
Host smart-e39f5d67-6128-47c5-8050-4cc16460e376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288342536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.288342536
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1106713453
Short name T231
Test name
Test status
Simulation time 35659649 ps
CPU time 0.77 seconds
Started Jul 11 06:23:58 PM PDT 24
Finished Jul 11 06:24:09 PM PDT 24
Peak memory 205364 kb
Host smart-edefa0c7-d107-4aa9-801c-9cfbddcbd354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106713453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1106713453
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.531289128
Short name T248
Test name
Test status
Simulation time 18047379827 ps
CPU time 55.33 seconds
Started Jul 11 06:24:01 PM PDT 24
Finished Jul 11 06:25:06 PM PDT 24
Peak memory 213964 kb
Host smart-0ed67bd2-f3f9-4b6f-894a-4c413f0f2aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531289128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.531289128
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2009681231
Short name T258
Test name
Test status
Simulation time 1191933947 ps
CPU time 1.88 seconds
Started Jul 11 06:23:57 PM PDT 24
Finished Jul 11 06:24:08 PM PDT 24
Peak memory 213776 kb
Host smart-f1ca839f-f857-4c19-8172-ad1a59a86c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009681231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2009681231
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1234301854
Short name T163
Test name
Test status
Simulation time 1646107534 ps
CPU time 3.67 seconds
Started Jul 11 06:24:00 PM PDT 24
Finished Jul 11 06:24:13 PM PDT 24
Peak memory 213800 kb
Host smart-32d7f0e1-0984-43b9-a619-6414208f014e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1234301854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1234301854
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3940662363
Short name T168
Test name
Test status
Simulation time 3201098448 ps
CPU time 5.78 seconds
Started Jul 11 06:23:57 PM PDT 24
Finished Jul 11 06:24:12 PM PDT 24
Peak memory 213708 kb
Host smart-b5832d3b-a305-4ed6-9bf4-70c4aff6b9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940662363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3940662363
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2859104826
Short name T124
Test name
Test status
Simulation time 95282603 ps
CPU time 0.93 seconds
Started Jul 11 06:24:02 PM PDT 24
Finished Jul 11 06:24:12 PM PDT 24
Peak memory 205368 kb
Host smart-2485064d-e001-4ed3-bd27-3c4d50be598d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859104826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2859104826
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.153397176
Short name T239
Test name
Test status
Simulation time 6870886735 ps
CPU time 5.69 seconds
Started Jul 11 06:24:03 PM PDT 24
Finished Jul 11 06:24:18 PM PDT 24
Peak memory 205828 kb
Host smart-df8115ec-9173-4666-985c-eb8535bd5278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153397176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.153397176
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.4113059560
Short name T267
Test name
Test status
Simulation time 1141183186 ps
CPU time 1.93 seconds
Started Jul 11 06:23:58 PM PDT 24
Finished Jul 11 06:24:10 PM PDT 24
Peak memory 205556 kb
Host smart-5e252749-5660-43ec-ac5e-b42cb7238f95
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4113059560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.4113059560
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2647106589
Short name T289
Test name
Test status
Simulation time 4097633457 ps
CPU time 10.27 seconds
Started Jul 11 06:23:56 PM PDT 24
Finished Jul 11 06:24:20 PM PDT 24
Peak memory 205600 kb
Host smart-bb03731a-ea82-4840-b366-3f62270f5749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647106589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2647106589
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.1372016260
Short name T148
Test name
Test status
Simulation time 11897908360 ps
CPU time 25 seconds
Started Jul 11 06:24:05 PM PDT 24
Finished Jul 11 06:24:39 PM PDT 24
Peak memory 213768 kb
Host smart-3e144d64-2906-4a17-a85e-3472e6ba6726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372016260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1372016260
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2592638344
Short name T206
Test name
Test status
Simulation time 168125190 ps
CPU time 0.9 seconds
Started Jul 11 06:24:04 PM PDT 24
Finished Jul 11 06:24:14 PM PDT 24
Peak memory 205532 kb
Host smart-5fbcb29f-e7fd-4af4-9be9-8c19a60c5072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592638344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2592638344
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3024832997
Short name T223
Test name
Test status
Simulation time 29421916026 ps
CPU time 38.31 seconds
Started Jul 11 06:24:03 PM PDT 24
Finished Jul 11 06:24:51 PM PDT 24
Peak memory 222040 kb
Host smart-cb42eb65-fec2-4c1e-89b9-f305fe84e371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024832997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3024832997
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3826873280
Short name T66
Test name
Test status
Simulation time 10252160403 ps
CPU time 27.43 seconds
Started Jul 11 06:24:02 PM PDT 24
Finished Jul 11 06:24:38 PM PDT 24
Peak memory 216128 kb
Host smart-c0351136-5870-43c8-84ed-9ebcd4ade0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826873280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3826873280
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1611983072
Short name T216
Test name
Test status
Simulation time 3084905740 ps
CPU time 6.22 seconds
Started Jul 11 06:24:00 PM PDT 24
Finished Jul 11 06:24:15 PM PDT 24
Peak memory 213928 kb
Host smart-07730254-dd00-46d7-b681-042dfbb66405
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611983072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1611983072
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2454781045
Short name T288
Test name
Test status
Simulation time 1648631684 ps
CPU time 2.85 seconds
Started Jul 11 06:24:03 PM PDT 24
Finished Jul 11 06:24:15 PM PDT 24
Peak memory 205664 kb
Host smart-00ee2805-2859-4c71-91de-097535a5b732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454781045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2454781045
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1478771132
Short name T247
Test name
Test status
Simulation time 82955226 ps
CPU time 0.74 seconds
Started Jul 11 06:24:06 PM PDT 24
Finished Jul 11 06:24:15 PM PDT 24
Peak memory 205336 kb
Host smart-61b5a38d-3abd-455e-b75d-5b9c39f24136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478771132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1478771132
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1092712210
Short name T277
Test name
Test status
Simulation time 46748272239 ps
CPU time 118.6 seconds
Started Jul 11 06:24:06 PM PDT 24
Finished Jul 11 06:26:14 PM PDT 24
Peak memory 213836 kb
Host smart-4b240f48-3791-4b48-819c-15d91d685921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092712210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1092712210
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3521357858
Short name T282
Test name
Test status
Simulation time 1032785268 ps
CPU time 1.83 seconds
Started Jul 11 06:24:03 PM PDT 24
Finished Jul 11 06:24:14 PM PDT 24
Peak memory 213792 kb
Host smart-d73f764e-9a72-45f2-b05f-e1b4ecc93fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521357858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3521357858
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.854840716
Short name T237
Test name
Test status
Simulation time 5701155413 ps
CPU time 13.72 seconds
Started Jul 11 06:24:02 PM PDT 24
Finished Jul 11 06:24:25 PM PDT 24
Peak memory 213844 kb
Host smart-d7875454-d948-456a-980e-ac60fd6a8d01
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854840716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.854840716
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3675973221
Short name T69
Test name
Test status
Simulation time 2028934531 ps
CPU time 1.25 seconds
Started Jul 11 06:24:02 PM PDT 24
Finished Jul 11 06:24:12 PM PDT 24
Peak memory 205592 kb
Host smart-1d1e740f-dccd-42c5-b5a7-db1be7ee7a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675973221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3675973221
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.3923190181
Short name T26
Test name
Test status
Simulation time 3219557768 ps
CPU time 3.85 seconds
Started Jul 11 06:24:12 PM PDT 24
Finished Jul 11 06:24:23 PM PDT 24
Peak memory 205596 kb
Host smart-c0ef0609-dc8e-4dc3-88c8-12457a6ee80b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923190181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3923190181
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3838148738
Short name T217
Test name
Test status
Simulation time 49318137 ps
CPU time 0.77 seconds
Started Jul 11 06:24:03 PM PDT 24
Finished Jul 11 06:24:13 PM PDT 24
Peak memory 205560 kb
Host smart-6c7c1c25-1442-47ad-9fc0-5fef673200ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838148738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3838148738
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.277004082
Short name T199
Test name
Test status
Simulation time 6045072967 ps
CPU time 8.96 seconds
Started Jul 11 06:24:03 PM PDT 24
Finished Jul 11 06:24:21 PM PDT 24
Peak memory 212620 kb
Host smart-f8770065-359b-4ef7-a5e6-c0486b5f9761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277004082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.277004082
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1035742687
Short name T200
Test name
Test status
Simulation time 3256460523 ps
CPU time 10.86 seconds
Started Jul 11 06:24:02 PM PDT 24
Finished Jul 11 06:24:22 PM PDT 24
Peak memory 215080 kb
Host smart-82792d35-3d0c-4753-b170-49871927ffe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035742687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1035742687
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2346316388
Short name T259
Test name
Test status
Simulation time 1735821070 ps
CPU time 3.27 seconds
Started Jul 11 06:24:03 PM PDT 24
Finished Jul 11 06:24:15 PM PDT 24
Peak memory 213852 kb
Host smart-d5e24346-c340-4b88-8d2b-6fa74a1abfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346316388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2346316388
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.1676593531
Short name T4
Test name
Test status
Simulation time 3465085664 ps
CPU time 3.69 seconds
Started Jul 11 06:24:07 PM PDT 24
Finished Jul 11 06:24:19 PM PDT 24
Peak memory 205568 kb
Host smart-9d4e8908-d9fa-4efd-a4b3-b735b3b0f302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676593531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.1676593531
Directory /workspace/9.rv_dm_stress_all/latest
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