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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.43 95.67 80.41 89.75 73.08 86.17 98.42 53.52


Total test records in report: 446
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html
T302 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4215131928 Jul 13 05:55:37 PM PDT 24 Jul 13 05:55:39 PM PDT 24 169149359 ps
T82 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3380618119 Jul 13 05:55:39 PM PDT 24 Jul 13 05:55:44 PM PDT 24 4165250305 ps
T91 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3766138635 Jul 13 05:55:45 PM PDT 24 Jul 13 05:55:47 PM PDT 24 77099979 ps
T83 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3498608931 Jul 13 05:56:39 PM PDT 24 Jul 13 05:56:42 PM PDT 24 196717246 ps
T84 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3316360215 Jul 13 05:56:02 PM PDT 24 Jul 13 05:56:06 PM PDT 24 140547511 ps
T303 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.277169518 Jul 13 05:55:53 PM PDT 24 Jul 13 05:56:00 PM PDT 24 4224994069 ps
T85 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2616168440 Jul 13 05:56:15 PM PDT 24 Jul 13 05:56:32 PM PDT 24 2307526309 ps
T304 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2332001252 Jul 13 05:55:36 PM PDT 24 Jul 13 05:55:37 PM PDT 24 175359724 ps
T305 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2824166886 Jul 13 05:56:17 PM PDT 24 Jul 13 05:56:21 PM PDT 24 1066528751 ps
T306 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.567824676 Jul 13 05:54:59 PM PDT 24 Jul 13 05:55:05 PM PDT 24 1660227418 ps
T92 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2459864708 Jul 13 05:54:55 PM PDT 24 Jul 13 05:54:59 PM PDT 24 801381700 ps
T93 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2374250818 Jul 13 05:55:39 PM PDT 24 Jul 13 05:55:47 PM PDT 24 1623883448 ps
T307 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2507470093 Jul 13 05:56:30 PM PDT 24 Jul 13 05:56:35 PM PDT 24 2277243381 ps
T308 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.562290862 Jul 13 05:54:58 PM PDT 24 Jul 13 05:54:59 PM PDT 24 65829293 ps
T97 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3788597480 Jul 13 05:55:05 PM PDT 24 Jul 13 05:55:10 PM PDT 24 3350147212 ps
T94 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.877885648 Jul 13 05:55:29 PM PDT 24 Jul 13 05:56:28 PM PDT 24 5865425742 ps
T86 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1269077850 Jul 13 05:55:45 PM PDT 24 Jul 13 05:55:56 PM PDT 24 4869993347 ps
T309 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1388713372 Jul 13 05:55:06 PM PDT 24 Jul 13 05:56:09 PM PDT 24 21735893492 ps
T310 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.187009552 Jul 13 05:56:39 PM PDT 24 Jul 13 05:56:47 PM PDT 24 2506347717 ps
T311 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.343920437 Jul 13 05:55:38 PM PDT 24 Jul 13 05:55:39 PM PDT 24 135612745 ps
T312 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4285980221 Jul 13 05:55:45 PM PDT 24 Jul 13 05:55:47 PM PDT 24 209147735 ps
T313 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2168011399 Jul 13 05:55:49 PM PDT 24 Jul 13 05:55:50 PM PDT 24 103440048 ps
T87 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.4218962465 Jul 13 05:56:02 PM PDT 24 Jul 13 05:56:08 PM PDT 24 479906134 ps
T114 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1525975536 Jul 13 05:55:11 PM PDT 24 Jul 13 05:55:20 PM PDT 24 586710708 ps
T100 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3374720062 Jul 13 05:56:37 PM PDT 24 Jul 13 05:56:41 PM PDT 24 694428115 ps
T115 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2813547704 Jul 13 05:56:00 PM PDT 24 Jul 13 05:56:07 PM PDT 24 246736738 ps
T314 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.825238858 Jul 13 05:55:19 PM PDT 24 Jul 13 05:55:23 PM PDT 24 2477906184 ps
T101 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1398709011 Jul 13 05:56:07 PM PDT 24 Jul 13 05:56:14 PM PDT 24 804271560 ps
T95 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.520843809 Jul 13 05:56:08 PM PDT 24 Jul 13 05:56:12 PM PDT 24 155586960 ps
T170 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3620517733 Jul 13 05:56:22 PM PDT 24 Jul 13 05:56:33 PM PDT 24 927738899 ps
T102 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.413979415 Jul 13 05:56:00 PM PDT 24 Jul 13 05:56:01 PM PDT 24 303446615 ps
T315 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1832258902 Jul 13 05:55:05 PM PDT 24 Jul 13 05:55:07 PM PDT 24 200794501 ps
T122 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.4268609060 Jul 13 05:56:16 PM PDT 24 Jul 13 05:56:36 PM PDT 24 6143345536 ps
T116 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.136333610 Jul 13 05:56:25 PM PDT 24 Jul 13 05:56:34 PM PDT 24 490670309 ps
T103 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.867621576 Jul 13 05:55:45 PM PDT 24 Jul 13 05:55:47 PM PDT 24 383265264 ps
T316 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2037635044 Jul 13 05:55:20 PM PDT 24 Jul 13 05:55:26 PM PDT 24 3355092292 ps
T317 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.490674596 Jul 13 05:56:16 PM PDT 24 Jul 13 05:56:18 PM PDT 24 845976246 ps
T318 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4004826013 Jul 13 05:55:37 PM PDT 24 Jul 13 05:55:50 PM PDT 24 14518149556 ps
T319 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1199974137 Jul 13 05:56:07 PM PDT 24 Jul 13 05:56:31 PM PDT 24 16932253493 ps
T104 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2139499441 Jul 13 05:55:54 PM PDT 24 Jul 13 05:55:57 PM PDT 24 465241956 ps
T320 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2163938229 Jul 13 05:56:15 PM PDT 24 Jul 13 05:56:20 PM PDT 24 8806215087 ps
T321 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2288606066 Jul 13 05:56:16 PM PDT 24 Jul 13 05:56:22 PM PDT 24 268229684 ps
T105 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1849469904 Jul 13 05:55:51 PM PDT 24 Jul 13 05:55:55 PM PDT 24 317370762 ps
T322 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2935223917 Jul 13 05:56:26 PM PDT 24 Jul 13 05:56:41 PM PDT 24 5406896150 ps
T110 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2994586735 Jul 13 05:55:38 PM PDT 24 Jul 13 05:55:41 PM PDT 24 464325400 ps
T323 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1311549420 Jul 13 05:54:49 PM PDT 24 Jul 13 05:54:53 PM PDT 24 1375876847 ps
T117 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.553097055 Jul 13 05:56:31 PM PDT 24 Jul 13 05:56:35 PM PDT 24 270946890 ps
T178 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.943908353 Jul 13 05:56:26 PM PDT 24 Jul 13 05:56:54 PM PDT 24 5058181755 ps
T111 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1147171917 Jul 13 05:56:38 PM PDT 24 Jul 13 05:56:40 PM PDT 24 264207018 ps
T324 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1024605522 Jul 13 05:56:02 PM PDT 24 Jul 13 05:56:51 PM PDT 24 18386673992 ps
T168 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3524250263 Jul 13 05:55:53 PM PDT 24 Jul 13 05:55:58 PM PDT 24 281728443 ps
T325 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2653560762 Jul 13 05:56:02 PM PDT 24 Jul 13 05:56:08 PM PDT 24 4371695640 ps
T112 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.236536179 Jul 13 05:54:56 PM PDT 24 Jul 13 05:54:59 PM PDT 24 89990891 ps
T326 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1914672650 Jul 13 05:54:57 PM PDT 24 Jul 13 05:55:01 PM PDT 24 267679519 ps
T123 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2358460858 Jul 13 05:55:46 PM PDT 24 Jul 13 05:56:24 PM PDT 24 3331571202 ps
T124 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.550272351 Jul 13 05:56:09 PM PDT 24 Jul 13 05:56:32 PM PDT 24 8292860301 ps
T118 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.685012427 Jul 13 05:54:56 PM PDT 24 Jul 13 05:55:01 PM PDT 24 231078626 ps
T327 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2792694814 Jul 13 05:56:09 PM PDT 24 Jul 13 05:56:16 PM PDT 24 296485105 ps
T328 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4080879258 Jul 13 05:54:49 PM PDT 24 Jul 13 05:54:50 PM PDT 24 387360250 ps
T329 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1463971162 Jul 13 05:55:29 PM PDT 24 Jul 13 05:55:32 PM PDT 24 432046578 ps
T98 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4072060159 Jul 13 05:55:36 PM PDT 24 Jul 13 05:55:46 PM PDT 24 3238740818 ps
T330 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3590140634 Jul 13 05:55:39 PM PDT 24 Jul 13 05:56:46 PM PDT 24 95960947234 ps
T331 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3888882960 Jul 13 05:56:30 PM PDT 24 Jul 13 05:56:34 PM PDT 24 3641324691 ps
T332 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3327292569 Jul 13 05:56:29 PM PDT 24 Jul 13 05:56:32 PM PDT 24 1530392633 ps
T333 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3438387144 Jul 13 05:54:54 PM PDT 24 Jul 13 05:54:56 PM PDT 24 58631615 ps
T334 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.51881163 Jul 13 05:56:09 PM PDT 24 Jul 13 05:56:13 PM PDT 24 490719776 ps
T335 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2998728602 Jul 13 05:55:42 PM PDT 24 Jul 13 05:55:44 PM PDT 24 501535529 ps
T336 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2481451899 Jul 13 05:56:30 PM PDT 24 Jul 13 05:56:34 PM PDT 24 557820534 ps
T337 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4028097964 Jul 13 05:56:15 PM PDT 24 Jul 13 05:56:18 PM PDT 24 172282929 ps
T338 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.667902508 Jul 13 05:55:03 PM PDT 24 Jul 13 05:55:07 PM PDT 24 201768703 ps
T339 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.75882959 Jul 13 05:55:04 PM PDT 24 Jul 13 05:55:33 PM PDT 24 10988522306 ps
T340 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3359902831 Jul 13 05:56:07 PM PDT 24 Jul 13 05:56:11 PM PDT 24 182115618 ps
T341 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1075052605 Jul 13 05:56:37 PM PDT 24 Jul 13 05:56:42 PM PDT 24 95108026 ps
T342 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.18832029 Jul 13 05:56:39 PM PDT 24 Jul 13 05:56:46 PM PDT 24 10552132033 ps
T343 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1045871344 Jul 13 05:55:59 PM PDT 24 Jul 13 05:56:01 PM PDT 24 123417915 ps
T180 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1168307017 Jul 13 05:56:36 PM PDT 24 Jul 13 05:56:54 PM PDT 24 1107129226 ps
T99 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.134842174 Jul 13 05:55:45 PM PDT 24 Jul 13 05:55:53 PM PDT 24 5260583726 ps
T176 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2284756915 Jul 13 05:55:03 PM PDT 24 Jul 13 05:55:16 PM PDT 24 1827953940 ps
T344 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2339248675 Jul 13 05:56:16 PM PDT 24 Jul 13 05:56:21 PM PDT 24 985650970 ps
T345 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2872289142 Jul 13 05:55:36 PM PDT 24 Jul 13 05:55:39 PM PDT 24 69282581 ps
T174 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1567873748 Jul 13 05:56:02 PM PDT 24 Jul 13 05:56:23 PM PDT 24 2198856195 ps
T346 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2074470764 Jul 13 05:55:54 PM PDT 24 Jul 13 05:56:01 PM PDT 24 1931842414 ps
T347 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.127394460 Jul 13 05:55:19 PM PDT 24 Jul 13 05:55:21 PM PDT 24 660178148 ps
T348 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2432644797 Jul 13 05:54:56 PM PDT 24 Jul 13 05:54:59 PM PDT 24 1770245825 ps
T113 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.369140074 Jul 13 05:54:52 PM PDT 24 Jul 13 05:55:23 PM PDT 24 1802033743 ps
T169 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1834317000 Jul 13 05:55:52 PM PDT 24 Jul 13 05:56:01 PM PDT 24 4005809538 ps
T349 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3883187601 Jul 13 05:56:16 PM PDT 24 Jul 13 05:56:19 PM PDT 24 129456602 ps
T179 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2908457405 Jul 13 05:56:02 PM PDT 24 Jul 13 05:56:22 PM PDT 24 1164293978 ps
T172 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3773382052 Jul 13 05:56:38 PM PDT 24 Jul 13 05:56:51 PM PDT 24 2874230044 ps
T350 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3779749997 Jul 13 05:54:56 PM PDT 24 Jul 13 05:54:58 PM PDT 24 486432103 ps
T351 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3770416120 Jul 13 05:56:07 PM PDT 24 Jul 13 05:56:11 PM PDT 24 6161385912 ps
T352 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.566527514 Jul 13 05:56:38 PM PDT 24 Jul 13 05:56:41 PM PDT 24 474605401 ps
T353 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3488312099 Jul 13 05:56:38 PM PDT 24 Jul 13 05:56:41 PM PDT 24 120280706 ps
T354 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2439849982 Jul 13 05:55:45 PM PDT 24 Jul 13 05:55:50 PM PDT 24 184790634 ps
T355 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2013711209 Jul 13 05:56:22 PM PDT 24 Jul 13 05:56:27 PM PDT 24 331588229 ps
T356 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3464430713 Jul 13 05:56:30 PM PDT 24 Jul 13 05:56:34 PM PDT 24 904049630 ps
T106 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2525085770 Jul 13 05:55:14 PM PDT 24 Jul 13 05:55:18 PM PDT 24 314563340 ps
T181 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.863630638 Jul 13 05:54:56 PM PDT 24 Jul 13 05:55:09 PM PDT 24 25740896346 ps
T357 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3881141688 Jul 13 05:56:29 PM PDT 24 Jul 13 05:56:30 PM PDT 24 256660165 ps
T358 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1915837405 Jul 13 05:56:36 PM PDT 24 Jul 13 05:56:41 PM PDT 24 205941964 ps
T359 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1582570180 Jul 13 05:55:31 PM PDT 24 Jul 13 05:55:32 PM PDT 24 93680592 ps
T360 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1859495317 Jul 13 05:55:05 PM PDT 24 Jul 13 05:55:14 PM PDT 24 2308923103 ps
T361 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3852596991 Jul 13 05:56:23 PM PDT 24 Jul 13 05:56:28 PM PDT 24 237455259 ps
T362 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3308593194 Jul 13 05:54:56 PM PDT 24 Jul 13 05:54:58 PM PDT 24 714456482 ps
T182 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.440585336 Jul 13 05:56:01 PM PDT 24 Jul 13 05:56:48 PM PDT 24 24327126306 ps
T363 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.75491188 Jul 13 05:56:31 PM PDT 24 Jul 13 05:56:33 PM PDT 24 129550686 ps
T173 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.713841865 Jul 13 05:56:30 PM PDT 24 Jul 13 05:56:55 PM PDT 24 3092153716 ps
T364 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2407900981 Jul 13 05:55:36 PM PDT 24 Jul 13 05:58:32 PM PDT 24 63751378917 ps
T365 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1687554331 Jul 13 05:55:11 PM PDT 24 Jul 13 05:55:13 PM PDT 24 1066939555 ps
T366 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3543492093 Jul 13 05:56:16 PM PDT 24 Jul 13 05:56:26 PM PDT 24 2845512357 ps
T367 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1664984 Jul 13 05:55:03 PM PDT 24 Jul 13 05:55:21 PM PDT 24 28197907283 ps
T368 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.196565145 Jul 13 05:56:22 PM PDT 24 Jul 13 05:56:25 PM PDT 24 1303468708 ps
T369 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.164652024 Jul 13 05:56:21 PM PDT 24 Jul 13 05:56:24 PM PDT 24 2226156498 ps
T370 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3820304463 Jul 13 05:56:38 PM PDT 24 Jul 13 05:56:42 PM PDT 24 3080861307 ps
T107 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1585678702 Jul 13 05:56:16 PM PDT 24 Jul 13 05:56:19 PM PDT 24 330815281 ps
T371 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.187369491 Jul 13 05:56:21 PM PDT 24 Jul 13 05:56:22 PM PDT 24 493837218 ps
T175 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3316166904 Jul 13 05:55:36 PM PDT 24 Jul 13 05:55:57 PM PDT 24 2633687274 ps
T372 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2267152424 Jul 13 05:56:24 PM PDT 24 Jul 13 05:56:26 PM PDT 24 653858338 ps
T373 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2859754023 Jul 13 05:56:07 PM PDT 24 Jul 13 05:56:12 PM PDT 24 1171879165 ps
T374 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3929975776 Jul 13 05:55:39 PM PDT 24 Jul 13 05:55:44 PM PDT 24 238475689 ps
T375 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1138112095 Jul 13 05:55:39 PM PDT 24 Jul 13 05:56:56 PM PDT 24 60969301122 ps
T376 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.447028111 Jul 13 05:56:16 PM PDT 24 Jul 13 05:56:20 PM PDT 24 194557340 ps
T377 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2121609208 Jul 13 05:55:05 PM PDT 24 Jul 13 05:56:45 PM PDT 24 67711492139 ps
T378 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4184171976 Jul 13 05:55:13 PM PDT 24 Jul 13 05:55:14 PM PDT 24 38865625 ps
T379 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.649702043 Jul 13 05:55:37 PM PDT 24 Jul 13 05:55:40 PM PDT 24 5211717951 ps
T380 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2025283180 Jul 13 05:56:21 PM PDT 24 Jul 13 05:56:22 PM PDT 24 746871101 ps
T381 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1953107525 Jul 13 05:56:07 PM PDT 24 Jul 13 05:56:56 PM PDT 24 34997033996 ps
T382 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1396303049 Jul 13 05:56:08 PM PDT 24 Jul 13 05:56:10 PM PDT 24 237996505 ps
T383 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1151485297 Jul 13 05:55:53 PM PDT 24 Jul 13 05:55:54 PM PDT 24 228174370 ps
T384 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.541234877 Jul 13 05:56:31 PM PDT 24 Jul 13 05:56:37 PM PDT 24 458602739 ps
T385 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2612308345 Jul 13 05:56:04 PM PDT 24 Jul 13 05:56:07 PM PDT 24 83691372 ps
T386 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2154650906 Jul 13 05:55:59 PM PDT 24 Jul 13 05:57:07 PM PDT 24 18784272088 ps
T387 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2005231691 Jul 13 05:55:06 PM PDT 24 Jul 13 05:55:07 PM PDT 24 44672780 ps
T388 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2061117378 Jul 13 05:56:07 PM PDT 24 Jul 13 05:56:10 PM PDT 24 458884477 ps
T171 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2029755753 Jul 13 05:55:28 PM PDT 24 Jul 13 05:55:37 PM PDT 24 1208898630 ps
T389 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.718350756 Jul 13 05:56:22 PM PDT 24 Jul 13 05:56:28 PM PDT 24 491684976 ps
T390 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.739269032 Jul 13 05:55:54 PM PDT 24 Jul 13 05:56:05 PM PDT 24 4380975766 ps
T391 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3495572869 Jul 13 05:55:12 PM PDT 24 Jul 13 05:56:24 PM PDT 24 6400252170 ps
T392 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.73406973 Jul 13 05:55:46 PM PDT 24 Jul 13 05:56:25 PM PDT 24 28465100014 ps
T393 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3641697818 Jul 13 05:55:49 PM PDT 24 Jul 13 05:55:50 PM PDT 24 71288925 ps
T394 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2778138493 Jul 13 05:55:36 PM PDT 24 Jul 13 05:55:38 PM PDT 24 43723763 ps
T395 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2492133758 Jul 13 05:56:21 PM PDT 24 Jul 13 05:56:24 PM PDT 24 187252868 ps
T396 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.19511951 Jul 13 05:56:26 PM PDT 24 Jul 13 05:57:01 PM PDT 24 12588123371 ps
T397 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.895661898 Jul 13 05:56:16 PM PDT 24 Jul 13 05:56:26 PM PDT 24 2764081019 ps
T398 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3077503090 Jul 13 05:55:49 PM PDT 24 Jul 13 05:55:54 PM PDT 24 1607078061 ps
T399 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2778136548 Jul 13 05:55:28 PM PDT 24 Jul 13 05:55:29 PM PDT 24 28288008 ps
T400 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3034896253 Jul 13 05:54:57 PM PDT 24 Jul 13 05:55:20 PM PDT 24 3922260021 ps
T401 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.118970782 Jul 13 05:55:53 PM PDT 24 Jul 13 05:56:00 PM PDT 24 349151536 ps
T402 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4153845216 Jul 13 05:55:35 PM PDT 24 Jul 13 05:55:38 PM PDT 24 930229527 ps
T403 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3709926327 Jul 13 05:55:46 PM PDT 24 Jul 13 05:55:52 PM PDT 24 4999470373 ps
T404 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.20502136 Jul 13 05:54:47 PM PDT 24 Jul 13 05:55:10 PM PDT 24 15491455017 ps
T405 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2215916039 Jul 13 05:56:30 PM PDT 24 Jul 13 05:56:35 PM PDT 24 761012384 ps
T406 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.372025689 Jul 13 05:55:29 PM PDT 24 Jul 13 05:55:31 PM PDT 24 148764437 ps
T407 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.294959703 Jul 13 05:55:47 PM PDT 24 Jul 13 05:55:49 PM PDT 24 390351826 ps
T408 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3572084851 Jul 13 05:56:08 PM PDT 24 Jul 13 05:56:10 PM PDT 24 144180319 ps
T409 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3685103039 Jul 13 05:55:54 PM PDT 24 Jul 13 05:56:03 PM PDT 24 2152564332 ps
T410 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2515117894 Jul 13 05:55:53 PM PDT 24 Jul 13 05:55:55 PM PDT 24 535841097 ps
T411 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.183064273 Jul 13 05:55:15 PM PDT 24 Jul 13 05:55:18 PM PDT 24 393290113 ps
T412 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3720780902 Jul 13 05:56:16 PM PDT 24 Jul 13 05:56:20 PM PDT 24 207901860 ps
T413 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1826664505 Jul 13 05:56:21 PM PDT 24 Jul 13 05:56:24 PM PDT 24 2466127811 ps
T414 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1038450608 Jul 13 05:54:57 PM PDT 24 Jul 13 05:55:01 PM PDT 24 1869988746 ps
T415 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1011187044 Jul 13 05:56:15 PM PDT 24 Jul 13 05:56:19 PM PDT 24 770616943 ps
T416 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1249545451 Jul 13 05:56:07 PM PDT 24 Jul 13 05:56:09 PM PDT 24 1011252703 ps
T417 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.714429074 Jul 13 05:55:10 PM PDT 24 Jul 13 05:55:12 PM PDT 24 129515873 ps
T418 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1478185859 Jul 13 05:56:07 PM PDT 24 Jul 13 05:56:09 PM PDT 24 477257288 ps
T419 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2747136777 Jul 13 05:56:25 PM PDT 24 Jul 13 05:56:28 PM PDT 24 793964724 ps
T420 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3576190200 Jul 13 05:56:01 PM PDT 24 Jul 13 05:56:05 PM PDT 24 2861450100 ps
T421 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1467919767 Jul 13 05:56:00 PM PDT 24 Jul 13 05:56:54 PM PDT 24 51047890075 ps
T422 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4094173918 Jul 13 05:55:53 PM PDT 24 Jul 13 05:55:56 PM PDT 24 1833442926 ps
T423 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1834843802 Jul 13 05:56:15 PM PDT 24 Jul 13 05:56:18 PM PDT 24 5315511131 ps
T424 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1328408783 Jul 13 05:56:01 PM PDT 24 Jul 13 05:56:30 PM PDT 24 11043484671 ps
T425 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.196286351 Jul 13 05:55:53 PM PDT 24 Jul 13 05:55:57 PM PDT 24 382177848 ps
T426 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2720412078 Jul 13 05:55:20 PM PDT 24 Jul 13 05:57:15 PM PDT 24 103021141706 ps
T427 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2196739243 Jul 13 05:56:15 PM PDT 24 Jul 13 05:56:23 PM PDT 24 462172746 ps
T428 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2480832186 Jul 13 05:56:37 PM PDT 24 Jul 13 05:56:44 PM PDT 24 1547242175 ps
T429 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.201029004 Jul 13 05:56:30 PM PDT 24 Jul 13 05:57:02 PM PDT 24 40689580015 ps
T430 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.4117114989 Jul 13 05:56:26 PM PDT 24 Jul 13 05:56:33 PM PDT 24 326947909 ps
T431 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.446812198 Jul 13 05:56:00 PM PDT 24 Jul 13 05:56:05 PM PDT 24 885769217 ps
T432 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1758754495 Jul 13 05:55:44 PM PDT 24 Jul 13 05:56:56 PM PDT 24 41506903058 ps
T433 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1313763015 Jul 13 05:55:39 PM PDT 24 Jul 13 05:56:02 PM PDT 24 16185143190 ps
T434 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1268882217 Jul 13 05:56:00 PM PDT 24 Jul 13 05:56:01 PM PDT 24 472767324 ps
T435 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2648134481 Jul 13 05:55:59 PM PDT 24 Jul 13 05:56:08 PM PDT 24 584916443 ps
T436 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2814994376 Jul 13 05:55:36 PM PDT 24 Jul 13 05:55:40 PM PDT 24 1294577398 ps
T437 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1019597666 Jul 13 05:55:29 PM PDT 24 Jul 13 05:55:34 PM PDT 24 548968237 ps
T438 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3908839959 Jul 13 05:56:30 PM PDT 24 Jul 13 05:56:38 PM PDT 24 253191674 ps
T439 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2502333553 Jul 13 05:55:47 PM PDT 24 Jul 13 05:55:55 PM PDT 24 15593182299 ps
T440 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3845682989 Jul 13 05:56:02 PM PDT 24 Jul 13 05:56:06 PM PDT 24 644029566 ps
T441 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2364078678 Jul 13 05:56:29 PM PDT 24 Jul 13 05:56:32 PM PDT 24 193921322 ps
T442 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3108584981 Jul 13 05:55:04 PM PDT 24 Jul 13 05:55:06 PM PDT 24 301205676 ps
T443 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.475778911 Jul 13 05:55:59 PM PDT 24 Jul 13 05:56:03 PM PDT 24 10364306694 ps
T108 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2417552118 Jul 13 05:55:12 PM PDT 24 Jul 13 05:55:14 PM PDT 24 62139991 ps
T177 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2572395525 Jul 13 05:56:07 PM PDT 24 Jul 13 05:56:28 PM PDT 24 5142178917 ps
T444 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3102219715 Jul 13 05:56:21 PM PDT 24 Jul 13 05:57:07 PM PDT 24 18864279725 ps
T445 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.745626413 Jul 13 05:55:51 PM PDT 24 Jul 13 05:55:55 PM PDT 24 4603943329 ps
T109 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2315048797 Jul 13 05:55:38 PM PDT 24 Jul 13 05:56:11 PM PDT 24 4499671975 ps
T446 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3079165246 Jul 13 05:56:30 PM PDT 24 Jul 13 05:56:32 PM PDT 24 626244658 ps

Test location /workspace/coverage/default/39.rv_dm_stress_all.785361208
Short name T4
Test name
Test status
Simulation time 2562242201 ps
CPU time 4.64 seconds
Started Jul 13 04:45:43 PM PDT 24
Finished Jul 13 04:45:50 PM PDT 24
Peak memory 205312 kb
Host smart-9e18b12b-566f-4400-92d1-40ec9e55f970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785361208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.785361208
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2877072773
Short name T33
Test name
Test status
Simulation time 9227899188 ps
CPU time 25.17 seconds
Started Jul 13 04:45:32 PM PDT 24
Finished Jul 13 04:45:58 PM PDT 24
Peak memory 213660 kb
Host smart-9a4eb2a5-06bf-4970-92fc-c1be4c6c2d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877072773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2877072773
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3522266940
Short name T56
Test name
Test status
Simulation time 45496828078 ps
CPU time 139.36 seconds
Started Jul 13 05:55:55 PM PDT 24
Finished Jul 13 05:58:15 PM PDT 24
Peak memory 221468 kb
Host smart-709b078d-ad30-4433-a963-303898e3b73c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522266940 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3522266940
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.740484873
Short name T44
Test name
Test status
Simulation time 6604802697 ps
CPU time 8.32 seconds
Started Jul 13 04:44:49 PM PDT 24
Finished Jul 13 04:44:59 PM PDT 24
Peak memory 205368 kb
Host smart-76b5228d-bc87-465d-bd8f-7b56f0e08e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740484873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.740484873
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.2099916285
Short name T20
Test name
Test status
Simulation time 7905965119 ps
CPU time 11.78 seconds
Started Jul 13 04:45:43 PM PDT 24
Finished Jul 13 04:45:56 PM PDT 24
Peak memory 213504 kb
Host smart-78033873-b417-4934-bc26-533e221ba560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099916285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2099916285
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3686989785
Short name T66
Test name
Test status
Simulation time 3347139202 ps
CPU time 9.57 seconds
Started Jul 13 05:56:30 PM PDT 24
Finished Jul 13 05:56:40 PM PDT 24
Peak memory 213180 kb
Host smart-541a9e6d-cb90-4e83-a903-434c353ee938
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686989785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
686989785
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.681573465
Short name T49
Test name
Test status
Simulation time 68198325 ps
CPU time 0.8 seconds
Started Jul 13 04:45:24 PM PDT 24
Finished Jul 13 04:45:26 PM PDT 24
Peak memory 205096 kb
Host smart-8c064150-72df-45ad-a51e-9a8d4d3401c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681573465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.681573465
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2095982246
Short name T156
Test name
Test status
Simulation time 4746094911 ps
CPU time 9.34 seconds
Started Jul 13 04:45:13 PM PDT 24
Finished Jul 13 04:45:23 PM PDT 24
Peak memory 213668 kb
Host smart-4fbab19f-9b6e-485c-88be-d21e2f0fa564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095982246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2095982246
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2238645969
Short name T12
Test name
Test status
Simulation time 8097326431 ps
CPU time 20.68 seconds
Started Jul 13 04:45:44 PM PDT 24
Finished Jul 13 04:46:07 PM PDT 24
Peak memory 213544 kb
Host smart-bf063531-5747-40bf-87b7-1cb49a1c1aa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238645969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2238645969
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3394925833
Short name T279
Test name
Test status
Simulation time 66812103324 ps
CPU time 94.47 seconds
Started Jul 13 04:45:22 PM PDT 24
Finished Jul 13 04:46:57 PM PDT 24
Peak memory 214684 kb
Host smart-52db6334-742d-408c-a6d6-8b9db49b44fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394925833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3394925833
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.1204988992
Short name T24
Test name
Test status
Simulation time 1061962570 ps
CPU time 1.71 seconds
Started Jul 13 04:44:43 PM PDT 24
Finished Jul 13 04:44:46 PM PDT 24
Peak memory 205004 kb
Host smart-aa8ccfc9-23f7-4fa5-b5f6-341d734222c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204988992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1204988992
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.2059021933
Short name T3
Test name
Test status
Simulation time 43992463 ps
CPU time 0.91 seconds
Started Jul 13 04:44:53 PM PDT 24
Finished Jul 13 04:44:55 PM PDT 24
Peak memory 215364 kb
Host smart-e42025b6-20fc-4e51-a441-12850f3213c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059021933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.2059021933
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1298061785
Short name T70
Test name
Test status
Simulation time 3179913210 ps
CPU time 27.83 seconds
Started Jul 13 05:54:56 PM PDT 24
Finished Jul 13 05:55:24 PM PDT 24
Peak memory 213180 kb
Host smart-eca3492c-8fab-4c55-b131-af30f19c2a42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298061785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1298061785
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2616168440
Short name T85
Test name
Test status
Simulation time 2307526309 ps
CPU time 16.69 seconds
Started Jul 13 05:56:15 PM PDT 24
Finished Jul 13 05:56:32 PM PDT 24
Peak memory 213216 kb
Host smart-98845f33-2773-4b49-8ad3-f463196ab99e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616168440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
616168440
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1099263917
Short name T31
Test name
Test status
Simulation time 1780101476 ps
CPU time 1.57 seconds
Started Jul 13 04:44:43 PM PDT 24
Finished Jul 13 04:44:46 PM PDT 24
Peak memory 205180 kb
Host smart-b91c46cf-e07a-4463-9d9f-3c0455819e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099263917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1099263917
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.2424393820
Short name T14
Test name
Test status
Simulation time 6701258251 ps
CPU time 5.67 seconds
Started Jul 13 04:45:45 PM PDT 24
Finished Jul 13 04:45:52 PM PDT 24
Peak memory 205308 kb
Host smart-ce3d23d1-0537-4bba-abe3-d568b6745188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424393820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2424393820
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.280150873
Short name T7
Test name
Test status
Simulation time 146583225 ps
CPU time 0.78 seconds
Started Jul 13 04:44:54 PM PDT 24
Finished Jul 13 04:44:56 PM PDT 24
Peak memory 205008 kb
Host smart-b1483c4f-e7d2-4c0d-b377-489f9a00a5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280150873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.280150873
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2505787408
Short name T53
Test name
Test status
Simulation time 2346115459 ps
CPU time 7.41 seconds
Started Jul 13 04:45:02 PM PDT 24
Finished Jul 13 04:45:11 PM PDT 24
Peak memory 228896 kb
Host smart-928592c5-1a7f-4785-b481-751900e0f52d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505787408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2505787408
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3023497692
Short name T43
Test name
Test status
Simulation time 302504367 ps
CPU time 0.86 seconds
Started Jul 13 04:44:54 PM PDT 24
Finished Jul 13 04:44:56 PM PDT 24
Peak memory 213332 kb
Host smart-09d05777-40b3-4e81-ac59-ad1c4fd9cf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023497692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3023497692
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.1213284505
Short name T132
Test name
Test status
Simulation time 8005596356 ps
CPU time 12.64 seconds
Started Jul 13 04:45:42 PM PDT 24
Finished Jul 13 04:45:56 PM PDT 24
Peak memory 214584 kb
Host smart-1d84ec05-60b1-4b7a-a3ec-999a4876acbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213284505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1213284505
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.1211312293
Short name T57
Test name
Test status
Simulation time 173940063 ps
CPU time 0.96 seconds
Started Jul 13 04:44:54 PM PDT 24
Finished Jul 13 04:44:56 PM PDT 24
Peak memory 205072 kb
Host smart-46b38e16-c6c5-409d-a30e-53a408e4293b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211312293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.1211312293
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.867621576
Short name T103
Test name
Test status
Simulation time 383265264 ps
CPU time 1.73 seconds
Started Jul 13 05:55:45 PM PDT 24
Finished Jul 13 05:55:47 PM PDT 24
Peak memory 213188 kb
Host smart-9ae3f740-dabd-4625-a260-89b6b16418b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867621576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.867621576
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.319604839
Short name T37
Test name
Test status
Simulation time 2294823729 ps
CPU time 1.69 seconds
Started Jul 13 04:45:12 PM PDT 24
Finished Jul 13 04:45:15 PM PDT 24
Peak memory 213608 kb
Host smart-2a421684-e988-4ba6-be35-30e17f3a1fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319604839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.319604839
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.1377973580
Short name T26
Test name
Test status
Simulation time 6617493727 ps
CPU time 19.39 seconds
Started Jul 13 04:45:31 PM PDT 24
Finished Jul 13 04:45:52 PM PDT 24
Peak memory 205268 kb
Host smart-5bf8f27b-e10d-455e-86b5-8c0037810439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377973580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1377973580
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2932101097
Short name T166
Test name
Test status
Simulation time 2317537497 ps
CPU time 7.67 seconds
Started Jul 13 04:44:54 PM PDT 24
Finished Jul 13 04:45:03 PM PDT 24
Peak memory 214676 kb
Host smart-94f1e381-727d-47df-83d0-ffeebb43c480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932101097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2932101097
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.3220248117
Short name T25
Test name
Test status
Simulation time 2346823864 ps
CPU time 2.92 seconds
Started Jul 13 04:45:33 PM PDT 24
Finished Jul 13 04:45:38 PM PDT 24
Peak memory 205328 kb
Host smart-c42b10fc-8cef-4e0a-bbf9-500b864f1bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220248117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3220248117
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.4007843241
Short name T23
Test name
Test status
Simulation time 5966200453 ps
CPU time 16.64 seconds
Started Jul 13 04:44:45 PM PDT 24
Finished Jul 13 04:45:03 PM PDT 24
Peak memory 205348 kb
Host smart-7aba00c5-7a72-4940-a465-08ea7b68d193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007843241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.4007843241
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2318386743
Short name T46
Test name
Test status
Simulation time 263834647 ps
CPU time 0.91 seconds
Started Jul 13 04:44:54 PM PDT 24
Finished Jul 13 04:44:56 PM PDT 24
Peak memory 205008 kb
Host smart-a259d3c3-3fc8-40bc-8ed7-df7218d03e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318386743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2318386743
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2572395525
Short name T177
Test name
Test status
Simulation time 5142178917 ps
CPU time 20.2 seconds
Started Jul 13 05:56:07 PM PDT 24
Finished Jul 13 05:56:28 PM PDT 24
Peak memory 221076 kb
Host smart-f8be0456-9d45-4628-b175-88a2bf5610ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572395525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2572395525
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3731499990
Short name T158
Test name
Test status
Simulation time 68919890519 ps
CPU time 57.31 seconds
Started Jul 13 04:44:53 PM PDT 24
Finished Jul 13 04:45:51 PM PDT 24
Peak memory 216492 kb
Host smart-5d32b319-e334-49be-9d54-2e94c0be5660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731499990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3731499990
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1627261348
Short name T165
Test name
Test status
Simulation time 11789814784 ps
CPU time 12.43 seconds
Started Jul 13 04:45:01 PM PDT 24
Finished Jul 13 04:45:15 PM PDT 24
Peak memory 213636 kb
Host smart-44ca0fe7-8b3b-4c8b-90ad-d1159992742f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627261348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1627261348
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.1414438609
Short name T39
Test name
Test status
Simulation time 4503589373 ps
CPU time 6.94 seconds
Started Jul 13 04:45:43 PM PDT 24
Finished Jul 13 04:45:51 PM PDT 24
Peak memory 213464 kb
Host smart-ef8cc7b6-02ee-40e6-bb3d-062a9480695f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414438609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1414438609
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1525975536
Short name T114
Test name
Test status
Simulation time 586710708 ps
CPU time 8.07 seconds
Started Jul 13 05:55:11 PM PDT 24
Finished Jul 13 05:55:20 PM PDT 24
Peak memory 204980 kb
Host smart-faf7cc92-6289-4b8d-9114-f37ab0b3255a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525975536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1525975536
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2824166886
Short name T305
Test name
Test status
Simulation time 1066528751 ps
CPU time 3.56 seconds
Started Jul 13 05:56:17 PM PDT 24
Finished Jul 13 05:56:21 PM PDT 24
Peak memory 204616 kb
Host smart-0f4b788f-4005-451d-bbcb-d9f8ef286276
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824166886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2824166886
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.750260499
Short name T41
Test name
Test status
Simulation time 720702526 ps
CPU time 3.14 seconds
Started Jul 13 04:44:46 PM PDT 24
Finished Jul 13 04:44:50 PM PDT 24
Peak memory 204984 kb
Host smart-89e5553a-4425-4101-8acd-dc6071ccac7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750260499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.750260499
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2407900981
Short name T364
Test name
Test status
Simulation time 63751378917 ps
CPU time 175.91 seconds
Started Jul 13 05:55:36 PM PDT 24
Finished Jul 13 05:58:32 PM PDT 24
Peak memory 223780 kb
Host smart-93ec3733-7a53-4a25-a6a5-fc55abbda416
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407900981 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2407900981
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1567873748
Short name T174
Test name
Test status
Simulation time 2198856195 ps
CPU time 20.44 seconds
Started Jul 13 05:56:02 PM PDT 24
Finished Jul 13 05:56:23 PM PDT 24
Peak memory 213152 kb
Host smart-31d09620-6d9e-4924-9e80-1650ba193d61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567873748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1567873748
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.113488120
Short name T159
Test name
Test status
Simulation time 19991198353 ps
CPU time 49.68 seconds
Started Jul 13 04:45:25 PM PDT 24
Finished Jul 13 04:46:15 PM PDT 24
Peak memory 213760 kb
Host smart-ebbb4bdc-9e26-4cb7-a5ed-504febbcc8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113488120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.113488120
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.671361781
Short name T45
Test name
Test status
Simulation time 4438872619 ps
CPU time 13.82 seconds
Started Jul 13 04:45:32 PM PDT 24
Finished Jul 13 04:45:48 PM PDT 24
Peak memory 205380 kb
Host smart-d0bcccfe-ffa1-4a4d-9a41-2c22f3a82503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671361781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.671361781
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.3938942290
Short name T15
Test name
Test status
Simulation time 6396882463 ps
CPU time 10.17 seconds
Started Jul 13 04:45:45 PM PDT 24
Finished Jul 13 04:45:57 PM PDT 24
Peak memory 205440 kb
Host smart-9ac31947-45c0-4ffe-a9d0-c23891e41359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938942290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3938942290
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3788597480
Short name T97
Test name
Test status
Simulation time 3350147212 ps
CPU time 4.28 seconds
Started Jul 13 05:55:05 PM PDT 24
Finished Jul 13 05:55:10 PM PDT 24
Peak memory 204916 kb
Host smart-30f39043-c25f-4a80-aff8-512e85a5484b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788597480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3788597480
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.16384579
Short name T272
Test name
Test status
Simulation time 9144131951 ps
CPU time 8.23 seconds
Started Jul 13 04:45:24 PM PDT 24
Finished Jul 13 04:45:33 PM PDT 24
Peak memory 213600 kb
Host smart-db8d3e70-46e7-4455-bc10-b41f580709c0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16384579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_tl
_access.16384579
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2806548585
Short name T38
Test name
Test status
Simulation time 7173359059 ps
CPU time 20.21 seconds
Started Jul 13 04:44:44 PM PDT 24
Finished Jul 13 04:45:05 PM PDT 24
Peak memory 213668 kb
Host smart-9d334d19-2156-46f9-92d7-00686d5edd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806548585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2806548585
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3180624837
Short name T167
Test name
Test status
Simulation time 1783650118 ps
CPU time 1.34 seconds
Started Jul 13 04:44:44 PM PDT 24
Finished Jul 13 04:44:46 PM PDT 24
Peak memory 205004 kb
Host smart-9e040f5d-9674-4d1f-9896-aaf4577e81ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180624837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3180624837
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3300811143
Short name T150
Test name
Test status
Simulation time 700707125 ps
CPU time 1.1 seconds
Started Jul 13 04:44:47 PM PDT 24
Finished Jul 13 04:44:49 PM PDT 24
Peak memory 205320 kb
Host smart-f0b75009-03b7-4503-a6d6-1e3b1b42e6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300811143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3300811143
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.1376066528
Short name T61
Test name
Test status
Simulation time 99032063 ps
CPU time 1.21 seconds
Started Jul 13 04:44:57 PM PDT 24
Finished Jul 13 04:44:58 PM PDT 24
Peak memory 215428 kb
Host smart-241e942b-d977-490e-849a-21ddc2d7390a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376066528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1376066528
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.570734308
Short name T160
Test name
Test status
Simulation time 2717952464 ps
CPU time 3.25 seconds
Started Jul 13 04:44:58 PM PDT 24
Finished Jul 13 04:45:02 PM PDT 24
Peak memory 213592 kb
Host smart-50cb6c46-75a3-4cfe-ab00-596008a32cd7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570734308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl
_access.570734308
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.3239679138
Short name T17
Test name
Test status
Simulation time 5770229692 ps
CPU time 11.81 seconds
Started Jul 13 04:45:23 PM PDT 24
Finished Jul 13 04:45:36 PM PDT 24
Peak memory 205236 kb
Host smart-8446ce98-3a9b-4694-8de4-d9c0484dbacf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239679138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3239679138
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2657218029
Short name T152
Test name
Test status
Simulation time 11373818745 ps
CPU time 17.06 seconds
Started Jul 13 04:45:23 PM PDT 24
Finished Jul 13 04:45:42 PM PDT 24
Peak memory 213560 kb
Host smart-199c2a1c-2f8e-49c6-9cd2-28ddd8833a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657218029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2657218029
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.543184033
Short name T30
Test name
Test status
Simulation time 4631484713 ps
CPU time 14.33 seconds
Started Jul 13 04:45:22 PM PDT 24
Finished Jul 13 04:45:37 PM PDT 24
Peak memory 205244 kb
Host smart-7734dfe5-3eef-456e-b5af-1ac89f794a32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543184033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.543184033
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.745207696
Short name T155
Test name
Test status
Simulation time 7442559981 ps
CPU time 19.43 seconds
Started Jul 13 04:45:22 PM PDT 24
Finished Jul 13 04:45:43 PM PDT 24
Peak memory 213588 kb
Host smart-0f2948cd-6fab-490a-8ca4-c89bd5d75f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745207696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.745207696
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.1783509718
Short name T142
Test name
Test status
Simulation time 7565379423 ps
CPU time 6.72 seconds
Started Jul 13 04:45:32 PM PDT 24
Finished Jul 13 04:45:39 PM PDT 24
Peak memory 213268 kb
Host smart-307b37cc-2a85-45ea-8c9e-8bc193cb6c00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783509718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1783509718
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3995113879
Short name T161
Test name
Test status
Simulation time 1041519609 ps
CPU time 3.69 seconds
Started Jul 13 04:45:33 PM PDT 24
Finished Jul 13 04:45:39 PM PDT 24
Peak memory 213564 kb
Host smart-427f3beb-13e9-4011-b216-77ce378b4ee6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3995113879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3995113879
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.3095501928
Short name T133
Test name
Test status
Simulation time 4351674131 ps
CPU time 7.4 seconds
Started Jul 13 04:45:35 PM PDT 24
Finished Jul 13 04:45:45 PM PDT 24
Peak memory 205224 kb
Host smart-c90ec5c7-dbe4-4341-b735-b75aefeb5d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095501928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3095501928
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.2228811700
Short name T153
Test name
Test status
Simulation time 14669153642 ps
CPU time 44.31 seconds
Started Jul 13 04:45:03 PM PDT 24
Finished Jul 13 04:45:49 PM PDT 24
Peak memory 213640 kb
Host smart-0db71ac0-2b64-48cb-a7b8-da2a1fafaa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228811700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2228811700
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.482278346
Short name T144
Test name
Test status
Simulation time 4708046041 ps
CPU time 8.18 seconds
Started Jul 13 04:45:33 PM PDT 24
Finished Jul 13 04:45:44 PM PDT 24
Peak memory 205528 kb
Host smart-8acde174-05be-44cb-9bc7-cd72145f9935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482278346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.482278346
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.2346056283
Short name T138
Test name
Test status
Simulation time 2793399588 ps
CPU time 3.72 seconds
Started Jul 13 04:45:44 PM PDT 24
Finished Jul 13 04:45:49 PM PDT 24
Peak memory 213568 kb
Host smart-79297059-81e4-424a-b2bb-c0dac326040e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346056283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2346056283
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3731789152
Short name T154
Test name
Test status
Simulation time 1672337996 ps
CPU time 3.7 seconds
Started Jul 13 04:45:02 PM PDT 24
Finished Jul 13 04:45:07 PM PDT 24
Peak memory 205468 kb
Host smart-4a445270-7350-4f6c-adb1-c0ab23a3e369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731789152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3731789152
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.4024851883
Short name T2
Test name
Test status
Simulation time 3894967540 ps
CPU time 7.81 seconds
Started Jul 13 04:45:03 PM PDT 24
Finished Jul 13 04:45:12 PM PDT 24
Peak memory 213592 kb
Host smart-24419a8b-1c72-48c7-b573-846376c4fabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024851883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.4024851883
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.2533248572
Short name T128
Test name
Test status
Simulation time 4061520618 ps
CPU time 1.94 seconds
Started Jul 13 04:45:00 PM PDT 24
Finished Jul 13 04:45:03 PM PDT 24
Peak memory 205340 kb
Host smart-5df94fbb-3ba2-45ca-89fd-b1c414e16435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533248572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2533248572
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.2727889872
Short name T149
Test name
Test status
Simulation time 2060983648 ps
CPU time 5.01 seconds
Started Jul 13 04:45:14 PM PDT 24
Finished Jul 13 04:45:20 PM PDT 24
Peak memory 205396 kb
Host smart-b641cf03-4ea0-4667-8281-38eaf0e3e437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727889872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.2727889872
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.369140074
Short name T113
Test name
Test status
Simulation time 1802033743 ps
CPU time 30.89 seconds
Started Jul 13 05:54:52 PM PDT 24
Finished Jul 13 05:55:23 PM PDT 24
Peak memory 204840 kb
Host smart-88f2efde-9efe-4bb3-b04a-b56c3bdc2960
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369140074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.369140074
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.236536179
Short name T112
Test name
Test status
Simulation time 89990891 ps
CPU time 2.37 seconds
Started Jul 13 05:54:56 PM PDT 24
Finished Jul 13 05:54:59 PM PDT 24
Peak memory 213244 kb
Host smart-ca091234-eef3-4599-a40f-21a8010a127c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236536179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.236536179
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1038450608
Short name T414
Test name
Test status
Simulation time 1869988746 ps
CPU time 3.21 seconds
Started Jul 13 05:54:57 PM PDT 24
Finished Jul 13 05:55:01 PM PDT 24
Peak memory 221244 kb
Host smart-0d74bc1b-9c84-47a5-b8e1-3e3940c04c18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038450608 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1038450608
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2459864708
Short name T92
Test name
Test status
Simulation time 801381700 ps
CPU time 2.6 seconds
Started Jul 13 05:54:55 PM PDT 24
Finished Jul 13 05:54:59 PM PDT 24
Peak memory 213024 kb
Host smart-39b1882a-0c00-4600-9e50-e8513f0bb4d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459864708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2459864708
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1041122450
Short name T295
Test name
Test status
Simulation time 19326089827 ps
CPU time 51.67 seconds
Started Jul 13 05:54:56 PM PDT 24
Finished Jul 13 05:55:48 PM PDT 24
Peak memory 204964 kb
Host smart-b93a8e01-8517-46ae-b7cb-4f7ea324bfa1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041122450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1041122450
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3081077917
Short name T299
Test name
Test status
Simulation time 4960343147 ps
CPU time 2.08 seconds
Started Jul 13 05:54:55 PM PDT 24
Finished Jul 13 05:54:58 PM PDT 24
Peak memory 204784 kb
Host smart-748fc1e4-52a6-4657-ab9f-bf12e8056f3c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081077917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.3081077917
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.567824676
Short name T306
Test name
Test status
Simulation time 1660227418 ps
CPU time 5.57 seconds
Started Jul 13 05:54:59 PM PDT 24
Finished Jul 13 05:55:05 PM PDT 24
Peak memory 204840 kb
Host smart-2ccf42c6-4a4b-4695-ab26-b6ce88ae6a6b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567824676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.567824676
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2432644797
Short name T348
Test name
Test status
Simulation time 1770245825 ps
CPU time 1.96 seconds
Started Jul 13 05:54:56 PM PDT 24
Finished Jul 13 05:54:59 PM PDT 24
Peak memory 204912 kb
Host smart-5a5c9e19-d32e-4620-839f-86bcba190ce5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432644797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
432644797
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3308593194
Short name T362
Test name
Test status
Simulation time 714456482 ps
CPU time 1.77 seconds
Started Jul 13 05:54:56 PM PDT 24
Finished Jul 13 05:54:58 PM PDT 24
Peak memory 204640 kb
Host smart-96228071-262a-414c-8b9e-f13217ec5dc8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308593194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3308593194
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.20502136
Short name T404
Test name
Test status
Simulation time 15491455017 ps
CPU time 22.76 seconds
Started Jul 13 05:54:47 PM PDT 24
Finished Jul 13 05:55:10 PM PDT 24
Peak memory 204900 kb
Host smart-d9248d47-c8ec-474f-9b2a-a275657e64b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20502136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_
bit_bash.20502136
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1311549420
Short name T323
Test name
Test status
Simulation time 1375876847 ps
CPU time 4.35 seconds
Started Jul 13 05:54:49 PM PDT 24
Finished Jul 13 05:54:53 PM PDT 24
Peak memory 204636 kb
Host smart-6c1763b4-091b-4849-9fce-54121ace8284
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311549420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1311549420
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.4080879258
Short name T328
Test name
Test status
Simulation time 387360250 ps
CPU time 1.19 seconds
Started Jul 13 05:54:49 PM PDT 24
Finished Jul 13 05:54:50 PM PDT 24
Peak memory 204608 kb
Host smart-d3a9a0cc-f427-40ec-ae41-c1fc329ddcb6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080879258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.4
080879258
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.562290862
Short name T308
Test name
Test status
Simulation time 65829293 ps
CPU time 0.68 seconds
Started Jul 13 05:54:58 PM PDT 24
Finished Jul 13 05:54:59 PM PDT 24
Peak memory 204604 kb
Host smart-9ef2c81e-0673-4843-b4fc-d9114c80998e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562290862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.562290862
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3438387144
Short name T333
Test name
Test status
Simulation time 58631615 ps
CPU time 0.7 seconds
Started Jul 13 05:54:54 PM PDT 24
Finished Jul 13 05:54:56 PM PDT 24
Peak memory 204648 kb
Host smart-03328d92-4d03-4f44-b349-299287273da9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438387144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3438387144
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.685012427
Short name T118
Test name
Test status
Simulation time 231078626 ps
CPU time 4.3 seconds
Started Jul 13 05:54:56 PM PDT 24
Finished Jul 13 05:55:01 PM PDT 24
Peak memory 204948 kb
Host smart-9f3e8684-db2a-4a49-a81a-82b2c9cca2df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685012427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_c
sr_outstanding.685012427
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.863630638
Short name T181
Test name
Test status
Simulation time 25740896346 ps
CPU time 12.22 seconds
Started Jul 13 05:54:56 PM PDT 24
Finished Jul 13 05:55:09 PM PDT 24
Peak memory 221040 kb
Host smart-b21c7e13-649d-4065-8838-11d3332f4cbb
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863630638 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.863630638
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1914672650
Short name T326
Test name
Test status
Simulation time 267679519 ps
CPU time 2.66 seconds
Started Jul 13 05:54:57 PM PDT 24
Finished Jul 13 05:55:01 PM PDT 24
Peak memory 213200 kb
Host smart-0f619e7e-c8ab-431b-8b25-d4a3b0b983e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914672650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1914672650
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3034896253
Short name T400
Test name
Test status
Simulation time 3922260021 ps
CPU time 23.05 seconds
Started Jul 13 05:54:57 PM PDT 24
Finished Jul 13 05:55:20 PM PDT 24
Peak memory 213148 kb
Host smart-3e1156f6-2445-489a-82cd-b2dfc240a06e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034896253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3034896253
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.712569076
Short name T90
Test name
Test status
Simulation time 4723823969 ps
CPU time 68.75 seconds
Started Jul 13 05:54:59 PM PDT 24
Finished Jul 13 05:56:08 PM PDT 24
Peak memory 213236 kb
Host smart-07151dbc-0e46-4031-9a64-fcf0203172b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712569076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.712569076
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3495572869
Short name T391
Test name
Test status
Simulation time 6400252170 ps
CPU time 71.46 seconds
Started Jul 13 05:55:12 PM PDT 24
Finished Jul 13 05:56:24 PM PDT 24
Peak memory 213116 kb
Host smart-21cc8dab-2e88-447b-8754-a74f0bff6e2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495572869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3495572869
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2525085770
Short name T106
Test name
Test status
Simulation time 314563340 ps
CPU time 3.04 seconds
Started Jul 13 05:55:14 PM PDT 24
Finished Jul 13 05:55:18 PM PDT 24
Peak memory 213588 kb
Host smart-02d44552-f2b9-4c77-a5b9-caeb86e15ec9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525085770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2525085770
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.183064273
Short name T411
Test name
Test status
Simulation time 393290113 ps
CPU time 2.81 seconds
Started Jul 13 05:55:15 PM PDT 24
Finished Jul 13 05:55:18 PM PDT 24
Peak memory 215128 kb
Host smart-c2b536fc-6ffc-4016-94d1-e9e80e1e26d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183064273 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.183064273
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2417552118
Short name T108
Test name
Test status
Simulation time 62139991 ps
CPU time 1.51 seconds
Started Jul 13 05:55:12 PM PDT 24
Finished Jul 13 05:55:14 PM PDT 24
Peak memory 213168 kb
Host smart-81b21263-d311-4998-a46c-e5969c90b0ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417552118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2417552118
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2121609208
Short name T377
Test name
Test status
Simulation time 67711492139 ps
CPU time 98.07 seconds
Started Jul 13 05:55:05 PM PDT 24
Finished Jul 13 05:56:45 PM PDT 24
Peak memory 205184 kb
Host smart-e585f3c8-0eef-457a-8801-75c1606bec34
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121609208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2121609208
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.75882959
Short name T339
Test name
Test status
Simulation time 10988522306 ps
CPU time 28.96 seconds
Started Jul 13 05:55:04 PM PDT 24
Finished Jul 13 05:55:33 PM PDT 24
Peak memory 204952 kb
Host smart-6f8d23cb-06fe-4fdf-a3ce-7516032685d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75882959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv
_dm_jtag_dmi_csr_bit_bash.75882959
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1859495317
Short name T360
Test name
Test status
Simulation time 2308923103 ps
CPU time 7.54 seconds
Started Jul 13 05:55:05 PM PDT 24
Finished Jul 13 05:55:14 PM PDT 24
Peak memory 204920 kb
Host smart-819b77cc-0d97-4ab8-b68b-cb21e6935fe5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859495317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
859495317
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3108584981
Short name T442
Test name
Test status
Simulation time 301205676 ps
CPU time 1.26 seconds
Started Jul 13 05:55:04 PM PDT 24
Finished Jul 13 05:55:06 PM PDT 24
Peak memory 204564 kb
Host smart-4e2a1b5c-e87d-4d91-9a8e-a0fe799a03ad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108584981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3108584981
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1388713372
Short name T309
Test name
Test status
Simulation time 21735893492 ps
CPU time 62.24 seconds
Started Jul 13 05:55:06 PM PDT 24
Finished Jul 13 05:56:09 PM PDT 24
Peak memory 204856 kb
Host smart-8f83d630-876c-4ce7-b2e4-21d0b238283f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388713372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1388713372
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3779749997
Short name T350
Test name
Test status
Simulation time 486432103 ps
CPU time 1.58 seconds
Started Jul 13 05:54:56 PM PDT 24
Finished Jul 13 05:54:58 PM PDT 24
Peak memory 204656 kb
Host smart-117eaff5-c998-42cf-aa0c-6ac0aa99a02c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779749997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3779749997
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1832258902
Short name T315
Test name
Test status
Simulation time 200794501 ps
CPU time 0.78 seconds
Started Jul 13 05:55:05 PM PDT 24
Finished Jul 13 05:55:07 PM PDT 24
Peak memory 204656 kb
Host smart-f99d6f58-b4fc-4b32-88ea-21e1abb1a871
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832258902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
832258902
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.4184171976
Short name T378
Test name
Test status
Simulation time 38865625 ps
CPU time 0.72 seconds
Started Jul 13 05:55:13 PM PDT 24
Finished Jul 13 05:55:14 PM PDT 24
Peak memory 204632 kb
Host smart-76e09577-c029-4a62-b88f-0d768f8abcca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184171976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.4184171976
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.2005231691
Short name T387
Test name
Test status
Simulation time 44672780 ps
CPU time 0.72 seconds
Started Jul 13 05:55:06 PM PDT 24
Finished Jul 13 05:55:07 PM PDT 24
Peak memory 204524 kb
Host smart-889b8bb5-7671-4b9b-ad53-a9a8cb625d34
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005231691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.2005231691
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1664984
Short name T367
Test name
Test status
Simulation time 28197907283 ps
CPU time 16.96 seconds
Started Jul 13 05:55:03 PM PDT 24
Finished Jul 13 05:55:21 PM PDT 24
Peak memory 221144 kb
Host smart-da9f9695-5760-4767-9050-5b83e19290d9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664984 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1664984
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.667902508
Short name T338
Test name
Test status
Simulation time 201768703 ps
CPU time 3.67 seconds
Started Jul 13 05:55:03 PM PDT 24
Finished Jul 13 05:55:07 PM PDT 24
Peak memory 212936 kb
Host smart-401397eb-0683-4403-b539-1ad276fff85b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667902508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.667902508
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2284756915
Short name T176
Test name
Test status
Simulation time 1827953940 ps
CPU time 12 seconds
Started Jul 13 05:55:03 PM PDT 24
Finished Jul 13 05:55:16 PM PDT 24
Peak memory 213168 kb
Host smart-d2edeaa8-d0fa-47f7-9487-e06246c4dca8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284756915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2284756915
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.520843809
Short name T95
Test name
Test status
Simulation time 155586960 ps
CPU time 2.74 seconds
Started Jul 13 05:56:08 PM PDT 24
Finished Jul 13 05:56:12 PM PDT 24
Peak memory 218996 kb
Host smart-c8421d9c-6edd-4621-b051-c1cf72397e81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520843809 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.520843809
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1396303049
Short name T382
Test name
Test status
Simulation time 237996505 ps
CPU time 1.57 seconds
Started Jul 13 05:56:08 PM PDT 24
Finished Jul 13 05:56:10 PM PDT 24
Peak memory 213052 kb
Host smart-64ccc815-34de-4ec5-a063-f1ea59d9a1f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396303049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1396303049
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1199974137
Short name T319
Test name
Test status
Simulation time 16932253493 ps
CPU time 22.85 seconds
Started Jul 13 05:56:07 PM PDT 24
Finished Jul 13 05:56:31 PM PDT 24
Peak memory 204924 kb
Host smart-0bfa7386-8832-4120-9012-b4bdf2ce9c26
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199974137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.1199974137
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3770416120
Short name T351
Test name
Test status
Simulation time 6161385912 ps
CPU time 3.37 seconds
Started Jul 13 05:56:07 PM PDT 24
Finished Jul 13 05:56:11 PM PDT 24
Peak memory 204980 kb
Host smart-1fcd50e6-2a85-4c0e-8fd0-1fb5047b3da2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770416120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3770416120
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1478185859
Short name T418
Test name
Test status
Simulation time 477257288 ps
CPU time 2 seconds
Started Jul 13 05:56:07 PM PDT 24
Finished Jul 13 05:56:09 PM PDT 24
Peak memory 204612 kb
Host smart-3e3789f8-8127-4d84-b9e3-3f4db81a2ee0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478185859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1478185859
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.51881163
Short name T334
Test name
Test status
Simulation time 490719776 ps
CPU time 4.02 seconds
Started Jul 13 05:56:09 PM PDT 24
Finished Jul 13 05:56:13 PM PDT 24
Peak memory 204904 kb
Host smart-17f9acb0-30ea-4d5f-9bc0-7c7637d96933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51881163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_c
sr_outstanding.51881163
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3359902831
Short name T340
Test name
Test status
Simulation time 182115618 ps
CPU time 3.03 seconds
Started Jul 13 05:56:07 PM PDT 24
Finished Jul 13 05:56:11 PM PDT 24
Peak memory 213200 kb
Host smart-8bbef8f1-3c30-45f0-9ef4-a468e895d27a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359902831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3359902831
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.550272351
Short name T124
Test name
Test status
Simulation time 8292860301 ps
CPU time 22.58 seconds
Started Jul 13 05:56:09 PM PDT 24
Finished Jul 13 05:56:32 PM PDT 24
Peak memory 221244 kb
Host smart-40c58d85-20e5-44d3-babc-c2594671b46b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550272351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.550272351
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3720780902
Short name T412
Test name
Test status
Simulation time 207901860 ps
CPU time 3.96 seconds
Started Jul 13 05:56:16 PM PDT 24
Finished Jul 13 05:56:20 PM PDT 24
Peak memory 218912 kb
Host smart-03151296-6ae2-45ea-bde1-4ee58cd0b928
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720780902 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3720780902
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4028097964
Short name T337
Test name
Test status
Simulation time 172282929 ps
CPU time 2.72 seconds
Started Jul 13 05:56:15 PM PDT 24
Finished Jul 13 05:56:18 PM PDT 24
Peak memory 213164 kb
Host smart-113a2297-9099-4c38-a6ce-3c5bd121d29e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028097964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4028097964
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1953107525
Short name T381
Test name
Test status
Simulation time 34997033996 ps
CPU time 47.79 seconds
Started Jul 13 05:56:07 PM PDT 24
Finished Jul 13 05:56:56 PM PDT 24
Peak memory 204844 kb
Host smart-9a252ec9-c1fc-414c-af99-9d9a638b7b3b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953107525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1953107525
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2859754023
Short name T373
Test name
Test status
Simulation time 1171879165 ps
CPU time 3.81 seconds
Started Jul 13 05:56:07 PM PDT 24
Finished Jul 13 05:56:12 PM PDT 24
Peak memory 204832 kb
Host smart-36e0b5c9-0d85-4cd8-9794-d1cc63a45141
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859754023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2859754023
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1249545451
Short name T416
Test name
Test status
Simulation time 1011252703 ps
CPU time 1.21 seconds
Started Jul 13 05:56:07 PM PDT 24
Finished Jul 13 05:56:09 PM PDT 24
Peak memory 204608 kb
Host smart-989e4146-e965-41cc-b2ed-d2990f3a6c80
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249545451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1249545451
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2196739243
Short name T427
Test name
Test status
Simulation time 462172746 ps
CPU time 7.78 seconds
Started Jul 13 05:56:15 PM PDT 24
Finished Jul 13 05:56:23 PM PDT 24
Peak memory 204916 kb
Host smart-ea784160-ae8b-4e24-88bd-83d2e7c1ef26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196739243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2196739243
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2792694814
Short name T327
Test name
Test status
Simulation time 296485105 ps
CPU time 6.05 seconds
Started Jul 13 05:56:09 PM PDT 24
Finished Jul 13 05:56:16 PM PDT 24
Peak memory 213112 kb
Host smart-e746ece3-8e7a-40e8-b012-c7f97011385a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792694814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2792694814
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1011187044
Short name T415
Test name
Test status
Simulation time 770616943 ps
CPU time 4.12 seconds
Started Jul 13 05:56:15 PM PDT 24
Finished Jul 13 05:56:19 PM PDT 24
Peak memory 219104 kb
Host smart-eb8ed4fb-9300-4a3d-a874-7dc84c4ea6ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011187044 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1011187044
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3883187601
Short name T349
Test name
Test status
Simulation time 129456602 ps
CPU time 1.63 seconds
Started Jul 13 05:56:16 PM PDT 24
Finished Jul 13 05:56:19 PM PDT 24
Peak memory 213168 kb
Host smart-751d8e10-2517-4bb6-bcec-5c14e3194f8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883187601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3883187601
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2163938229
Short name T320
Test name
Test status
Simulation time 8806215087 ps
CPU time 4.43 seconds
Started Jul 13 05:56:15 PM PDT 24
Finished Jul 13 05:56:20 PM PDT 24
Peak memory 204920 kb
Host smart-816b7186-d33e-4475-996b-5e274043a939
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163938229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2163938229
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3543492093
Short name T366
Test name
Test status
Simulation time 2845512357 ps
CPU time 9.28 seconds
Started Jul 13 05:56:16 PM PDT 24
Finished Jul 13 05:56:26 PM PDT 24
Peak memory 204876 kb
Host smart-043abff6-4a05-4198-bbf5-59fc87225c4a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543492093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3543492093
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3111676430
Short name T77
Test name
Test status
Simulation time 241439619 ps
CPU time 1.11 seconds
Started Jul 13 05:56:17 PM PDT 24
Finished Jul 13 05:56:19 PM PDT 24
Peak memory 204848 kb
Host smart-6b804885-90b1-42b6-b056-cdd39cec0197
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111676430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3111676430
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2339248675
Short name T344
Test name
Test status
Simulation time 985650970 ps
CPU time 4.1 seconds
Started Jul 13 05:56:16 PM PDT 24
Finished Jul 13 05:56:21 PM PDT 24
Peak memory 204936 kb
Host smart-cdac6601-f54f-4939-a49e-70a4deaa02ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339248675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2339248675
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2288606066
Short name T321
Test name
Test status
Simulation time 268229684 ps
CPU time 6.23 seconds
Started Jul 13 05:56:16 PM PDT 24
Finished Jul 13 05:56:22 PM PDT 24
Peak memory 213112 kb
Host smart-f2f84a22-8549-4d78-b507-afb12ed7f1f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288606066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2288606066
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.4268609060
Short name T122
Test name
Test status
Simulation time 6143345536 ps
CPU time 18.91 seconds
Started Jul 13 05:56:16 PM PDT 24
Finished Jul 13 05:56:36 PM PDT 24
Peak memory 213244 kb
Host smart-fa371aec-745e-4608-bb5b-57e7c52d9f7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268609060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.4
268609060
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.196565145
Short name T368
Test name
Test status
Simulation time 1303468708 ps
CPU time 2.88 seconds
Started Jul 13 05:56:22 PM PDT 24
Finished Jul 13 05:56:25 PM PDT 24
Peak memory 221524 kb
Host smart-cd28e72a-950f-47a9-ad0f-124b36fdc181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196565145 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.196565145
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1585678702
Short name T107
Test name
Test status
Simulation time 330815281 ps
CPU time 2.23 seconds
Started Jul 13 05:56:16 PM PDT 24
Finished Jul 13 05:56:19 PM PDT 24
Peak memory 213116 kb
Host smart-5dc28fec-bb28-4007-b36b-e67e3af3a85d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585678702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1585678702
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1834843802
Short name T423
Test name
Test status
Simulation time 5315511131 ps
CPU time 2.71 seconds
Started Jul 13 05:56:15 PM PDT 24
Finished Jul 13 05:56:18 PM PDT 24
Peak memory 204924 kb
Host smart-dfe23729-6f0b-46cb-a505-ac45650a1335
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834843802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.1834843802
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.490674596
Short name T317
Test name
Test status
Simulation time 845976246 ps
CPU time 1.88 seconds
Started Jul 13 05:56:16 PM PDT 24
Finished Jul 13 05:56:18 PM PDT 24
Peak memory 204728 kb
Host smart-1552f585-68f4-4162-967c-c045714486e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490674596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.490674596
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.136333610
Short name T116
Test name
Test status
Simulation time 490670309 ps
CPU time 7.78 seconds
Started Jul 13 05:56:25 PM PDT 24
Finished Jul 13 05:56:34 PM PDT 24
Peak memory 204812 kb
Host smart-cfe6a27f-661f-4181-bd20-7708833c0848
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136333610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.136333610
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.447028111
Short name T376
Test name
Test status
Simulation time 194557340 ps
CPU time 3.34 seconds
Started Jul 13 05:56:16 PM PDT 24
Finished Jul 13 05:56:20 PM PDT 24
Peak memory 213296 kb
Host smart-c0e2e0f9-ecfc-438a-a067-a0a5d4430fdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447028111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.447028111
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.895661898
Short name T397
Test name
Test status
Simulation time 2764081019 ps
CPU time 9.22 seconds
Started Jul 13 05:56:16 PM PDT 24
Finished Jul 13 05:56:26 PM PDT 24
Peak memory 213132 kb
Host smart-1103081c-4dd6-4ba8-bb74-8397f243a071
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895661898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.895661898
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2013711209
Short name T355
Test name
Test status
Simulation time 331588229 ps
CPU time 3.94 seconds
Started Jul 13 05:56:22 PM PDT 24
Finished Jul 13 05:56:27 PM PDT 24
Peak memory 219556 kb
Host smart-c021c898-acd3-4a60-a9a9-503e3a0fb5a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013711209 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2013711209
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2747136777
Short name T419
Test name
Test status
Simulation time 793964724 ps
CPU time 2.23 seconds
Started Jul 13 05:56:25 PM PDT 24
Finished Jul 13 05:56:28 PM PDT 24
Peak memory 213024 kb
Host smart-ff3e5136-f787-4ccd-b119-1ae117997058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747136777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2747136777
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1826664505
Short name T413
Test name
Test status
Simulation time 2466127811 ps
CPU time 2.95 seconds
Started Jul 13 05:56:21 PM PDT 24
Finished Jul 13 05:56:24 PM PDT 24
Peak memory 204888 kb
Host smart-a7245331-70a1-4fd9-b739-7274fc65912d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826664505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.1826664505
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.164652024
Short name T369
Test name
Test status
Simulation time 2226156498 ps
CPU time 2.29 seconds
Started Jul 13 05:56:21 PM PDT 24
Finished Jul 13 05:56:24 PM PDT 24
Peak memory 204832 kb
Host smart-1346542a-a65e-4d2f-8c33-08d0a1aa0611
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164652024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.164652024
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.682217662
Short name T79
Test name
Test status
Simulation time 164250895 ps
CPU time 0.7 seconds
Started Jul 13 05:56:25 PM PDT 24
Finished Jul 13 05:56:26 PM PDT 24
Peak memory 204536 kb
Host smart-4d222d7e-e38a-4ba2-ab16-55fef92c2264
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682217662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.682217662
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.4117114989
Short name T430
Test name
Test status
Simulation time 326947909 ps
CPU time 6.31 seconds
Started Jul 13 05:56:26 PM PDT 24
Finished Jul 13 05:56:33 PM PDT 24
Peak memory 204864 kb
Host smart-fc08279b-bbe2-4ee4-878d-c734c03ea00b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117114989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.4117114989
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3852596991
Short name T361
Test name
Test status
Simulation time 237455259 ps
CPU time 4.81 seconds
Started Jul 13 05:56:23 PM PDT 24
Finished Jul 13 05:56:28 PM PDT 24
Peak memory 213260 kb
Host smart-d3a1434b-34d4-45a2-ad93-60add54e0799
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852596991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3852596991
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.943908353
Short name T178
Test name
Test status
Simulation time 5058181755 ps
CPU time 28.26 seconds
Started Jul 13 05:56:26 PM PDT 24
Finished Jul 13 05:56:54 PM PDT 24
Peak memory 213080 kb
Host smart-ada1c6a7-aa0e-4f23-919f-6571d753b86d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943908353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.943908353
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2267152424
Short name T372
Test name
Test status
Simulation time 653858338 ps
CPU time 2.55 seconds
Started Jul 13 05:56:24 PM PDT 24
Finished Jul 13 05:56:26 PM PDT 24
Peak memory 214964 kb
Host smart-f7ccadf2-a6c6-48ce-8580-5f59024e9aef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267152424 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2267152424
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2492133758
Short name T395
Test name
Test status
Simulation time 187252868 ps
CPU time 2.35 seconds
Started Jul 13 05:56:21 PM PDT 24
Finished Jul 13 05:56:24 PM PDT 24
Peak memory 213168 kb
Host smart-108c6240-9532-4684-9b0e-0066b7787d2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492133758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2492133758
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3102219715
Short name T444
Test name
Test status
Simulation time 18864279725 ps
CPU time 44.81 seconds
Started Jul 13 05:56:21 PM PDT 24
Finished Jul 13 05:57:07 PM PDT 24
Peak memory 204896 kb
Host smart-8dea2938-01a0-4f85-9816-32df1b1b8f9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102219715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.3102219715
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2935223917
Short name T322
Test name
Test status
Simulation time 5406896150 ps
CPU time 14.29 seconds
Started Jul 13 05:56:26 PM PDT 24
Finished Jul 13 05:56:41 PM PDT 24
Peak memory 204868 kb
Host smart-abac536e-e43c-4089-8c5c-b5d3ddf76580
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935223917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2935223917
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2025283180
Short name T380
Test name
Test status
Simulation time 746871101 ps
CPU time 0.96 seconds
Started Jul 13 05:56:21 PM PDT 24
Finished Jul 13 05:56:22 PM PDT 24
Peak memory 204632 kb
Host smart-07cb01b6-5593-4ab9-828f-fe39faf4b1db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025283180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2025283180
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3752181038
Short name T68
Test name
Test status
Simulation time 721720605 ps
CPU time 6.54 seconds
Started Jul 13 05:56:25 PM PDT 24
Finished Jul 13 05:56:32 PM PDT 24
Peak memory 204820 kb
Host smart-cf3141e0-13d5-471f-a4ba-a2f476393801
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752181038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3752181038
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.718350756
Short name T389
Test name
Test status
Simulation time 491684976 ps
CPU time 5.91 seconds
Started Jul 13 05:56:22 PM PDT 24
Finished Jul 13 05:56:28 PM PDT 24
Peak memory 213116 kb
Host smart-171a2048-48ff-43bd-94ec-559b8c795a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718350756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.718350756
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3620517733
Short name T170
Test name
Test status
Simulation time 927738899 ps
CPU time 10.59 seconds
Started Jul 13 05:56:22 PM PDT 24
Finished Jul 13 05:56:33 PM PDT 24
Peak memory 213092 kb
Host smart-da468766-21e7-465e-887b-7532445fafa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620517733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
620517733
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2215916039
Short name T405
Test name
Test status
Simulation time 761012384 ps
CPU time 4.2 seconds
Started Jul 13 05:56:30 PM PDT 24
Finished Jul 13 05:56:35 PM PDT 24
Peak memory 219496 kb
Host smart-e2185cc8-be61-41a4-99a1-54349aecd80e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215916039 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2215916039
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3079165246
Short name T446
Test name
Test status
Simulation time 626244658 ps
CPU time 1.6 seconds
Started Jul 13 05:56:30 PM PDT 24
Finished Jul 13 05:56:32 PM PDT 24
Peak memory 213080 kb
Host smart-e4fb98cf-c69f-4f7c-8c24-cd53548ee073
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079165246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3079165246
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.19511951
Short name T396
Test name
Test status
Simulation time 12588123371 ps
CPU time 34.21 seconds
Started Jul 13 05:56:26 PM PDT 24
Finished Jul 13 05:57:01 PM PDT 24
Peak memory 204784 kb
Host smart-51e8d1d5-cf72-4b72-ae93-1d125eb57b84
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19511951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.r
v_dm_jtag_dmi_csr_bit_bash.19511951
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3327292569
Short name T332
Test name
Test status
Simulation time 1530392633 ps
CPU time 2.02 seconds
Started Jul 13 05:56:29 PM PDT 24
Finished Jul 13 05:56:32 PM PDT 24
Peak memory 204768 kb
Host smart-d8ac3894-19b3-4809-8d13-61e24e6b2130
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327292569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3327292569
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.187369491
Short name T371
Test name
Test status
Simulation time 493837218 ps
CPU time 1.25 seconds
Started Jul 13 05:56:21 PM PDT 24
Finished Jul 13 05:56:22 PM PDT 24
Peak memory 204640 kb
Host smart-ef3651e1-8e37-4020-b5be-996f38c28680
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187369491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.187369491
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3908839959
Short name T438
Test name
Test status
Simulation time 253191674 ps
CPU time 6.96 seconds
Started Jul 13 05:56:30 PM PDT 24
Finished Jul 13 05:56:38 PM PDT 24
Peak memory 204936 kb
Host smart-875ed06d-27cf-476d-93b9-29ceeb82e155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908839959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3908839959
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.541234877
Short name T384
Test name
Test status
Simulation time 458602739 ps
CPU time 5.49 seconds
Started Jul 13 05:56:31 PM PDT 24
Finished Jul 13 05:56:37 PM PDT 24
Peak memory 213176 kb
Host smart-c7ab11fc-1404-46d3-9902-45243b7f3e98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541234877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.541234877
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.713841865
Short name T173
Test name
Test status
Simulation time 3092153716 ps
CPU time 24.54 seconds
Started Jul 13 05:56:30 PM PDT 24
Finished Jul 13 05:56:55 PM PDT 24
Peak memory 213236 kb
Host smart-6b3f38a2-a1be-4f0b-9f18-b6e9b1e4fec2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713841865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.713841865
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2481451899
Short name T336
Test name
Test status
Simulation time 557820534 ps
CPU time 4.08 seconds
Started Jul 13 05:56:30 PM PDT 24
Finished Jul 13 05:56:34 PM PDT 24
Peak memory 219012 kb
Host smart-4b109bd9-98aa-4c62-9263-39fe4068d63e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481451899 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2481451899
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.75491188
Short name T363
Test name
Test status
Simulation time 129550686 ps
CPU time 1.53 seconds
Started Jul 13 05:56:31 PM PDT 24
Finished Jul 13 05:56:33 PM PDT 24
Peak memory 213176 kb
Host smart-bce5acf4-0ebe-4364-8daf-6ceb0137a07d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75491188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.75491188
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.201029004
Short name T429
Test name
Test status
Simulation time 40689580015 ps
CPU time 32.01 seconds
Started Jul 13 05:56:30 PM PDT 24
Finished Jul 13 05:57:02 PM PDT 24
Peak memory 204812 kb
Host smart-95e2adf9-8cb6-431f-91d2-0e7add78001a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201029004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.201029004
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.2507470093
Short name T307
Test name
Test status
Simulation time 2277243381 ps
CPU time 5.35 seconds
Started Jul 13 05:56:30 PM PDT 24
Finished Jul 13 05:56:35 PM PDT 24
Peak memory 204900 kb
Host smart-24cb2f57-64b4-487a-8640-b2fa5a50e127
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507470093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
2507470093
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3464430713
Short name T356
Test name
Test status
Simulation time 904049630 ps
CPU time 3.06 seconds
Started Jul 13 05:56:30 PM PDT 24
Finished Jul 13 05:56:34 PM PDT 24
Peak memory 204608 kb
Host smart-3d6e71c5-72c2-400b-8b1d-6421342f4af8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464430713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3464430713
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.553097055
Short name T117
Test name
Test status
Simulation time 270946890 ps
CPU time 4.28 seconds
Started Jul 13 05:56:31 PM PDT 24
Finished Jul 13 05:56:35 PM PDT 24
Peak memory 204924 kb
Host smart-7346b727-fd79-4642-a030-f6afcee49304
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553097055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.553097055
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2364078678
Short name T441
Test name
Test status
Simulation time 193921322 ps
CPU time 2.76 seconds
Started Jul 13 05:56:29 PM PDT 24
Finished Jul 13 05:56:32 PM PDT 24
Peak memory 213272 kb
Host smart-b9525d0f-4f15-4e93-bf7a-8d192cf0dfae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364078678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2364078678
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3498608931
Short name T83
Test name
Test status
Simulation time 196717246 ps
CPU time 2.36 seconds
Started Jul 13 05:56:39 PM PDT 24
Finished Jul 13 05:56:42 PM PDT 24
Peak memory 221240 kb
Host smart-f0b7a34d-8b2d-413b-b8e6-125051ae19b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498608931 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3498608931
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1147171917
Short name T111
Test name
Test status
Simulation time 264207018 ps
CPU time 1.66 seconds
Started Jul 13 05:56:38 PM PDT 24
Finished Jul 13 05:56:40 PM PDT 24
Peak memory 213172 kb
Host smart-6889df59-4c88-438e-8ac4-7721754a7320
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147171917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1147171917
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2132681724
Short name T300
Test name
Test status
Simulation time 181215814 ps
CPU time 0.77 seconds
Started Jul 13 05:56:37 PM PDT 24
Finished Jul 13 05:56:38 PM PDT 24
Peak memory 204648 kb
Host smart-aafef802-a2cb-4180-ad6d-980d631537b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132681724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2132681724
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3888882960
Short name T331
Test name
Test status
Simulation time 3641324691 ps
CPU time 3.47 seconds
Started Jul 13 05:56:30 PM PDT 24
Finished Jul 13 05:56:34 PM PDT 24
Peak memory 204924 kb
Host smart-46709b86-c886-49e5-9ed1-696a3c504e3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888882960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3888882960
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3881141688
Short name T357
Test name
Test status
Simulation time 256660165 ps
CPU time 0.85 seconds
Started Jul 13 05:56:29 PM PDT 24
Finished Jul 13 05:56:30 PM PDT 24
Peak memory 204608 kb
Host smart-f31f87ff-18d7-4382-9be2-81703adff228
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881141688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3881141688
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3374720062
Short name T100
Test name
Test status
Simulation time 694428115 ps
CPU time 3.78 seconds
Started Jul 13 05:56:37 PM PDT 24
Finished Jul 13 05:56:41 PM PDT 24
Peak memory 204900 kb
Host smart-0bc8655e-946f-4abe-815d-408657443c81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374720062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3374720062
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1915837405
Short name T358
Test name
Test status
Simulation time 205941964 ps
CPU time 4.78 seconds
Started Jul 13 05:56:36 PM PDT 24
Finished Jul 13 05:56:41 PM PDT 24
Peak memory 213148 kb
Host smart-75f102e4-e28c-4162-8fc7-fa25b46755d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915837405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1915837405
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3773382052
Short name T172
Test name
Test status
Simulation time 2874230044 ps
CPU time 12.49 seconds
Started Jul 13 05:56:38 PM PDT 24
Finished Jul 13 05:56:51 PM PDT 24
Peak memory 213100 kb
Host smart-7b560ae3-7f4c-4fa4-b879-a852f81b9f06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773382052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
773382052
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3820304463
Short name T370
Test name
Test status
Simulation time 3080861307 ps
CPU time 3.74 seconds
Started Jul 13 05:56:38 PM PDT 24
Finished Jul 13 05:56:42 PM PDT 24
Peak memory 218332 kb
Host smart-d5facd3d-194d-4ebb-ab37-d3eb01c6d325
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820304463 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3820304463
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3488312099
Short name T353
Test name
Test status
Simulation time 120280706 ps
CPU time 2.56 seconds
Started Jul 13 05:56:38 PM PDT 24
Finished Jul 13 05:56:41 PM PDT 24
Peak memory 213124 kb
Host smart-267fa4cc-44fa-40e4-8bd3-b15f232e944a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488312099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3488312099
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.18832029
Short name T342
Test name
Test status
Simulation time 10552132033 ps
CPU time 7.04 seconds
Started Jul 13 05:56:39 PM PDT 24
Finished Jul 13 05:56:46 PM PDT 24
Peak memory 204952 kb
Host smart-17db4c18-eb1f-47a6-b9e5-8a42c8750173
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18832029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.r
v_dm_jtag_dmi_csr_bit_bash.18832029
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.187009552
Short name T310
Test name
Test status
Simulation time 2506347717 ps
CPU time 8.13 seconds
Started Jul 13 05:56:39 PM PDT 24
Finished Jul 13 05:56:47 PM PDT 24
Peak memory 204896 kb
Host smart-a7a3442d-6abb-43e5-b112-aa2da22143d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187009552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.187009552
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.566527514
Short name T352
Test name
Test status
Simulation time 474605401 ps
CPU time 1.92 seconds
Started Jul 13 05:56:38 PM PDT 24
Finished Jul 13 05:56:41 PM PDT 24
Peak memory 204504 kb
Host smart-1da7c732-0b7c-4cbe-ac6e-b6d6c828a28e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566527514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.566527514
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1075052605
Short name T341
Test name
Test status
Simulation time 95108026 ps
CPU time 3.67 seconds
Started Jul 13 05:56:37 PM PDT 24
Finished Jul 13 05:56:42 PM PDT 24
Peak memory 204896 kb
Host smart-c2eb40e0-0dd8-4a79-9c65-4879586025ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075052605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1075052605
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2480832186
Short name T428
Test name
Test status
Simulation time 1547242175 ps
CPU time 6.39 seconds
Started Jul 13 05:56:37 PM PDT 24
Finished Jul 13 05:56:44 PM PDT 24
Peak memory 213204 kb
Host smart-affc4347-3c61-4bf8-b83b-a454e7af7537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480832186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2480832186
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.1168307017
Short name T180
Test name
Test status
Simulation time 1107129226 ps
CPU time 17.83 seconds
Started Jul 13 05:56:36 PM PDT 24
Finished Jul 13 05:56:54 PM PDT 24
Peak memory 213084 kb
Host smart-f5b9aa86-de94-4dd4-aca3-fe8a943f8618
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168307017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.1
168307017
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2224955430
Short name T88
Test name
Test status
Simulation time 3698849883 ps
CPU time 28.34 seconds
Started Jul 13 05:55:16 PM PDT 24
Finished Jul 13 05:55:44 PM PDT 24
Peak memory 213452 kb
Host smart-561bca70-eda4-4869-85a4-f030a2a9fddb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224955430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2224955430
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.877885648
Short name T94
Test name
Test status
Simulation time 5865425742 ps
CPU time 58.75 seconds
Started Jul 13 05:55:29 PM PDT 24
Finished Jul 13 05:56:28 PM PDT 24
Peak memory 205056 kb
Host smart-c09b4c21-ba5e-4f9d-89d8-9167011be49e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877885648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.877885648
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.372025689
Short name T406
Test name
Test status
Simulation time 148764437 ps
CPU time 1.82 seconds
Started Jul 13 05:55:29 PM PDT 24
Finished Jul 13 05:55:31 PM PDT 24
Peak memory 213172 kb
Host smart-dccdfa95-a45b-4424-8899-7be752151dd9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372025689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.372025689
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2814994376
Short name T436
Test name
Test status
Simulation time 1294577398 ps
CPU time 3.91 seconds
Started Jul 13 05:55:36 PM PDT 24
Finished Jul 13 05:55:40 PM PDT 24
Peak memory 217040 kb
Host smart-24e54c5a-db9c-4ac6-8524-ffaef075878d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814994376 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2814994376
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1463971162
Short name T329
Test name
Test status
Simulation time 432046578 ps
CPU time 1.63 seconds
Started Jul 13 05:55:29 PM PDT 24
Finished Jul 13 05:55:32 PM PDT 24
Peak memory 212996 kb
Host smart-131f2956-4d73-49fc-842c-252bfab54fc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463971162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1463971162
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2720412078
Short name T426
Test name
Test status
Simulation time 103021141706 ps
CPU time 115.44 seconds
Started Jul 13 05:55:20 PM PDT 24
Finished Jul 13 05:57:15 PM PDT 24
Peak memory 204900 kb
Host smart-69724e40-4c2e-438e-8391-43cba9a0d426
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720412078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2720412078
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.825238858
Short name T314
Test name
Test status
Simulation time 2477906184 ps
CPU time 4.16 seconds
Started Jul 13 05:55:19 PM PDT 24
Finished Jul 13 05:55:23 PM PDT 24
Peak memory 204892 kb
Host smart-336f3a51-4df4-4575-9cad-a0e8e478b4dc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825238858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r
v_dm_jtag_dmi_csr_bit_bash.825238858
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1684676033
Short name T96
Test name
Test status
Simulation time 4870364695 ps
CPU time 13.64 seconds
Started Jul 13 05:55:18 PM PDT 24
Finished Jul 13 05:55:32 PM PDT 24
Peak memory 204876 kb
Host smart-fa2c78d3-069f-4f9c-824c-932c33f578d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684676033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1684676033
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2472571216
Short name T297
Test name
Test status
Simulation time 7632525931 ps
CPU time 5.31 seconds
Started Jul 13 05:55:19 PM PDT 24
Finished Jul 13 05:55:24 PM PDT 24
Peak memory 204936 kb
Host smart-d85316e5-fb60-408a-827a-5de88f3969a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472571216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
472571216
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.127394460
Short name T347
Test name
Test status
Simulation time 660178148 ps
CPU time 1.17 seconds
Started Jul 13 05:55:19 PM PDT 24
Finished Jul 13 05:55:21 PM PDT 24
Peak memory 204636 kb
Host smart-a9ea708d-21ea-423d-aeb4-4cfb20271873
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127394460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.127394460
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2037635044
Short name T316
Test name
Test status
Simulation time 3355092292 ps
CPU time 5.62 seconds
Started Jul 13 05:55:20 PM PDT 24
Finished Jul 13 05:55:26 PM PDT 24
Peak memory 204924 kb
Host smart-60e83997-6477-4c00-948b-e27cac697ca8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037635044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2037635044
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1687554331
Short name T365
Test name
Test status
Simulation time 1066939555 ps
CPU time 0.93 seconds
Started Jul 13 05:55:11 PM PDT 24
Finished Jul 13 05:55:13 PM PDT 24
Peak memory 204520 kb
Host smart-031d746a-c072-4bdc-ba42-862b01108e74
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687554331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1687554331
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.714429074
Short name T417
Test name
Test status
Simulation time 129515873 ps
CPU time 0.95 seconds
Started Jul 13 05:55:10 PM PDT 24
Finished Jul 13 05:55:12 PM PDT 24
Peak memory 204540 kb
Host smart-90222eeb-c7ca-42fc-9d7b-0712d00b9c89
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714429074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.714429074
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2778136548
Short name T399
Test name
Test status
Simulation time 28288008 ps
CPU time 0.7 seconds
Started Jul 13 05:55:28 PM PDT 24
Finished Jul 13 05:55:29 PM PDT 24
Peak memory 204604 kb
Host smart-c8de201f-7452-4911-a34c-724e1cbabcbf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778136548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2778136548
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1582570180
Short name T359
Test name
Test status
Simulation time 93680592 ps
CPU time 0.85 seconds
Started Jul 13 05:55:31 PM PDT 24
Finished Jul 13 05:55:32 PM PDT 24
Peak memory 204852 kb
Host smart-0212a761-bdb5-403c-a2e6-d1b4c6805f03
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582570180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1582570180
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1019597666
Short name T437
Test name
Test status
Simulation time 548968237 ps
CPU time 4.1 seconds
Started Jul 13 05:55:29 PM PDT 24
Finished Jul 13 05:55:34 PM PDT 24
Peak memory 204888 kb
Host smart-7115caf6-d7fa-419f-b28a-249d8d9fe59a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019597666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1019597666
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1350313401
Short name T67
Test name
Test status
Simulation time 99353615 ps
CPU time 4.77 seconds
Started Jul 13 05:55:29 PM PDT 24
Finished Jul 13 05:55:35 PM PDT 24
Peak memory 213188 kb
Host smart-59a689de-75e1-4c5a-8853-1c679242b8e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350313401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1350313401
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2029755753
Short name T171
Test name
Test status
Simulation time 1208898630 ps
CPU time 8.48 seconds
Started Jul 13 05:55:28 PM PDT 24
Finished Jul 13 05:55:37 PM PDT 24
Peak memory 213112 kb
Host smart-9aa9848a-04ed-4d7c-8443-a5cff723105a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029755753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2029755753
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.109581721
Short name T89
Test name
Test status
Simulation time 14622632266 ps
CPU time 79.55 seconds
Started Jul 13 05:55:36 PM PDT 24
Finished Jul 13 05:56:56 PM PDT 24
Peak memory 204952 kb
Host smart-10b22b2c-4627-4806-8ee7-ec97ef81e808
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109581721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.109581721
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1138112095
Short name T375
Test name
Test status
Simulation time 60969301122 ps
CPU time 75.88 seconds
Started Jul 13 05:55:39 PM PDT 24
Finished Jul 13 05:56:56 PM PDT 24
Peak memory 213096 kb
Host smart-021ab296-954e-4439-9458-741c03ec0d75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138112095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1138112095
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2994586735
Short name T110
Test name
Test status
Simulation time 464325400 ps
CPU time 2.88 seconds
Started Jul 13 05:55:38 PM PDT 24
Finished Jul 13 05:55:41 PM PDT 24
Peak memory 214196 kb
Host smart-6bc47fb4-e86a-44a2-9972-0f1061198571
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994586735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2994586735
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3380618119
Short name T82
Test name
Test status
Simulation time 4165250305 ps
CPU time 5.1 seconds
Started Jul 13 05:55:39 PM PDT 24
Finished Jul 13 05:55:44 PM PDT 24
Peak memory 219920 kb
Host smart-c7a512b0-f92a-40d9-ac3c-d1e8c81b7f03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380618119 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3380618119
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2872289142
Short name T345
Test name
Test status
Simulation time 69282581 ps
CPU time 1.58 seconds
Started Jul 13 05:55:36 PM PDT 24
Finished Jul 13 05:55:39 PM PDT 24
Peak memory 213024 kb
Host smart-daef920a-4eab-4965-aa69-8ea5c92d5a98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872289142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2872289142
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3590140634
Short name T330
Test name
Test status
Simulation time 95960947234 ps
CPU time 66.63 seconds
Started Jul 13 05:55:39 PM PDT 24
Finished Jul 13 05:56:46 PM PDT 24
Peak memory 204968 kb
Host smart-6c7bbfb9-d2bb-4aac-a0b3-627ca57163a2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590140634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3590140634
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.649702043
Short name T379
Test name
Test status
Simulation time 5211717951 ps
CPU time 2.86 seconds
Started Jul 13 05:55:37 PM PDT 24
Finished Jul 13 05:55:40 PM PDT 24
Peak memory 204920 kb
Host smart-3309f91e-d414-4703-834e-1bf65ca8f3d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649702043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
v_dm_jtag_dmi_csr_bit_bash.649702043
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4072060159
Short name T98
Test name
Test status
Simulation time 3238740818 ps
CPU time 9.59 seconds
Started Jul 13 05:55:36 PM PDT 24
Finished Jul 13 05:55:46 PM PDT 24
Peak memory 204976 kb
Host smart-aeb87d65-d465-41ce-96a7-a2f522c604fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072060159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.4072060159
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4004826013
Short name T318
Test name
Test status
Simulation time 14518149556 ps
CPU time 13.01 seconds
Started Jul 13 05:55:37 PM PDT 24
Finished Jul 13 05:55:50 PM PDT 24
Peak memory 204984 kb
Host smart-45ba3b8d-7fa0-47cc-acff-5c4f889be987
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004826013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.4
004826013
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4215131928
Short name T302
Test name
Test status
Simulation time 169149359 ps
CPU time 1.12 seconds
Started Jul 13 05:55:37 PM PDT 24
Finished Jul 13 05:55:39 PM PDT 24
Peak memory 204640 kb
Host smart-65f51450-9065-4f1c-b5f9-79409007e8e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215131928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.4215131928
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1313763015
Short name T433
Test name
Test status
Simulation time 16185143190 ps
CPU time 22.49 seconds
Started Jul 13 05:55:39 PM PDT 24
Finished Jul 13 05:56:02 PM PDT 24
Peak memory 204824 kb
Host smart-7d17f168-0d9a-4b6c-9c4d-c90d57c15476
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313763015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1313763015
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4153845216
Short name T402
Test name
Test status
Simulation time 930229527 ps
CPU time 1.89 seconds
Started Jul 13 05:55:35 PM PDT 24
Finished Jul 13 05:55:38 PM PDT 24
Peak memory 204644 kb
Host smart-f94cd12e-e8bc-4cc1-b81d-d2b5bd8818e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153845216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.4153845216
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2332001252
Short name T304
Test name
Test status
Simulation time 175359724 ps
CPU time 0.89 seconds
Started Jul 13 05:55:36 PM PDT 24
Finished Jul 13 05:55:37 PM PDT 24
Peak memory 204616 kb
Host smart-c34aac75-13fa-4d7c-9bac-501fe113367e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332001252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
332001252
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2778138493
Short name T394
Test name
Test status
Simulation time 43723763 ps
CPU time 0.74 seconds
Started Jul 13 05:55:36 PM PDT 24
Finished Jul 13 05:55:38 PM PDT 24
Peak memory 204520 kb
Host smart-4c696767-c2da-488c-a28c-caed8c0b87e6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778138493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2778138493
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.343920437
Short name T311
Test name
Test status
Simulation time 135612745 ps
CPU time 0.84 seconds
Started Jul 13 05:55:38 PM PDT 24
Finished Jul 13 05:55:39 PM PDT 24
Peak memory 204628 kb
Host smart-e6eddfb5-2da0-464a-811e-8f4a1b3ace39
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343920437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.343920437
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2374250818
Short name T93
Test name
Test status
Simulation time 1623883448 ps
CPU time 7.37 seconds
Started Jul 13 05:55:39 PM PDT 24
Finished Jul 13 05:55:47 PM PDT 24
Peak memory 204912 kb
Host smart-b72bf032-ab8e-4bf3-a771-12889f5037bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374250818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2374250818
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3929975776
Short name T374
Test name
Test status
Simulation time 238475689 ps
CPU time 4.89 seconds
Started Jul 13 05:55:39 PM PDT 24
Finished Jul 13 05:55:44 PM PDT 24
Peak memory 213092 kb
Host smart-ba39f91a-b50e-4a77-b278-7ecb70616fa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929975776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3929975776
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3316166904
Short name T175
Test name
Test status
Simulation time 2633687274 ps
CPU time 19.86 seconds
Started Jul 13 05:55:36 PM PDT 24
Finished Jul 13 05:55:57 PM PDT 24
Peak memory 213144 kb
Host smart-0d419284-f38a-44ce-80fc-3f64954d91e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316166904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3316166904
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2315048797
Short name T109
Test name
Test status
Simulation time 4499671975 ps
CPU time 32.68 seconds
Started Jul 13 05:55:38 PM PDT 24
Finished Jul 13 05:56:11 PM PDT 24
Peak memory 205032 kb
Host smart-a0ca314a-85c0-4cde-9c3b-e03d2b877637
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315048797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2315048797
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2358460858
Short name T123
Test name
Test status
Simulation time 3331571202 ps
CPU time 37.34 seconds
Started Jul 13 05:55:46 PM PDT 24
Finished Jul 13 05:56:24 PM PDT 24
Peak memory 204920 kb
Host smart-7934c6ad-3f52-49d9-8f31-f4869233fca9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358460858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2358460858
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.745626413
Short name T445
Test name
Test status
Simulation time 4603943329 ps
CPU time 3.33 seconds
Started Jul 13 05:55:51 PM PDT 24
Finished Jul 13 05:55:55 PM PDT 24
Peak memory 219248 kb
Host smart-9dc06014-a6c2-4cb5-a9fc-12e7a91f3c41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745626413 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.745626413
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3766138635
Short name T91
Test name
Test status
Simulation time 77099979 ps
CPU time 1.59 seconds
Started Jul 13 05:55:45 PM PDT 24
Finished Jul 13 05:55:47 PM PDT 24
Peak memory 213048 kb
Host smart-a17ea1ad-3c17-4981-b8f2-923f3758f28e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766138635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3766138635
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2502333553
Short name T439
Test name
Test status
Simulation time 15593182299 ps
CPU time 7.08 seconds
Started Jul 13 05:55:47 PM PDT 24
Finished Jul 13 05:55:55 PM PDT 24
Peak memory 204648 kb
Host smart-14782f9a-3727-48a3-b0e3-3f65aaf04d69
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502333553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2502333553
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1758754495
Short name T432
Test name
Test status
Simulation time 41506903058 ps
CPU time 71.32 seconds
Started Jul 13 05:55:44 PM PDT 24
Finished Jul 13 05:56:56 PM PDT 24
Peak memory 204796 kb
Host smart-93a3ed27-ab6f-49bc-8b7a-7328ce49574e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758754495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.1758754495
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.134842174
Short name T99
Test name
Test status
Simulation time 5260583726 ps
CPU time 7.27 seconds
Started Jul 13 05:55:45 PM PDT 24
Finished Jul 13 05:55:53 PM PDT 24
Peak memory 204960 kb
Host smart-ac02c437-967c-4220-a764-bdf1312ebd9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134842174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.134842174
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3077503090
Short name T398
Test name
Test status
Simulation time 1607078061 ps
CPU time 5.23 seconds
Started Jul 13 05:55:49 PM PDT 24
Finished Jul 13 05:55:54 PM PDT 24
Peak memory 204836 kb
Host smart-4795c9a8-14ac-499a-b336-5dab9f96e7ac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077503090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
077503090
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4285980221
Short name T312
Test name
Test status
Simulation time 209147735 ps
CPU time 1.16 seconds
Started Jul 13 05:55:45 PM PDT 24
Finished Jul 13 05:55:47 PM PDT 24
Peak memory 204588 kb
Host smart-26feaef2-784a-4dd9-a1ff-0caf8cd45037
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285980221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.4285980221
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3709926327
Short name T403
Test name
Test status
Simulation time 4999470373 ps
CPU time 5.4 seconds
Started Jul 13 05:55:46 PM PDT 24
Finished Jul 13 05:55:52 PM PDT 24
Peak memory 204976 kb
Host smart-13748256-cb35-496f-8c2e-dfd118092971
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709926327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3709926327
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.294959703
Short name T407
Test name
Test status
Simulation time 390351826 ps
CPU time 1.17 seconds
Started Jul 13 05:55:47 PM PDT 24
Finished Jul 13 05:55:49 PM PDT 24
Peak memory 204376 kb
Host smart-01ab6fa0-0fe6-46e5-b262-d05735c3284a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294959703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.294959703
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2998728602
Short name T335
Test name
Test status
Simulation time 501535529 ps
CPU time 1.65 seconds
Started Jul 13 05:55:42 PM PDT 24
Finished Jul 13 05:55:44 PM PDT 24
Peak memory 204564 kb
Host smart-d4049f08-3a97-4afe-814e-222fcf4f6545
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998728602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
998728602
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2168011399
Short name T313
Test name
Test status
Simulation time 103440048 ps
CPU time 0.72 seconds
Started Jul 13 05:55:49 PM PDT 24
Finished Jul 13 05:55:50 PM PDT 24
Peak memory 204640 kb
Host smart-10b5a139-34a7-4280-857f-1ba84f7abe99
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168011399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2168011399
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3641697818
Short name T393
Test name
Test status
Simulation time 71288925 ps
CPU time 0.82 seconds
Started Jul 13 05:55:49 PM PDT 24
Finished Jul 13 05:55:50 PM PDT 24
Peak memory 204636 kb
Host smart-ed8d7fa9-ac36-4f19-b2a6-eb33da7f8b51
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641697818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3641697818
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1849469904
Short name T105
Test name
Test status
Simulation time 317370762 ps
CPU time 4.38 seconds
Started Jul 13 05:55:51 PM PDT 24
Finished Jul 13 05:55:55 PM PDT 24
Peak memory 204848 kb
Host smart-692d7d92-ae6c-4609-866b-1daab6e67316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849469904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1849469904
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.73406973
Short name T392
Test name
Test status
Simulation time 28465100014 ps
CPU time 38.23 seconds
Started Jul 13 05:55:46 PM PDT 24
Finished Jul 13 05:56:25 PM PDT 24
Peak memory 221032 kb
Host smart-fcbfe5e9-9a1f-4dbf-bfe6-0a05f51a3d81
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73406973 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.73406973
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2439849982
Short name T354
Test name
Test status
Simulation time 184790634 ps
CPU time 5.42 seconds
Started Jul 13 05:55:45 PM PDT 24
Finished Jul 13 05:55:50 PM PDT 24
Peak memory 216452 kb
Host smart-d7929d56-6dfa-4e1d-8101-25f4a87a217b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439849982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2439849982
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1269077850
Short name T86
Test name
Test status
Simulation time 4869993347 ps
CPU time 11.04 seconds
Started Jul 13 05:55:45 PM PDT 24
Finished Jul 13 05:55:56 PM PDT 24
Peak memory 213236 kb
Host smart-ffb49ef1-3f20-405f-8676-9840bcc32094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269077850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1269077850
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.1834317000
Short name T169
Test name
Test status
Simulation time 4005809538 ps
CPU time 8.12 seconds
Started Jul 13 05:55:52 PM PDT 24
Finished Jul 13 05:56:01 PM PDT 24
Peak memory 218208 kb
Host smart-8deae36a-576e-4d9b-80ab-31131147521c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834317000 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.1834317000
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2139499441
Short name T104
Test name
Test status
Simulation time 465241956 ps
CPU time 2.3 seconds
Started Jul 13 05:55:54 PM PDT 24
Finished Jul 13 05:55:57 PM PDT 24
Peak memory 213164 kb
Host smart-298aa03d-2f7a-49e6-a269-61a1273d9c47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139499441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2139499441
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.277169518
Short name T303
Test name
Test status
Simulation time 4224994069 ps
CPU time 5.48 seconds
Started Jul 13 05:55:53 PM PDT 24
Finished Jul 13 05:56:00 PM PDT 24
Peak memory 204900 kb
Host smart-af14ed13-dd4a-4e53-b35f-aee9d9cccc2d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277169518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r
v_dm_jtag_dmi_csr_bit_bash.277169518
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2074470764
Short name T346
Test name
Test status
Simulation time 1931842414 ps
CPU time 6.23 seconds
Started Jul 13 05:55:54 PM PDT 24
Finished Jul 13 05:56:01 PM PDT 24
Peak memory 204856 kb
Host smart-cc38bd7f-dfa3-4e28-bb48-384615c861e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074470764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
074470764
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1151485297
Short name T383
Test name
Test status
Simulation time 228174370 ps
CPU time 1.17 seconds
Started Jul 13 05:55:53 PM PDT 24
Finished Jul 13 05:55:54 PM PDT 24
Peak memory 204540 kb
Host smart-1153357f-abfd-401b-b57e-433e8de00432
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151485297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
151485297
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.118970782
Short name T401
Test name
Test status
Simulation time 349151536 ps
CPU time 6.55 seconds
Started Jul 13 05:55:53 PM PDT 24
Finished Jul 13 05:56:00 PM PDT 24
Peak memory 204904 kb
Host smart-b1e75a7f-1ac1-4c40-b075-690f29599e91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118970782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.118970782
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.1000574799
Short name T55
Test name
Test status
Simulation time 22253494575 ps
CPU time 14.22 seconds
Started Jul 13 05:55:52 PM PDT 24
Finished Jul 13 05:56:07 PM PDT 24
Peak memory 220744 kb
Host smart-3a4f1316-dcff-4136-971c-d1022026023e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000574799 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.1000574799
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.196286351
Short name T425
Test name
Test status
Simulation time 382177848 ps
CPU time 4.61 seconds
Started Jul 13 05:55:53 PM PDT 24
Finished Jul 13 05:55:57 PM PDT 24
Peak memory 213252 kb
Host smart-0ed7e984-a968-4002-b7c1-9d273fd5691e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196286351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.196286351
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3685103039
Short name T409
Test name
Test status
Simulation time 2152564332 ps
CPU time 8.47 seconds
Started Jul 13 05:55:54 PM PDT 24
Finished Jul 13 05:56:03 PM PDT 24
Peak memory 213172 kb
Host smart-49f5411c-a83d-4aab-aebd-36e1b3024075
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685103039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3685103039
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2612308345
Short name T385
Test name
Test status
Simulation time 83691372 ps
CPU time 2.64 seconds
Started Jul 13 05:56:04 PM PDT 24
Finished Jul 13 05:56:07 PM PDT 24
Peak memory 213396 kb
Host smart-401c57fd-fee1-4477-b269-88547fa2618e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612308345 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2612308345
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2874658638
Short name T69
Test name
Test status
Simulation time 537884384 ps
CPU time 1.66 seconds
Started Jul 13 05:56:03 PM PDT 24
Finished Jul 13 05:56:05 PM PDT 24
Peak memory 212996 kb
Host smart-4d0f5d8d-368a-4645-b10b-b809c380b30d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874658638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2874658638
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4094173918
Short name T422
Test name
Test status
Simulation time 1833442926 ps
CPU time 2.36 seconds
Started Jul 13 05:55:53 PM PDT 24
Finished Jul 13 05:55:56 PM PDT 24
Peak memory 204828 kb
Host smart-5fe6c334-2947-41b1-b4c3-0cbe2bfd5164
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094173918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.4094173918
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2277785784
Short name T296
Test name
Test status
Simulation time 12297292188 ps
CPU time 21.55 seconds
Started Jul 13 05:55:55 PM PDT 24
Finished Jul 13 05:56:17 PM PDT 24
Peak memory 204960 kb
Host smart-0e15e65b-fa30-4d7c-b451-016e327d0fd4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277785784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
277785784
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2515117894
Short name T410
Test name
Test status
Simulation time 535841097 ps
CPU time 1.31 seconds
Started Jul 13 05:55:53 PM PDT 24
Finished Jul 13 05:55:55 PM PDT 24
Peak memory 204628 kb
Host smart-f3d34b8b-bb55-4fc0-92c1-93d9cc71bdf0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515117894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
515117894
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3845682989
Short name T440
Test name
Test status
Simulation time 644029566 ps
CPU time 4.22 seconds
Started Jul 13 05:56:02 PM PDT 24
Finished Jul 13 05:56:06 PM PDT 24
Peak memory 205184 kb
Host smart-e96d4626-05dc-4a24-9387-8338c2eec54c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845682989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3845682989
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3524250263
Short name T168
Test name
Test status
Simulation time 281728443 ps
CPU time 4.14 seconds
Started Jul 13 05:55:53 PM PDT 24
Finished Jul 13 05:55:58 PM PDT 24
Peak memory 213212 kb
Host smart-7fa9907b-b463-4eea-8016-649b0a50a242
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524250263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3524250263
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.739269032
Short name T390
Test name
Test status
Simulation time 4380975766 ps
CPU time 10.47 seconds
Started Jul 13 05:55:54 PM PDT 24
Finished Jul 13 05:56:05 PM PDT 24
Peak memory 213232 kb
Host smart-e9bc799d-f246-4220-ab5b-ab4bc3e564f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739269032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.739269032
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3576190200
Short name T420
Test name
Test status
Simulation time 2861450100 ps
CPU time 3.34 seconds
Started Jul 13 05:56:01 PM PDT 24
Finished Jul 13 05:56:05 PM PDT 24
Peak memory 213220 kb
Host smart-5e35e694-a352-4707-8e1e-143b83e01be3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576190200 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3576190200
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.413979415
Short name T102
Test name
Test status
Simulation time 303446615 ps
CPU time 1.46 seconds
Started Jul 13 05:56:00 PM PDT 24
Finished Jul 13 05:56:01 PM PDT 24
Peak memory 213032 kb
Host smart-b46accae-606d-496a-8e7b-5fc877fcfdb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413979415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.413979415
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.475778911
Short name T443
Test name
Test status
Simulation time 10364306694 ps
CPU time 3.86 seconds
Started Jul 13 05:55:59 PM PDT 24
Finished Jul 13 05:56:03 PM PDT 24
Peak memory 204784 kb
Host smart-50c75d18-ce38-44c2-96cb-f1065e4aee09
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475778911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r
v_dm_jtag_dmi_csr_bit_bash.475778911
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2653560762
Short name T325
Test name
Test status
Simulation time 4371695640 ps
CPU time 4.66 seconds
Started Jul 13 05:56:02 PM PDT 24
Finished Jul 13 05:56:08 PM PDT 24
Peak memory 204900 kb
Host smart-5d89fb19-567f-45fd-9454-9a662e877f66
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653560762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
653560762
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1989109562
Short name T78
Test name
Test status
Simulation time 612478059 ps
CPU time 1.06 seconds
Started Jul 13 05:56:00 PM PDT 24
Finished Jul 13 05:56:02 PM PDT 24
Peak memory 204628 kb
Host smart-6c535f55-bbcd-4f61-8839-e7b2ad956a81
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989109562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
989109562
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.2813547704
Short name T115
Test name
Test status
Simulation time 246736738 ps
CPU time 6.53 seconds
Started Jul 13 05:56:00 PM PDT 24
Finished Jul 13 05:56:07 PM PDT 24
Peak memory 204896 kb
Host smart-db504dc9-e3f6-484e-8e33-d42826ae43ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813547704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.2813547704
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1467919767
Short name T421
Test name
Test status
Simulation time 51047890075 ps
CPU time 53.57 seconds
Started Jul 13 05:56:00 PM PDT 24
Finished Jul 13 05:56:54 PM PDT 24
Peak memory 222596 kb
Host smart-0fe1d76a-8e97-4730-b533-16ad41e219a3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467919767 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1467919767
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.446812198
Short name T431
Test name
Test status
Simulation time 885769217 ps
CPU time 4.97 seconds
Started Jul 13 05:56:00 PM PDT 24
Finished Jul 13 05:56:05 PM PDT 24
Peak memory 213212 kb
Host smart-8fb1d1dc-5903-4090-982f-81dd9dd47370
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446812198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.446812198
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2908457405
Short name T179
Test name
Test status
Simulation time 1164293978 ps
CPU time 18.33 seconds
Started Jul 13 05:56:02 PM PDT 24
Finished Jul 13 05:56:22 PM PDT 24
Peak memory 213180 kb
Host smart-1d9a05df-6786-4ac5-a8e1-3f730e9dcbb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908457405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2908457405
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.4218962465
Short name T87
Test name
Test status
Simulation time 479906134 ps
CPU time 4.36 seconds
Started Jul 13 05:56:02 PM PDT 24
Finished Jul 13 05:56:08 PM PDT 24
Peak memory 218300 kb
Host smart-2441e0ee-7e77-490b-99c5-ce4b8a498ed1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218962465 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.4218962465
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1045871344
Short name T343
Test name
Test status
Simulation time 123417915 ps
CPU time 1.57 seconds
Started Jul 13 05:55:59 PM PDT 24
Finished Jul 13 05:56:01 PM PDT 24
Peak memory 213076 kb
Host smart-0a71c656-9689-43cb-b165-f3db2cf1f6ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045871344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1045871344
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2588502985
Short name T298
Test name
Test status
Simulation time 5264326973 ps
CPU time 8.6 seconds
Started Jul 13 05:56:00 PM PDT 24
Finished Jul 13 05:56:10 PM PDT 24
Peak memory 204632 kb
Host smart-019ede86-73e5-465a-a68e-2b9721ee3de8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588502985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.2588502985
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3646458693
Short name T294
Test name
Test status
Simulation time 927152000 ps
CPU time 3.34 seconds
Started Jul 13 05:56:02 PM PDT 24
Finished Jul 13 05:56:06 PM PDT 24
Peak memory 204872 kb
Host smart-37f7d615-686b-4862-9fd3-eb704ec51395
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646458693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
646458693
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.524523671
Short name T301
Test name
Test status
Simulation time 546004344 ps
CPU time 1.98 seconds
Started Jul 13 05:56:02 PM PDT 24
Finished Jul 13 05:56:05 PM PDT 24
Peak memory 204524 kb
Host smart-84596aa5-5862-4623-89d7-254f45121d81
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524523671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.524523671
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2648134481
Short name T435
Test name
Test status
Simulation time 584916443 ps
CPU time 8.61 seconds
Started Jul 13 05:55:59 PM PDT 24
Finished Jul 13 05:56:08 PM PDT 24
Peak memory 204884 kb
Host smart-fdee19e6-2ed9-40a4-94ac-b2d563f9579b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648134481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2648134481
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.2154650906
Short name T386
Test name
Test status
Simulation time 18784272088 ps
CPU time 67.81 seconds
Started Jul 13 05:55:59 PM PDT 24
Finished Jul 13 05:57:07 PM PDT 24
Peak memory 221392 kb
Host smart-a13025c9-05c9-4670-b7a7-70d6018da922
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154650906 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.2154650906
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3316360215
Short name T84
Test name
Test status
Simulation time 140547511 ps
CPU time 3.4 seconds
Started Jul 13 05:56:02 PM PDT 24
Finished Jul 13 05:56:06 PM PDT 24
Peak memory 213232 kb
Host smart-7f11992d-6048-414d-aee5-123e6a4309c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316360215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3316360215
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2061117378
Short name T388
Test name
Test status
Simulation time 458884477 ps
CPU time 2.39 seconds
Started Jul 13 05:56:07 PM PDT 24
Finished Jul 13 05:56:10 PM PDT 24
Peak memory 213136 kb
Host smart-8196ab66-897b-4489-9933-25a2667faf22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061117378 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2061117378
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3572084851
Short name T408
Test name
Test status
Simulation time 144180319 ps
CPU time 1.59 seconds
Started Jul 13 05:56:08 PM PDT 24
Finished Jul 13 05:56:10 PM PDT 24
Peak memory 213028 kb
Host smart-9a16af7f-cfdf-4d2e-8dae-689afe59e9a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572084851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3572084851
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1024605522
Short name T324
Test name
Test status
Simulation time 18386673992 ps
CPU time 47.33 seconds
Started Jul 13 05:56:02 PM PDT 24
Finished Jul 13 05:56:51 PM PDT 24
Peak memory 204788 kb
Host smart-4d2dd788-fa1f-45ff-995d-d9836b344526
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024605522 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.1024605522
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1328408783
Short name T424
Test name
Test status
Simulation time 11043484671 ps
CPU time 28.74 seconds
Started Jul 13 05:56:01 PM PDT 24
Finished Jul 13 05:56:30 PM PDT 24
Peak memory 204844 kb
Host smart-29f71b71-939c-4346-adb3-e4d217d6c533
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328408783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
328408783
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1268882217
Short name T434
Test name
Test status
Simulation time 472767324 ps
CPU time 0.89 seconds
Started Jul 13 05:56:00 PM PDT 24
Finished Jul 13 05:56:01 PM PDT 24
Peak memory 204608 kb
Host smart-40f33b77-c9a0-45da-97a8-27c5e7b4a617
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268882217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
268882217
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1398709011
Short name T101
Test name
Test status
Simulation time 804271560 ps
CPU time 6.56 seconds
Started Jul 13 05:56:07 PM PDT 24
Finished Jul 13 05:56:14 PM PDT 24
Peak memory 204852 kb
Host smart-84462eea-1f70-4998-9a2b-c3b787dbff8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398709011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1398709011
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.440585336
Short name T182
Test name
Test status
Simulation time 24327126306 ps
CPU time 46.54 seconds
Started Jul 13 05:56:01 PM PDT 24
Finished Jul 13 05:56:48 PM PDT 24
Peak memory 213236 kb
Host smart-37c4b317-5aaa-4855-b16c-20d95c5648b8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440585336 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.440585336
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2385551193
Short name T81
Test name
Test status
Simulation time 396737596 ps
CPU time 5.27 seconds
Started Jul 13 05:56:01 PM PDT 24
Finished Jul 13 05:56:07 PM PDT 24
Peak memory 213260 kb
Host smart-4ded3c32-ea93-43f4-99a8-b458224012c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385551193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2385551193
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.161911864
Short name T47
Test name
Test status
Simulation time 555810954 ps
CPU time 0.93 seconds
Started Jul 13 04:44:47 PM PDT 24
Finished Jul 13 04:44:49 PM PDT 24
Peak memory 205008 kb
Host smart-d43bb104-e735-473c-a2c0-7aab9349cd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161911864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.161911864
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3275352861
Short name T243
Test name
Test status
Simulation time 168747606 ps
CPU time 0.8 seconds
Started Jul 13 04:44:53 PM PDT 24
Finished Jul 13 04:44:55 PM PDT 24
Peak memory 205088 kb
Host smart-32c7ee3f-81b8-4e6f-bc82-cd306fe6825c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275352861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3275352861
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1850556097
Short name T284
Test name
Test status
Simulation time 930024820 ps
CPU time 1.46 seconds
Started Jul 13 04:44:46 PM PDT 24
Finished Jul 13 04:44:48 PM PDT 24
Peak memory 205388 kb
Host smart-06c569b4-aa14-41a7-b747-c059059dadc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850556097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1850556097
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3492501561
Short name T11
Test name
Test status
Simulation time 627293398 ps
CPU time 1.16 seconds
Started Jul 13 04:44:43 PM PDT 24
Finished Jul 13 04:44:45 PM PDT 24
Peak memory 205092 kb
Host smart-d558593b-227b-4266-9fdf-906ce950b236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492501561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3492501561
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1346485023
Short name T188
Test name
Test status
Simulation time 214340912 ps
CPU time 0.82 seconds
Started Jul 13 04:44:44 PM PDT 24
Finished Jul 13 04:44:46 PM PDT 24
Peak memory 205064 kb
Host smart-2a82165a-c731-4f57-933c-842be33e32af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346485023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1346485023
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1437116296
Short name T233
Test name
Test status
Simulation time 73753884 ps
CPU time 0.87 seconds
Started Jul 13 04:44:43 PM PDT 24
Finished Jul 13 04:44:45 PM PDT 24
Peak memory 205000 kb
Host smart-f8fc8d7e-65a6-4a3a-ae4d-3efac30974e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437116296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1437116296
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3502636561
Short name T264
Test name
Test status
Simulation time 1622286225 ps
CPU time 5.98 seconds
Started Jul 13 04:44:43 PM PDT 24
Finished Jul 13 04:44:50 PM PDT 24
Peak memory 205384 kb
Host smart-491b4402-72f0-4728-912f-90a95a3790c3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502636561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3502636561
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.4080015981
Short name T213
Test name
Test status
Simulation time 210112503 ps
CPU time 1.24 seconds
Started Jul 13 04:44:45 PM PDT 24
Finished Jul 13 04:44:48 PM PDT 24
Peak memory 204960 kb
Host smart-e70999cf-414b-4e88-822e-386c5d1f1ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080015981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.4080015981
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1170738156
Short name T247
Test name
Test status
Simulation time 209857429 ps
CPU time 1.04 seconds
Started Jul 13 04:44:45 PM PDT 24
Finished Jul 13 04:44:47 PM PDT 24
Peak memory 205008 kb
Host smart-79ec9a0e-4c7e-4e0f-8570-69fe88d79264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170738156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1170738156
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.99630122
Short name T260
Test name
Test status
Simulation time 451481492 ps
CPU time 1 seconds
Started Jul 13 04:44:43 PM PDT 24
Finished Jul 13 04:44:45 PM PDT 24
Peak memory 205024 kb
Host smart-860b5cfb-f9f8-4e92-9f71-7c2dafb48b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99630122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.99630122
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.301731863
Short name T289
Test name
Test status
Simulation time 2249505173 ps
CPU time 4.62 seconds
Started Jul 13 04:44:47 PM PDT 24
Finished Jul 13 04:44:53 PM PDT 24
Peak memory 205280 kb
Host smart-cae51773-530a-42b7-8ff3-7116c381247e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301731863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.301731863
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.482185761
Short name T249
Test name
Test status
Simulation time 580241903 ps
CPU time 2.04 seconds
Started Jul 13 04:44:48 PM PDT 24
Finished Jul 13 04:44:52 PM PDT 24
Peak memory 205120 kb
Host smart-af71a898-10e7-42af-a664-71ed333c3753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482185761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.482185761
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2372600442
Short name T184
Test name
Test status
Simulation time 515801535 ps
CPU time 2.2 seconds
Started Jul 13 04:44:47 PM PDT 24
Finished Jul 13 04:44:50 PM PDT 24
Peak memory 205288 kb
Host smart-a5d5424b-5a86-4c16-a1d1-aa43ca9912b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372600442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2372600442
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2894360436
Short name T35
Test name
Test status
Simulation time 394286159 ps
CPU time 1.01 seconds
Started Jul 13 04:44:45 PM PDT 24
Finished Jul 13 04:44:47 PM PDT 24
Peak memory 205068 kb
Host smart-d86a4fc0-956a-4f59-838a-579328f6826e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894360436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2894360436
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.628824049
Short name T130
Test name
Test status
Simulation time 743532843 ps
CPU time 1.17 seconds
Started Jul 13 04:44:46 PM PDT 24
Finished Jul 13 04:44:48 PM PDT 24
Peak memory 205004 kb
Host smart-f1999eea-c4bd-4b75-bfc5-97f907bc0594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628824049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.628824049
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.757023082
Short name T73
Test name
Test status
Simulation time 888679538 ps
CPU time 3.52 seconds
Started Jul 13 04:44:53 PM PDT 24
Finished Jul 13 04:44:58 PM PDT 24
Peak memory 228852 kb
Host smart-fecb0496-7d16-4305-abaf-3a40258fe568
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757023082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.757023082
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2610955800
Short name T227
Test name
Test status
Simulation time 1961346875 ps
CPU time 1.63 seconds
Started Jul 13 04:44:43 PM PDT 24
Finished Jul 13 04:44:46 PM PDT 24
Peak memory 205108 kb
Host smart-b99920b9-ea72-4ada-8363-c06e266af9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610955800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2610955800
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.4169159348
Short name T5
Test name
Test status
Simulation time 2504618718 ps
CPU time 3.08 seconds
Started Jul 13 04:44:57 PM PDT 24
Finished Jul 13 04:45:00 PM PDT 24
Peak memory 213440 kb
Host smart-82e33099-bb27-4d38-b86c-a1c32d3dfde0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169159348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.4169159348
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.893525093
Short name T287
Test name
Test status
Simulation time 178955063 ps
CPU time 0.75 seconds
Started Jul 13 04:45:04 PM PDT 24
Finished Jul 13 04:45:06 PM PDT 24
Peak memory 205036 kb
Host smart-24287cd0-e625-4c5a-997a-cd1faef6b100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893525093 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.893525093
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3113053652
Short name T16
Test name
Test status
Simulation time 279826734 ps
CPU time 1.09 seconds
Started Jul 13 04:44:52 PM PDT 24
Finished Jul 13 04:44:54 PM PDT 24
Peak memory 205044 kb
Host smart-7088a839-55c6-4f52-84c2-4590c014734d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113053652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3113053652
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.901800717
Short name T22
Test name
Test status
Simulation time 2424296867 ps
CPU time 3.29 seconds
Started Jul 13 04:44:57 PM PDT 24
Finished Jul 13 04:45:01 PM PDT 24
Peak memory 205084 kb
Host smart-45e548c1-99de-4318-99f2-a770ab778760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901800717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.901800717
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3513540440
Short name T40
Test name
Test status
Simulation time 343201809 ps
CPU time 1.73 seconds
Started Jul 13 04:44:54 PM PDT 24
Finished Jul 13 04:44:57 PM PDT 24
Peak memory 204992 kb
Host smart-9bddd34d-e229-4971-b8a1-eb9b1dd42e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513540440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3513540440
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2550956744
Short name T186
Test name
Test status
Simulation time 881063391 ps
CPU time 1.66 seconds
Started Jul 13 04:44:52 PM PDT 24
Finished Jul 13 04:44:55 PM PDT 24
Peak memory 204996 kb
Host smart-0a45d10b-d51c-4df1-ad29-83f1fbe5ad79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550956744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2550956744
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.2134551236
Short name T190
Test name
Test status
Simulation time 395157408 ps
CPU time 0.93 seconds
Started Jul 13 04:44:53 PM PDT 24
Finished Jul 13 04:44:54 PM PDT 24
Peak memory 205100 kb
Host smart-24ff7f13-13b1-46a8-b60c-46f902d7af38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134551236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.2134551236
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.1316508963
Short name T58
Test name
Test status
Simulation time 484613948 ps
CPU time 1.97 seconds
Started Jul 13 04:44:53 PM PDT 24
Finished Jul 13 04:44:57 PM PDT 24
Peak memory 205112 kb
Host smart-a11b75f6-1b25-4112-9e21-0996aacaa33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316508963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.1316508963
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.554148217
Short name T256
Test name
Test status
Simulation time 1930172922 ps
CPU time 4.13 seconds
Started Jul 13 04:44:51 PM PDT 24
Finished Jul 13 04:44:56 PM PDT 24
Peak memory 205028 kb
Host smart-83be63df-1872-43b5-a1ac-de4d417ffe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554148217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.554148217
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2669339358
Short name T208
Test name
Test status
Simulation time 371482602 ps
CPU time 1.7 seconds
Started Jul 13 04:44:53 PM PDT 24
Finished Jul 13 04:44:56 PM PDT 24
Peak memory 204960 kb
Host smart-367b83aa-f7e2-4b5c-a49d-b549bf34b67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669339358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2669339358
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1023452181
Short name T250
Test name
Test status
Simulation time 262830441 ps
CPU time 1.36 seconds
Started Jul 13 04:44:53 PM PDT 24
Finished Jul 13 04:44:55 PM PDT 24
Peak memory 205012 kb
Host smart-318a3ea4-9c66-4240-a0d2-810711818cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023452181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1023452181
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1081482464
Short name T269
Test name
Test status
Simulation time 459830563 ps
CPU time 0.97 seconds
Started Jul 13 04:44:54 PM PDT 24
Finished Jul 13 04:44:57 PM PDT 24
Peak memory 204916 kb
Host smart-0b90e6f6-12ef-4161-905f-6d07182f8f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081482464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1081482464
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2532104179
Short name T36
Test name
Test status
Simulation time 2122450065 ps
CPU time 2.68 seconds
Started Jul 13 04:44:58 PM PDT 24
Finished Jul 13 04:45:01 PM PDT 24
Peak memory 204964 kb
Host smart-38f9ae5e-9ba7-4482-ba59-08063f563859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532104179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2532104179
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3774919272
Short name T253
Test name
Test status
Simulation time 288452296 ps
CPU time 0.86 seconds
Started Jul 13 04:44:51 PM PDT 24
Finished Jul 13 04:44:53 PM PDT 24
Peak memory 204964 kb
Host smart-e9e16e3d-17c7-48a3-aac6-4e16f4c04eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774919272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3774919272
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1882779763
Short name T185
Test name
Test status
Simulation time 1350686820 ps
CPU time 1.82 seconds
Started Jul 13 04:44:57 PM PDT 24
Finished Jul 13 04:44:59 PM PDT 24
Peak memory 205056 kb
Host smart-5bca1087-d35e-42e4-abc8-92df9959063c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882779763 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1882779763
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.561393897
Short name T187
Test name
Test status
Simulation time 1615732318 ps
CPU time 1.28 seconds
Started Jul 13 04:44:53 PM PDT 24
Finished Jul 13 04:44:55 PM PDT 24
Peak memory 205336 kb
Host smart-10501649-854b-4049-8ce3-fba7cddb7805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561393897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.561393897
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3513181689
Short name T65
Test name
Test status
Simulation time 434425743 ps
CPU time 1.07 seconds
Started Jul 13 04:44:52 PM PDT 24
Finished Jul 13 04:44:54 PM PDT 24
Peak memory 205100 kb
Host smart-732bfa71-26d5-4fbf-a606-8c8e39d5b8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513181689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3513181689
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3262279760
Short name T29
Test name
Test status
Simulation time 542735241 ps
CPU time 1.52 seconds
Started Jul 13 04:44:57 PM PDT 24
Finished Jul 13 04:44:59 PM PDT 24
Peak memory 205020 kb
Host smart-145c0d0c-56c1-4b4d-a8fb-8ad2da5e4f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262279760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3262279760
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.4224893442
Short name T6
Test name
Test status
Simulation time 250340108 ps
CPU time 1.21 seconds
Started Jul 13 04:44:52 PM PDT 24
Finished Jul 13 04:44:54 PM PDT 24
Peak memory 205108 kb
Host smart-ef4fa6e1-c00e-41c0-8f94-567e6aa8bbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224893442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.4224893442
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.2177144893
Short name T42
Test name
Test status
Simulation time 43942274 ps
CPU time 0.81 seconds
Started Jul 13 04:44:57 PM PDT 24
Finished Jul 13 04:44:59 PM PDT 24
Peak memory 213288 kb
Host smart-216ea1f6-2ca7-4e77-8008-255df9c6305f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177144893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.2177144893
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.2192320798
Short name T80
Test name
Test status
Simulation time 736812749 ps
CPU time 1.68 seconds
Started Jul 13 04:44:51 PM PDT 24
Finished Jul 13 04:44:53 PM PDT 24
Peak memory 205000 kb
Host smart-b5bcaa9f-5a1c-4bba-aba5-b42785dcc4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192320798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.2192320798
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3959988236
Short name T288
Test name
Test status
Simulation time 9551730432 ps
CPU time 8.21 seconds
Started Jul 13 04:44:53 PM PDT 24
Finished Jul 13 04:45:02 PM PDT 24
Peak memory 213676 kb
Host smart-5fbefdbe-eb9e-49ed-a8f1-d8b26829eeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959988236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3959988236
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3970982377
Short name T275
Test name
Test status
Simulation time 2777831733 ps
CPU time 3.27 seconds
Started Jul 13 04:44:57 PM PDT 24
Finished Jul 13 04:45:01 PM PDT 24
Peak memory 205080 kb
Host smart-8ed3583c-df2f-415c-9b91-c7393f6156df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970982377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3970982377
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.3623696668
Short name T19
Test name
Test status
Simulation time 2497694242 ps
CPU time 3.37 seconds
Started Jul 13 04:44:58 PM PDT 24
Finished Jul 13 04:45:02 PM PDT 24
Peak memory 205260 kb
Host smart-d5edb18a-49d3-460a-ba24-906aa25df218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623696668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3623696668
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3496637908
Short name T75
Test name
Test status
Simulation time 60948986 ps
CPU time 0.7 seconds
Started Jul 13 04:45:22 PM PDT 24
Finished Jul 13 04:45:24 PM PDT 24
Peak memory 205092 kb
Host smart-383498ed-76a0-4c22-ace1-9d0c2dba61ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496637908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3496637908
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1410588453
Short name T274
Test name
Test status
Simulation time 2543785272 ps
CPU time 2.63 seconds
Started Jul 13 04:45:22 PM PDT 24
Finished Jul 13 04:45:26 PM PDT 24
Peak memory 221860 kb
Host smart-7fc8254e-d814-4d8c-9da3-38832638aab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410588453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1410588453
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2608102193
Short name T164
Test name
Test status
Simulation time 1089189527 ps
CPU time 1.67 seconds
Started Jul 13 04:45:24 PM PDT 24
Finished Jul 13 04:45:27 PM PDT 24
Peak memory 213644 kb
Host smart-ae4f01d7-755c-4bb8-83ce-fbd8d24548ff
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608102193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2608102193
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1926361162
Short name T286
Test name
Test status
Simulation time 4812856144 ps
CPU time 15.45 seconds
Started Jul 13 04:45:22 PM PDT 24
Finished Jul 13 04:45:39 PM PDT 24
Peak memory 213760 kb
Host smart-e480e92a-f691-4117-82f9-2de1e135af8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926361162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1926361162
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.4201334066
Short name T222
Test name
Test status
Simulation time 2104098697 ps
CPU time 6.4 seconds
Started Jul 13 04:45:22 PM PDT 24
Finished Jul 13 04:45:30 PM PDT 24
Peak memory 213604 kb
Host smart-ec6e9b52-1a19-4ebf-9551-0e18e693a227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201334066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.4201334066
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.258220003
Short name T258
Test name
Test status
Simulation time 2385978925 ps
CPU time 3.12 seconds
Started Jul 13 04:45:25 PM PDT 24
Finished Jul 13 04:45:29 PM PDT 24
Peak memory 213572 kb
Host smart-9f84841a-0f13-494d-afe9-ae0dd4f86339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258220003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.258220003
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2575296077
Short name T50
Test name
Test status
Simulation time 67017661 ps
CPU time 0.84 seconds
Started Jul 13 04:45:26 PM PDT 24
Finished Jul 13 04:45:27 PM PDT 24
Peak memory 205136 kb
Host smart-7b9c2279-d8d4-4f91-a858-bc48b0454f77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575296077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2575296077
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.4074440033
Short name T244
Test name
Test status
Simulation time 2383828388 ps
CPU time 4.58 seconds
Started Jul 13 04:45:23 PM PDT 24
Finished Jul 13 04:45:29 PM PDT 24
Peak memory 213656 kb
Host smart-846d2f4e-c054-46f8-96f4-95db92952fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074440033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.4074440033
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.564853293
Short name T236
Test name
Test status
Simulation time 6135571678 ps
CPU time 6.47 seconds
Started Jul 13 04:45:22 PM PDT 24
Finished Jul 13 04:45:29 PM PDT 24
Peak memory 213624 kb
Host smart-b6caf199-3332-4b7d-a6b1-0b806cfb6f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564853293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.564853293
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1409919159
Short name T290
Test name
Test status
Simulation time 1211978722 ps
CPU time 1.46 seconds
Started Jul 13 04:45:24 PM PDT 24
Finished Jul 13 04:45:26 PM PDT 24
Peak memory 213540 kb
Host smart-f656a68c-5ddb-4167-a26b-287200436205
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1409919159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1409919159
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2421387800
Short name T270
Test name
Test status
Simulation time 1789157289 ps
CPU time 2.49 seconds
Started Jul 13 04:45:25 PM PDT 24
Finished Jul 13 04:45:28 PM PDT 24
Peak memory 213528 kb
Host smart-8d2d976c-b31c-41e9-b4ad-181facff8b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421387800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2421387800
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.4139469065
Short name T183
Test name
Test status
Simulation time 7207337302 ps
CPU time 10.13 seconds
Started Jul 13 04:45:23 PM PDT 24
Finished Jul 13 04:45:35 PM PDT 24
Peak memory 205320 kb
Host smart-53f80cf7-e159-491e-832e-9926f0ce63ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139469065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.4139469065
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3512319212
Short name T193
Test name
Test status
Simulation time 80132398 ps
CPU time 0.75 seconds
Started Jul 13 04:45:23 PM PDT 24
Finished Jul 13 04:45:25 PM PDT 24
Peak memory 205024 kb
Host smart-7d85ed8e-d53f-42ee-8b95-ccbc164794cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512319212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3512319212
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.930271529
Short name T198
Test name
Test status
Simulation time 5534090717 ps
CPU time 14.17 seconds
Started Jul 13 04:45:23 PM PDT 24
Finished Jul 13 04:45:38 PM PDT 24
Peak memory 213632 kb
Host smart-26fb749a-15ca-4eed-b3e1-f2696fc81fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930271529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.930271529
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1853020573
Short name T64
Test name
Test status
Simulation time 1312046736 ps
CPU time 4.89 seconds
Started Jul 13 04:45:24 PM PDT 24
Finished Jul 13 04:45:30 PM PDT 24
Peak memory 205356 kb
Host smart-943c037c-804c-472d-b1a5-84abdff7f8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853020573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1853020573
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.642717724
Short name T10
Test name
Test status
Simulation time 1473171853 ps
CPU time 5.29 seconds
Started Jul 13 04:45:23 PM PDT 24
Finished Jul 13 04:45:30 PM PDT 24
Peak memory 213552 kb
Host smart-bc288919-9880-4ee4-8d77-c48e3cc7d261
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642717724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.642717724
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.4150625961
Short name T221
Test name
Test status
Simulation time 42274539 ps
CPU time 0.78 seconds
Started Jul 13 04:45:32 PM PDT 24
Finished Jul 13 04:45:34 PM PDT 24
Peak memory 205116 kb
Host smart-7adca575-2a01-4cad-b28e-8e7f8d787fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150625961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.4150625961
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3325598029
Short name T263
Test name
Test status
Simulation time 22805996373 ps
CPU time 72.34 seconds
Started Jul 13 04:45:34 PM PDT 24
Finished Jul 13 04:46:48 PM PDT 24
Peak memory 213636 kb
Host smart-c9e32a4f-bd7e-4fe8-95c1-93924934c294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325598029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3325598029
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1264512120
Short name T239
Test name
Test status
Simulation time 3743739829 ps
CPU time 4.26 seconds
Started Jul 13 04:45:23 PM PDT 24
Finished Jul 13 04:45:28 PM PDT 24
Peak memory 215396 kb
Host smart-02f05b01-e9e1-4ebc-b84d-ae780de731c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264512120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1264512120
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3613340271
Short name T292
Test name
Test status
Simulation time 3914464812 ps
CPU time 11.56 seconds
Started Jul 13 04:45:20 PM PDT 24
Finished Jul 13 04:45:32 PM PDT 24
Peak memory 213628 kb
Host smart-3d96f79b-b876-48de-b17d-94928834aafc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3613340271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3613340271
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3954877405
Short name T277
Test name
Test status
Simulation time 47223785 ps
CPU time 0.78 seconds
Started Jul 13 04:45:33 PM PDT 24
Finished Jul 13 04:45:35 PM PDT 24
Peak memory 204984 kb
Host smart-6038942d-089a-4068-9ac2-a325c473da38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954877405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3954877405
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1399851653
Short name T285
Test name
Test status
Simulation time 6042883916 ps
CPU time 5.61 seconds
Started Jul 13 04:45:30 PM PDT 24
Finished Jul 13 04:45:36 PM PDT 24
Peak memory 215068 kb
Host smart-e12756aa-4955-43ea-9695-31d4147586c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399851653 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1399851653
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.812634685
Short name T59
Test name
Test status
Simulation time 12337543528 ps
CPU time 9.62 seconds
Started Jul 13 04:45:33 PM PDT 24
Finished Jul 13 04:45:45 PM PDT 24
Peak memory 213608 kb
Host smart-b45c211a-ba32-4bb4-9348-c112b971c2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812634685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.812634685
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.739972033
Short name T9
Test name
Test status
Simulation time 7449978426 ps
CPU time 4.72 seconds
Started Jul 13 04:45:35 PM PDT 24
Finished Jul 13 04:45:42 PM PDT 24
Peak memory 213608 kb
Host smart-8130bb93-f6da-4d19-a680-9c2874819bb7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=739972033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_t
l_access.739972033
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2224255846
Short name T219
Test name
Test status
Simulation time 3510464741 ps
CPU time 7.6 seconds
Started Jul 13 04:45:37 PM PDT 24
Finished Jul 13 04:45:45 PM PDT 24
Peak memory 213452 kb
Host smart-598dab98-37a0-4ea0-b7e1-7f4da75a5664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224255846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2224255846
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2991517038
Short name T225
Test name
Test status
Simulation time 118593053 ps
CPU time 0.98 seconds
Started Jul 13 04:45:33 PM PDT 24
Finished Jul 13 04:45:37 PM PDT 24
Peak memory 205096 kb
Host smart-81fd1cdb-ffdb-4484-a8bf-9f4f57755cfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991517038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2991517038
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.12206492
Short name T163
Test name
Test status
Simulation time 6791409287 ps
CPU time 3.41 seconds
Started Jul 13 04:45:34 PM PDT 24
Finished Jul 13 04:45:40 PM PDT 24
Peak memory 213680 kb
Host smart-33ba63dd-aa5d-4da9-8696-cba643a7c09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12206492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.12206492
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.695402832
Short name T224
Test name
Test status
Simulation time 7661408691 ps
CPU time 6.38 seconds
Started Jul 13 04:45:34 PM PDT 24
Finished Jul 13 04:45:42 PM PDT 24
Peak memory 205516 kb
Host smart-ebe7b35d-a1ee-423d-88d5-a3d3ea92b1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695402832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.695402832
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1034583673
Short name T293
Test name
Test status
Simulation time 6999173553 ps
CPU time 4.88 seconds
Started Jul 13 04:45:35 PM PDT 24
Finished Jul 13 04:45:42 PM PDT 24
Peak memory 205480 kb
Host smart-bcf77575-4f2a-4d60-90d6-6e2ed9194b9a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1034583673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1034583673
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.50510134
Short name T136
Test name
Test status
Simulation time 3477250262 ps
CPU time 6.26 seconds
Started Jul 13 04:45:35 PM PDT 24
Finished Jul 13 04:45:44 PM PDT 24
Peak memory 213628 kb
Host smart-4adadc06-d2ce-4ea1-9fda-cc364225da44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50510134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.50510134
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3184307356
Short name T231
Test name
Test status
Simulation time 51309251 ps
CPU time 0.76 seconds
Started Jul 13 04:45:32 PM PDT 24
Finished Jul 13 04:45:34 PM PDT 24
Peak memory 205000 kb
Host smart-5d30985b-b66a-418f-8449-56becbb77bd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184307356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3184307356
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3307587250
Short name T254
Test name
Test status
Simulation time 44316216062 ps
CPU time 123.29 seconds
Started Jul 13 04:45:36 PM PDT 24
Finished Jul 13 04:47:41 PM PDT 24
Peak memory 212916 kb
Host smart-ad422ead-1f56-4ab0-a889-676ef0d08bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307587250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3307587250
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.878447531
Short name T255
Test name
Test status
Simulation time 5249490724 ps
CPU time 15.64 seconds
Started Jul 13 04:45:34 PM PDT 24
Finished Jul 13 04:45:52 PM PDT 24
Peak memory 213540 kb
Host smart-8180e352-b096-4a42-898b-0e56e9d957da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878447531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.878447531
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.4116411706
Short name T62
Test name
Test status
Simulation time 2113803394 ps
CPU time 7.38 seconds
Started Jul 13 04:45:31 PM PDT 24
Finished Jul 13 04:45:40 PM PDT 24
Peak memory 205428 kb
Host smart-3fcac952-bbc0-4095-a7be-32851786dd42
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4116411706 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.4116411706
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.437195693
Short name T60
Test name
Test status
Simulation time 2590010524 ps
CPU time 7.45 seconds
Started Jul 13 04:45:34 PM PDT 24
Finished Jul 13 04:45:43 PM PDT 24
Peak memory 213572 kb
Host smart-e04525f9-7c2c-4c70-a37e-a3d9f8282702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437195693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.437195693
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.2711562752
Short name T18
Test name
Test status
Simulation time 4936762707 ps
CPU time 7.78 seconds
Started Jul 13 04:45:33 PM PDT 24
Finished Jul 13 04:45:43 PM PDT 24
Peak memory 205364 kb
Host smart-b1d0b66b-48ef-4c82-9008-4d2216b673aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711562752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2711562752
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2537709523
Short name T215
Test name
Test status
Simulation time 132642289 ps
CPU time 0.93 seconds
Started Jul 13 04:45:36 PM PDT 24
Finished Jul 13 04:45:39 PM PDT 24
Peak memory 204360 kb
Host smart-4810e9ea-696b-4964-bb79-a2660aa3dd33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537709523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2537709523
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2232328465
Short name T196
Test name
Test status
Simulation time 3994086755 ps
CPU time 6.3 seconds
Started Jul 13 04:45:32 PM PDT 24
Finished Jul 13 04:45:39 PM PDT 24
Peak memory 215540 kb
Host smart-79c4f32a-cf36-4a1a-a1de-6d0f49fd5222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232328465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2232328465
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1600036215
Short name T238
Test name
Test status
Simulation time 1265232388 ps
CPU time 3.04 seconds
Started Jul 13 04:45:32 PM PDT 24
Finished Jul 13 04:45:36 PM PDT 24
Peak memory 213532 kb
Host smart-1d76764c-3c28-4426-8427-a769be1d64f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600036215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1600036215
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2715959672
Short name T157
Test name
Test status
Simulation time 14673619542 ps
CPU time 44.31 seconds
Started Jul 13 04:45:34 PM PDT 24
Finished Jul 13 04:46:21 PM PDT 24
Peak memory 213576 kb
Host smart-fa70a8cf-8b4c-420a-b282-258b44e11296
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2715959672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2715959672
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.465482404
Short name T151
Test name
Test status
Simulation time 1793945358 ps
CPU time 2.35 seconds
Started Jul 13 04:45:36 PM PDT 24
Finished Jul 13 04:45:40 PM PDT 24
Peak memory 213404 kb
Host smart-ea7d81f6-e8e3-4dc4-b89a-815ec5200465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465482404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.465482404
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2573887837
Short name T148
Test name
Test status
Simulation time 3580548776 ps
CPU time 5.89 seconds
Started Jul 13 04:45:33 PM PDT 24
Finished Jul 13 04:45:40 PM PDT 24
Peak memory 213520 kb
Host smart-42a2df68-a842-4b50-bbbe-938209fd7642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573887837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2573887837
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1868974159
Short name T242
Test name
Test status
Simulation time 115343765 ps
CPU time 1 seconds
Started Jul 13 04:45:34 PM PDT 24
Finished Jul 13 04:45:37 PM PDT 24
Peak memory 205032 kb
Host smart-7a4b2eb9-16eb-4b1b-9974-32be94653c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868974159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1868974159
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.1248506445
Short name T251
Test name
Test status
Simulation time 12366213132 ps
CPU time 30.34 seconds
Started Jul 13 04:45:35 PM PDT 24
Finished Jul 13 04:46:07 PM PDT 24
Peak memory 213592 kb
Host smart-3c00203b-bb8c-4c04-8be2-614536ee6594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248506445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.1248506445
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.553258136
Short name T271
Test name
Test status
Simulation time 895890249 ps
CPU time 1.82 seconds
Started Jul 13 04:45:34 PM PDT 24
Finished Jul 13 04:45:38 PM PDT 24
Peak memory 205392 kb
Host smart-f5c2e7bf-1204-42dd-bdb5-19a94a3aec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553258136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.553258136
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2950998992
Short name T202
Test name
Test status
Simulation time 83553994 ps
CPU time 0.75 seconds
Started Jul 13 04:45:00 PM PDT 24
Finished Jul 13 04:45:02 PM PDT 24
Peak memory 205152 kb
Host smart-c3322d7b-1e89-489f-b4e8-78bed4e8d5bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950998992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2950998992
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.282704102
Short name T205
Test name
Test status
Simulation time 2256715442 ps
CPU time 2.7 seconds
Started Jul 13 04:45:03 PM PDT 24
Finished Jul 13 04:45:08 PM PDT 24
Peak memory 213552 kb
Host smart-cfb70695-3409-4fd3-b989-58d75e3f0b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282704102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.282704102
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3243830284
Short name T283
Test name
Test status
Simulation time 3361057122 ps
CPU time 2.99 seconds
Started Jul 13 04:45:04 PM PDT 24
Finished Jul 13 04:45:09 PM PDT 24
Peak memory 205192 kb
Host smart-63398cf8-e362-4bb3-b9cb-0ab35b4b3d4e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3243830284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3243830284
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.4029200351
Short name T234
Test name
Test status
Simulation time 326544082 ps
CPU time 0.88 seconds
Started Jul 13 04:45:03 PM PDT 24
Finished Jul 13 04:45:06 PM PDT 24
Peak memory 205004 kb
Host smart-20a3dd6e-ef59-44ff-840b-6ca6c9518081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029200351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.4029200351
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.3926058416
Short name T54
Test name
Test status
Simulation time 2655130444 ps
CPU time 1.75 seconds
Started Jul 13 04:45:02 PM PDT 24
Finished Jul 13 04:45:05 PM PDT 24
Peak memory 229184 kb
Host smart-d762a628-b72a-4aac-82bb-af623bf0fbc1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926058416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3926058416
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.3681449816
Short name T13
Test name
Test status
Simulation time 2711047201 ps
CPU time 7.84 seconds
Started Jul 13 04:45:04 PM PDT 24
Finished Jul 13 04:45:13 PM PDT 24
Peak memory 214236 kb
Host smart-601e550c-65c5-4621-99ba-6746b75835a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681449816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3681449816
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2861506746
Short name T121
Test name
Test status
Simulation time 73039365 ps
CPU time 0.71 seconds
Started Jul 13 04:45:36 PM PDT 24
Finished Jul 13 04:45:38 PM PDT 24
Peak memory 204912 kb
Host smart-4afa0c7a-611c-4f33-9df7-b8a0d5fa4f63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861506746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2861506746
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.1709187380
Short name T34
Test name
Test status
Simulation time 5076333638 ps
CPU time 4.76 seconds
Started Jul 13 04:45:34 PM PDT 24
Finished Jul 13 04:45:41 PM PDT 24
Peak memory 213528 kb
Host smart-f368bc9f-cae5-44a9-9438-993f620e3283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709187380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.1709187380
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.2467513929
Short name T281
Test name
Test status
Simulation time 227826885 ps
CPU time 0.69 seconds
Started Jul 13 04:45:35 PM PDT 24
Finished Jul 13 04:45:38 PM PDT 24
Peak memory 205052 kb
Host smart-78410df1-5892-46be-b52d-1bca9565b8e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467513929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2467513929
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.913138002
Short name T51
Test name
Test status
Simulation time 71843247 ps
CPU time 0.75 seconds
Started Jul 13 04:45:32 PM PDT 24
Finished Jul 13 04:45:34 PM PDT 24
Peak memory 205096 kb
Host smart-93f7e23d-e3dc-4cee-87f6-6c27dec57678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913138002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.913138002
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.2810294017
Short name T131
Test name
Test status
Simulation time 3533563501 ps
CPU time 9.85 seconds
Started Jul 13 04:45:35 PM PDT 24
Finished Jul 13 04:45:47 PM PDT 24
Peak memory 205272 kb
Host smart-60f9a4ef-2f0e-4aca-b9ec-16e153077636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810294017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2810294017
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1637836568
Short name T199
Test name
Test status
Simulation time 284289736 ps
CPU time 0.74 seconds
Started Jul 13 04:45:32 PM PDT 24
Finished Jul 13 04:45:34 PM PDT 24
Peak memory 205124 kb
Host smart-2ef15538-39b4-4ef9-a2b0-26f87ca8dbce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637836568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1637836568
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.1671708714
Short name T146
Test name
Test status
Simulation time 13833717979 ps
CPU time 11.88 seconds
Started Jul 13 04:45:33 PM PDT 24
Finished Jul 13 04:45:46 PM PDT 24
Peak memory 213552 kb
Host smart-8436be8b-d9a1-4b30-9cbd-91b7782ca41b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671708714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.1671708714
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.1081374678
Short name T237
Test name
Test status
Simulation time 78748140 ps
CPU time 0.79 seconds
Started Jul 13 04:45:33 PM PDT 24
Finished Jul 13 04:45:37 PM PDT 24
Peak memory 205096 kb
Host smart-502e5e3e-9731-488b-a426-96f5e292b3b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081374678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1081374678
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.1012769820
Short name T189
Test name
Test status
Simulation time 12732762990 ps
CPU time 32.31 seconds
Started Jul 13 04:45:33 PM PDT 24
Finished Jul 13 04:46:08 PM PDT 24
Peak memory 213516 kb
Host smart-e5e5d1a1-c460-4678-9aff-2ce0d87921a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012769820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.1012769820
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2162106811
Short name T119
Test name
Test status
Simulation time 32603368 ps
CPU time 0.75 seconds
Started Jul 13 04:45:37 PM PDT 24
Finished Jul 13 04:45:39 PM PDT 24
Peak memory 204912 kb
Host smart-6bc6661e-48d2-43f3-9bf4-d5ebe5acb6f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162106811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2162106811
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2293533722
Short name T229
Test name
Test status
Simulation time 115325463 ps
CPU time 0.74 seconds
Started Jul 13 04:45:35 PM PDT 24
Finished Jul 13 04:45:38 PM PDT 24
Peak memory 205036 kb
Host smart-ad8c36f2-31e1-4005-a3f8-ef1929254049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293533722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2293533722
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.3877955485
Short name T141
Test name
Test status
Simulation time 2076798784 ps
CPU time 6.26 seconds
Started Jul 13 04:45:33 PM PDT 24
Finished Jul 13 04:45:41 PM PDT 24
Peak memory 205160 kb
Host smart-199bb4f9-c4e5-47dd-9123-795ea4025b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877955485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3877955485
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.829150867
Short name T226
Test name
Test status
Simulation time 57669997 ps
CPU time 0.79 seconds
Started Jul 13 04:45:32 PM PDT 24
Finished Jul 13 04:45:35 PM PDT 24
Peak memory 204996 kb
Host smart-61625caa-5562-481e-adef-3636318378b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829150867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.829150867
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.4242255853
Short name T235
Test name
Test status
Simulation time 3432147361 ps
CPU time 6.25 seconds
Started Jul 13 04:45:36 PM PDT 24
Finished Jul 13 04:45:44 PM PDT 24
Peak memory 205268 kb
Host smart-1e337ca8-dd3e-4118-93ac-880b0f91cf69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242255853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.4242255853
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1619356619
Short name T201
Test name
Test status
Simulation time 57954161 ps
CPU time 0.73 seconds
Started Jul 13 04:45:32 PM PDT 24
Finished Jul 13 04:45:34 PM PDT 24
Peak memory 205112 kb
Host smart-afe1c691-33ca-4c49-92b4-a49ad6c02763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619356619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1619356619
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.387513798
Short name T145
Test name
Test status
Simulation time 2858726857 ps
CPU time 8.69 seconds
Started Jul 13 04:45:35 PM PDT 24
Finished Jul 13 04:45:46 PM PDT 24
Peak memory 205344 kb
Host smart-3a66950f-8028-4041-83a5-a1a6bbba19f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387513798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.387513798
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3904849052
Short name T206
Test name
Test status
Simulation time 81454410 ps
CPU time 0.71 seconds
Started Jul 13 04:45:45 PM PDT 24
Finished Jul 13 04:45:47 PM PDT 24
Peak memory 205136 kb
Host smart-16d19957-6a4b-4d22-8125-8f6834a00ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904849052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3904849052
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.3486380986
Short name T126
Test name
Test status
Simulation time 4706800536 ps
CPU time 9.23 seconds
Started Jul 13 04:45:43 PM PDT 24
Finished Jul 13 04:45:53 PM PDT 24
Peak memory 213632 kb
Host smart-7b98c76c-d997-4f51-8fe6-c4bc06e05c6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486380986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3486380986
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2424193179
Short name T268
Test name
Test status
Simulation time 75227055 ps
CPU time 0.7 seconds
Started Jul 13 04:45:12 PM PDT 24
Finished Jul 13 04:45:14 PM PDT 24
Peak memory 205132 kb
Host smart-484bd8ea-f6ed-483c-b694-730641942d89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424193179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2424193179
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2065547699
Short name T72
Test name
Test status
Simulation time 5222439228 ps
CPU time 9.28 seconds
Started Jul 13 04:45:02 PM PDT 24
Finished Jul 13 04:45:13 PM PDT 24
Peak memory 221924 kb
Host smart-43e82631-bb99-4752-b170-97a4f90dc514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065547699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2065547699
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3787316495
Short name T207
Test name
Test status
Simulation time 6215377575 ps
CPU time 17.09 seconds
Started Jul 13 04:45:13 PM PDT 24
Finished Jul 13 04:45:31 PM PDT 24
Peak memory 213732 kb
Host smart-6096e073-1e13-4e57-ba45-5b65e1ac3b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787316495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3787316495
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.442781269
Short name T245
Test name
Test status
Simulation time 1057151959 ps
CPU time 3.83 seconds
Started Jul 13 04:45:13 PM PDT 24
Finished Jul 13 04:45:17 PM PDT 24
Peak memory 205428 kb
Host smart-fa8394d1-00b8-4e84-af5a-a6b510a02e03
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=442781269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.442781269
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.399622342
Short name T8
Test name
Test status
Simulation time 160543591 ps
CPU time 0.73 seconds
Started Jul 13 04:45:02 PM PDT 24
Finished Jul 13 04:45:05 PM PDT 24
Peak memory 205008 kb
Host smart-a8a25fb3-b5e9-4f2b-95bf-e2c289fa3f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399622342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.399622342
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.927229924
Short name T240
Test name
Test status
Simulation time 2861961223 ps
CPU time 4.99 seconds
Started Jul 13 04:45:02 PM PDT 24
Finished Jul 13 04:45:08 PM PDT 24
Peak memory 213700 kb
Host smart-91d9cca4-d8f9-4d50-abcf-09a3ab5b47f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927229924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.927229924
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.4275221404
Short name T52
Test name
Test status
Simulation time 590496635 ps
CPU time 1.76 seconds
Started Jul 13 04:45:03 PM PDT 24
Finished Jul 13 04:45:06 PM PDT 24
Peak memory 228852 kb
Host smart-a3339910-2fc1-4df1-8fb3-9aaac35e15e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275221404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.4275221404
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.2300669168
Short name T134
Test name
Test status
Simulation time 7242510123 ps
CPU time 3.54 seconds
Started Jul 13 04:45:04 PM PDT 24
Finished Jul 13 04:45:09 PM PDT 24
Peak memory 205244 kb
Host smart-6edcf00e-0615-4170-bd0e-8c594a0e67c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300669168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2300669168
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2293003613
Short name T223
Test name
Test status
Simulation time 54596547 ps
CPU time 0.78 seconds
Started Jul 13 04:45:43 PM PDT 24
Finished Jul 13 04:45:45 PM PDT 24
Peak memory 205064 kb
Host smart-4b85fcd2-1519-408d-ab4d-b7a5007680f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293003613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2293003613
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.1115713754
Short name T147
Test name
Test status
Simulation time 12108479146 ps
CPU time 6.45 seconds
Started Jul 13 04:45:42 PM PDT 24
Finished Jul 13 04:45:49 PM PDT 24
Peak memory 213444 kb
Host smart-59e11956-6653-4f91-8108-82bf88421345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115713754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1115713754
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1749907993
Short name T209
Test name
Test status
Simulation time 60411949 ps
CPU time 0.87 seconds
Started Jul 13 04:45:44 PM PDT 24
Finished Jul 13 04:45:47 PM PDT 24
Peak memory 204996 kb
Host smart-8e63652b-e4cf-4bde-b9db-4a6c2d04b0f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749907993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1749907993
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1636587375
Short name T48
Test name
Test status
Simulation time 33057550 ps
CPU time 0.78 seconds
Started Jul 13 04:45:41 PM PDT 24
Finished Jul 13 04:45:43 PM PDT 24
Peak memory 205000 kb
Host smart-e12219f7-33f5-45f7-8743-1f7b15020186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636587375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1636587375
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.3349909112
Short name T139
Test name
Test status
Simulation time 4014344233 ps
CPU time 3.19 seconds
Started Jul 13 04:45:44 PM PDT 24
Finished Jul 13 04:45:49 PM PDT 24
Peak memory 205272 kb
Host smart-3ae67b1f-74b3-4db3-ab10-98963d88114f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349909112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3349909112
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.1377527410
Short name T278
Test name
Test status
Simulation time 57614103 ps
CPU time 0.72 seconds
Started Jul 13 04:45:44 PM PDT 24
Finished Jul 13 04:45:46 PM PDT 24
Peak memory 204996 kb
Host smart-c70f3c6d-c933-497e-8b92-6d41f21630ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377527410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.1377527410
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2225157225
Short name T200
Test name
Test status
Simulation time 83063504 ps
CPU time 0.77 seconds
Started Jul 13 04:45:41 PM PDT 24
Finished Jul 13 04:45:43 PM PDT 24
Peak memory 205032 kb
Host smart-7771a70f-c814-4f45-a38c-5c4edf254f59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225157225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2225157225
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3054165076
Short name T204
Test name
Test status
Simulation time 76894729 ps
CPU time 0.77 seconds
Started Jul 13 04:45:44 PM PDT 24
Finished Jul 13 04:45:46 PM PDT 24
Peak memory 205296 kb
Host smart-299dfd88-289d-402b-9f1f-d59519add7fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054165076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3054165076
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1300104917
Short name T211
Test name
Test status
Simulation time 150938792 ps
CPU time 0.82 seconds
Started Jul 13 04:45:44 PM PDT 24
Finished Jul 13 04:45:47 PM PDT 24
Peak memory 205132 kb
Host smart-2d03870b-c819-4cec-bed8-a2120f86ca50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300104917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1300104917
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.3902539348
Short name T143
Test name
Test status
Simulation time 9911677107 ps
CPU time 7.7 seconds
Started Jul 13 04:45:43 PM PDT 24
Finished Jul 13 04:45:52 PM PDT 24
Peak memory 205232 kb
Host smart-902610d5-e0b3-4e96-8a03-fa6cba12c9b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902539348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3902539348
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2468475371
Short name T220
Test name
Test status
Simulation time 68577856 ps
CPU time 0.8 seconds
Started Jul 13 04:45:45 PM PDT 24
Finished Jul 13 04:45:48 PM PDT 24
Peak memory 205020 kb
Host smart-804e5b51-a6a0-4381-9663-9d1a0a17c468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468475371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2468475371
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.601669741
Short name T127
Test name
Test status
Simulation time 3444837712 ps
CPU time 10.86 seconds
Started Jul 13 04:45:43 PM PDT 24
Finished Jul 13 04:45:55 PM PDT 24
Peak memory 213540 kb
Host smart-b5cd2899-7f70-4934-bf41-0b08db10fa95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601669741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.601669741
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2906516541
Short name T1
Test name
Test status
Simulation time 72210459 ps
CPU time 0.91 seconds
Started Jul 13 04:45:42 PM PDT 24
Finished Jul 13 04:45:44 PM PDT 24
Peak memory 205016 kb
Host smart-7eb37794-c9fd-4c39-999e-57029f13e341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906516541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2906516541
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.769101514
Short name T21
Test name
Test status
Simulation time 8255032399 ps
CPU time 10.26 seconds
Started Jul 13 04:45:43 PM PDT 24
Finished Jul 13 04:45:55 PM PDT 24
Peak memory 205252 kb
Host smart-6e26bca1-82af-4fa5-9c92-8f8a7c6c441e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769101514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.769101514
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2945902372
Short name T76
Test name
Test status
Simulation time 73316051 ps
CPU time 0.71 seconds
Started Jul 13 04:45:41 PM PDT 24
Finished Jul 13 04:45:43 PM PDT 24
Peak memory 205096 kb
Host smart-28426fa9-ffdd-4ddc-8057-a42690fd95ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945902372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2945902372
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3732900772
Short name T252
Test name
Test status
Simulation time 63444591 ps
CPU time 0.9 seconds
Started Jul 13 04:45:00 PM PDT 24
Finished Jul 13 04:45:02 PM PDT 24
Peak memory 205068 kb
Host smart-b99a6183-acfe-49ba-8311-dbfb020b5cdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732900772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3732900772
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.82203699
Short name T280
Test name
Test status
Simulation time 11137537395 ps
CPU time 11.91 seconds
Started Jul 13 04:45:04 PM PDT 24
Finished Jul 13 04:45:17 PM PDT 24
Peak memory 213564 kb
Host smart-bec77429-ffbd-4c4a-acd3-7c3b01a18cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82203699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.82203699
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2645053747
Short name T241
Test name
Test status
Simulation time 3952304917 ps
CPU time 12.22 seconds
Started Jul 13 04:45:01 PM PDT 24
Finished Jul 13 04:45:14 PM PDT 24
Peak memory 221708 kb
Host smart-93241047-7aee-40e2-a001-1ac848ea3cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645053747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2645053747
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1461367546
Short name T257
Test name
Test status
Simulation time 1440343935 ps
CPU time 5.16 seconds
Started Jul 13 04:45:03 PM PDT 24
Finished Jul 13 04:45:10 PM PDT 24
Peak memory 205480 kb
Host smart-dc9ac4f8-0175-4d26-8277-92d6a91b028f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1461367546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1461367546
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3865419160
Short name T282
Test name
Test status
Simulation time 739699626 ps
CPU time 2.75 seconds
Started Jul 13 04:45:03 PM PDT 24
Finished Jul 13 04:45:07 PM PDT 24
Peak memory 205004 kb
Host smart-e61400a7-4674-4aef-9c32-d0bf9a69cfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865419160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3865419160
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.675862541
Short name T74
Test name
Test status
Simulation time 1270871330 ps
CPU time 4.14 seconds
Started Jul 13 04:45:00 PM PDT 24
Finished Jul 13 04:45:05 PM PDT 24
Peak memory 228832 kb
Host smart-9a0bc3d7-be67-44b1-bcb1-e2d1556770f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675862541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.675862541
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.1543050178
Short name T27
Test name
Test status
Simulation time 11177660579 ps
CPU time 28.42 seconds
Started Jul 13 04:45:12 PM PDT 24
Finished Jul 13 04:45:42 PM PDT 24
Peak memory 215956 kb
Host smart-c0f17e98-180f-4327-b085-0a2f32d59d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543050178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.1543050178
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3354103185
Short name T216
Test name
Test status
Simulation time 153800042 ps
CPU time 0.92 seconds
Started Jul 13 04:45:42 PM PDT 24
Finished Jul 13 04:45:44 PM PDT 24
Peak memory 205024 kb
Host smart-09b6d8f2-2e4c-45ac-a92d-f1936e335813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354103185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3354103185
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1894764766
Short name T232
Test name
Test status
Simulation time 96201114 ps
CPU time 0.79 seconds
Started Jul 13 04:45:45 PM PDT 24
Finished Jul 13 04:45:48 PM PDT 24
Peak memory 205140 kb
Host smart-a9fd123a-fe13-450a-a45e-63d6c5a0db70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894764766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1894764766
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3292737232
Short name T195
Test name
Test status
Simulation time 66919524 ps
CPU time 0.8 seconds
Started Jul 13 04:45:43 PM PDT 24
Finished Jul 13 04:45:45 PM PDT 24
Peak memory 205116 kb
Host smart-5425dc18-30b4-44b8-a38f-ef4cd8fe8472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292737232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3292737232
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1076174478
Short name T197
Test name
Test status
Simulation time 156262663 ps
CPU time 0.78 seconds
Started Jul 13 04:45:44 PM PDT 24
Finished Jul 13 04:45:47 PM PDT 24
Peak memory 205096 kb
Host smart-f1c18ffd-4c61-4f74-b02a-c46ef52b5bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076174478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1076174478
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.1723142095
Short name T28
Test name
Test status
Simulation time 2686819053 ps
CPU time 5.9 seconds
Started Jul 13 04:45:47 PM PDT 24
Finished Jul 13 04:45:54 PM PDT 24
Peak memory 205292 kb
Host smart-faeeb1e0-d681-474c-99c6-e20f4d068756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723142095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.1723142095
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.4040902675
Short name T218
Test name
Test status
Simulation time 79754312 ps
CPU time 0.81 seconds
Started Jul 13 04:45:42 PM PDT 24
Finished Jul 13 04:45:44 PM PDT 24
Peak memory 204996 kb
Host smart-fd9febca-275c-41b2-9f7b-b0123cda7e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040902675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.4040902675
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1265861346
Short name T191
Test name
Test status
Simulation time 82086296 ps
CPU time 0.91 seconds
Started Jul 13 04:45:49 PM PDT 24
Finished Jul 13 04:45:50 PM PDT 24
Peak memory 205012 kb
Host smart-a3f46042-1805-41fc-9824-c446f345fcde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265861346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1265861346
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3579499878
Short name T71
Test name
Test status
Simulation time 69594373 ps
CPU time 0.77 seconds
Started Jul 13 04:45:45 PM PDT 24
Finished Jul 13 04:45:47 PM PDT 24
Peak memory 204972 kb
Host smart-d2f8c85b-abd7-430d-a85c-dbf3a6e0df42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579499878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3579499878
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.883646878
Short name T217
Test name
Test status
Simulation time 69523479 ps
CPU time 0.69 seconds
Started Jul 13 04:45:45 PM PDT 24
Finished Jul 13 04:45:47 PM PDT 24
Peak memory 205100 kb
Host smart-a0e536b4-634c-4c1f-9e86-5539a8f83ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883646878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.883646878
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.3720208973
Short name T135
Test name
Test status
Simulation time 9904946982 ps
CPU time 28.93 seconds
Started Jul 13 04:45:42 PM PDT 24
Finished Jul 13 04:46:12 PM PDT 24
Peak memory 213480 kb
Host smart-2c74e4bd-d7f0-48c4-ae32-3f4dead355c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720208973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.3720208973
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1613509464
Short name T230
Test name
Test status
Simulation time 205004860 ps
CPU time 0.76 seconds
Started Jul 13 04:45:44 PM PDT 24
Finished Jul 13 04:45:46 PM PDT 24
Peak memory 204996 kb
Host smart-3e2d80f7-8105-4ea8-9a21-8246780c1b29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613509464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1613509464
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.3679857682
Short name T137
Test name
Test status
Simulation time 4895165070 ps
CPU time 3.14 seconds
Started Jul 13 04:45:47 PM PDT 24
Finished Jul 13 04:45:51 PM PDT 24
Peak memory 205392 kb
Host smart-78142f1a-acd4-4c66-ac14-c2450f317b3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679857682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3679857682
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.495879578
Short name T203
Test name
Test status
Simulation time 67918690 ps
CPU time 0.74 seconds
Started Jul 13 04:45:46 PM PDT 24
Finished Jul 13 04:45:48 PM PDT 24
Peak memory 205032 kb
Host smart-85f138df-9b13-409a-8200-d92436bcd5c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495879578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.495879578
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2020649228
Short name T265
Test name
Test status
Simulation time 95319946 ps
CPU time 0.87 seconds
Started Jul 13 04:45:05 PM PDT 24
Finished Jul 13 04:45:07 PM PDT 24
Peak memory 205016 kb
Host smart-29f5300b-482e-4a28-b404-00cf585872e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020649228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2020649228
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2994231133
Short name T162
Test name
Test status
Simulation time 37706589300 ps
CPU time 49.15 seconds
Started Jul 13 04:45:12 PM PDT 24
Finished Jul 13 04:46:02 PM PDT 24
Peak memory 213676 kb
Host smart-f54e1fc1-9fe7-4576-bf35-0df8f7aa0ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994231133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2994231133
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3139951638
Short name T267
Test name
Test status
Simulation time 1374146372 ps
CPU time 2.94 seconds
Started Jul 13 04:45:04 PM PDT 24
Finished Jul 13 04:45:09 PM PDT 24
Peak memory 213508 kb
Host smart-c7f10af4-62ea-4f77-80c5-ceb8c59b77c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139951638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3139951638
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1333981553
Short name T273
Test name
Test status
Simulation time 1321261427 ps
CPU time 4.67 seconds
Started Jul 13 04:45:12 PM PDT 24
Finished Jul 13 04:45:18 PM PDT 24
Peak memory 205484 kb
Host smart-9e21f951-b67e-40c8-8349-690759dc3a1a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1333981553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1333981553
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1246985692
Short name T212
Test name
Test status
Simulation time 43637054 ps
CPU time 0.74 seconds
Started Jul 13 04:45:15 PM PDT 24
Finished Jul 13 04:45:16 PM PDT 24
Peak memory 205004 kb
Host smart-d196d7f2-3bc2-4441-9f41-aba38384faf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246985692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1246985692
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2858213261
Short name T248
Test name
Test status
Simulation time 1868182303 ps
CPU time 2.49 seconds
Started Jul 13 04:45:11 PM PDT 24
Finished Jul 13 04:45:14 PM PDT 24
Peak memory 213960 kb
Host smart-6e616554-2c53-4810-b62c-73c5984b3a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858213261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2858213261
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.4007383320
Short name T63
Test name
Test status
Simulation time 1461182733 ps
CPU time 5 seconds
Started Jul 13 04:45:12 PM PDT 24
Finished Jul 13 04:45:18 PM PDT 24
Peak memory 205440 kb
Host smart-4c244084-3c40-46c6-9cfb-21fbc38de7c1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4007383320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.4007383320
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.169679348
Short name T291
Test name
Test status
Simulation time 1853207199 ps
CPU time 6.49 seconds
Started Jul 13 04:45:04 PM PDT 24
Finished Jul 13 04:45:12 PM PDT 24
Peak memory 205340 kb
Host smart-b6bb5a91-a74b-4abe-8f4b-bbecf86c5737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169679348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.169679348
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.4071072865
Short name T125
Test name
Test status
Simulation time 9072789987 ps
CPU time 7.83 seconds
Started Jul 13 04:45:11 PM PDT 24
Finished Jul 13 04:45:20 PM PDT 24
Peak memory 213580 kb
Host smart-1e77ff64-79be-49ff-889c-bc1f67a69ffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071072865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.4071072865
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1735445242
Short name T210
Test name
Test status
Simulation time 149628918 ps
CPU time 0.84 seconds
Started Jul 13 04:45:12 PM PDT 24
Finished Jul 13 04:45:14 PM PDT 24
Peak memory 205036 kb
Host smart-b194eb85-7f52-45a3-9355-1b8559fea0c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735445242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1735445242
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.3570549062
Short name T266
Test name
Test status
Simulation time 4351685458 ps
CPU time 5.1 seconds
Started Jul 13 04:45:15 PM PDT 24
Finished Jul 13 04:45:20 PM PDT 24
Peak memory 213604 kb
Host smart-3478264c-3948-4a4a-98b0-14ce105c3d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570549062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.3570549062
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3458905462
Short name T228
Test name
Test status
Simulation time 5653801319 ps
CPU time 9.53 seconds
Started Jul 13 04:45:13 PM PDT 24
Finished Jul 13 04:45:23 PM PDT 24
Peak memory 214908 kb
Host smart-3c27acda-e3a8-4d32-a0be-e76358504259
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458905462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3458905462
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1816247790
Short name T276
Test name
Test status
Simulation time 5259649317 ps
CPU time 3.1 seconds
Started Jul 13 04:45:11 PM PDT 24
Finished Jul 13 04:45:15 PM PDT 24
Peak memory 214932 kb
Host smart-de62fc83-4abc-4180-9327-ef4c990ef528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816247790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1816247790
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.345869100
Short name T129
Test name
Test status
Simulation time 4907090354 ps
CPU time 6.15 seconds
Started Jul 13 04:45:11 PM PDT 24
Finished Jul 13 04:45:18 PM PDT 24
Peak memory 205252 kb
Host smart-e4ec02b6-a116-4177-9ba9-91a4a5c6090a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345869100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.345869100
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2243056159
Short name T214
Test name
Test status
Simulation time 77768229 ps
CPU time 0.77 seconds
Started Jul 13 04:45:12 PM PDT 24
Finished Jul 13 04:45:14 PM PDT 24
Peak memory 205008 kb
Host smart-773ebe79-870a-4962-8341-0b27c1ca3db3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243056159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2243056159
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1246218381
Short name T259
Test name
Test status
Simulation time 32620656181 ps
CPU time 15.96 seconds
Started Jul 13 04:45:11 PM PDT 24
Finished Jul 13 04:45:28 PM PDT 24
Peak memory 205388 kb
Host smart-794c793a-b43d-4823-a3e4-54aab5b4d003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246218381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1246218381
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3766034369
Short name T194
Test name
Test status
Simulation time 15945892081 ps
CPU time 9.26 seconds
Started Jul 13 04:45:10 PM PDT 24
Finished Jul 13 04:45:20 PM PDT 24
Peak memory 213548 kb
Host smart-de7521c0-d2cd-4b8e-bd2b-eae6b3c17cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766034369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3766034369
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2767500384
Short name T262
Test name
Test status
Simulation time 6977179826 ps
CPU time 2.71 seconds
Started Jul 13 04:45:11 PM PDT 24
Finished Jul 13 04:45:14 PM PDT 24
Peak memory 205504 kb
Host smart-745e2d4c-128a-427c-a3ed-27f519db3436
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2767500384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2767500384
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.746890753
Short name T261
Test name
Test status
Simulation time 2869191873 ps
CPU time 6.42 seconds
Started Jul 13 04:45:14 PM PDT 24
Finished Jul 13 04:45:21 PM PDT 24
Peak memory 205448 kb
Host smart-b5f207e6-ac1d-4f38-bc7b-34b4d84fbf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746890753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.746890753
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.52139750
Short name T140
Test name
Test status
Simulation time 8750989020 ps
CPU time 10.76 seconds
Started Jul 13 04:45:11 PM PDT 24
Finished Jul 13 04:45:22 PM PDT 24
Peak memory 213392 kb
Host smart-bca7cc4c-b0a6-4a90-b426-574bfd594735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52139750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.52139750
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2046643131
Short name T120
Test name
Test status
Simulation time 286417338 ps
CPU time 0.78 seconds
Started Jul 13 04:45:21 PM PDT 24
Finished Jul 13 04:45:22 PM PDT 24
Peak memory 205008 kb
Host smart-55ff32e3-db9b-46d3-bc2e-1618f3e28e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046643131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2046643131
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3130229239
Short name T192
Test name
Test status
Simulation time 14454955674 ps
CPU time 45.38 seconds
Started Jul 13 04:45:24 PM PDT 24
Finished Jul 13 04:46:10 PM PDT 24
Peak memory 217528 kb
Host smart-4ccbba5f-0d19-4206-860e-853539e64719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130229239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3130229239
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3118572016
Short name T32
Test name
Test status
Simulation time 5078712335 ps
CPU time 4.49 seconds
Started Jul 13 04:45:22 PM PDT 24
Finished Jul 13 04:45:28 PM PDT 24
Peak memory 213644 kb
Host smart-a2d92228-90b9-449e-8674-4b6d0dc8555a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118572016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3118572016
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.4130137836
Short name T246
Test name
Test status
Simulation time 1460564099 ps
CPU time 2.08 seconds
Started Jul 13 04:45:22 PM PDT 24
Finished Jul 13 04:45:25 PM PDT 24
Peak memory 213620 kb
Host smart-5f4df8a7-dc3f-4d6b-b91b-b48d496218e1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4130137836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.4130137836
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest
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