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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
82.86 95.77 81.52 89.91 75.00 86.50 98.32 52.97


Total test records in report: 429
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T97 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4107671588 Jul 16 07:27:30 PM PDT 24 Jul 16 07:27:54 PM PDT 24 195164101 ps
T107 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.968483851 Jul 16 07:27:41 PM PDT 24 Jul 16 07:27:57 PM PDT 24 149200007 ps
T294 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3102466198 Jul 16 07:27:03 PM PDT 24 Jul 16 07:29:33 PM PDT 24 43004488256 ps
T175 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3721935967 Jul 16 07:27:40 PM PDT 24 Jul 16 07:28:15 PM PDT 24 6405000121 ps
T295 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2610728533 Jul 16 07:27:38 PM PDT 24 Jul 16 07:27:57 PM PDT 24 3048623084 ps
T108 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1154272516 Jul 16 07:27:42 PM PDT 24 Jul 16 07:28:00 PM PDT 24 342117677 ps
T109 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.607611875 Jul 16 07:27:03 PM PDT 24 Jul 16 07:28:45 PM PDT 24 8031081256 ps
T296 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.689708501 Jul 16 07:27:44 PM PDT 24 Jul 16 07:27:58 PM PDT 24 384096841 ps
T114 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3876301680 Jul 16 07:26:51 PM PDT 24 Jul 16 07:27:30 PM PDT 24 325351326 ps
T297 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2912986553 Jul 16 07:27:13 PM PDT 24 Jul 16 07:27:42 PM PDT 24 142178961 ps
T298 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.566608725 Jul 16 07:27:27 PM PDT 24 Jul 16 07:27:48 PM PDT 24 291471028 ps
T143 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4002016428 Jul 16 07:27:45 PM PDT 24 Jul 16 07:28:21 PM PDT 24 4669673304 ps
T299 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.870980749 Jul 16 07:27:02 PM PDT 24 Jul 16 07:27:32 PM PDT 24 132191484 ps
T300 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2662216647 Jul 16 07:27:46 PM PDT 24 Jul 16 07:28:01 PM PDT 24 225433599 ps
T144 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2726378622 Jul 16 07:27:39 PM PDT 24 Jul 16 07:27:57 PM PDT 24 207991058 ps
T121 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1907997087 Jul 16 07:26:52 PM PDT 24 Jul 16 07:28:47 PM PDT 24 19987346531 ps
T301 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2763397104 Jul 16 07:27:42 PM PDT 24 Jul 16 07:27:59 PM PDT 24 3050807892 ps
T302 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2494345778 Jul 16 07:27:42 PM PDT 24 Jul 16 07:27:59 PM PDT 24 792471351 ps
T303 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2906084735 Jul 16 07:27:12 PM PDT 24 Jul 16 07:27:41 PM PDT 24 1956504136 ps
T304 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1049607804 Jul 16 07:26:52 PM PDT 24 Jul 16 07:27:27 PM PDT 24 97791652 ps
T305 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3379473185 Jul 16 07:27:01 PM PDT 24 Jul 16 07:27:33 PM PDT 24 327820794 ps
T122 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.427305888 Jul 16 07:27:03 PM PDT 24 Jul 16 07:28:01 PM PDT 24 2946461438 ps
T306 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4177479106 Jul 16 07:27:05 PM PDT 24 Jul 16 07:27:41 PM PDT 24 7208300679 ps
T123 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4075803779 Jul 16 07:27:40 PM PDT 24 Jul 16 07:27:56 PM PDT 24 217183941 ps
T307 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3335795945 Jul 16 07:27:41 PM PDT 24 Jul 16 07:28:20 PM PDT 24 32772944216 ps
T130 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3108480757 Jul 16 07:26:39 PM PDT 24 Jul 16 07:27:51 PM PDT 24 7926693090 ps
T308 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.517000201 Jul 16 07:26:52 PM PDT 24 Jul 16 07:27:39 PM PDT 24 7236310206 ps
T117 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4055882367 Jul 16 07:27:00 PM PDT 24 Jul 16 07:27:43 PM PDT 24 7315762347 ps
T309 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.649977220 Jul 16 07:27:13 PM PDT 24 Jul 16 07:27:40 PM PDT 24 142751888 ps
T310 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3258840965 Jul 16 07:27:40 PM PDT 24 Jul 16 07:27:57 PM PDT 24 389281061 ps
T311 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1109499809 Jul 16 07:27:00 PM PDT 24 Jul 16 07:28:35 PM PDT 24 22883795068 ps
T136 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4183047866 Jul 16 07:27:05 PM PDT 24 Jul 16 07:27:39 PM PDT 24 332890120 ps
T312 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3793556193 Jul 16 07:27:42 PM PDT 24 Jul 16 07:27:58 PM PDT 24 177419287 ps
T137 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4054113449 Jul 16 07:27:31 PM PDT 24 Jul 16 07:27:53 PM PDT 24 741337642 ps
T131 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3245345862 Jul 16 07:27:06 PM PDT 24 Jul 16 07:27:38 PM PDT 24 303547811 ps
T313 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2435413250 Jul 16 07:27:41 PM PDT 24 Jul 16 07:27:58 PM PDT 24 2261990239 ps
T172 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3871238989 Jul 16 07:26:52 PM PDT 24 Jul 16 07:27:46 PM PDT 24 2122977723 ps
T314 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3973166638 Jul 16 07:27:15 PM PDT 24 Jul 16 07:28:15 PM PDT 24 13443826842 ps
T315 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1784297919 Jul 16 07:27:43 PM PDT 24 Jul 16 07:28:00 PM PDT 24 479326286 ps
T124 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3220680671 Jul 16 07:27:40 PM PDT 24 Jul 16 07:27:58 PM PDT 24 119985157 ps
T316 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.56375131 Jul 16 07:27:29 PM PDT 24 Jul 16 07:28:02 PM PDT 24 4890789811 ps
T317 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3022385470 Jul 16 07:27:41 PM PDT 24 Jul 16 07:28:00 PM PDT 24 121435394 ps
T318 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.662487 Jul 16 07:26:52 PM PDT 24 Jul 16 07:27:25 PM PDT 24 27738911 ps
T118 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1061992556 Jul 16 07:27:02 PM PDT 24 Jul 16 07:27:50 PM PDT 24 12227962634 ps
T125 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2254967827 Jul 16 07:27:42 PM PDT 24 Jul 16 07:27:59 PM PDT 24 94576398 ps
T180 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.320374991 Jul 16 07:27:05 PM PDT 24 Jul 16 07:28:52 PM PDT 24 63045016087 ps
T319 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3052032149 Jul 16 07:27:15 PM PDT 24 Jul 16 07:27:41 PM PDT 24 367731690 ps
T320 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2216949191 Jul 16 07:27:07 PM PDT 24 Jul 16 07:27:40 PM PDT 24 206754849 ps
T321 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1807297875 Jul 16 07:26:49 PM PDT 24 Jul 16 07:27:25 PM PDT 24 503403586 ps
T132 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3196466747 Jul 16 07:27:01 PM PDT 24 Jul 16 07:27:33 PM PDT 24 160626832 ps
T169 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3841319503 Jul 16 07:27:43 PM PDT 24 Jul 16 07:28:03 PM PDT 24 347174092 ps
T322 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.115892373 Jul 16 07:27:14 PM PDT 24 Jul 16 07:27:48 PM PDT 24 7373563418 ps
T126 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3560985054 Jul 16 07:27:26 PM PDT 24 Jul 16 07:27:50 PM PDT 24 306781810 ps
T323 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2680734908 Jul 16 07:26:51 PM PDT 24 Jul 16 07:27:32 PM PDT 24 2529013705 ps
T324 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1578675196 Jul 16 07:26:50 PM PDT 24 Jul 16 07:28:48 PM PDT 24 57327408593 ps
T138 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2236307594 Jul 16 07:27:41 PM PDT 24 Jul 16 07:28:00 PM PDT 24 1553157266 ps
T176 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3233449520 Jul 16 07:27:40 PM PDT 24 Jul 16 07:28:10 PM PDT 24 2828115337 ps
T325 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.801602675 Jul 16 07:27:28 PM PDT 24 Jul 16 07:27:51 PM PDT 24 204809801 ps
T326 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3566515730 Jul 16 07:27:39 PM PDT 24 Jul 16 07:28:01 PM PDT 24 5623009878 ps
T327 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4218604211 Jul 16 07:27:26 PM PDT 24 Jul 16 07:27:50 PM PDT 24 3023400004 ps
T181 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2821860358 Jul 16 07:26:51 PM PDT 24 Jul 16 07:27:56 PM PDT 24 76945402522 ps
T127 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2140966350 Jul 16 07:27:44 PM PDT 24 Jul 16 07:28:02 PM PDT 24 1066953845 ps
T328 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.714706561 Jul 16 07:27:13 PM PDT 24 Jul 16 07:27:42 PM PDT 24 524543108 ps
T329 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1404931722 Jul 16 07:27:00 PM PDT 24 Jul 16 07:27:30 PM PDT 24 223942494 ps
T330 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.660691027 Jul 16 07:27:27 PM PDT 24 Jul 16 07:27:53 PM PDT 24 1857866076 ps
T139 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.884294671 Jul 16 07:27:13 PM PDT 24 Jul 16 07:27:43 PM PDT 24 304423728 ps
T178 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.751347097 Jul 16 07:27:13 PM PDT 24 Jul 16 07:27:56 PM PDT 24 1390317845 ps
T331 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3046371254 Jul 16 07:27:27 PM PDT 24 Jul 16 07:27:48 PM PDT 24 358761118 ps
T332 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.53490236 Jul 16 07:27:31 PM PDT 24 Jul 16 07:27:50 PM PDT 24 2080528681 ps
T333 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1237245031 Jul 16 07:27:26 PM PDT 24 Jul 16 07:27:49 PM PDT 24 2185086302 ps
T334 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3680934379 Jul 16 07:27:03 PM PDT 24 Jul 16 07:27:35 PM PDT 24 1739146898 ps
T335 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3086421308 Jul 16 07:27:02 PM PDT 24 Jul 16 07:27:33 PM PDT 24 87425548 ps
T133 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2743548793 Jul 16 07:27:44 PM PDT 24 Jul 16 07:27:59 PM PDT 24 99832192 ps
T336 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.757613977 Jul 16 07:27:02 PM PDT 24 Jul 16 07:27:34 PM PDT 24 486737524 ps
T337 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.350976158 Jul 16 07:26:49 PM PDT 24 Jul 16 07:27:28 PM PDT 24 310576260 ps
T338 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2847624681 Jul 16 07:27:04 PM PDT 24 Jul 16 07:27:37 PM PDT 24 157891134 ps
T339 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2688109074 Jul 16 07:27:25 PM PDT 24 Jul 16 07:27:48 PM PDT 24 126401278 ps
T340 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1076103443 Jul 16 07:27:07 PM PDT 24 Jul 16 07:27:40 PM PDT 24 676184620 ps
T341 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2292110223 Jul 16 07:26:52 PM PDT 24 Jul 16 07:28:31 PM PDT 24 24409832675 ps
T342 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1866078191 Jul 16 07:27:26 PM PDT 24 Jul 16 07:27:56 PM PDT 24 1172909896 ps
T128 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.463744453 Jul 16 07:27:02 PM PDT 24 Jul 16 07:27:38 PM PDT 24 522451607 ps
T173 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3842590817 Jul 16 07:27:13 PM PDT 24 Jul 16 07:28:04 PM PDT 24 2922150065 ps
T343 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4205201261 Jul 16 07:27:25 PM PDT 24 Jul 16 07:30:13 PM PDT 24 50613150516 ps
T344 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3451618899 Jul 16 07:27:02 PM PDT 24 Jul 16 07:27:52 PM PDT 24 23353355577 ps
T345 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1505276379 Jul 16 07:27:13 PM PDT 24 Jul 16 07:27:41 PM PDT 24 197673076 ps
T346 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.920151128 Jul 16 07:27:02 PM PDT 24 Jul 16 07:27:33 PM PDT 24 833334757 ps
T347 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4120279348 Jul 16 07:27:25 PM PDT 24 Jul 16 07:27:50 PM PDT 24 308974824 ps
T348 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2993862475 Jul 16 07:27:38 PM PDT 24 Jul 16 07:28:12 PM PDT 24 4339858509 ps
T349 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1276566518 Jul 16 07:27:38 PM PDT 24 Jul 16 07:27:56 PM PDT 24 342106939 ps
T350 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1601926490 Jul 16 07:27:26 PM PDT 24 Jul 16 07:27:50 PM PDT 24 184609762 ps
T351 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.334023181 Jul 16 07:27:42 PM PDT 24 Jul 16 07:27:57 PM PDT 24 363676907 ps
T352 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3709458015 Jul 16 07:26:47 PM PDT 24 Jul 16 07:27:23 PM PDT 24 302935259 ps
T134 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2845490100 Jul 16 07:27:13 PM PDT 24 Jul 16 07:28:31 PM PDT 24 1452652164 ps
T353 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.345782718 Jul 16 07:27:26 PM PDT 24 Jul 16 07:27:47 PM PDT 24 99231162 ps
T354 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1150593390 Jul 16 07:27:42 PM PDT 24 Jul 16 07:28:00 PM PDT 24 217149047 ps
T355 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3661036595 Jul 16 07:27:31 PM PDT 24 Jul 16 07:28:11 PM PDT 24 8208617142 ps
T356 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.300655164 Jul 16 07:27:27 PM PDT 24 Jul 16 07:27:54 PM PDT 24 490614827 ps
T135 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3554437867 Jul 16 07:26:49 PM PDT 24 Jul 16 07:27:27 PM PDT 24 489406040 ps
T357 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.219933542 Jul 16 07:26:50 PM PDT 24 Jul 16 07:27:49 PM PDT 24 15179193635 ps
T358 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3826738792 Jul 16 07:27:24 PM PDT 24 Jul 16 07:27:45 PM PDT 24 200133072 ps
T359 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.757595588 Jul 16 07:27:26 PM PDT 24 Jul 16 07:27:48 PM PDT 24 693890954 ps
T360 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2188893146 Jul 16 07:27:15 PM PDT 24 Jul 16 07:27:44 PM PDT 24 3772474791 ps
T361 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.580145883 Jul 16 07:27:28 PM PDT 24 Jul 16 07:27:50 PM PDT 24 483699514 ps
T119 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.653094799 Jul 16 07:26:52 PM PDT 24 Jul 16 07:27:38 PM PDT 24 5656159459 ps
T362 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1843830438 Jul 16 07:27:40 PM PDT 24 Jul 16 07:27:54 PM PDT 24 477651713 ps
T363 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1486176364 Jul 16 07:27:02 PM PDT 24 Jul 16 07:28:06 PM PDT 24 12806244139 ps
T364 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.57659544 Jul 16 07:27:45 PM PDT 24 Jul 16 07:28:00 PM PDT 24 236298470 ps
T365 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3731040879 Jul 16 07:27:23 PM PDT 24 Jul 16 07:27:46 PM PDT 24 306581326 ps
T366 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.137510106 Jul 16 07:27:01 PM PDT 24 Jul 16 07:27:58 PM PDT 24 2953603011 ps
T367 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3417383572 Jul 16 07:27:13 PM PDT 24 Jul 16 07:27:40 PM PDT 24 93865543 ps
T368 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3973345974 Jul 16 07:27:42 PM PDT 24 Jul 16 07:28:00 PM PDT 24 984552381 ps
T369 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1325992365 Jul 16 07:27:25 PM PDT 24 Jul 16 07:27:53 PM PDT 24 450714283 ps
T370 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3344312211 Jul 16 07:27:42 PM PDT 24 Jul 16 07:28:04 PM PDT 24 11225852073 ps
T371 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.915218285 Jul 16 07:27:03 PM PDT 24 Jul 16 07:27:36 PM PDT 24 487457417 ps
T372 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.245401659 Jul 16 07:27:44 PM PDT 24 Jul 16 07:28:14 PM PDT 24 2668256906 ps
T373 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.287601245 Jul 16 07:27:25 PM PDT 24 Jul 16 07:27:48 PM PDT 24 478203350 ps
T374 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2582782205 Jul 16 07:27:01 PM PDT 24 Jul 16 07:27:33 PM PDT 24 266844337 ps
T170 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3842635045 Jul 16 07:27:42 PM PDT 24 Jul 16 07:27:59 PM PDT 24 145919149 ps
T375 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3866490399 Jul 16 07:27:40 PM PDT 24 Jul 16 07:29:21 PM PDT 24 34475486267 ps
T376 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4260618173 Jul 16 07:27:03 PM PDT 24 Jul 16 07:28:12 PM PDT 24 9661455671 ps
T174 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2390656273 Jul 16 07:26:51 PM PDT 24 Jul 16 07:27:45 PM PDT 24 6506495784 ps
T377 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2211672963 Jul 16 07:27:28 PM PDT 24 Jul 16 07:27:51 PM PDT 24 1310064157 ps
T378 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3700146172 Jul 16 07:27:26 PM PDT 24 Jul 16 07:27:48 PM PDT 24 226911973 ps
T379 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1187168272 Jul 16 07:27:42 PM PDT 24 Jul 16 07:28:02 PM PDT 24 2118323653 ps
T120 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1978163700 Jul 16 07:26:38 PM PDT 24 Jul 16 07:27:33 PM PDT 24 6664633046 ps
T380 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3987228275 Jul 16 07:26:51 PM PDT 24 Jul 16 07:27:25 PM PDT 24 215324415 ps
T381 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.309245919 Jul 16 07:27:28 PM PDT 24 Jul 16 07:27:51 PM PDT 24 377371813 ps
T179 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1304062015 Jul 16 07:27:40 PM PDT 24 Jul 16 07:28:06 PM PDT 24 2053821783 ps
T382 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2946847541 Jul 16 07:27:30 PM PDT 24 Jul 16 07:27:53 PM PDT 24 3851563688 ps
T383 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1299507521 Jul 16 07:27:41 PM PDT 24 Jul 16 07:27:58 PM PDT 24 210388899 ps
T384 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2265407334 Jul 16 07:27:29 PM PDT 24 Jul 16 07:27:52 PM PDT 24 73919854 ps
T171 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3097154842 Jul 16 07:27:09 PM PDT 24 Jul 16 07:27:40 PM PDT 24 141115308 ps
T385 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1776629860 Jul 16 07:27:42 PM PDT 24 Jul 16 07:28:21 PM PDT 24 6854155052 ps
T386 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3647313454 Jul 16 07:27:29 PM PDT 24 Jul 16 07:28:49 PM PDT 24 35893339420 ps
T387 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2777004375 Jul 16 07:26:50 PM PDT 24 Jul 16 07:27:27 PM PDT 24 102578375 ps
T129 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.640979507 Jul 16 07:27:03 PM PDT 24 Jul 16 07:27:39 PM PDT 24 1146781782 ps
T388 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1668304799 Jul 16 07:26:52 PM PDT 24 Jul 16 07:27:32 PM PDT 24 3247223733 ps
T389 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2960725867 Jul 16 07:27:14 PM PDT 24 Jul 16 07:27:41 PM PDT 24 223021642 ps
T390 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3945371511 Jul 16 07:27:02 PM PDT 24 Jul 16 07:27:33 PM PDT 24 71595248 ps
T391 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.4102080872 Jul 16 07:27:39 PM PDT 24 Jul 16 07:27:57 PM PDT 24 267414176 ps
T392 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.513015196 Jul 16 07:27:41 PM PDT 24 Jul 16 07:27:58 PM PDT 24 127856885 ps
T393 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.842914659 Jul 16 07:26:50 PM PDT 24 Jul 16 07:27:24 PM PDT 24 68561372 ps
T394 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.673894537 Jul 16 07:27:39 PM PDT 24 Jul 16 07:27:54 PM PDT 24 304378924 ps
T395 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1702547313 Jul 16 07:27:40 PM PDT 24 Jul 16 07:28:01 PM PDT 24 532098815 ps
T396 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3321885820 Jul 16 07:27:43 PM PDT 24 Jul 16 07:28:04 PM PDT 24 1810637491 ps
T397 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.732800540 Jul 16 07:27:02 PM PDT 24 Jul 16 07:28:52 PM PDT 24 26472815973 ps
T398 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2910734438 Jul 16 07:27:28 PM PDT 24 Jul 16 07:27:56 PM PDT 24 2040971726 ps
T399 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1318082121 Jul 16 07:27:45 PM PDT 24 Jul 16 07:29:53 PM PDT 24 90992145278 ps
T400 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1804021005 Jul 16 07:27:28 PM PDT 24 Jul 16 07:27:52 PM PDT 24 1732770994 ps
T401 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3260445062 Jul 16 07:27:30 PM PDT 24 Jul 16 07:27:59 PM PDT 24 12309087783 ps
T402 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.783730127 Jul 16 07:27:00 PM PDT 24 Jul 16 07:28:22 PM PDT 24 34873378264 ps
T403 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.371104685 Jul 16 07:26:51 PM PDT 24 Jul 16 07:27:27 PM PDT 24 640328634 ps
T404 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2073150855 Jul 16 07:28:24 PM PDT 24 Jul 16 07:28:41 PM PDT 24 427986432 ps
T405 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2816243430 Jul 16 07:27:40 PM PDT 24 Jul 16 07:27:57 PM PDT 24 2080747779 ps
T406 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.541998854 Jul 16 07:26:51 PM PDT 24 Jul 16 07:27:57 PM PDT 24 35678425000 ps
T407 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2699367500 Jul 16 07:26:49 PM PDT 24 Jul 16 07:27:24 PM PDT 24 430980366 ps
T408 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4140374755 Jul 16 07:27:13 PM PDT 24 Jul 16 07:27:40 PM PDT 24 314237041 ps
T409 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4220795668 Jul 16 07:27:39 PM PDT 24 Jul 16 07:27:54 PM PDT 24 264309079 ps
T410 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.326777012 Jul 16 07:27:43 PM PDT 24 Jul 16 07:27:58 PM PDT 24 152632528 ps
T411 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2054673862 Jul 16 07:27:24 PM PDT 24 Jul 16 07:27:47 PM PDT 24 328445034 ps
T412 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1047931112 Jul 16 07:27:15 PM PDT 24 Jul 16 07:28:56 PM PDT 24 112350024848 ps
T413 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.12193463 Jul 16 07:27:40 PM PDT 24 Jul 16 07:27:57 PM PDT 24 2126080864 ps
T414 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1283761036 Jul 16 07:27:03 PM PDT 24 Jul 16 07:27:35 PM PDT 24 64682423 ps
T415 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.4075965388 Jul 16 07:27:41 PM PDT 24 Jul 16 07:28:01 PM PDT 24 6384750258 ps
T416 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2630013869 Jul 16 07:26:51 PM PDT 24 Jul 16 07:28:03 PM PDT 24 15221606438 ps
T417 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3480390965 Jul 16 07:27:01 PM PDT 24 Jul 16 07:27:34 PM PDT 24 446433560 ps
T418 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1653988924 Jul 16 07:27:02 PM PDT 24 Jul 16 07:27:35 PM PDT 24 2742904126 ps
T419 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3966651632 Jul 16 07:26:49 PM PDT 24 Jul 16 07:28:12 PM PDT 24 17118971915 ps
T420 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4137098750 Jul 16 07:26:52 PM PDT 24 Jul 16 07:28:22 PM PDT 24 59908716539 ps
T421 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3830088261 Jul 16 07:27:26 PM PDT 24 Jul 16 07:27:58 PM PDT 24 1371075994 ps
T422 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2907367932 Jul 16 07:27:05 PM PDT 24 Jul 16 07:29:13 PM PDT 24 91263869241 ps
T423 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2091060663 Jul 16 07:27:13 PM PDT 24 Jul 16 07:27:40 PM PDT 24 231580419 ps
T424 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3991578135 Jul 16 07:26:50 PM PDT 24 Jul 16 07:28:58 PM PDT 24 36325380428 ps
T425 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2063030122 Jul 16 07:27:43 PM PDT 24 Jul 16 07:27:58 PM PDT 24 174469630 ps
T426 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3861687099 Jul 16 07:27:40 PM PDT 24 Jul 16 07:28:22 PM PDT 24 15559690257 ps
T427 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3686515157 Jul 16 07:27:42 PM PDT 24 Jul 16 07:27:57 PM PDT 24 94194225 ps
T177 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1002732470 Jul 16 07:27:01 PM PDT 24 Jul 16 07:27:42 PM PDT 24 1924969932 ps
T428 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1852488724 Jul 16 07:27:01 PM PDT 24 Jul 16 07:27:33 PM PDT 24 1271986485 ps
T429 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.785976201 Jul 16 07:27:02 PM PDT 24 Jul 16 07:27:34 PM PDT 24 1264475516 ps

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2774792200
Short name T1
Test name
Test status
Simulation time 4665409126 ps
CPU time 6.61 seconds
Started Jul 16 07:34:24 PM PDT 24
Finished Jul 16 07:34:46 PM PDT 24
Peak memory 205564 kb
Host smart-98ccd56f-0f67-440e-925d-5b5c0559246d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774792200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2774792200
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.484161297
Short name T32
Test name
Test status
Simulation time 6391979909 ps
CPU time 18.77 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:19 PM PDT 24
Peak memory 213500 kb
Host smart-2d398a74-d4ec-4ee6-a51a-0ab82698e857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484161297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.484161297
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2912861875
Short name T69
Test name
Test status
Simulation time 13745128009 ps
CPU time 14.62 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:27:46 PM PDT 24
Peak memory 220044 kb
Host smart-4a6b7db7-7037-42c9-a459-cedbeff15c27
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912861875 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2912861875
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.2004899246
Short name T28
Test name
Test status
Simulation time 7502593625 ps
CPU time 9.52 seconds
Started Jul 16 07:34:24 PM PDT 24
Finished Jul 16 07:34:49 PM PDT 24
Peak memory 205260 kb
Host smart-c4ae7729-3c24-4fe9-ad54-93bcc3a67bc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004899246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2004899246
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.3807799781
Short name T24
Test name
Test status
Simulation time 6125172778 ps
CPU time 16.07 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:17 PM PDT 24
Peak memory 205468 kb
Host smart-ecef5dbd-bc1a-42e0-9e34-3d631d7b29eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807799781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3807799781
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1944060817
Short name T67
Test name
Test status
Simulation time 3344576713 ps
CPU time 21.5 seconds
Started Jul 16 07:27:26 PM PDT 24
Finished Jul 16 07:28:08 PM PDT 24
Peak memory 213732 kb
Host smart-f8f3f631-2155-46e6-85af-3a557095d837
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944060817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
944060817
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1757986450
Short name T50
Test name
Test status
Simulation time 3982907877 ps
CPU time 12.07 seconds
Started Jul 16 07:35:03 PM PDT 24
Finished Jul 16 07:35:19 PM PDT 24
Peak memory 213656 kb
Host smart-c637c126-59ff-444b-81cc-cc09e221fe5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757986450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1757986450
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1666678815
Short name T93
Test name
Test status
Simulation time 234779367 ps
CPU time 4.84 seconds
Started Jul 16 07:27:45 PM PDT 24
Finished Jul 16 07:28:05 PM PDT 24
Peak memory 213644 kb
Host smart-84082a78-e4e9-481c-9085-949fa90e78cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666678815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1666678815
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.828853803
Short name T110
Test name
Test status
Simulation time 78717902 ps
CPU time 0.77 seconds
Started Jul 16 07:35:00 PM PDT 24
Finished Jul 16 07:35:05 PM PDT 24
Peak memory 205012 kb
Host smart-6fea3f71-7b82-41fb-baf8-6eed97ef0386
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828853803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.828853803
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1183630770
Short name T191
Test name
Test status
Simulation time 11897619408 ps
CPU time 9.47 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:12 PM PDT 24
Peak memory 213620 kb
Host smart-47cbe2ca-629e-41f4-9f27-2dbd86cd7ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183630770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1183630770
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.2929812485
Short name T39
Test name
Test status
Simulation time 72481454 ps
CPU time 0.83 seconds
Started Jul 16 07:33:45 PM PDT 24
Finished Jul 16 07:34:06 PM PDT 24
Peak memory 213284 kb
Host smart-459ec9e8-8c34-4a96-99de-e1c2e177bb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929812485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.2929812485
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2329845426
Short name T19
Test name
Test status
Simulation time 411790019 ps
CPU time 1.84 seconds
Started Jul 16 07:33:46 PM PDT 24
Finished Jul 16 07:34:09 PM PDT 24
Peak memory 205032 kb
Host smart-d7d29602-ad86-4f6f-8d84-bf708c432258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329845426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2329845426
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.607611875
Short name T109
Test name
Test status
Simulation time 8031081256 ps
CPU time 72.52 seconds
Started Jul 16 07:27:03 PM PDT 24
Finished Jul 16 07:28:45 PM PDT 24
Peak memory 213664 kb
Host smart-58f0b4c3-1071-4db4-b65d-33594c22b25f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607611875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.607611875
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.3541121116
Short name T10
Test name
Test status
Simulation time 3977990638 ps
CPU time 11.64 seconds
Started Jul 16 07:35:57 PM PDT 24
Finished Jul 16 07:36:27 PM PDT 24
Peak memory 205300 kb
Host smart-d0ece93e-f000-48b4-a5d2-1d46ced46c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541121116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3541121116
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.1463419152
Short name T48
Test name
Test status
Simulation time 358912783 ps
CPU time 0.84 seconds
Started Jul 16 07:34:01 PM PDT 24
Finished Jul 16 07:34:24 PM PDT 24
Peak memory 215744 kb
Host smart-b3742e1d-f954-4227-b5b4-f09dd2809c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463419152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1463419152
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1259616865
Short name T166
Test name
Test status
Simulation time 9363871128 ps
CPU time 7.78 seconds
Started Jul 16 07:34:59 PM PDT 24
Finished Jul 16 07:35:09 PM PDT 24
Peak memory 213728 kb
Host smart-f49e1c10-23df-48a3-a03a-b41074973c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259616865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1259616865
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.154862809
Short name T79
Test name
Test status
Simulation time 1424846095 ps
CPU time 4.2 seconds
Started Jul 16 07:33:46 PM PDT 24
Finished Jul 16 07:34:12 PM PDT 24
Peak memory 205284 kb
Host smart-2e9a1c17-1eca-4f40-a4b6-59bd5bdb89bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154862809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.154862809
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3245083436
Short name T52
Test name
Test status
Simulation time 3145000493 ps
CPU time 3.79 seconds
Started Jul 16 07:33:48 PM PDT 24
Finished Jul 16 07:34:14 PM PDT 24
Peak memory 229728 kb
Host smart-7218b88a-455c-4a43-bceb-38dfc2578ae1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245083436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3245083436
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.3101930108
Short name T12
Test name
Test status
Simulation time 5125568910 ps
CPU time 8.62 seconds
Started Jul 16 07:34:58 PM PDT 24
Finished Jul 16 07:35:09 PM PDT 24
Peak memory 213456 kb
Host smart-5097a810-2009-4fab-bef2-66d384d388a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101930108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3101930108
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3057411920
Short name T43
Test name
Test status
Simulation time 343033359 ps
CPU time 0.87 seconds
Started Jul 16 07:33:46 PM PDT 24
Finished Jul 16 07:34:08 PM PDT 24
Peak memory 205004 kb
Host smart-63af9255-0471-437c-b0e2-670665ee86c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057411920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3057411920
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.861979775
Short name T56
Test name
Test status
Simulation time 85378067 ps
CPU time 0.88 seconds
Started Jul 16 07:33:49 PM PDT 24
Finished Jul 16 07:34:12 PM PDT 24
Peak memory 204880 kb
Host smart-26b4e3bd-91c6-4b5c-92bb-1e0d7fc92c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861979775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.861979775
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.833028993
Short name T5
Test name
Test status
Simulation time 882398894 ps
CPU time 3.31 seconds
Started Jul 16 07:34:06 PM PDT 24
Finished Jul 16 07:34:31 PM PDT 24
Peak memory 205144 kb
Host smart-e93e085b-dd19-41a6-a4cd-ba9fe2e85b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833028993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.833028993
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.764664319
Short name T113
Test name
Test status
Simulation time 1895530157 ps
CPU time 15.86 seconds
Started Jul 16 07:27:25 PM PDT 24
Finished Jul 16 07:28:01 PM PDT 24
Peak memory 213556 kb
Host smart-e99413a0-2473-47df-82e3-07c0058f5ce0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764664319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.764664319
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3768153437
Short name T159
Test name
Test status
Simulation time 10377275676 ps
CPU time 15.43 seconds
Started Jul 16 07:33:29 PM PDT 24
Finished Jul 16 07:34:08 PM PDT 24
Peak memory 213672 kb
Host smart-c9f2ebd7-705d-42d4-b8de-bf89edea558a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768153437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3768153437
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1039154492
Short name T17
Test name
Test status
Simulation time 1252916832 ps
CPU time 3.9 seconds
Started Jul 16 07:33:30 PM PDT 24
Finished Jul 16 07:33:59 PM PDT 24
Peak memory 205040 kb
Host smart-0997bee7-9aa3-4b2b-9d07-92dccfbb7d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039154492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1039154492
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2270914566
Short name T44
Test name
Test status
Simulation time 389390961 ps
CPU time 1.89 seconds
Started Jul 16 07:33:46 PM PDT 24
Finished Jul 16 07:34:09 PM PDT 24
Peak memory 204940 kb
Host smart-21803915-518f-46ae-b4a7-477bde3bbeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270914566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2270914566
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1776629860
Short name T385
Test name
Test status
Simulation time 6854155052 ps
CPU time 25 seconds
Started Jul 16 07:27:42 PM PDT 24
Finished Jul 16 07:28:21 PM PDT 24
Peak memory 213792 kb
Host smart-174c5179-293c-4168-80b4-02a778b3e178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776629860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
776629860
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.3611265450
Short name T27
Test name
Test status
Simulation time 187609500 ps
CPU time 0.9 seconds
Started Jul 16 07:33:48 PM PDT 24
Finished Jul 16 07:34:11 PM PDT 24
Peak memory 205004 kb
Host smart-beefbdd7-066a-49e6-8b32-28f8eb1c6fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611265450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3611265450
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.3624420880
Short name T21
Test name
Test status
Simulation time 5455051620 ps
CPU time 4.82 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:04 PM PDT 24
Peak memory 205284 kb
Host smart-6b97cd2c-692e-42bf-aa78-4f49b888151b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624420880 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3624420880
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2087995335
Short name T81
Test name
Test status
Simulation time 4576083989 ps
CPU time 4.38 seconds
Started Jul 16 07:35:50 PM PDT 24
Finished Jul 16 07:35:56 PM PDT 24
Peak memory 213740 kb
Host smart-eaa1eb04-5639-4c67-948f-5cb0aa5e9af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087995335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2087995335
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3841319503
Short name T169
Test name
Test status
Simulation time 347174092 ps
CPU time 6.74 seconds
Started Jul 16 07:27:43 PM PDT 24
Finished Jul 16 07:28:03 PM PDT 24
Peak memory 213604 kb
Host smart-ad6c2dde-79d9-49bd-8ccf-352e08544cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841319503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3841319503
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1002732470
Short name T177
Test name
Test status
Simulation time 1924969932 ps
CPU time 11.13 seconds
Started Jul 16 07:27:01 PM PDT 24
Finished Jul 16 07:27:42 PM PDT 24
Peak memory 213612 kb
Host smart-24d671b8-bcf8-4356-8592-2b2850b0aa55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002732470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1002732470
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.1409423994
Short name T26
Test name
Test status
Simulation time 4987532717 ps
CPU time 7.71 seconds
Started Jul 16 07:36:00 PM PDT 24
Finished Jul 16 07:36:28 PM PDT 24
Peak memory 205280 kb
Host smart-3203c8f7-c95a-4a08-9a40-b17f7cddb2c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409423994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1409423994
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1863941018
Short name T84
Test name
Test status
Simulation time 608670010 ps
CPU time 1.16 seconds
Started Jul 16 07:26:48 PM PDT 24
Finished Jul 16 07:27:24 PM PDT 24
Peak memory 205068 kb
Host smart-8e797c04-2848-4911-a65d-27f16f940c12
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863941018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1863941018
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.3757757097
Short name T41
Test name
Test status
Simulation time 13749530034 ps
CPU time 11.73 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:18 PM PDT 24
Peak memory 213532 kb
Host smart-440b16d4-7373-4f01-98ab-9f7037a4685f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757757097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3757757097
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.1978163700
Short name T120
Test name
Test status
Simulation time 6664633046 ps
CPU time 18.87 seconds
Started Jul 16 07:26:38 PM PDT 24
Finished Jul 16 07:27:33 PM PDT 24
Peak memory 205388 kb
Host smart-510b421c-acfc-4b30-8aca-d8ad47b8f712
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978163700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.1978163700
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4183047866
Short name T136
Test name
Test status
Simulation time 332890120 ps
CPU time 3.64 seconds
Started Jul 16 07:27:05 PM PDT 24
Finished Jul 16 07:27:39 PM PDT 24
Peak memory 205464 kb
Host smart-143844b9-e8f5-4c36-b89e-e3648eea6cfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183047866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.4183047866
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1257573286
Short name T38
Test name
Test status
Simulation time 490137715 ps
CPU time 2.07 seconds
Started Jul 16 07:33:32 PM PDT 24
Finished Jul 16 07:33:58 PM PDT 24
Peak memory 205024 kb
Host smart-785f9856-7a9a-4dbd-9048-be81a3a72ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257573286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1257573286
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2821860358
Short name T181
Test name
Test status
Simulation time 76945402522 ps
CPU time 31.15 seconds
Started Jul 16 07:26:51 PM PDT 24
Finished Jul 16 07:27:56 PM PDT 24
Peak memory 230156 kb
Host smart-133b8431-8684-491b-84e4-98d50410a192
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821860358 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2821860358
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3825131560
Short name T89
Test name
Test status
Simulation time 1864955825 ps
CPU time 20.77 seconds
Started Jul 16 07:27:30 PM PDT 24
Finished Jul 16 07:28:10 PM PDT 24
Peak memory 213672 kb
Host smart-e5e2a5ed-cb20-40d0-b2ae-436b01d243c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825131560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
825131560
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3458340673
Short name T279
Test name
Test status
Simulation time 183112122 ps
CPU time 1.21 seconds
Started Jul 16 07:33:46 PM PDT 24
Finished Jul 16 07:34:08 PM PDT 24
Peak memory 205012 kb
Host smart-6e7ba9bd-ea89-4c73-a1d0-5f54e8497c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458340673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3458340673
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2539075242
Short name T163
Test name
Test status
Simulation time 3819833168 ps
CPU time 10 seconds
Started Jul 16 07:35:02 PM PDT 24
Finished Jul 16 07:35:17 PM PDT 24
Peak memory 213704 kb
Host smart-5e2bbfa2-b6bf-436a-b057-2416d0ea407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539075242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2539075242
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3108480757
Short name T130
Test name
Test status
Simulation time 7926693090 ps
CPU time 33.66 seconds
Started Jul 16 07:26:39 PM PDT 24
Finished Jul 16 07:27:51 PM PDT 24
Peak memory 205448 kb
Host smart-d5400ee4-8d34-4a4c-9709-3baa57d85bfa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108480757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3108480757
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.245401659
Short name T372
Test name
Test status
Simulation time 2668256906 ps
CPU time 17.34 seconds
Started Jul 16 07:27:44 PM PDT 24
Finished Jul 16 07:28:14 PM PDT 24
Peak memory 213696 kb
Host smart-2f477a94-bebf-43d6-a5d9-80cf17b6684a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245401659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.245401659
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.541998854
Short name T406
Test name
Test status
Simulation time 35678425000 ps
CPU time 32.3 seconds
Started Jul 16 07:26:51 PM PDT 24
Finished Jul 16 07:27:57 PM PDT 24
Peak memory 221976 kb
Host smart-9d9866d2-e1fc-4d9c-9ab1-d3cf172f7a15
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541998854 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.541998854
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2630013869
Short name T416
Test name
Test status
Simulation time 15221606438 ps
CPU time 38.21 seconds
Started Jul 16 07:26:51 PM PDT 24
Finished Jul 16 07:28:03 PM PDT 24
Peak memory 213608 kb
Host smart-679d5a2e-9dcf-4286-9e31-fc09cac32f6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630013869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2630013869
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3554437867
Short name T135
Test name
Test status
Simulation time 489406040 ps
CPU time 3.41 seconds
Started Jul 16 07:26:49 PM PDT 24
Finished Jul 16 07:27:27 PM PDT 24
Peak memory 213656 kb
Host smart-8d88efac-4c58-4ae8-b2a5-bbdaa1fc9d46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554437867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3554437867
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1668304799
Short name T388
Test name
Test status
Simulation time 3247223733 ps
CPU time 7.28 seconds
Started Jul 16 07:26:52 PM PDT 24
Finished Jul 16 07:27:32 PM PDT 24
Peak memory 218060 kb
Host smart-d0af411c-c367-4a73-a248-75e37fdd5361
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668304799 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1668304799
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1049607804
Short name T304
Test name
Test status
Simulation time 97791652 ps
CPU time 2.4 seconds
Started Jul 16 07:26:52 PM PDT 24
Finished Jul 16 07:27:27 PM PDT 24
Peak memory 213564 kb
Host smart-8a05fdc1-b442-466c-86fb-77a02349c5e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049607804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1049607804
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3991578135
Short name T424
Test name
Test status
Simulation time 36325380428 ps
CPU time 94.45 seconds
Started Jul 16 07:26:50 PM PDT 24
Finished Jul 16 07:28:58 PM PDT 24
Peak memory 205344 kb
Host smart-e6790fcc-b369-46be-a20d-474fe1ab95cc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991578135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3991578135
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.2292110223
Short name T341
Test name
Test status
Simulation time 24409832675 ps
CPU time 66.35 seconds
Started Jul 16 07:26:52 PM PDT 24
Finished Jul 16 07:28:31 PM PDT 24
Peak memory 205320 kb
Host smart-85430caf-352f-476e-b4fb-3cc3c1531b81
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292110223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.2292110223
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2680734908
Short name T323
Test name
Test status
Simulation time 2529013705 ps
CPU time 7.66 seconds
Started Jul 16 07:26:51 PM PDT 24
Finished Jul 16 07:27:32 PM PDT 24
Peak memory 205304 kb
Host smart-1cb56896-1d9f-41e1-8ff5-5120785ae608
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680734908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
680734908
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3709458015
Short name T352
Test name
Test status
Simulation time 302935259 ps
CPU time 0.87 seconds
Started Jul 16 07:26:47 PM PDT 24
Finished Jul 16 07:27:23 PM PDT 24
Peak memory 205012 kb
Host smart-aab29426-68f7-43ea-a31d-027d47bcc496
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709458015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3709458015
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3966651632
Short name T419
Test name
Test status
Simulation time 17118971915 ps
CPU time 48.61 seconds
Started Jul 16 07:26:49 PM PDT 24
Finished Jul 16 07:28:12 PM PDT 24
Peak memory 205392 kb
Host smart-3a62b2e3-7275-4d6e-8634-fac2ad632610
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966651632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3966651632
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1807297875
Short name T321
Test name
Test status
Simulation time 503403586 ps
CPU time 1.01 seconds
Started Jul 16 07:26:49 PM PDT 24
Finished Jul 16 07:27:25 PM PDT 24
Peak memory 205004 kb
Host smart-4c638de4-79d3-46ef-b019-c749ec251e13
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807297875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
807297875
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.709063892
Short name T285
Test name
Test status
Simulation time 99738605 ps
CPU time 0.89 seconds
Started Jul 16 07:26:51 PM PDT 24
Finished Jul 16 07:27:24 PM PDT 24
Peak memory 205036 kb
Host smart-4814370e-56d7-416e-be39-ff7b2547a2b6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709063892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.709063892
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.842914659
Short name T393
Test name
Test status
Simulation time 68561372 ps
CPU time 0.73 seconds
Started Jul 16 07:26:50 PM PDT 24
Finished Jul 16 07:27:24 PM PDT 24
Peak memory 205028 kb
Host smart-b17e6d54-3430-42b7-a3e4-36b037fee2bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842914659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.842914659
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2777004375
Short name T387
Test name
Test status
Simulation time 102578375 ps
CPU time 3.53 seconds
Started Jul 16 07:26:50 PM PDT 24
Finished Jul 16 07:27:27 PM PDT 24
Peak memory 205472 kb
Host smart-69b49985-80ab-4c23-a115-7e42798ed122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777004375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2777004375
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.350976158
Short name T337
Test name
Test status
Simulation time 310576260 ps
CPU time 4.63 seconds
Started Jul 16 07:26:49 PM PDT 24
Finished Jul 16 07:27:28 PM PDT 24
Peak memory 213676 kb
Host smart-7191bc50-aa98-4ff7-a02c-3df79cb370eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350976158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.350976158
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2390656273
Short name T174
Test name
Test status
Simulation time 6506495784 ps
CPU time 20.51 seconds
Started Jul 16 07:26:51 PM PDT 24
Finished Jul 16 07:27:45 PM PDT 24
Peak memory 213748 kb
Host smart-ee151199-4b60-423c-835c-3c5b7f28bfde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390656273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2390656273
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1907997087
Short name T121
Test name
Test status
Simulation time 19987346531 ps
CPU time 82.61 seconds
Started Jul 16 07:26:52 PM PDT 24
Finished Jul 16 07:28:47 PM PDT 24
Peak memory 205424 kb
Host smart-2922ad95-ce17-43d4-81f3-c582c3ad485c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907997087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1907997087
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.4260618173
Short name T376
Test name
Test status
Simulation time 9661455671 ps
CPU time 37.86 seconds
Started Jul 16 07:27:03 PM PDT 24
Finished Jul 16 07:28:12 PM PDT 24
Peak memory 213656 kb
Host smart-a6ec051a-5275-44f2-8ffc-923e06264d0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260618173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.4260618173
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3945371511
Short name T390
Test name
Test status
Simulation time 71595248 ps
CPU time 1.66 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:27:33 PM PDT 24
Peak memory 213540 kb
Host smart-476c9d69-39c9-4cff-9285-4d428e9dac8c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945371511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3945371511
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3097154842
Short name T171
Test name
Test status
Simulation time 141115308 ps
CPU time 3.98 seconds
Started Jul 16 07:27:09 PM PDT 24
Finished Jul 16 07:27:40 PM PDT 24
Peak memory 220012 kb
Host smart-81b6a7ca-fea1-4a2b-8544-832c8fe47746
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097154842 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3097154842
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2847624681
Short name T338
Test name
Test status
Simulation time 157891134 ps
CPU time 2.15 seconds
Started Jul 16 07:27:04 PM PDT 24
Finished Jul 16 07:27:37 PM PDT 24
Peak memory 213548 kb
Host smart-b1096e05-636b-41f1-9ed3-1634e58905b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847624681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2847624681
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4137098750
Short name T420
Test name
Test status
Simulation time 59908716539 ps
CPU time 57.79 seconds
Started Jul 16 07:26:52 PM PDT 24
Finished Jul 16 07:28:22 PM PDT 24
Peak memory 205348 kb
Host smart-b68e3421-a720-4941-a7b6-375b50a7c77c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137098750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.4137098750
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1578675196
Short name T324
Test name
Test status
Simulation time 57327408593 ps
CPU time 85.85 seconds
Started Jul 16 07:26:50 PM PDT 24
Finished Jul 16 07:28:48 PM PDT 24
Peak memory 205292 kb
Host smart-0d786086-4b0b-45b8-b232-ab5a0c224dfb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578675196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1578675196
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.653094799
Short name T119
Test name
Test status
Simulation time 5656159459 ps
CPU time 13.11 seconds
Started Jul 16 07:26:52 PM PDT 24
Finished Jul 16 07:27:38 PM PDT 24
Peak memory 205436 kb
Host smart-9e5d853e-4f08-4474-b3f0-9f1b17571574
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653094799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_hw_reset.653094799
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.219933542
Short name T357
Test name
Test status
Simulation time 15179193635 ps
CPU time 25.26 seconds
Started Jul 16 07:26:50 PM PDT 24
Finished Jul 16 07:27:49 PM PDT 24
Peak memory 205376 kb
Host smart-402e5e06-b4f0-41ce-98d0-6d544f029443
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219933542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.219933542
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.371104685
Short name T403
Test name
Test status
Simulation time 640328634 ps
CPU time 2.31 seconds
Started Jul 16 07:26:51 PM PDT 24
Finished Jul 16 07:27:27 PM PDT 24
Peak memory 204948 kb
Host smart-98afbd7e-c868-4a1b-a181-9a92b079b8f8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371104685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.371104685
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.517000201
Short name T308
Test name
Test status
Simulation time 7236310206 ps
CPU time 14.82 seconds
Started Jul 16 07:26:52 PM PDT 24
Finished Jul 16 07:27:39 PM PDT 24
Peak memory 205416 kb
Host smart-4e0b227f-0c15-47d2-8443-716184f91c69
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517000201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.517000201
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2699367500
Short name T407
Test name
Test status
Simulation time 430980366 ps
CPU time 0.75 seconds
Started Jul 16 07:26:49 PM PDT 24
Finished Jul 16 07:27:24 PM PDT 24
Peak memory 205016 kb
Host smart-7d3307d7-cee7-4f97-9acf-6a68f77bc782
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699367500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2699367500
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3987228275
Short name T380
Test name
Test status
Simulation time 215324415 ps
CPU time 0.76 seconds
Started Jul 16 07:26:51 PM PDT 24
Finished Jul 16 07:27:25 PM PDT 24
Peak memory 204968 kb
Host smart-fa9a526b-91f5-4a4a-83aa-4b7e4a2c27a1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987228275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
987228275
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2369449436
Short name T281
Test name
Test status
Simulation time 60582427 ps
CPU time 0.66 seconds
Started Jul 16 07:27:04 PM PDT 24
Finished Jul 16 07:27:35 PM PDT 24
Peak memory 205040 kb
Host smart-aace6356-06be-4389-be0b-64f6e5501f68
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369449436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2369449436
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.662487
Short name T318
Test name
Test status
Simulation time 27738911 ps
CPU time 0.7 seconds
Started Jul 16 07:26:52 PM PDT 24
Finished Jul 16 07:27:25 PM PDT 24
Peak memory 205036 kb
Host smart-6398c415-0f9c-45f5-82dc-1b48ade93a1c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.662487
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3876301680
Short name T114
Test name
Test status
Simulation time 325351326 ps
CPU time 5.09 seconds
Started Jul 16 07:26:51 PM PDT 24
Finished Jul 16 07:27:30 PM PDT 24
Peak memory 213728 kb
Host smart-d97cd582-1f03-4595-a92e-bec180412222
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876301680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3876301680
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3871238989
Short name T172
Test name
Test status
Simulation time 2122977723 ps
CPU time 22.27 seconds
Started Jul 16 07:26:52 PM PDT 24
Finished Jul 16 07:27:46 PM PDT 24
Peak memory 213632 kb
Host smart-b330d2cc-f885-46f8-9d88-88fcb51acfab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871238989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3871238989
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3731040879
Short name T365
Test name
Test status
Simulation time 306581326 ps
CPU time 2.92 seconds
Started Jul 16 07:27:23 PM PDT 24
Finished Jul 16 07:27:46 PM PDT 24
Peak memory 217268 kb
Host smart-e04c5822-0b68-486c-82ef-6313b6db3d74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731040879 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3731040879
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.309245919
Short name T381
Test name
Test status
Simulation time 377371813 ps
CPU time 2.23 seconds
Started Jul 16 07:27:28 PM PDT 24
Finished Jul 16 07:27:51 PM PDT 24
Peak memory 213500 kb
Host smart-3d829a1a-b1c2-492f-8617-427e717a2dab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309245919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.309245919
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.56375131
Short name T316
Test name
Test status
Simulation time 4890789811 ps
CPU time 13.14 seconds
Started Jul 16 07:27:29 PM PDT 24
Finished Jul 16 07:28:02 PM PDT 24
Peak memory 205348 kb
Host smart-32b1bfad-00e8-44bf-8877-8761a44c74fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56375131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.r
v_dm_jtag_dmi_csr_bit_bash.56375131
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.660691027
Short name T330
Test name
Test status
Simulation time 1857866076 ps
CPU time 5.62 seconds
Started Jul 16 07:27:27 PM PDT 24
Finished Jul 16 07:27:53 PM PDT 24
Peak memory 205276 kb
Host smart-7c418490-d1bb-4e57-8b36-05961bff03d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660691027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.660691027
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.757595588
Short name T359
Test name
Test status
Simulation time 693890954 ps
CPU time 1.52 seconds
Started Jul 16 07:27:26 PM PDT 24
Finished Jul 16 07:27:48 PM PDT 24
Peak memory 205020 kb
Host smart-af2c430f-129d-46f0-b7ea-39a2b855b224
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757595588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.757595588
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.4054113449
Short name T137
Test name
Test status
Simulation time 741337642 ps
CPU time 4.29 seconds
Started Jul 16 07:27:31 PM PDT 24
Finished Jul 16 07:27:53 PM PDT 24
Peak memory 205360 kb
Host smart-578d39c2-4d8a-413b-81d1-1ed77a0c0c1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054113449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.4054113449
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.4120279348
Short name T347
Test name
Test status
Simulation time 308974824 ps
CPU time 5 seconds
Started Jul 16 07:27:25 PM PDT 24
Finished Jul 16 07:27:50 PM PDT 24
Peak memory 213740 kb
Host smart-7ee63f9b-52bb-4f0e-a6f4-1bf1d42ed78b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120279348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.4120279348
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.2816243430
Short name T405
Test name
Test status
Simulation time 2080747779 ps
CPU time 3.44 seconds
Started Jul 16 07:27:40 PM PDT 24
Finished Jul 16 07:27:57 PM PDT 24
Peak memory 213696 kb
Host smart-5e0b2d59-a157-4a0b-87fb-61bd629e39bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816243430 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.2816243430
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4075803779
Short name T123
Test name
Test status
Simulation time 217183941 ps
CPU time 2.19 seconds
Started Jul 16 07:27:40 PM PDT 24
Finished Jul 16 07:27:56 PM PDT 24
Peak memory 213604 kb
Host smart-f692ade4-76e1-4c3f-99b5-22cb929136b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075803779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4075803779
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3661036595
Short name T355
Test name
Test status
Simulation time 8208617142 ps
CPU time 22.57 seconds
Started Jul 16 07:27:31 PM PDT 24
Finished Jul 16 07:28:11 PM PDT 24
Peak memory 205368 kb
Host smart-42d8996c-661c-4c5a-a43f-1662a21ba4b4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661036595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3661036595
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2211672963
Short name T377
Test name
Test status
Simulation time 1310064157 ps
CPU time 1.73 seconds
Started Jul 16 07:27:28 PM PDT 24
Finished Jul 16 07:27:51 PM PDT 24
Peak memory 205216 kb
Host smart-9ede1068-080f-401f-bd6b-2a11effaeae5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211672963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2211672963
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.345782718
Short name T353
Test name
Test status
Simulation time 99231162 ps
CPU time 0.79 seconds
Started Jul 16 07:27:26 PM PDT 24
Finished Jul 16 07:27:47 PM PDT 24
Peak memory 204976 kb
Host smart-2259aa3b-20e5-4bea-a6f0-4b2ece70e1d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345782718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.345782718
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2584374415
Short name T106
Test name
Test status
Simulation time 1095976331 ps
CPU time 7.87 seconds
Started Jul 16 07:27:41 PM PDT 24
Finished Jul 16 07:28:03 PM PDT 24
Peak memory 205448 kb
Host smart-6061f118-34f0-4554-927e-31bb056a471c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584374415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2584374415
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.2265407334
Short name T384
Test name
Test status
Simulation time 73919854 ps
CPU time 2.77 seconds
Started Jul 16 07:27:29 PM PDT 24
Finished Jul 16 07:27:52 PM PDT 24
Peak memory 213600 kb
Host smart-cc051ed6-d78b-4fb8-b092-6f6203179e87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265407334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.2265407334
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1299507521
Short name T383
Test name
Test status
Simulation time 210388899 ps
CPU time 2.82 seconds
Started Jul 16 07:27:41 PM PDT 24
Finished Jul 16 07:27:58 PM PDT 24
Peak memory 219312 kb
Host smart-3924e7ea-0322-4f2b-9ead-ccef8c518109
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299507521 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1299507521
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3996982036
Short name T105
Test name
Test status
Simulation time 117332887 ps
CPU time 2.42 seconds
Started Jul 16 07:27:39 PM PDT 24
Finished Jul 16 07:27:54 PM PDT 24
Peak memory 213500 kb
Host smart-7ff0ea45-3fb6-44be-b856-000c25b94557
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996982036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3996982036
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.3344312211
Short name T370
Test name
Test status
Simulation time 11225852073 ps
CPU time 8.26 seconds
Started Jul 16 07:27:42 PM PDT 24
Finished Jul 16 07:28:04 PM PDT 24
Peak memory 205376 kb
Host smart-dedcee9e-7646-4123-9d93-2cecc303cc06
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344312211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.3344312211
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.2763397104
Short name T301
Test name
Test status
Simulation time 3050807892 ps
CPU time 3.76 seconds
Started Jul 16 07:27:42 PM PDT 24
Finished Jul 16 07:27:59 PM PDT 24
Peak memory 205212 kb
Host smart-e315cb53-2877-4929-a029-324e91472541
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763397104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
2763397104
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.673894537
Short name T394
Test name
Test status
Simulation time 304378924 ps
CPU time 1.47 seconds
Started Jul 16 07:27:39 PM PDT 24
Finished Jul 16 07:27:54 PM PDT 24
Peak memory 204992 kb
Host smart-c28096e4-f069-413d-9e3a-446611101d6a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673894537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.673894537
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3321885820
Short name T396
Test name
Test status
Simulation time 1810637491 ps
CPU time 7.89 seconds
Started Jul 16 07:27:43 PM PDT 24
Finished Jul 16 07:28:04 PM PDT 24
Peak memory 205384 kb
Host smart-9cd3e6e6-89d2-4d9a-8db3-836830691c99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321885820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3321885820
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3793556193
Short name T312
Test name
Test status
Simulation time 177419287 ps
CPU time 2.4 seconds
Started Jul 16 07:27:42 PM PDT 24
Finished Jul 16 07:27:58 PM PDT 24
Peak memory 217992 kb
Host smart-efcda863-b243-4b8f-896e-abbf574a6b73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793556193 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3793556193
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3343580610
Short name T103
Test name
Test status
Simulation time 353610922 ps
CPU time 2.54 seconds
Started Jul 16 07:27:41 PM PDT 24
Finished Jul 16 07:27:58 PM PDT 24
Peak memory 213604 kb
Host smart-71584cb2-de86-40c2-af2a-e3dafbf8aabc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343580610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3343580610
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2769991801
Short name T286
Test name
Test status
Simulation time 5855083639 ps
CPU time 16.07 seconds
Started Jul 16 07:27:41 PM PDT 24
Finished Jul 16 07:28:12 PM PDT 24
Peak memory 205364 kb
Host smart-55e15c86-5ae4-400a-bc7e-8963a9101ef0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769991801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2769991801
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3566515730
Short name T326
Test name
Test status
Simulation time 5623009878 ps
CPU time 8.64 seconds
Started Jul 16 07:27:39 PM PDT 24
Finished Jul 16 07:28:01 PM PDT 24
Peak memory 205276 kb
Host smart-b375e583-b111-4515-b2f3-7e5a2d3e1137
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566515730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3566515730
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1511214559
Short name T292
Test name
Test status
Simulation time 494774454 ps
CPU time 1.03 seconds
Started Jul 16 07:27:41 PM PDT 24
Finished Jul 16 07:27:57 PM PDT 24
Peak memory 205064 kb
Host smart-34cef468-8bfa-419a-93a5-3a34e63a20df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511214559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1511214559
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2254967827
Short name T125
Test name
Test status
Simulation time 94576398 ps
CPU time 3.51 seconds
Started Jul 16 07:27:42 PM PDT 24
Finished Jul 16 07:27:59 PM PDT 24
Peak memory 205392 kb
Host smart-00875077-49df-4ae2-9cd8-b6b781ea1cb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254967827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2254967827
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.4102080872
Short name T391
Test name
Test status
Simulation time 267414176 ps
CPU time 4.43 seconds
Started Jul 16 07:27:39 PM PDT 24
Finished Jul 16 07:27:57 PM PDT 24
Peak memory 213684 kb
Host smart-b7547444-ba64-49c1-85c2-d41364d1d719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102080872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.4102080872
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2993862475
Short name T348
Test name
Test status
Simulation time 4339858509 ps
CPU time 19.76 seconds
Started Jul 16 07:27:38 PM PDT 24
Finished Jul 16 07:28:12 PM PDT 24
Peak memory 213728 kb
Host smart-86969b9b-8925-4320-ac29-49fef765cc65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993862475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
993862475
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2726378622
Short name T144
Test name
Test status
Simulation time 207991058 ps
CPU time 3.94 seconds
Started Jul 16 07:27:39 PM PDT 24
Finished Jul 16 07:27:57 PM PDT 24
Peak memory 219504 kb
Host smart-0840c57e-635b-44c9-bf88-6ef3f3566c63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726378622 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2726378622
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3939954760
Short name T102
Test name
Test status
Simulation time 133970218 ps
CPU time 1.54 seconds
Started Jul 16 07:27:45 PM PDT 24
Finished Jul 16 07:28:02 PM PDT 24
Peak memory 213580 kb
Host smart-86e6bb31-e0d3-49d9-a318-5b4e259e987a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939954760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3939954760
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.3866490399
Short name T375
Test name
Test status
Simulation time 34475486267 ps
CPU time 85.74 seconds
Started Jul 16 07:27:40 PM PDT 24
Finished Jul 16 07:29:21 PM PDT 24
Peak memory 205260 kb
Host smart-b2120353-d2ab-4b25-b936-4342685d6b9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866490399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.3866490399
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.12193463
Short name T413
Test name
Test status
Simulation time 2126080864 ps
CPU time 3.32 seconds
Started Jul 16 07:27:40 PM PDT 24
Finished Jul 16 07:27:57 PM PDT 24
Peak memory 205248 kb
Host smart-322ce0e4-ac57-44ba-b86d-85808cbbfca3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12193463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.12193463
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2494345778
Short name T302
Test name
Test status
Simulation time 792471351 ps
CPU time 2.76 seconds
Started Jul 16 07:27:42 PM PDT 24
Finished Jul 16 07:27:59 PM PDT 24
Peak memory 205012 kb
Host smart-ea58f9c1-3b10-4bce-9508-91fede4a49a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494345778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2494345778
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3220680671
Short name T124
Test name
Test status
Simulation time 119985157 ps
CPU time 3.79 seconds
Started Jul 16 07:27:40 PM PDT 24
Finished Jul 16 07:27:58 PM PDT 24
Peak memory 205384 kb
Host smart-f2d691d7-b9df-4f37-a682-078734f5ed97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220680671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3220680671
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.513015196
Short name T392
Test name
Test status
Simulation time 127856885 ps
CPU time 2.7 seconds
Started Jul 16 07:27:41 PM PDT 24
Finished Jul 16 07:27:58 PM PDT 24
Peak memory 213744 kb
Host smart-fa93ec01-f3f9-43b8-a309-00085a0f7598
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513015196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.513015196
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3721935967
Short name T175
Test name
Test status
Simulation time 6405000121 ps
CPU time 21.21 seconds
Started Jul 16 07:27:40 PM PDT 24
Finished Jul 16 07:28:15 PM PDT 24
Peak memory 213740 kb
Host smart-781c2652-9d20-4201-b326-e7de0127987f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721935967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
721935967
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1276566518
Short name T349
Test name
Test status
Simulation time 342106939 ps
CPU time 3.9 seconds
Started Jul 16 07:27:38 PM PDT 24
Finished Jul 16 07:27:56 PM PDT 24
Peak memory 221712 kb
Host smart-88b89a5d-f01b-46a0-b938-413f282eea29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276566518 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1276566518
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2743548793
Short name T133
Test name
Test status
Simulation time 99832192 ps
CPU time 1.64 seconds
Started Jul 16 07:27:44 PM PDT 24
Finished Jul 16 07:27:59 PM PDT 24
Peak memory 213580 kb
Host smart-0254accc-0b61-4183-a726-92616e7fb56e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743548793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2743548793
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.3861687099
Short name T426
Test name
Test status
Simulation time 15559690257 ps
CPU time 29.16 seconds
Started Jul 16 07:27:40 PM PDT 24
Finished Jul 16 07:28:22 PM PDT 24
Peak memory 205348 kb
Host smart-d2323ca2-d1a9-49d9-a7c0-6d76530a0ea7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861687099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.3861687099
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3973345974
Short name T368
Test name
Test status
Simulation time 984552381 ps
CPU time 3.63 seconds
Started Jul 16 07:27:42 PM PDT 24
Finished Jul 16 07:28:00 PM PDT 24
Peak memory 205164 kb
Host smart-40fa60e5-f163-4efc-b071-aae6e54a8293
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973345974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3973345974
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4220795668
Short name T409
Test name
Test status
Simulation time 264309079 ps
CPU time 1.39 seconds
Started Jul 16 07:27:39 PM PDT 24
Finished Jul 16 07:27:54 PM PDT 24
Peak memory 204976 kb
Host smart-cd8a6ef9-a3ce-4a2b-83e2-91692be8e9ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220795668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
4220795668
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1150593390
Short name T354
Test name
Test status
Simulation time 217149047 ps
CPU time 3.92 seconds
Started Jul 16 07:27:42 PM PDT 24
Finished Jul 16 07:28:00 PM PDT 24
Peak memory 205424 kb
Host smart-457acd41-726c-47b6-a0fc-1163cf298251
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150593390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1150593390
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3022385470
Short name T317
Test name
Test status
Simulation time 121435394 ps
CPU time 4.84 seconds
Started Jul 16 07:27:41 PM PDT 24
Finished Jul 16 07:28:00 PM PDT 24
Peak memory 213760 kb
Host smart-4b5434ec-cb51-4e04-8e46-577abebd146a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022385470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3022385470
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.179955204
Short name T68
Test name
Test status
Simulation time 2435455255 ps
CPU time 10.85 seconds
Started Jul 16 07:27:40 PM PDT 24
Finished Jul 16 07:28:04 PM PDT 24
Peak memory 213712 kb
Host smart-fc0ebbad-69d7-432b-85b8-fd580973454d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179955204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.179955204
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3258840965
Short name T310
Test name
Test status
Simulation time 389281061 ps
CPU time 3.18 seconds
Started Jul 16 07:27:40 PM PDT 24
Finished Jul 16 07:27:57 PM PDT 24
Peak memory 218300 kb
Host smart-6028f46e-ae1e-4443-b585-727c0083060f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258840965 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3258840965
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.968483851
Short name T107
Test name
Test status
Simulation time 149200007 ps
CPU time 1.75 seconds
Started Jul 16 07:27:41 PM PDT 24
Finished Jul 16 07:27:57 PM PDT 24
Peak memory 213588 kb
Host smart-0571cfa5-d090-4368-aa07-0a7754f1b712
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968483851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.968483851
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3335795945
Short name T307
Test name
Test status
Simulation time 32772944216 ps
CPU time 24.59 seconds
Started Jul 16 07:27:41 PM PDT 24
Finished Jul 16 07:28:20 PM PDT 24
Peak memory 205352 kb
Host smart-06096930-d9c7-4d9e-946d-31631e7a9d32
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335795945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.3335795945
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2610728533
Short name T295
Test name
Test status
Simulation time 3048623084 ps
CPU time 4.86 seconds
Started Jul 16 07:27:38 PM PDT 24
Finished Jul 16 07:27:57 PM PDT 24
Peak memory 205268 kb
Host smart-cd6683ba-20d0-4e45-9830-699f73985402
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610728533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2610728533
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.334023181
Short name T351
Test name
Test status
Simulation time 363676907 ps
CPU time 1.61 seconds
Started Jul 16 07:27:42 PM PDT 24
Finished Jul 16 07:27:57 PM PDT 24
Peak memory 204936 kb
Host smart-92229c7d-3770-459d-9c42-2496a08f8a98
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334023181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.334023181
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1702547313
Short name T395
Test name
Test status
Simulation time 532098815 ps
CPU time 7.68 seconds
Started Jul 16 07:27:40 PM PDT 24
Finished Jul 16 07:28:01 PM PDT 24
Peak memory 205400 kb
Host smart-0ab04f03-00c3-48f6-a357-f4852bbd9892
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702547313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1702547313
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3842635045
Short name T170
Test name
Test status
Simulation time 145919149 ps
CPU time 3 seconds
Started Jul 16 07:27:42 PM PDT 24
Finished Jul 16 07:27:59 PM PDT 24
Peak memory 213656 kb
Host smart-6c22e80d-8b11-48b7-a1fb-e5d09ef3de20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842635045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3842635045
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1304062015
Short name T179
Test name
Test status
Simulation time 2053821783 ps
CPU time 10.87 seconds
Started Jul 16 07:27:40 PM PDT 24
Finished Jul 16 07:28:06 PM PDT 24
Peak memory 213560 kb
Host smart-0d1badb7-7010-4d2a-b278-0659e0c9a9dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304062015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
304062015
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1417251991
Short name T95
Test name
Test status
Simulation time 84715968 ps
CPU time 2.1 seconds
Started Jul 16 07:27:43 PM PDT 24
Finished Jul 16 07:27:59 PM PDT 24
Peak memory 217204 kb
Host smart-ac0d2d04-8179-4efa-bbb3-e3f686a387b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417251991 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1417251991
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3686515157
Short name T427
Test name
Test status
Simulation time 94194225 ps
CPU time 1.38 seconds
Started Jul 16 07:27:42 PM PDT 24
Finished Jul 16 07:27:57 PM PDT 24
Peak memory 213600 kb
Host smart-e63b726e-1142-4b03-84bc-b440e663e0b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686515157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3686515157
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.4075965388
Short name T415
Test name
Test status
Simulation time 6384750258 ps
CPU time 5.57 seconds
Started Jul 16 07:27:41 PM PDT 24
Finished Jul 16 07:28:01 PM PDT 24
Peak memory 205296 kb
Host smart-f1859119-4cc3-4840-ac0c-338f6e2e8a5b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075965388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.4075965388
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.313427912
Short name T289
Test name
Test status
Simulation time 3781353552 ps
CPU time 4.13 seconds
Started Jul 16 07:27:45 PM PDT 24
Finished Jul 16 07:28:04 PM PDT 24
Peak memory 205196 kb
Host smart-dd358d7e-ed86-4064-9ea7-fa7b55df7e3b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313427912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.313427912
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2662216647
Short name T300
Test name
Test status
Simulation time 225433599 ps
CPU time 0.78 seconds
Started Jul 16 07:27:46 PM PDT 24
Finished Jul 16 07:28:01 PM PDT 24
Peak memory 204956 kb
Host smart-e8d3b670-9fbf-4974-98eb-0a6a627f3cba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662216647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2662216647
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2236307594
Short name T138
Test name
Test status
Simulation time 1553157266 ps
CPU time 4.64 seconds
Started Jul 16 07:27:41 PM PDT 24
Finished Jul 16 07:28:00 PM PDT 24
Peak memory 205400 kb
Host smart-f6bc89cc-2075-4536-8ca2-3a69e843c516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236307594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2236307594
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3233449520
Short name T176
Test name
Test status
Simulation time 2828115337 ps
CPU time 16.28 seconds
Started Jul 16 07:27:40 PM PDT 24
Finished Jul 16 07:28:10 PM PDT 24
Peak memory 213716 kb
Host smart-7bea2004-dabb-4c24-94f5-d4ebce76e98f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233449520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
233449520
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2073150855
Short name T404
Test name
Test status
Simulation time 427986432 ps
CPU time 3.92 seconds
Started Jul 16 07:28:24 PM PDT 24
Finished Jul 16 07:28:41 PM PDT 24
Peak memory 221904 kb
Host smart-bf6ac313-e758-477c-b697-46ed4850b69e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073150855 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2073150855
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.57659544
Short name T364
Test name
Test status
Simulation time 236298470 ps
CPU time 2.17 seconds
Started Jul 16 07:27:45 PM PDT 24
Finished Jul 16 07:28:00 PM PDT 24
Peak memory 213532 kb
Host smart-712b0796-9485-41a9-9ace-539e8478415f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57659544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.57659544
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.1187168272
Short name T379
Test name
Test status
Simulation time 2118323653 ps
CPU time 6.75 seconds
Started Jul 16 07:27:42 PM PDT 24
Finished Jul 16 07:28:02 PM PDT 24
Peak memory 205280 kb
Host smart-1f93eaa7-227f-4401-9267-7636ff22c5c2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187168272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.1187168272
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2435413250
Short name T313
Test name
Test status
Simulation time 2261990239 ps
CPU time 2.31 seconds
Started Jul 16 07:27:41 PM PDT 24
Finished Jul 16 07:27:58 PM PDT 24
Peak memory 205360 kb
Host smart-ae968f63-a8cd-42da-b3ab-29f12a8575ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435413250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2435413250
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1843830438
Short name T362
Test name
Test status
Simulation time 477651713 ps
CPU time 0.89 seconds
Started Jul 16 07:27:40 PM PDT 24
Finished Jul 16 07:27:54 PM PDT 24
Peak memory 205024 kb
Host smart-026dd1eb-d50e-40c7-8327-8804a7203986
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843830438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1843830438
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2140966350
Short name T127
Test name
Test status
Simulation time 1066953845 ps
CPU time 4.23 seconds
Started Jul 16 07:27:44 PM PDT 24
Finished Jul 16 07:28:02 PM PDT 24
Peak memory 205452 kb
Host smart-f0e4a921-13bc-442e-83fa-0e1beae8f739
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140966350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2140966350
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1784297919
Short name T315
Test name
Test status
Simulation time 479326286 ps
CPU time 2.9 seconds
Started Jul 16 07:27:43 PM PDT 24
Finished Jul 16 07:28:00 PM PDT 24
Peak memory 213668 kb
Host smart-27891d9c-b4cc-4e4a-8341-d9a6e70278d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784297919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1784297919
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3232363182
Short name T94
Test name
Test status
Simulation time 3870825006 ps
CPU time 6.87 seconds
Started Jul 16 07:27:45 PM PDT 24
Finished Jul 16 07:28:07 PM PDT 24
Peak memory 220692 kb
Host smart-e4bc3a08-e38e-40f4-ab9c-c26ca99fbc74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232363182 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3232363182
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.326777012
Short name T410
Test name
Test status
Simulation time 152632528 ps
CPU time 1.61 seconds
Started Jul 16 07:27:43 PM PDT 24
Finished Jul 16 07:27:58 PM PDT 24
Peak memory 213604 kb
Host smart-321b826b-b97a-4f6b-be13-382742d8d6dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326777012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.326777012
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1318082121
Short name T399
Test name
Test status
Simulation time 90992145278 ps
CPU time 113.06 seconds
Started Jul 16 07:27:45 PM PDT 24
Finished Jul 16 07:29:53 PM PDT 24
Peak memory 205332 kb
Host smart-d679bbbe-100a-43b5-98d9-8d3bb03a0fe9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318082121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.1318082121
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.4084385991
Short name T283
Test name
Test status
Simulation time 2226987107 ps
CPU time 2.19 seconds
Started Jul 16 07:27:45 PM PDT 24
Finished Jul 16 07:28:02 PM PDT 24
Peak memory 205264 kb
Host smart-c0bee86e-9860-49d1-a305-ad63dde4f13c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084385991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
4084385991
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.689708501
Short name T296
Test name
Test status
Simulation time 384096841 ps
CPU time 0.93 seconds
Started Jul 16 07:27:44 PM PDT 24
Finished Jul 16 07:27:58 PM PDT 24
Peak memory 205016 kb
Host smart-e5b114c5-9479-46b5-a203-be53b26b2965
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689708501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.689708501
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1154272516
Short name T108
Test name
Test status
Simulation time 342117677 ps
CPU time 4.28 seconds
Started Jul 16 07:27:42 PM PDT 24
Finished Jul 16 07:28:00 PM PDT 24
Peak memory 205464 kb
Host smart-ff406238-b6f9-4294-926b-c11dd724e007
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154272516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1154272516
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2063030122
Short name T425
Test name
Test status
Simulation time 174469630 ps
CPU time 2.27 seconds
Started Jul 16 07:27:43 PM PDT 24
Finished Jul 16 07:27:58 PM PDT 24
Peak memory 213656 kb
Host smart-30060539-60a9-4eb5-a37e-30a4bf8a1650
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063030122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2063030122
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4002016428
Short name T143
Test name
Test status
Simulation time 4669673304 ps
CPU time 21.37 seconds
Started Jul 16 07:27:45 PM PDT 24
Finished Jul 16 07:28:21 PM PDT 24
Peak memory 213724 kb
Host smart-85a7a8d1-fd41-45fb-8136-67e8c08d7b39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002016428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4
002016428
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1486176364
Short name T363
Test name
Test status
Simulation time 12806244139 ps
CPU time 33.88 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:28:06 PM PDT 24
Peak memory 205468 kb
Host smart-d1caecca-7050-4315-8f38-f7f6af465f13
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486176364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1486176364
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.427305888
Short name T122
Test name
Test status
Simulation time 2946461438 ps
CPU time 26.63 seconds
Started Jul 16 07:27:03 PM PDT 24
Finished Jul 16 07:28:01 PM PDT 24
Peak memory 213644 kb
Host smart-40f0b06d-d371-4e16-ae6d-633b9d49e51b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427305888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.427305888
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1404931722
Short name T329
Test name
Test status
Simulation time 223942494 ps
CPU time 2.25 seconds
Started Jul 16 07:27:00 PM PDT 24
Finished Jul 16 07:27:30 PM PDT 24
Peak memory 213600 kb
Host smart-4019baa7-11b7-4c8c-8536-a19b366ecab4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404931722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1404931722
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2216949191
Short name T320
Test name
Test status
Simulation time 206754849 ps
CPU time 2.47 seconds
Started Jul 16 07:27:07 PM PDT 24
Finished Jul 16 07:27:40 PM PDT 24
Peak memory 216888 kb
Host smart-b1b3576b-7d88-4e56-8d6c-c1d32faae6e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216949191 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2216949191
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3245345862
Short name T131
Test name
Test status
Simulation time 303547811 ps
CPU time 2.26 seconds
Started Jul 16 07:27:06 PM PDT 24
Finished Jul 16 07:27:38 PM PDT 24
Peak memory 213516 kb
Host smart-0ab70187-9284-4c7c-a732-134fe298d44a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245345862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3245345862
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2907367932
Short name T422
Test name
Test status
Simulation time 91263869241 ps
CPU time 97.42 seconds
Started Jul 16 07:27:05 PM PDT 24
Finished Jul 16 07:29:13 PM PDT 24
Peak memory 205268 kb
Host smart-16a81b7c-fc8c-4e21-ba65-5b4e85e30f64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907367932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2907367932
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1109499809
Short name T311
Test name
Test status
Simulation time 22883795068 ps
CPU time 62.88 seconds
Started Jul 16 07:27:00 PM PDT 24
Finished Jul 16 07:28:35 PM PDT 24
Peak memory 205332 kb
Host smart-2b531871-3fe4-4eaa-a00d-bdb6bd2ab64c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109499809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1109499809
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.4055882367
Short name T117
Test name
Test status
Simulation time 7315762347 ps
CPU time 12.82 seconds
Started Jul 16 07:27:00 PM PDT 24
Finished Jul 16 07:27:43 PM PDT 24
Peak memory 205432 kb
Host smart-34837712-c990-48cb-b350-65ac71bbabae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055882367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.4055882367
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1653988924
Short name T418
Test name
Test status
Simulation time 2742904126 ps
CPU time 3.02 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:27:35 PM PDT 24
Peak memory 205260 kb
Host smart-080ceff7-88a9-47bf-946d-798cc47e0cb2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653988924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
653988924
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3379473185
Short name T305
Test name
Test status
Simulation time 327820794 ps
CPU time 1.27 seconds
Started Jul 16 07:27:01 PM PDT 24
Finished Jul 16 07:27:33 PM PDT 24
Peak memory 204992 kb
Host smart-f538971d-8559-452d-8aa5-db8aaf5fe6bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379473185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3379473185
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1445362730
Short name T290
Test name
Test status
Simulation time 35013174858 ps
CPU time 26.13 seconds
Started Jul 16 07:27:04 PM PDT 24
Finished Jul 16 07:28:01 PM PDT 24
Peak memory 205324 kb
Host smart-c40c8bc0-2d79-4e72-9ec2-598a197ab2ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445362730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1445362730
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1852488724
Short name T428
Test name
Test status
Simulation time 1271986485 ps
CPU time 1.13 seconds
Started Jul 16 07:27:01 PM PDT 24
Finished Jul 16 07:27:33 PM PDT 24
Peak memory 204944 kb
Host smart-98b8cbf6-82ba-42eb-b525-c98398ba372b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852488724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1852488724
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3501384234
Short name T86
Test name
Test status
Simulation time 199928325 ps
CPU time 1.09 seconds
Started Jul 16 07:27:00 PM PDT 24
Finished Jul 16 07:27:32 PM PDT 24
Peak memory 204992 kb
Host smart-0123996f-751e-4cdb-aee2-f1de91e846db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501384234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
501384234
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3086421308
Short name T335
Test name
Test status
Simulation time 87425548 ps
CPU time 0.78 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:27:33 PM PDT 24
Peak memory 204980 kb
Host smart-b852d002-2caf-413b-9170-1e41b99ad5b7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086421308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3086421308
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2922622062
Short name T287
Test name
Test status
Simulation time 57867735 ps
CPU time 0.72 seconds
Started Jul 16 07:27:00 PM PDT 24
Finished Jul 16 07:27:31 PM PDT 24
Peak memory 204980 kb
Host smart-7dc6d7d8-a33f-4134-aa41-394cca910d50
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922622062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2922622062
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.463744453
Short name T128
Test name
Test status
Simulation time 522451607 ps
CPU time 6.11 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:27:38 PM PDT 24
Peak memory 205448 kb
Host smart-05c0595d-17e9-492c-8ebc-ba186ff448ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463744453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.463744453
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1076103443
Short name T340
Test name
Test status
Simulation time 676184620 ps
CPU time 2.96 seconds
Started Jul 16 07:27:07 PM PDT 24
Finished Jul 16 07:27:40 PM PDT 24
Peak memory 213296 kb
Host smart-e814f549-9656-4999-bdda-0324670ff769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076103443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1076103443
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.137510106
Short name T366
Test name
Test status
Simulation time 2953603011 ps
CPU time 26.86 seconds
Started Jul 16 07:27:01 PM PDT 24
Finished Jul 16 07:27:58 PM PDT 24
Peak memory 205464 kb
Host smart-e688b7b8-c3b1-4693-bad6-a2217211b360
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137510106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.137510106
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3196466747
Short name T132
Test name
Test status
Simulation time 160626832 ps
CPU time 1.61 seconds
Started Jul 16 07:27:01 PM PDT 24
Finished Jul 16 07:27:33 PM PDT 24
Peak memory 213576 kb
Host smart-72c0274a-7b4c-4b1b-a48e-93a668f9b8bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196466747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3196466747
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.757613977
Short name T336
Test name
Test status
Simulation time 486737524 ps
CPU time 2.67 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:27:34 PM PDT 24
Peak memory 218224 kb
Host smart-bc221e9a-026f-4030-b9ab-25a408247fa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757613977 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.757613977
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.3480390965
Short name T417
Test name
Test status
Simulation time 446433560 ps
CPU time 2.42 seconds
Started Jul 16 07:27:01 PM PDT 24
Finished Jul 16 07:27:34 PM PDT 24
Peak memory 213580 kb
Host smart-b331bca0-148e-4df3-aac4-c797ddff81dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480390965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.3480390965
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.783730127
Short name T402
Test name
Test status
Simulation time 34873378264 ps
CPU time 49.92 seconds
Started Jul 16 07:27:00 PM PDT 24
Finished Jul 16 07:28:22 PM PDT 24
Peak memory 205292 kb
Host smart-e2d08ff6-60a4-4f0a-89ae-5bc23cbd326d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783730127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.783730127
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.732800540
Short name T397
Test name
Test status
Simulation time 26472815973 ps
CPU time 79.89 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:28:52 PM PDT 24
Peak memory 205436 kb
Host smart-34679ad0-57ac-499f-8d88-4e88b2c42f3b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732800540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
v_dm_jtag_dmi_csr_bit_bash.732800540
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.1061992556
Short name T118
Test name
Test status
Simulation time 12227962634 ps
CPU time 18.19 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:27:50 PM PDT 24
Peak memory 205372 kb
Host smart-b67a9994-4446-4d2b-b371-4c431dfd51a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061992556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.1061992556
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1085622801
Short name T288
Test name
Test status
Simulation time 2526786631 ps
CPU time 4.61 seconds
Started Jul 16 07:27:00 PM PDT 24
Finished Jul 16 07:27:35 PM PDT 24
Peak memory 205260 kb
Host smart-efb422c2-78a5-4886-8e00-28cf6c8b3045
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085622801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
085622801
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.785976201
Short name T429
Test name
Test status
Simulation time 1264475516 ps
CPU time 1.95 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:27:34 PM PDT 24
Peak memory 205044 kb
Host smart-cc8256f2-fa0d-46c9-9c41-3fe420256e51
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785976201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.785976201
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2832341529
Short name T293
Test name
Test status
Simulation time 11669567315 ps
CPU time 8.45 seconds
Started Jul 16 07:27:01 PM PDT 24
Finished Jul 16 07:27:40 PM PDT 24
Peak memory 205280 kb
Host smart-62775b17-a68f-497f-a49f-c6b71dc9afe3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832341529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2832341529
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2582782205
Short name T374
Test name
Test status
Simulation time 266844337 ps
CPU time 0.82 seconds
Started Jul 16 07:27:01 PM PDT 24
Finished Jul 16 07:27:33 PM PDT 24
Peak memory 205084 kb
Host smart-627d8665-2aca-4989-9fec-997b6a926e91
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582782205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2582782205
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.870980749
Short name T299
Test name
Test status
Simulation time 132191484 ps
CPU time 0.94 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:27:32 PM PDT 24
Peak memory 204992 kb
Host smart-b3ce8346-0653-4bfc-b9f1-3b0285b50de0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870980749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.870980749
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1283761036
Short name T414
Test name
Test status
Simulation time 64682423 ps
CPU time 0.75 seconds
Started Jul 16 07:27:03 PM PDT 24
Finished Jul 16 07:27:35 PM PDT 24
Peak memory 205020 kb
Host smart-91c35ead-2d02-4447-8ad0-5e1db4fdcaef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283761036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1283761036
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1811123025
Short name T284
Test name
Test status
Simulation time 212972603 ps
CPU time 0.74 seconds
Started Jul 16 07:27:06 PM PDT 24
Finished Jul 16 07:27:36 PM PDT 24
Peak memory 205028 kb
Host smart-86ae8664-0786-4239-8ec5-2ef4c07b502c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811123025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1811123025
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.640979507
Short name T129
Test name
Test status
Simulation time 1146781782 ps
CPU time 6.59 seconds
Started Jul 16 07:27:03 PM PDT 24
Finished Jul 16 07:27:39 PM PDT 24
Peak memory 205456 kb
Host smart-a8283bcb-5f41-4096-9373-d7d35cd8fd57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640979507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.640979507
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.320374991
Short name T180
Test name
Test status
Simulation time 63045016087 ps
CPU time 77.85 seconds
Started Jul 16 07:27:05 PM PDT 24
Finished Jul 16 07:28:52 PM PDT 24
Peak memory 221984 kb
Host smart-1b2246a4-6512-4cde-80a9-0dd3d155dc5c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320374991 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.320374991
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4141851631
Short name T96
Test name
Test status
Simulation time 91882654 ps
CPU time 2.18 seconds
Started Jul 16 07:27:06 PM PDT 24
Finished Jul 16 07:27:38 PM PDT 24
Peak memory 213676 kb
Host smart-e855d4b4-7ab3-4a61-9da1-69c3dc934d28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141851631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4141851631
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2873099443
Short name T91
Test name
Test status
Simulation time 2857531101 ps
CPU time 14.66 seconds
Started Jul 16 07:27:05 PM PDT 24
Finished Jul 16 07:27:50 PM PDT 24
Peak memory 213596 kb
Host smart-7c66bc29-813a-42b0-aa7b-577cfdd5e727
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873099443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2873099443
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4104608930
Short name T100
Test name
Test status
Simulation time 7043632751 ps
CPU time 76.57 seconds
Started Jul 16 07:27:05 PM PDT 24
Finished Jul 16 07:28:52 PM PDT 24
Peak memory 219812 kb
Host smart-5f9d43b1-5572-4ecd-aebd-d36b171f67d8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104608930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.4104608930
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2845490100
Short name T134
Test name
Test status
Simulation time 1452652164 ps
CPU time 52.39 seconds
Started Jul 16 07:27:13 PM PDT 24
Finished Jul 16 07:28:31 PM PDT 24
Peak memory 213556 kb
Host smart-52074bce-aaaf-4f3f-8579-9295e38fab8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845490100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2845490100
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2091060663
Short name T423
Test name
Test status
Simulation time 231580419 ps
CPU time 1.74 seconds
Started Jul 16 07:27:13 PM PDT 24
Finished Jul 16 07:27:40 PM PDT 24
Peak memory 213564 kb
Host smart-6492987f-fabe-40d1-8088-548b249d7ffd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091060663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2091060663
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.115892373
Short name T322
Test name
Test status
Simulation time 7373563418 ps
CPU time 9.21 seconds
Started Jul 16 07:27:14 PM PDT 24
Finished Jul 16 07:27:48 PM PDT 24
Peak memory 222024 kb
Host smart-d2842393-7f12-4452-9c52-d1648ff74fe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115892373 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.115892373
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2960725867
Short name T389
Test name
Test status
Simulation time 223021642 ps
CPU time 2.15 seconds
Started Jul 16 07:27:14 PM PDT 24
Finished Jul 16 07:27:41 PM PDT 24
Peak memory 213580 kb
Host smart-d704e6e1-94cc-4125-aecc-4cb56c979d1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960725867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2960725867
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3102466198
Short name T294
Test name
Test status
Simulation time 43004488256 ps
CPU time 119.66 seconds
Started Jul 16 07:27:03 PM PDT 24
Finished Jul 16 07:29:33 PM PDT 24
Peak memory 205324 kb
Host smart-d1bb1dfb-2ae8-48d0-a8da-04b37af3f030
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102466198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.3102466198
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.4177479106
Short name T306
Test name
Test status
Simulation time 7208300679 ps
CPU time 4.93 seconds
Started Jul 16 07:27:05 PM PDT 24
Finished Jul 16 07:27:41 PM PDT 24
Peak memory 205320 kb
Host smart-20a1e4a6-5229-4184-8d93-2d38c8a0074b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177479106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.4177479106
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3842195927
Short name T116
Test name
Test status
Simulation time 14478742404 ps
CPU time 7.28 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:27:39 PM PDT 24
Peak memory 205452 kb
Host smart-98b8c741-f97d-4512-bf77-38ba1bdc074e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842195927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3842195927
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3680934379
Short name T334
Test name
Test status
Simulation time 1739146898 ps
CPU time 1.74 seconds
Started Jul 16 07:27:03 PM PDT 24
Finished Jul 16 07:27:35 PM PDT 24
Peak memory 205200 kb
Host smart-0ad76a03-1d9e-4c76-8af4-0bf9a8665478
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680934379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
680934379
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.920151128
Short name T346
Test name
Test status
Simulation time 833334757 ps
CPU time 0.89 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:27:33 PM PDT 24
Peak memory 205032 kb
Host smart-19546f14-7b39-45c2-9ed1-07211a9df1e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920151128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.920151128
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3451618899
Short name T344
Test name
Test status
Simulation time 23353355577 ps
CPU time 20.33 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:27:52 PM PDT 24
Peak memory 205392 kb
Host smart-5824eb9e-6ab9-46b0-9f57-c3c8588ac99f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451618899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3451618899
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1366864472
Short name T85
Test name
Test status
Simulation time 718950778 ps
CPU time 1.17 seconds
Started Jul 16 07:27:02 PM PDT 24
Finished Jul 16 07:27:33 PM PDT 24
Peak memory 205048 kb
Host smart-b1ee1906-5eae-4efa-8103-a2c40ff65ee4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366864472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1366864472
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.915218285
Short name T371
Test name
Test status
Simulation time 487457417 ps
CPU time 1.12 seconds
Started Jul 16 07:27:03 PM PDT 24
Finished Jul 16 07:27:36 PM PDT 24
Peak memory 205012 kb
Host smart-55ce18ef-b0b0-4786-8e59-720933b929c5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915218285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.915218285
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.649977220
Short name T309
Test name
Test status
Simulation time 142751888 ps
CPU time 1 seconds
Started Jul 16 07:27:13 PM PDT 24
Finished Jul 16 07:27:40 PM PDT 24
Peak memory 205024 kb
Host smart-ed6bb448-8afe-4bc6-9656-2f57f0a1201d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649977220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.649977220
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3417383572
Short name T367
Test name
Test status
Simulation time 93865543 ps
CPU time 0.92 seconds
Started Jul 16 07:27:13 PM PDT 24
Finished Jul 16 07:27:40 PM PDT 24
Peak memory 205028 kb
Host smart-aab35b0a-1159-4212-b6e8-f2a368e5ff18
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417383572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3417383572
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.884294671
Short name T139
Test name
Test status
Simulation time 304423728 ps
CPU time 3.55 seconds
Started Jul 16 07:27:13 PM PDT 24
Finished Jul 16 07:27:43 PM PDT 24
Peak memory 205428 kb
Host smart-049b6f77-22c4-4761-8b8c-c19576439f40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884294671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.884294671
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3115782070
Short name T88
Test name
Test status
Simulation time 100972980 ps
CPU time 2.36 seconds
Started Jul 16 07:27:13 PM PDT 24
Finished Jul 16 07:27:41 PM PDT 24
Peak memory 213656 kb
Host smart-7e7a88e0-cea6-4bc6-9e7b-196e298285d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115782070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3115782070
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.751347097
Short name T178
Test name
Test status
Simulation time 1390317845 ps
CPU time 17.02 seconds
Started Jul 16 07:27:13 PM PDT 24
Finished Jul 16 07:27:56 PM PDT 24
Peak memory 213592 kb
Host smart-862cbd7c-7000-4cb9-b652-1c0b1bddbac4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751347097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.751347097
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.718105268
Short name T92
Test name
Test status
Simulation time 1347991442 ps
CPU time 2.26 seconds
Started Jul 16 07:27:13 PM PDT 24
Finished Jul 16 07:27:41 PM PDT 24
Peak memory 217372 kb
Host smart-db6b280f-c8f5-4e51-96d7-dec96dcdcab0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718105268 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.718105268
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.1505276379
Short name T345
Test name
Test status
Simulation time 197673076 ps
CPU time 1.58 seconds
Started Jul 16 07:27:13 PM PDT 24
Finished Jul 16 07:27:41 PM PDT 24
Peak memory 213448 kb
Host smart-befb78ae-8ef7-4da8-b990-fcfb53a06eb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505276379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.1505276379
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3973166638
Short name T314
Test name
Test status
Simulation time 13443826842 ps
CPU time 35.07 seconds
Started Jul 16 07:27:15 PM PDT 24
Finished Jul 16 07:28:15 PM PDT 24
Peak memory 205436 kb
Host smart-c1266612-86d4-43c6-8ef0-e1699fc22a7d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973166638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3973166638
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2906084735
Short name T303
Test name
Test status
Simulation time 1956504136 ps
CPU time 2.59 seconds
Started Jul 16 07:27:12 PM PDT 24
Finished Jul 16 07:27:41 PM PDT 24
Peak memory 205200 kb
Host smart-32e013d4-d8bd-4c77-b693-f74116852820
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906084735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
906084735
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.4140374755
Short name T408
Test name
Test status
Simulation time 314237041 ps
CPU time 1.1 seconds
Started Jul 16 07:27:13 PM PDT 24
Finished Jul 16 07:27:40 PM PDT 24
Peak memory 204988 kb
Host smart-2a1e1dd0-a6ab-42d4-b55a-f900c19fbf0c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140374755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.4
140374755
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.386462077
Short name T104
Test name
Test status
Simulation time 92797106 ps
CPU time 3.54 seconds
Started Jul 16 07:27:14 PM PDT 24
Finished Jul 16 07:27:43 PM PDT 24
Peak memory 205416 kb
Host smart-002f9681-7387-45ef-8957-970319d4b160
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386462077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.386462077
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.714706561
Short name T328
Test name
Test status
Simulation time 524543108 ps
CPU time 2.79 seconds
Started Jul 16 07:27:13 PM PDT 24
Finished Jul 16 07:27:42 PM PDT 24
Peak memory 213664 kb
Host smart-dca3427a-3420-4557-8187-cfe4a14bd283
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714706561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.714706561
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3842590817
Short name T173
Test name
Test status
Simulation time 2922150065 ps
CPU time 25.14 seconds
Started Jul 16 07:27:13 PM PDT 24
Finished Jul 16 07:28:04 PM PDT 24
Peak memory 213668 kb
Host smart-77845590-26bf-48d9-9e51-0714f1bb8b66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842590817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3842590817
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.287601245
Short name T373
Test name
Test status
Simulation time 478203350 ps
CPU time 2.37 seconds
Started Jul 16 07:27:25 PM PDT 24
Finished Jul 16 07:27:48 PM PDT 24
Peak memory 221876 kb
Host smart-e0325e71-cd38-4e8b-8f95-2b7a89836248
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287601245 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.287601245
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1533120276
Short name T101
Test name
Test status
Simulation time 150534632 ps
CPU time 1.53 seconds
Started Jul 16 07:27:31 PM PDT 24
Finished Jul 16 07:27:50 PM PDT 24
Peak memory 213568 kb
Host smart-071bd6c0-2933-481c-a894-da174954a84b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533120276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1533120276
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1047931112
Short name T412
Test name
Test status
Simulation time 112350024848 ps
CPU time 76.98 seconds
Started Jul 16 07:27:15 PM PDT 24
Finished Jul 16 07:28:56 PM PDT 24
Peak memory 205312 kb
Host smart-bee4c023-d9fa-4397-a169-8f9fc43af46d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047931112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.1047931112
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2188893146
Short name T360
Test name
Test status
Simulation time 3772474791 ps
CPU time 3.68 seconds
Started Jul 16 07:27:15 PM PDT 24
Finished Jul 16 07:27:44 PM PDT 24
Peak memory 205264 kb
Host smart-1ac791eb-6081-4871-bff6-ee1607bf3e0e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188893146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
188893146
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3052032149
Short name T319
Test name
Test status
Simulation time 367731690 ps
CPU time 1.6 seconds
Started Jul 16 07:27:15 PM PDT 24
Finished Jul 16 07:27:41 PM PDT 24
Peak memory 204860 kb
Host smart-ffcdc5a0-caeb-4cb2-8a69-bcb3486224d5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052032149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3
052032149
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.1325992365
Short name T369
Test name
Test status
Simulation time 450714283 ps
CPU time 7.72 seconds
Started Jul 16 07:27:25 PM PDT 24
Finished Jul 16 07:27:53 PM PDT 24
Peak memory 205336 kb
Host smart-8f360aa7-e63e-479f-b4a2-5e4eeae42dc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325992365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.1325992365
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.692678513
Short name T83
Test name
Test status
Simulation time 62382988000 ps
CPU time 173.51 seconds
Started Jul 16 07:27:14 PM PDT 24
Finished Jul 16 07:30:33 PM PDT 24
Peak memory 224820 kb
Host smart-44a856c8-749f-4909-9f72-9c4b81c0df5d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692678513 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.692678513
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2912986553
Short name T297
Test name
Test status
Simulation time 142178961 ps
CPU time 2.61 seconds
Started Jul 16 07:27:13 PM PDT 24
Finished Jul 16 07:27:42 PM PDT 24
Peak memory 213628 kb
Host smart-6b0b244f-f7bc-4030-b7dd-ec15d51d1a63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912986553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2912986553
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2335360030
Short name T90
Test name
Test status
Simulation time 7460677313 ps
CPU time 25.97 seconds
Started Jul 16 07:27:15 PM PDT 24
Finished Jul 16 07:28:06 PM PDT 24
Peak memory 213564 kb
Host smart-0987cdfb-bfee-42d0-a945-1f68753e6802
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335360030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2335360030
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1804021005
Short name T400
Test name
Test status
Simulation time 1732770994 ps
CPU time 3.51 seconds
Started Jul 16 07:27:28 PM PDT 24
Finished Jul 16 07:27:52 PM PDT 24
Peak memory 218172 kb
Host smart-372d0887-1760-4674-8f36-3dc1682d7f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804021005 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1804021005
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.566608725
Short name T298
Test name
Test status
Simulation time 291471028 ps
CPU time 1.61 seconds
Started Jul 16 07:27:27 PM PDT 24
Finished Jul 16 07:27:48 PM PDT 24
Peak memory 213600 kb
Host smart-caa4fe7e-eb35-48f9-9e57-a4541c3a0c00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566608725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.566608725
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1480816994
Short name T291
Test name
Test status
Simulation time 2490233400 ps
CPU time 2.65 seconds
Started Jul 16 07:27:27 PM PDT 24
Finished Jul 16 07:27:50 PM PDT 24
Peak memory 205312 kb
Host smart-910c5993-5672-4f01-8d8a-48fe569a38ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480816994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.1480816994
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1237245031
Short name T333
Test name
Test status
Simulation time 2185086302 ps
CPU time 2.38 seconds
Started Jul 16 07:27:26 PM PDT 24
Finished Jul 16 07:27:49 PM PDT 24
Peak memory 205172 kb
Host smart-11392df2-59bb-4ab7-8533-dc3d9fc53f10
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237245031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
237245031
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3826738792
Short name T358
Test name
Test status
Simulation time 200133072 ps
CPU time 0.73 seconds
Started Jul 16 07:27:24 PM PDT 24
Finished Jul 16 07:27:45 PM PDT 24
Peak memory 204960 kb
Host smart-56555c5d-7a3e-4e62-8b8c-3408e4facd80
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826738792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
826738792
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3560985054
Short name T126
Test name
Test status
Simulation time 306781810 ps
CPU time 3.95 seconds
Started Jul 16 07:27:26 PM PDT 24
Finished Jul 16 07:27:50 PM PDT 24
Peak memory 205380 kb
Host smart-734a7825-622b-4e12-bd23-7c4071ab4d6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560985054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3560985054
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.4205201261
Short name T343
Test name
Test status
Simulation time 50613150516 ps
CPU time 147.85 seconds
Started Jul 16 07:27:25 PM PDT 24
Finished Jul 16 07:30:13 PM PDT 24
Peak memory 222572 kb
Host smart-45ef1fbb-d15c-4d58-b336-a14d9bf64512
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205201261 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.4205201261
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.4107671588
Short name T97
Test name
Test status
Simulation time 195164101 ps
CPU time 4.78 seconds
Started Jul 16 07:27:30 PM PDT 24
Finished Jul 16 07:27:54 PM PDT 24
Peak memory 213732 kb
Host smart-f69df2d6-68a3-4513-8b37-2ebb5ad0cb00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107671588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.4107671588
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3830088261
Short name T421
Test name
Test status
Simulation time 1371075994 ps
CPU time 11.41 seconds
Started Jul 16 07:27:26 PM PDT 24
Finished Jul 16 07:27:58 PM PDT 24
Peak memory 213624 kb
Host smart-8ed7316e-0ed1-4a07-bdc1-669759948afd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830088261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3830088261
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2946847541
Short name T382
Test name
Test status
Simulation time 3851563688 ps
CPU time 3.95 seconds
Started Jul 16 07:27:30 PM PDT 24
Finished Jul 16 07:27:53 PM PDT 24
Peak memory 218656 kb
Host smart-8ccefa2d-27fa-403d-aae6-09e7dd5aa5c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946847541 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2946847541
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2688109074
Short name T339
Test name
Test status
Simulation time 126401278 ps
CPU time 1.56 seconds
Started Jul 16 07:27:25 PM PDT 24
Finished Jul 16 07:27:48 PM PDT 24
Peak memory 213536 kb
Host smart-5336d21b-0d70-4060-ba33-39f6bd2c0169
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688109074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2688109074
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.901801160
Short name T282
Test name
Test status
Simulation time 8974506839 ps
CPU time 23.53 seconds
Started Jul 16 07:27:31 PM PDT 24
Finished Jul 16 07:28:12 PM PDT 24
Peak memory 205348 kb
Host smart-1209f2c2-56ad-4050-98b3-7411febdc754
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901801160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
v_dm_jtag_dmi_csr_bit_bash.901801160
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.4218604211
Short name T327
Test name
Test status
Simulation time 3023400004 ps
CPU time 2.82 seconds
Started Jul 16 07:27:26 PM PDT 24
Finished Jul 16 07:27:50 PM PDT 24
Peak memory 205200 kb
Host smart-970b30db-3710-48c5-9b51-72d5042526ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218604211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.4
218604211
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.580145883
Short name T361
Test name
Test status
Simulation time 483699514 ps
CPU time 0.98 seconds
Started Jul 16 07:27:28 PM PDT 24
Finished Jul 16 07:27:50 PM PDT 24
Peak memory 205012 kb
Host smart-3745d093-23b7-461f-ad91-8861195ed452
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580145883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.580145883
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2054673862
Short name T411
Test name
Test status
Simulation time 328445034 ps
CPU time 3.8 seconds
Started Jul 16 07:27:24 PM PDT 24
Finished Jul 16 07:27:47 PM PDT 24
Peak memory 205392 kb
Host smart-aea312a8-8b68-4ba6-b4f6-331333e4a9ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054673862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2054673862
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.3647313454
Short name T386
Test name
Test status
Simulation time 35893339420 ps
CPU time 60.08 seconds
Started Jul 16 07:27:29 PM PDT 24
Finished Jul 16 07:28:49 PM PDT 24
Peak memory 222044 kb
Host smart-e028d08b-f727-40da-9f06-b076bf577a2a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647313454 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.3647313454
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1601926490
Short name T350
Test name
Test status
Simulation time 184609762 ps
CPU time 3.29 seconds
Started Jul 16 07:27:26 PM PDT 24
Finished Jul 16 07:27:50 PM PDT 24
Peak memory 213640 kb
Host smart-564f8b29-7e68-4b65-8592-6bd5d69d354f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601926490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1601926490
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1866078191
Short name T342
Test name
Test status
Simulation time 1172909896 ps
CPU time 8.83 seconds
Started Jul 16 07:27:26 PM PDT 24
Finished Jul 16 07:27:56 PM PDT 24
Peak memory 213604 kb
Host smart-5aee70bf-3e12-4411-9f64-55225569e57a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866078191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1866078191
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2910734438
Short name T398
Test name
Test status
Simulation time 2040971726 ps
CPU time 7.56 seconds
Started Jul 16 07:27:28 PM PDT 24
Finished Jul 16 07:27:56 PM PDT 24
Peak memory 220284 kb
Host smart-f081b704-ac03-47d5-a588-214aaf13573d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910734438 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2910734438
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3700146172
Short name T378
Test name
Test status
Simulation time 226911973 ps
CPU time 1.54 seconds
Started Jul 16 07:27:26 PM PDT 24
Finished Jul 16 07:27:48 PM PDT 24
Peak memory 213528 kb
Host smart-f9654867-8a29-4eab-bbc5-6433ce9477d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700146172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3700146172
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3260445062
Short name T401
Test name
Test status
Simulation time 12309087783 ps
CPU time 10.35 seconds
Started Jul 16 07:27:30 PM PDT 24
Finished Jul 16 07:27:59 PM PDT 24
Peak memory 205320 kb
Host smart-bcb98a1c-397a-49ec-bfc2-c939d25d527b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260445062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3260445062
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.53490236
Short name T332
Test name
Test status
Simulation time 2080528681 ps
CPU time 1.45 seconds
Started Jul 16 07:27:31 PM PDT 24
Finished Jul 16 07:27:50 PM PDT 24
Peak memory 205164 kb
Host smart-adb46868-f410-4e06-9cae-caf378211de6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53490236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.53490236
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3046371254
Short name T331
Test name
Test status
Simulation time 358761118 ps
CPU time 1.15 seconds
Started Jul 16 07:27:27 PM PDT 24
Finished Jul 16 07:27:48 PM PDT 24
Peak memory 204936 kb
Host smart-b5075245-682f-4119-8467-f831019c2973
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046371254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
046371254
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.300655164
Short name T356
Test name
Test status
Simulation time 490614827 ps
CPU time 7.18 seconds
Started Jul 16 07:27:27 PM PDT 24
Finished Jul 16 07:27:54 PM PDT 24
Peak memory 205340 kb
Host smart-0e6a2419-b6e2-4ab9-be51-b97cc99a9bad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300655164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.300655164
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.801602675
Short name T325
Test name
Test status
Simulation time 204809801 ps
CPU time 2.48 seconds
Started Jul 16 07:27:28 PM PDT 24
Finished Jul 16 07:27:51 PM PDT 24
Peak memory 213688 kb
Host smart-dd7636b9-c0b9-4ed2-9701-3473f5297c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801602675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.801602675
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2841498816
Short name T190
Test name
Test status
Simulation time 51205665 ps
CPU time 0.75 seconds
Started Jul 16 07:33:49 PM PDT 24
Finished Jul 16 07:34:12 PM PDT 24
Peak memory 204276 kb
Host smart-226905c9-0bdf-480c-b8c8-34316b43ef7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841498816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2841498816
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.4133333334
Short name T150
Test name
Test status
Simulation time 9194779565 ps
CPU time 27.77 seconds
Started Jul 16 07:33:32 PM PDT 24
Finished Jul 16 07:34:24 PM PDT 24
Peak memory 213696 kb
Host smart-abbfda9d-f1ec-4aa9-a14d-84b536a8b59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133333334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.4133333334
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.347491510
Short name T20
Test name
Test status
Simulation time 731986418 ps
CPU time 1.73 seconds
Started Jul 16 07:33:28 PM PDT 24
Finished Jul 16 07:33:52 PM PDT 24
Peak memory 204980 kb
Host smart-4ebb68da-ac38-40e7-b4d9-477a1704b7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347491510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.347491510
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.4285257739
Short name T188
Test name
Test status
Simulation time 249299007 ps
CPU time 0.76 seconds
Started Jul 16 07:33:28 PM PDT 24
Finished Jul 16 07:33:51 PM PDT 24
Peak memory 205016 kb
Host smart-dbc9d2a0-64de-42fb-9235-4cc9c5bcbc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285257739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.4285257739
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3144577426
Short name T187
Test name
Test status
Simulation time 314526772 ps
CPU time 0.9 seconds
Started Jul 16 07:33:29 PM PDT 24
Finished Jul 16 07:33:55 PM PDT 24
Peak memory 204992 kb
Host smart-da1a6182-1d1a-46d3-89b9-1bc7ded1c7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144577426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3144577426
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.4292772947
Short name T63
Test name
Test status
Simulation time 49727043 ps
CPU time 0.87 seconds
Started Jul 16 07:33:49 PM PDT 24
Finished Jul 16 07:34:13 PM PDT 24
Peak memory 215676 kb
Host smart-0b5c0d5e-4d73-4035-8433-9194deee6b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292772947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.4292772947
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.724307130
Short name T237
Test name
Test status
Simulation time 2949621881 ps
CPU time 9.01 seconds
Started Jul 16 07:33:29 PM PDT 24
Finished Jul 16 07:34:02 PM PDT 24
Peak memory 205464 kb
Host smart-b0752b00-db6c-46a1-9729-f07b12e8be64
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724307130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.724307130
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.552026628
Short name T98
Test name
Test status
Simulation time 478587914 ps
CPU time 1.03 seconds
Started Jul 16 07:33:27 PM PDT 24
Finished Jul 16 07:33:51 PM PDT 24
Peak memory 205036 kb
Host smart-c012df42-4463-41ce-bd2c-5e127eca1548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552026628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.552026628
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2435915177
Short name T160
Test name
Test status
Simulation time 387329952 ps
CPU time 1.71 seconds
Started Jul 16 07:33:28 PM PDT 24
Finished Jul 16 07:33:52 PM PDT 24
Peak memory 205008 kb
Host smart-4947ee01-75e8-4d2e-88be-336e3410c38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435915177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2435915177
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4216856819
Short name T272
Test name
Test status
Simulation time 809728230 ps
CPU time 1.71 seconds
Started Jul 16 07:33:45 PM PDT 24
Finished Jul 16 07:34:07 PM PDT 24
Peak memory 204864 kb
Host smart-d2824b87-2503-4057-89fb-8d419ddb97cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216856819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4216856819
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3948407973
Short name T55
Test name
Test status
Simulation time 3941032996 ps
CPU time 10.51 seconds
Started Jul 16 07:33:45 PM PDT 24
Finished Jul 16 07:34:16 PM PDT 24
Peak memory 205244 kb
Host smart-30b2f9ec-ac4f-4bed-bca0-2e102cd265da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948407973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3948407973
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1384245970
Short name T230
Test name
Test status
Simulation time 682389103 ps
CPU time 2.52 seconds
Started Jul 16 07:33:45 PM PDT 24
Finished Jul 16 07:34:08 PM PDT 24
Peak memory 205024 kb
Host smart-1f13d014-ea28-48f2-8c05-317354335255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384245970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1384245970
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.392511756
Short name T185
Test name
Test status
Simulation time 288564038 ps
CPU time 1.33 seconds
Started Jul 16 07:33:28 PM PDT 24
Finished Jul 16 07:33:51 PM PDT 24
Peak memory 205012 kb
Host smart-24e601d0-f33e-4f9b-a01c-a0887b8cf7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392511756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.392511756
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2689945792
Short name T7
Test name
Test status
Simulation time 1666117016 ps
CPU time 2.78 seconds
Started Jul 16 07:33:28 PM PDT 24
Finished Jul 16 07:33:53 PM PDT 24
Peak memory 205196 kb
Host smart-561bf3f2-5c99-4bab-9ecb-eef672667f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689945792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2689945792
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.614531502
Short name T275
Test name
Test status
Simulation time 517467927 ps
CPU time 1.37 seconds
Started Jul 16 07:33:44 PM PDT 24
Finished Jul 16 07:34:07 PM PDT 24
Peak memory 213404 kb
Host smart-0c81196b-6cca-4f35-88d3-3a528811e24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614531502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.614531502
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3609192273
Short name T42
Test name
Test status
Simulation time 601808893 ps
CPU time 1.59 seconds
Started Jul 16 07:33:45 PM PDT 24
Finished Jul 16 07:34:07 PM PDT 24
Peak memory 205044 kb
Host smart-ab96e94f-a667-4db6-8ed5-2b4a878e1dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609192273 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3609192273
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2779432203
Short name T13
Test name
Test status
Simulation time 2874326775 ps
CPU time 7.86 seconds
Started Jul 16 07:33:30 PM PDT 24
Finished Jul 16 07:34:03 PM PDT 24
Peak memory 213664 kb
Host smart-c7ba7a5a-4472-414c-95c1-33c6fff65906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779432203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2779432203
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2563059166
Short name T145
Test name
Test status
Simulation time 417891841 ps
CPU time 1.34 seconds
Started Jul 16 07:33:31 PM PDT 24
Finished Jul 16 07:33:57 PM PDT 24
Peak memory 205012 kb
Host smart-2157bf4f-a4a9-4698-8da9-0867a37abd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563059166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2563059166
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3010540264
Short name T82
Test name
Test status
Simulation time 9353298421 ps
CPU time 15.63 seconds
Started Jul 16 07:33:27 PM PDT 24
Finished Jul 16 07:34:06 PM PDT 24
Peak memory 205400 kb
Host smart-de32de0d-bbe4-418a-a23f-6aa79b87840c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010540264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3010540264
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.441740332
Short name T46
Test name
Test status
Simulation time 169474183 ps
CPU time 0.99 seconds
Started Jul 16 07:34:01 PM PDT 24
Finished Jul 16 07:34:24 PM PDT 24
Peak memory 205020 kb
Host smart-e95a196f-a580-4b7c-bedd-a18026a1c1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441740332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.441740332
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1878319202
Short name T154
Test name
Test status
Simulation time 126222711 ps
CPU time 0.87 seconds
Started Jul 16 07:34:01 PM PDT 24
Finished Jul 16 07:34:24 PM PDT 24
Peak memory 205040 kb
Host smart-e14d2924-f679-4bc3-94f8-fcc285b3b12f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878319202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1878319202
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1355660569
Short name T260
Test name
Test status
Simulation time 3845493711 ps
CPU time 3.07 seconds
Started Jul 16 07:33:46 PM PDT 24
Finished Jul 16 07:34:11 PM PDT 24
Peak memory 213620 kb
Host smart-eab675aa-bf41-4fe3-aff9-67e16893e581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355660569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1355660569
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.4069806217
Short name T77
Test name
Test status
Simulation time 3614079816 ps
CPU time 10.63 seconds
Started Jul 16 07:33:45 PM PDT 24
Finished Jul 16 07:34:16 PM PDT 24
Peak memory 213680 kb
Host smart-83181067-ded8-4fc8-aefd-d7bf9b6becdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069806217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.4069806217
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2412420256
Short name T6
Test name
Test status
Simulation time 1125762485 ps
CPU time 3.82 seconds
Started Jul 16 07:33:49 PM PDT 24
Finished Jul 16 07:34:15 PM PDT 24
Peak memory 204332 kb
Host smart-a2e9361e-db1e-490b-a8ec-96af63ffb541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412420256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2412420256
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.3543844686
Short name T37
Test name
Test status
Simulation time 651656803 ps
CPU time 2.58 seconds
Started Jul 16 07:34:06 PM PDT 24
Finished Jul 16 07:34:30 PM PDT 24
Peak memory 205024 kb
Host smart-f8f1431c-e684-4ee2-822f-c5ed15fceef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543844686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.3543844686
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.235058871
Short name T33
Test name
Test status
Simulation time 240858490 ps
CPU time 0.9 seconds
Started Jul 16 07:33:46 PM PDT 24
Finished Jul 16 07:34:09 PM PDT 24
Peak memory 204940 kb
Host smart-a3b447d1-25af-46e2-88b3-b5be865fb8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235058871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.235058871
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.904301324
Short name T35
Test name
Test status
Simulation time 143474556 ps
CPU time 0.81 seconds
Started Jul 16 07:34:06 PM PDT 24
Finished Jul 16 07:34:29 PM PDT 24
Peak memory 205028 kb
Host smart-f31918d8-4864-4758-bc12-95f667487f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904301324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.904301324
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.628679130
Short name T168
Test name
Test status
Simulation time 652728342 ps
CPU time 1.47 seconds
Started Jul 16 07:33:47 PM PDT 24
Finished Jul 16 07:34:11 PM PDT 24
Peak memory 205100 kb
Host smart-29ee087a-1b55-4f18-afe0-bcdc7e084e73
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628679130 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl
_access.628679130
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.118760700
Short name T57
Test name
Test status
Simulation time 113501471 ps
CPU time 0.87 seconds
Started Jul 16 07:34:01 PM PDT 24
Finished Jul 16 07:34:23 PM PDT 24
Peak memory 204948 kb
Host smart-0593f880-f94a-4c01-a4a8-953c970f7653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118760700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.118760700
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.190787007
Short name T184
Test name
Test status
Simulation time 1075445778 ps
CPU time 1.48 seconds
Started Jul 16 07:34:03 PM PDT 24
Finished Jul 16 07:34:26 PM PDT 24
Peak memory 204972 kb
Host smart-8089521f-36fb-4a43-b166-e197a40decd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190787007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.190787007
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2952840218
Short name T112
Test name
Test status
Simulation time 165173006 ps
CPU time 0.75 seconds
Started Jul 16 07:33:59 PM PDT 24
Finished Jul 16 07:34:23 PM PDT 24
Peak memory 205028 kb
Host smart-c4a5ecbf-8a9c-451a-92e3-76babb1a4cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952840218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2952840218
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.2103439118
Short name T78
Test name
Test status
Simulation time 120633765 ps
CPU time 0.97 seconds
Started Jul 16 07:34:00 PM PDT 24
Finished Jul 16 07:34:23 PM PDT 24
Peak memory 204988 kb
Host smart-89644f7e-0378-4e2c-9328-978b19216d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103439118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.2103439118
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.496536385
Short name T280
Test name
Test status
Simulation time 414889535 ps
CPU time 0.89 seconds
Started Jul 16 07:34:02 PM PDT 24
Finished Jul 16 07:34:25 PM PDT 24
Peak memory 204920 kb
Host smart-55c88795-3f38-485e-8aff-8346a7e93bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496536385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.496536385
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.361141119
Short name T59
Test name
Test status
Simulation time 5368739510 ps
CPU time 3.68 seconds
Started Jul 16 07:34:02 PM PDT 24
Finished Jul 16 07:34:28 PM PDT 24
Peak memory 205324 kb
Host smart-3092092f-08a2-48e2-ac66-4b5db9017906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361141119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.361141119
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.943325596
Short name T58
Test name
Test status
Simulation time 373333740 ps
CPU time 0.97 seconds
Started Jul 16 07:34:06 PM PDT 24
Finished Jul 16 07:34:29 PM PDT 24
Peak memory 205028 kb
Host smart-2ec54da6-e663-48c1-b446-af7f4a8cd776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943325596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.943325596
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2788684060
Short name T61
Test name
Test status
Simulation time 764112992 ps
CPU time 1.27 seconds
Started Jul 16 07:33:47 PM PDT 24
Finished Jul 16 07:34:11 PM PDT 24
Peak memory 205004 kb
Host smart-b062928e-9041-4120-ae24-10e85b5b670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788684060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2788684060
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2803785348
Short name T186
Test name
Test status
Simulation time 2705293709 ps
CPU time 3.07 seconds
Started Jul 16 07:33:47 PM PDT 24
Finished Jul 16 07:34:13 PM PDT 24
Peak memory 205276 kb
Host smart-28df082f-414d-43f2-b370-08e0cf504168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803785348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2803785348
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.627471962
Short name T65
Test name
Test status
Simulation time 158871562 ps
CPU time 0.92 seconds
Started Jul 16 07:34:00 PM PDT 24
Finished Jul 16 07:34:23 PM PDT 24
Peak memory 213176 kb
Host smart-936db1c1-58e0-4b24-a9f8-649fb57ca88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627471962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.627471962
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1452724943
Short name T45
Test name
Test status
Simulation time 688946296 ps
CPU time 1.75 seconds
Started Jul 16 07:34:01 PM PDT 24
Finished Jul 16 07:34:24 PM PDT 24
Peak memory 204940 kb
Host smart-4692da7e-d946-47c8-92db-ab19fb31b82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452724943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1452724943
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1960719855
Short name T40
Test name
Test status
Simulation time 54233640 ps
CPU time 0.84 seconds
Started Jul 16 07:34:06 PM PDT 24
Finished Jul 16 07:34:29 PM PDT 24
Peak memory 213340 kb
Host smart-571bf954-d0bb-4d13-8a65-1c88311ecec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960719855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1960719855
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3779392243
Short name T87
Test name
Test status
Simulation time 1709281307 ps
CPU time 5.04 seconds
Started Jul 16 07:34:00 PM PDT 24
Finished Jul 16 07:34:27 PM PDT 24
Peak memory 205192 kb
Host smart-cbf863d5-1aee-41fa-aaed-1fa83b66b6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779392243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3779392243
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3713522638
Short name T155
Test name
Test status
Simulation time 2513018090 ps
CPU time 4.98 seconds
Started Jul 16 07:33:47 PM PDT 24
Finished Jul 16 07:34:15 PM PDT 24
Peak memory 205260 kb
Host smart-28a60e89-4b10-4683-821e-20d6698a4393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713522638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3713522638
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3485105628
Short name T73
Test name
Test status
Simulation time 486220545 ps
CPU time 2.14 seconds
Started Jul 16 07:34:01 PM PDT 24
Finished Jul 16 07:34:24 PM PDT 24
Peak memory 229256 kb
Host smart-57daa708-c248-4141-8125-45ffcfa6c56b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485105628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3485105628
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2936598772
Short name T205
Test name
Test status
Simulation time 3453598116 ps
CPU time 3.71 seconds
Started Jul 16 07:33:47 PM PDT 24
Finished Jul 16 07:34:13 PM PDT 24
Peak memory 205088 kb
Host smart-04ddfcd5-73a4-4cc2-a348-6b9b5dabaecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936598772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2936598772
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.4262450305
Short name T222
Test name
Test status
Simulation time 85718902 ps
CPU time 0.78 seconds
Started Jul 16 07:35:02 PM PDT 24
Finished Jul 16 07:35:06 PM PDT 24
Peak memory 205032 kb
Host smart-9924f975-73a9-48e0-ba00-1d92bfd39fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262450305 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.4262450305
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.4235398610
Short name T31
Test name
Test status
Simulation time 8375911127 ps
CPU time 14.86 seconds
Started Jul 16 07:35:02 PM PDT 24
Finished Jul 16 07:35:20 PM PDT 24
Peak memory 205532 kb
Host smart-6857b2e7-f8bf-4cb3-af60-74de0cfcd4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235398610 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.4235398610
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.1319140521
Short name T223
Test name
Test status
Simulation time 8101679588 ps
CPU time 20.56 seconds
Started Jul 16 07:35:02 PM PDT 24
Finished Jul 16 07:35:27 PM PDT 24
Peak memory 221836 kb
Host smart-d109104e-db46-4837-94f9-aff5bbc71de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319140521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.1319140521
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.2267338892
Short name T227
Test name
Test status
Simulation time 6991498455 ps
CPU time 20.79 seconds
Started Jul 16 07:35:01 PM PDT 24
Finished Jul 16 07:35:26 PM PDT 24
Peak memory 213596 kb
Host smart-1e7a3ad2-2dc7-4ad6-bf59-331cd56ac1c9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267338892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.2267338892
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1127500076
Short name T264
Test name
Test status
Simulation time 7410365818 ps
CPU time 12.15 seconds
Started Jul 16 07:35:05 PM PDT 24
Finished Jul 16 07:35:20 PM PDT 24
Peak memory 213668 kb
Host smart-de6a47d8-432d-4d2b-a1a2-95b7329f639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127500076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1127500076
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.4166193632
Short name T156
Test name
Test status
Simulation time 12239846373 ps
CPU time 33.87 seconds
Started Jul 16 07:35:02 PM PDT 24
Finished Jul 16 07:35:40 PM PDT 24
Peak memory 213532 kb
Host smart-baeda61a-86f4-45fa-8e72-24b338f00687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166193632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.4166193632
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3522620021
Short name T269
Test name
Test status
Simulation time 64064030 ps
CPU time 0.73 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:07 PM PDT 24
Peak memory 204964 kb
Host smart-708b1edc-572a-4807-b591-267c18bb1c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522620021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3522620021
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.1951900906
Short name T267
Test name
Test status
Simulation time 13071762012 ps
CPU time 37.46 seconds
Started Jul 16 07:35:06 PM PDT 24
Finished Jul 16 07:35:46 PM PDT 24
Peak memory 213616 kb
Host smart-200f3273-6643-45b2-a7b9-04127fe6316f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951900906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.1951900906
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2457813974
Short name T197
Test name
Test status
Simulation time 678809074 ps
CPU time 1.93 seconds
Started Jul 16 07:35:02 PM PDT 24
Finished Jul 16 07:35:08 PM PDT 24
Peak memory 205348 kb
Host smart-a85fc89d-d654-4c30-b9d2-9a464e5a2e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457813974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2457813974
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.2991164236
Short name T36
Test name
Test status
Simulation time 8930714579 ps
CPU time 5.35 seconds
Started Jul 16 07:35:51 PM PDT 24
Finished Jul 16 07:35:58 PM PDT 24
Peak memory 213492 kb
Host smart-c670c73d-2ca6-4795-9022-44e43b2fc8f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991164236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2991164236
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2600288142
Short name T231
Test name
Test status
Simulation time 80883826 ps
CPU time 0.79 seconds
Started Jul 16 07:35:55 PM PDT 24
Finished Jul 16 07:36:09 PM PDT 24
Peak memory 205000 kb
Host smart-a2784ab6-9a72-4e5a-8827-bf740751a45e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600288142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2600288142
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.484020135
Short name T254
Test name
Test status
Simulation time 135833578833 ps
CPU time 109.19 seconds
Started Jul 16 07:35:52 PM PDT 24
Finished Jul 16 07:37:48 PM PDT 24
Peak memory 214008 kb
Host smart-1ef3a345-9b5b-4605-bf71-444a99ee0c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484020135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.484020135
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.374394334
Short name T251
Test name
Test status
Simulation time 4707752924 ps
CPU time 4.86 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:04 PM PDT 24
Peak memory 213704 kb
Host smart-13b5a5ff-2cf8-4757-95b7-481097d66eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374394334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.374394334
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2032826721
Short name T80
Test name
Test status
Simulation time 5500811033 ps
CPU time 17.55 seconds
Started Jul 16 07:35:50 PM PDT 24
Finished Jul 16 07:36:09 PM PDT 24
Peak memory 205540 kb
Host smart-cc67feb9-96d1-44e5-b203-47703c30a115
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032826721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2032826721
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.710742767
Short name T194
Test name
Test status
Simulation time 3200347945 ps
CPU time 2.27 seconds
Started Jul 16 07:35:52 PM PDT 24
Finished Jul 16 07:35:57 PM PDT 24
Peak memory 205396 kb
Host smart-4753445b-d1eb-46e2-8006-5d3925dc7baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710742767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.710742767
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.2944344777
Short name T66
Test name
Test status
Simulation time 7509049567 ps
CPU time 10.84 seconds
Started Jul 16 07:35:56 PM PDT 24
Finished Jul 16 07:36:22 PM PDT 24
Peak memory 205260 kb
Host smart-a98e15f5-8e2a-4436-98a4-c845d9d34dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944344777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2944344777
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2035475253
Short name T257
Test name
Test status
Simulation time 157250541 ps
CPU time 0.76 seconds
Started Jul 16 07:35:52 PM PDT 24
Finished Jul 16 07:35:56 PM PDT 24
Peak memory 204780 kb
Host smart-3166c2fb-43e1-486f-9eee-6411804c84e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035475253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2035475253
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1195044424
Short name T250
Test name
Test status
Simulation time 63040870472 ps
CPU time 27.07 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:35 PM PDT 24
Peak memory 213764 kb
Host smart-5aba46a1-faeb-435e-b045-871c0f4eafbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195044424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1195044424
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3913229146
Short name T212
Test name
Test status
Simulation time 2004264717 ps
CPU time 4.46 seconds
Started Jul 16 07:35:52 PM PDT 24
Finished Jul 16 07:35:59 PM PDT 24
Peak memory 213544 kb
Host smart-6d16f121-c65e-48ba-927d-277bf8a8952b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913229146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3913229146
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.4253856030
Short name T277
Test name
Test status
Simulation time 655924170 ps
CPU time 1.44 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:05 PM PDT 24
Peak memory 205324 kb
Host smart-1a8121a2-120a-435c-81a0-3f39be6f9472
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4253856030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.4253856030
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.2640583665
Short name T265
Test name
Test status
Simulation time 3714419816 ps
CPU time 6.31 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:06 PM PDT 24
Peak memory 213616 kb
Host smart-7e446e0e-c103-45be-9710-5603d09b08fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640583665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.2640583665
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.971862511
Short name T242
Test name
Test status
Simulation time 88908539 ps
CPU time 0.76 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:07 PM PDT 24
Peak memory 204936 kb
Host smart-0b138c8e-a677-4e09-9986-7aa7736283ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971862511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.971862511
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1506964792
Short name T30
Test name
Test status
Simulation time 22239264816 ps
CPU time 64.75 seconds
Started Jul 16 07:35:51 PM PDT 24
Finished Jul 16 07:36:59 PM PDT 24
Peak memory 213736 kb
Host smart-c6f5969f-2cb4-4b64-aefc-b1a751c73608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506964792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1506964792
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2079451587
Short name T249
Test name
Test status
Simulation time 5196548317 ps
CPU time 5.27 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:11 PM PDT 24
Peak memory 221844 kb
Host smart-40b1697d-6157-4cf6-bd2c-9ec37da16b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079451587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2079451587
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1605577077
Short name T208
Test name
Test status
Simulation time 5776752008 ps
CPU time 16.89 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:16 PM PDT 24
Peak memory 213728 kb
Host smart-ee510df5-f7aa-4469-b411-97be01f626eb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605577077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1605577077
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2807753533
Short name T152
Test name
Test status
Simulation time 951449525 ps
CPU time 1.61 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:08 PM PDT 24
Peak memory 205404 kb
Host smart-7f7c7a55-fc1d-4972-bcb6-c6cdbe75a370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807753533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2807753533
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.128895239
Short name T8
Test name
Test status
Simulation time 2281440616 ps
CPU time 4.76 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:08 PM PDT 24
Peak memory 205224 kb
Host smart-ae246988-0d23-4d7b-a2a6-f696d505d268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128895239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.128895239
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.2922979883
Short name T232
Test name
Test status
Simulation time 82547490 ps
CPU time 0.73 seconds
Started Jul 16 07:35:52 PM PDT 24
Finished Jul 16 07:35:58 PM PDT 24
Peak memory 205036 kb
Host smart-9a414794-1768-4c9e-9cc4-eacc9f41fdb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922979883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.2922979883
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.4052042464
Short name T157
Test name
Test status
Simulation time 9139219738 ps
CPU time 14.45 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:18 PM PDT 24
Peak memory 215652 kb
Host smart-56a83b00-cb7e-4e57-bd72-4aa39e3dd9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052042464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.4052042464
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.444931142
Short name T253
Test name
Test status
Simulation time 3240923420 ps
CPU time 7.27 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:13 PM PDT 24
Peak memory 213624 kb
Host smart-aa229294-4b6e-451a-9d1e-992da1070277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444931142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.444931142
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1746424760
Short name T217
Test name
Test status
Simulation time 1703618030 ps
CPU time 2.45 seconds
Started Jul 16 07:35:56 PM PDT 24
Finished Jul 16 07:36:15 PM PDT 24
Peak memory 213480 kb
Host smart-7e1f3abe-0021-4c54-982e-608701d032d7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1746424760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.1746424760
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.984765842
Short name T115
Test name
Test status
Simulation time 2930967492 ps
CPU time 1.82 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:03 PM PDT 24
Peak memory 213604 kb
Host smart-41f65c00-e5d8-484b-a1b1-cb3343283f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984765842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.984765842
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1006091911
Short name T34
Test name
Test status
Simulation time 4891157895 ps
CPU time 10.41 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:14 PM PDT 24
Peak memory 213516 kb
Host smart-fab08333-7120-4c05-a0a6-431959b9a856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006091911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1006091911
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1951321140
Short name T209
Test name
Test status
Simulation time 71586371 ps
CPU time 0.8 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:00 PM PDT 24
Peak memory 205048 kb
Host smart-6105344c-ab82-4ca2-b502-aae4d1b3bcf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951321140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1951321140
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3768214828
Short name T29
Test name
Test status
Simulation time 22448434218 ps
CPU time 31.65 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:31 PM PDT 24
Peak memory 213728 kb
Host smart-172d7bfc-2fa3-47bf-a462-38e91615c3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768214828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3768214828
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2990089893
Short name T229
Test name
Test status
Simulation time 5518932247 ps
CPU time 6.94 seconds
Started Jul 16 07:35:51 PM PDT 24
Finished Jul 16 07:36:00 PM PDT 24
Peak memory 213720 kb
Host smart-cd174c08-d5e4-4f4d-98bf-b17ce3eae5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990089893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2990089893
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2005599159
Short name T261
Test name
Test status
Simulation time 4608508780 ps
CPU time 14.02 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:14 PM PDT 24
Peak memory 205496 kb
Host smart-676f6d6e-3315-481e-a431-3938bb443b3a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2005599159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2005599159
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2742616203
Short name T167
Test name
Test status
Simulation time 2559302662 ps
CPU time 4.18 seconds
Started Jul 16 07:35:52 PM PDT 24
Finished Jul 16 07:35:58 PM PDT 24
Peak memory 205408 kb
Host smart-63e61f52-536b-4120-99e4-6cab6bc21ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742616203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2742616203
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2605215455
Short name T158
Test name
Test status
Simulation time 5812535697 ps
CPU time 9.47 seconds
Started Jul 16 07:35:52 PM PDT 24
Finished Jul 16 07:36:04 PM PDT 24
Peak memory 205304 kb
Host smart-822f10e3-0e50-43f9-b522-dba27af4c494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605215455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2605215455
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2135803820
Short name T213
Test name
Test status
Simulation time 64181694 ps
CPU time 0.82 seconds
Started Jul 16 07:35:57 PM PDT 24
Finished Jul 16 07:36:16 PM PDT 24
Peak memory 204976 kb
Host smart-01a4cbb0-5aee-4158-9c66-d10f23069c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135803820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2135803820
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.4195649473
Short name T75
Test name
Test status
Simulation time 25129734177 ps
CPU time 28.63 seconds
Started Jul 16 07:35:55 PM PDT 24
Finished Jul 16 07:36:38 PM PDT 24
Peak memory 213552 kb
Host smart-1a04bbd2-6d51-4d43-9812-0e08fbc510a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195649473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.4195649473
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.2745613065
Short name T60
Test name
Test status
Simulation time 8290633729 ps
CPU time 7.03 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:07 PM PDT 24
Peak memory 213612 kb
Host smart-5a030f65-74d6-4fa1-8b74-fbbac2b8dafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745613065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.2745613065
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2768662065
Short name T256
Test name
Test status
Simulation time 1105161192 ps
CPU time 1.7 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:09 PM PDT 24
Peak memory 205264 kb
Host smart-e2101893-4bb2-498b-bb03-457748acd138
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768662065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.2768662065
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3492723753
Short name T240
Test name
Test status
Simulation time 3577964268 ps
CPU time 2.5 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:09 PM PDT 24
Peak memory 205408 kb
Host smart-f58d3e8b-b82e-45f8-99ed-1c0829592f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492723753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3492723753
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2127657878
Short name T245
Test name
Test status
Simulation time 85964641 ps
CPU time 0.76 seconds
Started Jul 16 07:35:57 PM PDT 24
Finished Jul 16 07:36:16 PM PDT 24
Peak memory 204896 kb
Host smart-98baee9e-7001-459b-9dc6-a385453551d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127657878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2127657878
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.4161201778
Short name T148
Test name
Test status
Simulation time 56043292781 ps
CPU time 41.76 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:45 PM PDT 24
Peak memory 213776 kb
Host smart-a8de17ff-f19f-466c-a522-af6e2c6705e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161201778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.4161201778
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.116252666
Short name T49
Test name
Test status
Simulation time 12272039815 ps
CPU time 8.75 seconds
Started Jul 16 07:35:57 PM PDT 24
Finished Jul 16 07:36:24 PM PDT 24
Peak memory 213580 kb
Host smart-98c5948c-9279-427e-94f8-cdf87a944c1a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=116252666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.116252666
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1524380550
Short name T238
Test name
Test status
Simulation time 1509361297 ps
CPU time 1.77 seconds
Started Jul 16 07:35:52 PM PDT 24
Finished Jul 16 07:35:57 PM PDT 24
Peak memory 213376 kb
Host smart-bb351ba2-4053-477c-bf12-f04fbfc6750f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524380550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1524380550
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.4294754878
Short name T234
Test name
Test status
Simulation time 57927605 ps
CPU time 0.72 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:00 PM PDT 24
Peak memory 205044 kb
Host smart-266789a1-da82-4047-a0fd-255389996f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294754878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.4294754878
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.563405609
Short name T72
Test name
Test status
Simulation time 4770904813 ps
CPU time 12.2 seconds
Started Jul 16 07:35:51 PM PDT 24
Finished Jul 16 07:36:04 PM PDT 24
Peak memory 205476 kb
Host smart-ee9f2198-c6a2-4369-85aa-1f99089cd97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563405609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.563405609
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.171653895
Short name T266
Test name
Test status
Simulation time 2188554373 ps
CPU time 2.05 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:10 PM PDT 24
Peak memory 205384 kb
Host smart-e0831233-ba03-4b03-bee4-34336021063c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171653895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.171653895
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.4049152417
Short name T195
Test name
Test status
Simulation time 4979570310 ps
CPU time 4.82 seconds
Started Jul 16 07:35:51 PM PDT 24
Finished Jul 16 07:35:58 PM PDT 24
Peak memory 205520 kb
Host smart-29a99b04-5c0b-4bce-a2ad-7d384620e904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049152417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.4049152417
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.782363634
Short name T226
Test name
Test status
Simulation time 144501669 ps
CPU time 0.76 seconds
Started Jul 16 07:33:59 PM PDT 24
Finished Jul 16 07:34:22 PM PDT 24
Peak memory 205036 kb
Host smart-68ad5cb9-535f-4c5a-a1f4-737e902d7be5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782363634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.782363634
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3667107326
Short name T215
Test name
Test status
Simulation time 16680620130 ps
CPU time 45.33 seconds
Started Jul 16 07:34:00 PM PDT 24
Finished Jul 16 07:35:08 PM PDT 24
Peak memory 213656 kb
Host smart-6b736e16-8e23-4471-8104-ab862580effc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667107326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3667107326
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.245497926
Short name T218
Test name
Test status
Simulation time 3563594541 ps
CPU time 3.67 seconds
Started Jul 16 07:34:09 PM PDT 24
Finished Jul 16 07:34:33 PM PDT 24
Peak memory 213604 kb
Host smart-2e9b96a4-5421-4cae-a685-c8d27d496eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245497926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.245497926
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2132390708
Short name T202
Test name
Test status
Simulation time 2094467189 ps
CPU time 2.62 seconds
Started Jul 16 07:33:59 PM PDT 24
Finished Jul 16 07:34:24 PM PDT 24
Peak memory 213588 kb
Host smart-114a3022-f8af-4032-8daf-bb012cea9b45
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2132390708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2132390708
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2492286549
Short name T47
Test name
Test status
Simulation time 1322083504 ps
CPU time 2.43 seconds
Started Jul 16 07:33:58 PM PDT 24
Finished Jul 16 07:34:23 PM PDT 24
Peak memory 204992 kb
Host smart-3af0442d-ada2-4057-a996-9464114e8e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492286549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2492286549
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.2198290079
Short name T274
Test name
Test status
Simulation time 6429352196 ps
CPU time 17.7 seconds
Started Jul 16 07:34:04 PM PDT 24
Finished Jul 16 07:34:44 PM PDT 24
Peak memory 213740 kb
Host smart-f4a8e0e3-e82b-468e-8d96-df1e7760f1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198290079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2198290079
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.461052296
Short name T54
Test name
Test status
Simulation time 344362081 ps
CPU time 1.13 seconds
Started Jul 16 07:34:07 PM PDT 24
Finished Jul 16 07:34:29 PM PDT 24
Peak memory 236572 kb
Host smart-91c46a13-afcb-4a9e-95cd-f802d438f5c7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461052296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.461052296
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2303708607
Short name T76
Test name
Test status
Simulation time 43087143 ps
CPU time 0.73 seconds
Started Jul 16 07:35:56 PM PDT 24
Finished Jul 16 07:36:12 PM PDT 24
Peak memory 204964 kb
Host smart-f80546b4-fe15-44f5-b5f9-85632bc901a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303708607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2303708607
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3799784133
Short name T224
Test name
Test status
Simulation time 108570384 ps
CPU time 0.82 seconds
Started Jul 16 07:35:56 PM PDT 24
Finished Jul 16 07:36:12 PM PDT 24
Peak memory 204964 kb
Host smart-ed366949-a8a8-4762-8448-a96e00446ec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799784133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3799784133
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.4286380360
Short name T263
Test name
Test status
Simulation time 173614344 ps
CPU time 0.85 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:00 PM PDT 24
Peak memory 205024 kb
Host smart-3c97a70a-517a-449a-af3d-8e954a741f70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286380360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.4286380360
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.2479300658
Short name T18
Test name
Test status
Simulation time 3514200441 ps
CPU time 3.6 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:04 PM PDT 24
Peak memory 213548 kb
Host smart-558eb528-b2bc-4d23-8712-93910d6483f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479300658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2479300658
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.355962525
Short name T2
Test name
Test status
Simulation time 86931787 ps
CPU time 0.73 seconds
Started Jul 16 07:35:55 PM PDT 24
Finished Jul 16 07:36:10 PM PDT 24
Peak memory 204980 kb
Host smart-5a873193-9489-4101-b2b6-7b962bf16f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355962525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.355962525
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.2917200743
Short name T201
Test name
Test status
Simulation time 166178396 ps
CPU time 0.71 seconds
Started Jul 16 07:35:52 PM PDT 24
Finished Jul 16 07:35:55 PM PDT 24
Peak memory 204988 kb
Host smart-fd6d74a8-63fb-40f5-b9bc-8e023604f6d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917200743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.2917200743
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.591526630
Short name T22
Test name
Test status
Simulation time 9334061897 ps
CPU time 23.85 seconds
Started Jul 16 07:35:55 PM PDT 24
Finished Jul 16 07:36:32 PM PDT 24
Peak memory 205400 kb
Host smart-c7f8422d-7f6b-4cea-a205-604a8a11c338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591526630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.591526630
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3339882703
Short name T196
Test name
Test status
Simulation time 124039031 ps
CPU time 0.74 seconds
Started Jul 16 07:35:56 PM PDT 24
Finished Jul 16 07:36:13 PM PDT 24
Peak memory 204984 kb
Host smart-1d5f831e-dd0f-465c-979c-cf12d7477f6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339882703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3339882703
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.3357433343
Short name T183
Test name
Test status
Simulation time 5300507789 ps
CPU time 4.4 seconds
Started Jul 16 07:35:56 PM PDT 24
Finished Jul 16 07:36:15 PM PDT 24
Peak memory 205252 kb
Host smart-fd8febf0-e87e-4467-91dd-c4df0f8e610f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357433343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3357433343
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1154084748
Short name T151
Test name
Test status
Simulation time 95705211 ps
CPU time 0.7 seconds
Started Jul 16 07:35:55 PM PDT 24
Finished Jul 16 07:36:10 PM PDT 24
Peak memory 204892 kb
Host smart-344b12e9-1376-457c-a493-de7567e2de5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154084748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1154084748
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.516282834
Short name T200
Test name
Test status
Simulation time 33013446 ps
CPU time 0.75 seconds
Started Jul 16 07:35:57 PM PDT 24
Finished Jul 16 07:36:15 PM PDT 24
Peak memory 205052 kb
Host smart-31a9b5b1-42b0-4dfd-89e5-20873ce8797c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516282834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.516282834
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.534590670
Short name T236
Test name
Test status
Simulation time 60209330 ps
CPU time 0.83 seconds
Started Jul 16 07:35:56 PM PDT 24
Finished Jul 16 07:36:11 PM PDT 24
Peak memory 204828 kb
Host smart-ab7e8ceb-33d4-4707-80bb-bfe31f460a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534590670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.534590670
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.238016333
Short name T11
Test name
Test status
Simulation time 6133799738 ps
CPU time 4.48 seconds
Started Jul 16 07:35:58 PM PDT 24
Finished Jul 16 07:36:20 PM PDT 24
Peak memory 213500 kb
Host smart-7062c476-0054-4591-9c5e-13eeb3800a7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238016333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.238016333
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1993270349
Short name T140
Test name
Test status
Simulation time 47606357 ps
CPU time 0.76 seconds
Started Jul 16 07:36:02 PM PDT 24
Finished Jul 16 07:36:23 PM PDT 24
Peak memory 204992 kb
Host smart-e402d14b-005b-4fb0-aca4-b2c5d8a936c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993270349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1993270349
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.1181458020
Short name T146
Test name
Test status
Simulation time 6308660282 ps
CPU time 15.72 seconds
Started Jul 16 07:35:55 PM PDT 24
Finished Jul 16 07:36:24 PM PDT 24
Peak memory 213404 kb
Host smart-dafc721e-7819-40b0-8821-1f89771e6b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181458020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1181458020
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.4152488623
Short name T199
Test name
Test status
Simulation time 47373508 ps
CPU time 0.73 seconds
Started Jul 16 07:34:21 PM PDT 24
Finished Jul 16 07:34:38 PM PDT 24
Peak memory 205208 kb
Host smart-11a016f9-d1dc-47c0-aefd-e5a74ecbb640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152488623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.4152488623
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1410126839
Short name T270
Test name
Test status
Simulation time 37475665325 ps
CPU time 29.98 seconds
Started Jul 16 07:34:23 PM PDT 24
Finished Jul 16 07:35:08 PM PDT 24
Peak memory 213708 kb
Host smart-b326e53e-d1c2-4786-a550-21a5c56fd835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410126839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1410126839
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4131982147
Short name T162
Test name
Test status
Simulation time 2248510134 ps
CPU time 3 seconds
Started Jul 16 07:34:01 PM PDT 24
Finished Jul 16 07:34:25 PM PDT 24
Peak memory 205436 kb
Host smart-5182e19f-1b3b-4938-81eb-203839dbd819
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131982147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.4131982147
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1185493386
Short name T204
Test name
Test status
Simulation time 133373206 ps
CPU time 1.03 seconds
Started Jul 16 07:34:20 PM PDT 24
Finished Jul 16 07:34:38 PM PDT 24
Peak memory 204952 kb
Host smart-61e4cafe-4ec8-44bb-b875-b143d61aa33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185493386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1185493386
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.41425024
Short name T164
Test name
Test status
Simulation time 2739999697 ps
CPU time 8.81 seconds
Started Jul 16 07:34:08 PM PDT 24
Finished Jul 16 07:34:39 PM PDT 24
Peak memory 205444 kb
Host smart-0e43496a-04cd-46f5-a553-961e7eb1d4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41425024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.41425024
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1733164076
Short name T53
Test name
Test status
Simulation time 1104248441 ps
CPU time 2.02 seconds
Started Jul 16 07:34:22 PM PDT 24
Finished Jul 16 07:34:40 PM PDT 24
Peak memory 229680 kb
Host smart-b353bbf3-33c8-48a0-8f5c-de4c693f325c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733164076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1733164076
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.2799829582
Short name T4
Test name
Test status
Simulation time 8635992011 ps
CPU time 4.99 seconds
Started Jul 16 07:34:25 PM PDT 24
Finished Jul 16 07:34:44 PM PDT 24
Peak memory 214392 kb
Host smart-a6787c3c-11c6-4d39-bef5-d45f0157d4bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799829582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2799829582
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.525467291
Short name T111
Test name
Test status
Simulation time 91825484 ps
CPU time 0.88 seconds
Started Jul 16 07:36:03 PM PDT 24
Finished Jul 16 07:36:24 PM PDT 24
Peak memory 204992 kb
Host smart-e4c9e372-73ce-42be-883f-ec90a8caef74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525467291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.525467291
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3226490396
Short name T142
Test name
Test status
Simulation time 32587990 ps
CPU time 0.78 seconds
Started Jul 16 07:35:58 PM PDT 24
Finished Jul 16 07:36:18 PM PDT 24
Peak memory 204868 kb
Host smart-bf5a5541-9023-49d5-a16e-ade9564e2bab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226490396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3226490396
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.3540664605
Short name T15
Test name
Test status
Simulation time 5229791988 ps
CPU time 14.09 seconds
Started Jul 16 07:35:30 PM PDT 24
Finished Jul 16 07:35:45 PM PDT 24
Peak memory 205336 kb
Host smart-b0eee836-3c8a-4112-beef-df3eff1a9cb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540664605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.3540664605
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1729250792
Short name T193
Test name
Test status
Simulation time 37866240 ps
CPU time 0.78 seconds
Started Jul 16 07:35:58 PM PDT 24
Finished Jul 16 07:36:18 PM PDT 24
Peak memory 204620 kb
Host smart-74b38087-3f35-4b4b-882c-f3e56387f365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729250792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1729250792
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3397698744
Short name T149
Test name
Test status
Simulation time 100599076 ps
CPU time 0.72 seconds
Started Jul 16 07:35:58 PM PDT 24
Finished Jul 16 07:36:18 PM PDT 24
Peak memory 204640 kb
Host smart-8a3f7fda-e1e1-4148-b164-51835ed02719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397698744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3397698744
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.4079531312
Short name T210
Test name
Test status
Simulation time 172169899 ps
CPU time 0.83 seconds
Started Jul 16 07:35:57 PM PDT 24
Finished Jul 16 07:36:13 PM PDT 24
Peak memory 205004 kb
Host smart-4746c363-8ef8-46fb-b328-5db16ffb39c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079531312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.4079531312
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.1066470318
Short name T64
Test name
Test status
Simulation time 3145624487 ps
CPU time 3.81 seconds
Started Jul 16 07:35:58 PM PDT 24
Finished Jul 16 07:36:19 PM PDT 24
Peak memory 213480 kb
Host smart-9512f53b-ee05-45a6-88cd-4380dc17aa4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066470318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1066470318
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.4164487698
Short name T3
Test name
Test status
Simulation time 236505455 ps
CPU time 0.73 seconds
Started Jul 16 07:35:57 PM PDT 24
Finished Jul 16 07:36:13 PM PDT 24
Peak memory 205004 kb
Host smart-57049fcb-8c55-4242-ac98-3f60c305a915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164487698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.4164487698
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2978611237
Short name T147
Test name
Test status
Simulation time 9039321379 ps
CPU time 4.58 seconds
Started Jul 16 07:36:03 PM PDT 24
Finished Jul 16 07:36:30 PM PDT 24
Peak memory 213524 kb
Host smart-c05a4c53-2395-4fdc-b115-ba7bb63f2e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978611237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2978611237
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3800012117
Short name T276
Test name
Test status
Simulation time 155041201 ps
CPU time 0.91 seconds
Started Jul 16 07:36:03 PM PDT 24
Finished Jul 16 07:36:26 PM PDT 24
Peak memory 205012 kb
Host smart-779e7cfe-75e9-4ba5-81dc-a6ccbd6a0bd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800012117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3800012117
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.3376475519
Short name T23
Test name
Test status
Simulation time 4831229160 ps
CPU time 3.14 seconds
Started Jul 16 07:36:00 PM PDT 24
Finished Jul 16 07:36:24 PM PDT 24
Peak memory 205132 kb
Host smart-fedc2b2e-8f1a-44a6-af0c-575f8c80449a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376475519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.3376475519
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.14755392
Short name T189
Test name
Test status
Simulation time 135246109 ps
CPU time 0.94 seconds
Started Jul 16 07:36:03 PM PDT 24
Finished Jul 16 07:36:26 PM PDT 24
Peak memory 204876 kb
Host smart-2635c989-fb4b-411d-90db-6f23f7764fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14755392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.14755392
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3892718424
Short name T220
Test name
Test status
Simulation time 144337336 ps
CPU time 0.86 seconds
Started Jul 16 07:36:00 PM PDT 24
Finished Jul 16 07:36:21 PM PDT 24
Peak memory 204972 kb
Host smart-e801a468-de73-4364-90d6-c38bbd4ff5d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892718424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3892718424
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.3380299012
Short name T206
Test name
Test status
Simulation time 37089668 ps
CPU time 0.76 seconds
Started Jul 16 07:35:57 PM PDT 24
Finished Jul 16 07:36:15 PM PDT 24
Peak memory 205040 kb
Host smart-ca389598-0177-457a-9fb2-fca1ab88cc97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380299012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3380299012
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.729213491
Short name T9
Test name
Test status
Simulation time 4723463572 ps
CPU time 6.11 seconds
Started Jul 16 07:36:03 PM PDT 24
Finished Jul 16 07:36:31 PM PDT 24
Peak memory 214360 kb
Host smart-97b0f60a-5869-4fd6-a813-b0b5b1759bf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729213491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.729213491
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.206000774
Short name T278
Test name
Test status
Simulation time 147502339 ps
CPU time 0.82 seconds
Started Jul 16 07:34:22 PM PDT 24
Finished Jul 16 07:34:38 PM PDT 24
Peak memory 204932 kb
Host smart-adff4e81-cd25-429b-b7db-c8edb898b5f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206000774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.206000774
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.1852588073
Short name T198
Test name
Test status
Simulation time 7274613057 ps
CPU time 7.04 seconds
Started Jul 16 07:34:23 PM PDT 24
Finished Jul 16 07:34:45 PM PDT 24
Peak memory 213764 kb
Host smart-5800ee08-dd88-4cee-81cb-06c5b7778f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852588073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.1852588073
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3381964097
Short name T235
Test name
Test status
Simulation time 3765449625 ps
CPU time 3.75 seconds
Started Jul 16 07:34:23 PM PDT 24
Finished Jul 16 07:34:42 PM PDT 24
Peak memory 213716 kb
Host smart-21a14673-9bc4-4ebc-a59a-202d28da5f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381964097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3381964097
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1039619124
Short name T214
Test name
Test status
Simulation time 2066294793 ps
CPU time 7.15 seconds
Started Jul 16 07:34:24 PM PDT 24
Finished Jul 16 07:34:46 PM PDT 24
Peak memory 205356 kb
Host smart-8df5422f-080b-442d-bdf0-e53f2acdb9ee
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039619124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1039619124
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3769729277
Short name T233
Test name
Test status
Simulation time 166552256 ps
CPU time 1.13 seconds
Started Jul 16 07:34:23 PM PDT 24
Finished Jul 16 07:34:40 PM PDT 24
Peak memory 205012 kb
Host smart-1d44f647-f153-4163-8ea2-29eea72665e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769729277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3769729277
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.308969725
Short name T165
Test name
Test status
Simulation time 5134988581 ps
CPU time 4.25 seconds
Started Jul 16 07:34:22 PM PDT 24
Finished Jul 16 07:34:42 PM PDT 24
Peak memory 205532 kb
Host smart-ddffe011-234e-439e-a278-67a94ba6789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308969725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.308969725
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.33204503
Short name T74
Test name
Test status
Simulation time 358456522 ps
CPU time 1.96 seconds
Started Jul 16 07:34:23 PM PDT 24
Finished Jul 16 07:34:40 PM PDT 24
Peak memory 229736 kb
Host smart-5ca070fe-f4cb-4581-9bd0-2db291bc65e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33204503 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.33204503
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.2193040122
Short name T99
Test name
Test status
Simulation time 3287469270 ps
CPU time 9.42 seconds
Started Jul 16 07:34:22 PM PDT 24
Finished Jul 16 07:34:47 PM PDT 24
Peak memory 213432 kb
Host smart-3bb2623d-6fca-4662-bc2b-507c171e7ceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193040122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.2193040122
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1396190238
Short name T268
Test name
Test status
Simulation time 160199926 ps
CPU time 0.71 seconds
Started Jul 16 07:35:57 PM PDT 24
Finished Jul 16 07:36:15 PM PDT 24
Peak memory 205040 kb
Host smart-c990cba1-dfb7-4276-b58e-9fa9344ae8f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396190238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1396190238
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.388572447
Short name T141
Test name
Test status
Simulation time 126908615 ps
CPU time 0.84 seconds
Started Jul 16 07:36:03 PM PDT 24
Finished Jul 16 07:36:26 PM PDT 24
Peak memory 205008 kb
Host smart-f46322ab-f0fa-4b61-9a22-0ef2c4c048d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388572447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.388572447
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3104674918
Short name T246
Test name
Test status
Simulation time 131792311 ps
CPU time 0.75 seconds
Started Jul 16 07:35:58 PM PDT 24
Finished Jul 16 07:36:18 PM PDT 24
Peak memory 205208 kb
Host smart-0135f2cc-6e8d-41ba-b490-66479015b7f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104674918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3104674918
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.441757813
Short name T252
Test name
Test status
Simulation time 39177546 ps
CPU time 0.76 seconds
Started Jul 16 07:35:58 PM PDT 24
Finished Jul 16 07:36:18 PM PDT 24
Peak memory 205204 kb
Host smart-2d56f628-0ab9-4854-969d-c78dd78955f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441757813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.441757813
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.4141193100
Short name T259
Test name
Test status
Simulation time 98887628 ps
CPU time 0.72 seconds
Started Jul 16 07:35:59 PM PDT 24
Finished Jul 16 07:36:18 PM PDT 24
Peak memory 205048 kb
Host smart-a0db1893-4987-46d5-af7d-2af48eee207a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141193100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.4141193100
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2125088719
Short name T244
Test name
Test status
Simulation time 56255906 ps
CPU time 0.67 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:01 PM PDT 24
Peak memory 204924 kb
Host smart-1285d405-f9c0-4991-8eb6-79cd3b368f84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125088719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2125088719
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2102748885
Short name T51
Test name
Test status
Simulation time 142143845 ps
CPU time 1.05 seconds
Started Jul 16 07:35:54 PM PDT 24
Finished Jul 16 07:36:09 PM PDT 24
Peak memory 204932 kb
Host smart-601d98ae-dcf6-4a4d-8100-35ffba520433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102748885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2102748885
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1797026345
Short name T62
Test name
Test status
Simulation time 77543799 ps
CPU time 0.79 seconds
Started Jul 16 07:35:56 PM PDT 24
Finished Jul 16 07:36:11 PM PDT 24
Peak memory 204964 kb
Host smart-c9fcb7e7-be9c-482c-bb3b-fb3a25857228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797026345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1797026345
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.1644278462
Short name T182
Test name
Test status
Simulation time 4339084417 ps
CPU time 6.31 seconds
Started Jul 16 07:35:56 PM PDT 24
Finished Jul 16 07:36:18 PM PDT 24
Peak memory 205244 kb
Host smart-4cb3db97-a846-44f4-8f82-66a110c8fff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644278462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1644278462
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3485904936
Short name T247
Test name
Test status
Simulation time 135913711 ps
CPU time 0.74 seconds
Started Jul 16 07:35:55 PM PDT 24
Finished Jul 16 07:36:09 PM PDT 24
Peak memory 205008 kb
Host smart-6e7b9541-657b-4795-91ef-c6c120e4acab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485904936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3485904936
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2637280315
Short name T192
Test name
Test status
Simulation time 51547498 ps
CPU time 0.76 seconds
Started Jul 16 07:35:53 PM PDT 24
Finished Jul 16 07:36:04 PM PDT 24
Peak memory 205044 kb
Host smart-4463182b-5229-4e6e-9ef5-b8b1c3a8a1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637280315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2637280315
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3073513319
Short name T219
Test name
Test status
Simulation time 90652729 ps
CPU time 0.77 seconds
Started Jul 16 07:34:23 PM PDT 24
Finished Jul 16 07:34:39 PM PDT 24
Peak memory 204888 kb
Host smart-c469564f-7fa1-4708-b154-291b888e3786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073513319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3073513319
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2757745950
Short name T161
Test name
Test status
Simulation time 2564114642 ps
CPU time 2.91 seconds
Started Jul 16 07:34:23 PM PDT 24
Finished Jul 16 07:34:41 PM PDT 24
Peak memory 205444 kb
Host smart-ce2ac54d-8ed3-4d29-942d-01ed698a29f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757745950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2757745950
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2125386857
Short name T25
Test name
Test status
Simulation time 1502297833 ps
CPU time 5.02 seconds
Started Jul 16 07:34:26 PM PDT 24
Finished Jul 16 07:34:45 PM PDT 24
Peak memory 213580 kb
Host smart-e87b3d23-88bf-4ad6-9327-b103d9cfed69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125386857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2125386857
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1154618025
Short name T243
Test name
Test status
Simulation time 15268653657 ps
CPU time 8.46 seconds
Started Jul 16 07:34:23 PM PDT 24
Finished Jul 16 07:34:47 PM PDT 24
Peak memory 213656 kb
Host smart-6904c0c5-2aab-41d3-bb5f-36f8b367898c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1154618025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1154618025
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1891813694
Short name T248
Test name
Test status
Simulation time 4267321286 ps
CPU time 10.64 seconds
Started Jul 16 07:34:23 PM PDT 24
Finished Jul 16 07:34:49 PM PDT 24
Peak memory 205396 kb
Host smart-f31a4ef6-8ef3-46d4-bbd3-a17cbc4a2a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891813694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1891813694
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3921143190
Short name T228
Test name
Test status
Simulation time 50698499 ps
CPU time 0.76 seconds
Started Jul 16 07:35:02 PM PDT 24
Finished Jul 16 07:35:07 PM PDT 24
Peak memory 205016 kb
Host smart-4d45f38f-f299-4c78-921c-c7fb48904666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921143190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3921143190
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.3742926892
Short name T14
Test name
Test status
Simulation time 617650290 ps
CPU time 1.29 seconds
Started Jul 16 07:34:25 PM PDT 24
Finished Jul 16 07:34:41 PM PDT 24
Peak memory 205380 kb
Host smart-4252208b-baa1-4c36-becb-792d7e0d5c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742926892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.3742926892
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3491045275
Short name T225
Test name
Test status
Simulation time 1733077084 ps
CPU time 6.39 seconds
Started Jul 16 07:34:25 PM PDT 24
Finished Jul 16 07:34:46 PM PDT 24
Peak memory 205400 kb
Host smart-62b43019-7a6b-40e2-a610-b882abf11a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491045275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3491045275
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2081848629
Short name T241
Test name
Test status
Simulation time 6882869887 ps
CPU time 5.89 seconds
Started Jul 16 07:34:23 PM PDT 24
Finished Jul 16 07:34:44 PM PDT 24
Peak memory 213928 kb
Host smart-8efd4993-7a50-406b-b67d-8409b8ff6ede
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2081848629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2081848629
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.4261345573
Short name T203
Test name
Test status
Simulation time 1827700787 ps
CPU time 6.68 seconds
Started Jul 16 07:34:27 PM PDT 24
Finished Jul 16 07:34:48 PM PDT 24
Peak memory 213584 kb
Host smart-4f7a743e-59bc-4d0e-9384-df7bbfa2c83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261345573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.4261345573
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.4283505895
Short name T16
Test name
Test status
Simulation time 12180648655 ps
CPU time 12.54 seconds
Started Jul 16 07:34:26 PM PDT 24
Finished Jul 16 07:34:53 PM PDT 24
Peak memory 213548 kb
Host smart-066ba7e2-8324-42f9-8722-2b0b96f2d7a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283505895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.4283505895
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.18829341
Short name T262
Test name
Test status
Simulation time 33147185795 ps
CPU time 91.39 seconds
Started Jul 16 07:34:59 PM PDT 24
Finished Jul 16 07:36:32 PM PDT 24
Peak memory 213684 kb
Host smart-b286cc08-44f4-47ee-aa76-c5463de9dfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18829341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.18829341
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1239327340
Short name T271
Test name
Test status
Simulation time 2931697446 ps
CPU time 7.9 seconds
Started Jul 16 07:35:00 PM PDT 24
Finished Jul 16 07:35:12 PM PDT 24
Peak memory 205432 kb
Host smart-277275b8-d681-4963-9591-82bc57a1db46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239327340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1239327340
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3183086104
Short name T258
Test name
Test status
Simulation time 3423841992 ps
CPU time 5.82 seconds
Started Jul 16 07:34:59 PM PDT 24
Finished Jul 16 07:35:06 PM PDT 24
Peak memory 213588 kb
Host smart-a27272e8-37cd-405d-b86d-ff4c7cec9bbe
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3183086104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3183086104
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.344831618
Short name T239
Test name
Test status
Simulation time 6083848424 ps
CPU time 15.34 seconds
Started Jul 16 07:34:58 PM PDT 24
Finished Jul 16 07:35:14 PM PDT 24
Peak memory 213704 kb
Host smart-567adb08-1df4-4d75-b57f-a46fad07843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344831618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.344831618
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.686023742
Short name T211
Test name
Test status
Simulation time 33771148 ps
CPU time 0.74 seconds
Started Jul 16 07:35:00 PM PDT 24
Finished Jul 16 07:35:05 PM PDT 24
Peak memory 205036 kb
Host smart-c7d48f2e-3357-4dee-b9c9-30b1a0f333f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686023742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.686023742
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.534173046
Short name T255
Test name
Test status
Simulation time 17776548219 ps
CPU time 14.12 seconds
Started Jul 16 07:35:00 PM PDT 24
Finished Jul 16 07:35:18 PM PDT 24
Peak memory 213764 kb
Host smart-597c36c0-2c2b-48a8-89db-011175096840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534173046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.534173046
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.4221288039
Short name T153
Test name
Test status
Simulation time 3698029843 ps
CPU time 6.49 seconds
Started Jul 16 07:35:02 PM PDT 24
Finished Jul 16 07:35:13 PM PDT 24
Peak memory 213628 kb
Host smart-5231abf7-053b-45d3-b3ce-e4414cd9ad29
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221288039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.4221288039
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1862038056
Short name T216
Test name
Test status
Simulation time 3059284979 ps
CPU time 3.47 seconds
Started Jul 16 07:34:59 PM PDT 24
Finished Jul 16 07:35:05 PM PDT 24
Peak memory 205464 kb
Host smart-905cb0f6-26d6-4311-a7cf-bd6a1358b137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862038056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1862038056
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.3283949793
Short name T273
Test name
Test status
Simulation time 41615844 ps
CPU time 0.73 seconds
Started Jul 16 07:35:00 PM PDT 24
Finished Jul 16 07:35:04 PM PDT 24
Peak memory 205000 kb
Host smart-b874d18e-6bb2-4a7c-b5ef-8a1472fd7da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283949793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3283949793
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3060876073
Short name T71
Test name
Test status
Simulation time 5062098964 ps
CPU time 15.32 seconds
Started Jul 16 07:34:59 PM PDT 24
Finished Jul 16 07:35:17 PM PDT 24
Peak memory 213740 kb
Host smart-80590c03-d56c-4539-b7c4-a957e0d6aa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060876073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3060876073
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1473484742
Short name T221
Test name
Test status
Simulation time 4751818140 ps
CPU time 10.45 seconds
Started Jul 16 07:35:01 PM PDT 24
Finished Jul 16 07:35:15 PM PDT 24
Peak memory 205504 kb
Host smart-4bf88c92-cf0f-47f9-9e7f-d24748bf7b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473484742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1473484742
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3998775179
Short name T207
Test name
Test status
Simulation time 1283663089 ps
CPU time 2.38 seconds
Started Jul 16 07:35:00 PM PDT 24
Finished Jul 16 07:35:06 PM PDT 24
Peak memory 205404 kb
Host smart-bc2e5e70-3c0d-44e8-a304-e02372e1160e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998775179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3998775179
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3038586289
Short name T70
Test name
Test status
Simulation time 1025049920 ps
CPU time 3.5 seconds
Started Jul 16 07:35:02 PM PDT 24
Finished Jul 16 07:35:10 PM PDT 24
Peak memory 205408 kb
Host smart-61296a04-4f64-49d9-b209-09d903309638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038586289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3038586289
Directory /workspace/9.rv_dm_sba_tl_access/latest
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