SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
83.19 | 95.77 | 81.52 | 89.91 | 75.00 | 86.50 | 98.53 | 55.12 |
T299 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.210221819 | Jul 17 05:24:01 PM PDT 24 | Jul 17 05:24:04 PM PDT 24 | 58657333 ps | ||
T300 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1514283124 | Jul 17 05:24:45 PM PDT 24 | Jul 17 05:26:27 PM PDT 24 | 59761544871 ps | ||
T100 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.4070742180 | Jul 17 05:24:17 PM PDT 24 | Jul 17 05:24:21 PM PDT 24 | 555322479 ps | ||
T301 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1241635579 | Jul 17 05:25:43 PM PDT 24 | Jul 17 05:25:51 PM PDT 24 | 6942276202 ps | ||
T91 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4052746240 | Jul 17 05:27:20 PM PDT 24 | Jul 17 05:27:24 PM PDT 24 | 296386427 ps | ||
T101 | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.479632326 | Jul 17 05:24:40 PM PDT 24 | Jul 17 05:24:44 PM PDT 24 | 1137534973 ps | ||
T92 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3157823627 | Jul 17 05:25:49 PM PDT 24 | Jul 17 05:26:11 PM PDT 24 | 4093310042 ps | ||
T115 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3437535517 | Jul 17 05:25:44 PM PDT 24 | Jul 17 05:25:47 PM PDT 24 | 253732672 ps | ||
T302 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.994236442 | Jul 17 05:24:55 PM PDT 24 | Jul 17 05:24:57 PM PDT 24 | 103368459 ps | ||
T303 | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2065002364 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:24:50 PM PDT 24 | 271761022 ps | ||
T304 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.782602766 | Jul 17 05:24:17 PM PDT 24 | Jul 17 05:24:24 PM PDT 24 | 5172582936 ps | ||
T305 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2849126560 | Jul 17 05:25:38 PM PDT 24 | Jul 17 05:25:40 PM PDT 24 | 290304114 ps | ||
T81 | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3321572496 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:25:55 PM PDT 24 | 42186287536 ps | ||
T125 | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3709271529 | Jul 17 05:24:48 PM PDT 24 | Jul 17 05:24:55 PM PDT 24 | 715121191 ps | ||
T170 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2949461607 | Jul 17 05:24:56 PM PDT 24 | Jul 17 05:25:17 PM PDT 24 | 2155157352 ps | ||
T306 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3549216771 | Jul 17 05:24:19 PM PDT 24 | Jul 17 05:24:22 PM PDT 24 | 134124174 ps | ||
T307 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1920294523 | Jul 17 05:25:12 PM PDT 24 | Jul 17 05:25:23 PM PDT 24 | 7928112673 ps | ||
T308 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2647342787 | Jul 17 05:24:35 PM PDT 24 | Jul 17 05:24:38 PM PDT 24 | 121272356 ps | ||
T309 | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3832019902 | Jul 17 05:24:33 PM PDT 24 | Jul 17 05:24:50 PM PDT 24 | 10489873985 ps | ||
T310 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2454117642 | Jul 17 05:24:47 PM PDT 24 | Jul 17 05:24:55 PM PDT 24 | 3933671692 ps | ||
T102 | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.887583566 | Jul 17 05:25:04 PM PDT 24 | Jul 17 05:25:30 PM PDT 24 | 78418914858 ps | ||
T311 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3647931406 | Jul 17 05:25:24 PM PDT 24 | Jul 17 05:25:26 PM PDT 24 | 262841762 ps | ||
T103 | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4264113523 | Jul 17 05:24:45 PM PDT 24 | Jul 17 05:24:53 PM PDT 24 | 104181160 ps | ||
T312 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1818355934 | Jul 17 05:24:40 PM PDT 24 | Jul 17 05:24:42 PM PDT 24 | 350203499 ps | ||
T313 | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.939305394 | Jul 17 05:24:58 PM PDT 24 | Jul 17 05:25:01 PM PDT 24 | 1214125374 ps | ||
T136 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3267856034 | Jul 17 05:24:47 PM PDT 24 | Jul 17 05:24:52 PM PDT 24 | 109065132 ps | ||
T137 | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3325362364 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:25:00 PM PDT 24 | 3574734881 ps | ||
T116 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1079588727 | Jul 17 05:24:35 PM PDT 24 | Jul 17 05:24:39 PM PDT 24 | 120586778 ps | ||
T314 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2040572655 | Jul 17 05:25:13 PM PDT 24 | Jul 17 05:25:20 PM PDT 24 | 5189011341 ps | ||
T126 | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1180693361 | Jul 17 05:24:35 PM PDT 24 | Jul 17 05:24:43 PM PDT 24 | 155247474 ps | ||
T315 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3752953340 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:24:52 PM PDT 24 | 879835936 ps | ||
T117 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2736462842 | Jul 17 05:24:17 PM PDT 24 | Jul 17 05:25:35 PM PDT 24 | 4388623263 ps | ||
T316 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2046100855 | Jul 17 05:25:05 PM PDT 24 | Jul 17 05:25:21 PM PDT 24 | 10381829694 ps | ||
T317 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2448574688 | Jul 17 05:25:12 PM PDT 24 | Jul 17 05:25:17 PM PDT 24 | 61420092 ps | ||
T127 | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.318659022 | Jul 17 05:24:47 PM PDT 24 | Jul 17 05:24:55 PM PDT 24 | 247129425 ps | ||
T318 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1796489352 | Jul 17 05:24:16 PM PDT 24 | Jul 17 05:24:19 PM PDT 24 | 295757700 ps | ||
T319 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1636276760 | Jul 17 05:25:24 PM PDT 24 | Jul 17 05:25:40 PM PDT 24 | 8135994731 ps | ||
T320 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.187169911 | Jul 17 05:24:48 PM PDT 24 | Jul 17 05:25:04 PM PDT 24 | 4695008782 ps | ||
T108 | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.631324957 | Jul 17 05:24:40 PM PDT 24 | Jul 17 05:24:49 PM PDT 24 | 3955402717 ps | ||
T128 | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4210064599 | Jul 17 05:24:21 PM PDT 24 | Jul 17 05:24:27 PM PDT 24 | 602176474 ps | ||
T129 | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2273487476 | Jul 17 05:27:20 PM PDT 24 | Jul 17 05:27:26 PM PDT 24 | 2035505850 ps | ||
T109 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1297928742 | Jul 17 05:25:59 PM PDT 24 | Jul 17 05:26:02 PM PDT 24 | 438483425 ps | ||
T130 | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1089810387 | Jul 17 05:27:20 PM PDT 24 | Jul 17 05:27:28 PM PDT 24 | 589314851 ps | ||
T321 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2363102588 | Jul 17 05:25:01 PM PDT 24 | Jul 17 05:25:04 PM PDT 24 | 484083353 ps | ||
T322 | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2208105668 | Jul 17 05:26:59 PM PDT 24 | Jul 17 05:27:03 PM PDT 24 | 177444743 ps | ||
T323 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1357970262 | Jul 17 05:24:21 PM PDT 24 | Jul 17 05:24:23 PM PDT 24 | 67169186 ps | ||
T324 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3562370781 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:28:26 PM PDT 24 | 85739459319 ps | ||
T118 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1331971505 | Jul 17 05:24:35 PM PDT 24 | Jul 17 05:25:04 PM PDT 24 | 732801609 ps | ||
T171 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3377324905 | Jul 17 05:24:50 PM PDT 24 | Jul 17 05:25:12 PM PDT 24 | 2179549733 ps | ||
T325 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4006225747 | Jul 17 05:24:16 PM PDT 24 | Jul 17 05:24:23 PM PDT 24 | 2916009613 ps | ||
T326 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2499072335 | Jul 17 05:24:19 PM PDT 24 | Jul 17 05:24:41 PM PDT 24 | 12314678143 ps | ||
T110 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2919370494 | Jul 17 05:25:10 PM PDT 24 | Jul 17 05:25:46 PM PDT 24 | 2414944132 ps | ||
T327 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.45609837 | Jul 17 05:24:35 PM PDT 24 | Jul 17 05:24:39 PM PDT 24 | 650135057 ps | ||
T328 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2514454566 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:25:45 PM PDT 24 | 63340773814 ps | ||
T329 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.861022353 | Jul 17 05:24:20 PM PDT 24 | Jul 17 05:25:29 PM PDT 24 | 43896579694 ps | ||
T330 | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2448291237 | Jul 17 05:24:45 PM PDT 24 | Jul 17 05:24:51 PM PDT 24 | 2431363263 ps | ||
T331 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1465549756 | Jul 17 05:24:01 PM PDT 24 | Jul 17 05:24:36 PM PDT 24 | 118645265548 ps | ||
T332 | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2518988385 | Jul 17 05:24:44 PM PDT 24 | Jul 17 05:24:54 PM PDT 24 | 663317880 ps | ||
T119 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2977938424 | Jul 17 05:24:36 PM PDT 24 | Jul 17 05:24:40 PM PDT 24 | 368082464 ps | ||
T333 | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1178982791 | Jul 17 05:27:20 PM PDT 24 | Jul 17 05:27:22 PM PDT 24 | 251655968 ps | ||
T334 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.797653863 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:24:51 PM PDT 24 | 2473594824 ps | ||
T120 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3956093021 | Jul 17 05:24:44 PM PDT 24 | Jul 17 05:24:49 PM PDT 24 | 93821775 ps | ||
T176 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1767861600 | Jul 17 05:24:47 PM PDT 24 | Jul 17 05:25:15 PM PDT 24 | 3140946768 ps | ||
T335 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1437627435 | Jul 17 05:24:43 PM PDT 24 | Jul 17 05:24:54 PM PDT 24 | 4227714571 ps | ||
T336 | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1886256373 | Jul 17 05:24:43 PM PDT 24 | Jul 17 05:24:52 PM PDT 24 | 1457833277 ps | ||
T337 | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3414292858 | Jul 17 05:26:51 PM PDT 24 | Jul 17 05:27:01 PM PDT 24 | 508517556 ps | ||
T338 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1347323308 | Jul 17 05:25:10 PM PDT 24 | Jul 17 05:25:15 PM PDT 24 | 1291905949 ps | ||
T179 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3991235860 | Jul 17 05:24:27 PM PDT 24 | Jul 17 05:24:46 PM PDT 24 | 2030853292 ps | ||
T339 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.466151600 | Jul 17 05:23:59 PM PDT 24 | Jul 17 05:24:32 PM PDT 24 | 3507598732 ps | ||
T340 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1519595206 | Jul 17 05:24:45 PM PDT 24 | Jul 17 05:24:49 PM PDT 24 | 232496242 ps | ||
T123 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1302887709 | Jul 17 05:24:17 PM PDT 24 | Jul 17 05:24:21 PM PDT 24 | 584859293 ps | ||
T169 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.58987576 | Jul 17 05:24:58 PM PDT 24 | Jul 17 05:25:17 PM PDT 24 | 1164112555 ps | ||
T104 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2365614839 | Jul 17 05:24:35 PM PDT 24 | Jul 17 05:24:48 PM PDT 24 | 4408539619 ps | ||
T341 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3683674479 | Jul 17 05:25:13 PM PDT 24 | Jul 17 05:25:22 PM PDT 24 | 2144072215 ps | ||
T342 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2988248389 | Jul 17 05:24:47 PM PDT 24 | Jul 17 05:24:53 PM PDT 24 | 228914552 ps | ||
T173 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.525438216 | Jul 17 05:24:48 PM PDT 24 | Jul 17 05:25:08 PM PDT 24 | 2536924772 ps | ||
T343 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.286379777 | Jul 17 05:25:04 PM PDT 24 | Jul 17 05:25:06 PM PDT 24 | 242532958 ps | ||
T344 | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1455166840 | Jul 17 05:24:47 PM PDT 24 | Jul 17 05:24:54 PM PDT 24 | 412275934 ps | ||
T111 | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1346827717 | Jul 17 05:24:56 PM PDT 24 | Jul 17 05:25:04 PM PDT 24 | 463190594 ps | ||
T112 | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2727864402 | Jul 17 05:24:43 PM PDT 24 | Jul 17 05:24:54 PM PDT 24 | 552045599 ps | ||
T345 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3085288823 | Jul 17 05:24:17 PM PDT 24 | Jul 17 05:24:24 PM PDT 24 | 107777152 ps | ||
T346 | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1912908569 | Jul 17 05:24:59 PM PDT 24 | Jul 17 05:25:06 PM PDT 24 | 142442692 ps | ||
T124 | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2253341707 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:24:51 PM PDT 24 | 482940330 ps | ||
T347 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1891761591 | Jul 17 05:24:48 PM PDT 24 | Jul 17 05:24:52 PM PDT 24 | 362386311 ps | ||
T348 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1007969339 | Jul 17 05:26:48 PM PDT 24 | Jul 17 05:28:28 PM PDT 24 | 36461630645 ps | ||
T349 | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2802488719 | Jul 17 05:24:17 PM PDT 24 | Jul 17 05:24:22 PM PDT 24 | 431366711 ps | ||
T350 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1464487033 | Jul 17 05:24:41 PM PDT 24 | Jul 17 05:24:43 PM PDT 24 | 60872378 ps | ||
T113 | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2623778402 | Jul 17 05:25:50 PM PDT 24 | Jul 17 05:25:59 PM PDT 24 | 405193851 ps | ||
T351 | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.788027478 | Jul 17 05:24:51 PM PDT 24 | Jul 17 05:29:21 PM PDT 24 | 48392603142 ps | ||
T352 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2600937520 | Jul 17 05:24:07 PM PDT 24 | Jul 17 05:24:10 PM PDT 24 | 249505656 ps | ||
T114 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2964219320 | Jul 17 05:24:56 PM PDT 24 | Jul 17 05:24:59 PM PDT 24 | 161196294 ps | ||
T353 | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3102159136 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:24:52 PM PDT 24 | 1003460709 ps | ||
T354 | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.365234238 | Jul 17 05:24:47 PM PDT 24 | Jul 17 05:24:54 PM PDT 24 | 212335615 ps | ||
T355 | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3610021367 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:24:52 PM PDT 24 | 400457260 ps | ||
T356 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3213593373 | Jul 17 05:24:28 PM PDT 24 | Jul 17 05:24:29 PM PDT 24 | 56301040 ps | ||
T357 | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2626330039 | Jul 17 05:24:00 PM PDT 24 | Jul 17 05:24:03 PM PDT 24 | 81177808 ps | ||
T358 | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.383076803 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:24:54 PM PDT 24 | 2687652798 ps | ||
T359 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2115430737 | Jul 17 05:24:33 PM PDT 24 | Jul 17 05:24:40 PM PDT 24 | 282572080 ps | ||
T360 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.208426895 | Jul 17 05:25:50 PM PDT 24 | Jul 17 05:25:54 PM PDT 24 | 352053576 ps | ||
T361 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3401823621 | Jul 17 05:24:17 PM PDT 24 | Jul 17 05:24:20 PM PDT 24 | 158487496 ps | ||
T362 | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.789626827 | Jul 17 05:24:35 PM PDT 24 | Jul 17 05:24:43 PM PDT 24 | 371087660 ps | ||
T363 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.273462632 | Jul 17 05:24:47 PM PDT 24 | Jul 17 05:24:52 PM PDT 24 | 94800947 ps | ||
T364 | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2388641720 | Jul 17 05:25:43 PM PDT 24 | Jul 17 05:25:48 PM PDT 24 | 1350299753 ps | ||
T365 | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2613856583 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:24:54 PM PDT 24 | 124244042 ps | ||
T366 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3317753180 | Jul 17 05:24:07 PM PDT 24 | Jul 17 05:24:10 PM PDT 24 | 967603206 ps | ||
T367 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.225863381 | Jul 17 05:24:43 PM PDT 24 | Jul 17 05:24:46 PM PDT 24 | 1170221113 ps | ||
T368 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.572416163 | Jul 17 05:24:40 PM PDT 24 | Jul 17 05:24:43 PM PDT 24 | 206093042 ps | ||
T369 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2630445003 | Jul 17 05:24:17 PM PDT 24 | Jul 17 05:24:22 PM PDT 24 | 245733213 ps | ||
T370 | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1338658518 | Jul 17 05:24:45 PM PDT 24 | Jul 17 05:24:54 PM PDT 24 | 5199919289 ps | ||
T371 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1372950992 | Jul 17 05:24:43 PM PDT 24 | Jul 17 05:25:00 PM PDT 24 | 5011266777 ps | ||
T372 | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.92718259 | Jul 17 05:24:35 PM PDT 24 | Jul 17 05:24:37 PM PDT 24 | 43536085 ps | ||
T105 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.108183795 | Jul 17 05:24:27 PM PDT 24 | Jul 17 05:24:41 PM PDT 24 | 5865294773 ps | ||
T373 | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1072356169 | Jul 17 05:24:35 PM PDT 24 | Jul 17 05:24:50 PM PDT 24 | 4626232074 ps | ||
T374 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2146893171 | Jul 17 05:24:48 PM PDT 24 | Jul 17 05:24:58 PM PDT 24 | 3717572372 ps | ||
T375 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2989179137 | Jul 17 05:24:35 PM PDT 24 | Jul 17 05:24:38 PM PDT 24 | 216951474 ps | ||
T376 | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1625964878 | Jul 17 05:24:19 PM PDT 24 | Jul 17 05:24:21 PM PDT 24 | 252890841 ps | ||
T377 | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1546874549 | Jul 17 05:24:37 PM PDT 24 | Jul 17 05:26:07 PM PDT 24 | 52111281097 ps | ||
T378 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3491544045 | Jul 17 05:25:13 PM PDT 24 | Jul 17 05:25:25 PM PDT 24 | 5989465262 ps | ||
T379 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2304769460 | Jul 17 05:27:13 PM PDT 24 | Jul 17 05:27:20 PM PDT 24 | 655038277 ps | ||
T175 | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2453506556 | Jul 17 05:25:25 PM PDT 24 | Jul 17 05:25:35 PM PDT 24 | 1387286932 ps | ||
T172 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3899608812 | Jul 17 05:24:45 PM PDT 24 | Jul 17 05:24:59 PM PDT 24 | 3166837113 ps | ||
T177 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.739780171 | Jul 17 05:24:45 PM PDT 24 | Jul 17 05:24:58 PM PDT 24 | 1946069302 ps | ||
T380 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2581328906 | Jul 17 05:24:19 PM PDT 24 | Jul 17 05:24:23 PM PDT 24 | 2223812244 ps | ||
T381 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2521191489 | Jul 17 05:25:13 PM PDT 24 | Jul 17 05:25:36 PM PDT 24 | 7539493345 ps | ||
T382 | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3217327623 | Jul 17 05:24:43 PM PDT 24 | Jul 17 05:24:52 PM PDT 24 | 604560260 ps | ||
T383 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1725491592 | Jul 17 05:24:38 PM PDT 24 | Jul 17 05:25:11 PM PDT 24 | 4409589574 ps | ||
T384 | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.4266503971 | Jul 17 05:24:43 PM PDT 24 | Jul 17 05:24:46 PM PDT 24 | 161922159 ps | ||
T385 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4280446365 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:24:51 PM PDT 24 | 277483227 ps | ||
T178 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1799992364 | Jul 17 05:24:47 PM PDT 24 | Jul 17 05:25:15 PM PDT 24 | 4228222106 ps | ||
T174 | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1946373608 | Jul 17 05:24:34 PM PDT 24 | Jul 17 05:24:55 PM PDT 24 | 5636284651 ps | ||
T386 | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3720405760 | Jul 17 05:24:38 PM PDT 24 | Jul 17 05:24:40 PM PDT 24 | 149117440 ps | ||
T387 | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.525286717 | Jul 17 05:25:44 PM PDT 24 | Jul 17 05:25:47 PM PDT 24 | 316410739 ps | ||
T388 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.86432495 | Jul 17 05:25:50 PM PDT 24 | Jul 17 05:25:59 PM PDT 24 | 4024591069 ps | ||
T389 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1502470695 | Jul 17 05:25:44 PM PDT 24 | Jul 17 05:25:47 PM PDT 24 | 1253535235 ps | ||
T390 | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.567405342 | Jul 17 05:27:19 PM PDT 24 | Jul 17 05:27:25 PM PDT 24 | 2705250158 ps | ||
T391 | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1092968310 | Jul 17 05:24:22 PM PDT 24 | Jul 17 05:24:28 PM PDT 24 | 179406424 ps | ||
T121 | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2006191199 | Jul 17 05:24:03 PM PDT 24 | Jul 17 05:24:07 PM PDT 24 | 130299707 ps | ||
T392 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1891222257 | Jul 17 05:24:51 PM PDT 24 | Jul 17 05:24:55 PM PDT 24 | 3005448269 ps | ||
T393 | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.446567156 | Jul 17 05:24:18 PM PDT 24 | Jul 17 05:24:25 PM PDT 24 | 1457760169 ps | ||
T394 | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.799012108 | Jul 17 05:26:21 PM PDT 24 | Jul 17 05:26:26 PM PDT 24 | 2886092565 ps | ||
T395 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1337125596 | Jul 17 05:24:35 PM PDT 24 | Jul 17 05:24:45 PM PDT 24 | 9151455799 ps | ||
T396 | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3429382468 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:24:50 PM PDT 24 | 61249600 ps | ||
T397 | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.636836910 | Jul 17 05:24:45 PM PDT 24 | Jul 17 05:24:54 PM PDT 24 | 2204663335 ps | ||
T398 | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1273783652 | Jul 17 05:24:33 PM PDT 24 | Jul 17 05:24:37 PM PDT 24 | 110819371 ps | ||
T399 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.185960422 | Jul 17 05:25:09 PM PDT 24 | Jul 17 05:25:14 PM PDT 24 | 660073232 ps | ||
T400 | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3060765538 | Jul 17 05:24:58 PM PDT 24 | Jul 17 05:25:03 PM PDT 24 | 282922173 ps | ||
T401 | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2056334035 | Jul 17 05:24:47 PM PDT 24 | Jul 17 05:25:36 PM PDT 24 | 66520737632 ps | ||
T402 | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2335460228 | Jul 17 05:24:56 PM PDT 24 | Jul 17 05:25:03 PM PDT 24 | 5672490580 ps | ||
T403 | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3916864543 | Jul 17 05:24:43 PM PDT 24 | Jul 17 05:24:51 PM PDT 24 | 855414500 ps | ||
T106 | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2488878725 | Jul 17 05:24:27 PM PDT 24 | Jul 17 05:24:34 PM PDT 24 | 2555632341 ps | ||
T404 | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1809196738 | Jul 17 05:24:45 PM PDT 24 | Jul 17 05:25:59 PM PDT 24 | 25239010385 ps | ||
T405 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.949101928 | Jul 17 05:24:20 PM PDT 24 | Jul 17 05:24:46 PM PDT 24 | 13560106923 ps | ||
T406 | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1228544796 | Jul 17 05:25:12 PM PDT 24 | Jul 17 05:25:17 PM PDT 24 | 70518138 ps | ||
T407 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.740300608 | Jul 17 05:24:18 PM PDT 24 | Jul 17 05:25:55 PM PDT 24 | 39194863563 ps | ||
T408 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1648153511 | Jul 17 05:24:38 PM PDT 24 | Jul 17 05:24:43 PM PDT 24 | 670146723 ps | ||
T409 | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1104031196 | Jul 17 05:25:13 PM PDT 24 | Jul 17 05:25:20 PM PDT 24 | 286221805 ps | ||
T410 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2701852441 | Jul 17 05:24:41 PM PDT 24 | Jul 17 05:24:46 PM PDT 24 | 188089476 ps | ||
T411 | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.746455046 | Jul 17 05:25:45 PM PDT 24 | Jul 17 05:25:49 PM PDT 24 | 1615978310 ps | ||
T412 | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1291754306 | Jul 17 05:25:13 PM PDT 24 | Jul 17 05:25:21 PM PDT 24 | 239539028 ps | ||
T413 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1340182267 | Jul 17 05:24:45 PM PDT 24 | Jul 17 05:24:54 PM PDT 24 | 289708456 ps | ||
T180 | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2283074432 | Jul 17 05:24:21 PM PDT 24 | Jul 17 05:24:32 PM PDT 24 | 1624603900 ps | ||
T414 | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2606999031 | Jul 17 05:24:51 PM PDT 24 | Jul 17 05:25:17 PM PDT 24 | 4023294174 ps | ||
T415 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.7849967 | Jul 17 05:24:21 PM PDT 24 | Jul 17 05:24:24 PM PDT 24 | 729046242 ps | ||
T416 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2471374711 | Jul 17 05:24:22 PM PDT 24 | Jul 17 05:24:29 PM PDT 24 | 5509152034 ps | ||
T417 | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.599504462 | Jul 17 05:24:20 PM PDT 24 | Jul 17 05:24:30 PM PDT 24 | 3281126163 ps | ||
T418 | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.357465718 | Jul 17 05:24:45 PM PDT 24 | Jul 17 05:24:50 PM PDT 24 | 409635465 ps | ||
T419 | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1609856489 | Jul 17 05:24:46 PM PDT 24 | Jul 17 05:25:50 PM PDT 24 | 47410525622 ps | ||
T420 | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2367431692 | Jul 17 05:25:04 PM PDT 24 | Jul 17 05:25:10 PM PDT 24 | 2553632287 ps | ||
T107 | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3184356346 | Jul 17 05:25:44 PM PDT 24 | Jul 17 05:25:47 PM PDT 24 | 2836718897 ps | ||
T421 | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2226633208 | Jul 17 05:25:01 PM PDT 24 | Jul 17 05:25:11 PM PDT 24 | 9464337170 ps | ||
T422 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2285579532 | Jul 17 05:24:20 PM PDT 24 | Jul 17 05:24:24 PM PDT 24 | 1227207234 ps | ||
T423 | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2570100552 | Jul 17 05:24:35 PM PDT 24 | Jul 17 05:24:39 PM PDT 24 | 467601744 ps | ||
T424 | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2106627162 | Jul 17 05:24:19 PM PDT 24 | Jul 17 05:24:27 PM PDT 24 | 4753528971 ps | ||
T425 | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.556012529 | Jul 17 05:25:50 PM PDT 24 | Jul 17 05:25:58 PM PDT 24 | 2844900739 ps | ||
T426 | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.425734353 | Jul 17 05:24:47 PM PDT 24 | Jul 17 05:24:56 PM PDT 24 | 426521996 ps | ||
T427 | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1393047971 | Jul 17 05:25:13 PM PDT 24 | Jul 17 05:26:57 PM PDT 24 | 39731532050 ps | ||
T428 | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3927052151 | Jul 17 05:24:22 PM PDT 24 | Jul 17 05:24:32 PM PDT 24 | 588749809 ps | ||
T429 | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1508426876 | Jul 17 05:25:44 PM PDT 24 | Jul 17 05:26:54 PM PDT 24 | 51174660829 ps | ||
T430 | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2760675480 | Jul 17 05:27:13 PM PDT 24 | Jul 17 05:27:18 PM PDT 24 | 2847709166 ps | ||
T431 | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1330480973 | Jul 17 05:25:58 PM PDT 24 | Jul 17 05:26:10 PM PDT 24 | 923406851 ps | ||
T432 | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2822045847 | Jul 17 05:24:47 PM PDT 24 | Jul 17 05:26:00 PM PDT 24 | 23401063427 ps | ||
T122 | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3755919546 | Jul 17 05:24:42 PM PDT 24 | Jul 17 05:24:45 PM PDT 24 | 293956943 ps | ||
T433 | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1409008203 | Jul 17 05:24:47 PM PDT 24 | Jul 17 05:24:52 PM PDT 24 | 517747517 ps | ||
T434 | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1729120160 | Jul 17 05:24:34 PM PDT 24 | Jul 17 05:25:09 PM PDT 24 | 9141231190 ps | ||
T435 | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.335095267 | Jul 17 05:27:20 PM PDT 24 | Jul 17 05:27:27 PM PDT 24 | 466158583 ps | ||
T436 | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2357970491 | Jul 17 05:24:56 PM PDT 24 | Jul 17 05:25:16 PM PDT 24 | 3884107235 ps |
Test location | /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.663998699 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 4043720470 ps |
CPU time | 5.54 seconds |
Started | Jul 17 05:26:50 PM PDT 24 |
Finished | Jul 17 05:27:01 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-70bfd390-d0af-4b41-8086-e755ba2fb69e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=663998699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.663998699 |
Directory | /workspace/1.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_stress_all.3056454927 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 7051076408 ps |
CPU time | 6.33 seconds |
Started | Jul 17 05:25:29 PM PDT 24 |
Finished | Jul 17 05:25:36 PM PDT 24 |
Peak memory | 213564 kb |
Host | smart-5f20f215-3748-4ba6-a651-3379005ddec7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056454927 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.3056454927 |
Directory | /workspace/10.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3314542822 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 1683280012 ps |
CPU time | 5.25 seconds |
Started | Jul 17 05:24:38 PM PDT 24 |
Finished | Jul 17 05:24:44 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-fafd3759-5123-439e-bbb4-7b734eb5e43d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314542822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3314542822 |
Directory | /workspace/2.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.1418849369 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 1632385368 ps |
CPU time | 1.27 seconds |
Started | Jul 17 05:25:25 PM PDT 24 |
Finished | Jul 17 05:25:28 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-9198de32-fb88-47a4-a358-421dbc25c5de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1418849369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.1418849369 |
Directory | /workspace/14.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.3387304892 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 63813883038 ps |
CPU time | 101.24 seconds |
Started | Jul 17 05:24:44 PM PDT 24 |
Finished | Jul 17 05:26:28 PM PDT 24 |
Peak memory | 222148 kb |
Host | smart-b3883985-2aec-4ec6-888a-3b0a96d6f8e3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387304892 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.3387304892 |
Directory | /workspace/3.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3796793060 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 4020230770 ps |
CPU time | 17.75 seconds |
Started | Jul 17 05:24:43 PM PDT 24 |
Finished | Jul 17 05:25:04 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-c26e9999-8b93-4d8e-aecb-2c35a705a2bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796793060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3796793060 |
Directory | /workspace/3.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/35.rv_dm_stress_all.1315431723 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 6535714738 ps |
CPU time | 16.59 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:26:09 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-7c015110-1de0-451f-9304-9006a34fea95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315431723 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1315431723 |
Directory | /workspace/35.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1459219167 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 34720676786 ps |
CPU time | 24.39 seconds |
Started | Jul 17 05:25:09 PM PDT 24 |
Finished | Jul 17 05:25:36 PM PDT 24 |
Peak memory | 213732 kb |
Host | smart-fcb90368-1bc7-48a0-baaf-8be57eb4d851 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1459219167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1459219167 |
Directory | /workspace/6.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/39.rv_dm_alert_test.213022157 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 143529342 ps |
CPU time | 0.76 seconds |
Started | Jul 17 05:27:14 PM PDT 24 |
Finished | Jul 17 05:27:15 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-23994294-dec9-4206-8f94-5c025563930f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213022157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.213022157 |
Directory | /workspace/39.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_exception.709985939 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 1881853321 ps |
CPU time | 1.17 seconds |
Started | Jul 17 05:25:08 PM PDT 24 |
Finished | Jul 17 05:25:11 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-1ff52e22-c972-4a1e-8191-1d73fa70e6b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=709985939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.709985939 |
Directory | /workspace/1.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/19.rv_dm_stress_all.3179059475 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 5012368126 ps |
CPU time | 14.49 seconds |
Started | Jul 17 05:27:17 PM PDT 24 |
Finished | Jul 17 05:27:32 PM PDT 24 |
Peak memory | 213508 kb |
Host | smart-63ea2a22-eff0-4abf-8afe-338009f9265f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179059475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3179059475 |
Directory | /workspace/19.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_dm_debug_disabled.896053734 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 58863922 ps |
CPU time | 0.87 seconds |
Started | Jul 17 05:25:07 PM PDT 24 |
Finished | Jul 17 05:25:09 PM PDT 24 |
Peak memory | 215408 kb |
Host | smart-5cd8a2b2-b0ac-47dd-9388-801a62a3b35d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=896053734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.896053734 |
Directory | /workspace/1.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.2756282468 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 69788044297 ps |
CPU time | 49.84 seconds |
Started | Jul 17 05:25:09 PM PDT 24 |
Finished | Jul 17 05:26:02 PM PDT 24 |
Peak memory | 216292 kb |
Host | smart-75eb59c4-d565-49e6-af44-8ae87614c6bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756282468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.2756282468 |
Directory | /workspace/8.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.1814564569 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 3814526252 ps |
CPU time | 35.92 seconds |
Started | Jul 17 05:24:17 PM PDT 24 |
Finished | Jul 17 05:24:54 PM PDT 24 |
Peak memory | 213640 kb |
Host | smart-c4ad6d10-7d2a-45ca-8298-3598c2e82062 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814564569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.1814564569 |
Directory | /workspace/0.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_debug_disabled.3234123745 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 2586658864 ps |
CPU time | 4.51 seconds |
Started | Jul 17 05:26:53 PM PDT 24 |
Finished | Jul 17 05:27:02 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-9d251075-2f7d-49c6-84f3-a54b4315e75d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3234123745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3234123745 |
Directory | /workspace/0.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sec_cm.4082929578 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 934380743 ps |
CPU time | 2.01 seconds |
Started | Jul 17 05:26:59 PM PDT 24 |
Finished | Jul 17 05:27:02 PM PDT 24 |
Peak memory | 229292 kb |
Host | smart-7fcd0cea-7921-4f7d-bdf0-8af68d512338 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082929578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.4082929578 |
Directory | /workspace/1.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/44.rv_dm_stress_all.2219709231 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 3953471883 ps |
CPU time | 7.98 seconds |
Started | Jul 17 05:26:44 PM PDT 24 |
Finished | Jul 17 05:26:53 PM PDT 24 |
Peak memory | 213376 kb |
Host | smart-765a71c4-e2da-4064-b066-8709def06d43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219709231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2219709231 |
Directory | /workspace/44.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_abstractcmd_status.446094054 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 176111678 ps |
CPU time | 0.74 seconds |
Started | Jul 17 05:25:04 PM PDT 24 |
Finished | Jul 17 05:25:06 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-7d9f9d34-d2bc-4584-bfbe-1572ef7834e1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446094054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.446094054 |
Directory | /workspace/0.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/45.rv_dm_stress_all.2675805258 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 12870400051 ps |
CPU time | 32.28 seconds |
Started | Jul 17 05:26:46 PM PDT 24 |
Finished | Jul 17 05:27:21 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-fe0a2104-d999-422c-9234-6661200f05f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675805258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.2675805258 |
Directory | /workspace/45.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_rom_read_access.21297357 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 109254354 ps |
CPU time | 0.91 seconds |
Started | Jul 17 05:27:03 PM PDT 24 |
Finished | Jul 17 05:27:05 PM PDT 24 |
Peak memory | 213248 kb |
Host | smart-4180f7a8-a0b7-4948-b189-57f749dbb950 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21297357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.21297357 |
Directory | /workspace/0.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2006191199 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 130299707 ps |
CPU time | 2.28 seconds |
Started | Jul 17 05:24:03 PM PDT 24 |
Finished | Jul 17 05:24:07 PM PDT 24 |
Peak memory | 213628 kb |
Host | smart-063754ff-883c-4a06-97bc-13bdc66f4c2c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006191199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2006191199 |
Directory | /workspace/0.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.479632326 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 1137534973 ps |
CPU time | 4.13 seconds |
Started | Jul 17 05:24:40 PM PDT 24 |
Finished | Jul 17 05:24:44 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-edf00612-9fab-4e72-af47-2566406172ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479632326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c sr_outstanding.479632326 |
Directory | /workspace/4.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/default/0.rv_dm_dmi_failed_op.3249796660 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 368867560 ps |
CPU time | 1.11 seconds |
Started | Jul 17 05:25:00 PM PDT 24 |
Finished | Jul 17 05:25:02 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-6119094b-4a6f-4b4b-b52b-3f3621131e27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3249796660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.3249796660 |
Directory | /workspace/0.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/42.rv_dm_stress_all.3884959921 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 8117099940 ps |
CPU time | 3.19 seconds |
Started | Jul 17 05:27:17 PM PDT 24 |
Finished | Jul 17 05:27:20 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-71adc593-f4a4-41af-a78b-ce2375944ed4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884959921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.3884959921 |
Directory | /workspace/42.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/34.rv_dm_stress_all.2537678590 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 5003988771 ps |
CPU time | 4.78 seconds |
Started | Jul 17 05:27:14 PM PDT 24 |
Finished | Jul 17 05:27:20 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-a0e19fb3-d65a-4ec7-81c0-054688da4ae9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537678590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2537678590 |
Directory | /workspace/34.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_busy.2351577876 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 942291792 ps |
CPU time | 1.71 seconds |
Started | Jul 17 05:26:48 PM PDT 24 |
Finished | Jul 17 05:26:55 PM PDT 24 |
Peak memory | 205148 kb |
Host | smart-81271f45-4b83-49f1-baf5-cab480201d9d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2351577876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.2351577876 |
Directory | /workspace/0.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.3104169931 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 664902004 ps |
CPU time | 1.62 seconds |
Started | Jul 17 05:27:04 PM PDT 24 |
Finished | Jul 17 05:27:06 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-c2cd3ad2-fec3-4917-b147-ad75bbe82130 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3104169931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.3104169931 |
Directory | /workspace/0.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2453506556 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 1387286932 ps |
CPU time | 8.65 seconds |
Started | Jul 17 05:25:25 PM PDT 24 |
Finished | Jul 17 05:25:35 PM PDT 24 |
Peak memory | 213624 kb |
Host | smart-e93015ad-84ee-4d7c-b93a-037ce66923d3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453506556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2453506556 |
Directory | /workspace/0.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_hartsel_warl.2600274961 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 295367314 ps |
CPU time | 0.8 seconds |
Started | Jul 17 05:24:59 PM PDT 24 |
Finished | Jul 17 05:25:02 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-f2407211-d02e-49e4-84a5-99cd71e220ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600274961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.2600274961 |
Directory | /workspace/0.rv_dm_hartsel_warl/latest |
Test location | /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3639251585 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 9773220951 ps |
CPU time | 5.18 seconds |
Started | Jul 17 05:25:24 PM PDT 24 |
Finished | Jul 17 05:25:30 PM PDT 24 |
Peak memory | 213760 kb |
Host | smart-cd401480-7617-4a1e-a6c8-3d1d26d927b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3639251585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3639251585 |
Directory | /workspace/12.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1946373608 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 5636284651 ps |
CPU time | 19.78 seconds |
Started | Jul 17 05:24:34 PM PDT 24 |
Finished | Jul 17 05:24:55 PM PDT 24 |
Peak memory | 213712 kb |
Host | smart-f55c5ac3-8f0f-4fca-9c85-5a73ab6fb5fb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946373608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1946373608 |
Directory | /workspace/4.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/33.rv_dm_stress_all.586536 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 3970623965 ps |
CPU time | 3.45 seconds |
Started | Jul 17 05:27:16 PM PDT 24 |
Finished | Jul 17 05:27:20 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-7ec66b70-3124-4640-9f04-4ec15cf66fa7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.586536 |
Directory | /workspace/33.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3848193447 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 4142166231 ps |
CPU time | 2.58 seconds |
Started | Jul 17 05:25:09 PM PDT 24 |
Finished | Jul 17 05:25:15 PM PDT 24 |
Peak memory | 215576 kb |
Host | smart-87a9637e-6da1-44d1-bc1f-5046dd47d4ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848193447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3848193447 |
Directory | /workspace/5.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.2849126560 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 290304114 ps |
CPU time | 1.13 seconds |
Started | Jul 17 05:25:38 PM PDT 24 |
Finished | Jul 17 05:25:40 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-9f95f890-1df0-4d22-88db-b926921aac2b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849126560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.2 849126560 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/default/7.rv_dm_stress_all.4168157909 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 4465818928 ps |
CPU time | 12 seconds |
Started | Jul 17 05:25:15 PM PDT 24 |
Finished | Jul 17 05:25:29 PM PDT 24 |
Peak memory | 213712 kb |
Host | smart-713d6454-0347-4804-866f-6e46c26a71ae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168157909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.4168157909 |
Directory | /workspace/7.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3184356346 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 2836718897 ps |
CPU time | 2.41 seconds |
Started | Jul 17 05:25:44 PM PDT 24 |
Finished | Jul 17 05:25:47 PM PDT 24 |
Peak memory | 205380 kb |
Host | smart-dfe1dedc-678f-4e10-aa18-8a86897ce9e3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184356346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_hw_reset.3184356346 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1744476302 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 911403176 ps |
CPU time | 1.08 seconds |
Started | Jul 17 05:26:49 PM PDT 24 |
Finished | Jul 17 05:26:55 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-6ad9f504-b1d7-43f1-903c-d04a153b1017 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1744476302 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1744476302 |
Directory | /workspace/0.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.3991235860 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 2030853292 ps |
CPU time | 18.54 seconds |
Started | Jul 17 05:24:27 PM PDT 24 |
Finished | Jul 17 05:24:46 PM PDT 24 |
Peak memory | 213620 kb |
Host | smart-18430ff1-2217-4ff6-8d25-dcae5497c078 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991235860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.3991235860 |
Directory | /workspace/1.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1799992364 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 4228222106 ps |
CPU time | 23.83 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:25:15 PM PDT 24 |
Peak memory | 214460 kb |
Host | smart-d2a6c2aa-bb83-4850-b89d-a42750dcd00a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799992364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1 799992364 |
Directory | /workspace/12.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_stress_all.2409772156 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 2889497223 ps |
CPU time | 9.58 seconds |
Started | Jul 17 05:26:48 PM PDT 24 |
Finished | Jul 17 05:27:02 PM PDT 24 |
Peak memory | 213412 kb |
Host | smart-1b78e466-ab90-4c7b-beb6-d115551d450f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409772156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2409772156 |
Directory | /workspace/0.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_stress_all.2078274269 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 5530170892 ps |
CPU time | 3.74 seconds |
Started | Jul 17 05:25:49 PM PDT 24 |
Finished | Jul 17 05:25:55 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-ac2b215d-6280-4e97-ac7e-6caf3428a103 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078274269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2078274269 |
Directory | /workspace/17.rv_dm_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.466151600 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 3507598732 ps |
CPU time | 31.41 seconds |
Started | Jul 17 05:23:59 PM PDT 24 |
Finished | Jul 17 05:24:32 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-1066e369-8709-4dfb-a500-4377ad6627ce |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466151600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na me 0.rv_dm_csr_aliasing.466151600 |
Directory | /workspace/0.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.3054500143 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 285522725 ps |
CPU time | 2.35 seconds |
Started | Jul 17 05:24:18 PM PDT 24 |
Finished | Jul 17 05:24:22 PM PDT 24 |
Peak memory | 221836 kb |
Host | smart-f7919cf1-3122-48b6-ac35-829705953a4e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054500143 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.3054500143 |
Directory | /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.4070742180 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 555322479 ps |
CPU time | 2.43 seconds |
Started | Jul 17 05:24:17 PM PDT 24 |
Finished | Jul 17 05:24:21 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-7f5ce635-79be-4bb0-9439-235269620065 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070742180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.4070742180 |
Directory | /workspace/0.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1465549756 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 118645265548 ps |
CPU time | 32.54 seconds |
Started | Jul 17 05:24:01 PM PDT 24 |
Finished | Jul 17 05:24:36 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-ccb07b63-f280-4444-b7ef-1d0afd1da607 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465549756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs r_aliasing.1465549756 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3278925947 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 6333978735 ps |
CPU time | 5.83 seconds |
Started | Jul 17 05:24:02 PM PDT 24 |
Finished | Jul 17 05:24:10 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-a3f648f0-1bd6-497e-94b2-d44decec9024 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278925947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. rv_dm_jtag_dmi_csr_bit_bash.3278925947 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1502470695 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 1253535235 ps |
CPU time | 1.73 seconds |
Started | Jul 17 05:25:44 PM PDT 24 |
Finished | Jul 17 05:25:47 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-dfd01f17-7d8c-4732-93d4-3f64bae61efd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502470695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1 502470695 |
Directory | /workspace/0.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3317753180 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 967603206 ps |
CPU time | 1.94 seconds |
Started | Jul 17 05:24:07 PM PDT 24 |
Finished | Jul 17 05:24:10 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-2f7996b2-93d3-4f62-9341-1c607558a040 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317753180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_aliasing.3317753180 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1920294523 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 7928112673 ps |
CPU time | 7.47 seconds |
Started | Jul 17 05:25:12 PM PDT 24 |
Finished | Jul 17 05:25:23 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-9030f950-e453-4b20-adfa-dfd88bc08e4b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920294523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_bit_bash.1920294523 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2600937520 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 249505656 ps |
CPU time | 1.08 seconds |
Started | Jul 17 05:24:07 PM PDT 24 |
Finished | Jul 17 05:24:10 PM PDT 24 |
Peak memory | 205124 kb |
Host | smart-35b16008-2be3-4b10-b307-a9e1eeb85364 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600937520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs r_hw_reset.2600937520 |
Directory | /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.210221819 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 58657333 ps |
CPU time | 0.74 seconds |
Started | Jul 17 05:24:01 PM PDT 24 |
Finished | Jul 17 05:24:04 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-f2ae468e-e62e-49ae-9459-92f5588ed6cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210221819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part ial_access.210221819 |
Directory | /workspace/0.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2626330039 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 81177808 ps |
CPU time | 0.68 seconds |
Started | Jul 17 05:24:00 PM PDT 24 |
Finished | Jul 17 05:24:03 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-58e6b516-62ac-439a-9c8c-7dbab0a8859a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626330039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2626330039 |
Directory | /workspace/0.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4210064599 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 602176474 ps |
CPU time | 4.18 seconds |
Started | Jul 17 05:24:21 PM PDT 24 |
Finished | Jul 17 05:24:27 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-0390286e-3aeb-4f31-b106-0bd416c6587d |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210064599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_ csr_outstanding.4210064599 |
Directory | /workspace/0.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1508426876 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 51174660829 ps |
CPU time | 68.91 seconds |
Started | Jul 17 05:25:44 PM PDT 24 |
Finished | Jul 17 05:26:54 PM PDT 24 |
Peak memory | 221900 kb |
Host | smart-ec2a69e3-2d59-4917-a248-7701ff7ed76a |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508426876 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1508426876 |
Directory | /workspace/0.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3553502789 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 235929064 ps |
CPU time | 3.41 seconds |
Started | Jul 17 05:24:04 PM PDT 24 |
Finished | Jul 17 05:24:09 PM PDT 24 |
Peak memory | 213688 kb |
Host | smart-9eba5fce-5251-45b1-b224-11e49e109408 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553502789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3553502789 |
Directory | /workspace/0.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2736462842 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 4388623263 ps |
CPU time | 76.42 seconds |
Started | Jul 17 05:24:17 PM PDT 24 |
Finished | Jul 17 05:25:35 PM PDT 24 |
Peak memory | 218248 kb |
Host | smart-46af1cb9-a3be-4269-b169-d58f86e07b4f |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736462842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 1.rv_dm_csr_aliasing.2736462842 |
Directory | /workspace/1.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1383547945 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 2530837523 ps |
CPU time | 33.46 seconds |
Started | Jul 17 05:24:17 PM PDT 24 |
Finished | Jul 17 05:24:52 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-49948d41-480a-4400-8be2-3b485ac04b09 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383547945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1383547945 |
Directory | /workspace/1.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.1302887709 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 584859293 ps |
CPU time | 1.72 seconds |
Started | Jul 17 05:24:17 PM PDT 24 |
Finished | Jul 17 05:24:21 PM PDT 24 |
Peak memory | 213820 kb |
Host | smart-b33afdcb-5e33-4066-a407-a304437c0a3e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302887709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.1302887709 |
Directory | /workspace/1.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3085288823 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 107777152 ps |
CPU time | 4.59 seconds |
Started | Jul 17 05:24:17 PM PDT 24 |
Finished | Jul 17 05:24:24 PM PDT 24 |
Peak memory | 220452 kb |
Host | smart-2e0aaee4-9c44-43f2-a619-202dd58dfacc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085288823 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3085288823 |
Directory | /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2802488719 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 431366711 ps |
CPU time | 2.41 seconds |
Started | Jul 17 05:24:17 PM PDT 24 |
Finished | Jul 17 05:24:22 PM PDT 24 |
Peak memory | 213648 kb |
Host | smart-717d50c1-47d6-4a3d-883e-5638b1675465 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802488719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2802488719 |
Directory | /workspace/1.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.861022353 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 43896579694 ps |
CPU time | 67.17 seconds |
Started | Jul 17 05:24:20 PM PDT 24 |
Finished | Jul 17 05:25:29 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-cc354964-d7a0-4b68-b2ef-d16ed83aa03d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861022353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr _aliasing.861022353 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3401823621 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 158487496 ps |
CPU time | 1.08 seconds |
Started | Jul 17 05:24:17 PM PDT 24 |
Finished | Jul 17 05:24:20 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-fee4bc79-6639-451b-a258-1966a06df998 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401823621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. rv_dm_jtag_dmi_csr_bit_bash.3401823621 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.108183795 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 5865294773 ps |
CPU time | 12.93 seconds |
Started | Jul 17 05:24:27 PM PDT 24 |
Finished | Jul 17 05:24:41 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-46c70fd1-f4a6-4de0-925a-71bf4a458c24 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108183795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr _hw_reset.108183795 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2106627162 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 4753528971 ps |
CPU time | 6.86 seconds |
Started | Jul 17 05:24:19 PM PDT 24 |
Finished | Jul 17 05:24:27 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-407d77c6-5319-4eca-89f1-6e288eb71732 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106627162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2 106627162 |
Directory | /workspace/1.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.286379777 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 242532958 ps |
CPU time | 0.75 seconds |
Started | Jul 17 05:25:04 PM PDT 24 |
Finished | Jul 17 05:25:06 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-0dfcf132-2ed6-480d-ae99-44a69a804821 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286379777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr _aliasing.286379777 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.740300608 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 39194863563 ps |
CPU time | 95.06 seconds |
Started | Jul 17 05:24:18 PM PDT 24 |
Finished | Jul 17 05:25:55 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-4d6dcbb6-e567-48b2-9fe6-d81bdc8d7b77 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740300608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr _bit_bash.740300608 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.7849967 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 729046242 ps |
CPU time | 1.15 seconds |
Started | Jul 17 05:24:21 PM PDT 24 |
Finished | Jul 17 05:24:24 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-bd9dd8d0-e08a-45f7-84b0-589492a8363c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7849967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_h w_reset.7849967 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3549216771 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 134124174 ps |
CPU time | 1.06 seconds |
Started | Jul 17 05:24:19 PM PDT 24 |
Finished | Jul 17 05:24:22 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-645abe3b-74dc-4ae9-8c8c-fe0d80bf2eeb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549216771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3 549216771 |
Directory | /workspace/1.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1357970262 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 67169186 ps |
CPU time | 0.79 seconds |
Started | Jul 17 05:24:21 PM PDT 24 |
Finished | Jul 17 05:24:23 PM PDT 24 |
Peak memory | 204856 kb |
Host | smart-a7382834-0417-4685-a415-44d5c76ce2b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357970262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par tial_access.1357970262 |
Directory | /workspace/1.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1625964878 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 252890841 ps |
CPU time | 0.71 seconds |
Started | Jul 17 05:24:19 PM PDT 24 |
Finished | Jul 17 05:24:21 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-b5a43acc-e2c3-462b-a88a-f6a0591420d8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625964878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1625964878 |
Directory | /workspace/1.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.599504462 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 3281126163 ps |
CPU time | 8.38 seconds |
Started | Jul 17 05:24:20 PM PDT 24 |
Finished | Jul 17 05:24:30 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-a45ef5ba-632a-4584-8421-7f8493f10286 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599504462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c sr_outstanding.599504462 |
Directory | /workspace/1.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.1393047971 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 39731532050 ps |
CPU time | 101.6 seconds |
Started | Jul 17 05:25:13 PM PDT 24 |
Finished | Jul 17 05:26:57 PM PDT 24 |
Peak memory | 221968 kb |
Host | smart-1ee67815-a950-4a5b-b256-60f0e9f4c1de |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393047971 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.1393047971 |
Directory | /workspace/1.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1092968310 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 179406424 ps |
CPU time | 3.33 seconds |
Started | Jul 17 05:24:22 PM PDT 24 |
Finished | Jul 17 05:24:28 PM PDT 24 |
Peak memory | 213636 kb |
Host | smart-da9fb001-190d-495b-a2c5-503217ae01b6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092968310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1092968310 |
Directory | /workspace/1.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3752953340 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 879835936 ps |
CPU time | 3.19 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:24:52 PM PDT 24 |
Peak memory | 219132 kb |
Host | smart-ce9a896e-04aa-4703-bc56-838d9af636bd |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752953340 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3752953340 |
Directory | /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1409008203 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 517747517 ps |
CPU time | 1.58 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:24:52 PM PDT 24 |
Peak memory | 213300 kb |
Host | smart-f4bc4e5c-1fa4-4c49-b7b3-988f5f3a36b0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409008203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1409008203 |
Directory | /workspace/10.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3429382468 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 61249600 ps |
CPU time | 0.7 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:24:50 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-ce75627d-8c3a-474f-9189-e60f6181c2c9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429382468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10 .rv_dm_jtag_dmi_csr_bit_bash.3429382468 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2021427605 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 3089667473 ps |
CPU time | 5.34 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:24:56 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-ee7bc1c8-10d2-4e53-9d64-a62ef77244ec |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021427605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw. 2021427605 |
Directory | /workspace/10.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4136399569 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 130168467 ps |
CPU time | 0.78 seconds |
Started | Jul 17 05:24:43 PM PDT 24 |
Finished | Jul 17 05:24:45 PM PDT 24 |
Peak memory | 205096 kb |
Host | smart-89444db6-2b18-4714-a476-4f2d31b42545 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136399569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw. 4136399569 |
Directory | /workspace/10.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2518988385 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 663317880 ps |
CPU time | 6.93 seconds |
Started | Jul 17 05:24:44 PM PDT 24 |
Finished | Jul 17 05:24:54 PM PDT 24 |
Peak memory | 205428 kb |
Host | smart-51c452e6-0ae5-4580-991f-a5431421b04b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518988385 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same _csr_outstanding.2518988385 |
Directory | /workspace/10.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.425734353 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 426521996 ps |
CPU time | 4.98 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:24:56 PM PDT 24 |
Peak memory | 213752 kb |
Host | smart-3fbf6e27-4c9b-4904-a801-f0b805c2447b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425734353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.425734353 |
Directory | /workspace/10.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4280466928 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 1889936853 ps |
CPU time | 8.91 seconds |
Started | Jul 17 05:24:49 PM PDT 24 |
Finished | Jul 17 05:25:01 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-5b66f566-0a27-4788-82ae-fab2ebb2e5c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280466928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.4 280466928 |
Directory | /workspace/10.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.4264113523 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 104181160 ps |
CPU time | 4.66 seconds |
Started | Jul 17 05:24:45 PM PDT 24 |
Finished | Jul 17 05:24:53 PM PDT 24 |
Peak memory | 221932 kb |
Host | smart-c8af78d5-4422-4a29-830e-6508338a9cf3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264113523 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.4264113523 |
Directory | /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.3437535517 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 253732672 ps |
CPU time | 2.33 seconds |
Started | Jul 17 05:25:44 PM PDT 24 |
Finished | Jul 17 05:25:47 PM PDT 24 |
Peak memory | 213564 kb |
Host | smart-b4f01ed0-7bf5-448b-90db-19f9f206396c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437535517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.3437535517 |
Directory | /workspace/11.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2822045847 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 23401063427 ps |
CPU time | 69.28 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:26:00 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-9cb3db29-7c29-4efd-a5ca-efcfc0ab2bf3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822045847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .rv_dm_jtag_dmi_csr_bit_bash.2822045847 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3491544045 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 5989465262 ps |
CPU time | 8.9 seconds |
Started | Jul 17 05:25:13 PM PDT 24 |
Finished | Jul 17 05:25:25 PM PDT 24 |
Peak memory | 205172 kb |
Host | smart-7686a5ea-21ea-4713-a544-f4c465bc0c51 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491544045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw. 3491544045 |
Directory | /workspace/11.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.273462632 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 94800947 ps |
CPU time | 0.86 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:24:52 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-cd873439-5dd5-411f-992c-e0eba9f3a63d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273462632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.273462632 |
Directory | /workspace/11.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.535845871 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 948092620 ps |
CPU time | 4.27 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:24:53 PM PDT 24 |
Peak memory | 205464 kb |
Host | smart-29b73faa-a4f6-4873-87a4-48e7fb4fe09e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535845871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_ csr_outstanding.535845871 |
Directory | /workspace/11.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1455166840 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 412275934 ps |
CPU time | 4.09 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:24:54 PM PDT 24 |
Peak memory | 213700 kb |
Host | smart-da7f1cf6-6c6e-4068-8dfa-b83a07c38952 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455166840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1455166840 |
Directory | /workspace/11.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.525438216 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 2536924772 ps |
CPU time | 16.93 seconds |
Started | Jul 17 05:24:48 PM PDT 24 |
Finished | Jul 17 05:25:08 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-11c3c813-169e-4b79-be6b-1eb71c59dedb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525438216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.525438216 |
Directory | /workspace/11.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.3267856034 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 109065132 ps |
CPU time | 2.23 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:24:52 PM PDT 24 |
Peak memory | 217580 kb |
Host | smart-29306f20-db10-43c1-9931-a26951062c65 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267856034 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.3267856034 |
Directory | /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3610021367 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 400457260 ps |
CPU time | 2.37 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:24:52 PM PDT 24 |
Peak memory | 213608 kb |
Host | smart-16abad1b-1ba9-47d1-abb3-fb5c919e885e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610021367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3610021367 |
Directory | /workspace/12.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.1338658518 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 5199919289 ps |
CPU time | 6.17 seconds |
Started | Jul 17 05:24:45 PM PDT 24 |
Finished | Jul 17 05:24:54 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-3e26c45b-fd10-4680-8de0-37201454b2bd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338658518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12 .rv_dm_jtag_dmi_csr_bit_bash.1338658518 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3707533677 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 11232615926 ps |
CPU time | 30.71 seconds |
Started | Jul 17 05:24:44 PM PDT 24 |
Finished | Jul 17 05:25:17 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-ad4a4149-5227-4507-af8a-0d906ccbd073 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707533677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw. 3707533677 |
Directory | /workspace/12.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.550696540 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 212775992 ps |
CPU time | 1.17 seconds |
Started | Jul 17 05:24:43 PM PDT 24 |
Finished | Jul 17 05:24:46 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-45d23159-c0d5-4823-9db4-8cf8d43d653a |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550696540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.550696540 |
Directory | /workspace/12.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3709271529 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 715121191 ps |
CPU time | 4.17 seconds |
Started | Jul 17 05:24:48 PM PDT 24 |
Finished | Jul 17 05:24:55 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-6de90a71-5712-409b-83a3-ebac779ecd74 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709271529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same _csr_outstanding.3709271529 |
Directory | /workspace/12.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.3916864543 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 855414500 ps |
CPU time | 5.41 seconds |
Started | Jul 17 05:24:43 PM PDT 24 |
Finished | Jul 17 05:24:51 PM PDT 24 |
Peak memory | 213764 kb |
Host | smart-f7119bf3-4120-4563-8ae6-4ca056fe6b88 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916864543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.3916864543 |
Directory | /workspace/12.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3683674479 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 2144072215 ps |
CPU time | 6.52 seconds |
Started | Jul 17 05:25:13 PM PDT 24 |
Finished | Jul 17 05:25:22 PM PDT 24 |
Peak memory | 219364 kb |
Host | smart-e76add51-5295-40da-8708-73c35592dfd9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683674479 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3683674479 |
Directory | /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3102159136 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 1003460709 ps |
CPU time | 1.73 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:24:52 PM PDT 24 |
Peak memory | 213572 kb |
Host | smart-3e96eccf-31cd-42cb-8767-07ee971865f6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102159136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3102159136 |
Directory | /workspace/13.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2056334035 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 66520737632 ps |
CPU time | 45.55 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:25:36 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-14324d62-d2c1-4e73-82d1-a536a5bcb8d0 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056334035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13 .rv_dm_jtag_dmi_csr_bit_bash.2056334035 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1891222257 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 3005448269 ps |
CPU time | 1.88 seconds |
Started | Jul 17 05:24:51 PM PDT 24 |
Finished | Jul 17 05:24:55 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-e39052d0-1ebe-4009-90b7-2369d69083d6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891222257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw. 1891222257 |
Directory | /workspace/13.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2884673692 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 402574997 ps |
CPU time | 1.26 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:24:50 PM PDT 24 |
Peak memory | 205076 kb |
Host | smart-1460f8f4-625f-494b-b7c8-d9f2979becdb |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884673692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw. 2884673692 |
Directory | /workspace/13.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2273487476 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 2035505850 ps |
CPU time | 4.34 seconds |
Started | Jul 17 05:27:20 PM PDT 24 |
Finished | Jul 17 05:27:26 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-661ab263-9122-42ad-9257-e3883b92628e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273487476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same _csr_outstanding.2273487476 |
Directory | /workspace/13.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1104031196 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 286221805 ps |
CPU time | 4.15 seconds |
Started | Jul 17 05:25:13 PM PDT 24 |
Finished | Jul 17 05:25:20 PM PDT 24 |
Peak memory | 213616 kb |
Host | smart-f2bee2a5-4b66-4c07-bdd0-7b09ada4cf5e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104031196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1104031196 |
Directory | /workspace/13.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1767861600 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 3140946768 ps |
CPU time | 24.25 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:25:15 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-ca7640cf-b892-410b-b24a-be0d0ee4c147 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767861600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1 767861600 |
Directory | /workspace/13.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.86432495 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 4024591069 ps |
CPU time | 6.75 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:25:59 PM PDT 24 |
Peak memory | 221824 kb |
Host | smart-442b113f-0f7f-4e6c-bb74-9921757a81a7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86432495 -assert nopostproc +UVM_TESTNAME=r v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.86432495 |
Directory | /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1228544796 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 70518138 ps |
CPU time | 2.07 seconds |
Started | Jul 17 05:25:12 PM PDT 24 |
Finished | Jul 17 05:25:17 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-9b52cd8c-d21d-4d1c-a03f-c654dcd89645 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228544796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1228544796 |
Directory | /workspace/14.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2514454566 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 63340773814 ps |
CPU time | 55.14 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:25:45 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-d17b0c61-d535-42e3-8398-b745b7fa69e9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514454566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .rv_dm_jtag_dmi_csr_bit_bash.2514454566 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2040572655 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 5189011341 ps |
CPU time | 4.8 seconds |
Started | Jul 17 05:25:13 PM PDT 24 |
Finished | Jul 17 05:25:20 PM PDT 24 |
Peak memory | 205224 kb |
Host | smart-68480ba2-e9e7-48cd-bbd2-4cc62083c2a1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040572655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw. 2040572655 |
Directory | /workspace/14.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1178982791 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 251655968 ps |
CPU time | 0.95 seconds |
Started | Jul 17 05:27:20 PM PDT 24 |
Finished | Jul 17 05:27:22 PM PDT 24 |
Peak memory | 204692 kb |
Host | smart-357a3229-6b28-4f29-aa7b-dd6854e00821 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178982791 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw. 1178982791 |
Directory | /workspace/14.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1886256373 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 1457833277 ps |
CPU time | 7.86 seconds |
Started | Jul 17 05:24:43 PM PDT 24 |
Finished | Jul 17 05:24:52 PM PDT 24 |
Peak memory | 205628 kb |
Host | smart-22d8a523-9e01-4a4e-b43c-768a89961cb3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886256373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same _csr_outstanding.1886256373 |
Directory | /workspace/14.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.1291754306 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 239539028 ps |
CPU time | 5.65 seconds |
Started | Jul 17 05:25:13 PM PDT 24 |
Finished | Jul 17 05:25:21 PM PDT 24 |
Peak memory | 213624 kb |
Host | smart-16b3286d-0cdc-4cee-9002-b062f3f207f0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291754306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.1291754306 |
Directory | /workspace/14.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3157823627 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 4093310042 ps |
CPU time | 20.42 seconds |
Started | Jul 17 05:25:49 PM PDT 24 |
Finished | Jul 17 05:26:11 PM PDT 24 |
Peak memory | 213688 kb |
Host | smart-8264d342-7b1c-4898-a59c-19ffdfe2800e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157823627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3 157823627 |
Directory | /workspace/14.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2146893171 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 3717572372 ps |
CPU time | 6.24 seconds |
Started | Jul 17 05:24:48 PM PDT 24 |
Finished | Jul 17 05:24:58 PM PDT 24 |
Peak memory | 220308 kb |
Host | smart-c40b4bd6-b727-45a5-a823-c240e17a659a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146893171 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2146893171 |
Directory | /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.357465718 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 409635465 ps |
CPU time | 2.47 seconds |
Started | Jul 17 05:24:45 PM PDT 24 |
Finished | Jul 17 05:24:50 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-1bf216b2-2118-45ab-8c7b-f4fe4a2d285a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357465718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.357465718 |
Directory | /workspace/15.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1609856489 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 47410525622 ps |
CPU time | 60.18 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:25:50 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-49d83dbc-734e-4d41-ad12-0f540a0c2eca |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609856489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .rv_dm_jtag_dmi_csr_bit_bash.1609856489 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.187169911 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 4695008782 ps |
CPU time | 12.78 seconds |
Started | Jul 17 05:24:48 PM PDT 24 |
Finished | Jul 17 05:25:04 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-ef46278b-c1f9-441a-a600-4b1834cdf02d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187169911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.187169911 |
Directory | /workspace/15.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4280446365 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 277483227 ps |
CPU time | 0.77 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:24:51 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-7012d282-5f00-46b0-91da-1a77633fdb60 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280446365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw. 4280446365 |
Directory | /workspace/15.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.318659022 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 247129425 ps |
CPU time | 3.59 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:24:55 PM PDT 24 |
Peak memory | 205640 kb |
Host | smart-242cd158-9478-43ca-ab16-205b6d55753a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318659022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_ csr_outstanding.318659022 |
Directory | /workspace/15.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3128419330 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 130393864 ps |
CPU time | 4.65 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:24:54 PM PDT 24 |
Peak memory | 213768 kb |
Host | smart-8711de88-e665-4220-be2e-52409cba7d89 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128419330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3128419330 |
Directory | /workspace/15.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3325362364 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 3574734881 ps |
CPU time | 11.22 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:25:00 PM PDT 24 |
Peak memory | 213748 kb |
Host | smart-dfe426f1-d200-4fb3-9090-9906974b82c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325362364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3 325362364 |
Directory | /workspace/15.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2367431692 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 2553632287 ps |
CPU time | 4.47 seconds |
Started | Jul 17 05:25:04 PM PDT 24 |
Finished | Jul 17 05:25:10 PM PDT 24 |
Peak memory | 219472 kb |
Host | smart-12f9e0a5-0374-422c-b2d8-848bac189a95 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367431692 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2367431692 |
Directory | /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.923398651 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 210772021 ps |
CPU time | 2.55 seconds |
Started | Jul 17 05:24:50 PM PDT 24 |
Finished | Jul 17 05:24:55 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-be688bcb-fc63-411f-9fa4-c4f094426f55 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923398651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.923398651 |
Directory | /workspace/16.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2454117642 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 3933671692 ps |
CPU time | 4.45 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:24:55 PM PDT 24 |
Peak memory | 205568 kb |
Host | smart-4ab9af93-1a0e-47ff-8320-26db4aef84c9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454117642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .rv_dm_jtag_dmi_csr_bit_bash.2454117642 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.383076803 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 2687652798 ps |
CPU time | 4.79 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:24:54 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-978054b6-e2e2-46bb-b6d7-719f1f62bf8c |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383076803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.383076803 |
Directory | /workspace/16.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1891761591 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 362386311 ps |
CPU time | 0.82 seconds |
Started | Jul 17 05:24:48 PM PDT 24 |
Finished | Jul 17 05:24:52 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-c64784a6-d702-4aec-8be6-087847755ab1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891761591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw. 1891761591 |
Directory | /workspace/16.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1089810387 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 589314851 ps |
CPU time | 6.8 seconds |
Started | Jul 17 05:27:20 PM PDT 24 |
Finished | Jul 17 05:27:28 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-51f2e9ad-967f-4e25-b027-03d6ec0bfca6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089810387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same _csr_outstanding.1089810387 |
Directory | /workspace/16.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2613856583 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 124244042 ps |
CPU time | 4.79 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:24:54 PM PDT 24 |
Peak memory | 213692 kb |
Host | smart-88202e7d-9af2-4af5-8437-10fc39000494 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613856583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2613856583 |
Directory | /workspace/16.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3377324905 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 2179549733 ps |
CPU time | 19.03 seconds |
Started | Jul 17 05:24:50 PM PDT 24 |
Finished | Jul 17 05:25:12 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-692ee135-3fe0-4a64-b1ae-8ec28a8ff046 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377324905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3 377324905 |
Directory | /workspace/16.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.799012108 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 2886092565 ps |
CPU time | 5.27 seconds |
Started | Jul 17 05:26:21 PM PDT 24 |
Finished | Jul 17 05:26:26 PM PDT 24 |
Peak memory | 221884 kb |
Host | smart-0ba7de7c-5a07-41c6-8583-8c5c96322dd6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799012108 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.799012108 |
Directory | /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1297928742 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 438483425 ps |
CPU time | 2.41 seconds |
Started | Jul 17 05:25:59 PM PDT 24 |
Finished | Jul 17 05:26:02 PM PDT 24 |
Peak memory | 213636 kb |
Host | smart-3a4cee48-9b21-4946-a9f3-09651dd8f014 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297928742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1297928742 |
Directory | /workspace/17.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2226633208 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 9464337170 ps |
CPU time | 9.19 seconds |
Started | Jul 17 05:25:01 PM PDT 24 |
Finished | Jul 17 05:25:11 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-3770c687-9fac-475c-bd61-0e811e1e89ef |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226633208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .rv_dm_jtag_dmi_csr_bit_bash.2226633208 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3303610858 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 1459964600 ps |
CPU time | 2.47 seconds |
Started | Jul 17 05:24:56 PM PDT 24 |
Finished | Jul 17 05:25:00 PM PDT 24 |
Peak memory | 205292 kb |
Host | smart-128dc96c-bdba-4fe3-850a-2d7ccf628d92 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303610858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw. 3303610858 |
Directory | /workspace/17.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2363102588 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 484083353 ps |
CPU time | 1.5 seconds |
Started | Jul 17 05:25:01 PM PDT 24 |
Finished | Jul 17 05:25:04 PM PDT 24 |
Peak memory | 205100 kb |
Host | smart-1a3ee46e-3ae6-49fe-80f3-9176ece3ce47 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363102588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw. 2363102588 |
Directory | /workspace/17.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3060765538 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 282922173 ps |
CPU time | 4.16 seconds |
Started | Jul 17 05:24:58 PM PDT 24 |
Finished | Jul 17 05:25:03 PM PDT 24 |
Peak memory | 205384 kb |
Host | smart-39f04906-6ff3-43e0-a80d-b5dda9f456dd |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060765538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same _csr_outstanding.3060765538 |
Directory | /workspace/17.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2304769460 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 655038277 ps |
CPU time | 6.52 seconds |
Started | Jul 17 05:27:13 PM PDT 24 |
Finished | Jul 17 05:27:20 PM PDT 24 |
Peak memory | 213660 kb |
Host | smart-c50e034c-084e-4b79-b667-5675ae5b3a03 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304769460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2304769460 |
Directory | /workspace/17.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2357970491 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 3884107235 ps |
CPU time | 19.25 seconds |
Started | Jul 17 05:24:56 PM PDT 24 |
Finished | Jul 17 05:25:16 PM PDT 24 |
Peak memory | 213712 kb |
Host | smart-92588d5a-9742-4b05-9043-c69fc59fa1da |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357970491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2 357970491 |
Directory | /workspace/17.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2335460228 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 5672490580 ps |
CPU time | 6.71 seconds |
Started | Jul 17 05:24:56 PM PDT 24 |
Finished | Jul 17 05:25:03 PM PDT 24 |
Peak memory | 218792 kb |
Host | smart-14156716-1865-4344-be8d-c66b264d1894 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335460228 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2335460228 |
Directory | /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2964219320 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 161196294 ps |
CPU time | 1.57 seconds |
Started | Jul 17 05:24:56 PM PDT 24 |
Finished | Jul 17 05:24:59 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-6d7840e2-7f3f-41cb-ad05-18823ba118f8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964219320 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2964219320 |
Directory | /workspace/18.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2046100855 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 10381829694 ps |
CPU time | 15.1 seconds |
Started | Jul 17 05:25:05 PM PDT 24 |
Finished | Jul 17 05:25:21 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-29c5608d-144c-41bf-9066-e63d7063df07 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046100855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .rv_dm_jtag_dmi_csr_bit_bash.2046100855 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2760675480 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 2847709166 ps |
CPU time | 3.77 seconds |
Started | Jul 17 05:27:13 PM PDT 24 |
Finished | Jul 17 05:27:18 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-41e4aafd-8cb2-4b97-80b5-b2555e41c57b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760675480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw. 2760675480 |
Directory | /workspace/18.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2220489916 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 351639266 ps |
CPU time | 1.15 seconds |
Started | Jul 17 05:25:07 PM PDT 24 |
Finished | Jul 17 05:25:10 PM PDT 24 |
Peak memory | 205056 kb |
Host | smart-f75deb43-a14e-4220-b062-0f1a3884d982 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220489916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw. 2220489916 |
Directory | /workspace/18.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2050504755 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 192691696 ps |
CPU time | 3.64 seconds |
Started | Jul 17 05:24:55 PM PDT 24 |
Finished | Jul 17 05:25:00 PM PDT 24 |
Peak memory | 205452 kb |
Host | smart-ed1e3c2a-226d-425a-a351-d2f7f04c66fc |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050504755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same _csr_outstanding.2050504755 |
Directory | /workspace/18.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1912908569 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 142442692 ps |
CPU time | 5.31 seconds |
Started | Jul 17 05:24:59 PM PDT 24 |
Finished | Jul 17 05:25:06 PM PDT 24 |
Peak memory | 213940 kb |
Host | smart-735490ca-5de4-4ccc-b8af-488e398cbfc4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912908569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1912908569 |
Directory | /workspace/18.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.58987576 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 1164112555 ps |
CPU time | 17.93 seconds |
Started | Jul 17 05:24:58 PM PDT 24 |
Finished | Jul 17 05:25:17 PM PDT 24 |
Peak memory | 213640 kb |
Host | smart-c2a71ca0-443a-4195-9d4e-8ee7dd6ca64f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58987576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.58987576 |
Directory | /workspace/18.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3414292858 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 508517556 ps |
CPU time | 3.94 seconds |
Started | Jul 17 05:26:51 PM PDT 24 |
Finished | Jul 17 05:27:01 PM PDT 24 |
Peak memory | 219424 kb |
Host | smart-2a81b0cc-47ab-4a1b-8f70-4456eeb40dc7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414292858 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3414292858 |
Directory | /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3365462952 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 292363050 ps |
CPU time | 2.3 seconds |
Started | Jul 17 05:25:00 PM PDT 24 |
Finished | Jul 17 05:25:03 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-5239797a-c9ae-4b25-b1c4-334c70850f13 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365462952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3365462952 |
Directory | /workspace/19.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1062037558 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 11834023020 ps |
CPU time | 13.42 seconds |
Started | Jul 17 05:27:01 PM PDT 24 |
Finished | Jul 17 05:27:15 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-a7b891df-1163-4e84-80dc-b1b8c761aba6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062037558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .rv_dm_jtag_dmi_csr_bit_bash.1062037558 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.939305394 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 1214125374 ps |
CPU time | 1.62 seconds |
Started | Jul 17 05:24:58 PM PDT 24 |
Finished | Jul 17 05:25:01 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-bf8e0dbf-b6c7-4b5c-94fa-3afea01131a7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939305394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.939305394 |
Directory | /workspace/19.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.994236442 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 103368459 ps |
CPU time | 0.92 seconds |
Started | Jul 17 05:24:55 PM PDT 24 |
Finished | Jul 17 05:24:57 PM PDT 24 |
Peak memory | 205080 kb |
Host | smart-45dd145b-c5e2-403e-b686-9aa2210bf342 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994236442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.994236442 |
Directory | /workspace/19.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1346827717 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 463190594 ps |
CPU time | 7.34 seconds |
Started | Jul 17 05:24:56 PM PDT 24 |
Finished | Jul 17 05:25:04 PM PDT 24 |
Peak memory | 205516 kb |
Host | smart-0c3fb5af-d31e-4fb9-ab7f-d0fca1dec5b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346827717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same _csr_outstanding.1346827717 |
Directory | /workspace/19.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2208105668 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 177444743 ps |
CPU time | 3.68 seconds |
Started | Jul 17 05:26:59 PM PDT 24 |
Finished | Jul 17 05:27:03 PM PDT 24 |
Peak memory | 213668 kb |
Host | smart-7d171793-6126-4766-a46e-1d92bd7a54ac |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208105668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2208105668 |
Directory | /workspace/19.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2949461607 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 2155157352 ps |
CPU time | 19.67 seconds |
Started | Jul 17 05:24:56 PM PDT 24 |
Finished | Jul 17 05:25:17 PM PDT 24 |
Peak memory | 213708 kb |
Host | smart-1bc6556b-6953-4d08-9d77-91d677411b5b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949461607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2 949461607 |
Directory | /workspace/19.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2919370494 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 2414944132 ps |
CPU time | 33.34 seconds |
Started | Jul 17 05:25:10 PM PDT 24 |
Finished | Jul 17 05:25:46 PM PDT 24 |
Peak memory | 205496 kb |
Host | smart-db280589-f325-483b-957d-f2ba6ead980e |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919370494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 2.rv_dm_csr_aliasing.2919370494 |
Directory | /workspace/2.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.518546080 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 2907760222 ps |
CPU time | 33.61 seconds |
Started | Jul 17 05:24:20 PM PDT 24 |
Finished | Jul 17 05:24:55 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-986de2bb-23df-4794-b1d8-d495000340ee |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518546080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.518546080 |
Directory | /workspace/2.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2630445003 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 245733213 ps |
CPU time | 2.59 seconds |
Started | Jul 17 05:24:17 PM PDT 24 |
Finished | Jul 17 05:24:22 PM PDT 24 |
Peak memory | 213660 kb |
Host | smart-6191d7ef-5aae-43e1-86d3-7490306bba7d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630445003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2630445003 |
Directory | /workspace/2.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.446567156 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 1457760169 ps |
CPU time | 5.69 seconds |
Started | Jul 17 05:24:18 PM PDT 24 |
Finished | Jul 17 05:24:25 PM PDT 24 |
Peak memory | 221388 kb |
Host | smart-41c1d43c-4354-46d3-a16a-97a8d563845a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446567156 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.446567156 |
Directory | /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.208426895 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 352053576 ps |
CPU time | 2.33 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:25:54 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-a491e09f-9bab-4f2c-a140-0bdca59a1c10 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208426895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.208426895 |
Directory | /workspace/2.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.949101928 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 13560106923 ps |
CPU time | 24.35 seconds |
Started | Jul 17 05:24:20 PM PDT 24 |
Finished | Jul 17 05:24:46 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-a1927d43-5ba8-4352-bfae-7112e6420b4e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949101928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr _aliasing.949101928 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.782602766 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 5172582936 ps |
CPU time | 4.76 seconds |
Started | Jul 17 05:24:17 PM PDT 24 |
Finished | Jul 17 05:24:24 PM PDT 24 |
Peak memory | 205324 kb |
Host | smart-fed2ca90-9d13-4fcc-a0f7-1e20863709c1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782602766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.r v_dm_jtag_dmi_csr_bit_bash.782602766 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1636276760 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 8135994731 ps |
CPU time | 14.06 seconds |
Started | Jul 17 05:25:24 PM PDT 24 |
Finished | Jul 17 05:25:40 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-68274e9d-36a4-4e19-b32f-60eec5130eee |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636276760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs r_hw_reset.1636276760 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.556012529 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 2844900739 ps |
CPU time | 6.33 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:25:58 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-5828d631-3332-4f1a-ada4-a7918c9915c8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556012529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.556012529 |
Directory | /workspace/2.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.1347323308 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 1291905949 ps |
CPU time | 2.41 seconds |
Started | Jul 17 05:25:10 PM PDT 24 |
Finished | Jul 17 05:25:15 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-e3f30fbc-7eca-4d68-a1f2-473919e0365b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347323308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_aliasing.1347323308 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2471374711 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 5509152034 ps |
CPU time | 5.21 seconds |
Started | Jul 17 05:24:22 PM PDT 24 |
Finished | Jul 17 05:24:29 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-576b37d0-08a4-4d36-be8b-cb176f6e8d11 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471374711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_bit_bash.2471374711 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2285579532 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 1227207234 ps |
CPU time | 2.31 seconds |
Started | Jul 17 05:24:20 PM PDT 24 |
Finished | Jul 17 05:24:24 PM PDT 24 |
Peak memory | 205088 kb |
Host | smart-5a82a550-072c-4f60-8c7a-5241d29b9454 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285579532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs r_hw_reset.2285579532 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1796489352 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 295757700 ps |
CPU time | 0.88 seconds |
Started | Jul 17 05:24:16 PM PDT 24 |
Finished | Jul 17 05:24:19 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-e5c723fc-400b-4c1d-a14b-94b56b391ac2 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796489352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1 796489352 |
Directory | /workspace/2.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3720405760 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 149117440 ps |
CPU time | 0.83 seconds |
Started | Jul 17 05:24:38 PM PDT 24 |
Finished | Jul 17 05:24:40 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-6f55f477-d8a6-4683-88ee-8f1eaa18ae10 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720405760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par tial_access.3720405760 |
Directory | /workspace/2.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3213593373 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 56301040 ps |
CPU time | 0.67 seconds |
Started | Jul 17 05:24:28 PM PDT 24 |
Finished | Jul 17 05:24:29 PM PDT 24 |
Peak memory | 205036 kb |
Host | smart-69eccdee-35d6-4bcf-bad0-579eb2fc4646 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213593373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3213593373 |
Directory | /workspace/2.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3927052151 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 588749809 ps |
CPU time | 7.85 seconds |
Started | Jul 17 05:24:22 PM PDT 24 |
Finished | Jul 17 05:24:32 PM PDT 24 |
Peak memory | 205412 kb |
Host | smart-40443df0-dfbd-4690-b72d-812131607e28 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927052151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_ csr_outstanding.3927052151 |
Directory | /workspace/2.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2283074432 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 1624603900 ps |
CPU time | 9.7 seconds |
Started | Jul 17 05:24:21 PM PDT 24 |
Finished | Jul 17 05:24:32 PM PDT 24 |
Peak memory | 221780 kb |
Host | smart-cafbeb7a-479d-496b-acf7-2a53965b4783 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283074432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2283074432 |
Directory | /workspace/2.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.83313773 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 1789404030 ps |
CPU time | 29.1 seconds |
Started | Jul 17 05:24:27 PM PDT 24 |
Finished | Jul 17 05:24:57 PM PDT 24 |
Peak memory | 214736 kb |
Host | smart-ca96ac03-3a2e-4636-ba63-3189360b0aa3 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83313773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UV M_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.rv_dm_csr_aliasing.83313773 |
Directory | /workspace/3.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1725491592 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 4409589574 ps |
CPU time | 31.68 seconds |
Started | Jul 17 05:24:38 PM PDT 24 |
Finished | Jul 17 05:25:11 PM PDT 24 |
Peak memory | 213560 kb |
Host | smart-4c2960fa-272b-45f1-8358-5a0266dd6e65 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725491592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1725491592 |
Directory | /workspace/3.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.572416163 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 206093042 ps |
CPU time | 1.84 seconds |
Started | Jul 17 05:24:40 PM PDT 24 |
Finished | Jul 17 05:24:43 PM PDT 24 |
Peak memory | 213648 kb |
Host | smart-91f21ef3-5dfc-4649-9f5b-c7a122478435 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572416163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.572416163 |
Directory | /workspace/3.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.4052746240 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 296386427 ps |
CPU time | 2.56 seconds |
Started | Jul 17 05:27:20 PM PDT 24 |
Finished | Jul 17 05:27:24 PM PDT 24 |
Peak memory | 221788 kb |
Host | smart-6ada5bcc-2b34-4d7f-a7e0-595b94a18758 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052746240 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.4052746240 |
Directory | /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.525286717 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 316410739 ps |
CPU time | 2.02 seconds |
Started | Jul 17 05:25:44 PM PDT 24 |
Finished | Jul 17 05:25:47 PM PDT 24 |
Peak memory | 213616 kb |
Host | smart-4b62155c-1981-42e5-9f63-0390040b928b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525286717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.525286717 |
Directory | /workspace/3.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1007969339 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 36461630645 ps |
CPU time | 95.45 seconds |
Started | Jul 17 05:26:48 PM PDT 24 |
Finished | Jul 17 05:28:28 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-090dc0a2-a6fc-4341-82fc-a598efbb9dfe |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007969339 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_aliasing.1007969339 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2499072335 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 12314678143 ps |
CPU time | 20.55 seconds |
Started | Jul 17 05:24:19 PM PDT 24 |
Finished | Jul 17 05:24:41 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-4db98af1-d46c-4688-b433-988f41e44cc1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499072335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. rv_dm_jtag_dmi_csr_bit_bash.2499072335 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2488878725 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 2555632341 ps |
CPU time | 6.12 seconds |
Started | Jul 17 05:24:27 PM PDT 24 |
Finished | Jul 17 05:24:34 PM PDT 24 |
Peak memory | 205268 kb |
Host | smart-3340e766-7d22-4606-8163-1d09ca8fc9b1 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488878725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs r_hw_reset.2488878725 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.4006225747 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 2916009613 ps |
CPU time | 5.41 seconds |
Started | Jul 17 05:24:16 PM PDT 24 |
Finished | Jul 17 05:24:23 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-103926fe-386b-458d-b0c8-8ba4f2cecb12 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006225747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.4 006225747 |
Directory | /workspace/3.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2581328906 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 2223812244 ps |
CPU time | 2.42 seconds |
Started | Jul 17 05:24:19 PM PDT 24 |
Finished | Jul 17 05:24:23 PM PDT 24 |
Peak memory | 205068 kb |
Host | smart-6af2197c-33c3-42c5-9cee-022c115adc55 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581328906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_aliasing.2581328906 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2521191489 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 7539493345 ps |
CPU time | 21.08 seconds |
Started | Jul 17 05:25:13 PM PDT 24 |
Finished | Jul 17 05:25:36 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-6383b817-aa1c-4296-b7da-ab442bc719b9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521191489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs r_bit_bash.2521191489 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.185960422 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 660073232 ps |
CPU time | 1.82 seconds |
Started | Jul 17 05:25:09 PM PDT 24 |
Finished | Jul 17 05:25:14 PM PDT 24 |
Peak memory | 205144 kb |
Host | smart-f13484ed-ef7d-4ec2-aa3a-168f1ef5cb79 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185960422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr _hw_reset.185960422 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.378239919 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 231794934 ps |
CPU time | 1.14 seconds |
Started | Jul 17 05:25:24 PM PDT 24 |
Finished | Jul 17 05:25:26 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-d29e7be9-2df1-4dc2-b3e5-9d41aff0af04 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378239919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.378239919 |
Directory | /workspace/3.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2647342787 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 121272356 ps |
CPU time | 0.67 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:24:38 PM PDT 24 |
Peak memory | 205052 kb |
Host | smart-65d5911e-b91a-4732-b78a-99deadf8dfb5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647342787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par tial_access.2647342787 |
Directory | /workspace/3.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.92718259 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 43536085 ps |
CPU time | 0.77 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:24:37 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-b5ddeb8c-0b8e-4598-934c-bf5aa2067f7a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92718259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.92718259 |
Directory | /workspace/3.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1180693361 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 155247474 ps |
CPU time | 6.36 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:24:43 PM PDT 24 |
Peak memory | 205492 kb |
Host | smart-107f9ca9-07db-42c3-b5b5-bab1fba9d373 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180693361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_ csr_outstanding.1180693361 |
Directory | /workspace/3.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1273783652 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 110819371 ps |
CPU time | 2.64 seconds |
Started | Jul 17 05:24:33 PM PDT 24 |
Finished | Jul 17 05:24:37 PM PDT 24 |
Peak memory | 213776 kb |
Host | smart-de07e6c9-0960-40bd-a756-9708eeb3d1ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273783652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.1273783652 |
Directory | /workspace/3.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1729120160 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 9141231190 ps |
CPU time | 32.8 seconds |
Started | Jul 17 05:24:34 PM PDT 24 |
Finished | Jul 17 05:25:09 PM PDT 24 |
Peak memory | 213712 kb |
Host | smart-6dbe5628-ee78-4279-9c28-0af4ea483262 |
User | root |
Command | /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729120160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test + UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 4.rv_dm_csr_aliasing.1729120160 |
Directory | /workspace/4.rv_dm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1331971505 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 732801609 ps |
CPU time | 27.27 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:25:04 PM PDT 24 |
Peak memory | 205432 kb |
Host | smart-25b2fd1c-af35-4e4d-9def-c9482c673288 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331971505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1331971505 |
Directory | /workspace/4.rv_dm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2989179137 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 216951474 ps |
CPU time | 1.58 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:24:38 PM PDT 24 |
Peak memory | 213580 kb |
Host | smart-2fac6548-b03d-44dd-8ad7-57be048465ed |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989179137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2989179137 |
Directory | /workspace/4.rv_dm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1648153511 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 670146723 ps |
CPU time | 4.14 seconds |
Started | Jul 17 05:24:38 PM PDT 24 |
Finished | Jul 17 05:24:43 PM PDT 24 |
Peak memory | 221800 kb |
Host | smart-7cd523a2-72b8-4939-ae31-e8eb061920d0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648153511 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1648153511 |
Directory | /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2448574688 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 61420092 ps |
CPU time | 1.41 seconds |
Started | Jul 17 05:25:12 PM PDT 24 |
Finished | Jul 17 05:25:17 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-c3273698-5c26-4e5f-aaf0-e5304cef0c14 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448574688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2448574688 |
Directory | /workspace/4.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1026117121 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 30029285957 ps |
CPU time | 81.73 seconds |
Started | Jul 17 05:24:33 PM PDT 24 |
Finished | Jul 17 05:25:56 PM PDT 24 |
Peak memory | 205276 kb |
Host | smart-d145e7e8-a4bc-4d5e-8e11-90fd0785a9f6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026117121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_aliasing.1026117121 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1779611227 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 9995369018 ps |
CPU time | 29.17 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:25:05 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-c9a04c7d-df64-4e2c-b188-5eaeaa5b44f8 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779611227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4. rv_dm_jtag_dmi_csr_bit_bash.1779611227 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2365614839 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 4408539619 ps |
CPU time | 11.89 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:24:48 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-8e742f0b-943d-4f2e-a978-0c8d732a7b54 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365614839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs r_hw_reset.2365614839 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1227192201 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 7515281836 ps |
CPU time | 6.34 seconds |
Started | Jul 17 05:27:03 PM PDT 24 |
Finished | Jul 17 05:27:10 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-1207530e-aa44-4292-90c1-5c9e33c4e91e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227192201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1 227192201 |
Directory | /workspace/4.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.45609837 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 650135057 ps |
CPU time | 2.29 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:24:39 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-fbd6c199-4eb8-4df1-8491-bbf7e7f7588e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45609837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_ aliasing.45609837 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1337125596 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 9151455799 ps |
CPU time | 8.34 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:24:45 PM PDT 24 |
Peak memory | 205180 kb |
Host | smart-e3cd576c-db2a-47fd-9032-52fd0e272817 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337125596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_bit_bash.1337125596 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2570100552 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 467601744 ps |
CPU time | 1.83 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:24:39 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-45251312-32eb-415f-8771-8af12fac63a6 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570100552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs r_hw_reset.2570100552 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1818355934 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 350203499 ps |
CPU time | 0.92 seconds |
Started | Jul 17 05:24:40 PM PDT 24 |
Finished | Jul 17 05:24:42 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-2f4191c7-61cc-4764-9488-4aa90f988c9f |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818355934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1 818355934 |
Directory | /workspace/4.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.4266503971 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 161922159 ps |
CPU time | 0.83 seconds |
Started | Jul 17 05:24:43 PM PDT 24 |
Finished | Jul 17 05:24:46 PM PDT 24 |
Peak memory | 205064 kb |
Host | smart-330d573d-c95c-43cd-93c4-22dbbf9c73b5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266503971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par tial_access.4266503971 |
Directory | /workspace/4.rv_dm_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1464487033 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 60872378 ps |
CPU time | 0.75 seconds |
Started | Jul 17 05:24:41 PM PDT 24 |
Finished | Jul 17 05:24:43 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-4a6d9c28-6af8-44cf-b1c5-7d38bd6e0a68 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464487033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1464487033 |
Directory | /workspace/4.rv_dm_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1546874549 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 52111281097 ps |
CPU time | 88.48 seconds |
Started | Jul 17 05:24:37 PM PDT 24 |
Finished | Jul 17 05:26:07 PM PDT 24 |
Peak memory | 222848 kb |
Host | smart-bd5818b5-52f8-4502-b288-7905bbfbb73b |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546874549 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1546874549 |
Directory | /workspace/4.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2115430737 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 282572080 ps |
CPU time | 5.53 seconds |
Started | Jul 17 05:24:33 PM PDT 24 |
Finished | Jul 17 05:24:40 PM PDT 24 |
Peak memory | 213780 kb |
Host | smart-63341fb3-68be-4a56-930b-0ae840be4ca0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115430737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2115430737 |
Directory | /workspace/4.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2388641720 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 1350299753 ps |
CPU time | 4.88 seconds |
Started | Jul 17 05:25:43 PM PDT 24 |
Finished | Jul 17 05:25:48 PM PDT 24 |
Peak memory | 220092 kb |
Host | smart-93d95b32-c73e-4856-9fea-df6f4ea9ec31 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388641720 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2388641720 |
Directory | /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2977938424 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 368082464 ps |
CPU time | 2.31 seconds |
Started | Jul 17 05:24:36 PM PDT 24 |
Finished | Jul 17 05:24:40 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-69e2d579-654f-46ac-8841-33487c963450 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977938424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2977938424 |
Directory | /workspace/5.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1372950992 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 5011266777 ps |
CPU time | 14.53 seconds |
Started | Jul 17 05:24:43 PM PDT 24 |
Finished | Jul 17 05:25:00 PM PDT 24 |
Peak memory | 205284 kb |
Host | smart-0fa5e188-4418-494a-b4c9-a04a630f2638 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372950992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. rv_dm_jtag_dmi_csr_bit_bash.1372950992 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1072356169 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 4626232074 ps |
CPU time | 13.04 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:24:50 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-342a77ce-e27d-41ca-a07e-ed7ccc586bc9 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072356169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1 072356169 |
Directory | /workspace/5.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3647931406 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 262841762 ps |
CPU time | 1.35 seconds |
Started | Jul 17 05:25:24 PM PDT 24 |
Finished | Jul 17 05:25:26 PM PDT 24 |
Peak memory | 205084 kb |
Host | smart-e69a839b-480d-4afe-9911-0f0b57b7db0b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647931406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3 647931406 |
Directory | /workspace/5.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.631324957 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 3955402717 ps |
CPU time | 7.49 seconds |
Started | Jul 17 05:24:40 PM PDT 24 |
Finished | Jul 17 05:24:49 PM PDT 24 |
Peak memory | 205588 kb |
Host | smart-20321174-2b8b-4008-98c3-829cbdade2d3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631324957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c sr_outstanding.631324957 |
Directory | /workspace/5.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.887583566 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 78418914858 ps |
CPU time | 24.78 seconds |
Started | Jul 17 05:25:04 PM PDT 24 |
Finished | Jul 17 05:25:30 PM PDT 24 |
Peak memory | 230124 kb |
Host | smart-65af620f-96e0-4315-a7b3-0da7249e5ab1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887583566 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.887583566 |
Directory | /workspace/5.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2701852441 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 188089476 ps |
CPU time | 4.6 seconds |
Started | Jul 17 05:24:41 PM PDT 24 |
Finished | Jul 17 05:24:46 PM PDT 24 |
Peak memory | 213644 kb |
Host | smart-3d0fb7b5-378d-4d3b-ac4c-56d77e984b1b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701852441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2701852441 |
Directory | /workspace/5.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1330480973 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 923406851 ps |
CPU time | 10.9 seconds |
Started | Jul 17 05:25:58 PM PDT 24 |
Finished | Jul 17 05:26:10 PM PDT 24 |
Peak memory | 213704 kb |
Host | smart-300f6440-c1df-4885-a41b-c2f346ff9aea |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330480973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1330480973 |
Directory | /workspace/5.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2448291237 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 2431363263 ps |
CPU time | 3.39 seconds |
Started | Jul 17 05:24:45 PM PDT 24 |
Finished | Jul 17 05:24:51 PM PDT 24 |
Peak memory | 218800 kb |
Host | smart-ffaa8d9a-20c8-4667-8414-0d1c971e485b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448291237 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2448291237 |
Directory | /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1079588727 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 120586778 ps |
CPU time | 2.31 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:24:39 PM PDT 24 |
Peak memory | 213564 kb |
Host | smart-96bc8862-d188-44be-ae71-6fc4f63d34f1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079588727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1079588727 |
Directory | /workspace/6.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.3219714882 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 38232050295 ps |
CPU time | 50.57 seconds |
Started | Jul 17 05:24:36 PM PDT 24 |
Finished | Jul 17 05:25:28 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-bdb03021-6c2f-4735-b5cc-236a810e0c51 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219714882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. rv_dm_jtag_dmi_csr_bit_bash.3219714882 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3832019902 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 10489873985 ps |
CPU time | 15.38 seconds |
Started | Jul 17 05:24:33 PM PDT 24 |
Finished | Jul 17 05:24:50 PM PDT 24 |
Peak memory | 205304 kb |
Host | smart-c15ac2ac-d39c-49ce-aa50-d36eaa80bcf7 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832019902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3 832019902 |
Directory | /workspace/6.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.3293410622 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 757367452 ps |
CPU time | 2.57 seconds |
Started | Jul 17 05:24:33 PM PDT 24 |
Finished | Jul 17 05:24:37 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-b271d7d2-b829-4299-8054-7c953c387655 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293410622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.3 293410622 |
Directory | /workspace/6.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.789626827 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 371087660 ps |
CPU time | 6.48 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:24:43 PM PDT 24 |
Peak memory | 205448 kb |
Host | smart-afdd6007-863d-427b-a587-f7f927d89c82 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789626827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c sr_outstanding.789626827 |
Directory | /workspace/6.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3642723754 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 201480631 ps |
CPU time | 4.39 seconds |
Started | Jul 17 05:24:35 PM PDT 24 |
Finished | Jul 17 05:24:41 PM PDT 24 |
Peak memory | 213608 kb |
Host | smart-5fc5cd6b-bd42-4573-8648-12306c8c930d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642723754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3642723754 |
Directory | /workspace/6.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2757909848 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 492606731 ps |
CPU time | 8.92 seconds |
Started | Jul 17 05:24:37 PM PDT 24 |
Finished | Jul 17 05:24:47 PM PDT 24 |
Peak memory | 213588 kb |
Host | smart-fafc5116-2f14-4595-aa23-e4d01338ee6a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757909848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2757909848 |
Directory | /workspace/6.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.365234238 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 212335615 ps |
CPU time | 4.09 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:24:54 PM PDT 24 |
Peak memory | 221008 kb |
Host | smart-8ae5d172-805f-4acb-ad30-1dc5507c637e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365234238 -assert nopostproc +UVM_TESTNAME= rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.365234238 |
Directory | /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3956093021 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 93821775 ps |
CPU time | 2.25 seconds |
Started | Jul 17 05:24:44 PM PDT 24 |
Finished | Jul 17 05:24:49 PM PDT 24 |
Peak memory | 213560 kb |
Host | smart-07b265ef-406a-4a3f-98d3-0a1e0334e079 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956093021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3956093021 |
Directory | /workspace/7.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.797653863 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 2473594824 ps |
CPU time | 1.74 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:24:51 PM PDT 24 |
Peak memory | 205340 kb |
Host | smart-689c85f5-0621-4a2f-a8a1-b2b2a0b2c33b |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797653863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ= rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.r v_dm_jtag_dmi_csr_bit_bash.797653863 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.746455046 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 1615978310 ps |
CPU time | 2.79 seconds |
Started | Jul 17 05:25:45 PM PDT 24 |
Finished | Jul 17 05:25:49 PM PDT 24 |
Peak memory | 205500 kb |
Host | smart-8aa66e1b-f052-44d4-8ee7-6ba120485184 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746455046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.746455046 |
Directory | /workspace/7.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1519595206 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 232496242 ps |
CPU time | 1.01 seconds |
Started | Jul 17 05:24:45 PM PDT 24 |
Finished | Jul 17 05:24:49 PM PDT 24 |
Peak memory | 205060 kb |
Host | smart-2f40a641-24d1-4288-b5f2-74ba2b70e67d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519595206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1 519595206 |
Directory | /workspace/7.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3217327623 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 604560260 ps |
CPU time | 6.5 seconds |
Started | Jul 17 05:24:43 PM PDT 24 |
Finished | Jul 17 05:24:52 PM PDT 24 |
Peak memory | 205428 kb |
Host | smart-5480f945-9c06-4eb6-b5e7-4ffa67abf1e1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217327623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_ csr_outstanding.3217327623 |
Directory | /workspace/7.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1809196738 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 25239010385 ps |
CPU time | 71.64 seconds |
Started | Jul 17 05:24:45 PM PDT 24 |
Finished | Jul 17 05:25:59 PM PDT 24 |
Peak memory | 221816 kb |
Host | smart-38ee45f7-f485-4e77-b76f-73e2829e3d87 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809196738 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1809196738 |
Directory | /workspace/7.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.636836910 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 2204663335 ps |
CPU time | 5.91 seconds |
Started | Jul 17 05:24:45 PM PDT 24 |
Finished | Jul 17 05:24:54 PM PDT 24 |
Peak memory | 213748 kb |
Host | smart-c99a0fb0-53ed-4cc2-a31f-dedc80edc291 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636836910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.636836910 |
Directory | /workspace/7.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.3899608812 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 3166837113 ps |
CPU time | 11.15 seconds |
Started | Jul 17 05:24:45 PM PDT 24 |
Finished | Jul 17 05:24:59 PM PDT 24 |
Peak memory | 221940 kb |
Host | smart-a9b0a6d1-b994-4c34-9c78-b3a3d759f411 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899608812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.3899608812 |
Directory | /workspace/7.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1437627435 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 4227714571 ps |
CPU time | 9.97 seconds |
Started | Jul 17 05:24:43 PM PDT 24 |
Finished | Jul 17 05:24:54 PM PDT 24 |
Peak memory | 221848 kb |
Host | smart-c206f2d5-0d19-4a80-ad41-b57d6efd0261 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437627435 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1437627435 |
Directory | /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2253341707 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 482940330 ps |
CPU time | 2.47 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:24:51 PM PDT 24 |
Peak memory | 213640 kb |
Host | smart-a1ea1518-15b7-4ced-9bcc-f6b1854f9e3b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253341707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2253341707 |
Directory | /workspace/8.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1514283124 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 59761544871 ps |
CPU time | 97.95 seconds |
Started | Jul 17 05:24:45 PM PDT 24 |
Finished | Jul 17 05:26:27 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-84ffb587-5f07-46ec-94cd-3a8a35bbc0f3 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514283124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8. rv_dm_jtag_dmi_csr_bit_bash.1514283124 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1241635579 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 6942276202 ps |
CPU time | 7.23 seconds |
Started | Jul 17 05:25:43 PM PDT 24 |
Finished | Jul 17 05:25:51 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-a76e622b-b050-4745-a475-8ab052165d39 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241635579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1 241635579 |
Directory | /workspace/8.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2065002364 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 271761022 ps |
CPU time | 0.81 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:24:50 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-603102d2-2b35-4607-b3a7-2b7090d303c4 |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065002364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2 065002364 |
Directory | /workspace/8.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2623778402 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 405193851 ps |
CPU time | 6.54 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:25:59 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-fedd24f3-93a7-44c8-a50e-81e35ff8ab9c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623778402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_ csr_outstanding.2623778402 |
Directory | /workspace/8.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.788027478 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 48392603142 ps |
CPU time | 267.92 seconds |
Started | Jul 17 05:24:51 PM PDT 24 |
Finished | Jul 17 05:29:21 PM PDT 24 |
Peak memory | 221948 kb |
Host | smart-65e6ed06-c54f-40f9-a977-9973dd8b008e |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788027478 -assert nopostproc +UVM_TESTNAM E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.788027478 |
Directory | /workspace/8.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1340182267 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 289708456 ps |
CPU time | 5.26 seconds |
Started | Jul 17 05:24:45 PM PDT 24 |
Finished | Jul 17 05:24:54 PM PDT 24 |
Peak memory | 213708 kb |
Host | smart-c936b853-d348-4f24-bcd4-fbc2d9532f64 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340182267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1340182267 |
Directory | /workspace/8.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2606999031 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 4023294174 ps |
CPU time | 23.95 seconds |
Started | Jul 17 05:24:51 PM PDT 24 |
Finished | Jul 17 05:25:17 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-e9f8ad00-6ccf-4810-8869-0317acb64ddc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606999031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2606999031 |
Directory | /workspace/8.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2988248389 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 228914552 ps |
CPU time | 2.36 seconds |
Started | Jul 17 05:24:47 PM PDT 24 |
Finished | Jul 17 05:24:53 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-39558f92-c6ab-41ce-82b6-facb5dcee4fa |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988248389 -assert nopostproc +UVM_TESTNAME =rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2988248389 |
Directory | /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3755919546 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 293956943 ps |
CPU time | 2.17 seconds |
Started | Jul 17 05:24:42 PM PDT 24 |
Finished | Jul 17 05:24:45 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-ee2e009c-4a76-4a4e-8691-1b9442bdb0cb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755919546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3755919546 |
Directory | /workspace/9.rv_dm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3562370781 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 85739459319 ps |
CPU time | 215.67 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:28:26 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-2ed6dada-afd5-4d31-9780-61fa8baa2c8e |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562370781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ =rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9. rv_dm_jtag_dmi_csr_bit_bash.3562370781 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.567405342 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 2705250158 ps |
CPU time | 4.11 seconds |
Started | Jul 17 05:27:19 PM PDT 24 |
Finished | Jul 17 05:27:25 PM PDT 24 |
Peak memory | 205288 kb |
Host | smart-a344d0aa-077a-486f-9a70-4f2a7517753d |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567405342 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.567405342 |
Directory | /workspace/9.rv_dm_jtag_dmi_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.225863381 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 1170221113 ps |
CPU time | 1.25 seconds |
Started | Jul 17 05:24:43 PM PDT 24 |
Finished | Jul 17 05:24:46 PM PDT 24 |
Peak memory | 205072 kb |
Host | smart-039183b9-8fe5-4f4b-a998-70e7ce2200cd |
User | root |
Command | /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225863381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.225863381 |
Directory | /workspace/9.rv_dm_jtag_dtm_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2727864402 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 552045599 ps |
CPU time | 8.16 seconds |
Started | Jul 17 05:24:43 PM PDT 24 |
Finished | Jul 17 05:24:54 PM PDT 24 |
Peak memory | 205512 kb |
Host | smart-09245ebc-f03f-4d69-8761-5dd10e063792 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727864402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_ csr_outstanding.2727864402 |
Directory | /workspace/9.rv_dm_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3321572496 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 42186287536 ps |
CPU time | 65.46 seconds |
Started | Jul 17 05:24:46 PM PDT 24 |
Finished | Jul 17 05:25:55 PM PDT 24 |
Peak memory | 221920 kb |
Host | smart-64273cdb-1ed1-492f-8674-3de2c3607717 |
User | root |
Command | /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321572496 -assert nopostproc +UVM_TESTNA ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3321572496 |
Directory | /workspace/9.rv_dm_tap_fsm_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.335095267 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 466158583 ps |
CPU time | 5.51 seconds |
Started | Jul 17 05:27:20 PM PDT 24 |
Finished | Jul 17 05:27:27 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-829308e3-91c0-448c-8978-527ff2a45cf3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335095267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.335095267 |
Directory | /workspace/9.rv_dm_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.739780171 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 1946069302 ps |
CPU time | 10.29 seconds |
Started | Jul 17 05:24:45 PM PDT 24 |
Finished | Jul 17 05:24:58 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-2183e383-7668-4460-9935-5325de05f105 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739780171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.739780171 |
Directory | /workspace/9.rv_dm_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_dm_alert_test.603063759 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 26315204 ps |
CPU time | 0.73 seconds |
Started | Jul 17 05:27:04 PM PDT 24 |
Finished | Jul 17 05:27:05 PM PDT 24 |
Peak memory | 204892 kb |
Host | smart-4357722e-fdc1-4728-b5e9-b86a8c69f679 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603063759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.603063759 |
Directory | /workspace/0.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2404761808 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 6652060073 ps |
CPU time | 4.24 seconds |
Started | Jul 17 05:27:02 PM PDT 24 |
Finished | Jul 17 05:27:07 PM PDT 24 |
Peak memory | 213628 kb |
Host | smart-79702666-3f5a-48b6-ac78-bd2da2dc36fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2404761808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2404761808 |
Directory | /workspace/0.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.347327859 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 2128677722 ps |
CPU time | 6.27 seconds |
Started | Jul 17 05:25:08 PM PDT 24 |
Finished | Jul 17 05:25:17 PM PDT 24 |
Peak memory | 214508 kb |
Host | smart-b9bb199e-9a26-43ab-beeb-003524ae79c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=347327859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.347327859 |
Directory | /workspace/0.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_busy.1838401367 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 471808820 ps |
CPU time | 1.12 seconds |
Started | Jul 17 05:27:01 PM PDT 24 |
Finished | Jul 17 05:27:03 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-1151765a-62e4-4890-b5e3-7407f9f8bc24 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1838401367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1838401367 |
Directory | /workspace/0.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_exception.1476081532 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 1177941838 ps |
CPU time | 3.62 seconds |
Started | Jul 17 05:25:08 PM PDT 24 |
Finished | Jul 17 05:25:14 PM PDT 24 |
Peak memory | 204852 kb |
Host | smart-e1cdabf3-485a-4a2f-9c0f-c253ddcdecfd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1476081532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.1476081532 |
Directory | /workspace/0.rv_dm_cmderr_exception/latest |
Test location | /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1491665294 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 110207385 ps |
CPU time | 0.95 seconds |
Started | Jul 17 05:26:56 PM PDT 24 |
Finished | Jul 17 05:26:59 PM PDT 24 |
Peak memory | 204880 kb |
Host | smart-ebc10d1c-1733-4c9e-a6c4-f973cc462ee4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1491665294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1491665294 |
Directory | /workspace/0.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1218511537 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 347881451 ps |
CPU time | 1.6 seconds |
Started | Jul 17 05:24:57 PM PDT 24 |
Finished | Jul 17 05:25:00 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-c901d277-31fd-41cd-9bb7-fdad4148fb32 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1218511537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1218511537 |
Directory | /workspace/0.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_debug_disabled.39333942 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 43818293 ps |
CPU time | 0.93 seconds |
Started | Jul 17 05:24:57 PM PDT 24 |
Finished | Jul 17 05:24:59 PM PDT 24 |
Peak memory | 215428 kb |
Host | smart-f665aceb-5b4b-48db-ab7c-66c944939f16 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39333942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.39333942 |
Directory | /workspace/0.rv_dm_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3783581875 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 1989607071 ps |
CPU time | 2.7 seconds |
Started | Jul 17 05:26:56 PM PDT 24 |
Finished | Jul 17 05:27:01 PM PDT 24 |
Peak memory | 205240 kb |
Host | smart-594bd7f7-b402-4621-872c-743414cd278d |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3783581875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t l_access.3783581875 |
Directory | /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3724780097 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 1292776073 ps |
CPU time | 4.05 seconds |
Started | Jul 17 05:26:53 PM PDT 24 |
Finished | Jul 17 05:27:02 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-05317852-f304-4b93-a3b5-896ef956d56c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3724780097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3724780097 |
Directory | /workspace/0.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/0.rv_dm_hart_unavail.1945004843 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 142628866 ps |
CPU time | 1.12 seconds |
Started | Jul 17 05:26:53 PM PDT 24 |
Finished | Jul 17 05:26:59 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-d90139e3-a290-4fa0-80ea-a64fd6d48b4d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945004843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1945004843 |
Directory | /workspace/0.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1743028627 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 784984117 ps |
CPU time | 1.36 seconds |
Started | Jul 17 05:25:10 PM PDT 24 |
Finished | Jul 17 05:25:15 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-d3b0eba2-c3c7-450d-808b-0b258fe38408 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1743028627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1743028627 |
Directory | /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3984638853 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 516756648 ps |
CPU time | 1.01 seconds |
Started | Jul 17 05:27:00 PM PDT 24 |
Finished | Jul 17 05:27:02 PM PDT 24 |
Peak memory | 204844 kb |
Host | smart-c44753fa-cf56-4e6d-92f9-3a9505d0693c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3984638853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3984638853 |
Directory | /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1607522333 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 572084147 ps |
CPU time | 2.33 seconds |
Started | Jul 17 05:25:10 PM PDT 24 |
Finished | Jul 17 05:25:15 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-dc933ed3-fe75-4a52-a886-0c8b1846c9e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1607522333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1607522333 |
Directory | /workspace/0.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1195699228 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 206763303 ps |
CPU time | 1.22 seconds |
Started | Jul 17 05:24:59 PM PDT 24 |
Finished | Jul 17 05:25:02 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-482c3f2e-461b-4fd9-a4d5-e2a82535488c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1195699228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1195699228 |
Directory | /workspace/0.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1807623747 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 477185823 ps |
CPU time | 1.09 seconds |
Started | Jul 17 05:26:49 PM PDT 24 |
Finished | Jul 17 05:26:56 PM PDT 24 |
Peak memory | 204960 kb |
Host | smart-b1a88083-1d4f-4111-8d25-5e23316924a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1807623747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1807623747 |
Directory | /workspace/0.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.976255252 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 1960195482 ps |
CPU time | 2.6 seconds |
Started | Jul 17 05:25:04 PM PDT 24 |
Finished | Jul 17 05:25:08 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-f77d2d86-f6f9-43cd-b09a-6d0efb940f9e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=976255252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.976255252 |
Directory | /workspace/0.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/0.rv_dm_ndmreset_req.1307303731 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 213068120 ps |
CPU time | 1.3 seconds |
Started | Jul 17 05:26:51 PM PDT 24 |
Finished | Jul 17 05:26:58 PM PDT 24 |
Peak memory | 213228 kb |
Host | smart-a45c7bce-3fcd-408d-9af7-a82bbdba4afb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1307303731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1307303731 |
Directory | /workspace/0.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/0.rv_dm_sba_tl_access.2349722951 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 690004899 ps |
CPU time | 2.94 seconds |
Started | Jul 17 05:26:52 PM PDT 24 |
Finished | Jul 17 05:27:00 PM PDT 24 |
Peak memory | 205232 kb |
Host | smart-420a84fe-ce11-4d18-9736-639ea01e4061 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349722951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2349722951 |
Directory | /workspace/0.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/0.rv_dm_sec_cm.3826129641 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 1086227499 ps |
CPU time | 1.98 seconds |
Started | Jul 17 05:25:05 PM PDT 24 |
Finished | Jul 17 05:25:08 PM PDT 24 |
Peak memory | 229380 kb |
Host | smart-25971b57-01aa-4595-8046-1f7740ee5e97 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826129641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3826129641 |
Directory | /workspace/0.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/0.rv_dm_smoke.3204926934 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 802737372 ps |
CPU time | 1.87 seconds |
Started | Jul 17 05:24:59 PM PDT 24 |
Finished | Jul 17 05:25:02 PM PDT 24 |
Peak memory | 205192 kb |
Host | smart-c5153f89-6317-4b86-8ff5-7a27ace3f612 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3204926934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3204926934 |
Directory | /workspace/0.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/0.rv_dm_tap_fsm.3160355818 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 5606294183 ps |
CPU time | 5.52 seconds |
Started | Jul 17 05:25:05 PM PDT 24 |
Finished | Jul 17 05:25:12 PM PDT 24 |
Peak memory | 205368 kb |
Host | smart-fd35740f-a28d-43b7-8b7b-50061941e234 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3160355818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3160355818 |
Directory | /workspace/0.rv_dm_tap_fsm/latest |
Test location | /workspace/coverage/default/1.rv_dm_abstractcmd_status.4141695501 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 631627141 ps |
CPU time | 1.16 seconds |
Started | Jul 17 05:25:10 PM PDT 24 |
Finished | Jul 17 05:25:14 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-d2f4010e-118b-4b24-8faa-cbdeb7c86a25 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4141695501 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.4141695501 |
Directory | /workspace/1.rv_dm_abstractcmd_status/latest |
Test location | /workspace/coverage/default/1.rv_dm_alert_test.1057765230 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 34576655 ps |
CPU time | 0.74 seconds |
Started | Jul 17 05:25:20 PM PDT 24 |
Finished | Jul 17 05:25:21 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-13acb9c5-6227-4629-bc12-f9cc37d527cc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057765230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1057765230 |
Directory | /workspace/1.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.644369649 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 2763027438 ps |
CPU time | 1.82 seconds |
Started | Jul 17 05:25:08 PM PDT 24 |
Finished | Jul 17 05:25:13 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-e86fbb93-f451-4adc-8c9b-61afebc87d8e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=644369649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.644369649 |
Directory | /workspace/1.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_busy.1736847373 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 541963940 ps |
CPU time | 1.52 seconds |
Started | Jul 17 05:25:08 PM PDT 24 |
Finished | Jul 17 05:25:11 PM PDT 24 |
Peak memory | 204932 kb |
Host | smart-67975272-7909-41c8-9cb3-acc3cf5adaad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1736847373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1736847373 |
Directory | /workspace/1.rv_dm_cmderr_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1453400764 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 620592667 ps |
CPU time | 1.17 seconds |
Started | Jul 17 05:25:07 PM PDT 24 |
Finished | Jul 17 05:25:10 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-6c743f54-b75a-4eab-8be5-a453edf95a17 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1453400764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1453400764 |
Directory | /workspace/1.rv_dm_cmderr_halt_resume/latest |
Test location | /workspace/coverage/default/1.rv_dm_cmderr_not_supported.2278841145 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 320532600 ps |
CPU time | 1.02 seconds |
Started | Jul 17 05:27:01 PM PDT 24 |
Finished | Jul 17 05:27:03 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-a3000964-08db-41c6-9f0e-44dbebbbf34e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2278841145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.2278841145 |
Directory | /workspace/1.rv_dm_cmderr_not_supported/latest |
Test location | /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3074525332 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 202179275 ps |
CPU time | 0.79 seconds |
Started | Jul 17 05:24:56 PM PDT 24 |
Finished | Jul 17 05:24:58 PM PDT 24 |
Peak memory | 205008 kb |
Host | smart-ec4d13ae-59af-40e6-b7a6-ae4cd55a31e0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074525332 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3074525332 |
Directory | /workspace/1.rv_dm_dataaddr_rw_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.276689328 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 10220623068 ps |
CPU time | 15.56 seconds |
Started | Jul 17 05:25:10 PM PDT 24 |
Finished | Jul 17 05:25:29 PM PDT 24 |
Peak memory | 213612 kb |
Host | smart-f177041e-8759-40b6-923c-abf318ac20d4 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=276689328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_tl _access.276689328 |
Directory | /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_dmi_failed_op.1757593026 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 219416145 ps |
CPU time | 0.99 seconds |
Started | Jul 17 05:25:15 PM PDT 24 |
Finished | Jul 17 05:25:18 PM PDT 24 |
Peak memory | 205188 kb |
Host | smart-f7dd9131-effa-48d3-93ab-b36c8eb18800 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1757593026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.1757593026 |
Directory | /workspace/1.rv_dm_dmi_failed_op/latest |
Test location | /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3280780200 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 1576991723 ps |
CPU time | 3.27 seconds |
Started | Jul 17 05:25:08 PM PDT 24 |
Finished | Jul 17 05:25:13 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-18edd460-806e-4dee-bf8b-bc3cf4dddb02 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280780200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3280780200 |
Directory | /workspace/1.rv_dm_halt_resume_whereto/latest |
Test location | /workspace/coverage/default/1.rv_dm_hart_unavail.1222052232 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 251907108 ps |
CPU time | 0.78 seconds |
Started | Jul 17 05:25:07 PM PDT 24 |
Finished | Jul 17 05:25:09 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-7ee0cf43-727a-47b3-a0d1-1de79e15c837 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222052232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1222052232 |
Directory | /workspace/1.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3970462900 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 201755584 ps |
CPU time | 1.23 seconds |
Started | Jul 17 05:25:02 PM PDT 24 |
Finished | Jul 17 05:25:04 PM PDT 24 |
Peak memory | 204936 kb |
Host | smart-472a5e82-4561-43ee-b36f-5b830debb39f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970462900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3970462900 |
Directory | /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.712660157 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 410737603 ps |
CPU time | 1.21 seconds |
Started | Jul 17 05:25:07 PM PDT 24 |
Finished | Jul 17 05:25:11 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-dbb7cd18-ba3a-4cda-afaa-ab6744da001e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712660157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.712660157 |
Directory | /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3107855278 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 1052368312 ps |
CPU time | 1.81 seconds |
Started | Jul 17 05:27:03 PM PDT 24 |
Finished | Jul 17 05:27:05 PM PDT 24 |
Peak memory | 205204 kb |
Host | smart-d0f64653-a2d4-4cb2-9c97-abb423c4d5e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3107855278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3107855278 |
Directory | /workspace/1.rv_dm_jtag_dtm_hard_reset/latest |
Test location | /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1841520982 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 95003019 ps |
CPU time | 0.93 seconds |
Started | Jul 17 05:25:03 PM PDT 24 |
Finished | Jul 17 05:25:05 PM PDT 24 |
Peak memory | 205016 kb |
Host | smart-97452e11-9e18-41b4-b021-f56ba092ca66 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1841520982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1841520982 |
Directory | /workspace/1.rv_dm_jtag_dtm_idle_hint/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3470828141 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 462242551 ps |
CPU time | 1.83 seconds |
Started | Jul 17 05:25:07 PM PDT 24 |
Finished | Jul 17 05:25:09 PM PDT 24 |
Peak memory | 205012 kb |
Host | smart-ae36d1b4-859a-4f96-8182-56a1d77f7b83 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470828141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3470828141 |
Directory | /workspace/1.rv_dm_mem_tl_access_halted/latest |
Test location | /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3822003 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 407764089 ps |
CPU time | 1.03 seconds |
Started | Jul 17 05:26:48 PM PDT 24 |
Finished | Jul 17 05:26:54 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-c13981a9-2d74-4377-8285-4d057915705e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3822003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3822003 |
Directory | /workspace/1.rv_dm_mem_tl_access_resuming/latest |
Test location | /workspace/coverage/default/1.rv_dm_ndmreset_req.2811224540 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 342422429 ps |
CPU time | 1.08 seconds |
Started | Jul 17 05:25:01 PM PDT 24 |
Finished | Jul 17 05:25:03 PM PDT 24 |
Peak memory | 213192 kb |
Host | smart-4764f812-80af-410e-b7cf-ebec5e32aad7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2811224540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2811224540 |
Directory | /workspace/1.rv_dm_ndmreset_req/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_busy.4241844910 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 2973107180 ps |
CPU time | 4.56 seconds |
Started | Jul 17 05:25:11 PM PDT 24 |
Finished | Jul 17 05:25:19 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-08bb47d1-4075-47a8-84ff-94d35de8002c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241844910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.4241844910 |
Directory | /workspace/1.rv_dm_progbuf_busy/latest |
Test location | /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3656523252 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 301744197 ps |
CPU time | 0.95 seconds |
Started | Jul 17 05:25:11 PM PDT 24 |
Finished | Jul 17 05:25:15 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-e19b1721-425d-4e78-951c-3ef7d45295f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3656523252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3656523252 |
Directory | /workspace/1.rv_dm_progbuf_read_write_execute/latest |
Test location | /workspace/coverage/default/1.rv_dm_rom_read_access.541025165 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 216809795 ps |
CPU time | 0.82 seconds |
Started | Jul 17 05:25:11 PM PDT 24 |
Finished | Jul 17 05:25:15 PM PDT 24 |
Peak memory | 213492 kb |
Host | smart-23316353-ba9a-49ae-8fcc-7c0e8d3cbb34 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=541025165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.541025165 |
Directory | /workspace/1.rv_dm_rom_read_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3817928895 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 2048881832 ps |
CPU time | 2.04 seconds |
Started | Jul 17 05:25:02 PM PDT 24 |
Finished | Jul 17 05:25:05 PM PDT 24 |
Peak memory | 205248 kb |
Host | smart-ab36aa85-fedd-4223-a767-47dda4c24a3e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817928895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3817928895 |
Directory | /workspace/1.rv_dm_sba_debug_disabled/latest |
Test location | /workspace/coverage/default/1.rv_dm_sba_tl_access.313286152 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 3885589989 ps |
CPU time | 5.68 seconds |
Started | Jul 17 05:26:50 PM PDT 24 |
Finished | Jul 17 05:27:01 PM PDT 24 |
Peak memory | 205220 kb |
Host | smart-eccacf29-66b6-4f42-a2db-3c2f5f77d180 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313286152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.313286152 |
Directory | /workspace/1.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/1.rv_dm_smoke.1799772020 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 382425859 ps |
CPU time | 1.07 seconds |
Started | Jul 17 05:26:49 PM PDT 24 |
Finished | Jul 17 05:26:55 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-d3b088ea-7daf-4035-835d-9e629c95b2d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1799772020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1799772020 |
Directory | /workspace/1.rv_dm_smoke/latest |
Test location | /workspace/coverage/default/10.rv_dm_alert_test.309708933 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 32147937 ps |
CPU time | 0.81 seconds |
Started | Jul 17 05:25:24 PM PDT 24 |
Finished | Jul 17 05:25:26 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-6f37450f-508d-4611-b04f-32cefeaafa8c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309708933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.309708933 |
Directory | /workspace/10.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3671911082 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 7968905669 ps |
CPU time | 23.65 seconds |
Started | Jul 17 05:25:23 PM PDT 24 |
Finished | Jul 17 05:25:48 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-32301bd5-17bc-4d02-898b-54d80041a20b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3671911082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3671911082 |
Directory | /workspace/10.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2366569783 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 4225217573 ps |
CPU time | 12.46 seconds |
Started | Jul 17 05:30:40 PM PDT 24 |
Finished | Jul 17 05:30:54 PM PDT 24 |
Peak memory | 214068 kb |
Host | smart-8d3acfad-2a68-46b1-832d-479d554f4831 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2366569783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2366569783 |
Directory | /workspace/10.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.4076758542 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 5522505063 ps |
CPU time | 15.42 seconds |
Started | Jul 17 05:26:25 PM PDT 24 |
Finished | Jul 17 05:26:41 PM PDT 24 |
Peak memory | 213664 kb |
Host | smart-e0e949a0-e8c8-49cc-9c03-d7d6b08eb929 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4076758542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_ tl_access.4076758542 |
Directory | /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/10.rv_dm_sba_tl_access.1013836414 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 3052840518 ps |
CPU time | 6.27 seconds |
Started | Jul 17 05:25:24 PM PDT 24 |
Finished | Jul 17 05:25:31 PM PDT 24 |
Peak memory | 205344 kb |
Host | smart-09682dae-0771-4c30-8ef8-b86f76a58600 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1013836414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1013836414 |
Directory | /workspace/10.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_alert_test.705429222 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 158172244 ps |
CPU time | 0.7 seconds |
Started | Jul 17 05:25:26 PM PDT 24 |
Finished | Jul 17 05:25:27 PM PDT 24 |
Peak memory | 204976 kb |
Host | smart-b83efaf9-a85c-4e8c-9c77-1cb7cac14509 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705429222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.705429222 |
Directory | /workspace/11.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3538551959 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 7057769739 ps |
CPU time | 20.76 seconds |
Started | Jul 17 05:30:38 PM PDT 24 |
Finished | Jul 17 05:31:00 PM PDT 24 |
Peak memory | 213660 kb |
Host | smart-ae56dde8-46f4-415b-bb31-a77aba8d4b44 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3538551959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3538551959 |
Directory | /workspace/11.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2077599780 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 1653724770 ps |
CPU time | 5.21 seconds |
Started | Jul 17 05:25:28 PM PDT 24 |
Finished | Jul 17 05:25:34 PM PDT 24 |
Peak memory | 205308 kb |
Host | smart-7851069c-1cd6-43bf-97d3-15c9e9cd5e2e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2077599780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2077599780 |
Directory | /workspace/11.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3283766068 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 5656699606 ps |
CPU time | 4.23 seconds |
Started | Jul 17 05:25:29 PM PDT 24 |
Finished | Jul 17 05:25:34 PM PDT 24 |
Peak memory | 213736 kb |
Host | smart-7b30e0a1-b51c-4a42-9ab1-13686b70329e |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3283766068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_ tl_access.3283766068 |
Directory | /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_sba_tl_access.2487393297 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 3290652907 ps |
CPU time | 2.81 seconds |
Started | Jul 17 05:25:22 PM PDT 24 |
Finished | Jul 17 05:25:26 PM PDT 24 |
Peak memory | 213660 kb |
Host | smart-1378f7fa-876c-4057-bdda-9663bd7f2079 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487393297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2487393297 |
Directory | /workspace/11.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/11.rv_dm_stress_all.3577774882 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 12189568531 ps |
CPU time | 27.26 seconds |
Started | Jul 17 05:25:22 PM PDT 24 |
Finished | Jul 17 05:25:51 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-bb306750-4ab8-49d4-95a5-fe19ec3816fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577774882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3577774882 |
Directory | /workspace/11.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/12.rv_dm_alert_test.603638839 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 65433744 ps |
CPU time | 0.78 seconds |
Started | Jul 17 05:25:21 PM PDT 24 |
Finished | Jul 17 05:25:23 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-c5283803-4a4e-43f4-9e9d-a92376d0b536 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603638839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.603638839 |
Directory | /workspace/12.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.4143943519 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 49772139235 ps |
CPU time | 148.92 seconds |
Started | Jul 17 05:25:59 PM PDT 24 |
Finished | Jul 17 05:28:29 PM PDT 24 |
Peak memory | 214044 kb |
Host | smart-d3babb83-1e5d-41f9-a23b-fc967f9491ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4143943519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.4143943519 |
Directory | /workspace/12.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3365528054 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 7534263673 ps |
CPU time | 9.1 seconds |
Started | Jul 17 05:25:20 PM PDT 24 |
Finished | Jul 17 05:25:31 PM PDT 24 |
Peak memory | 205524 kb |
Host | smart-d74d9d6f-6e84-4896-aca0-24dcd8cb02cf |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3365528054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_ tl_access.3365528054 |
Directory | /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/12.rv_dm_sba_tl_access.1930861764 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 2219655667 ps |
CPU time | 3.14 seconds |
Started | Jul 17 05:26:49 PM PDT 24 |
Finished | Jul 17 05:26:58 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-54fca24a-4e01-4cb1-806a-228e9318c4eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1930861764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1930861764 |
Directory | /workspace/12.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_alert_test.1648632468 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 72926612 ps |
CPU time | 0.83 seconds |
Started | Jul 17 05:25:21 PM PDT 24 |
Finished | Jul 17 05:25:23 PM PDT 24 |
Peak memory | 204876 kb |
Host | smart-9de73888-1b06-4d25-8f2b-e711427c0257 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648632468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1648632468 |
Directory | /workspace/13.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2335393350 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 7454750302 ps |
CPU time | 7.28 seconds |
Started | Jul 17 05:27:14 PM PDT 24 |
Finished | Jul 17 05:27:21 PM PDT 24 |
Peak memory | 205376 kb |
Host | smart-cae287db-6a68-46db-954d-f4db7812a900 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335393350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2335393350 |
Directory | /workspace/13.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1974355296 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 2527466215 ps |
CPU time | 4.55 seconds |
Started | Jul 17 05:25:20 PM PDT 24 |
Finished | Jul 17 05:25:26 PM PDT 24 |
Peak memory | 213668 kb |
Host | smart-d932365a-2e4e-4309-9864-e68e9a198f1d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1974355296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1974355296 |
Directory | /workspace/13.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2322361049 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 4701038073 ps |
CPU time | 4.22 seconds |
Started | Jul 17 05:25:21 PM PDT 24 |
Finished | Jul 17 05:25:27 PM PDT 24 |
Peak memory | 213680 kb |
Host | smart-5a8a1c96-be5d-4c90-bbab-7e36e5e96cf2 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2322361049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_ tl_access.2322361049 |
Directory | /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_sba_tl_access.3817473300 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 3649856824 ps |
CPU time | 7.77 seconds |
Started | Jul 17 05:25:24 PM PDT 24 |
Finished | Jul 17 05:25:33 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-21f705ea-9829-4f8a-acc3-fab0ae8982ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817473300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3817473300 |
Directory | /workspace/13.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/13.rv_dm_stress_all.2658723274 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 6252244725 ps |
CPU time | 7.45 seconds |
Started | Jul 17 05:25:43 PM PDT 24 |
Finished | Jul 17 05:25:51 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-245f7cc8-96dd-47af-9c96-99c7be221aae |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658723274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.2658723274 |
Directory | /workspace/13.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_dm_alert_test.1929586311 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 86816459 ps |
CPU time | 0.77 seconds |
Started | Jul 17 05:25:23 PM PDT 24 |
Finished | Jul 17 05:25:25 PM PDT 24 |
Peak memory | 204988 kb |
Host | smart-025103c7-e16a-4674-b899-d6b129b876bb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929586311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1929586311 |
Directory | /workspace/14.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1476309918 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 7862640755 ps |
CPU time | 6.55 seconds |
Started | Jul 17 05:25:23 PM PDT 24 |
Finished | Jul 17 05:25:30 PM PDT 24 |
Peak memory | 213688 kb |
Host | smart-d439e4f1-354e-4271-ab21-201539bf603e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1476309918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1476309918 |
Directory | /workspace/14.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2220190042 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 3071314255 ps |
CPU time | 7.65 seconds |
Started | Jul 17 05:25:27 PM PDT 24 |
Finished | Jul 17 05:25:35 PM PDT 24 |
Peak memory | 205396 kb |
Host | smart-e509599b-beff-4e51-bb8e-9b041b5f3a35 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2220190042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_ tl_access.2220190042 |
Directory | /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/14.rv_dm_sba_tl_access.2882516853 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 1249193176 ps |
CPU time | 2.34 seconds |
Started | Jul 17 05:25:26 PM PDT 24 |
Finished | Jul 17 05:25:29 PM PDT 24 |
Peak memory | 213620 kb |
Host | smart-7b3c11f8-eb49-4bba-89b7-445b90ebfb8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2882516853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2882516853 |
Directory | /workspace/14.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_alert_test.3770233523 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 45383870 ps |
CPU time | 0.85 seconds |
Started | Jul 17 05:25:24 PM PDT 24 |
Finished | Jul 17 05:25:26 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-72f262b9-f7fb-4d8e-9c09-0dbcd3aa27c2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770233523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3770233523 |
Directory | /workspace/15.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2720436587 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 12830958788 ps |
CPU time | 35.61 seconds |
Started | Jul 17 05:28:42 PM PDT 24 |
Finished | Jul 17 05:29:18 PM PDT 24 |
Peak memory | 221800 kb |
Host | smart-7ed0b98e-66b8-431b-88eb-4bb9b4dbf494 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2720436587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2720436587 |
Directory | /workspace/15.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.373486633 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 13089676067 ps |
CPU time | 19.24 seconds |
Started | Jul 17 05:25:21 PM PDT 24 |
Finished | Jul 17 05:25:41 PM PDT 24 |
Peak memory | 215940 kb |
Host | smart-cccbd792-0195-4696-b79d-df82073a3890 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373486633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.373486633 |
Directory | /workspace/15.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1218795630 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 1938217684 ps |
CPU time | 6.59 seconds |
Started | Jul 17 05:25:24 PM PDT 24 |
Finished | Jul 17 05:25:32 PM PDT 24 |
Peak memory | 213532 kb |
Host | smart-c8ddd53c-14b1-45f3-8f93-b73ec74dfbe7 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1218795630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_ tl_access.1218795630 |
Directory | /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/15.rv_dm_sba_tl_access.1969901283 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 3382502114 ps |
CPU time | 5.28 seconds |
Started | Jul 17 05:26:53 PM PDT 24 |
Finished | Jul 17 05:27:03 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-7a43a148-9e9e-45de-8a94-78f8a7f311b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969901283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1969901283 |
Directory | /workspace/15.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_alert_test.2267199249 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 95501292 ps |
CPU time | 0.81 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:25:53 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-059952d2-8d47-4d77-af6a-16fdb16aa6d3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267199249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2267199249 |
Directory | /workspace/16.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.2777934674 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 5090063015 ps |
CPU time | 7.01 seconds |
Started | Jul 17 05:25:46 PM PDT 24 |
Finished | Jul 17 05:25:54 PM PDT 24 |
Peak memory | 213712 kb |
Host | smart-3afab645-102b-4383-a669-f74aa0a5e7dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777934674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.2777934674 |
Directory | /workspace/16.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2816432281 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 1039591563 ps |
CPU time | 3.38 seconds |
Started | Jul 17 05:25:46 PM PDT 24 |
Finished | Jul 17 05:25:51 PM PDT 24 |
Peak memory | 205392 kb |
Host | smart-0a718dc8-58e2-4dc2-9f1e-f650283ded15 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816432281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2816432281 |
Directory | /workspace/16.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.229963189 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 5876333193 ps |
CPU time | 4.45 seconds |
Started | Jul 17 05:25:48 PM PDT 24 |
Finished | Jul 17 05:25:54 PM PDT 24 |
Peak memory | 213728 kb |
Host | smart-5dacb4e7-5880-4412-b522-512e6fb5bad5 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=229963189 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t l_access.229963189 |
Directory | /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_sba_tl_access.1142108811 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 1604858721 ps |
CPU time | 5.97 seconds |
Started | Jul 17 05:27:18 PM PDT 24 |
Finished | Jul 17 05:27:25 PM PDT 24 |
Peak memory | 205348 kb |
Host | smart-c08d785a-76cc-4771-b02b-4754368fc64a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142108811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1142108811 |
Directory | /workspace/16.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/16.rv_dm_stress_all.3279179557 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 3496234043 ps |
CPU time | 3.37 seconds |
Started | Jul 17 05:26:20 PM PDT 24 |
Finished | Jul 17 05:26:24 PM PDT 24 |
Peak memory | 213408 kb |
Host | smart-bb1281a9-1c4a-4135-afc4-e61fc6623aa9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279179557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3279179557 |
Directory | /workspace/16.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/17.rv_dm_alert_test.2026431239 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 95898173 ps |
CPU time | 0.76 seconds |
Started | Jul 17 05:30:32 PM PDT 24 |
Finished | Jul 17 05:30:34 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-4fefcb5d-9269-4960-ac74-f38848d4ee02 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026431239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2026431239 |
Directory | /workspace/17.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.224876918 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 26563589539 ps |
CPU time | 64.46 seconds |
Started | Jul 17 05:25:46 PM PDT 24 |
Finished | Jul 17 05:26:51 PM PDT 24 |
Peak memory | 213676 kb |
Host | smart-e42466a4-d7c1-4e71-ab1b-5e97a7076d87 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=224876918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.224876918 |
Directory | /workspace/17.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.4070029054 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 10234350857 ps |
CPU time | 14.79 seconds |
Started | Jul 17 05:25:47 PM PDT 24 |
Finished | Jul 17 05:26:03 PM PDT 24 |
Peak memory | 205528 kb |
Host | smart-961643a7-1e1a-4463-9328-d35377dae73f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070029054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.4070029054 |
Directory | /workspace/17.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.325969398 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 922513492 ps |
CPU time | 1.5 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:25:53 PM PDT 24 |
Peak memory | 205280 kb |
Host | smart-f51eb3ca-0137-4531-a88a-04ea5fd6e070 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=325969398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t l_access.325969398 |
Directory | /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/17.rv_dm_sba_tl_access.1494056726 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 8576708022 ps |
CPU time | 12.24 seconds |
Started | Jul 17 05:25:48 PM PDT 24 |
Finished | Jul 17 05:26:01 PM PDT 24 |
Peak memory | 205476 kb |
Host | smart-7889ea44-6979-43a2-bcd9-d5f30322f41e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1494056726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1494056726 |
Directory | /workspace/17.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_alert_test.1371385018 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 67163500 ps |
CPU time | 0.77 seconds |
Started | Jul 17 05:26:25 PM PDT 24 |
Finished | Jul 17 05:26:27 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-5216ac08-9005-494e-a367-3c4a36e9f98b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371385018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1371385018 |
Directory | /workspace/18.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3392006104 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 23699191071 ps |
CPU time | 22.7 seconds |
Started | Jul 17 05:25:48 PM PDT 24 |
Finished | Jul 17 05:26:12 PM PDT 24 |
Peak memory | 213632 kb |
Host | smart-0560a954-6ef4-44e0-939d-dc364e4d1eec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3392006104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3392006104 |
Directory | /workspace/18.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.659709389 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 4133922373 ps |
CPU time | 2.17 seconds |
Started | Jul 17 05:25:46 PM PDT 24 |
Finished | Jul 17 05:25:50 PM PDT 24 |
Peak memory | 205596 kb |
Host | smart-620ee320-f5a6-4166-bfb2-b2cde1166591 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=659709389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.659709389 |
Directory | /workspace/18.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2025737622 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 8078363219 ps |
CPU time | 12.32 seconds |
Started | Jul 17 05:25:49 PM PDT 24 |
Finished | Jul 17 05:26:02 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-06aa1bb7-30b3-4613-bbbd-d46eb2e7a512 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2025737622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_ tl_access.2025737622 |
Directory | /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/18.rv_dm_sba_tl_access.2712059158 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 2945071549 ps |
CPU time | 2.96 seconds |
Started | Jul 17 05:25:47 PM PDT 24 |
Finished | Jul 17 05:25:51 PM PDT 24 |
Peak memory | 213648 kb |
Host | smart-cfcf0200-6502-4b58-af73-66b1ee055395 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2712059158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2712059158 |
Directory | /workspace/18.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_alert_test.425541341 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 65670068 ps |
CPU time | 0.81 seconds |
Started | Jul 17 05:25:48 PM PDT 24 |
Finished | Jul 17 05:25:49 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-561a519e-c3af-45d2-9c66-fc00cd0bb85f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425541341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.425541341 |
Directory | /workspace/19.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1047257541 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 5023453322 ps |
CPU time | 8.34 seconds |
Started | Jul 17 05:28:49 PM PDT 24 |
Finished | Jul 17 05:28:58 PM PDT 24 |
Peak memory | 213596 kb |
Host | smart-5a201d8d-2810-4b16-b36c-d35d7b1a217b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1047257541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1047257541 |
Directory | /workspace/19.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.65529376 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 1172032233 ps |
CPU time | 1.83 seconds |
Started | Jul 17 05:26:53 PM PDT 24 |
Finished | Jul 17 05:27:00 PM PDT 24 |
Peak memory | 213600 kb |
Host | smart-18ed43a5-cd16-4038-afc0-bf05d0ecce1c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=65529376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.65529376 |
Directory | /workspace/19.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1104101772 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 5492937392 ps |
CPU time | 4.39 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:25:56 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-4790ee2b-9d27-49ca-a09c-5b623bb38859 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1104101772 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_ tl_access.1104101772 |
Directory | /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/19.rv_dm_sba_tl_access.4229442236 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 2387973851 ps |
CPU time | 4.23 seconds |
Started | Jul 17 05:25:46 PM PDT 24 |
Finished | Jul 17 05:25:51 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-e8fd4955-a88c-4144-a56b-c2918aada6e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4229442236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.4229442236 |
Directory | /workspace/19.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_alert_test.4109235215 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 28942314 ps |
CPU time | 0.73 seconds |
Started | Jul 17 05:25:18 PM PDT 24 |
Finished | Jul 17 05:25:20 PM PDT 24 |
Peak memory | 205048 kb |
Host | smart-5d592bee-0db4-4f98-8c11-28e51acdff2f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109235215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.4109235215 |
Directory | /workspace/2.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3439896014 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 3226729643 ps |
CPU time | 4.47 seconds |
Started | Jul 17 05:25:09 PM PDT 24 |
Finished | Jul 17 05:25:16 PM PDT 24 |
Peak memory | 205480 kb |
Host | smart-0878202d-725d-422b-b4eb-c1dce283bf0a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3439896014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3439896014 |
Directory | /workspace/2.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3232878072 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 3586658184 ps |
CPU time | 9.13 seconds |
Started | Jul 17 05:25:15 PM PDT 24 |
Finished | Jul 17 05:25:26 PM PDT 24 |
Peak memory | 205704 kb |
Host | smart-1c4b9379-b614-4523-95bb-c8133982121f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3232878072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3232878072 |
Directory | /workspace/2.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2713882808 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 566405361 ps |
CPU time | 1.51 seconds |
Started | Jul 17 05:27:03 PM PDT 24 |
Finished | Jul 17 05:27:06 PM PDT 24 |
Peak memory | 205120 kb |
Host | smart-39579da0-b890-41a4-947e-b65c03d5c666 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2713882808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t l_access.2713882808 |
Directory | /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_hart_unavail.3700025609 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 586805578 ps |
CPU time | 1.01 seconds |
Started | Jul 17 05:25:11 PM PDT 24 |
Finished | Jul 17 05:25:15 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-5a92550a-745b-43fb-8a7f-af6c1b29d826 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3700025609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3700025609 |
Directory | /workspace/2.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/2.rv_dm_sba_tl_access.2056935846 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 1831878008 ps |
CPU time | 2.78 seconds |
Started | Jul 17 05:29:00 PM PDT 24 |
Finished | Jul 17 05:29:04 PM PDT 24 |
Peak memory | 213512 kb |
Host | smart-b335f4b4-3ddf-4c5f-bafd-ee5e12c54ccb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056935846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2056935846 |
Directory | /workspace/2.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/2.rv_dm_sec_cm.1260064749 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 862275702 ps |
CPU time | 2.04 seconds |
Started | Jul 17 05:26:26 PM PDT 24 |
Finished | Jul 17 05:26:29 PM PDT 24 |
Peak memory | 228736 kb |
Host | smart-bb4d2ec9-becc-4465-88c9-2c0fe5e0c57f |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260064749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1260064749 |
Directory | /workspace/2.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/2.rv_dm_stress_all.1943994427 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 7508751622 ps |
CPU time | 19.77 seconds |
Started | Jul 17 05:27:18 PM PDT 24 |
Finished | Jul 17 05:27:39 PM PDT 24 |
Peak memory | 205312 kb |
Host | smart-d5b69faf-6f20-43da-b0c8-7159e73646ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943994427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1943994427 |
Directory | /workspace/2.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/20.rv_dm_alert_test.4069632584 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 162396600 ps |
CPU time | 0.76 seconds |
Started | Jul 17 05:25:49 PM PDT 24 |
Finished | Jul 17 05:25:51 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-f59b4841-a632-46ca-996a-da20f3d499a5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069632584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.4069632584 |
Directory | /workspace/20.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/20.rv_dm_stress_all.2669329205 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 5848913872 ps |
CPU time | 4.13 seconds |
Started | Jul 17 05:27:11 PM PDT 24 |
Finished | Jul 17 05:27:16 PM PDT 24 |
Peak memory | 213428 kb |
Host | smart-bdc21f51-cc1f-451e-866a-056669e83351 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669329205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2669329205 |
Directory | /workspace/20.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/21.rv_dm_alert_test.1528806331 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 76808740 ps |
CPU time | 0.71 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:25:53 PM PDT 24 |
Peak memory | 204956 kb |
Host | smart-811ae7b8-d1ce-45e3-bc76-01e9d84aa28f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528806331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1528806331 |
Directory | /workspace/21.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/22.rv_dm_alert_test.769790467 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 89847233 ps |
CPU time | 0.86 seconds |
Started | Jul 17 05:25:46 PM PDT 24 |
Finished | Jul 17 05:25:47 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-bec01306-2030-49ab-b85b-3ce13ba2a3fc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769790467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.769790467 |
Directory | /workspace/22.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_alert_test.2467764991 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 62201739 ps |
CPU time | 0.7 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:25:53 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-fb2e940b-2418-458f-940b-bac52f558266 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467764991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2467764991 |
Directory | /workspace/23.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/23.rv_dm_stress_all.3730913080 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 11325877542 ps |
CPU time | 7.98 seconds |
Started | Jul 17 05:25:51 PM PDT 24 |
Finished | Jul 17 05:26:00 PM PDT 24 |
Peak memory | 205364 kb |
Host | smart-e74b697d-9b85-4f16-9ed7-7cee3a528154 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730913080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3730913080 |
Directory | /workspace/23.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_dm_alert_test.1293167120 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 31092340 ps |
CPU time | 0.81 seconds |
Started | Jul 17 05:27:01 PM PDT 24 |
Finished | Jul 17 05:27:03 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-daf3e77b-48c5-46e8-92d5-c07f5c865c14 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293167120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.1293167120 |
Directory | /workspace/24.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_alert_test.2173142091 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 157280506 ps |
CPU time | 0.85 seconds |
Started | Jul 17 05:25:46 PM PDT 24 |
Finished | Jul 17 05:25:48 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-eaf07028-29d9-4582-9f85-51c38f71e74c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173142091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2173142091 |
Directory | /workspace/25.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/25.rv_dm_stress_all.3856313612 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 10322177971 ps |
CPU time | 31.49 seconds |
Started | Jul 17 05:25:47 PM PDT 24 |
Finished | Jul 17 05:26:19 PM PDT 24 |
Peak memory | 213556 kb |
Host | smart-20fcc738-ffbb-4ba0-a57e-fd2ac5555eac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856313612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.3856313612 |
Directory | /workspace/25.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/26.rv_dm_alert_test.1095658408 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 129804471 ps |
CPU time | 0.82 seconds |
Started | Jul 17 05:25:47 PM PDT 24 |
Finished | Jul 17 05:25:49 PM PDT 24 |
Peak memory | 204968 kb |
Host | smart-748fbd28-246b-4fee-8b59-1798a0cdec9e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095658408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1095658408 |
Directory | /workspace/26.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/27.rv_dm_alert_test.3445496574 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 226840095 ps |
CPU time | 0.7 seconds |
Started | Jul 17 05:25:58 PM PDT 24 |
Finished | Jul 17 05:26:00 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-b7fece51-4e60-4037-81aa-665aa2396517 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445496574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3445496574 |
Directory | /workspace/27.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_alert_test.3896583468 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 28264900 ps |
CPU time | 0.73 seconds |
Started | Jul 17 05:25:48 PM PDT 24 |
Finished | Jul 17 05:25:50 PM PDT 24 |
Peak memory | 205212 kb |
Host | smart-1b1bee21-15a4-454c-b0b9-74f7864a4ce1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896583468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3896583468 |
Directory | /workspace/28.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/28.rv_dm_stress_all.2739521537 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 8354706533 ps |
CPU time | 5.7 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:25:57 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-619b821d-c264-4535-b222-081bd2ccddc1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739521537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.2739521537 |
Directory | /workspace/28.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_dm_alert_test.2721002716 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 97119050 ps |
CPU time | 0.68 seconds |
Started | Jul 17 05:25:49 PM PDT 24 |
Finished | Jul 17 05:25:51 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-dcc00db4-43a4-4f9a-94aa-6f61ce05ed4a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721002716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2721002716 |
Directory | /workspace/29.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/29.rv_dm_stress_all.409462520 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 7175895600 ps |
CPU time | 7.23 seconds |
Started | Jul 17 05:25:47 PM PDT 24 |
Finished | Jul 17 05:25:55 PM PDT 24 |
Peak memory | 213584 kb |
Host | smart-71362a28-d4ba-4f78-a0d8-b87e99feccc2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409462520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.409462520 |
Directory | /workspace/29.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/3.rv_dm_alert_test.1636174921 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 160470663 ps |
CPU time | 1.08 seconds |
Started | Jul 17 05:25:09 PM PDT 24 |
Finished | Jul 17 05:25:13 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-efc48e37-47d4-48e9-ad05-e7811272db1d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636174921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1636174921 |
Directory | /workspace/3.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3660323601 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 2207713788 ps |
CPU time | 2.45 seconds |
Started | Jul 17 05:25:15 PM PDT 24 |
Finished | Jul 17 05:25:20 PM PDT 24 |
Peak memory | 214244 kb |
Host | smart-d1c52e29-0d41-40e9-bb1a-c8b35ecf316e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660323601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3660323601 |
Directory | /workspace/3.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.284802775 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 5274559088 ps |
CPU time | 13.76 seconds |
Started | Jul 17 05:25:10 PM PDT 24 |
Finished | Jul 17 05:25:27 PM PDT 24 |
Peak memory | 213728 kb |
Host | smart-a9a94da7-7d55-45c4-b435-5e318e784d3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=284802775 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.284802775 |
Directory | /workspace/3.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1528763465 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 1944393954 ps |
CPU time | 3.51 seconds |
Started | Jul 17 05:25:10 PM PDT 24 |
Finished | Jul 17 05:25:16 PM PDT 24 |
Peak memory | 205388 kb |
Host | smart-a6299d78-4f40-4194-a044-834e2fecfcc9 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1528763465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t l_access.1528763465 |
Directory | /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_hart_unavail.2297130652 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 255284144 ps |
CPU time | 1.1 seconds |
Started | Jul 17 05:25:10 PM PDT 24 |
Finished | Jul 17 05:25:14 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-7982f30b-d56d-4a43-b6c1-49344fce6ce3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2297130652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2297130652 |
Directory | /workspace/3.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/3.rv_dm_sba_tl_access.3089134364 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 8398954674 ps |
CPU time | 7.56 seconds |
Started | Jul 17 05:25:09 PM PDT 24 |
Finished | Jul 17 05:25:20 PM PDT 24 |
Peak memory | 213740 kb |
Host | smart-860a619d-0a94-47e2-909b-09d8d44bd6eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3089134364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3089134364 |
Directory | /workspace/3.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/3.rv_dm_sec_cm.2382373098 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 1597656084 ps |
CPU time | 5.32 seconds |
Started | Jul 17 05:26:26 PM PDT 24 |
Finished | Jul 17 05:26:32 PM PDT 24 |
Peak memory | 229404 kb |
Host | smart-904c9075-1b41-4c25-a374-4b7ab6c6866d |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382373098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2382373098 |
Directory | /workspace/3.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/30.rv_dm_alert_test.1384673397 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 87310946 ps |
CPU time | 0.74 seconds |
Started | Jul 17 05:25:49 PM PDT 24 |
Finished | Jul 17 05:25:50 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-84e415fd-4005-4531-9f87-55e6ce1059ee |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384673397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1384673397 |
Directory | /workspace/30.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/30.rv_dm_stress_all.996222484 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 9722119230 ps |
CPU time | 4.21 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:25:56 PM PDT 24 |
Peak memory | 213524 kb |
Host | smart-ed9c2cdd-9bb0-4dc3-a36a-f633e4c6d798 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996222484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.996222484 |
Directory | /workspace/30.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/31.rv_dm_alert_test.1775527064 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 126050394 ps |
CPU time | 0.71 seconds |
Started | Jul 17 05:25:51 PM PDT 24 |
Finished | Jul 17 05:25:54 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-c25cd521-460a-40a6-96ac-aa2fea9a55c2 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775527064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1775527064 |
Directory | /workspace/31.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/31.rv_dm_stress_all.4201162092 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 7634502342 ps |
CPU time | 17.72 seconds |
Started | Jul 17 05:27:09 PM PDT 24 |
Finished | Jul 17 05:27:27 PM PDT 24 |
Peak memory | 213460 kb |
Host | smart-712d484b-4cc0-4f71-96cc-8cf50162bc95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201162092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.4201162092 |
Directory | /workspace/31.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/32.rv_dm_alert_test.802540909 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 99319936 ps |
CPU time | 0.84 seconds |
Started | Jul 17 05:25:51 PM PDT 24 |
Finished | Jul 17 05:25:54 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-c32fb7aa-0e9e-484f-8fb3-15738b8505bc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802540909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.802540909 |
Directory | /workspace/32.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/32.rv_dm_stress_all.1687815686 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 6908636167 ps |
CPU time | 9.36 seconds |
Started | Jul 17 05:27:21 PM PDT 24 |
Finished | Jul 17 05:27:31 PM PDT 24 |
Peak memory | 205416 kb |
Host | smart-85854899-dc16-4953-8b77-303dd77a9dca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687815686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1687815686 |
Directory | /workspace/32.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/33.rv_dm_alert_test.346876392 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 93078801 ps |
CPU time | 0.92 seconds |
Started | Jul 17 05:26:54 PM PDT 24 |
Finished | Jul 17 05:26:59 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-ffae47c2-1216-40de-be88-8c4fbb43e33d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346876392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.346876392 |
Directory | /workspace/33.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/34.rv_dm_alert_test.3058926636 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 205970620 ps |
CPU time | 0.9 seconds |
Started | Jul 17 05:28:47 PM PDT 24 |
Finished | Jul 17 05:28:48 PM PDT 24 |
Peak memory | 204964 kb |
Host | smart-463ad664-9fd8-440e-868c-c43d40a40670 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058926636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3058926636 |
Directory | /workspace/34.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/35.rv_dm_alert_test.1189516608 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 106234485 ps |
CPU time | 0.72 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:25:52 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-c417aa44-1281-4b43-a2eb-2a45383db072 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189516608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1189516608 |
Directory | /workspace/35.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/36.rv_dm_alert_test.2421550624 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 35057530 ps |
CPU time | 0.7 seconds |
Started | Jul 17 05:25:51 PM PDT 24 |
Finished | Jul 17 05:25:53 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-c581fa58-5a58-422a-9247-074662182cb5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421550624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.2421550624 |
Directory | /workspace/36.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_alert_test.622326876 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 66705855 ps |
CPU time | 0.73 seconds |
Started | Jul 17 05:25:49 PM PDT 24 |
Finished | Jul 17 05:25:50 PM PDT 24 |
Peak memory | 205004 kb |
Host | smart-93e55f33-2c9b-4057-945a-e74df172bd93 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622326876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.622326876 |
Directory | /workspace/37.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/37.rv_dm_stress_all.4187603809 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 9292558015 ps |
CPU time | 7.6 seconds |
Started | Jul 17 05:25:50 PM PDT 24 |
Finished | Jul 17 05:25:59 PM PDT 24 |
Peak memory | 205296 kb |
Host | smart-b37d37da-5c05-4c7f-9889-bee23ca284fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187603809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.4187603809 |
Directory | /workspace/37.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/38.rv_dm_alert_test.3743490740 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 34393380 ps |
CPU time | 0.78 seconds |
Started | Jul 17 05:28:37 PM PDT 24 |
Finished | Jul 17 05:28:38 PM PDT 24 |
Peak memory | 204972 kb |
Host | smart-3e6a4321-b5ea-4868-8533-38d80c188d7d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743490740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3743490740 |
Directory | /workspace/38.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/39.rv_dm_stress_all.334903636 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 2934786787 ps |
CPU time | 6.08 seconds |
Started | Jul 17 05:25:51 PM PDT 24 |
Finished | Jul 17 05:25:59 PM PDT 24 |
Peak memory | 205520 kb |
Host | smart-190be54d-0b83-49c5-9e9f-f5ceebf63ba4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334903636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.334903636 |
Directory | /workspace/39.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_dm_alert_test.3436926628 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 121815586 ps |
CPU time | 0.68 seconds |
Started | Jul 17 05:25:17 PM PDT 24 |
Finished | Jul 17 05:25:19 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-66fed1eb-caa6-45f9-bd40-49fce449d1fb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436926628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3436926628 |
Directory | /workspace/4.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3800487917 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 16185384990 ps |
CPU time | 15.63 seconds |
Started | Jul 17 05:25:10 PM PDT 24 |
Finished | Jul 17 05:25:29 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-611ea838-7469-49f5-bda1-7c0e7715bdfd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3800487917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3800487917 |
Directory | /workspace/4.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2122832116 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 3319028572 ps |
CPU time | 10.27 seconds |
Started | Jul 17 05:25:15 PM PDT 24 |
Finished | Jul 17 05:25:27 PM PDT 24 |
Peak memory | 213568 kb |
Host | smart-c38ce76b-ce1b-4874-9e04-45fee1ce850a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2122832116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2122832116 |
Directory | /workspace/4.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1658150856 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 6997542482 ps |
CPU time | 20.09 seconds |
Started | Jul 17 05:28:05 PM PDT 24 |
Finished | Jul 17 05:28:28 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-2aee2e71-ffc7-4899-92c6-da7784a0c273 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1658150856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t l_access.1658150856 |
Directory | /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_hart_unavail.3450604912 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 79533546 ps |
CPU time | 0.7 seconds |
Started | Jul 17 05:25:15 PM PDT 24 |
Finished | Jul 17 05:25:18 PM PDT 24 |
Peak memory | 205180 kb |
Host | smart-19ddd44e-ce56-4599-8347-4be4c251037f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3450604912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3450604912 |
Directory | /workspace/4.rv_dm_hart_unavail/latest |
Test location | /workspace/coverage/default/4.rv_dm_sba_tl_access.2438020568 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 2167640264 ps |
CPU time | 2.98 seconds |
Started | Jul 17 05:25:17 PM PDT 24 |
Finished | Jul 17 05:25:21 PM PDT 24 |
Peak memory | 205416 kb |
Host | smart-dfeb4f58-a682-448e-a9d6-360e298c99d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2438020568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2438020568 |
Directory | /workspace/4.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/4.rv_dm_sec_cm.2745849445 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 760623590 ps |
CPU time | 1.88 seconds |
Started | Jul 17 05:26:26 PM PDT 24 |
Finished | Jul 17 05:26:29 PM PDT 24 |
Peak memory | 229708 kb |
Host | smart-14cc9bec-2cd1-4c2a-b018-e6da0a5b9fd5 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745849445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2745849445 |
Directory | /workspace/4.rv_dm_sec_cm/latest |
Test location | /workspace/coverage/default/40.rv_dm_alert_test.2034706873 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 52932954 ps |
CPU time | 0.71 seconds |
Started | Jul 17 05:25:51 PM PDT 24 |
Finished | Jul 17 05:25:53 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-c4c509ad-e5aa-4de3-a248-4aaafcf6d133 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034706873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2034706873 |
Directory | /workspace/40.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/40.rv_dm_stress_all.1991198086 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 2411164354 ps |
CPU time | 7.85 seconds |
Started | Jul 17 05:27:17 PM PDT 24 |
Finished | Jul 17 05:27:26 PM PDT 24 |
Peak memory | 205260 kb |
Host | smart-4e9927ce-78c7-44b6-bcf5-dd024c7e6194 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991198086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1991198086 |
Directory | /workspace/40.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/41.rv_dm_alert_test.3587315539 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 80343928 ps |
CPU time | 0.87 seconds |
Started | Jul 17 05:25:51 PM PDT 24 |
Finished | Jul 17 05:25:54 PM PDT 24 |
Peak memory | 205228 kb |
Host | smart-d1978a8f-1d53-41be-9f4c-9a89ab67ce29 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587315539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3587315539 |
Directory | /workspace/41.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/41.rv_dm_stress_all.892528513 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 12106928712 ps |
CPU time | 6.85 seconds |
Started | Jul 17 05:27:17 PM PDT 24 |
Finished | Jul 17 05:27:25 PM PDT 24 |
Peak memory | 213576 kb |
Host | smart-cd8c3bbf-3732-4a12-914d-759c3dca7355 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892528513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.892528513 |
Directory | /workspace/41.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/42.rv_dm_alert_test.3735911212 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 45077856 ps |
CPU time | 0.75 seconds |
Started | Jul 17 05:26:46 PM PDT 24 |
Finished | Jul 17 05:26:49 PM PDT 24 |
Peak memory | 205000 kb |
Host | smart-04cab723-7b13-41b2-ae2c-6d37ce08ec54 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735911212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3735911212 |
Directory | /workspace/42.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/43.rv_dm_alert_test.2744341755 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 88547037 ps |
CPU time | 0.9 seconds |
Started | Jul 17 05:29:44 PM PDT 24 |
Finished | Jul 17 05:29:46 PM PDT 24 |
Peak memory | 204948 kb |
Host | smart-d8dda5fb-e4ba-4898-b944-d703b6b495ab |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744341755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2744341755 |
Directory | /workspace/43.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/44.rv_dm_alert_test.2500253521 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 69369964 ps |
CPU time | 0.74 seconds |
Started | Jul 17 05:26:44 PM PDT 24 |
Finished | Jul 17 05:26:46 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-91291fa8-8d36-4c2d-bc28-63a0b84744b9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500253521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2500253521 |
Directory | /workspace/44.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/45.rv_dm_alert_test.2690907050 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 30366709 ps |
CPU time | 0.75 seconds |
Started | Jul 17 05:27:13 PM PDT 24 |
Finished | Jul 17 05:27:15 PM PDT 24 |
Peak memory | 204984 kb |
Host | smart-e67b74b4-2333-46b2-a5a7-1925452cd1e5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690907050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2690907050 |
Directory | /workspace/45.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_alert_test.3316212160 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 216372399 ps |
CPU time | 0.98 seconds |
Started | Jul 17 05:26:42 PM PDT 24 |
Finished | Jul 17 05:26:44 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-cf9b8859-d9a9-49db-bbbd-f1751c148b16 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316212160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3316212160 |
Directory | /workspace/46.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/46.rv_dm_stress_all.793171184 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 4163295777 ps |
CPU time | 4.29 seconds |
Started | Jul 17 05:26:45 PM PDT 24 |
Finished | Jul 17 05:26:51 PM PDT 24 |
Peak memory | 205264 kb |
Host | smart-469af06e-cf61-4923-b66d-1bc76997d105 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793171184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.793171184 |
Directory | /workspace/46.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/47.rv_dm_alert_test.1020808064 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 62840775 ps |
CPU time | 0.83 seconds |
Started | Jul 17 05:26:44 PM PDT 24 |
Finished | Jul 17 05:26:47 PM PDT 24 |
Peak memory | 205024 kb |
Host | smart-830f9f91-9da0-4241-8740-db5599b3b5bc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020808064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1020808064 |
Directory | /workspace/47.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/47.rv_dm_stress_all.2776205851 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 3640976612 ps |
CPU time | 11.04 seconds |
Started | Jul 17 05:26:46 PM PDT 24 |
Finished | Jul 17 05:26:59 PM PDT 24 |
Peak memory | 213504 kb |
Host | smart-efd54c7e-5e52-4221-a80a-f10d2cd8034a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776205851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.2776205851 |
Directory | /workspace/47.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_dm_alert_test.3376363036 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 124340675 ps |
CPU time | 0.75 seconds |
Started | Jul 17 05:26:42 PM PDT 24 |
Finished | Jul 17 05:26:43 PM PDT 24 |
Peak memory | 205032 kb |
Host | smart-65b21248-29bc-4a0e-9b25-dab905fe7237 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376363036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3376363036 |
Directory | /workspace/48.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/48.rv_dm_stress_all.2805672120 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 5750990333 ps |
CPU time | 9.07 seconds |
Started | Jul 17 05:26:49 PM PDT 24 |
Finished | Jul 17 05:27:04 PM PDT 24 |
Peak memory | 205444 kb |
Host | smart-535d7ffa-9cb1-41a7-b26e-57fcaa89e792 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805672120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2805672120 |
Directory | /workspace/48.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/49.rv_dm_alert_test.529672954 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 135837950 ps |
CPU time | 0.82 seconds |
Started | Jul 17 05:27:17 PM PDT 24 |
Finished | Jul 17 05:27:19 PM PDT 24 |
Peak memory | 205020 kb |
Host | smart-e1cd3d35-202f-40b1-87be-9bd115a943b0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529672954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.529672954 |
Directory | /workspace/49.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/49.rv_dm_stress_all.2124571994 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 2196967438 ps |
CPU time | 3.5 seconds |
Started | Jul 17 05:26:43 PM PDT 24 |
Finished | Jul 17 05:26:48 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-2bd2c3cc-d437-4adc-ad10-49cc1effdaf0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124571994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2124571994 |
Directory | /workspace/49.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_dm_alert_test.1723846379 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 72871881 ps |
CPU time | 0.74 seconds |
Started | Jul 17 05:25:19 PM PDT 24 |
Finished | Jul 17 05:25:21 PM PDT 24 |
Peak memory | 204996 kb |
Host | smart-9b33b246-da81-4d87-ac0d-36928afa979a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723846379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1723846379 |
Directory | /workspace/5.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.47723443 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 10826077152 ps |
CPU time | 33.01 seconds |
Started | Jul 17 05:25:10 PM PDT 24 |
Finished | Jul 17 05:25:47 PM PDT 24 |
Peak memory | 213688 kb |
Host | smart-d706df1d-2f06-4e40-a889-2ae00d48b1c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47723443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.47723443 |
Directory | /workspace/5.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3624262402 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 1507041510 ps |
CPU time | 4.98 seconds |
Started | Jul 17 05:26:52 PM PDT 24 |
Finished | Jul 17 05:27:03 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-c2192adc-c0bc-4957-80db-29c9289c28b8 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3624262402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t l_access.3624262402 |
Directory | /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_sba_tl_access.471624117 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 9750745508 ps |
CPU time | 22.04 seconds |
Started | Jul 17 05:27:17 PM PDT 24 |
Finished | Jul 17 05:27:40 PM PDT 24 |
Peak memory | 205528 kb |
Host | smart-f0d6f10f-badd-45dd-bc50-c6b012aea486 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471624117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.471624117 |
Directory | /workspace/5.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/5.rv_dm_stress_all.2471144403 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 8278469514 ps |
CPU time | 9.31 seconds |
Started | Jul 17 05:25:12 PM PDT 24 |
Finished | Jul 17 05:25:24 PM PDT 24 |
Peak memory | 213464 kb |
Host | smart-469aec10-5f1c-47da-ac57-a722787d8d2f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471144403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.2471144403 |
Directory | /workspace/5.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_dm_alert_test.2158132828 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 147456933 ps |
CPU time | 0.73 seconds |
Started | Jul 17 05:25:14 PM PDT 24 |
Finished | Jul 17 05:25:17 PM PDT 24 |
Peak memory | 205040 kb |
Host | smart-c3320a7e-44c6-40f8-a449-775ffd2990d7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158132828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2158132828 |
Directory | /workspace/6.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2123085446 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 1903021550 ps |
CPU time | 6.42 seconds |
Started | Jul 17 05:25:12 PM PDT 24 |
Finished | Jul 17 05:25:21 PM PDT 24 |
Peak memory | 213552 kb |
Host | smart-6ffc4d94-d431-470b-97d1-59765eb9e5d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2123085446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2123085446 |
Directory | /workspace/6.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2488776966 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 4078898704 ps |
CPU time | 3.94 seconds |
Started | Jul 17 05:25:09 PM PDT 24 |
Finished | Jul 17 05:25:15 PM PDT 24 |
Peak memory | 205352 kb |
Host | smart-62af4e7c-0dc8-4441-afe0-920c87b88408 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2488776966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t l_access.2488776966 |
Directory | /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_sba_tl_access.2796565108 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 8555442002 ps |
CPU time | 5.78 seconds |
Started | Jul 17 05:25:11 PM PDT 24 |
Finished | Jul 17 05:25:20 PM PDT 24 |
Peak memory | 213624 kb |
Host | smart-771c47c4-82ea-4c89-9f7b-4a441a1cff28 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2796565108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2796565108 |
Directory | /workspace/6.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/6.rv_dm_stress_all.1537470800 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 4540573001 ps |
CPU time | 2.28 seconds |
Started | Jul 17 05:25:17 PM PDT 24 |
Finished | Jul 17 05:25:21 PM PDT 24 |
Peak memory | 205332 kb |
Host | smart-18a679b2-9b78-4523-9639-5f1ab91b8cc0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537470800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1537470800 |
Directory | /workspace/6.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_dm_alert_test.1567205479 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 108661436 ps |
CPU time | 0.72 seconds |
Started | Jul 17 05:25:18 PM PDT 24 |
Finished | Jul 17 05:25:19 PM PDT 24 |
Peak memory | 205044 kb |
Host | smart-37a5ed64-96ec-4938-ab6b-0b272f0f442e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567205479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1567205479 |
Directory | /workspace/7.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.4114567479 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 10479071392 ps |
CPU time | 31.96 seconds |
Started | Jul 17 05:25:19 PM PDT 24 |
Finished | Jul 17 05:25:52 PM PDT 24 |
Peak memory | 213656 kb |
Host | smart-93f6ce96-1972-4364-95d5-0baf1062e2f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4114567479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.4114567479 |
Directory | /workspace/7.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1385747670 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 1884639823 ps |
CPU time | 2.2 seconds |
Started | Jul 17 05:25:15 PM PDT 24 |
Finished | Jul 17 05:25:19 PM PDT 24 |
Peak memory | 213520 kb |
Host | smart-96676bbb-c202-4d5d-ba8e-f2cef2921c97 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385747670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1385747670 |
Directory | /workspace/7.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1186311776 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 1171825996 ps |
CPU time | 1.81 seconds |
Started | Jul 17 05:25:09 PM PDT 24 |
Finished | Jul 17 05:25:14 PM PDT 24 |
Peak memory | 205408 kb |
Host | smart-2a3fc27b-8551-4f4c-bd2c-860f9d9426b1 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1186311776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t l_access.1186311776 |
Directory | /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/7.rv_dm_sba_tl_access.4091367487 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 2823520213 ps |
CPU time | 4.49 seconds |
Started | Jul 17 05:25:12 PM PDT 24 |
Finished | Jul 17 05:25:19 PM PDT 24 |
Peak memory | 205360 kb |
Host | smart-8aee38e5-89b1-4caf-8774-8ab810d66450 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091367487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.4091367487 |
Directory | /workspace/7.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_alert_test.3293639062 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 156545019 ps |
CPU time | 0.75 seconds |
Started | Jul 17 05:25:45 PM PDT 24 |
Finished | Jul 17 05:25:46 PM PDT 24 |
Peak memory | 205272 kb |
Host | smart-ca08b375-3206-4b31-b846-8dff6b109e0f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293639062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3293639062 |
Directory | /workspace/8.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.4040213263 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 8972911349 ps |
CPU time | 7.99 seconds |
Started | Jul 17 05:25:20 PM PDT 24 |
Finished | Jul 17 05:25:29 PM PDT 24 |
Peak memory | 213732 kb |
Host | smart-cb4e60f1-1818-4f81-a90a-20449247ddf8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040213263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.4040213263 |
Directory | /workspace/8.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.423583647 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 2197844490 ps |
CPU time | 7.16 seconds |
Started | Jul 17 05:26:52 PM PDT 24 |
Finished | Jul 17 05:27:05 PM PDT 24 |
Peak memory | 213528 kb |
Host | smart-396114b7-0315-4e2c-8ae4-6519df2d976c |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=423583647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl _access.423583647 |
Directory | /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_sba_tl_access.208530955 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 13429997464 ps |
CPU time | 35.9 seconds |
Started | Jul 17 05:25:16 PM PDT 24 |
Finished | Jul 17 05:25:54 PM PDT 24 |
Peak memory | 213616 kb |
Host | smart-4ee9000a-677c-4f2e-abd7-96ecaae396c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208530955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.208530955 |
Directory | /workspace/8.rv_dm_sba_tl_access/latest |
Test location | /workspace/coverage/default/8.rv_dm_stress_all.2246336586 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 2448272986 ps |
CPU time | 3.93 seconds |
Started | Jul 17 05:25:30 PM PDT 24 |
Finished | Jul 17 05:25:35 PM PDT 24 |
Peak memory | 205252 kb |
Host | smart-ed41c8b9-c3ad-44ec-bd68-37c0a48532ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246336586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2246336586 |
Directory | /workspace/8.rv_dm_stress_all/latest |
Test location | /workspace/coverage/default/9.rv_dm_alert_test.17016852 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 55645541 ps |
CPU time | 0.81 seconds |
Started | Jul 17 05:25:24 PM PDT 24 |
Finished | Jul 17 05:25:26 PM PDT 24 |
Peak memory | 205028 kb |
Host | smart-dd9157b9-09dc-44e8-94ef-026aa21116a8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17016852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.17016852 |
Directory | /workspace/9.rv_dm_alert_test/latest |
Test location | /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.2442120655 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 1524650082 ps |
CPU time | 3.29 seconds |
Started | Jul 17 05:28:49 PM PDT 24 |
Finished | Jul 17 05:28:53 PM PDT 24 |
Peak memory | 205596 kb |
Host | smart-a3f25c98-a9d6-4062-ba51-32b756ad7407 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442120655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.2442120655 |
Directory | /workspace/9.rv_dm_autoincr_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.4056647750 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 4511765475 ps |
CPU time | 13.84 seconds |
Started | Jul 17 05:25:20 PM PDT 24 |
Finished | Jul 17 05:25:36 PM PDT 24 |
Peak memory | 213740 kb |
Host | smart-62d1d9e7-a614-40b2-90da-18c5a2922a64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4056647750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.4056647750 |
Directory | /workspace/9.rv_dm_bad_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3410111116 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 1636830048 ps |
CPU time | 5.16 seconds |
Started | Jul 17 05:25:23 PM PDT 24 |
Finished | Jul 17 05:25:29 PM PDT 24 |
Peak memory | 205328 kb |
Host | smart-47f6433d-3d78-4c2b-9e26-7c9b7e2d9f26 |
User | root |
Command | /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3410111116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t l_access.3410111116 |
Directory | /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest |
Test location | /workspace/coverage/default/9.rv_dm_sba_tl_access.72356809 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 2228633418 ps |
CPU time | 6.97 seconds |
Started | Jul 17 05:25:22 PM PDT 24 |
Finished | Jul 17 05:25:30 PM PDT 24 |
Peak memory | 205420 kb |
Host | smart-8a7d8bb4-2bda-459c-b2e3-4a027a0dc988 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72356809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.72356809 |
Directory | /workspace/9.rv_dm_sba_tl_access/latest |
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