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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.52 95.82 84.14 89.91 75.00 88.33 98.53 52.90


Total test records in report: 444
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T80 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.448025859 Jul 25 04:49:54 PM PDT 24 Jul 25 04:49:57 PM PDT 24 135989951 ps
T301 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1812469586 Jul 25 04:49:58 PM PDT 24 Jul 25 04:50:01 PM PDT 24 1344699533 ps
T81 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3239191401 Jul 25 04:49:28 PM PDT 24 Jul 25 04:49:30 PM PDT 24 115999894 ps
T302 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1167100954 Jul 25 04:50:06 PM PDT 24 Jul 25 04:50:27 PM PDT 24 15000169202 ps
T82 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3741747000 Jul 25 04:49:23 PM PDT 24 Jul 25 04:49:31 PM PDT 24 1705534011 ps
T91 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4069115632 Jul 25 04:49:27 PM PDT 24 Jul 25 04:49:58 PM PDT 24 3303488822 ps
T303 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3730741968 Jul 25 04:49:27 PM PDT 24 Jul 25 04:49:48 PM PDT 24 13992438439 ps
T83 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.685113660 Jul 25 04:49:39 PM PDT 24 Jul 25 04:49:46 PM PDT 24 1746852177 ps
T304 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2700571048 Jul 25 04:49:59 PM PDT 24 Jul 25 04:50:02 PM PDT 24 413673512 ps
T65 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3212017540 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:26 PM PDT 24 314519335 ps
T111 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.754938732 Jul 25 04:49:50 PM PDT 24 Jul 25 04:49:53 PM PDT 24 410415063 ps
T92 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2588295400 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:27 PM PDT 24 409583938 ps
T305 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.589153655 Jul 25 04:49:24 PM PDT 24 Jul 25 04:49:28 PM PDT 24 4637441818 ps
T306 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.881623456 Jul 25 04:49:27 PM PDT 24 Jul 25 04:49:29 PM PDT 24 124211394 ps
T307 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.501714594 Jul 25 04:49:42 PM PDT 24 Jul 25 04:49:50 PM PDT 24 2346996937 ps
T308 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3914133110 Jul 25 04:49:20 PM PDT 24 Jul 25 04:49:22 PM PDT 24 302561729 ps
T309 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2660806467 Jul 25 04:49:45 PM PDT 24 Jul 25 04:49:47 PM PDT 24 1262792266 ps
T93 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.88445146 Jul 25 04:49:39 PM PDT 24 Jul 25 04:49:41 PM PDT 24 118460199 ps
T310 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3420293827 Jul 25 04:49:49 PM PDT 24 Jul 25 04:49:50 PM PDT 24 203238374 ps
T120 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2577438984 Jul 25 04:49:41 PM PDT 24 Jul 25 04:49:50 PM PDT 24 1010557192 ps
T311 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1293846854 Jul 25 04:49:51 PM PDT 24 Jul 25 04:49:57 PM PDT 24 3658985483 ps
T94 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.48610986 Jul 25 04:49:49 PM PDT 24 Jul 25 04:49:57 PM PDT 24 2854578675 ps
T312 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.119619566 Jul 25 04:49:43 PM PDT 24 Jul 25 04:49:49 PM PDT 24 2590458627 ps
T95 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.906366821 Jul 25 04:50:04 PM PDT 24 Jul 25 04:50:06 PM PDT 24 951765608 ps
T313 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.707344195 Jul 25 04:49:21 PM PDT 24 Jul 25 04:50:04 PM PDT 24 16666160142 ps
T116 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.349262269 Jul 25 04:49:39 PM PDT 24 Jul 25 04:49:41 PM PDT 24 83226366 ps
T102 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3057308767 Jul 25 04:49:45 PM PDT 24 Jul 25 04:49:46 PM PDT 24 140472748 ps
T103 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3871771377 Jul 25 04:49:58 PM PDT 24 Jul 25 04:50:00 PM PDT 24 102051739 ps
T314 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.471643895 Jul 25 04:49:23 PM PDT 24 Jul 25 04:49:35 PM PDT 24 14660892334 ps
T315 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.521891345 Jul 25 04:49:39 PM PDT 24 Jul 25 04:49:47 PM PDT 24 7032114429 ps
T96 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3548240949 Jul 25 04:49:42 PM PDT 24 Jul 25 04:49:48 PM PDT 24 194371068 ps
T316 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.495650571 Jul 25 04:49:34 PM PDT 24 Jul 25 04:50:00 PM PDT 24 2209228753 ps
T97 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1262502177 Jul 25 04:49:22 PM PDT 24 Jul 25 04:50:41 PM PDT 24 36309101295 ps
T317 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1103146739 Jul 25 04:49:17 PM PDT 24 Jul 25 04:49:18 PM PDT 24 160254551 ps
T318 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.479915711 Jul 25 04:49:55 PM PDT 24 Jul 25 04:49:57 PM PDT 24 3327341183 ps
T105 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2563889034 Jul 25 04:49:27 PM PDT 24 Jul 25 04:49:55 PM PDT 24 1494980222 ps
T319 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.271436877 Jul 25 04:49:46 PM PDT 24 Jul 25 04:49:48 PM PDT 24 1337643549 ps
T106 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1529414442 Jul 25 04:49:23 PM PDT 24 Jul 25 04:49:26 PM PDT 24 232357568 ps
T320 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.483996514 Jul 25 04:49:24 PM PDT 24 Jul 25 04:49:26 PM PDT 24 679252296 ps
T107 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.4063703038 Jul 25 04:49:15 PM PDT 24 Jul 25 04:49:18 PM PDT 24 675551932 ps
T321 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.93834847 Jul 25 04:49:38 PM PDT 24 Jul 25 04:49:42 PM PDT 24 1022708343 ps
T121 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3530178967 Jul 25 04:49:47 PM PDT 24 Jul 25 04:50:05 PM PDT 24 1065917483 ps
T322 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.224522845 Jul 25 04:49:41 PM PDT 24 Jul 25 04:49:46 PM PDT 24 7051941155 ps
T112 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.962560397 Jul 25 04:49:12 PM PDT 24 Jul 25 04:49:20 PM PDT 24 1777919853 ps
T169 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2959720331 Jul 25 04:49:52 PM PDT 24 Jul 25 04:50:25 PM PDT 24 25733455517 ps
T159 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.254161074 Jul 25 04:50:04 PM PDT 24 Jul 25 04:50:21 PM PDT 24 5425222782 ps
T323 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1501149672 Jul 25 04:49:34 PM PDT 24 Jul 25 04:49:57 PM PDT 24 23853536871 ps
T98 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2750102756 Jul 25 04:49:27 PM PDT 24 Jul 25 04:49:29 PM PDT 24 132562967 ps
T324 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2240456883 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:27 PM PDT 24 232135711 ps
T325 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3086457535 Jul 25 04:49:57 PM PDT 24 Jul 25 04:50:02 PM PDT 24 305257948 ps
T326 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1420402747 Jul 25 04:49:28 PM PDT 24 Jul 25 04:49:33 PM PDT 24 505094027 ps
T86 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4048608526 Jul 25 04:49:24 PM PDT 24 Jul 25 04:49:48 PM PDT 24 8626324673 ps
T170 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2367365455 Jul 25 04:49:36 PM PDT 24 Jul 25 04:51:15 PM PDT 24 37598334529 ps
T113 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3017052155 Jul 25 04:49:49 PM PDT 24 Jul 25 04:49:54 PM PDT 24 1196156246 ps
T327 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.761103904 Jul 25 04:49:41 PM PDT 24 Jul 25 04:49:42 PM PDT 24 872331169 ps
T328 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3303901687 Jul 25 04:49:18 PM PDT 24 Jul 25 04:49:19 PM PDT 24 256060077 ps
T329 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3140940092 Jul 25 04:49:59 PM PDT 24 Jul 25 04:50:00 PM PDT 24 125317752 ps
T330 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2777343450 Jul 25 04:49:16 PM PDT 24 Jul 25 04:49:17 PM PDT 24 44352939 ps
T160 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2621265515 Jul 25 04:49:41 PM PDT 24 Jul 25 04:50:07 PM PDT 24 5669189196 ps
T108 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2069130108 Jul 25 04:49:20 PM PDT 24 Jul 25 04:50:45 PM PDT 24 57517238414 ps
T161 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3295950671 Jul 25 04:49:33 PM PDT 24 Jul 25 04:49:54 PM PDT 24 14106038753 ps
T331 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3160935587 Jul 25 04:49:38 PM PDT 24 Jul 25 04:49:56 PM PDT 24 5619975228 ps
T332 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1191745143 Jul 25 04:49:32 PM PDT 24 Jul 25 04:49:51 PM PDT 24 1867791026 ps
T114 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1780106962 Jul 25 04:49:23 PM PDT 24 Jul 25 04:49:27 PM PDT 24 860025221 ps
T333 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2636257938 Jul 25 04:49:25 PM PDT 24 Jul 25 04:50:42 PM PDT 24 26453799085 ps
T334 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1702570228 Jul 25 04:50:01 PM PDT 24 Jul 25 04:51:50 PM PDT 24 31813915885 ps
T335 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2270013372 Jul 25 04:49:28 PM PDT 24 Jul 25 04:49:31 PM PDT 24 378566987 ps
T163 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.157741663 Jul 25 04:49:50 PM PDT 24 Jul 25 04:50:13 PM PDT 24 7035168360 ps
T336 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2141632818 Jul 25 04:49:50 PM PDT 24 Jul 25 04:49:53 PM PDT 24 655876100 ps
T337 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2198113752 Jul 25 04:49:46 PM PDT 24 Jul 25 04:49:47 PM PDT 24 182665645 ps
T338 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.676513183 Jul 25 04:49:39 PM PDT 24 Jul 25 04:49:41 PM PDT 24 228993249 ps
T339 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2156583133 Jul 25 04:49:37 PM PDT 24 Jul 25 04:49:39 PM PDT 24 49277381 ps
T340 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1259513473 Jul 25 04:49:13 PM PDT 24 Jul 25 04:49:14 PM PDT 24 87924235 ps
T341 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3647747705 Jul 25 04:50:00 PM PDT 24 Jul 25 04:50:03 PM PDT 24 2810241419 ps
T115 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3672318433 Jul 25 04:49:24 PM PDT 24 Jul 25 04:49:30 PM PDT 24 174558390 ps
T342 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1419362149 Jul 25 04:49:21 PM PDT 24 Jul 25 04:49:43 PM PDT 24 7612322263 ps
T343 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1061017406 Jul 25 04:49:34 PM PDT 24 Jul 25 04:49:35 PM PDT 24 53682109 ps
T344 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2187189860 Jul 25 04:49:22 PM PDT 24 Jul 25 04:49:40 PM PDT 24 23091060963 ps
T345 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4283242898 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:29 PM PDT 24 938138721 ps
T346 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1974000707 Jul 25 04:49:41 PM PDT 24 Jul 25 04:49:44 PM PDT 24 2209765078 ps
T347 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3103586086 Jul 25 04:49:24 PM PDT 24 Jul 25 04:49:56 PM PDT 24 18025261634 ps
T348 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3518567073 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:26 PM PDT 24 45650197 ps
T349 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.941416451 Jul 25 04:49:43 PM PDT 24 Jul 25 04:49:46 PM PDT 24 271327896 ps
T350 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2424453681 Jul 25 04:49:56 PM PDT 24 Jul 25 04:49:58 PM PDT 24 367882019 ps
T166 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4053331852 Jul 25 04:49:41 PM PDT 24 Jul 25 04:49:58 PM PDT 24 1079400550 ps
T351 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3596669201 Jul 25 04:50:00 PM PDT 24 Jul 25 04:50:04 PM PDT 24 314668436 ps
T352 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.423581471 Jul 25 04:49:26 PM PDT 24 Jul 25 04:50:44 PM PDT 24 54460639721 ps
T109 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.618804645 Jul 25 04:50:02 PM PDT 24 Jul 25 04:50:05 PM PDT 24 202119263 ps
T353 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4183889789 Jul 25 04:49:51 PM PDT 24 Jul 25 04:49:53 PM PDT 24 252761496 ps
T167 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3786745939 Jul 25 04:49:38 PM PDT 24 Jul 25 04:49:59 PM PDT 24 4672120416 ps
T87 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4154343506 Jul 25 04:49:28 PM PDT 24 Jul 25 04:49:30 PM PDT 24 4131784269 ps
T110 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1924090521 Jul 25 04:49:31 PM PDT 24 Jul 25 04:50:26 PM PDT 24 1450298349 ps
T354 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2373899099 Jul 25 04:49:22 PM PDT 24 Jul 25 04:49:24 PM PDT 24 1363963975 ps
T355 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1331374078 Jul 25 04:49:39 PM PDT 24 Jul 25 04:50:56 PM PDT 24 25269431982 ps
T356 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1797003816 Jul 25 04:49:24 PM PDT 24 Jul 25 04:49:28 PM PDT 24 396039989 ps
T357 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3977487890 Jul 25 04:49:47 PM PDT 24 Jul 25 04:49:50 PM PDT 24 635687375 ps
T358 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4253900848 Jul 25 04:49:52 PM PDT 24 Jul 25 04:49:57 PM PDT 24 350797525 ps
T359 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2446532673 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:27 PM PDT 24 341716134 ps
T360 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2265612599 Jul 25 04:49:19 PM PDT 24 Jul 25 04:49:22 PM PDT 24 791814453 ps
T361 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1729211495 Jul 25 04:49:38 PM PDT 24 Jul 25 04:49:45 PM PDT 24 423739341 ps
T362 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1092106193 Jul 25 04:49:23 PM PDT 24 Jul 25 04:49:27 PM PDT 24 126471196 ps
T162 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1856577432 Jul 25 04:49:40 PM PDT 24 Jul 25 04:49:51 PM PDT 24 1768710275 ps
T164 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1764620051 Jul 25 04:49:17 PM PDT 24 Jul 25 04:49:44 PM PDT 24 4223718170 ps
T99 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1198345102 Jul 25 04:49:19 PM PDT 24 Jul 25 04:50:34 PM PDT 24 4185940380 ps
T363 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.837623960 Jul 25 04:49:30 PM PDT 24 Jul 25 04:51:17 PM PDT 24 67275929307 ps
T364 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.509965142 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:26 PM PDT 24 281310226 ps
T365 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2939530860 Jul 25 04:49:23 PM PDT 24 Jul 25 04:49:43 PM PDT 24 28665489616 ps
T366 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1462366120 Jul 25 04:49:41 PM PDT 24 Jul 25 04:50:07 PM PDT 24 13418109183 ps
T367 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3766241948 Jul 25 04:49:49 PM PDT 24 Jul 25 04:49:51 PM PDT 24 120477397 ps
T100 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3349963460 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:33 PM PDT 24 489595502 ps
T368 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2261712341 Jul 25 04:49:51 PM PDT 24 Jul 25 04:50:06 PM PDT 24 10213909046 ps
T369 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1443970467 Jul 25 04:49:41 PM PDT 24 Jul 25 04:49:50 PM PDT 24 1079417793 ps
T370 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.752018128 Jul 25 04:50:05 PM PDT 24 Jul 25 04:50:09 PM PDT 24 117010184 ps
T371 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3246948652 Jul 25 04:49:30 PM PDT 24 Jul 25 04:49:33 PM PDT 24 104029366 ps
T372 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.850398347 Jul 25 04:49:38 PM PDT 24 Jul 25 04:49:41 PM PDT 24 407054210 ps
T373 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3314340217 Jul 25 04:49:34 PM PDT 24 Jul 25 04:49:37 PM PDT 24 2506665808 ps
T374 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2663035861 Jul 25 04:49:44 PM PDT 24 Jul 25 04:49:47 PM PDT 24 871686298 ps
T88 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2447263368 Jul 25 04:49:24 PM PDT 24 Jul 25 04:49:33 PM PDT 24 9554089146 ps
T375 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3442792174 Jul 25 04:49:20 PM PDT 24 Jul 25 04:49:26 PM PDT 24 322465185 ps
T376 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.343952357 Jul 25 04:49:37 PM PDT 24 Jul 25 04:49:46 PM PDT 24 723045551 ps
T377 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2021494866 Jul 25 04:49:39 PM PDT 24 Jul 25 04:49:46 PM PDT 24 247247524 ps
T378 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.658647291 Jul 25 04:49:37 PM PDT 24 Jul 25 04:49:55 PM PDT 24 10418008110 ps
T379 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.699175088 Jul 25 04:49:46 PM PDT 24 Jul 25 04:49:48 PM PDT 24 94016981 ps
T380 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3498758456 Jul 25 04:49:59 PM PDT 24 Jul 25 04:50:03 PM PDT 24 563890899 ps
T381 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.410400800 Jul 25 04:49:59 PM PDT 24 Jul 25 04:50:01 PM PDT 24 573272468 ps
T382 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1839492108 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:26 PM PDT 24 274464864 ps
T383 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.935440815 Jul 25 04:49:44 PM PDT 24 Jul 25 04:49:52 PM PDT 24 587716435 ps
T384 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1292770673 Jul 25 04:49:42 PM PDT 24 Jul 25 04:49:44 PM PDT 24 180685891 ps
T385 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1573810322 Jul 25 04:49:23 PM PDT 24 Jul 25 04:49:27 PM PDT 24 704444995 ps
T386 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2412403433 Jul 25 04:49:21 PM PDT 24 Jul 25 04:49:54 PM PDT 24 1964112925 ps
T89 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.4014153777 Jul 25 04:49:17 PM PDT 24 Jul 25 04:49:27 PM PDT 24 5751277117 ps
T387 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3928482576 Jul 25 04:49:30 PM PDT 24 Jul 25 04:49:32 PM PDT 24 416009541 ps
T388 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.612042100 Jul 25 04:49:43 PM PDT 24 Jul 25 04:49:52 PM PDT 24 634040599 ps
T389 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3257890809 Jul 25 04:49:24 PM PDT 24 Jul 25 04:49:52 PM PDT 24 30393914875 ps
T390 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2206248941 Jul 25 04:49:56 PM PDT 24 Jul 25 04:49:57 PM PDT 24 178246080 ps
T391 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.320674400 Jul 25 04:50:06 PM PDT 24 Jul 25 04:50:09 PM PDT 24 77600366 ps
T392 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.427736198 Jul 25 04:49:24 PM PDT 24 Jul 25 04:49:25 PM PDT 24 40032960 ps
T393 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.719263238 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:25 PM PDT 24 205883706 ps
T394 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4189929736 Jul 25 04:49:49 PM PDT 24 Jul 25 04:49:51 PM PDT 24 64703512 ps
T395 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2588200789 Jul 25 04:49:21 PM PDT 24 Jul 25 04:49:28 PM PDT 24 2478562029 ps
T396 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1216928017 Jul 25 04:49:48 PM PDT 24 Jul 25 04:49:56 PM PDT 24 1736075309 ps
T397 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2375132518 Jul 25 04:50:01 PM PDT 24 Jul 25 04:50:04 PM PDT 24 244247499 ps
T398 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1762822549 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:27 PM PDT 24 553182637 ps
T399 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2318016498 Jul 25 04:49:24 PM PDT 24 Jul 25 04:49:28 PM PDT 24 849592614 ps
T400 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1222635372 Jul 25 04:50:08 PM PDT 24 Jul 25 04:50:20 PM PDT 24 14699009351 ps
T401 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1425535241 Jul 25 04:49:21 PM PDT 24 Jul 25 04:49:27 PM PDT 24 228970692 ps
T402 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1299858554 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:30 PM PDT 24 4466004835 ps
T403 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.826786179 Jul 25 04:49:51 PM PDT 24 Jul 25 04:50:03 PM PDT 24 1754001560 ps
T404 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1814065095 Jul 25 04:50:10 PM PDT 24 Jul 25 04:50:15 PM PDT 24 488138592 ps
T405 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3949052877 Jul 25 04:49:37 PM PDT 24 Jul 25 04:49:41 PM PDT 24 120387326 ps
T406 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3286718184 Jul 25 04:49:50 PM PDT 24 Jul 25 04:50:04 PM PDT 24 3292262981 ps
T165 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2586918351 Jul 25 04:49:24 PM PDT 24 Jul 25 04:49:47 PM PDT 24 2008569550 ps
T407 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.296674368 Jul 25 04:49:16 PM PDT 24 Jul 25 04:49:17 PM PDT 24 230222479 ps
T408 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3665154879 Jul 25 04:49:45 PM PDT 24 Jul 25 04:49:48 PM PDT 24 106718707 ps
T104 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3594529514 Jul 25 04:49:34 PM PDT 24 Jul 25 04:49:36 PM PDT 24 467127398 ps
T409 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3313024387 Jul 25 04:49:39 PM PDT 24 Jul 25 04:49:42 PM PDT 24 915460470 ps
T410 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.148412272 Jul 25 04:49:44 PM PDT 24 Jul 25 04:49:49 PM PDT 24 132043894 ps
T411 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3275314174 Jul 25 04:49:35 PM PDT 24 Jul 25 04:49:41 PM PDT 24 3512441494 ps
T412 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2770084786 Jul 25 04:49:32 PM PDT 24 Jul 25 04:57:15 PM PDT 24 162581261113 ps
T413 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1348998004 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:28 PM PDT 24 2497945846 ps
T168 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.736838835 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:45 PM PDT 24 4122671037 ps
T414 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1717695421 Jul 25 04:49:23 PM PDT 24 Jul 25 04:49:24 PM PDT 24 155510448 ps
T415 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.41257060 Jul 25 04:49:45 PM PDT 24 Jul 25 04:49:48 PM PDT 24 75566503 ps
T416 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3795293447 Jul 25 04:50:13 PM PDT 24 Jul 25 04:50:17 PM PDT 24 354685989 ps
T417 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3413933870 Jul 25 04:50:11 PM PDT 24 Jul 25 04:50:14 PM PDT 24 297189686 ps
T418 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1720252606 Jul 25 04:49:38 PM PDT 24 Jul 25 04:49:49 PM PDT 24 9149226337 ps
T419 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.662460799 Jul 25 04:49:41 PM PDT 24 Jul 25 04:49:48 PM PDT 24 3346361325 ps
T420 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.244300999 Jul 25 04:49:44 PM PDT 24 Jul 25 04:49:48 PM PDT 24 170713183 ps
T90 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2004546877 Jul 25 04:49:13 PM PDT 24 Jul 25 04:49:24 PM PDT 24 6234425070 ps
T421 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3696247533 Jul 25 04:49:22 PM PDT 24 Jul 25 04:49:29 PM PDT 24 4152925615 ps
T422 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.533707352 Jul 25 04:49:26 PM PDT 24 Jul 25 04:49:27 PM PDT 24 97895700 ps
T101 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4030809119 Jul 25 04:49:57 PM PDT 24 Jul 25 04:49:59 PM PDT 24 350250773 ps
T423 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2364456656 Jul 25 04:49:50 PM PDT 24 Jul 25 04:49:51 PM PDT 24 608454557 ps
T424 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1651248610 Jul 25 04:49:50 PM PDT 24 Jul 25 04:49:52 PM PDT 24 62199801 ps
T425 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3470304061 Jul 25 04:49:17 PM PDT 24 Jul 25 04:49:18 PM PDT 24 400384730 ps
T426 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3006036044 Jul 25 04:49:45 PM PDT 24 Jul 25 04:49:47 PM PDT 24 446656807 ps
T427 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3364782656 Jul 25 04:49:54 PM PDT 24 Jul 25 04:50:29 PM PDT 24 34475922342 ps
T428 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1133025553 Jul 25 04:50:07 PM PDT 24 Jul 25 04:50:10 PM PDT 24 2061709459 ps
T429 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2834510854 Jul 25 04:49:54 PM PDT 24 Jul 25 04:50:16 PM PDT 24 3497805139 ps
T430 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3562999003 Jul 25 04:49:16 PM PDT 24 Jul 25 04:52:08 PM PDT 24 59376494378 ps
T431 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1678467590 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:29 PM PDT 24 682838813 ps
T432 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.176592761 Jul 25 04:49:36 PM PDT 24 Jul 25 04:49:38 PM PDT 24 819772033 ps
T433 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.971938827 Jul 25 04:49:32 PM PDT 24 Jul 25 04:49:38 PM PDT 24 3129799456 ps
T434 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1193856140 Jul 25 04:49:25 PM PDT 24 Jul 25 04:49:26 PM PDT 24 213948622 ps
T435 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1019526778 Jul 25 04:49:20 PM PDT 24 Jul 25 04:49:21 PM PDT 24 64314681 ps
T436 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.38226700 Jul 25 04:49:27 PM PDT 24 Jul 25 04:49:30 PM PDT 24 109726897 ps
T437 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.183948395 Jul 25 04:49:19 PM PDT 24 Jul 25 04:50:22 PM PDT 24 62893398259 ps
T438 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.7895460 Jul 25 04:49:38 PM PDT 24 Jul 25 04:50:16 PM PDT 24 13998425601 ps
T439 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.313378004 Jul 25 04:49:34 PM PDT 24 Jul 25 04:49:36 PM PDT 24 431091718 ps
T440 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2862984389 Jul 25 04:49:34 PM PDT 24 Jul 25 04:49:36 PM PDT 24 133339815 ps
T441 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2492631374 Jul 25 04:49:22 PM PDT 24 Jul 25 04:49:33 PM PDT 24 1180367019 ps
T442 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2402790576 Jul 25 04:49:50 PM PDT 24 Jul 25 04:50:10 PM PDT 24 1734431637 ps
T443 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3424519767 Jul 25 04:49:40 PM PDT 24 Jul 25 04:49:43 PM PDT 24 231527109 ps
T444 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3410733193 Jul 25 04:49:22 PM PDT 24 Jul 25 04:50:41 PM PDT 24 30852822480 ps

Test location /workspace/coverage/default/9.rv_dm_stress_all.2021863729
Short name T7
Test name
Test status
Simulation time 8982945136 ps
CPU time 3.96 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:15 PM PDT 24
Peak memory 213364 kb
Host smart-0428075d-3aae-4f98-9485-879de9ce7a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021863729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.2021863729
Directory /workspace/9.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.1538329292
Short name T5
Test name
Test status
Simulation time 191296648893 ps
CPU time 690.9 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 05:01:44 PM PDT 24
Peak memory 232124 kb
Host smart-a9db7611-a910-47be-8636-7dba97528ec6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538329292 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.1538329292
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2970477444
Short name T25
Test name
Test status
Simulation time 16155598284 ps
CPU time 10 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:29 PM PDT 24
Peak memory 213532 kb
Host smart-d1b1816a-a0f1-44b8-9096-d387bfe89ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970477444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2970477444
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2534117118
Short name T62
Test name
Test status
Simulation time 47107982177 ps
CPU time 135 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:51:40 PM PDT 24
Peak memory 221516 kb
Host smart-d027cb26-634b-4c7c-9aa9-9c0c000ded3d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534117118 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2534117118
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4283609229
Short name T118
Test name
Test status
Simulation time 3193907937 ps
CPU time 10.69 seconds
Started Jul 25 04:49:15 PM PDT 24
Finished Jul 25 04:49:26 PM PDT 24
Peak memory 213268 kb
Host smart-12ad7d27-a2e2-4b4b-b159-e2ff140945c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283609229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.4283609229
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2980636727
Short name T29
Test name
Test status
Simulation time 9870979806 ps
CPU time 13.84 seconds
Started Jul 25 04:50:14 PM PDT 24
Finished Jul 25 04:50:29 PM PDT 24
Peak memory 213452 kb
Host smart-11150a7f-d0a7-466e-8ed0-de131cb0a3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980636727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2980636727
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2752239257
Short name T39
Test name
Test status
Simulation time 57221451 ps
CPU time 0.78 seconds
Started Jul 25 04:50:10 PM PDT 24
Finished Jul 25 04:50:11 PM PDT 24
Peak memory 205032 kb
Host smart-32a69a78-bd19-4230-9c8f-3922edd2773d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752239257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2752239257
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.554762489
Short name T22
Test name
Test status
Simulation time 769736793 ps
CPU time 2.3 seconds
Started Jul 25 04:49:58 PM PDT 24
Finished Jul 25 04:50:00 PM PDT 24
Peak memory 204964 kb
Host smart-85ae15b5-6b3d-42e7-a943-0509303a184a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554762489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.554762489
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.4198757613
Short name T143
Test name
Test status
Simulation time 12141395034 ps
CPU time 17.38 seconds
Started Jul 25 04:50:20 PM PDT 24
Finished Jul 25 04:50:37 PM PDT 24
Peak memory 213556 kb
Host smart-d58f9c7a-6e8e-4378-aa78-06e64b475960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198757613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.4198757613
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.1036016716
Short name T123
Test name
Test status
Simulation time 1660850233 ps
CPU time 1.92 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:13 PM PDT 24
Peak memory 205044 kb
Host smart-fa96a674-295a-44a1-94e9-6a3866b600d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036016716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.1036016716
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.842667910
Short name T67
Test name
Test status
Simulation time 42279782501 ps
CPU time 333.23 seconds
Started Jul 25 04:49:53 PM PDT 24
Finished Jul 25 04:55:26 PM PDT 24
Peak memory 221784 kb
Host smart-e3806121-926c-41c1-b5e5-3793af9af68b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842667910 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.842667910
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1262502177
Short name T97
Test name
Test status
Simulation time 36309101295 ps
CPU time 78.47 seconds
Started Jul 25 04:49:22 PM PDT 24
Finished Jul 25 04:50:41 PM PDT 24
Peak memory 213280 kb
Host smart-2fbbff43-d380-4a20-8495-bf23ac8122cc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262502177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1262502177
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.254161074
Short name T159
Test name
Test status
Simulation time 5425222782 ps
CPU time 16.87 seconds
Started Jul 25 04:50:04 PM PDT 24
Finished Jul 25 04:50:21 PM PDT 24
Peak memory 213340 kb
Host smart-61f6500d-e181-4532-be8f-fcb31dd3841b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254161074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.254161074
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.827329101
Short name T57
Test name
Test status
Simulation time 2146791482 ps
CPU time 4.98 seconds
Started Jul 25 04:49:58 PM PDT 24
Finished Jul 25 04:50:03 PM PDT 24
Peak memory 229240 kb
Host smart-3cc92f06-867b-4dba-bb5a-2c21f9064ab7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827329101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.827329101
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.2993895808
Short name T38
Test name
Test status
Simulation time 529783022 ps
CPU time 1.97 seconds
Started Jul 25 04:49:55 PM PDT 24
Finished Jul 25 04:49:58 PM PDT 24
Peak memory 204976 kb
Host smart-50a0d475-4075-46c7-9a36-8f14e8a9da71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993895808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.2993895808
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3733303651
Short name T136
Test name
Test status
Simulation time 11938472089 ps
CPU time 11.05 seconds
Started Jul 25 04:50:09 PM PDT 24
Finished Jul 25 04:50:20 PM PDT 24
Peak memory 213512 kb
Host smart-04fd62d4-855f-4719-a5af-cccc0fbe8388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733303651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3733303651
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3265650116
Short name T33
Test name
Test status
Simulation time 193324583 ps
CPU time 0.88 seconds
Started Jul 25 04:50:10 PM PDT 24
Finished Jul 25 04:50:11 PM PDT 24
Peak memory 213160 kb
Host smart-7184fda0-ed89-413a-adca-4277a646f0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265650116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3265650116
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.2747919151
Short name T45
Test name
Test status
Simulation time 310322389 ps
CPU time 1.59 seconds
Started Jul 25 04:49:59 PM PDT 24
Finished Jul 25 04:50:01 PM PDT 24
Peak memory 204984 kb
Host smart-6177b390-b063-4f19-8e8a-df812bd48259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747919151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2747919151
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.214283945
Short name T78
Test name
Test status
Simulation time 2109090840 ps
CPU time 4.25 seconds
Started Jul 25 04:49:45 PM PDT 24
Finished Jul 25 04:49:49 PM PDT 24
Peak memory 204964 kb
Host smart-d655a628-9f1e-4b68-b0e1-85bb07f7a8e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214283945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same_
csr_outstanding.214283945
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.498691739
Short name T131
Test name
Test status
Simulation time 6685728123 ps
CPU time 20.49 seconds
Started Jul 25 04:49:47 PM PDT 24
Finished Jul 25 04:50:08 PM PDT 24
Peak memory 213588 kb
Host smart-2a34b707-06bd-49c0-bc0a-51a348a68a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498691739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.498691739
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.369790460
Short name T4
Test name
Test status
Simulation time 1006058364 ps
CPU time 1.44 seconds
Started Jul 25 04:50:10 PM PDT 24
Finished Jul 25 04:50:11 PM PDT 24
Peak memory 204960 kb
Host smart-89532ed3-4a8f-4ec8-a9e0-cd67890803bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369790460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.369790460
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3814465614
Short name T130
Test name
Test status
Simulation time 6708635953 ps
CPU time 11.18 seconds
Started Jul 25 04:50:07 PM PDT 24
Finished Jul 25 04:50:18 PM PDT 24
Peak memory 213524 kb
Host smart-5ed5e16b-90b0-497d-9de5-7066aac322cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814465614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3814465614
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.3665967281
Short name T28
Test name
Test status
Simulation time 81151109 ps
CPU time 0.71 seconds
Started Jul 25 04:49:52 PM PDT 24
Finished Jul 25 04:49:53 PM PDT 24
Peak memory 204984 kb
Host smart-f88789a2-25e5-441c-a0e3-5512dc8c010f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665967281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3665967281
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3530178967
Short name T121
Test name
Test status
Simulation time 1065917483 ps
CPU time 17.07 seconds
Started Jul 25 04:49:47 PM PDT 24
Finished Jul 25 04:50:05 PM PDT 24
Peak memory 213252 kb
Host smart-fbf9ca7f-a47b-455e-94cf-53eb8e7cc797
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530178967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
530178967
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3970222981
Short name T63
Test name
Test status
Simulation time 7985468886 ps
CPU time 12.11 seconds
Started Jul 25 04:49:20 PM PDT 24
Finished Jul 25 04:49:32 PM PDT 24
Peak memory 204960 kb
Host smart-16da1327-e473-4bab-b349-a7343abfffc3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970222981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3970222981
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2004546877
Short name T90
Test name
Test status
Simulation time 6234425070 ps
CPU time 10.23 seconds
Started Jul 25 04:49:13 PM PDT 24
Finished Jul 25 04:49:24 PM PDT 24
Peak memory 205000 kb
Host smart-bd0d4c7d-c611-456a-b7be-dff35a2125d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004546877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2004546877
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3239191401
Short name T81
Test name
Test status
Simulation time 115999894 ps
CPU time 2.36 seconds
Started Jul 25 04:49:28 PM PDT 24
Finished Jul 25 04:49:30 PM PDT 24
Peak memory 213240 kb
Host smart-998c883c-4905-4b9e-be84-120a5c08a146
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239191401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3239191401
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2263722655
Short name T147
Test name
Test status
Simulation time 4172740361 ps
CPU time 3.08 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:16 PM PDT 24
Peak memory 205428 kb
Host smart-a30335c3-b413-491e-90cb-e3b30cc37586
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263722655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2263722655
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.608406582
Short name T9
Test name
Test status
Simulation time 473562078 ps
CPU time 1.1 seconds
Started Jul 25 04:49:59 PM PDT 24
Finished Jul 25 04:50:01 PM PDT 24
Peak memory 204964 kb
Host smart-0811f680-e101-4ed0-9608-2479611db334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608406582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.608406582
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2577438984
Short name T120
Test name
Test status
Simulation time 1010557192 ps
CPU time 8.53 seconds
Started Jul 25 04:49:41 PM PDT 24
Finished Jul 25 04:49:50 PM PDT 24
Peak memory 213292 kb
Host smart-28449401-4272-4c9f-abe3-391ebf1269ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577438984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
577438984
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3295950671
Short name T161
Test name
Test status
Simulation time 14106038753 ps
CPU time 20.33 seconds
Started Jul 25 04:49:33 PM PDT 24
Finished Jul 25 04:49:54 PM PDT 24
Peak memory 213344 kb
Host smart-bace2801-332e-4d6a-8ee3-3d20871d6269
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295950671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3295950671
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.784469884
Short name T126
Test name
Test status
Simulation time 19642652438 ps
CPU time 36.16 seconds
Started Jul 25 04:50:06 PM PDT 24
Finished Jul 25 04:50:43 PM PDT 24
Peak memory 213540 kb
Host smart-9fc88655-9b14-4f10-bb41-86121748cf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784469884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.784469884
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.961242914
Short name T66
Test name
Test status
Simulation time 133395918 ps
CPU time 1.03 seconds
Started Jul 25 04:50:02 PM PDT 24
Finished Jul 25 04:50:03 PM PDT 24
Peak memory 204968 kb
Host smart-67913186-d913-434e-8b08-6fd764117cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961242914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.961242914
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2865018110
Short name T150
Test name
Test status
Simulation time 1838202109 ps
CPU time 2.26 seconds
Started Jul 25 04:49:58 PM PDT 24
Finished Jul 25 04:50:00 PM PDT 24
Peak memory 205224 kb
Host smart-4abb4d82-75de-4346-aeaf-a49954411a38
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865018110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2865018110
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1920473830
Short name T125
Test name
Test status
Simulation time 4793708134 ps
CPU time 13.18 seconds
Started Jul 25 04:50:03 PM PDT 24
Finished Jul 25 04:50:16 PM PDT 24
Peak memory 205252 kb
Host smart-75708c90-ad93-41da-a6b6-22aecad5a593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920473830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1920473830
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.1385724675
Short name T153
Test name
Test status
Simulation time 3953527510 ps
CPU time 2.76 seconds
Started Jul 25 04:50:15 PM PDT 24
Finished Jul 25 04:50:18 PM PDT 24
Peak memory 205232 kb
Host smart-e1355783-cbaf-46c7-9d27-b2f00c113eb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385724675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.1385724675
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1198345102
Short name T99
Test name
Test status
Simulation time 4185940380 ps
CPU time 74.85 seconds
Started Jul 25 04:49:19 PM PDT 24
Finished Jul 25 04:50:34 PM PDT 24
Peak memory 213228 kb
Host smart-dc1ce30a-9bdf-499d-95e3-e17613c2a5f0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198345102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1198345102
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.4030809119
Short name T101
Test name
Test status
Simulation time 350250773 ps
CPU time 2.28 seconds
Started Jul 25 04:49:57 PM PDT 24
Finished Jul 25 04:49:59 PM PDT 24
Peak memory 213296 kb
Host smart-6f59bdd6-f4f6-4931-92c1-8fc958d33d63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030809119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.4030809119
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2636257938
Short name T333
Test name
Test status
Simulation time 26453799085 ps
CPU time 77.28 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:50:42 PM PDT 24
Peak memory 213280 kb
Host smart-51a18135-14ee-4a0b-8f1b-484d7c8be6da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636257938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2636257938
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.2862984389
Short name T440
Test name
Test status
Simulation time 133339815 ps
CPU time 2.46 seconds
Started Jul 25 04:49:34 PM PDT 24
Finished Jul 25 04:49:36 PM PDT 24
Peak memory 213192 kb
Host smart-99257206-cabf-4cdc-80e1-19f145900e2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862984389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.2862984389
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.93834847
Short name T321
Test name
Test status
Simulation time 1022708343 ps
CPU time 3.81 seconds
Started Jul 25 04:49:38 PM PDT 24
Finished Jul 25 04:49:42 PM PDT 24
Peak memory 218780 kb
Host smart-ce6b86e8-136d-4f91-a52c-36b266471c77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93834847 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.93834847
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3303901687
Short name T328
Test name
Test status
Simulation time 256060077 ps
CPU time 1.55 seconds
Started Jul 25 04:49:18 PM PDT 24
Finished Jul 25 04:49:19 PM PDT 24
Peak memory 213196 kb
Host smart-23109644-94f5-40db-a8cb-2b4577092d40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303901687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3303901687
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2187189860
Short name T344
Test name
Test status
Simulation time 23091060963 ps
CPU time 17.87 seconds
Started Jul 25 04:49:22 PM PDT 24
Finished Jul 25 04:49:40 PM PDT 24
Peak memory 204952 kb
Host smart-d8476a40-cf95-4c8a-8330-7eac6ff7d6fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187189860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2187189860
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.183948395
Short name T437
Test name
Test status
Simulation time 62893398259 ps
CPU time 62.32 seconds
Started Jul 25 04:49:19 PM PDT 24
Finished Jul 25 04:50:22 PM PDT 24
Peak memory 205032 kb
Host smart-faddfc84-9bb7-4c9a-8c68-1b374b72925c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183948395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.r
v_dm_jtag_dmi_csr_bit_bash.183948395
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.176592761
Short name T432
Test name
Test status
Simulation time 819772033 ps
CPU time 2.18 seconds
Started Jul 25 04:49:36 PM PDT 24
Finished Jul 25 04:49:38 PM PDT 24
Peak memory 204884 kb
Host smart-c5672a43-8154-4e24-b22b-cb91c06e8e29
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176592761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.176592761
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2373899099
Short name T354
Test name
Test status
Simulation time 1363963975 ps
CPU time 1.04 seconds
Started Jul 25 04:49:22 PM PDT 24
Finished Jul 25 04:49:24 PM PDT 24
Peak memory 204736 kb
Host smart-9210a899-4b29-4716-9e36-f6e1e07153fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373899099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2373899099
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3470304061
Short name T425
Test name
Test status
Simulation time 400384730 ps
CPU time 0.97 seconds
Started Jul 25 04:49:17 PM PDT 24
Finished Jul 25 04:49:18 PM PDT 24
Peak memory 204704 kb
Host smart-42a22a70-f850-4194-8ae8-51bf671f58df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470304061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3470304061
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3442792174
Short name T375
Test name
Test status
Simulation time 322465185 ps
CPU time 0.94 seconds
Started Jul 25 04:49:20 PM PDT 24
Finished Jul 25 04:49:26 PM PDT 24
Peak memory 204820 kb
Host smart-ed68dec8-fbf0-496d-a362-c857575d29b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442792174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
442792174
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1259513473
Short name T340
Test name
Test status
Simulation time 87924235 ps
CPU time 0.69 seconds
Started Jul 25 04:49:13 PM PDT 24
Finished Jul 25 04:49:14 PM PDT 24
Peak memory 204668 kb
Host smart-c15b281d-b354-4426-b128-4b8579a5957b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259513473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1259513473
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2777343450
Short name T330
Test name
Test status
Simulation time 44352939 ps
CPU time 0.66 seconds
Started Jul 25 04:49:16 PM PDT 24
Finished Jul 25 04:49:17 PM PDT 24
Peak memory 204744 kb
Host smart-ef7a9072-57de-4453-a5d2-29bc65a26417
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777343450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2777343450
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1780106962
Short name T114
Test name
Test status
Simulation time 860025221 ps
CPU time 4.43 seconds
Started Jul 25 04:49:23 PM PDT 24
Finished Jul 25 04:49:27 PM PDT 24
Peak memory 204944 kb
Host smart-4b50cb8d-14a8-468e-b6ba-322d6dbc5285
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780106962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1780106962
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3562999003
Short name T430
Test name
Test status
Simulation time 59376494378 ps
CPU time 171.97 seconds
Started Jul 25 04:49:16 PM PDT 24
Finished Jul 25 04:52:08 PM PDT 24
Peak memory 223972 kb
Host smart-745eece2-54ae-4781-b15f-80f8c09ab1ea
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562999003 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3562999003
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1425535241
Short name T401
Test name
Test status
Simulation time 228970692 ps
CPU time 5.16 seconds
Started Jul 25 04:49:21 PM PDT 24
Finished Jul 25 04:49:27 PM PDT 24
Peak memory 213324 kb
Host smart-4fd2b5ba-54f5-40f4-85bc-0ad1f04bbbc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425535241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1425535241
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2069130108
Short name T108
Test name
Test status
Simulation time 57517238414 ps
CPU time 84.87 seconds
Started Jul 25 04:49:20 PM PDT 24
Finished Jul 25 04:50:45 PM PDT 24
Peak memory 205032 kb
Host smart-f178e17b-f173-47a1-8688-e13df52a5514
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069130108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2069130108
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.4063703038
Short name T107
Test name
Test status
Simulation time 675551932 ps
CPU time 2.55 seconds
Started Jul 25 04:49:15 PM PDT 24
Finished Jul 25 04:49:18 PM PDT 24
Peak memory 213212 kb
Host smart-58d62556-de76-4c86-8571-9519865099c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063703038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.4063703038
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2318859838
Short name T72
Test name
Test status
Simulation time 287759048 ps
CPU time 2.28 seconds
Started Jul 25 04:49:22 PM PDT 24
Finished Jul 25 04:49:24 PM PDT 24
Peak memory 213224 kb
Host smart-c26ca87f-f67b-494b-83eb-413a4f1d27bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318859838 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2318859838
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.296674368
Short name T407
Test name
Test status
Simulation time 230222479 ps
CPU time 1.57 seconds
Started Jul 25 04:49:16 PM PDT 24
Finished Jul 25 04:49:17 PM PDT 24
Peak memory 213176 kb
Host smart-3446b43b-0168-49db-84f2-fac302dd8303
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296674368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.296674368
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.707344195
Short name T313
Test name
Test status
Simulation time 16666160142 ps
CPU time 43.62 seconds
Started Jul 25 04:49:21 PM PDT 24
Finished Jul 25 04:50:04 PM PDT 24
Peak memory 204996 kb
Host smart-c25c16ae-d7c8-4003-955a-187f0b986232
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707344195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.707344195
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1419362149
Short name T342
Test name
Test status
Simulation time 7612322263 ps
CPU time 22 seconds
Started Jul 25 04:49:21 PM PDT 24
Finished Jul 25 04:49:43 PM PDT 24
Peak memory 204892 kb
Host smart-665da179-12e0-4669-a230-cf9d370fa4eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419362149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1419362149
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.4014153777
Short name T89
Test name
Test status
Simulation time 5751277117 ps
CPU time 10.24 seconds
Started Jul 25 04:49:17 PM PDT 24
Finished Jul 25 04:49:27 PM PDT 24
Peak memory 205076 kb
Host smart-5d5152d3-4f08-4eab-b63f-3d96dd6994bb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014153777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.4014153777
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.876812720
Short name T295
Test name
Test status
Simulation time 3011931830 ps
CPU time 2.26 seconds
Started Jul 25 04:49:17 PM PDT 24
Finished Jul 25 04:49:19 PM PDT 24
Peak memory 205100 kb
Host smart-51628925-d664-4d20-9cef-2bda95d49654
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876812720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.876812720
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2588200789
Short name T395
Test name
Test status
Simulation time 2478562029 ps
CPU time 6.91 seconds
Started Jul 25 04:49:21 PM PDT 24
Finished Jul 25 04:49:28 PM PDT 24
Peak memory 204796 kb
Host smart-059e3402-a4e7-4db7-9973-634ecc2d0ed0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588200789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2588200789
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.471643895
Short name T314
Test name
Test status
Simulation time 14660892334 ps
CPU time 12 seconds
Started Jul 25 04:49:23 PM PDT 24
Finished Jul 25 04:49:35 PM PDT 24
Peak memory 205020 kb
Host smart-baedaeee-6049-49e1-971e-f46f66dd6bfd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471643895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.471643895
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2265612599
Short name T360
Test name
Test status
Simulation time 791814453 ps
CPU time 2.8 seconds
Started Jul 25 04:49:19 PM PDT 24
Finished Jul 25 04:49:22 PM PDT 24
Peak memory 204732 kb
Host smart-fbd7b970-c1c7-4660-b66c-679f1eef149b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265612599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2265612599
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3914133110
Short name T308
Test name
Test status
Simulation time 302561729 ps
CPU time 1.54 seconds
Started Jul 25 04:49:20 PM PDT 24
Finished Jul 25 04:49:22 PM PDT 24
Peak memory 204772 kb
Host smart-caca3923-c2d0-48ff-9999-193507d1d571
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914133110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
914133110
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1061017406
Short name T343
Test name
Test status
Simulation time 53682109 ps
CPU time 0.84 seconds
Started Jul 25 04:49:34 PM PDT 24
Finished Jul 25 04:49:35 PM PDT 24
Peak memory 204668 kb
Host smart-15e6e9d1-be56-484d-95a7-36c0d50081db
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061017406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1061017406
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.3151658535
Short name T292
Test name
Test status
Simulation time 124987530 ps
CPU time 0.71 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:13 PM PDT 24
Peak memory 204800 kb
Host smart-710d1f8e-6766-4ba6-9628-37c7a50b327b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151658535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.3151658535
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.962560397
Short name T112
Test name
Test status
Simulation time 1777919853 ps
CPU time 7.96 seconds
Started Jul 25 04:49:12 PM PDT 24
Finished Jul 25 04:49:20 PM PDT 24
Peak memory 204884 kb
Host smart-96cb5d5f-7467-4daa-9d9d-1de61bf2cec5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962560397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.962560397
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.4096540477
Short name T119
Test name
Test status
Simulation time 358360393 ps
CPU time 3.81 seconds
Started Jul 25 04:49:19 PM PDT 24
Finished Jul 25 04:49:23 PM PDT 24
Peak memory 213300 kb
Host smart-5306cc40-b299-47ec-8a1e-17388c0e4b08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096540477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.4096540477
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1764620051
Short name T164
Test name
Test status
Simulation time 4223718170 ps
CPU time 26.86 seconds
Started Jul 25 04:49:17 PM PDT 24
Finished Jul 25 04:49:44 PM PDT 24
Peak memory 213264 kb
Host smart-6c9d2829-52a9-4726-b346-41ac0137a412
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764620051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1764620051
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.320674400
Short name T391
Test name
Test status
Simulation time 77600366 ps
CPU time 2.16 seconds
Started Jul 25 04:50:06 PM PDT 24
Finished Jul 25 04:50:09 PM PDT 24
Peak memory 218260 kb
Host smart-4db97388-5217-4d7f-9f0e-069dddc895b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320674400 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.320674400
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3057308767
Short name T102
Test name
Test status
Simulation time 140472748 ps
CPU time 1.63 seconds
Started Jul 25 04:49:45 PM PDT 24
Finished Jul 25 04:49:46 PM PDT 24
Peak memory 213240 kb
Host smart-2139f807-96cf-41a3-bb61-cce8fd554afa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057308767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3057308767
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1462366120
Short name T366
Test name
Test status
Simulation time 13418109183 ps
CPU time 25.84 seconds
Started Jul 25 04:49:41 PM PDT 24
Finished Jul 25 04:50:07 PM PDT 24
Peak memory 204988 kb
Host smart-20765176-8561-4444-be85-0d861ec6ca05
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462366120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.1462366120
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.271436877
Short name T319
Test name
Test status
Simulation time 1337643549 ps
CPU time 2.2 seconds
Started Jul 25 04:49:46 PM PDT 24
Finished Jul 25 04:49:48 PM PDT 24
Peak memory 204920 kb
Host smart-6493abe1-7271-41fb-9496-c50f9341983f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271436877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.271436877
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3977487890
Short name T357
Test name
Test status
Simulation time 635687375 ps
CPU time 2.31 seconds
Started Jul 25 04:49:47 PM PDT 24
Finished Jul 25 04:49:50 PM PDT 24
Peak memory 204816 kb
Host smart-0839c297-c4db-46ea-87eb-d5001855f60b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977487890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3977487890
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.754938732
Short name T111
Test name
Test status
Simulation time 410415063 ps
CPU time 3.65 seconds
Started Jul 25 04:49:50 PM PDT 24
Finished Jul 25 04:49:53 PM PDT 24
Peak memory 205072 kb
Host smart-4ae6cdf8-6d0e-4db7-b377-00f9040c2c38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754938732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.754938732
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.41257060
Short name T415
Test name
Test status
Simulation time 75566503 ps
CPU time 2.98 seconds
Started Jul 25 04:49:45 PM PDT 24
Finished Jul 25 04:49:48 PM PDT 24
Peak memory 213268 kb
Host smart-52f16a0a-de78-4126-8211-96e184a0ea46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41257060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.41257060
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3786745939
Short name T167
Test name
Test status
Simulation time 4672120416 ps
CPU time 21.38 seconds
Started Jul 25 04:49:38 PM PDT 24
Finished Jul 25 04:49:59 PM PDT 24
Peak memory 213324 kb
Host smart-3cc01e63-bdc0-47e1-a68d-c8083201c827
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786745939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
786745939
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3424519767
Short name T443
Test name
Test status
Simulation time 231527109 ps
CPU time 2.47 seconds
Started Jul 25 04:49:40 PM PDT 24
Finished Jul 25 04:49:43 PM PDT 24
Peak memory 218028 kb
Host smart-83d8e9e6-3423-47ae-85fa-6b0831f74ad5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424519767 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3424519767
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4189929736
Short name T394
Test name
Test status
Simulation time 64703512 ps
CPU time 1.65 seconds
Started Jul 25 04:49:49 PM PDT 24
Finished Jul 25 04:49:51 PM PDT 24
Peak memory 213292 kb
Host smart-75d2198d-b8c3-4e1c-ad2c-2debd53783a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189929736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4189929736
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1720252606
Short name T418
Test name
Test status
Simulation time 9149226337 ps
CPU time 11.57 seconds
Started Jul 25 04:49:38 PM PDT 24
Finished Jul 25 04:49:49 PM PDT 24
Peak memory 205036 kb
Host smart-524be24f-c74a-4c19-87ea-84fadec172eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720252606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1720252606
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.662460799
Short name T419
Test name
Test status
Simulation time 3346361325 ps
CPU time 6.2 seconds
Started Jul 25 04:49:41 PM PDT 24
Finished Jul 25 04:49:48 PM PDT 24
Peak memory 205020 kb
Host smart-ed84da15-1d12-4930-976f-379207562875
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662460799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.662460799
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2663035861
Short name T374
Test name
Test status
Simulation time 871686298 ps
CPU time 2.78 seconds
Started Jul 25 04:49:44 PM PDT 24
Finished Jul 25 04:49:47 PM PDT 24
Peak memory 204740 kb
Host smart-5266e794-0cca-48e1-b41e-701bd8c3655b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663035861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2663035861
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.244300999
Short name T420
Test name
Test status
Simulation time 170713183 ps
CPU time 3.69 seconds
Started Jul 25 04:49:44 PM PDT 24
Finished Jul 25 04:49:48 PM PDT 24
Peak memory 205060 kb
Host smart-37ccc22a-c4c7-4f87-9ac4-105e797dc3c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244300999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.244300999
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1812469586
Short name T301
Test name
Test status
Simulation time 1344699533 ps
CPU time 3.06 seconds
Started Jul 25 04:49:58 PM PDT 24
Finished Jul 25 04:50:01 PM PDT 24
Peak memory 213348 kb
Host smart-c9a7c9c4-7bf4-4d1f-8998-7379c6905177
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812469586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1812469586
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.4053331852
Short name T166
Test name
Test status
Simulation time 1079400550 ps
CPU time 17.26 seconds
Started Jul 25 04:49:41 PM PDT 24
Finished Jul 25 04:49:58 PM PDT 24
Peak memory 213220 kb
Host smart-a0e3da7f-7519-4bb7-90fc-124a1f6f0ef4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053331852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.4
053331852
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.5510879
Short name T71
Test name
Test status
Simulation time 135462098 ps
CPU time 2.51 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:14 PM PDT 24
Peak memory 221248 kb
Host smart-af82a71b-359d-4aca-abad-d82edc15221c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5510879 -assert nopostproc +UVM_TESTNAME=rv
_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.5510879
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.618804645
Short name T109
Test name
Test status
Simulation time 202119263 ps
CPU time 2.51 seconds
Started Jul 25 04:50:02 PM PDT 24
Finished Jul 25 04:50:05 PM PDT 24
Peak memory 213228 kb
Host smart-59e54ca7-0aba-466d-b971-f9805c555639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618804645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.618804645
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.658647291
Short name T378
Test name
Test status
Simulation time 10418008110 ps
CPU time 12.6 seconds
Started Jul 25 04:49:37 PM PDT 24
Finished Jul 25 04:49:55 PM PDT 24
Peak memory 204944 kb
Host smart-17e9ca94-81da-4b7d-8eca-58285044f06f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658647291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rv_dm_jtag_dmi_csr_bit_bash.658647291
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1974000707
Short name T346
Test name
Test status
Simulation time 2209765078 ps
CPU time 2.53 seconds
Started Jul 25 04:49:41 PM PDT 24
Finished Jul 25 04:49:44 PM PDT 24
Peak memory 204952 kb
Host smart-ada3be98-0c41-4d84-949d-87158c920260
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974000707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1974000707
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.1443970467
Short name T369
Test name
Test status
Simulation time 1079417793 ps
CPU time 3.65 seconds
Started Jul 25 04:49:41 PM PDT 24
Finished Jul 25 04:49:50 PM PDT 24
Peak memory 204740 kb
Host smart-722700a4-10d1-4cfe-a935-ff96e20f1a0f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443970467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
1443970467
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3596669201
Short name T351
Test name
Test status
Simulation time 314668436 ps
CPU time 3.62 seconds
Started Jul 25 04:50:00 PM PDT 24
Finished Jul 25 04:50:04 PM PDT 24
Peak memory 205080 kb
Host smart-c7160133-54f3-40b6-87c7-241c7484c753
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596669201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3596669201
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2424453681
Short name T350
Test name
Test status
Simulation time 367882019 ps
CPU time 2.46 seconds
Started Jul 25 04:49:56 PM PDT 24
Finished Jul 25 04:49:58 PM PDT 24
Peak memory 213296 kb
Host smart-95459f6d-34e7-45a3-b2f2-6e607d09bb5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424453681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2424453681
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2621265515
Short name T160
Test name
Test status
Simulation time 5669189196 ps
CPU time 26.06 seconds
Started Jul 25 04:49:41 PM PDT 24
Finished Jul 25 04:50:07 PM PDT 24
Peak memory 213268 kb
Host smart-6490defb-53e4-456d-b4d9-9b864d980ff8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621265515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
621265515
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3498758456
Short name T380
Test name
Test status
Simulation time 563890899 ps
CPU time 3.85 seconds
Started Jul 25 04:49:59 PM PDT 24
Finished Jul 25 04:50:03 PM PDT 24
Peak memory 218488 kb
Host smart-521f056b-8eeb-47d3-b33c-c33d38ee8da5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498758456 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3498758456
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.349262269
Short name T116
Test name
Test status
Simulation time 83226366 ps
CPU time 1.54 seconds
Started Jul 25 04:49:39 PM PDT 24
Finished Jul 25 04:49:41 PM PDT 24
Peak memory 213180 kb
Host smart-6deace02-58f6-4a40-b344-935ac4354823
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349262269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.349262269
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3160935587
Short name T331
Test name
Test status
Simulation time 5619975228 ps
CPU time 17.94 seconds
Started Jul 25 04:49:38 PM PDT 24
Finished Jul 25 04:49:56 PM PDT 24
Peak memory 205056 kb
Host smart-3e1a0e96-9931-411c-b7a2-528c24d98f48
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160935587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.3160935587
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1293846854
Short name T311
Test name
Test status
Simulation time 3658985483 ps
CPU time 6.04 seconds
Started Jul 25 04:49:51 PM PDT 24
Finished Jul 25 04:49:57 PM PDT 24
Peak memory 205036 kb
Host smart-cba57785-e7e4-48e8-b77e-5a0f0a2049c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293846854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1293846854
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2198113752
Short name T337
Test name
Test status
Simulation time 182665645 ps
CPU time 0.92 seconds
Started Jul 25 04:49:46 PM PDT 24
Finished Jul 25 04:49:47 PM PDT 24
Peak memory 204820 kb
Host smart-26f83101-e422-4a13-9cc7-59efbf7613b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198113752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2198113752
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.148412272
Short name T410
Test name
Test status
Simulation time 132043894 ps
CPU time 4.63 seconds
Started Jul 25 04:49:44 PM PDT 24
Finished Jul 25 04:49:49 PM PDT 24
Peak memory 213268 kb
Host smart-e5625695-7f3f-4567-b5ad-ae84dfe6e9b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148412272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.148412272
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.343952357
Short name T376
Test name
Test status
Simulation time 723045551 ps
CPU time 8.71 seconds
Started Jul 25 04:49:37 PM PDT 24
Finished Jul 25 04:49:46 PM PDT 24
Peak memory 213332 kb
Host smart-2dd74c93-9cd8-4441-abf7-a5918fa7ae08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343952357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.343952357
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.4183889789
Short name T353
Test name
Test status
Simulation time 252761496 ps
CPU time 2.56 seconds
Started Jul 25 04:49:51 PM PDT 24
Finished Jul 25 04:49:53 PM PDT 24
Peak memory 213220 kb
Host smart-1e57ef27-e482-4b0d-9341-307bbcfac51b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183889789 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.4183889789
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3871771377
Short name T103
Test name
Test status
Simulation time 102051739 ps
CPU time 2.47 seconds
Started Jul 25 04:49:58 PM PDT 24
Finished Jul 25 04:50:00 PM PDT 24
Peak memory 213232 kb
Host smart-ea7f408e-d624-4df7-805f-5293455c9e9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871771377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3871771377
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.2261712341
Short name T368
Test name
Test status
Simulation time 10213909046 ps
CPU time 15.08 seconds
Started Jul 25 04:49:51 PM PDT 24
Finished Jul 25 04:50:06 PM PDT 24
Peak memory 205012 kb
Host smart-bb907e39-51af-4b5c-aaa1-ea275a2d5992
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261712341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.2261712341
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.7895460
Short name T438
Test name
Test status
Simulation time 13998425601 ps
CPU time 36.94 seconds
Started Jul 25 04:49:38 PM PDT 24
Finished Jul 25 04:50:16 PM PDT 24
Peak memory 204956 kb
Host smart-d37d7625-9877-46a5-a48b-5d0b5972579a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7895460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.7895460
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2206248941
Short name T390
Test name
Test status
Simulation time 178246080 ps
CPU time 1.23 seconds
Started Jul 25 04:49:56 PM PDT 24
Finished Jul 25 04:49:57 PM PDT 24
Peak memory 204820 kb
Host smart-44264cd3-5627-493c-8aa2-afc1e481a3ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206248941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2206248941
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2021494866
Short name T377
Test name
Test status
Simulation time 247247524 ps
CPU time 6.61 seconds
Started Jul 25 04:49:39 PM PDT 24
Finished Jul 25 04:49:46 PM PDT 24
Peak memory 205044 kb
Host smart-48cd50a3-7508-42bc-a1a0-6e82098c6dac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021494866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2021494866
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.968148276
Short name T70
Test name
Test status
Simulation time 156060406 ps
CPU time 2.82 seconds
Started Jul 25 04:49:53 PM PDT 24
Finished Jul 25 04:50:01 PM PDT 24
Peak memory 213228 kb
Host smart-035e9ee3-0f20-43a7-8c57-622d873e52b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968148276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.968148276
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.941416451
Short name T349
Test name
Test status
Simulation time 271327896 ps
CPU time 3.49 seconds
Started Jul 25 04:49:43 PM PDT 24
Finished Jul 25 04:49:46 PM PDT 24
Peak memory 218532 kb
Host smart-c302894b-ef91-42e4-97c2-fb517a1eceb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941416451 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.941416451
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1292770673
Short name T384
Test name
Test status
Simulation time 180685891 ps
CPU time 2.13 seconds
Started Jul 25 04:49:42 PM PDT 24
Finished Jul 25 04:49:44 PM PDT 24
Peak memory 213292 kb
Host smart-70f7a094-84a6-4d82-a699-199e62834e30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292770673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1292770673
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.224522845
Short name T322
Test name
Test status
Simulation time 7051941155 ps
CPU time 4.93 seconds
Started Jul 25 04:49:41 PM PDT 24
Finished Jul 25 04:49:46 PM PDT 24
Peak memory 204944 kb
Host smart-ff3858d9-f8dc-49d0-ba06-8e7397aa141c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224522845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
rv_dm_jtag_dmi_csr_bit_bash.224522845
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.119619566
Short name T312
Test name
Test status
Simulation time 2590458627 ps
CPU time 5.57 seconds
Started Jul 25 04:49:43 PM PDT 24
Finished Jul 25 04:49:49 PM PDT 24
Peak memory 204952 kb
Host smart-e0d50b34-57c5-42d4-b62f-8afac910412a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119619566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.119619566
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.410400800
Short name T381
Test name
Test status
Simulation time 573272468 ps
CPU time 2.15 seconds
Started Jul 25 04:49:59 PM PDT 24
Finished Jul 25 04:50:01 PM PDT 24
Peak memory 204792 kb
Host smart-4de2a08c-dd02-4a26-95f9-08b9df5d81b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410400800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.410400800
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.752018128
Short name T370
Test name
Test status
Simulation time 117010184 ps
CPU time 3.54 seconds
Started Jul 25 04:50:05 PM PDT 24
Finished Jul 25 04:50:09 PM PDT 24
Peak memory 205004 kb
Host smart-14ac7a0b-d6e7-4cf4-b2c4-d93dc52ccc97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752018128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_
csr_outstanding.752018128
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3665154879
Short name T408
Test name
Test status
Simulation time 106718707 ps
CPU time 2.61 seconds
Started Jul 25 04:49:45 PM PDT 24
Finished Jul 25 04:49:48 PM PDT 24
Peak memory 213196 kb
Host smart-ef31532d-20d3-4b07-a930-0003baf6f29a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665154879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3665154879
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.826786179
Short name T403
Test name
Test status
Simulation time 1754001560 ps
CPU time 11.56 seconds
Started Jul 25 04:49:51 PM PDT 24
Finished Jul 25 04:50:03 PM PDT 24
Peak memory 213164 kb
Host smart-a8ef4d50-40b6-48a0-b025-18ec7ef6b412
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826786179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.826786179
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2700571048
Short name T304
Test name
Test status
Simulation time 413673512 ps
CPU time 2.74 seconds
Started Jul 25 04:49:59 PM PDT 24
Finished Jul 25 04:50:02 PM PDT 24
Peak memory 217280 kb
Host smart-f579a590-babc-4784-8afc-f0a8255d9a90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700571048 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2700571048
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.448025859
Short name T80
Test name
Test status
Simulation time 135989951 ps
CPU time 2.48 seconds
Started Jul 25 04:49:54 PM PDT 24
Finished Jul 25 04:49:57 PM PDT 24
Peak memory 213276 kb
Host smart-e92252c7-e75c-4b6f-a7f3-d2f68278fb17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448025859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.448025859
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3314340217
Short name T373
Test name
Test status
Simulation time 2506665808 ps
CPU time 2.84 seconds
Started Jul 25 04:49:34 PM PDT 24
Finished Jul 25 04:49:37 PM PDT 24
Peak memory 205048 kb
Host smart-0f94a6e6-27c5-41e8-aab5-89254cdaf7f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314340217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.3314340217
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2660806467
Short name T309
Test name
Test status
Simulation time 1262792266 ps
CPU time 1.53 seconds
Started Jul 25 04:49:45 PM PDT 24
Finished Jul 25 04:49:47 PM PDT 24
Peak memory 204928 kb
Host smart-e57b1685-d358-42bb-b828-4bf030001d5b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660806467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2660806467
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.761103904
Short name T327
Test name
Test status
Simulation time 872331169 ps
CPU time 1.25 seconds
Started Jul 25 04:49:41 PM PDT 24
Finished Jul 25 04:49:42 PM PDT 24
Peak memory 204740 kb
Host smart-ef9c6b64-cf7f-4071-8b51-56636658e524
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761103904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.761103904
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3795293447
Short name T416
Test name
Test status
Simulation time 354685989 ps
CPU time 3.51 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:17 PM PDT 24
Peak memory 204896 kb
Host smart-6491ac21-2708-4a09-b40a-ffe0be8a17bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795293447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3795293447
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3413933870
Short name T417
Test name
Test status
Simulation time 297189686 ps
CPU time 3 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:14 PM PDT 24
Peak memory 213164 kb
Host smart-e2d0263f-7bf6-42b8-bb7d-ed7d97b8fe3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413933870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3413933870
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2834510854
Short name T429
Test name
Test status
Simulation time 3497805139 ps
CPU time 21.42 seconds
Started Jul 25 04:49:54 PM PDT 24
Finished Jul 25 04:50:16 PM PDT 24
Peak memory 213336 kb
Host smart-9c06bb20-3f35-452d-b193-fde6d77d33fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834510854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
834510854
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3086457535
Short name T325
Test name
Test status
Simulation time 305257948 ps
CPU time 4.39 seconds
Started Jul 25 04:49:57 PM PDT 24
Finished Jul 25 04:50:02 PM PDT 24
Peak memory 219548 kb
Host smart-ca584d70-73d0-433e-9235-8648a796f01d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086457535 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3086457535
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.136970746
Short name T294
Test name
Test status
Simulation time 21032319518 ps
CPU time 41.59 seconds
Started Jul 25 04:49:55 PM PDT 24
Finished Jul 25 04:50:37 PM PDT 24
Peak memory 205036 kb
Host smart-1b95e7c0-a17d-40bf-b87c-e41caeae3c85
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136970746 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.136970746
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1167100954
Short name T302
Test name
Test status
Simulation time 15000169202 ps
CPU time 20.62 seconds
Started Jul 25 04:50:06 PM PDT 24
Finished Jul 25 04:50:27 PM PDT 24
Peak memory 205112 kb
Host smart-55771ef4-6f66-49d3-ac56-77c290a8663b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167100954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1167100954
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3420293827
Short name T310
Test name
Test status
Simulation time 203238374 ps
CPU time 0.73 seconds
Started Jul 25 04:49:49 PM PDT 24
Finished Jul 25 04:49:50 PM PDT 24
Peak memory 204740 kb
Host smart-d52b2466-6d84-4420-b47c-c36cf10af33e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420293827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3420293827
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.935440815
Short name T383
Test name
Test status
Simulation time 587716435 ps
CPU time 8.03 seconds
Started Jul 25 04:49:44 PM PDT 24
Finished Jul 25 04:49:52 PM PDT 24
Peak memory 204956 kb
Host smart-b0deaa7b-01b7-4abf-afcd-bdd8659b19d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935440815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.935440815
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2141632818
Short name T336
Test name
Test status
Simulation time 655876100 ps
CPU time 2.52 seconds
Started Jul 25 04:49:50 PM PDT 24
Finished Jul 25 04:49:53 PM PDT 24
Peak memory 213212 kb
Host smart-474dd9c3-e54e-4d5c-94b5-12a4a05d17e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141632818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2141632818
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.2402790576
Short name T442
Test name
Test status
Simulation time 1734431637 ps
CPU time 19.49 seconds
Started Jul 25 04:49:50 PM PDT 24
Finished Jul 25 04:50:10 PM PDT 24
Peak memory 213140 kb
Host smart-fb4d48a1-3d33-4a00-aaca-c702e57e97f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402790576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.2
402790576
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2375132518
Short name T397
Test name
Test status
Simulation time 244247499 ps
CPU time 2.49 seconds
Started Jul 25 04:50:01 PM PDT 24
Finished Jul 25 04:50:04 PM PDT 24
Peak memory 213172 kb
Host smart-994b0c0d-5aa3-4f67-af90-0c2032bfcdf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375132518 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2375132518
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.906366821
Short name T95
Test name
Test status
Simulation time 951765608 ps
CPU time 2.32 seconds
Started Jul 25 04:50:04 PM PDT 24
Finished Jul 25 04:50:06 PM PDT 24
Peak memory 213176 kb
Host smart-146fe81e-904f-402f-9600-71e663a24184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906366821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.906366821
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3364782656
Short name T427
Test name
Test status
Simulation time 34475922342 ps
CPU time 34.91 seconds
Started Jul 25 04:49:54 PM PDT 24
Finished Jul 25 04:50:29 PM PDT 24
Peak memory 204960 kb
Host smart-a794cd6e-ac33-40bd-b32f-51a826f4f4a2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364782656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.3364782656
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2274459995
Short name T291
Test name
Test status
Simulation time 11675889275 ps
CPU time 5.01 seconds
Started Jul 25 04:50:05 PM PDT 24
Finished Jul 25 04:50:11 PM PDT 24
Peak memory 204996 kb
Host smart-3ea16cca-ab41-4252-97de-c612880c4032
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274459995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2274459995
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3006036044
Short name T426
Test name
Test status
Simulation time 446656807 ps
CPU time 1.52 seconds
Started Jul 25 04:49:45 PM PDT 24
Finished Jul 25 04:49:47 PM PDT 24
Peak memory 204804 kb
Host smart-a6adad24-f18e-4a9f-92a1-4b0069ba7df4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006036044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3006036044
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.48610986
Short name T94
Test name
Test status
Simulation time 2854578675 ps
CPU time 7.91 seconds
Started Jul 25 04:49:49 PM PDT 24
Finished Jul 25 04:49:57 PM PDT 24
Peak memory 205072 kb
Host smart-dc001fa8-cafb-4c37-a17e-d3d382bbc8e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48610986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_c
sr_outstanding.48610986
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.699175088
Short name T379
Test name
Test status
Simulation time 94016981 ps
CPU time 2.4 seconds
Started Jul 25 04:49:46 PM PDT 24
Finished Jul 25 04:49:48 PM PDT 24
Peak memory 213212 kb
Host smart-310b1593-64a9-468c-b6a9-280008c35cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699175088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.699175088
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.325732052
Short name T299
Test name
Test status
Simulation time 305670037 ps
CPU time 2.56 seconds
Started Jul 25 04:50:05 PM PDT 24
Finished Jul 25 04:50:08 PM PDT 24
Peak memory 217808 kb
Host smart-f6bc438e-12d1-4b33-97e3-ec619bcfc6c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325732052 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.325732052
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.940997125
Short name T76
Test name
Test status
Simulation time 63561662 ps
CPU time 1.63 seconds
Started Jul 25 04:49:47 PM PDT 24
Finished Jul 25 04:49:49 PM PDT 24
Peak memory 213232 kb
Host smart-664b3762-8cc3-4a2d-b99f-a84392914ea2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940997125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.940997125
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.1222635372
Short name T400
Test name
Test status
Simulation time 14699009351 ps
CPU time 11.49 seconds
Started Jul 25 04:50:08 PM PDT 24
Finished Jul 25 04:50:20 PM PDT 24
Peak memory 205040 kb
Host smart-45f96a3a-6891-41fe-8db6-26ea13469237
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222635372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.1222635372
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3820509423
Short name T297
Test name
Test status
Simulation time 3130267551 ps
CPU time 2.39 seconds
Started Jul 25 04:50:07 PM PDT 24
Finished Jul 25 04:50:09 PM PDT 24
Peak memory 205032 kb
Host smart-18705550-fd61-4be4-bbbb-f06e5c119999
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820509423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3820509423
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3140940092
Short name T329
Test name
Test status
Simulation time 125317752 ps
CPU time 0.97 seconds
Started Jul 25 04:49:59 PM PDT 24
Finished Jul 25 04:50:00 PM PDT 24
Peak memory 204736 kb
Host smart-058b6f95-3571-4354-af50-0e54bb638ccf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140940092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3140940092
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1216928017
Short name T396
Test name
Test status
Simulation time 1736075309 ps
CPU time 7.86 seconds
Started Jul 25 04:49:48 PM PDT 24
Finished Jul 25 04:49:56 PM PDT 24
Peak memory 205060 kb
Host smart-da3c5d68-7cf5-45b7-ae00-6b25e6ad4b22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216928017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1216928017
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.1814065095
Short name T404
Test name
Test status
Simulation time 488138592 ps
CPU time 4.87 seconds
Started Jul 25 04:50:10 PM PDT 24
Finished Jul 25 04:50:15 PM PDT 24
Peak memory 213324 kb
Host smart-ff713d7d-24a8-493e-941a-41141c78ba6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814065095 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.1814065095
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2412403433
Short name T386
Test name
Test status
Simulation time 1964112925 ps
CPU time 32.94 seconds
Started Jul 25 04:49:21 PM PDT 24
Finished Jul 25 04:49:54 PM PDT 24
Peak memory 205036 kb
Host smart-1bc2da62-c16b-4d10-9989-fae5d06dc236
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412403433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2412403433
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2563889034
Short name T105
Test name
Test status
Simulation time 1494980222 ps
CPU time 28.09 seconds
Started Jul 25 04:49:27 PM PDT 24
Finished Jul 25 04:49:55 PM PDT 24
Peak memory 204996 kb
Host smart-c6056a35-ef2a-4af9-b309-0ed2f4e4f90b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563889034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2563889034
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2750102756
Short name T98
Test name
Test status
Simulation time 132562967 ps
CPU time 1.75 seconds
Started Jul 25 04:49:27 PM PDT 24
Finished Jul 25 04:49:29 PM PDT 24
Peak memory 213284 kb
Host smart-903cb107-feb4-4d36-9ab1-38030c69f549
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750102756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2750102756
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1573810322
Short name T385
Test name
Test status
Simulation time 704444995 ps
CPU time 3.7 seconds
Started Jul 25 04:49:23 PM PDT 24
Finished Jul 25 04:49:27 PM PDT 24
Peak memory 221428 kb
Host smart-ec403643-8dfb-4b61-b2b4-83b735e12956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573810322 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1573810322
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.3257890809
Short name T389
Test name
Test status
Simulation time 30393914875 ps
CPU time 28.39 seconds
Started Jul 25 04:49:24 PM PDT 24
Finished Jul 25 04:49:52 PM PDT 24
Peak memory 204912 kb
Host smart-7bf95d9c-851b-4ff0-9fe6-4b44fafe7623
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257890809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.3257890809
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1299858554
Short name T402
Test name
Test status
Simulation time 4466004835 ps
CPU time 4.89 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:30 PM PDT 24
Peak memory 205016 kb
Host smart-c5fe18f9-2821-4750-a2c0-04aaee72cbd0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299858554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1299858554
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2447263368
Short name T88
Test name
Test status
Simulation time 9554089146 ps
CPU time 8.64 seconds
Started Jul 25 04:49:24 PM PDT 24
Finished Jul 25 04:49:33 PM PDT 24
Peak memory 205024 kb
Host smart-68b5dc31-c26d-464f-b1f0-8b7aa2c5b8fc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447263368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2447263368
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.971938827
Short name T433
Test name
Test status
Simulation time 3129799456 ps
CPU time 6.34 seconds
Started Jul 25 04:49:32 PM PDT 24
Finished Jul 25 04:49:38 PM PDT 24
Peak memory 204932 kb
Host smart-bc06f6b8-a296-46e1-a54a-9ba3d8ab6a19
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971938827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.971938827
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.3928482576
Short name T387
Test name
Test status
Simulation time 416009541 ps
CPU time 1.3 seconds
Started Jul 25 04:49:30 PM PDT 24
Finished Jul 25 04:49:32 PM PDT 24
Peak memory 204796 kb
Host smart-ff131d7e-3b75-4e7c-a6b9-e4816ff33539
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928482576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.3928482576
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.2939530860
Short name T365
Test name
Test status
Simulation time 28665489616 ps
CPU time 19.61 seconds
Started Jul 25 04:49:23 PM PDT 24
Finished Jul 25 04:49:43 PM PDT 24
Peak memory 204956 kb
Host smart-2dc7abfb-43fb-4ad7-ad9d-b76a07e75870
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939530860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.2939530860
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.1103146739
Short name T317
Test name
Test status
Simulation time 160254551 ps
CPU time 1.06 seconds
Started Jul 25 04:49:17 PM PDT 24
Finished Jul 25 04:49:18 PM PDT 24
Peak memory 204728 kb
Host smart-79af2b36-e971-4e42-ab60-424e7963d7a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103146739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.1103146739
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1717695421
Short name T414
Test name
Test status
Simulation time 155510448 ps
CPU time 1.13 seconds
Started Jul 25 04:49:23 PM PDT 24
Finished Jul 25 04:49:24 PM PDT 24
Peak memory 204760 kb
Host smart-1931c625-7d09-4a7d-b468-9de3c0b3a46b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717695421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
717695421
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.533707352
Short name T422
Test name
Test status
Simulation time 97895700 ps
CPU time 0.74 seconds
Started Jul 25 04:49:26 PM PDT 24
Finished Jul 25 04:49:27 PM PDT 24
Peak memory 204760 kb
Host smart-1d480364-0545-48a2-a64e-c3463d03baa3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533707352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.533707352
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2917670644
Short name T300
Test name
Test status
Simulation time 40016513 ps
CPU time 0.81 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:26 PM PDT 24
Peak memory 204744 kb
Host smart-ccad62c7-6d8a-433e-a3ad-74dacc84a74e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917670644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2917670644
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1678467590
Short name T431
Test name
Test status
Simulation time 682838813 ps
CPU time 4.45 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:29 PM PDT 24
Peak memory 204964 kb
Host smart-90cbb79b-60c1-4301-8f8b-27aeaac010ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678467590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1678467590
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.3410733193
Short name T444
Test name
Test status
Simulation time 30852822480 ps
CPU time 79.1 seconds
Started Jul 25 04:49:22 PM PDT 24
Finished Jul 25 04:50:41 PM PDT 24
Peak memory 221380 kb
Host smart-409a4c89-369e-4982-bde1-71f6ef311b33
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410733193 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.3410733193
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1420402747
Short name T326
Test name
Test status
Simulation time 505094027 ps
CPU time 4.39 seconds
Started Jul 25 04:49:28 PM PDT 24
Finished Jul 25 04:49:33 PM PDT 24
Peak memory 213224 kb
Host smart-54984056-e6b3-44a0-84cd-a4b4605f115e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420402747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1420402747
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2492631374
Short name T441
Test name
Test status
Simulation time 1180367019 ps
CPU time 10.76 seconds
Started Jul 25 04:49:22 PM PDT 24
Finished Jul 25 04:49:33 PM PDT 24
Peak memory 213192 kb
Host smart-0f4eb910-7e37-46e4-8cc6-33275a3dbc3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492631374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2492631374
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.495650571
Short name T316
Test name
Test status
Simulation time 2209228753 ps
CPU time 25.99 seconds
Started Jul 25 04:49:34 PM PDT 24
Finished Jul 25 04:50:00 PM PDT 24
Peak memory 205060 kb
Host smart-a3ba2431-3141-40ea-9bb3-b189a6509514
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495650571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.495650571
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1924090521
Short name T110
Test name
Test status
Simulation time 1450298349 ps
CPU time 54.71 seconds
Started Jul 25 04:49:31 PM PDT 24
Finished Jul 25 04:50:26 PM PDT 24
Peak memory 204988 kb
Host smart-a0c51480-d41d-47a6-b06b-d13f797671bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924090521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1924090521
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1684767157
Short name T75
Test name
Test status
Simulation time 116940478 ps
CPU time 1.94 seconds
Started Jul 25 04:49:23 PM PDT 24
Finished Jul 25 04:49:26 PM PDT 24
Peak memory 213228 kb
Host smart-c56fab57-923e-49ef-a9fe-4673e236de0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684767157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1684767157
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1651248610
Short name T424
Test name
Test status
Simulation time 62199801 ps
CPU time 2.45 seconds
Started Jul 25 04:49:50 PM PDT 24
Finished Jul 25 04:49:52 PM PDT 24
Peak memory 213164 kb
Host smart-16bf184b-0431-440e-a14e-61b95fcd8385
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651248610 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1651248610
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.950155059
Short name T77
Test name
Test status
Simulation time 180535105 ps
CPU time 1.6 seconds
Started Jul 25 04:49:34 PM PDT 24
Finished Jul 25 04:49:35 PM PDT 24
Peak memory 213164 kb
Host smart-ac4c7ab0-d893-40e4-a8c9-aa5744749bd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950155059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.950155059
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2124987045
Short name T293
Test name
Test status
Simulation time 39677415924 ps
CPU time 40.09 seconds
Started Jul 25 04:49:23 PM PDT 24
Finished Jul 25 04:50:03 PM PDT 24
Peak memory 204868 kb
Host smart-7f48e178-3fad-4727-a890-0e3538443e48
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124987045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2124987045
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3275314174
Short name T411
Test name
Test status
Simulation time 3512441494 ps
CPU time 5.78 seconds
Started Jul 25 04:49:35 PM PDT 24
Finished Jul 25 04:49:41 PM PDT 24
Peak memory 204952 kb
Host smart-bdde51df-a537-44d6-b526-69043c895d70
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275314174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.3275314174
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4048608526
Short name T86
Test name
Test status
Simulation time 8626324673 ps
CPU time 24.44 seconds
Started Jul 25 04:49:24 PM PDT 24
Finished Jul 25 04:49:48 PM PDT 24
Peak memory 205080 kb
Host smart-9306c4e4-aaad-49ab-ba44-afdce99291ec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048608526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.4048608526
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1348998004
Short name T413
Test name
Test status
Simulation time 2497945846 ps
CPU time 2.76 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:28 PM PDT 24
Peak memory 205028 kb
Host smart-402a6906-8936-46d8-9b40-7e64801bc518
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348998004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
348998004
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.719263238
Short name T393
Test name
Test status
Simulation time 205883706 ps
CPU time 0.75 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:25 PM PDT 24
Peak memory 204716 kb
Host smart-cf25ee9d-059b-46f8-a9b6-3e891b842ff6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719263238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.719263238
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.922545240
Short name T64
Test name
Test status
Simulation time 11709706395 ps
CPU time 4.53 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:30 PM PDT 24
Peak memory 205084 kb
Host smart-77c148e5-7bc0-495d-b178-1a429d0b3a8c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922545240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.922545240
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.313378004
Short name T439
Test name
Test status
Simulation time 431091718 ps
CPU time 1.25 seconds
Started Jul 25 04:49:34 PM PDT 24
Finished Jul 25 04:49:36 PM PDT 24
Peak memory 204740 kb
Host smart-e332dc55-4e49-47fd-ace8-a7c8dc502075
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313378004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.313378004
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2446532673
Short name T359
Test name
Test status
Simulation time 341716134 ps
CPU time 1.19 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:27 PM PDT 24
Peak memory 204796 kb
Host smart-22f50fa2-c2ae-4c46-908d-06505d26fd26
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446532673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
446532673
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3518567073
Short name T348
Test name
Test status
Simulation time 45650197 ps
CPU time 0.68 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:26 PM PDT 24
Peak memory 204648 kb
Host smart-811fbe9c-ea6f-49c0-8919-7b7fcc845c35
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518567073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3518567073
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1019526778
Short name T435
Test name
Test status
Simulation time 64314681 ps
CPU time 0.7 seconds
Started Jul 25 04:49:20 PM PDT 24
Finished Jul 25 04:49:21 PM PDT 24
Peak memory 204800 kb
Host smart-a9fe8905-b278-45c8-b035-fecbe170c70b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019526778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1019526778
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.4283242898
Short name T345
Test name
Test status
Simulation time 938138721 ps
CPU time 4.11 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:29 PM PDT 24
Peak memory 205012 kb
Host smart-64d8f136-fe33-4e1d-b415-2be4f277fa97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283242898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.4283242898
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.837623960
Short name T363
Test name
Test status
Simulation time 67275929307 ps
CPU time 106.88 seconds
Started Jul 25 04:49:30 PM PDT 24
Finished Jul 25 04:51:17 PM PDT 24
Peak memory 223472 kb
Host smart-a55ec69a-be6c-4f6b-b779-0d4be6592529
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837623960 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.837623960
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2270013372
Short name T335
Test name
Test status
Simulation time 378566987 ps
CPU time 2.5 seconds
Started Jul 25 04:49:28 PM PDT 24
Finished Jul 25 04:49:31 PM PDT 24
Peak memory 213308 kb
Host smart-506a9b65-0b85-4b2b-80e6-0ab8a7295631
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270013372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2270013372
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.4069115632
Short name T91
Test name
Test status
Simulation time 3303488822 ps
CPU time 30.69 seconds
Started Jul 25 04:49:27 PM PDT 24
Finished Jul 25 04:49:58 PM PDT 24
Peak memory 205112 kb
Host smart-d154dd02-39fd-4536-b93c-a9dc0186922e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069115632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.4069115632
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1331374078
Short name T355
Test name
Test status
Simulation time 25269431982 ps
CPU time 77.46 seconds
Started Jul 25 04:49:39 PM PDT 24
Finished Jul 25 04:50:56 PM PDT 24
Peak memory 205040 kb
Host smart-20226d7c-e2f8-4f2f-9188-3fcc51fcb63d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331374078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1331374078
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1529414442
Short name T106
Test name
Test status
Simulation time 232357568 ps
CPU time 2.8 seconds
Started Jul 25 04:49:23 PM PDT 24
Finished Jul 25 04:49:26 PM PDT 24
Peak memory 213416 kb
Host smart-0fcdd4c4-f3c9-4d15-899a-fd446df5cf3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529414442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1529414442
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1797003816
Short name T356
Test name
Test status
Simulation time 396039989 ps
CPU time 3.95 seconds
Started Jul 25 04:49:24 PM PDT 24
Finished Jul 25 04:49:28 PM PDT 24
Peak memory 221388 kb
Host smart-f1654fa4-5815-4b0d-8388-7bfc0bb5d2d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797003816 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1797003816
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2588295400
Short name T92
Test name
Test status
Simulation time 409583938 ps
CPU time 1.59 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:27 PM PDT 24
Peak memory 213176 kb
Host smart-3b68dd7e-a3b5-4a99-bf85-09f62ace2bd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588295400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2588295400
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2770084786
Short name T412
Test name
Test status
Simulation time 162581261113 ps
CPU time 463.49 seconds
Started Jul 25 04:49:32 PM PDT 24
Finished Jul 25 04:57:15 PM PDT 24
Peak memory 206664 kb
Host smart-9eec825c-7c29-472e-837a-d80ab87cac23
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770084786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2770084786
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1501149672
Short name T323
Test name
Test status
Simulation time 23853536871 ps
CPU time 22.73 seconds
Started Jul 25 04:49:34 PM PDT 24
Finished Jul 25 04:49:57 PM PDT 24
Peak memory 205016 kb
Host smart-6e9caf32-9e7a-4964-afed-a83b02278b7d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501149672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.1501149672
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4154343506
Short name T87
Test name
Test status
Simulation time 4131784269 ps
CPU time 2.02 seconds
Started Jul 25 04:49:28 PM PDT 24
Finished Jul 25 04:49:30 PM PDT 24
Peak memory 205004 kb
Host smart-60b88bb2-6a5d-494d-a822-7be84d3b3861
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154343506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.4154343506
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.589153655
Short name T305
Test name
Test status
Simulation time 4637441818 ps
CPU time 4.1 seconds
Started Jul 25 04:49:24 PM PDT 24
Finished Jul 25 04:49:28 PM PDT 24
Peak memory 204968 kb
Host smart-b5751489-9001-4751-836b-133232b36369
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589153655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.589153655
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1762822549
Short name T398
Test name
Test status
Simulation time 553182637 ps
CPU time 2.25 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:27 PM PDT 24
Peak memory 204792 kb
Host smart-63f312e2-3d9a-4e7d-9441-a36ced637ce5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762822549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1762822549
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.521891345
Short name T315
Test name
Test status
Simulation time 7032114429 ps
CPU time 7.11 seconds
Started Jul 25 04:49:39 PM PDT 24
Finished Jul 25 04:49:47 PM PDT 24
Peak memory 205028 kb
Host smart-eddc9815-2007-4f47-986b-470f6ac979a7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521891345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.521891345
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1193856140
Short name T434
Test name
Test status
Simulation time 213948622 ps
CPU time 0.76 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:26 PM PDT 24
Peak memory 204780 kb
Host smart-230a45f8-f363-4d46-b7e9-bb7105b997ac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193856140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1193856140
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.3212017540
Short name T65
Test name
Test status
Simulation time 314519335 ps
CPU time 1.02 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:26 PM PDT 24
Peak memory 204748 kb
Host smart-b472a1ef-3612-4ef2-aa8b-a0ec3d088c15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212017540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.3
212017540
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.427736198
Short name T392
Test name
Test status
Simulation time 40032960 ps
CPU time 0.77 seconds
Started Jul 25 04:49:24 PM PDT 24
Finished Jul 25 04:49:25 PM PDT 24
Peak memory 204804 kb
Host smart-f1e6777c-e78a-4479-8171-342c59562ae3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427736198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.427736198
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.881623456
Short name T306
Test name
Test status
Simulation time 124211394 ps
CPU time 0.99 seconds
Started Jul 25 04:49:27 PM PDT 24
Finished Jul 25 04:49:29 PM PDT 24
Peak memory 204736 kb
Host smart-b84eb070-5e12-494c-835d-fa8080c6d764
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881623456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.881623456
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3672318433
Short name T115
Test name
Test status
Simulation time 174558390 ps
CPU time 6.65 seconds
Started Jul 25 04:49:24 PM PDT 24
Finished Jul 25 04:49:30 PM PDT 24
Peak memory 204928 kb
Host smart-137c2610-e1ef-449c-abd3-80da9d235605
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672318433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3672318433
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2367365455
Short name T170
Test name
Test status
Simulation time 37598334529 ps
CPU time 99.07 seconds
Started Jul 25 04:49:36 PM PDT 24
Finished Jul 25 04:51:15 PM PDT 24
Peak memory 221304 kb
Host smart-33b42ea9-01a1-48f6-a705-c801f42291f1
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367365455 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2367365455
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2156583133
Short name T339
Test name
Test status
Simulation time 49277381 ps
CPU time 2.27 seconds
Started Jul 25 04:49:37 PM PDT 24
Finished Jul 25 04:49:39 PM PDT 24
Peak memory 213168 kb
Host smart-9eb75b61-84ee-4968-a867-db9ca8e55a38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156583133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2156583133
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.736838835
Short name T168
Test name
Test status
Simulation time 4122671037 ps
CPU time 19.21 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:45 PM PDT 24
Peak memory 213332 kb
Host smart-f82f6c14-c922-4b7f-9cfb-66b4669a835a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736838835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.736838835
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.38226700
Short name T436
Test name
Test status
Simulation time 109726897 ps
CPU time 2.38 seconds
Started Jul 25 04:49:27 PM PDT 24
Finished Jul 25 04:49:30 PM PDT 24
Peak memory 213204 kb
Host smart-e7f2d3a7-ac5a-43f0-9af1-68f7f57f67a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38226700 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.38226700
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.483996514
Short name T320
Test name
Test status
Simulation time 679252296 ps
CPU time 1.67 seconds
Started Jul 25 04:49:24 PM PDT 24
Finished Jul 25 04:49:26 PM PDT 24
Peak memory 213244 kb
Host smart-8e26c3fe-1852-4eb0-be39-f1d9c7ee3642
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483996514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.483996514
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.3103586086
Short name T347
Test name
Test status
Simulation time 18025261634 ps
CPU time 31.4 seconds
Started Jul 25 04:49:24 PM PDT 24
Finished Jul 25 04:49:56 PM PDT 24
Peak memory 204956 kb
Host smart-a5b26b66-ec7a-45ba-b7f2-9ee1a1e88d8a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103586086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.3103586086
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.3730741968
Short name T303
Test name
Test status
Simulation time 13992438439 ps
CPU time 20.57 seconds
Started Jul 25 04:49:27 PM PDT 24
Finished Jul 25 04:49:48 PM PDT 24
Peak memory 204968 kb
Host smart-308c2110-f866-407b-a7c1-d17261690e32
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730741968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.3
730741968
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2364456656
Short name T423
Test name
Test status
Simulation time 608454557 ps
CPU time 1.06 seconds
Started Jul 25 04:49:50 PM PDT 24
Finished Jul 25 04:49:51 PM PDT 24
Peak memory 204820 kb
Host smart-8716b63d-12cc-40ab-ad5f-4427ffaaafc5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364456656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
364456656
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3349963460
Short name T100
Test name
Test status
Simulation time 489595502 ps
CPU time 8 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:33 PM PDT 24
Peak memory 205012 kb
Host smart-7c30cb92-ca5d-40a1-bcd7-6062d2bf317b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349963460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3349963460
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.423581471
Short name T352
Test name
Test status
Simulation time 54460639721 ps
CPU time 77.8 seconds
Started Jul 25 04:49:26 PM PDT 24
Finished Jul 25 04:50:44 PM PDT 24
Peak memory 221900 kb
Host smart-a4708d44-f1eb-4ab4-8529-0e287c3eadbe
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423581471 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.423581471
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1092106193
Short name T362
Test name
Test status
Simulation time 126471196 ps
CPU time 3.48 seconds
Started Jul 25 04:49:23 PM PDT 24
Finished Jul 25 04:49:27 PM PDT 24
Peak memory 213244 kb
Host smart-de744375-0ab7-45c1-b5a7-2b3e400710ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092106193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1092106193
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1191745143
Short name T332
Test name
Test status
Simulation time 1867791026 ps
CPU time 19.62 seconds
Started Jul 25 04:49:32 PM PDT 24
Finished Jul 25 04:49:51 PM PDT 24
Peak memory 213144 kb
Host smart-a2ccbc56-0cc0-4c81-b6e5-38e5fd17bcd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191745143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1191745143
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2318016498
Short name T399
Test name
Test status
Simulation time 849592614 ps
CPU time 4.34 seconds
Started Jul 25 04:49:24 PM PDT 24
Finished Jul 25 04:49:28 PM PDT 24
Peak memory 219208 kb
Host smart-87a4c30e-83fd-4880-ab3a-eb52d2c3c698
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318016498 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2318016498
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.2240456883
Short name T324
Test name
Test status
Simulation time 232135711 ps
CPU time 1.57 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:27 PM PDT 24
Peak memory 213212 kb
Host smart-c4ff2f40-5b55-4262-a00b-0a15d5bbfbf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240456883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.2240456883
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.479915711
Short name T318
Test name
Test status
Simulation time 3327341183 ps
CPU time 2.32 seconds
Started Jul 25 04:49:55 PM PDT 24
Finished Jul 25 04:49:57 PM PDT 24
Peak memory 205020 kb
Host smart-bc622fc6-b452-4ffd-84ba-a0ed228454b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479915711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
v_dm_jtag_dmi_csr_bit_bash.479915711
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3696247533
Short name T421
Test name
Test status
Simulation time 4152925615 ps
CPU time 7.24 seconds
Started Jul 25 04:49:22 PM PDT 24
Finished Jul 25 04:49:29 PM PDT 24
Peak memory 204988 kb
Host smart-04569c16-5dae-41ae-a9aa-7894c8f6a883
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696247533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
696247533
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.509965142
Short name T364
Test name
Test status
Simulation time 281310226 ps
CPU time 0.77 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:26 PM PDT 24
Peak memory 204752 kb
Host smart-c175a127-1db2-4ca7-b35f-9f7cea976769
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509965142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.509965142
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3741747000
Short name T82
Test name
Test status
Simulation time 1705534011 ps
CPU time 7.7 seconds
Started Jul 25 04:49:23 PM PDT 24
Finished Jul 25 04:49:31 PM PDT 24
Peak memory 204936 kb
Host smart-c6a0ddd9-34b4-4903-87bb-031e319f814d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741747000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3741747000
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.3426900684
Short name T61
Test name
Test status
Simulation time 53954283606 ps
CPU time 392.66 seconds
Started Jul 25 04:49:24 PM PDT 24
Finished Jul 25 04:55:57 PM PDT 24
Peak memory 221232 kb
Host smart-512dc4a3-eda7-4e45-9fea-db8cd979ad44
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426900684 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.3426900684
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3246948652
Short name T371
Test name
Test status
Simulation time 104029366 ps
CPU time 2.59 seconds
Started Jul 25 04:49:30 PM PDT 24
Finished Jul 25 04:49:33 PM PDT 24
Peak memory 213264 kb
Host smart-590814c0-9b43-4164-a7ba-a9156dc33d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246948652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3246948652
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2586918351
Short name T165
Test name
Test status
Simulation time 2008569550 ps
CPU time 21.95 seconds
Started Jul 25 04:49:24 PM PDT 24
Finished Jul 25 04:49:47 PM PDT 24
Peak memory 213204 kb
Host smart-267880bb-2b50-4db2-ae36-b95aa9f26db6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586918351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2586918351
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.1881853593
Short name T84
Test name
Test status
Simulation time 934858850 ps
CPU time 3.88 seconds
Started Jul 25 04:49:41 PM PDT 24
Finished Jul 25 04:49:45 PM PDT 24
Peak memory 221324 kb
Host smart-ad62f3d7-204c-4581-b53b-c25c40cb3076
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881853593 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.1881853593
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.88445146
Short name T93
Test name
Test status
Simulation time 118460199 ps
CPU time 1.68 seconds
Started Jul 25 04:49:39 PM PDT 24
Finished Jul 25 04:49:41 PM PDT 24
Peak memory 213216 kb
Host smart-5dc115ec-00a3-4c5a-bad7-b31c60fe08bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88445146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.88445146
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1133025553
Short name T428
Test name
Test status
Simulation time 2061709459 ps
CPU time 3.13 seconds
Started Jul 25 04:50:07 PM PDT 24
Finished Jul 25 04:50:10 PM PDT 24
Peak memory 204920 kb
Host smart-bedf2403-46e3-4e26-8b73-960dcffe07a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133025553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.1133025553
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3647747705
Short name T341
Test name
Test status
Simulation time 2810241419 ps
CPU time 2.86 seconds
Started Jul 25 04:50:00 PM PDT 24
Finished Jul 25 04:50:03 PM PDT 24
Peak memory 205024 kb
Host smart-289eea92-9de1-4b39-8a57-f25f2f28456d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647747705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
647747705
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1839492108
Short name T382
Test name
Test status
Simulation time 274464864 ps
CPU time 0.92 seconds
Started Jul 25 04:49:25 PM PDT 24
Finished Jul 25 04:49:26 PM PDT 24
Peak memory 204740 kb
Host smart-fb735585-0a6e-4539-81c1-d182108ddcb3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839492108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
839492108
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3548240949
Short name T96
Test name
Test status
Simulation time 194371068 ps
CPU time 6.33 seconds
Started Jul 25 04:49:42 PM PDT 24
Finished Jul 25 04:49:48 PM PDT 24
Peak memory 205084 kb
Host smart-5e9efa1d-aa3b-455c-8b9a-fef27e1eca49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548240949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3548240949
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3206921476
Short name T296
Test name
Test status
Simulation time 873644851 ps
CPU time 4.5 seconds
Started Jul 25 04:50:01 PM PDT 24
Finished Jul 25 04:50:05 PM PDT 24
Peak memory 213312 kb
Host smart-ff061b5c-ef57-48ab-9130-e77d77df0eee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206921476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3206921476
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.612042100
Short name T388
Test name
Test status
Simulation time 634040599 ps
CPU time 8.53 seconds
Started Jul 25 04:49:43 PM PDT 24
Finished Jul 25 04:49:52 PM PDT 24
Peak memory 213160 kb
Host smart-b5fb0890-6d89-4abe-9b2f-bd3b7b3136b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612042100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.612042100
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.850398347
Short name T372
Test name
Test status
Simulation time 407054210 ps
CPU time 2.59 seconds
Started Jul 25 04:49:38 PM PDT 24
Finished Jul 25 04:49:41 PM PDT 24
Peak memory 217324 kb
Host smart-5c075b7d-7273-4a6b-9cb4-9ec388a4b5fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850398347 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.850398347
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3594529514
Short name T104
Test name
Test status
Simulation time 467127398 ps
CPU time 1.74 seconds
Started Jul 25 04:49:34 PM PDT 24
Finished Jul 25 04:49:36 PM PDT 24
Peak memory 213200 kb
Host smart-032d4d2f-86f0-4233-a22b-812ac0b91852
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594529514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3594529514
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.3286718184
Short name T406
Test name
Test status
Simulation time 3292262981 ps
CPU time 9.26 seconds
Started Jul 25 04:49:50 PM PDT 24
Finished Jul 25 04:50:04 PM PDT 24
Peak memory 204976 kb
Host smart-22c11652-8a49-4a78-a0fa-df78fb485394
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286718184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.3286718184
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.501714594
Short name T307
Test name
Test status
Simulation time 2346996937 ps
CPU time 8.14 seconds
Started Jul 25 04:49:42 PM PDT 24
Finished Jul 25 04:49:50 PM PDT 24
Peak memory 205020 kb
Host smart-f1d8be8c-febd-4ac9-b5ed-dd4cf430aafa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501714594 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.501714594
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.676513183
Short name T338
Test name
Test status
Simulation time 228993249 ps
CPU time 1.27 seconds
Started Jul 25 04:49:39 PM PDT 24
Finished Jul 25 04:49:41 PM PDT 24
Peak memory 204748 kb
Host smart-db12bd73-3c61-45ad-a4a1-679343cf5b90
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676513183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.676513183
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.685113660
Short name T83
Test name
Test status
Simulation time 1746852177 ps
CPU time 6.7 seconds
Started Jul 25 04:49:39 PM PDT 24
Finished Jul 25 04:49:46 PM PDT 24
Peak memory 205016 kb
Host smart-d1ad965b-ad8a-49be-a543-dd590b6ed41d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685113660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.685113660
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1702570228
Short name T334
Test name
Test status
Simulation time 31813915885 ps
CPU time 108.17 seconds
Started Jul 25 04:50:01 PM PDT 24
Finished Jul 25 04:51:50 PM PDT 24
Peak memory 221400 kb
Host smart-4e300179-c27b-412d-9121-c158f5f3bdc7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702570228 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1702570228
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.3949052877
Short name T405
Test name
Test status
Simulation time 120387326 ps
CPU time 4.55 seconds
Started Jul 25 04:49:37 PM PDT 24
Finished Jul 25 04:49:41 PM PDT 24
Peak memory 213156 kb
Host smart-42ed8a77-285a-4429-83ac-fefe1e6f1d08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949052877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.3949052877
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1856577432
Short name T162
Test name
Test status
Simulation time 1768710275 ps
CPU time 11.18 seconds
Started Jul 25 04:49:40 PM PDT 24
Finished Jul 25 04:49:51 PM PDT 24
Peak memory 213196 kb
Host smart-72d2aa3a-5f5f-4460-b456-61c357ec8221
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856577432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1856577432
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4253900848
Short name T358
Test name
Test status
Simulation time 350797525 ps
CPU time 4.81 seconds
Started Jul 25 04:49:52 PM PDT 24
Finished Jul 25 04:49:57 PM PDT 24
Peak memory 221176 kb
Host smart-b8b1dc1a-85c0-4674-b146-3c8e5e292e61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253900848 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.4253900848
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2132502478
Short name T79
Test name
Test status
Simulation time 255841804 ps
CPU time 1.66 seconds
Started Jul 25 04:49:55 PM PDT 24
Finished Jul 25 04:49:56 PM PDT 24
Peak memory 213204 kb
Host smart-cb29e9fc-4e54-4b9c-9ddd-92a657cd146b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132502478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2132502478
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.3766241948
Short name T367
Test name
Test status
Simulation time 120477397 ps
CPU time 1.04 seconds
Started Jul 25 04:49:49 PM PDT 24
Finished Jul 25 04:49:51 PM PDT 24
Peak memory 204788 kb
Host smart-d244297a-2aad-4db9-9b50-99b6c5779e66
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766241948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.3766241948
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2455357794
Short name T298
Test name
Test status
Simulation time 5151222167 ps
CPU time 9.6 seconds
Started Jul 25 04:49:38 PM PDT 24
Finished Jul 25 04:49:48 PM PDT 24
Peak memory 204900 kb
Host smart-b57fe526-e4c0-4d7b-8d0e-2fe51c7df85c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455357794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
455357794
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3313024387
Short name T409
Test name
Test status
Simulation time 915460470 ps
CPU time 2.65 seconds
Started Jul 25 04:49:39 PM PDT 24
Finished Jul 25 04:49:42 PM PDT 24
Peak memory 204736 kb
Host smart-41db9d5d-df0f-44c2-a0a7-9b7576aa3a81
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313024387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
313024387
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3017052155
Short name T113
Test name
Test status
Simulation time 1196156246 ps
CPU time 4.73 seconds
Started Jul 25 04:49:49 PM PDT 24
Finished Jul 25 04:49:54 PM PDT 24
Peak memory 204952 kb
Host smart-31e30a2f-83aa-46ff-ab9d-b6f9bec9183a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017052155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3017052155
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2959720331
Short name T169
Test name
Test status
Simulation time 25733455517 ps
CPU time 32.86 seconds
Started Jul 25 04:49:52 PM PDT 24
Finished Jul 25 04:50:25 PM PDT 24
Peak memory 221376 kb
Host smart-0d6afecb-5b2d-47ca-9ad2-5aa5d34e6a2c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959720331 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2959720331
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1729211495
Short name T361
Test name
Test status
Simulation time 423739341 ps
CPU time 6.23 seconds
Started Jul 25 04:49:38 PM PDT 24
Finished Jul 25 04:49:45 PM PDT 24
Peak memory 213204 kb
Host smart-fe26989a-74ba-46d6-9515-fc3dbd339393
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729211495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1729211495
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.157741663
Short name T163
Test name
Test status
Simulation time 7035168360 ps
CPU time 22.76 seconds
Started Jul 25 04:49:50 PM PDT 24
Finished Jul 25 04:50:13 PM PDT 24
Peak memory 213236 kb
Host smart-3fab759b-3453-4c36-9cc0-b97c1a68b5f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157741663 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.157741663
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.678697457
Short name T36
Test name
Test status
Simulation time 106235193 ps
CPU time 0.81 seconds
Started Jul 25 04:49:54 PM PDT 24
Finished Jul 25 04:49:55 PM PDT 24
Peak memory 204836 kb
Host smart-65eadb2a-8249-4d5b-880b-b94286d2baa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678697457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.678697457
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.816072635
Short name T210
Test name
Test status
Simulation time 54097899 ps
CPU time 0.78 seconds
Started Jul 25 04:50:09 PM PDT 24
Finished Jul 25 04:50:10 PM PDT 24
Peak memory 205024 kb
Host smart-5b4d6b56-097c-4de7-8bdf-43755d6bb12c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816072635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.816072635
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2994098662
Short name T187
Test name
Test status
Simulation time 16968461292 ps
CPU time 28.93 seconds
Started Jul 25 04:49:50 PM PDT 24
Finished Jul 25 04:50:20 PM PDT 24
Peak memory 221616 kb
Host smart-6796a814-5728-48aa-8583-d78c6ea523d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994098662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2994098662
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3155425906
Short name T17
Test name
Test status
Simulation time 720910100 ps
CPU time 0.83 seconds
Started Jul 25 04:50:06 PM PDT 24
Finished Jul 25 04:50:07 PM PDT 24
Peak memory 204980 kb
Host smart-fb83edb4-1cf7-4018-a5db-c803872e3da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155425906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3155425906
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.4167137792
Short name T155
Test name
Test status
Simulation time 193022742 ps
CPU time 0.96 seconds
Started Jul 25 04:50:07 PM PDT 24
Finished Jul 25 04:50:08 PM PDT 24
Peak memory 204888 kb
Host smart-480a314f-c278-43b1-8b63-de6a2c0a68e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167137792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.4167137792
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.1638051240
Short name T53
Test name
Test status
Simulation time 44044178 ps
CPU time 0.84 seconds
Started Jul 25 04:49:53 PM PDT 24
Finished Jul 25 04:49:54 PM PDT 24
Peak memory 215076 kb
Host smart-5bcd4b9a-e7ed-4e4c-88b7-ec3f9d9ac0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638051240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.1638051240
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.4030614001
Short name T289
Test name
Test status
Simulation time 11998254453 ps
CPU time 19 seconds
Started Jul 25 04:49:48 PM PDT 24
Finished Jul 25 04:50:08 PM PDT 24
Peak memory 213548 kb
Host smart-c00135b6-9bf5-4fe8-bfc2-1cd4fe9d86e1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4030614001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.4030614001
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2268376054
Short name T51
Test name
Test status
Simulation time 488627892 ps
CPU time 2.1 seconds
Started Jul 25 04:50:09 PM PDT 24
Finished Jul 25 04:50:11 PM PDT 24
Peak memory 204900 kb
Host smart-33927c6a-5ba0-41a3-8ae0-22395fbbeee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268376054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2268376054
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1146348567
Short name T189
Test name
Test status
Simulation time 395694347 ps
CPU time 1.14 seconds
Started Jul 25 04:49:54 PM PDT 24
Finished Jul 25 04:49:55 PM PDT 24
Peak memory 204832 kb
Host smart-9e846ad9-5231-4529-9d45-b23a24c8c6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146348567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1146348567
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.421036426
Short name T194
Test name
Test status
Simulation time 537469002 ps
CPU time 2.15 seconds
Started Jul 25 04:49:51 PM PDT 24
Finished Jul 25 04:49:54 PM PDT 24
Peak memory 204872 kb
Host smart-d28461da-d563-42b1-a3e7-78dc1cdfa421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421036426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.421036426
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.702013160
Short name T284
Test name
Test status
Simulation time 2520659302 ps
CPU time 7.3 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:19 PM PDT 24
Peak memory 204968 kb
Host smart-1af1cf13-5b0d-497b-9475-28e825c18fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702013160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.702013160
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.594966877
Short name T144
Test name
Test status
Simulation time 645137816 ps
CPU time 2.31 seconds
Started Jul 25 04:49:57 PM PDT 24
Finished Jul 25 04:50:00 PM PDT 24
Peak memory 204872 kb
Host smart-ab5719e0-de4d-4a03-acb9-b1ad0f23b178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594966877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.594966877
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.1029661678
Short name T181
Test name
Test status
Simulation time 259768223 ps
CPU time 1.31 seconds
Started Jul 25 04:50:08 PM PDT 24
Finished Jul 25 04:50:10 PM PDT 24
Peak memory 204848 kb
Host smart-f45ba7cf-ca26-4609-8ea9-5b5630661c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029661678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.1029661678
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.462639421
Short name T290
Test name
Test status
Simulation time 439478391 ps
CPU time 1.33 seconds
Started Jul 25 04:50:09 PM PDT 24
Finished Jul 25 04:50:10 PM PDT 24
Peak memory 204876 kb
Host smart-517c049e-5f6e-4c15-a35f-ef6f3b35bc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462639421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.462639421
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1647627343
Short name T8
Test name
Test status
Simulation time 1233657277 ps
CPU time 4.03 seconds
Started Jul 25 04:49:48 PM PDT 24
Finished Jul 25 04:49:52 PM PDT 24
Peak memory 204840 kb
Host smart-3ae2546e-3495-40e5-8f1a-44ab17537dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647627343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1647627343
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1822253547
Short name T208
Test name
Test status
Simulation time 726276956 ps
CPU time 2.51 seconds
Started Jul 25 04:49:49 PM PDT 24
Finished Jul 25 04:49:51 PM PDT 24
Peak memory 213192 kb
Host smart-a4e1e736-03da-4950-b06d-43950db374c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822253547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1822253547
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1315484978
Short name T146
Test name
Test status
Simulation time 338773586 ps
CPU time 1.54 seconds
Started Jul 25 04:50:01 PM PDT 24
Finished Jul 25 04:50:03 PM PDT 24
Peak memory 204932 kb
Host smart-246bb055-be80-403c-bd9b-22160e547ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315484978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1315484978
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.180783410
Short name T216
Test name
Test status
Simulation time 1450510029 ps
CPU time 1.94 seconds
Started Jul 25 04:49:48 PM PDT 24
Finished Jul 25 04:49:50 PM PDT 24
Peak memory 205336 kb
Host smart-bc01a038-8885-4aee-8df4-f0e8209ef919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180783410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.180783410
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3109862183
Short name T177
Test name
Test status
Simulation time 2994372140 ps
CPU time 2.97 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:14 PM PDT 24
Peak memory 205024 kb
Host smart-bedee04c-65f6-42ba-a9c2-26c0ddd99f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109862183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3109862183
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.894389910
Short name T141
Test name
Test status
Simulation time 10515608342 ps
CPU time 12.07 seconds
Started Jul 25 04:50:15 PM PDT 24
Finished Jul 25 04:50:27 PM PDT 24
Peak memory 205172 kb
Host smart-be2bfc08-72b4-4dc2-b847-29aab40afd5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894389910 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.894389910
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1486928012
Short name T3
Test name
Test status
Simulation time 9013959325 ps
CPU time 8.25 seconds
Started Jul 25 04:49:53 PM PDT 24
Finished Jul 25 04:50:01 PM PDT 24
Peak memory 205052 kb
Host smart-448c8d71-aad2-430f-836a-f60b75e98942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486928012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1486928012
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3932475556
Short name T59
Test name
Test status
Simulation time 72636083 ps
CPU time 0.7 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:14 PM PDT 24
Peak memory 205004 kb
Host smart-588d2137-0450-4048-a38a-f62e79f8484d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932475556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3932475556
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3627465257
Short name T254
Test name
Test status
Simulation time 537943774 ps
CPU time 2.03 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:14 PM PDT 24
Peak memory 204880 kb
Host smart-6adb65b2-5685-4fc7-8e76-f9f701ef9d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627465257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3627465257
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1260488065
Short name T21
Test name
Test status
Simulation time 859538680 ps
CPU time 1.3 seconds
Started Jul 25 04:50:10 PM PDT 24
Finished Jul 25 04:50:11 PM PDT 24
Peak memory 204972 kb
Host smart-d8c90a8b-cc23-4f6f-bbb0-6ee273360f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260488065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1260488065
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2862740725
Short name T31
Test name
Test status
Simulation time 1665345033 ps
CPU time 3.94 seconds
Started Jul 25 04:50:06 PM PDT 24
Finished Jul 25 04:50:10 PM PDT 24
Peak memory 204824 kb
Host smart-86236697-278c-4f48-9bb4-57921ddc45b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862740725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2862740725
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1795625180
Short name T191
Test name
Test status
Simulation time 139610165 ps
CPU time 0.85 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:14 PM PDT 24
Peak memory 204828 kb
Host smart-6f84478c-f2e0-4f0b-b931-6b59e789bc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795625180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1795625180
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1036615444
Short name T268
Test name
Test status
Simulation time 237987851 ps
CPU time 0.83 seconds
Started Jul 25 04:49:59 PM PDT 24
Finished Jul 25 04:50:00 PM PDT 24
Peak memory 204864 kb
Host smart-960f62a6-f63d-4059-87b5-0a951642d895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036615444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1036615444
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.3943144632
Short name T232
Test name
Test status
Simulation time 128909884 ps
CPU time 1.01 seconds
Started Jul 25 04:49:54 PM PDT 24
Finished Jul 25 04:49:55 PM PDT 24
Peak memory 215028 kb
Host smart-0e72b567-c632-4470-8411-b1bf7139e043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943144632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3943144632
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.3261317674
Short name T44
Test name
Test status
Simulation time 111634122 ps
CPU time 0.81 seconds
Started Jul 25 04:50:06 PM PDT 24
Finished Jul 25 04:50:06 PM PDT 24
Peak memory 204972 kb
Host smart-8b97a911-b15c-4d78-a03e-d9b0224c0b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261317674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3261317674
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.1137437734
Short name T247
Test name
Test status
Simulation time 498957820 ps
CPU time 1.09 seconds
Started Jul 25 04:49:47 PM PDT 24
Finished Jul 25 04:49:49 PM PDT 24
Peak memory 204972 kb
Host smart-51adc4a3-c217-4a51-9217-5c7e405839a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137437734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.1137437734
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3693805481
Short name T212
Test name
Test status
Simulation time 228232233 ps
CPU time 1.34 seconds
Started Jul 25 04:50:02 PM PDT 24
Finished Jul 25 04:50:03 PM PDT 24
Peak memory 204892 kb
Host smart-89cbe7a3-aa6a-488c-90b0-91d948e10805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693805481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3693805481
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3155033435
Short name T55
Test name
Test status
Simulation time 515918662 ps
CPU time 2.19 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:13 PM PDT 24
Peak memory 204968 kb
Host smart-85776a8f-a76b-4be2-8698-69e876ea4237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155033435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3155033435
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1922190820
Short name T280
Test name
Test status
Simulation time 1020255875 ps
CPU time 3.64 seconds
Started Jul 25 04:49:55 PM PDT 24
Finished Jul 25 04:49:58 PM PDT 24
Peak memory 204804 kb
Host smart-1f8bcb5f-7537-45d1-986b-d3e6ad91b333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922190820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1922190820
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3391102539
Short name T253
Test name
Test status
Simulation time 728659909 ps
CPU time 1.77 seconds
Started Jul 25 04:50:03 PM PDT 24
Finished Jul 25 04:50:04 PM PDT 24
Peak memory 204880 kb
Host smart-547899ec-a023-4c78-9496-092d2824fdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391102539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3391102539
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.118134829
Short name T285
Test name
Test status
Simulation time 599924770 ps
CPU time 1.5 seconds
Started Jul 25 04:49:50 PM PDT 24
Finished Jul 25 04:49:51 PM PDT 24
Peak memory 204868 kb
Host smart-1fd91406-6b86-4c9e-aff9-018a44223bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118134829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.118134829
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.849735318
Short name T222
Test name
Test status
Simulation time 404962674 ps
CPU time 1.04 seconds
Started Jul 25 04:49:48 PM PDT 24
Finished Jul 25 04:49:49 PM PDT 24
Peak memory 204976 kb
Host smart-2589d10a-2324-46c8-b63b-f1efd454c7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849735318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.849735318
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.921983129
Short name T134
Test name
Test status
Simulation time 1056480415 ps
CPU time 3.41 seconds
Started Jul 25 04:50:10 PM PDT 24
Finished Jul 25 04:50:13 PM PDT 24
Peak memory 204896 kb
Host smart-5e1f3642-3063-482c-a017-e8c2181a3d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921983129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.921983129
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.990811940
Short name T243
Test name
Test status
Simulation time 433133865 ps
CPU time 0.9 seconds
Started Jul 25 04:50:00 PM PDT 24
Finished Jul 25 04:50:01 PM PDT 24
Peak memory 213188 kb
Host smart-6431f579-80d8-48fb-b842-e45b4fa272cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990811940 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.990811940
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.1786917638
Short name T35
Test name
Test status
Simulation time 414298912 ps
CPU time 1.23 seconds
Started Jul 25 04:50:04 PM PDT 24
Finished Jul 25 04:50:05 PM PDT 24
Peak memory 204972 kb
Host smart-7f3a7b65-b14a-4f75-b4c3-1a076c9c4066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786917638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.1786917638
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.502534718
Short name T252
Test name
Test status
Simulation time 216384162 ps
CPU time 1.29 seconds
Started Jul 25 04:49:54 PM PDT 24
Finished Jul 25 04:49:56 PM PDT 24
Peak memory 204964 kb
Host smart-6dad0a56-4aa1-4a13-a27b-59b7129675f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502534718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.502534718
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3805912937
Short name T32
Test name
Test status
Simulation time 103308141 ps
CPU time 0.97 seconds
Started Jul 25 04:50:20 PM PDT 24
Finished Jul 25 04:50:22 PM PDT 24
Peak memory 213188 kb
Host smart-8c2e6e5e-628c-4835-8feb-c8ad1a8c0180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805912937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3805912937
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.3415803651
Short name T122
Test name
Test status
Simulation time 2276537643 ps
CPU time 6.35 seconds
Started Jul 25 04:49:56 PM PDT 24
Finished Jul 25 04:50:02 PM PDT 24
Peak memory 205108 kb
Host smart-a4f6b86d-6f83-4bf2-9a42-94e1148f48d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415803651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.3415803651
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.129529263
Short name T200
Test name
Test status
Simulation time 7550620239 ps
CPU time 19.35 seconds
Started Jul 25 04:49:47 PM PDT 24
Finished Jul 25 04:50:07 PM PDT 24
Peak memory 205280 kb
Host smart-7b27e6c3-e826-4a03-8d75-ff301268460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129529263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.129529263
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2989005335
Short name T43
Test name
Test status
Simulation time 972526568 ps
CPU time 1.26 seconds
Started Jul 25 04:50:10 PM PDT 24
Finished Jul 25 04:50:11 PM PDT 24
Peak memory 229280 kb
Host smart-fcd64706-cd29-46c4-b0e0-370861b49666
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989005335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2989005335
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.350060525
Short name T12
Test name
Test status
Simulation time 1835547829 ps
CPU time 6.17 seconds
Started Jul 25 04:50:02 PM PDT 24
Finished Jul 25 04:50:08 PM PDT 24
Peak memory 205044 kb
Host smart-1e1560ff-3dd7-4e22-bc6b-b90528f9a9c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350060525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.350060525
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.1085863751
Short name T14
Test name
Test status
Simulation time 209525141193 ps
CPU time 1186 seconds
Started Jul 25 04:49:49 PM PDT 24
Finished Jul 25 05:09:35 PM PDT 24
Peak memory 241680 kb
Host smart-836fbdac-f4a8-43dc-85c8-b02df7881274
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085863751 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.1085863751
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.414995285
Short name T250
Test name
Test status
Simulation time 125328425 ps
CPU time 0.77 seconds
Started Jul 25 04:50:17 PM PDT 24
Finished Jul 25 04:50:19 PM PDT 24
Peak memory 204924 kb
Host smart-2bcc8280-2448-4b88-8323-3d0ae35d670e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414995285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.414995285
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2301212930
Short name T27
Test name
Test status
Simulation time 40666612971 ps
CPU time 11.31 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:22 PM PDT 24
Peak memory 213468 kb
Host smart-d76f938a-fba0-411f-85b4-4e8f29b98b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301212930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2301212930
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.94611124
Short name T286
Test name
Test status
Simulation time 1548833241 ps
CPU time 3.46 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:17 PM PDT 24
Peak memory 213636 kb
Host smart-8be31f50-8b8d-409a-8e7d-42b961927e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94611124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.94611124
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1181701894
Short name T275
Test name
Test status
Simulation time 13158503727 ps
CPU time 11.02 seconds
Started Jul 25 04:50:05 PM PDT 24
Finished Jul 25 04:50:17 PM PDT 24
Peak memory 213532 kb
Host smart-b1168082-023a-4d05-a353-7b73fdf5b77f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1181701894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1181701894
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3231873821
Short name T215
Test name
Test status
Simulation time 3621758473 ps
CPU time 5.14 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:19 PM PDT 24
Peak memory 205568 kb
Host smart-c99e261a-8ea3-404a-a114-fa3e3952cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231873821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3231873821
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.166596963
Short name T244
Test name
Test status
Simulation time 136285009 ps
CPU time 0.85 seconds
Started Jul 25 04:50:22 PM PDT 24
Finished Jul 25 04:50:25 PM PDT 24
Peak memory 205024 kb
Host smart-908b39b7-ad42-4901-97b7-b8e1ee8d200a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166596963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.166596963
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.676365859
Short name T149
Test name
Test status
Simulation time 26154529436 ps
CPU time 43.33 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:56 PM PDT 24
Peak memory 213452 kb
Host smart-720b22cc-c4df-478b-91f5-4a50a3a80e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676365859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.676365859
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2019652361
Short name T217
Test name
Test status
Simulation time 1364895074 ps
CPU time 1.63 seconds
Started Jul 25 04:50:17 PM PDT 24
Finished Jul 25 04:50:19 PM PDT 24
Peak memory 213388 kb
Host smart-6b726e37-4d1d-4075-aeb0-798e0e08b7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019652361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2019652361
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2522730961
Short name T234
Test name
Test status
Simulation time 1852490185 ps
CPU time 5.33 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:19 PM PDT 24
Peak memory 205224 kb
Host smart-1aaf7999-909a-42e0-9b43-3afa4fcb4ece
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2522730961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2522730961
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3750162303
Short name T10
Test name
Test status
Simulation time 5564029260 ps
CPU time 16.04 seconds
Started Jul 25 04:50:07 PM PDT 24
Finished Jul 25 04:50:23 PM PDT 24
Peak memory 213440 kb
Host smart-39741655-22fe-4f49-b0ed-b9b7e4b8060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750162303 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3750162303
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1942628949
Short name T201
Test name
Test status
Simulation time 89506887 ps
CPU time 0.71 seconds
Started Jul 25 04:50:03 PM PDT 24
Finished Jul 25 04:50:04 PM PDT 24
Peak memory 204888 kb
Host smart-bece46c9-a11a-4810-ba01-6ee5bfd9fee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942628949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1942628949
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2216532139
Short name T152
Test name
Test status
Simulation time 6188361830 ps
CPU time 6.75 seconds
Started Jul 25 04:50:21 PM PDT 24
Finished Jul 25 04:50:28 PM PDT 24
Peak memory 213496 kb
Host smart-3061723c-e6d4-4a20-a6c8-00d234bb9a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216532139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2216532139
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.491403590
Short name T223
Test name
Test status
Simulation time 3705309624 ps
CPU time 2.39 seconds
Started Jul 25 04:50:23 PM PDT 24
Finished Jul 25 04:50:26 PM PDT 24
Peak memory 205292 kb
Host smart-443ffe16-fc91-48e7-b77d-ccda82426b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491403590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.491403590
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3718861966
Short name T260
Test name
Test status
Simulation time 12816770538 ps
CPU time 38.69 seconds
Started Jul 25 04:50:10 PM PDT 24
Finished Jul 25 04:50:48 PM PDT 24
Peak memory 213440 kb
Host smart-9d1e0ffe-591b-4a05-bf6e-24c47ed9211b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3718861966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3718861966
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3617652195
Short name T255
Test name
Test status
Simulation time 1963810511 ps
CPU time 2.38 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:15 PM PDT 24
Peak memory 205312 kb
Host smart-409adf50-a79a-4133-b6c4-26e3e6cd2cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617652195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3617652195
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1035952754
Short name T2
Test name
Test status
Simulation time 41227698 ps
CPU time 0.77 seconds
Started Jul 25 04:50:41 PM PDT 24
Finished Jul 25 04:50:41 PM PDT 24
Peak memory 205016 kb
Host smart-ea85ed19-7a4e-4834-84c7-094776f77e62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035952754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1035952754
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.752725243
Short name T237
Test name
Test status
Simulation time 1049865060 ps
CPU time 4.07 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:17 PM PDT 24
Peak memory 213412 kb
Host smart-a0a58c89-f5d6-47fd-8ec4-0ef0e8218f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752725243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.752725243
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.704798326
Short name T202
Test name
Test status
Simulation time 4779031709 ps
CPU time 3.98 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:16 PM PDT 24
Peak memory 205380 kb
Host smart-bbe60d2f-d319-4cce-8b07-a1a3716cef41
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704798326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.704798326
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.354528631
Short name T60
Test name
Test status
Simulation time 4008374009 ps
CPU time 8.25 seconds
Started Jul 25 04:50:18 PM PDT 24
Finished Jul 25 04:50:27 PM PDT 24
Peak memory 205296 kb
Host smart-162f9543-dd4b-4f85-be43-32d5b202ef5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354528631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.354528631
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1979698415
Short name T219
Test name
Test status
Simulation time 60641341 ps
CPU time 0.86 seconds
Started Jul 25 04:50:10 PM PDT 24
Finished Jul 25 04:50:11 PM PDT 24
Peak memory 205020 kb
Host smart-9e9ce580-cf7f-47fc-94ff-982a83a8771f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979698415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1979698415
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2524214180
Short name T183
Test name
Test status
Simulation time 3689230614 ps
CPU time 10.5 seconds
Started Jul 25 04:50:23 PM PDT 24
Finished Jul 25 04:50:34 PM PDT 24
Peak memory 213512 kb
Host smart-eae2d139-e899-4ddf-8624-a775c5a1604f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524214180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2524214180
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.4008268490
Short name T238
Test name
Test status
Simulation time 5067848052 ps
CPU time 2.34 seconds
Started Jul 25 04:50:16 PM PDT 24
Finished Jul 25 04:50:19 PM PDT 24
Peak memory 205376 kb
Host smart-d6708e29-e115-4293-b371-2451d3cb6d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008268490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.4008268490
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1582026823
Short name T278
Test name
Test status
Simulation time 12368618296 ps
CPU time 11.28 seconds
Started Jul 25 04:50:18 PM PDT 24
Finished Jul 25 04:50:30 PM PDT 24
Peak memory 213472 kb
Host smart-b46aa644-2e82-4fce-871f-55667282a62c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1582026823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1582026823
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.4198117879
Short name T151
Test name
Test status
Simulation time 1489523946 ps
CPU time 5.04 seconds
Started Jul 25 04:50:19 PM PDT 24
Finished Jul 25 04:50:24 PM PDT 24
Peak memory 213436 kb
Host smart-0628e8c1-3c8c-4e69-b1e6-ccea3a86b665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198117879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.4198117879
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1449141175
Short name T241
Test name
Test status
Simulation time 154784359 ps
CPU time 0.87 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:14 PM PDT 24
Peak memory 205036 kb
Host smart-5b0b3b9d-bf40-400a-beb9-1e25558d7015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449141175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1449141175
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.213091171
Short name T207
Test name
Test status
Simulation time 2524956558 ps
CPU time 4.71 seconds
Started Jul 25 04:50:16 PM PDT 24
Finished Jul 25 04:50:21 PM PDT 24
Peak memory 213460 kb
Host smart-859580a5-127c-4117-91a2-ce9b45acc75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213091171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.213091171
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.2455177193
Short name T211
Test name
Test status
Simulation time 1691868564 ps
CPU time 3.1 seconds
Started Jul 25 04:50:09 PM PDT 24
Finished Jul 25 04:50:13 PM PDT 24
Peak memory 205320 kb
Host smart-b713fb0b-9f9a-41da-8178-588b949015eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455177193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.2455177193
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2373927040
Short name T206
Test name
Test status
Simulation time 1776316073 ps
CPU time 3.52 seconds
Started Jul 25 04:50:17 PM PDT 24
Finished Jul 25 04:50:21 PM PDT 24
Peak memory 213576 kb
Host smart-6e90dfe9-bb37-4a4a-b532-de4948bfdcdf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2373927040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2373927040
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.3833765922
Short name T132
Test name
Test status
Simulation time 633355258 ps
CPU time 1.09 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:14 PM PDT 24
Peak memory 205144 kb
Host smart-ab53c1b1-65f5-4f05-b0d9-84bc40a93d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833765922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3833765922
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.2495138914
Short name T261
Test name
Test status
Simulation time 2213979477 ps
CPU time 7.53 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:21 PM PDT 24
Peak memory 213432 kb
Host smart-62322ba7-9f95-469e-954e-ecf14c26f26d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495138914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.2495138914
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.565799710
Short name T282
Test name
Test status
Simulation time 139201506 ps
CPU time 0.73 seconds
Started Jul 25 04:50:24 PM PDT 24
Finished Jul 25 04:50:25 PM PDT 24
Peak memory 204960 kb
Host smart-a4087e85-14dd-45aa-a27a-4aa8a1b06c6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565799710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.565799710
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1493245975
Short name T214
Test name
Test status
Simulation time 15863337891 ps
CPU time 44.99 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:59 PM PDT 24
Peak memory 205340 kb
Host smart-15ba8a09-7600-4f2a-aa8f-56323c989c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493245975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1493245975
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2714267284
Short name T193
Test name
Test status
Simulation time 8821815415 ps
CPU time 4.74 seconds
Started Jul 25 04:50:24 PM PDT 24
Finished Jul 25 04:50:29 PM PDT 24
Peak memory 213552 kb
Host smart-533f40e6-c1ac-4b8a-8550-96f05842c511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714267284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2714267284
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3993241155
Short name T239
Test name
Test status
Simulation time 918570737 ps
CPU time 1.58 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:14 PM PDT 24
Peak memory 205324 kb
Host smart-4a8aaf00-99dd-4337-84db-878dfac14af1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993241155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.3993241155
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.1889805582
Short name T227
Test name
Test status
Simulation time 929504849 ps
CPU time 3.66 seconds
Started Jul 25 04:50:08 PM PDT 24
Finished Jul 25 04:50:12 PM PDT 24
Peak memory 205296 kb
Host smart-9c0ba534-e537-46b5-99ff-b5913390e832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889805582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.1889805582
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.1129218029
Short name T156
Test name
Test status
Simulation time 2640070335 ps
CPU time 4.9 seconds
Started Jul 25 04:50:21 PM PDT 24
Finished Jul 25 04:50:26 PM PDT 24
Peak memory 213380 kb
Host smart-9c4cf898-7bb7-4d94-90f2-8895ef53a380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129218029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.1129218029
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.1732164858
Short name T248
Test name
Test status
Simulation time 80679995 ps
CPU time 0.73 seconds
Started Jul 25 04:53:44 PM PDT 24
Finished Jul 25 04:53:45 PM PDT 24
Peak memory 205020 kb
Host smart-43d243e6-dac3-4718-9012-790d68dc8604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732164858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1732164858
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2557067542
Short name T279
Test name
Test status
Simulation time 5230654007 ps
CPU time 9.47 seconds
Started Jul 25 04:50:28 PM PDT 24
Finished Jul 25 04:50:37 PM PDT 24
Peak memory 213548 kb
Host smart-b47905f6-3aed-4e95-a077-e08ccfb8a2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557067542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2557067542
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.676696300
Short name T26
Test name
Test status
Simulation time 8817047746 ps
CPU time 19.43 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:32 PM PDT 24
Peak memory 205396 kb
Host smart-168f863f-875c-40e0-9231-94a73c3d24f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676696300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.676696300
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.697491835
Short name T148
Test name
Test status
Simulation time 4125937484 ps
CPU time 13.13 seconds
Started Jul 25 04:50:18 PM PDT 24
Finished Jul 25 04:50:31 PM PDT 24
Peak memory 213560 kb
Host smart-4acdc514-f736-4694-848e-4eaff9429eaf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697491835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.697491835
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3669337127
Short name T198
Test name
Test status
Simulation time 7603428053 ps
CPU time 13.26 seconds
Started Jul 25 04:50:24 PM PDT 24
Finished Jul 25 04:50:38 PM PDT 24
Peak memory 213612 kb
Host smart-f4a44ba6-9b6b-4ffa-96da-3de0c4fff85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669337127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3669337127
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.3586472416
Short name T258
Test name
Test status
Simulation time 13747178498 ps
CPU time 27.51 seconds
Started Jul 25 04:50:10 PM PDT 24
Finished Jul 25 04:50:38 PM PDT 24
Peak memory 214168 kb
Host smart-155c401c-798c-4aa0-9b1e-d1a50822232f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586472416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.3586472416
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1619251153
Short name T117
Test name
Test status
Simulation time 94273344 ps
CPU time 0.71 seconds
Started Jul 25 04:50:22 PM PDT 24
Finished Jul 25 04:50:25 PM PDT 24
Peak memory 204924 kb
Host smart-f4554374-1193-49a3-b0bb-2ad354502600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619251153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1619251153
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2676180870
Short name T128
Test name
Test status
Simulation time 11189844559 ps
CPU time 31.39 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:45 PM PDT 24
Peak memory 213528 kb
Host smart-b4c0688c-e33a-4d1f-a5b6-3f8034796660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676180870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2676180870
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.330311230
Short name T1
Test name
Test status
Simulation time 2897443491 ps
CPU time 4.75 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:18 PM PDT 24
Peak memory 213588 kb
Host smart-84782b32-db8f-4cde-81cd-4f8f13974d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330311230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.330311230
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2307789934
Short name T133
Test name
Test status
Simulation time 8806500578 ps
CPU time 14.06 seconds
Started Jul 25 04:50:14 PM PDT 24
Finished Jul 25 04:50:28 PM PDT 24
Peak memory 213356 kb
Host smart-e41da332-47d6-4251-88b2-0e0e9fe95743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307789934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2307789934
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.773124380
Short name T171
Test name
Test status
Simulation time 78642271 ps
CPU time 0.7 seconds
Started Jul 25 04:50:14 PM PDT 24
Finished Jul 25 04:50:15 PM PDT 24
Peak memory 204924 kb
Host smart-90f8aea6-924f-46ba-a396-ba1b7612c913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773124380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.773124380
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2337164125
Short name T192
Test name
Test status
Simulation time 21105785796 ps
CPU time 28.46 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:39 PM PDT 24
Peak memory 205316 kb
Host smart-2811eced-741a-4911-a653-1c563cfba636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337164125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2337164125
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.278354261
Short name T46
Test name
Test status
Simulation time 9241028258 ps
CPU time 25.35 seconds
Started Jul 25 04:50:19 PM PDT 24
Finished Jul 25 04:50:45 PM PDT 24
Peak memory 213396 kb
Host smart-77e05b3c-92b5-4b16-8011-c40406be30c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278354261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.278354261
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2003690142
Short name T263
Test name
Test status
Simulation time 9370982909 ps
CPU time 5.77 seconds
Started Jul 25 04:50:16 PM PDT 24
Finished Jul 25 04:50:22 PM PDT 24
Peak memory 213624 kb
Host smart-e58199da-b92a-47c4-b85f-a39a3c80636e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2003690142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.2003690142
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2777303461
Short name T138
Test name
Test status
Simulation time 8157284198 ps
CPU time 5.28 seconds
Started Jul 25 04:50:17 PM PDT 24
Finished Jul 25 04:50:23 PM PDT 24
Peak memory 205320 kb
Host smart-dc446378-26e6-437e-93a2-0bf2ce23a379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777303461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2777303461
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2269017236
Short name T265
Test name
Test status
Simulation time 63401321 ps
CPU time 0.73 seconds
Started Jul 25 04:50:04 PM PDT 24
Finished Jul 25 04:50:10 PM PDT 24
Peak memory 204920 kb
Host smart-1ebf6484-0a02-4e23-b2e1-724b1142296a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269017236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2269017236
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.243380250
Short name T135
Test name
Test status
Simulation time 6842340685 ps
CPU time 17.52 seconds
Started Jul 25 04:50:09 PM PDT 24
Finished Jul 25 04:50:26 PM PDT 24
Peak memory 213636 kb
Host smart-94d7e98d-bea3-4aed-a972-7360947911b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243380250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.243380250
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3367867031
Short name T283
Test name
Test status
Simulation time 7444811672 ps
CPU time 10.07 seconds
Started Jul 25 04:50:00 PM PDT 24
Finished Jul 25 04:50:10 PM PDT 24
Peak memory 215268 kb
Host smart-26d0238f-2c49-440e-8c47-e4c8aa6bd415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367867031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3367867031
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.604266127
Short name T225
Test name
Test status
Simulation time 4957744819 ps
CPU time 4.47 seconds
Started Jul 25 04:49:54 PM PDT 24
Finished Jul 25 04:49:59 PM PDT 24
Peak memory 213496 kb
Host smart-e4220cff-20f6-40d1-b3d3-5c114bb2da40
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604266127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.604266127
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1734292492
Short name T50
Test name
Test status
Simulation time 269321116 ps
CPU time 0.77 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:12 PM PDT 24
Peak memory 204972 kb
Host smart-642e384f-c71a-4ca2-97c7-944c1e91356e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734292492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1734292492
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.474045421
Short name T246
Test name
Test status
Simulation time 10285546012 ps
CPU time 25.39 seconds
Started Jul 25 04:50:10 PM PDT 24
Finished Jul 25 04:50:36 PM PDT 24
Peak memory 213588 kb
Host smart-12c9ddfc-4771-44c9-af8c-5201ebd4b8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474045421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.474045421
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.3407490911
Short name T42
Test name
Test status
Simulation time 2811002877 ps
CPU time 7.7 seconds
Started Jul 25 04:50:18 PM PDT 24
Finished Jul 25 04:50:26 PM PDT 24
Peak memory 229524 kb
Host smart-c0551204-2da8-48e4-ba44-590c037cfcdb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407490911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3407490911
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.2071969433
Short name T220
Test name
Test status
Simulation time 8737914735 ps
CPU time 8.79 seconds
Started Jul 25 04:50:09 PM PDT 24
Finished Jul 25 04:50:18 PM PDT 24
Peak memory 205048 kb
Host smart-be8168c9-f611-45c6-9384-37de187b310e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071969433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2071969433
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2817690176
Short name T236
Test name
Test status
Simulation time 183589265 ps
CPU time 0.69 seconds
Started Jul 25 04:50:18 PM PDT 24
Finished Jul 25 04:50:19 PM PDT 24
Peak memory 204920 kb
Host smart-cd539abb-a2ad-47de-8b04-5905a9c0d38b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817690176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2817690176
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.3512351885
Short name T264
Test name
Test status
Simulation time 8986186022 ps
CPU time 26.5 seconds
Started Jul 25 04:50:19 PM PDT 24
Finished Jul 25 04:50:46 PM PDT 24
Peak memory 213368 kb
Host smart-33a6a49d-a9e6-4bdd-ba31-f7b09a3cd28a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512351885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3512351885
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.618873205
Short name T233
Test name
Test status
Simulation time 128375044 ps
CPU time 0.75 seconds
Started Jul 25 04:50:23 PM PDT 24
Finished Jul 25 04:50:24 PM PDT 24
Peak memory 204920 kb
Host smart-c70e7ca6-d230-41b7-95ee-d75914d986a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618873205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.618873205
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.2569208214
Short name T13
Test name
Test status
Simulation time 15389696508 ps
CPU time 14.05 seconds
Started Jul 25 04:50:23 PM PDT 24
Finished Jul 25 04:50:37 PM PDT 24
Peak memory 213296 kb
Host smart-125526dc-441f-4aac-92de-f38fe3b83b7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569208214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.2569208214
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.2469551521
Short name T173
Test name
Test status
Simulation time 83217475 ps
CPU time 0.75 seconds
Started Jul 25 04:50:19 PM PDT 24
Finished Jul 25 04:50:20 PM PDT 24
Peak memory 204924 kb
Host smart-5e9c2f74-286b-459e-8efa-2725dfb9bcd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469551521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2469551521
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1929070059
Short name T262
Test name
Test status
Simulation time 192553585 ps
CPU time 0.73 seconds
Started Jul 25 04:50:32 PM PDT 24
Finished Jul 25 04:50:33 PM PDT 24
Peak memory 205044 kb
Host smart-b4e75755-b499-4e5d-9b24-59674786a1d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929070059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1929070059
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.4196748392
Short name T74
Test name
Test status
Simulation time 4007389936 ps
CPU time 5.04 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:19 PM PDT 24
Peak memory 213440 kb
Host smart-692df6a8-a782-47f6-9b3e-6b26315306fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196748392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.4196748392
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3775074899
Short name T172
Test name
Test status
Simulation time 83918392 ps
CPU time 0.87 seconds
Started Jul 25 04:50:19 PM PDT 24
Finished Jul 25 04:50:20 PM PDT 24
Peak memory 204920 kb
Host smart-e8525621-6bc4-4b72-b2d5-989c61eec9b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775074899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3775074899
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.2166511107
Short name T54
Test name
Test status
Simulation time 4663603494 ps
CPU time 3.24 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:16 PM PDT 24
Peak memory 213364 kb
Host smart-50cc07e6-8c0e-4f20-8a25-2fbc2a843a6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166511107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2166511107
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3949141036
Short name T272
Test name
Test status
Simulation time 156369583 ps
CPU time 0.85 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:24 PM PDT 24
Peak memory 205040 kb
Host smart-446a3fce-9e9d-4dc2-9418-161b2b54216e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949141036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3949141036
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.429254476
Short name T20
Test name
Test status
Simulation time 2785569373 ps
CPU time 3.75 seconds
Started Jul 25 04:50:14 PM PDT 24
Finished Jul 25 04:50:18 PM PDT 24
Peak memory 205148 kb
Host smart-c376aa16-bf34-47e4-b38f-37373cc1e25a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429254476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.429254476
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1944421158
Short name T269
Test name
Test status
Simulation time 172645533 ps
CPU time 0.77 seconds
Started Jul 25 04:50:23 PM PDT 24
Finished Jul 25 04:50:25 PM PDT 24
Peak memory 204996 kb
Host smart-786b627a-b344-4775-9b3a-8378cbe94811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944421158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1944421158
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.4137775243
Short name T281
Test name
Test status
Simulation time 7813066084 ps
CPU time 11.48 seconds
Started Jul 25 04:50:25 PM PDT 24
Finished Jul 25 04:50:37 PM PDT 24
Peak memory 205116 kb
Host smart-9da7e3dc-1cd1-4120-a5f7-97405c382b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137775243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.4137775243
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.404626762
Short name T40
Test name
Test status
Simulation time 52826593 ps
CPU time 0.75 seconds
Started Jul 25 04:50:23 PM PDT 24
Finished Jul 25 04:50:24 PM PDT 24
Peak memory 205024 kb
Host smart-2cd54277-918f-44e0-b908-b226d46d2f09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404626762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.404626762
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2263346759
Short name T270
Test name
Test status
Simulation time 116291382 ps
CPU time 0.98 seconds
Started Jul 25 04:50:16 PM PDT 24
Finished Jul 25 04:50:18 PM PDT 24
Peak memory 205032 kb
Host smart-5e911dfc-263e-49f6-a3f7-e7d7f57222c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263346759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2263346759
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1758345166
Short name T11
Test name
Test status
Simulation time 7816028021 ps
CPU time 15.22 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:28 PM PDT 24
Peak memory 213704 kb
Host smart-c08862b5-83ad-4b3a-aa1e-c609d31d13c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758345166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1758345166
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1947440887
Short name T209
Test name
Test status
Simulation time 91399288 ps
CPU time 0.75 seconds
Started Jul 25 04:50:21 PM PDT 24
Finished Jul 25 04:50:22 PM PDT 24
Peak memory 205032 kb
Host smart-5af061c7-a60c-435c-b7e7-0c8bc065dc39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947440887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1947440887
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.1795716040
Short name T73
Test name
Test status
Simulation time 3089221427 ps
CPU time 8.85 seconds
Started Jul 25 04:50:22 PM PDT 24
Finished Jul 25 04:50:32 PM PDT 24
Peak memory 213416 kb
Host smart-902e4f67-8018-4ffe-bd68-6ddf36513fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795716040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1795716040
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1069870341
Short name T174
Test name
Test status
Simulation time 64022722 ps
CPU time 0.7 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:12 PM PDT 24
Peak memory 205012 kb
Host smart-a5490e0e-d9c8-4d57-8c15-b6cab2ba403b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069870341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1069870341
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1402818139
Short name T249
Test name
Test status
Simulation time 933335009 ps
CPU time 1.85 seconds
Started Jul 25 04:50:14 PM PDT 24
Finished Jul 25 04:50:16 PM PDT 24
Peak memory 213556 kb
Host smart-a123c322-2a4e-4569-a0b0-3211d0de7f3f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1402818139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1402818139
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.514216834
Short name T229
Test name
Test status
Simulation time 186318702 ps
CPU time 0.7 seconds
Started Jul 25 04:50:35 PM PDT 24
Finished Jul 25 04:50:36 PM PDT 24
Peak memory 204908 kb
Host smart-b03f4fa4-c7db-4501-9778-2cff9132dc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514216834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.514216834
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3237477429
Short name T271
Test name
Test status
Simulation time 8775556052 ps
CPU time 11.86 seconds
Started Jul 25 04:50:18 PM PDT 24
Finished Jul 25 04:50:30 PM PDT 24
Peak memory 205364 kb
Host smart-a8f07190-78fa-4296-a8e0-a08c0eeee1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237477429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3237477429
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.2759747135
Short name T58
Test name
Test status
Simulation time 2539541364 ps
CPU time 4.14 seconds
Started Jul 25 04:50:09 PM PDT 24
Finished Jul 25 04:50:13 PM PDT 24
Peak memory 229212 kb
Host smart-207f81f3-dd02-49b3-b7a3-a483360a74fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759747135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.2759747135
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.2956919333
Short name T37
Test name
Test status
Simulation time 4009145420 ps
CPU time 9.97 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:22 PM PDT 24
Peak memory 205196 kb
Host smart-e95a36c7-c9ef-4360-b739-1a425cd7d31b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956919333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2956919333
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3868154735
Short name T204
Test name
Test status
Simulation time 42668935 ps
CPU time 0.77 seconds
Started Jul 25 04:50:46 PM PDT 24
Finished Jul 25 04:50:47 PM PDT 24
Peak memory 205036 kb
Host smart-e44c23cb-df04-4307-96fe-2e0ebf2630d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868154735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3868154735
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3613354827
Short name T158
Test name
Test status
Simulation time 3955731413 ps
CPU time 11.87 seconds
Started Jul 25 04:50:14 PM PDT 24
Finished Jul 25 04:50:31 PM PDT 24
Peak memory 213440 kb
Host smart-88232905-95ef-495a-9fd4-b02ee9f8571a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613354827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3613354827
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3228971829
Short name T197
Test name
Test status
Simulation time 65705131 ps
CPU time 0.82 seconds
Started Jul 25 04:50:41 PM PDT 24
Finished Jul 25 04:50:42 PM PDT 24
Peak memory 205044 kb
Host smart-7921051e-86bd-4e25-8773-1e071d35a41a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228971829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3228971829
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3159828806
Short name T184
Test name
Test status
Simulation time 79963609 ps
CPU time 0.75 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:14 PM PDT 24
Peak memory 205036 kb
Host smart-e09f78ba-8f4e-4336-8348-788f5da4759a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159828806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3159828806
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.636932556
Short name T145
Test name
Test status
Simulation time 4612846536 ps
CPU time 13.39 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:25 PM PDT 24
Peak memory 213428 kb
Host smart-5810ce48-c042-4425-a5f4-d77e033b8986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636932556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.636932556
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2728663890
Short name T256
Test name
Test status
Simulation time 93248513 ps
CPU time 0.77 seconds
Started Jul 25 04:50:44 PM PDT 24
Finished Jul 25 04:50:45 PM PDT 24
Peak memory 205044 kb
Host smart-2e6d43d5-0222-49c5-971a-8b46f38c69c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728663890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2728663890
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.2349508938
Short name T19
Test name
Test status
Simulation time 6757081689 ps
CPU time 19.08 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:32 PM PDT 24
Peak memory 213324 kb
Host smart-6d11591e-071b-495a-98c6-68a165f5dc9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349508938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.2349508938
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1019591107
Short name T224
Test name
Test status
Simulation time 105127298 ps
CPU time 0.74 seconds
Started Jul 25 04:50:21 PM PDT 24
Finished Jul 25 04:50:21 PM PDT 24
Peak memory 204844 kb
Host smart-a6475a1b-bea4-4f8a-a2d3-30435fe54c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019591107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1019591107
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.460893171
Short name T195
Test name
Test status
Simulation time 147677683 ps
CPU time 0.75 seconds
Started Jul 25 04:50:16 PM PDT 24
Finished Jul 25 04:50:23 PM PDT 24
Peak memory 204904 kb
Host smart-6b190869-2a5d-4582-bbef-e07f46096330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460893171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.460893171
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2707028217
Short name T199
Test name
Test status
Simulation time 3643081515 ps
CPU time 3.63 seconds
Started Jul 25 04:50:14 PM PDT 24
Finished Jul 25 04:50:18 PM PDT 24
Peak memory 213328 kb
Host smart-ffdfbb34-e5e4-46f1-b194-62614ecdbbe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707028217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2707028217
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.4179285316
Short name T190
Test name
Test status
Simulation time 65627965 ps
CPU time 0.77 seconds
Started Jul 25 04:50:24 PM PDT 24
Finished Jul 25 04:50:25 PM PDT 24
Peak memory 205016 kb
Host smart-9307cbbb-dd14-4799-8129-a8daff21e54d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179285316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.4179285316
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.4243177312
Short name T142
Test name
Test status
Simulation time 3718387159 ps
CPU time 10.34 seconds
Started Jul 25 04:50:46 PM PDT 24
Finished Jul 25 04:50:56 PM PDT 24
Peak memory 213264 kb
Host smart-d3b53613-8d1b-4c34-b617-0d0b30cb6f92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243177312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.4243177312
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3069859080
Short name T274
Test name
Test status
Simulation time 76661835 ps
CPU time 0.87 seconds
Started Jul 25 04:50:14 PM PDT 24
Finished Jul 25 04:50:15 PM PDT 24
Peak memory 205032 kb
Host smart-27a092c2-6eeb-4522-8397-fa899fafe371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069859080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3069859080
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3452308141
Short name T288
Test name
Test status
Simulation time 209185293 ps
CPU time 0.7 seconds
Started Jul 25 04:50:30 PM PDT 24
Finished Jul 25 04:50:31 PM PDT 24
Peak memory 204916 kb
Host smart-ea3f9288-b29c-4447-a3c3-e4ee211a5ffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452308141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3452308141
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.760217476
Short name T251
Test name
Test status
Simulation time 191192001 ps
CPU time 0.74 seconds
Started Jul 25 04:50:20 PM PDT 24
Finished Jul 25 04:50:21 PM PDT 24
Peak memory 204920 kb
Host smart-5617c25d-1d5b-4deb-ac39-14d80ed7ca5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760217476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.760217476
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.354722432
Short name T6
Test name
Test status
Simulation time 3545798296 ps
CPU time 5.8 seconds
Started Jul 25 04:50:24 PM PDT 24
Finished Jul 25 04:50:30 PM PDT 24
Peak memory 205224 kb
Host smart-cd86053f-4a00-4d5e-871e-2e48bd634e7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354722432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.354722432
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.578438698
Short name T228
Test name
Test status
Simulation time 16093191198 ps
CPU time 12.42 seconds
Started Jul 25 04:50:09 PM PDT 24
Finished Jul 25 04:50:21 PM PDT 24
Peak memory 213536 kb
Host smart-7524d32d-5f67-4dc1-a88a-8723ef5f5638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578438698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.578438698
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2885186362
Short name T47
Test name
Test status
Simulation time 2331495854 ps
CPU time 2.83 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:17 PM PDT 24
Peak memory 214640 kb
Host smart-f2a4b8cd-4dcb-49ff-a90e-533e795aa0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885186362 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2885186362
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.3428111436
Short name T276
Test name
Test status
Simulation time 2561175120 ps
CPU time 2.25 seconds
Started Jul 25 04:50:17 PM PDT 24
Finished Jul 25 04:50:20 PM PDT 24
Peak memory 213524 kb
Host smart-8b79dd2b-fc91-4598-92f7-ddd872cf8acc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3428111436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.3428111436
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.3671378932
Short name T49
Test name
Test status
Simulation time 234351755 ps
CPU time 1.3 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:13 PM PDT 24
Peak memory 204828 kb
Host smart-4c26e9b0-22df-42a2-9c52-70f6cc10b2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671378932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.3671378932
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2983065745
Short name T137
Test name
Test status
Simulation time 5350270320 ps
CPU time 14.27 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:26 PM PDT 24
Peak memory 213540 kb
Host smart-3db9a743-9c2b-4bc0-a0dd-54712456806d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983065745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2983065745
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3283217295
Short name T41
Test name
Test status
Simulation time 1244758399 ps
CPU time 2.69 seconds
Started Jul 25 04:50:15 PM PDT 24
Finished Jul 25 04:50:17 PM PDT 24
Peak memory 229444 kb
Host smart-0d5faccf-5608-4b2d-b3e4-19a66f631fd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283217295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3283217295
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.3394333157
Short name T140
Test name
Test status
Simulation time 2597923803 ps
CPU time 3.04 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:16 PM PDT 24
Peak memory 213372 kb
Host smart-fb4cbcf3-588f-4e6c-bb87-56a667fbf71f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394333157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.3394333157
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.2773851784
Short name T24
Test name
Test status
Simulation time 27589528489 ps
CPU time 620.85 seconds
Started Jul 25 04:50:10 PM PDT 24
Finished Jul 25 05:00:31 PM PDT 24
Peak memory 229820 kb
Host smart-e3e77967-1a6b-4e3e-ad07-9e17e467eb40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773851784 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.2773851784
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3922485820
Short name T34
Test name
Test status
Simulation time 99441624 ps
CPU time 0.95 seconds
Started Jul 25 04:50:18 PM PDT 24
Finished Jul 25 04:50:19 PM PDT 24
Peak memory 205028 kb
Host smart-b671558e-228b-4bb5-b018-00b3faa1069a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922485820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3922485820
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.772097257
Short name T30
Test name
Test status
Simulation time 2969708273 ps
CPU time 4.01 seconds
Started Jul 25 04:50:29 PM PDT 24
Finished Jul 25 04:50:34 PM PDT 24
Peak memory 213368 kb
Host smart-ce610b6d-ebce-4970-8d23-c1d2aecaaade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772097257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.772097257
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1857663535
Short name T175
Test name
Test status
Simulation time 30630209 ps
CPU time 0.74 seconds
Started Jul 25 04:50:37 PM PDT 24
Finished Jul 25 04:50:38 PM PDT 24
Peak memory 205052 kb
Host smart-82a47e4f-8010-4f5a-bac2-ed213dfdc33c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857663535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1857663535
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.1212799587
Short name T230
Test name
Test status
Simulation time 7952827353 ps
CPU time 23.17 seconds
Started Jul 25 04:50:23 PM PDT 24
Finished Jul 25 04:50:47 PM PDT 24
Peak memory 213420 kb
Host smart-fb988fa5-1410-4aee-b0c0-79ebbb33aff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212799587 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1212799587
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3285205809
Short name T245
Test name
Test status
Simulation time 93557897 ps
CPU time 0.71 seconds
Started Jul 25 04:50:23 PM PDT 24
Finished Jul 25 04:50:24 PM PDT 24
Peak memory 204920 kb
Host smart-c1bfddea-0521-4c26-974b-778c5db90eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285205809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3285205809
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.199575524
Short name T182
Test name
Test status
Simulation time 45145849 ps
CPU time 0.77 seconds
Started Jul 25 04:50:50 PM PDT 24
Finished Jul 25 04:50:51 PM PDT 24
Peak memory 204932 kb
Host smart-c8301714-13f0-4eef-b69a-b024864a9d13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199575524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.199575524
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.2112714376
Short name T180
Test name
Test status
Simulation time 3822835662 ps
CPU time 11.51 seconds
Started Jul 25 04:50:33 PM PDT 24
Finished Jul 25 04:50:45 PM PDT 24
Peak memory 205064 kb
Host smart-b538ff0d-3496-4b20-ae47-24a0b1210878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112714376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2112714376
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1749044392
Short name T266
Test name
Test status
Simulation time 56514616 ps
CPU time 0.81 seconds
Started Jul 25 04:50:29 PM PDT 24
Finished Jul 25 04:50:30 PM PDT 24
Peak memory 205024 kb
Host smart-e3f68222-8b0b-4ebf-bbfb-af57e0e58a11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749044392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1749044392
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.3090458656
Short name T240
Test name
Test status
Simulation time 55551588 ps
CPU time 0.83 seconds
Started Jul 25 04:50:18 PM PDT 24
Finished Jul 25 04:50:19 PM PDT 24
Peak memory 204908 kb
Host smart-b1bf543f-0be8-4a85-9755-ba20c6331b60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090458656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.3090458656
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.570456421
Short name T287
Test name
Test status
Simulation time 1965535285 ps
CPU time 6.33 seconds
Started Jul 25 04:50:30 PM PDT 24
Finished Jul 25 04:50:36 PM PDT 24
Peak memory 213244 kb
Host smart-8c283b99-b866-4335-8d53-b65111a1e481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570456421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.570456421
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3683772712
Short name T48
Test name
Test status
Simulation time 60176729 ps
CPU time 0.66 seconds
Started Jul 25 04:50:32 PM PDT 24
Finished Jul 25 04:50:32 PM PDT 24
Peak memory 205024 kb
Host smart-574eefc5-709e-425b-8e65-17f9c2d3765c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683772712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3683772712
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.715113800
Short name T23
Test name
Test status
Simulation time 4578842166 ps
CPU time 4.44 seconds
Started Jul 25 04:50:24 PM PDT 24
Finished Jul 25 04:50:29 PM PDT 24
Peak memory 213412 kb
Host smart-eab5be47-8e01-412b-b81c-850f64a970ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715113800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.715113800
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1630466745
Short name T52
Test name
Test status
Simulation time 139213375 ps
CPU time 0.71 seconds
Started Jul 25 04:50:39 PM PDT 24
Finished Jul 25 04:50:39 PM PDT 24
Peak memory 204904 kb
Host smart-8b5874f5-b4a4-486d-80c5-654c560a74d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630466745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1630466745
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1453379573
Short name T235
Test name
Test status
Simulation time 99884456 ps
CPU time 0.9 seconds
Started Jul 25 04:50:20 PM PDT 24
Finished Jul 25 04:50:21 PM PDT 24
Peak memory 205024 kb
Host smart-b2ca29af-be46-4703-8cc8-83e4ec758508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453379573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1453379573
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.3977888622
Short name T242
Test name
Test status
Simulation time 2472655845 ps
CPU time 7.04 seconds
Started Jul 25 04:50:23 PM PDT 24
Finished Jul 25 04:50:31 PM PDT 24
Peak memory 213244 kb
Host smart-c433a2ed-1f96-4608-b647-baeecfb496ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977888622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.3977888622
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3849686900
Short name T56
Test name
Test status
Simulation time 36671372 ps
CPU time 0.72 seconds
Started Jul 25 04:50:21 PM PDT 24
Finished Jul 25 04:50:25 PM PDT 24
Peak memory 204920 kb
Host smart-dd61d142-4042-479b-931f-8594021b1d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849686900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3849686900
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.3648564800
Short name T218
Test name
Test status
Simulation time 48813282 ps
CPU time 0.78 seconds
Started Jul 25 04:50:17 PM PDT 24
Finished Jul 25 04:50:18 PM PDT 24
Peak memory 205028 kb
Host smart-ec1f5133-7411-4559-9887-77c66c2e7b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648564800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3648564800
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3237978117
Short name T221
Test name
Test status
Simulation time 31029401231 ps
CPU time 24.02 seconds
Started Jul 25 04:50:23 PM PDT 24
Finished Jul 25 04:50:48 PM PDT 24
Peak memory 213620 kb
Host smart-1963970c-cc5a-4417-81de-8ce7ae31f3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237978117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3237978117
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3182589048
Short name T127
Test name
Test status
Simulation time 1113664477 ps
CPU time 4.23 seconds
Started Jul 25 04:50:18 PM PDT 24
Finished Jul 25 04:50:22 PM PDT 24
Peak memory 205292 kb
Host smart-186d8ff6-2ab7-4222-bbd4-7954ddec0f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182589048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3182589048
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1248983458
Short name T231
Test name
Test status
Simulation time 4276735282 ps
CPU time 12.51 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:29 PM PDT 24
Peak memory 205336 kb
Host smart-b66b63af-9e3e-4a02-af12-e4f87e764ac0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248983458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1248983458
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.543853120
Short name T124
Test name
Test status
Simulation time 6313801423 ps
CPU time 5.11 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:19 PM PDT 24
Peak memory 205388 kb
Host smart-24d17cc3-98db-4138-b652-fbdb022926ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543853120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.543853120
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.3419397553
Short name T154
Test name
Test status
Simulation time 3535957953 ps
CPU time 10.66 seconds
Started Jul 25 04:50:08 PM PDT 24
Finished Jul 25 04:50:19 PM PDT 24
Peak memory 213172 kb
Host smart-baa3ce89-0ef8-4284-89e3-398799d0c85e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419397553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3419397553
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.1116460124
Short name T68
Test name
Test status
Simulation time 79947106015 ps
CPU time 739.61 seconds
Started Jul 25 04:50:14 PM PDT 24
Finished Jul 25 05:02:34 PM PDT 24
Peak memory 229940 kb
Host smart-f1e1eb92-e03f-4939-9430-5c70bdf842a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116460124 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.1116460124
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1690807646
Short name T203
Test name
Test status
Simulation time 73884882 ps
CPU time 0.76 seconds
Started Jul 25 04:50:43 PM PDT 24
Finished Jul 25 04:50:44 PM PDT 24
Peak memory 205020 kb
Host smart-09196505-d41b-4df5-8c8d-60aa4585cd20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690807646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1690807646
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2496909703
Short name T257
Test name
Test status
Simulation time 28283541666 ps
CPU time 82.81 seconds
Started Jul 25 04:50:15 PM PDT 24
Finished Jul 25 04:51:38 PM PDT 24
Peak memory 213444 kb
Host smart-4453cc15-a85b-46e7-b56b-59f27c9af9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496909703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2496909703
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.321520460
Short name T129
Test name
Test status
Simulation time 1028058499 ps
CPU time 2.18 seconds
Started Jul 25 04:50:14 PM PDT 24
Finished Jul 25 04:50:17 PM PDT 24
Peak memory 205296 kb
Host smart-d090c439-02b0-400f-a2a3-a10484e6635e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321520460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.321520460
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1695188730
Short name T157
Test name
Test status
Simulation time 1834432555 ps
CPU time 6.25 seconds
Started Jul 25 04:50:20 PM PDT 24
Finished Jul 25 04:50:26 PM PDT 24
Peak memory 205288 kb
Host smart-9e15b9d8-e5c7-4cb7-83bf-a2deb5cacb65
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1695188730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1695188730
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.178046888
Short name T16
Test name
Test status
Simulation time 5156887213 ps
CPU time 7.95 seconds
Started Jul 25 04:50:14 PM PDT 24
Finished Jul 25 04:50:22 PM PDT 24
Peak memory 213604 kb
Host smart-f7afe08d-7e70-4221-aad6-96173064d92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178046888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.178046888
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.2985349481
Short name T139
Test name
Test status
Simulation time 4929897630 ps
CPU time 11.78 seconds
Started Jul 25 04:50:11 PM PDT 24
Finished Jul 25 04:50:23 PM PDT 24
Peak memory 213344 kb
Host smart-3b243e7c-c7c7-426b-a8b0-fb068af975a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985349481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2985349481
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.3114736204
Short name T69
Test name
Test status
Simulation time 11865341322 ps
CPU time 163.03 seconds
Started Jul 25 04:50:14 PM PDT 24
Finished Jul 25 04:52:58 PM PDT 24
Peak memory 221508 kb
Host smart-84cd1cf6-e7dc-4195-ac50-28354f8f53df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114736204 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.3114736204
Directory /workspace/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.3347034714
Short name T273
Test name
Test status
Simulation time 65267171 ps
CPU time 0.77 seconds
Started Jul 25 04:50:24 PM PDT 24
Finished Jul 25 04:50:25 PM PDT 24
Peak memory 205028 kb
Host smart-b424ee6d-e6f5-489c-997a-1a48f43f7230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347034714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3347034714
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1897733894
Short name T205
Test name
Test status
Simulation time 185192688572 ps
CPU time 163.51 seconds
Started Jul 25 04:50:15 PM PDT 24
Finished Jul 25 04:52:59 PM PDT 24
Peak memory 230192 kb
Host smart-8efc3529-8d40-4b49-abc3-83e3d5918bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897733894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1897733894
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1550071997
Short name T178
Test name
Test status
Simulation time 2172416926 ps
CPU time 2.54 seconds
Started Jul 25 04:50:22 PM PDT 24
Finished Jul 25 04:50:24 PM PDT 24
Peak memory 213552 kb
Host smart-7143c68d-0bdd-4905-87fd-6a1c68dc52c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550071997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1550071997
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1716197117
Short name T85
Test name
Test status
Simulation time 5605961328 ps
CPU time 16.8 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:29 PM PDT 24
Peak memory 213560 kb
Host smart-f69c6bae-3e40-41b3-b79b-67051d7e057a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1716197117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1716197117
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3031778199
Short name T185
Test name
Test status
Simulation time 3586723410 ps
CPU time 4.31 seconds
Started Jul 25 04:50:19 PM PDT 24
Finished Jul 25 04:50:24 PM PDT 24
Peak memory 205396 kb
Host smart-12ccb05f-43cb-4ecd-81ef-b61508825fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031778199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3031778199
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.2209993888
Short name T15
Test name
Test status
Simulation time 2146887433 ps
CPU time 3.17 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:17 PM PDT 24
Peak memory 205108 kb
Host smart-12358b22-5ee5-4efe-b287-ea204d8eed0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209993888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2209993888
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.4067279090
Short name T196
Test name
Test status
Simulation time 131353342 ps
CPU time 0.98 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:14 PM PDT 24
Peak memory 205048 kb
Host smart-e5e1dc4a-f233-4bed-857e-b2de7601c46e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067279090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.4067279090
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.816732649
Short name T176
Test name
Test status
Simulation time 39991255067 ps
CPU time 67.15 seconds
Started Jul 25 04:50:15 PM PDT 24
Finished Jul 25 04:51:22 PM PDT 24
Peak memory 213524 kb
Host smart-71399a12-fb27-4d3a-bd72-ce37acd889f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816732649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.816732649
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1411188407
Short name T277
Test name
Test status
Simulation time 2243604837 ps
CPU time 2.24 seconds
Started Jul 25 04:50:16 PM PDT 24
Finished Jul 25 04:50:18 PM PDT 24
Peak memory 213408 kb
Host smart-ce12647e-270b-4d9b-9946-2b28a25ee67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411188407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1411188407
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.224235048
Short name T179
Test name
Test status
Simulation time 11224181210 ps
CPU time 10.74 seconds
Started Jul 25 04:50:13 PM PDT 24
Finished Jul 25 04:50:24 PM PDT 24
Peak memory 213464 kb
Host smart-f9540e8f-918e-4495-888f-5aa01f3c31eb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224235048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.224235048
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1373386861
Short name T188
Test name
Test status
Simulation time 9313108007 ps
CPU time 12.4 seconds
Started Jul 25 04:50:19 PM PDT 24
Finished Jul 25 04:50:32 PM PDT 24
Peak memory 205256 kb
Host smart-0695fbb9-7fcc-4ae5-92cf-978c4cf5e915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373386861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1373386861
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.1451735247
Short name T18
Test name
Test status
Simulation time 4610617656 ps
CPU time 2.62 seconds
Started Jul 25 04:50:20 PM PDT 24
Finished Jul 25 04:50:23 PM PDT 24
Peak memory 213296 kb
Host smart-da58737a-4824-488a-9510-1168371f8d11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451735247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.1451735247
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1285013571
Short name T186
Test name
Test status
Simulation time 53855422 ps
CPU time 0.71 seconds
Started Jul 25 04:50:06 PM PDT 24
Finished Jul 25 04:50:07 PM PDT 24
Peak memory 204980 kb
Host smart-5635d36f-3f35-4a28-80a8-ed9c3703883a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285013571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1285013571
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3692893306
Short name T213
Test name
Test status
Simulation time 1638391059 ps
CPU time 5 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:18 PM PDT 24
Peak memory 213508 kb
Host smart-39f7a3e2-103f-4f0e-81b2-3095c1c610e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692893306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3692893306
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1171020829
Short name T226
Test name
Test status
Simulation time 9083127816 ps
CPU time 25.81 seconds
Started Jul 25 04:50:19 PM PDT 24
Finished Jul 25 04:50:45 PM PDT 24
Peak memory 213436 kb
Host smart-115dac89-92b8-4294-8028-69b8183fac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171020829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1171020829
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1368024656
Short name T267
Test name
Test status
Simulation time 1026779192 ps
CPU time 3.76 seconds
Started Jul 25 04:50:12 PM PDT 24
Finished Jul 25 04:50:16 PM PDT 24
Peak memory 205348 kb
Host smart-9a511e9b-46b5-44e3-8731-680e5e863999
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1368024656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1368024656
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1373885649
Short name T259
Test name
Test status
Simulation time 2911951572 ps
CPU time 3.58 seconds
Started Jul 25 04:50:18 PM PDT 24
Finished Jul 25 04:50:22 PM PDT 24
Peak memory 213552 kb
Host smart-e0241ab3-51af-49a5-8b59-cd770a9e687d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373885649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1373885649
Directory /workspace/9.rv_dm_sba_tl_access/latest
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