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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.71 96.18 85.48 89.91 71.25 88.33 98.53 56.31


Total test records in report: 468
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T312 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1587039425 Jul 29 05:18:04 PM PDT 24 Jul 29 05:18:13 PM PDT 24 4498454369 ps
T108 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4058807551 Jul 29 05:17:58 PM PDT 24 Jul 29 05:18:01 PM PDT 24 338350470 ps
T111 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.879662512 Jul 29 05:18:07 PM PDT 24 Jul 29 05:18:16 PM PDT 24 687006051 ps
T68 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.483361010 Jul 29 05:18:01 PM PDT 24 Jul 29 05:18:03 PM PDT 24 131591900 ps
T313 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4021705357 Jul 29 05:18:15 PM PDT 24 Jul 29 05:18:32 PM PDT 24 6330998238 ps
T314 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.95421605 Jul 29 05:17:41 PM PDT 24 Jul 29 05:18:12 PM PDT 24 10664046171 ps
T69 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3015049978 Jul 29 05:17:55 PM PDT 24 Jul 29 05:17:57 PM PDT 24 57216014 ps
T70 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3767504145 Jul 29 05:17:46 PM PDT 24 Jul 29 05:17:52 PM PDT 24 307212842 ps
T54 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2716642349 Jul 29 05:18:01 PM PDT 24 Jul 29 05:18:02 PM PDT 24 295831901 ps
T112 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4130442655 Jul 29 05:18:06 PM PDT 24 Jul 29 05:18:16 PM PDT 24 1604663687 ps
T71 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1150285585 Jul 29 05:18:27 PM PDT 24 Jul 29 05:18:35 PM PDT 24 951328162 ps
T55 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.294978728 Jul 29 05:18:06 PM PDT 24 Jul 29 05:18:07 PM PDT 24 689337774 ps
T79 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3993117990 Jul 29 05:17:49 PM PDT 24 Jul 29 05:17:59 PM PDT 24 3881361520 ps
T56 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.703767150 Jul 29 05:18:05 PM PDT 24 Jul 29 05:18:06 PM PDT 24 190251397 ps
T315 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.737671874 Jul 29 05:17:47 PM PDT 24 Jul 29 05:17:47 PM PDT 24 100842715 ps
T316 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.4272747627 Jul 29 05:18:06 PM PDT 24 Jul 29 05:18:10 PM PDT 24 76021793 ps
T317 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.976856731 Jul 29 05:18:29 PM PDT 24 Jul 29 05:20:47 PM PDT 24 100651278991 ps
T72 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.720977645 Jul 29 05:18:37 PM PDT 24 Jul 29 05:18:39 PM PDT 24 250139571 ps
T318 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.472310348 Jul 29 05:17:46 PM PDT 24 Jul 29 05:18:33 PM PDT 24 16042493888 ps
T319 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.782751914 Jul 29 05:18:22 PM PDT 24 Jul 29 05:18:38 PM PDT 24 26372713416 ps
T73 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3033863358 Jul 29 05:18:12 PM PDT 24 Jul 29 05:18:18 PM PDT 24 320216759 ps
T109 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1087498863 Jul 29 05:17:58 PM PDT 24 Jul 29 05:18:03 PM PDT 24 630139017 ps
T74 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1227424133 Jul 29 05:17:45 PM PDT 24 Jul 29 05:18:12 PM PDT 24 1175745074 ps
T320 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2506931709 Jul 29 05:17:57 PM PDT 24 Jul 29 05:17:58 PM PDT 24 181600064 ps
T113 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.802325031 Jul 29 05:18:14 PM PDT 24 Jul 29 05:18:35 PM PDT 24 3798515226 ps
T321 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3927136557 Jul 29 05:17:50 PM PDT 24 Jul 29 05:18:10 PM PDT 24 13218938727 ps
T322 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2685443176 Jul 29 05:17:59 PM PDT 24 Jul 29 05:18:00 PM PDT 24 729192463 ps
T323 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2169127000 Jul 29 05:18:00 PM PDT 24 Jul 29 05:18:00 PM PDT 24 149177565 ps
T52 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1320242795 Jul 29 05:17:55 PM PDT 24 Jul 29 05:18:57 PM PDT 24 58670155259 ps
T75 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3603448761 Jul 29 05:18:00 PM PDT 24 Jul 29 05:18:08 PM PDT 24 624837632 ps
T324 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1587137147 Jul 29 05:17:39 PM PDT 24 Jul 29 05:17:40 PM PDT 24 849756498 ps
T76 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.209445174 Jul 29 05:18:01 PM PDT 24 Jul 29 05:18:06 PM PDT 24 1072804961 ps
T155 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3520658681 Jul 29 05:18:01 PM PDT 24 Jul 29 05:18:24 PM PDT 24 4659009782 ps
T77 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1207683007 Jul 29 05:18:07 PM PDT 24 Jul 29 05:18:08 PM PDT 24 192051979 ps
T325 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1945426518 Jul 29 05:17:54 PM PDT 24 Jul 29 05:18:18 PM PDT 24 25864382683 ps
T326 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2681055600 Jul 29 05:17:59 PM PDT 24 Jul 29 05:18:02 PM PDT 24 4475787499 ps
T152 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2443847722 Jul 29 05:18:30 PM PDT 24 Jul 29 05:18:40 PM PDT 24 3505831460 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.363793771 Jul 29 05:17:55 PM PDT 24 Jul 29 05:17:56 PM PDT 24 540760373 ps
T328 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2369753281 Jul 29 05:18:15 PM PDT 24 Jul 29 05:18:19 PM PDT 24 236220565 ps
T329 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1309138293 Jul 29 05:18:27 PM PDT 24 Jul 29 05:18:31 PM PDT 24 6153354085 ps
T330 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2662347117 Jul 29 05:17:44 PM PDT 24 Jul 29 05:18:03 PM PDT 24 5788913356 ps
T331 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.4024637720 Jul 29 05:17:38 PM PDT 24 Jul 29 05:17:45 PM PDT 24 1087951656 ps
T332 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2614248500 Jul 29 05:18:22 PM PDT 24 Jul 29 05:18:25 PM PDT 24 232436215 ps
T84 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3067072979 Jul 29 05:17:51 PM PDT 24 Jul 29 05:18:00 PM PDT 24 1683536145 ps
T333 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1313937528 Jul 29 05:18:18 PM PDT 24 Jul 29 05:18:21 PM PDT 24 213066380 ps
T162 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3475215425 Jul 29 05:18:07 PM PDT 24 Jul 29 05:18:18 PM PDT 24 1395186022 ps
T334 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.370157292 Jul 29 05:17:50 PM PDT 24 Jul 29 05:17:54 PM PDT 24 247889414 ps
T85 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3640586347 Jul 29 05:17:55 PM PDT 24 Jul 29 05:17:58 PM PDT 24 228389604 ps
T335 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3696930294 Jul 29 05:17:56 PM PDT 24 Jul 29 05:18:02 PM PDT 24 1166615216 ps
T336 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3830021132 Jul 29 05:18:11 PM PDT 24 Jul 29 05:18:14 PM PDT 24 413083583 ps
T86 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.25435000 Jul 29 05:18:20 PM PDT 24 Jul 29 05:18:22 PM PDT 24 125847222 ps
T337 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1422078864 Jul 29 05:18:02 PM PDT 24 Jul 29 05:18:07 PM PDT 24 923870944 ps
T338 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1982142762 Jul 29 05:18:05 PM PDT 24 Jul 29 05:18:08 PM PDT 24 529110990 ps
T339 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2331174348 Jul 29 05:17:51 PM PDT 24 Jul 29 05:18:57 PM PDT 24 19571465991 ps
T340 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3381076850 Jul 29 05:18:19 PM PDT 24 Jul 29 05:18:22 PM PDT 24 343410273 ps
T87 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.438341971 Jul 29 05:18:02 PM PDT 24 Jul 29 05:18:04 PM PDT 24 315893163 ps
T341 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1419793035 Jul 29 05:18:17 PM PDT 24 Jul 29 05:18:20 PM PDT 24 3558829365 ps
T342 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3597702650 Jul 29 05:17:50 PM PDT 24 Jul 29 05:17:52 PM PDT 24 653909712 ps
T343 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.673965717 Jul 29 05:18:29 PM PDT 24 Jul 29 05:18:34 PM PDT 24 224662110 ps
T344 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.42581205 Jul 29 05:17:53 PM PDT 24 Jul 29 05:18:31 PM PDT 24 36198467922 ps
T345 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3896295458 Jul 29 05:18:08 PM PDT 24 Jul 29 05:18:14 PM PDT 24 3371300605 ps
T153 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.823157100 Jul 29 05:17:50 PM PDT 24 Jul 29 05:18:12 PM PDT 24 2267802852 ps
T346 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3028175818 Jul 29 05:18:16 PM PDT 24 Jul 29 05:18:19 PM PDT 24 445760218 ps
T347 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1329278249 Jul 29 05:17:59 PM PDT 24 Jul 29 05:18:00 PM PDT 24 256440592 ps
T88 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2011952014 Jul 29 05:17:51 PM PDT 24 Jul 29 05:19:07 PM PDT 24 17275369023 ps
T154 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.197383269 Jul 29 05:17:45 PM PDT 24 Jul 29 05:18:06 PM PDT 24 2481996214 ps
T348 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3842638485 Jul 29 05:18:21 PM PDT 24 Jul 29 05:18:23 PM PDT 24 2556414008 ps
T102 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3662961919 Jul 29 05:18:20 PM PDT 24 Jul 29 05:18:28 PM PDT 24 815898380 ps
T53 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3342713684 Jul 29 05:17:59 PM PDT 24 Jul 29 05:24:04 PM PDT 24 31649482598 ps
T349 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3522443675 Jul 29 05:18:30 PM PDT 24 Jul 29 05:18:31 PM PDT 24 247270266 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.459397698 Jul 29 05:17:39 PM PDT 24 Jul 29 05:18:08 PM PDT 24 2455702125 ps
T351 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.953410237 Jul 29 05:17:42 PM PDT 24 Jul 29 05:17:44 PM PDT 24 276129959 ps
T352 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.243806805 Jul 29 05:17:51 PM PDT 24 Jul 29 05:17:52 PM PDT 24 80325554 ps
T353 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3514183277 Jul 29 05:18:06 PM PDT 24 Jul 29 05:18:12 PM PDT 24 634304007 ps
T354 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3404191382 Jul 29 05:17:48 PM PDT 24 Jul 29 05:17:50 PM PDT 24 261304964 ps
T103 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3674896174 Jul 29 05:17:54 PM PDT 24 Jul 29 05:18:01 PM PDT 24 237608746 ps
T355 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1423602460 Jul 29 05:17:52 PM PDT 24 Jul 29 05:17:53 PM PDT 24 350255007 ps
T356 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.496433397 Jul 29 05:17:59 PM PDT 24 Jul 29 05:18:02 PM PDT 24 172413434 ps
T357 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.254477985 Jul 29 05:17:43 PM PDT 24 Jul 29 05:17:45 PM PDT 24 74969999 ps
T358 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1201027152 Jul 29 05:17:45 PM PDT 24 Jul 29 05:18:53 PM PDT 24 23046804119 ps
T359 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.896932466 Jul 29 05:18:16 PM PDT 24 Jul 29 05:18:17 PM PDT 24 123804326 ps
T360 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.430808934 Jul 29 05:17:49 PM PDT 24 Jul 29 05:17:51 PM PDT 24 2282805961 ps
T361 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2397697577 Jul 29 05:17:43 PM PDT 24 Jul 29 05:17:45 PM PDT 24 476954023 ps
T362 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2514589609 Jul 29 05:18:11 PM PDT 24 Jul 29 05:18:33 PM PDT 24 26001783980 ps
T363 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1809593528 Jul 29 05:18:03 PM PDT 24 Jul 29 05:18:04 PM PDT 24 1984426908 ps
T159 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3280360221 Jul 29 05:17:45 PM PDT 24 Jul 29 05:18:05 PM PDT 24 4707668845 ps
T364 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2530736957 Jul 29 05:18:06 PM PDT 24 Jul 29 05:18:07 PM PDT 24 129163784 ps
T89 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2613524286 Jul 29 05:17:53 PM PDT 24 Jul 29 05:17:56 PM PDT 24 371993773 ps
T365 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.984819016 Jul 29 05:18:00 PM PDT 24 Jul 29 05:18:02 PM PDT 24 100344864 ps
T366 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3759955850 Jul 29 05:18:05 PM PDT 24 Jul 29 05:18:25 PM PDT 24 7286497447 ps
T163 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3097199609 Jul 29 05:18:14 PM PDT 24 Jul 29 05:18:26 PM PDT 24 9014716867 ps
T367 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3899206109 Jul 29 05:17:43 PM PDT 24 Jul 29 05:17:45 PM PDT 24 432269089 ps
T368 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.841437617 Jul 29 05:17:54 PM PDT 24 Jul 29 05:18:09 PM PDT 24 10925864414 ps
T369 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.780942719 Jul 29 05:18:03 PM PDT 24 Jul 29 05:20:58 PM PDT 24 118849385590 ps
T104 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2296457769 Jul 29 05:18:08 PM PDT 24 Jul 29 05:18:15 PM PDT 24 625713940 ps
T164 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.244101589 Jul 29 05:17:50 PM PDT 24 Jul 29 05:18:55 PM PDT 24 64768940024 ps
T90 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3457610509 Jul 29 05:17:44 PM PDT 24 Jul 29 05:17:47 PM PDT 24 1621876506 ps
T370 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3045852508 Jul 29 05:17:56 PM PDT 24 Jul 29 05:17:59 PM PDT 24 481437065 ps
T80 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3353381074 Jul 29 05:17:44 PM PDT 24 Jul 29 05:17:49 PM PDT 24 12842082139 ps
T105 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.466022874 Jul 29 05:18:02 PM PDT 24 Jul 29 05:18:09 PM PDT 24 357713629 ps
T157 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.994517519 Jul 29 05:18:00 PM PDT 24 Jul 29 05:18:10 PM PDT 24 798525588 ps
T371 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2744542335 Jul 29 05:18:11 PM PDT 24 Jul 29 05:18:16 PM PDT 24 551916571 ps
T372 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.224644425 Jul 29 05:18:01 PM PDT 24 Jul 29 05:18:02 PM PDT 24 172557642 ps
T93 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3861003701 Jul 29 05:18:03 PM PDT 24 Jul 29 05:18:04 PM PDT 24 253610898 ps
T373 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3423855977 Jul 29 05:18:05 PM PDT 24 Jul 29 05:18:12 PM PDT 24 301438686 ps
T374 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2963933182 Jul 29 05:18:11 PM PDT 24 Jul 29 05:18:16 PM PDT 24 386289703 ps
T91 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3934518982 Jul 29 05:17:43 PM PDT 24 Jul 29 05:17:45 PM PDT 24 99749920 ps
T160 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3819104284 Jul 29 05:17:50 PM PDT 24 Jul 29 05:18:09 PM PDT 24 4201141814 ps
T165 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3610514232 Jul 29 05:17:56 PM PDT 24 Jul 29 05:18:44 PM PDT 24 55323023243 ps
T375 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1814751806 Jul 29 05:18:04 PM PDT 24 Jul 29 05:18:07 PM PDT 24 172671342 ps
T97 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1905848358 Jul 29 05:18:01 PM PDT 24 Jul 29 05:18:34 PM PDT 24 6845239822 ps
T376 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2983914801 Jul 29 05:18:12 PM PDT 24 Jul 29 05:18:13 PM PDT 24 53383228 ps
T377 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.299055102 Jul 29 05:18:18 PM PDT 24 Jul 29 05:18:20 PM PDT 24 1172947312 ps
T92 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1415039888 Jul 29 05:18:14 PM PDT 24 Jul 29 05:18:21 PM PDT 24 175087321 ps
T378 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.267380026 Jul 29 05:17:53 PM PDT 24 Jul 29 05:18:25 PM PDT 24 1985800932 ps
T379 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1023996961 Jul 29 05:18:16 PM PDT 24 Jul 29 05:18:53 PM PDT 24 14727111087 ps
T380 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.276541321 Jul 29 05:17:44 PM PDT 24 Jul 29 05:17:46 PM PDT 24 443997784 ps
T381 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2389071172 Jul 29 05:18:13 PM PDT 24 Jul 29 05:18:14 PM PDT 24 224895852 ps
T382 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.965359657 Jul 29 05:18:01 PM PDT 24 Jul 29 05:18:08 PM PDT 24 7343333145 ps
T383 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3248966417 Jul 29 05:18:21 PM PDT 24 Jul 29 05:18:35 PM PDT 24 2832109006 ps
T384 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.586522175 Jul 29 05:18:18 PM PDT 24 Jul 29 05:18:19 PM PDT 24 527957658 ps
T98 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2711949879 Jul 29 05:18:05 PM PDT 24 Jul 29 05:18:07 PM PDT 24 64036122 ps
T385 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1801926453 Jul 29 05:18:06 PM PDT 24 Jul 29 05:18:09 PM PDT 24 704114372 ps
T386 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.38642314 Jul 29 05:18:22 PM PDT 24 Jul 29 05:18:29 PM PDT 24 7567027783 ps
T387 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1759199497 Jul 29 05:18:00 PM PDT 24 Jul 29 05:18:16 PM PDT 24 8283916132 ps
T388 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2281988533 Jul 29 05:18:16 PM PDT 24 Jul 29 05:18:24 PM PDT 24 2258488593 ps
T389 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1726698891 Jul 29 05:17:55 PM PDT 24 Jul 29 05:18:39 PM PDT 24 51484479596 ps
T390 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4273796589 Jul 29 05:17:45 PM PDT 24 Jul 29 05:18:51 PM PDT 24 4953052765 ps
T391 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3592587264 Jul 29 05:17:40 PM PDT 24 Jul 29 05:17:43 PM PDT 24 2784223537 ps
T392 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3947353434 Jul 29 05:18:08 PM PDT 24 Jul 29 05:18:11 PM PDT 24 222385303 ps
T393 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3598243352 Jul 29 05:17:59 PM PDT 24 Jul 29 05:24:02 PM PDT 24 45591362266 ps
T156 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3104843816 Jul 29 05:18:01 PM PDT 24 Jul 29 05:18:24 PM PDT 24 4185491072 ps
T394 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2091169760 Jul 29 05:17:38 PM PDT 24 Jul 29 05:18:46 PM PDT 24 88971960609 ps
T395 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.93558471 Jul 29 05:18:09 PM PDT 24 Jul 29 05:18:11 PM PDT 24 113354788 ps
T396 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2457959851 Jul 29 05:18:01 PM PDT 24 Jul 29 05:18:16 PM PDT 24 15002188575 ps
T397 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1688245096 Jul 29 05:17:54 PM PDT 24 Jul 29 05:17:57 PM PDT 24 145197946 ps
T398 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1075619000 Jul 29 05:18:30 PM PDT 24 Jul 29 05:18:33 PM PDT 24 379124158 ps
T399 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.475084100 Jul 29 05:18:01 PM PDT 24 Jul 29 05:18:04 PM PDT 24 138890317 ps
T400 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1916346873 Jul 29 05:17:46 PM PDT 24 Jul 29 05:17:47 PM PDT 24 125761978 ps
T401 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1573625045 Jul 29 05:17:46 PM PDT 24 Jul 29 05:17:47 PM PDT 24 113115246 ps
T402 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3776219049 Jul 29 05:17:48 PM PDT 24 Jul 29 05:17:59 PM PDT 24 6356871597 ps
T403 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.587886819 Jul 29 05:17:45 PM PDT 24 Jul 29 05:17:46 PM PDT 24 155697279 ps
T404 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2290621432 Jul 29 05:17:56 PM PDT 24 Jul 29 05:18:00 PM PDT 24 2340118743 ps
T405 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1695682494 Jul 29 05:18:00 PM PDT 24 Jul 29 05:18:06 PM PDT 24 241859535 ps
T406 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1094746112 Jul 29 05:17:54 PM PDT 24 Jul 29 05:17:59 PM PDT 24 1379127741 ps
T407 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2469605715 Jul 29 05:17:43 PM PDT 24 Jul 29 05:19:12 PM PDT 24 28378161249 ps
T408 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.135776436 Jul 29 05:17:40 PM PDT 24 Jul 29 05:17:45 PM PDT 24 5315028301 ps
T409 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1630482481 Jul 29 05:17:41 PM PDT 24 Jul 29 05:18:01 PM PDT 24 28444904291 ps
T410 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.669183237 Jul 29 05:17:56 PM PDT 24 Jul 29 05:17:57 PM PDT 24 1335280070 ps
T411 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1315994749 Jul 29 05:17:52 PM PDT 24 Jul 29 05:20:06 PM PDT 24 88142198006 ps
T412 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3761290252 Jul 29 05:17:43 PM PDT 24 Jul 29 05:17:48 PM PDT 24 2142383657 ps
T413 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.202190600 Jul 29 05:17:47 PM PDT 24 Jul 29 05:17:49 PM PDT 24 153822212 ps
T99 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.270321956 Jul 29 05:17:59 PM PDT 24 Jul 29 05:18:37 PM PDT 24 3826220706 ps
T414 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2253375100 Jul 29 05:17:53 PM PDT 24 Jul 29 05:18:01 PM PDT 24 7137026142 ps
T415 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1365396555 Jul 29 05:18:02 PM PDT 24 Jul 29 05:21:17 PM PDT 24 90832792294 ps
T416 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2924615240 Jul 29 05:17:52 PM PDT 24 Jul 29 05:18:55 PM PDT 24 21028197935 ps
T417 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1972150789 Jul 29 05:17:55 PM PDT 24 Jul 29 05:18:02 PM PDT 24 160700829 ps
T418 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3244549516 Jul 29 05:18:26 PM PDT 24 Jul 29 05:18:34 PM PDT 24 435911264 ps
T419 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1690042193 Jul 29 05:18:17 PM PDT 24 Jul 29 05:18:19 PM PDT 24 143466117 ps
T420 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.119241538 Jul 29 05:17:51 PM PDT 24 Jul 29 05:17:52 PM PDT 24 94902054 ps
T100 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2015239532 Jul 29 05:17:46 PM PDT 24 Jul 29 05:19:01 PM PDT 24 26477076046 ps
T421 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.499422555 Jul 29 05:17:48 PM PDT 24 Jul 29 05:17:49 PM PDT 24 107421454 ps
T94 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1184257524 Jul 29 05:17:50 PM PDT 24 Jul 29 05:17:52 PM PDT 24 145801196 ps
T422 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3008684506 Jul 29 05:17:54 PM PDT 24 Jul 29 05:18:15 PM PDT 24 4980410230 ps
T423 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1013530136 Jul 29 05:18:07 PM PDT 24 Jul 29 05:18:11 PM PDT 24 1031189198 ps
T158 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1026790739 Jul 29 05:17:57 PM PDT 24 Jul 29 05:18:19 PM PDT 24 2429936014 ps
T424 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2009918670 Jul 29 05:18:07 PM PDT 24 Jul 29 05:18:15 PM PDT 24 1346419807 ps
T425 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2415717758 Jul 29 05:18:27 PM PDT 24 Jul 29 05:18:41 PM PDT 24 2905537936 ps
T426 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4010795377 Jul 29 05:18:02 PM PDT 24 Jul 29 05:18:03 PM PDT 24 295203081 ps
T427 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.655633947 Jul 29 05:17:50 PM PDT 24 Jul 29 05:18:27 PM PDT 24 11378466512 ps
T428 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4001711911 Jul 29 05:18:09 PM PDT 24 Jul 29 05:18:12 PM PDT 24 3426865040 ps
T429 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.895530123 Jul 29 05:18:01 PM PDT 24 Jul 29 05:22:14 PM PDT 24 100078284953 ps
T430 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2534635967 Jul 29 05:17:55 PM PDT 24 Jul 29 05:18:00 PM PDT 24 226064472 ps
T431 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4209926054 Jul 29 05:17:48 PM PDT 24 Jul 29 05:17:53 PM PDT 24 505648068 ps
T161 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3903723651 Jul 29 05:18:16 PM PDT 24 Jul 29 05:18:26 PM PDT 24 1535680751 ps
T432 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4044335855 Jul 29 05:17:45 PM PDT 24 Jul 29 05:17:47 PM PDT 24 115887164 ps
T433 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2405524450 Jul 29 05:18:05 PM PDT 24 Jul 29 05:18:12 PM PDT 24 2422103345 ps
T81 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.233270769 Jul 29 05:17:40 PM PDT 24 Jul 29 05:17:44 PM PDT 24 7322178220 ps
T434 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.377988987 Jul 29 05:18:14 PM PDT 24 Jul 29 05:19:21 PM PDT 24 27361203831 ps
T435 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.358790633 Jul 29 05:18:06 PM PDT 24 Jul 29 05:18:08 PM PDT 24 312289886 ps
T436 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2308026933 Jul 29 05:17:43 PM PDT 24 Jul 29 05:17:45 PM PDT 24 1199114896 ps
T437 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1789494265 Jul 29 05:17:53 PM PDT 24 Jul 29 05:17:57 PM PDT 24 93529431 ps
T438 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.729842696 Jul 29 05:18:14 PM PDT 24 Jul 29 05:18:20 PM PDT 24 242315793 ps
T82 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3671053306 Jul 29 05:17:54 PM PDT 24 Jul 29 05:18:01 PM PDT 24 2352475603 ps
T439 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1206342321 Jul 29 05:17:44 PM PDT 24 Jul 29 05:17:59 PM PDT 24 17774368837 ps
T96 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.911498612 Jul 29 05:17:52 PM PDT 24 Jul 29 05:17:56 PM PDT 24 410541686 ps
T440 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.611135923 Jul 29 05:17:50 PM PDT 24 Jul 29 05:17:52 PM PDT 24 272737519 ps
T441 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.4169782789 Jul 29 05:17:50 PM PDT 24 Jul 29 05:17:52 PM PDT 24 972139954 ps
T442 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1393719243 Jul 29 05:18:05 PM PDT 24 Jul 29 05:18:07 PM PDT 24 1658466131 ps
T443 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3223447155 Jul 29 05:18:26 PM PDT 24 Jul 29 05:18:29 PM PDT 24 3146541866 ps
T444 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2721988081 Jul 29 05:17:59 PM PDT 24 Jul 29 05:18:25 PM PDT 24 2924686097 ps
T445 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3234370127 Jul 29 05:18:06 PM PDT 24 Jul 29 05:18:08 PM PDT 24 1072635852 ps
T446 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3721988171 Jul 29 05:18:12 PM PDT 24 Jul 29 05:18:13 PM PDT 24 419797057 ps
T447 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1660314068 Jul 29 05:18:07 PM PDT 24 Jul 29 05:18:12 PM PDT 24 284991862 ps
T448 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3692853624 Jul 29 05:18:17 PM PDT 24 Jul 29 05:18:23 PM PDT 24 2181464272 ps
T449 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1140369592 Jul 29 05:18:28 PM PDT 24 Jul 29 05:18:30 PM PDT 24 488450740 ps
T450 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2565602237 Jul 29 05:18:07 PM PDT 24 Jul 29 05:18:16 PM PDT 24 1535592412 ps
T451 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2962378663 Jul 29 05:18:06 PM PDT 24 Jul 29 05:18:09 PM PDT 24 132462329 ps
T452 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3644462863 Jul 29 05:17:55 PM PDT 24 Jul 29 05:17:58 PM PDT 24 126596737 ps
T453 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.565027332 Jul 29 05:18:02 PM PDT 24 Jul 29 05:18:06 PM PDT 24 754316140 ps
T454 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.103523398 Jul 29 05:17:56 PM PDT 24 Jul 29 05:18:00 PM PDT 24 1301262185 ps
T455 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.370635820 Jul 29 05:17:46 PM PDT 24 Jul 29 05:17:48 PM PDT 24 249638906 ps
T456 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1869683602 Jul 29 05:18:19 PM PDT 24 Jul 29 05:18:26 PM PDT 24 615917394 ps
T457 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3179489984 Jul 29 05:17:50 PM PDT 24 Jul 29 05:18:01 PM PDT 24 15367739003 ps
T458 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4085010941 Jul 29 05:18:19 PM PDT 24 Jul 29 05:18:23 PM PDT 24 180991889 ps
T101 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3383609454 Jul 29 05:17:49 PM PDT 24 Jul 29 05:17:52 PM PDT 24 494655322 ps
T459 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1307000140 Jul 29 05:17:45 PM PDT 24 Jul 29 05:17:53 PM PDT 24 675901926 ps
T95 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3298384783 Jul 29 05:17:43 PM PDT 24 Jul 29 05:18:59 PM PDT 24 14000885299 ps
T460 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1268820711 Jul 29 05:18:17 PM PDT 24 Jul 29 05:18:20 PM PDT 24 299227104 ps
T461 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3457776218 Jul 29 05:17:39 PM PDT 24 Jul 29 05:17:40 PM PDT 24 808205661 ps
T462 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1601831657 Jul 29 05:18:20 PM PDT 24 Jul 29 05:18:22 PM PDT 24 141448305 ps
T463 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2034175314 Jul 29 05:17:50 PM PDT 24 Jul 29 05:17:51 PM PDT 24 1329274041 ps
T464 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3283970807 Jul 29 05:17:56 PM PDT 24 Jul 29 05:17:57 PM PDT 24 35950260 ps
T83 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2133768913 Jul 29 05:17:49 PM PDT 24 Jul 29 05:18:01 PM PDT 24 7549703493 ps
T465 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1815446369 Jul 29 05:17:47 PM PDT 24 Jul 29 05:17:50 PM PDT 24 165529211 ps
T466 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4060905217 Jul 29 05:17:54 PM PDT 24 Jul 29 05:20:51 PM PDT 24 71587903465 ps
T467 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.965975963 Jul 29 05:18:00 PM PDT 24 Jul 29 05:18:02 PM PDT 24 230635845 ps
T468 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.792461052 Jul 29 05:18:28 PM PDT 24 Jul 29 05:18:31 PM PDT 24 376018290 ps

Test location /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.4156871082
Short name T19
Test name
Test status
Simulation time 405999273213 ps
CPU time 2512.64 seconds
Started Jul 29 05:18:56 PM PDT 24
Finished Jul 29 06:00:49 PM PDT 24
Peak memory 254792 kb
Host smart-3979bdea-426b-41a9-88fb-c82ff4cdbbed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156871082 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.4156871082
Directory /workspace/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1180355078
Short name T24
Test name
Test status
Simulation time 87720992307 ps
CPU time 219.97 seconds
Started Jul 29 05:18:47 PM PDT 24
Finished Jul 29 05:22:27 PM PDT 24
Peak memory 217540 kb
Host smart-2b29bcdc-d6e3-4fdd-b5e1-ab73995a1d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180355078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1180355078
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.4130442655
Short name T112
Test name
Test status
Simulation time 1604663687 ps
CPU time 10.02 seconds
Started Jul 29 05:18:06 PM PDT 24
Finished Jul 29 05:18:16 PM PDT 24
Peak memory 213808 kb
Host smart-1f725902-86f4-4b2a-b38e-50b949b12573
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130442655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.4
130442655
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3502667945
Short name T51
Test name
Test status
Simulation time 7548961551 ps
CPU time 6.67 seconds
Started Jul 29 05:18:31 PM PDT 24
Finished Jul 29 05:18:38 PM PDT 24
Peak memory 205708 kb
Host smart-6b2185c7-2f40-480a-9c9a-5095d173f75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502667945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3502667945
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1098889624
Short name T44
Test name
Test status
Simulation time 45570634 ps
CPU time 0.77 seconds
Started Jul 29 05:19:06 PM PDT 24
Finished Jul 29 05:19:07 PM PDT 24
Peak memory 205392 kb
Host smart-3e36788b-6070-4186-8fc1-b1b3c8a7c949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098889624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1098889624
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.1190563063
Short name T65
Test name
Test status
Simulation time 116845947931 ps
CPU time 853.38 seconds
Started Jul 29 05:18:54 PM PDT 24
Finished Jul 29 05:33:07 PM PDT 24
Peak memory 234824 kb
Host smart-3c2db5df-6ba2-479f-879c-fcb02f575f6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190563063 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.1190563063
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.3626642266
Short name T38
Test name
Test status
Simulation time 4831326666 ps
CPU time 8.36 seconds
Started Jul 29 05:19:00 PM PDT 24
Finished Jul 29 05:19:09 PM PDT 24
Peak memory 213804 kb
Host smart-0279297a-4412-4b55-97fd-c4a3bfa60565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626642266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.3626642266
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.483361010
Short name T68
Test name
Test status
Simulation time 131591900 ps
CPU time 2.46 seconds
Started Jul 29 05:18:01 PM PDT 24
Finished Jul 29 05:18:03 PM PDT 24
Peak memory 213788 kb
Host smart-16f4c786-76bf-4693-b52a-31d5687428dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483361010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.483361010
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.2627939447
Short name T114
Test name
Test status
Simulation time 1132451320 ps
CPU time 3.88 seconds
Started Jul 29 05:18:34 PM PDT 24
Finished Jul 29 05:18:38 PM PDT 24
Peak memory 205560 kb
Host smart-a65649dd-cdee-4590-a79e-642f462301f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627939447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.2627939447
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3988752423
Short name T148
Test name
Test status
Simulation time 2611075018 ps
CPU time 8.44 seconds
Started Jul 29 05:19:01 PM PDT 24
Finished Jul 29 05:19:09 PM PDT 24
Peak memory 214180 kb
Host smart-f1a3f9eb-f17b-46da-a6e6-20b906fd8b99
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3988752423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3988752423
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.1688760864
Short name T8
Test name
Test status
Simulation time 117202494937 ps
CPU time 935.31 seconds
Started Jul 29 05:18:55 PM PDT 24
Finished Jul 29 05:34:31 PM PDT 24
Peak memory 235460 kb
Host smart-16e1d725-a575-4ae5-8320-d8db947f22ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688760864 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.1688760864
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.2033482631
Short name T117
Test name
Test status
Simulation time 59745146347 ps
CPU time 121.65 seconds
Started Jul 29 05:18:57 PM PDT 24
Finished Jul 29 05:20:59 PM PDT 24
Peak memory 215056 kb
Host smart-610076ca-4218-43cb-9a06-6d0cbf26525c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033482631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.2033482631
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3520658681
Short name T155
Test name
Test status
Simulation time 4659009782 ps
CPU time 22.59 seconds
Started Jul 29 05:18:01 PM PDT 24
Finished Jul 29 05:18:24 PM PDT 24
Peak memory 213868 kb
Host smart-3b79a512-77fb-470f-a3a7-647894ef1bcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520658681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3520658681
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.422165830
Short name T26
Test name
Test status
Simulation time 2944557942 ps
CPU time 4.56 seconds
Started Jul 29 05:18:34 PM PDT 24
Finished Jul 29 05:18:39 PM PDT 24
Peak memory 229944 kb
Host smart-ef285b84-522c-40ac-821f-896839a5fa10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422165830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.422165830
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.720977645
Short name T72
Test name
Test status
Simulation time 250139571 ps
CPU time 1.69 seconds
Started Jul 29 05:18:37 PM PDT 24
Finished Jul 29 05:18:39 PM PDT 24
Peak memory 213840 kb
Host smart-08e90201-5843-4c3f-a469-2bc626ac2a69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720977645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.720977645
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3054915514
Short name T16
Test name
Test status
Simulation time 1028308415 ps
CPU time 1.36 seconds
Started Jul 29 05:18:28 PM PDT 24
Finished Jul 29 05:18:30 PM PDT 24
Peak memory 205388 kb
Host smart-3ff4385a-71e0-47bf-8508-831d7b487463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054915514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3054915514
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.1144096531
Short name T48
Test name
Test status
Simulation time 135060990 ps
CPU time 1.02 seconds
Started Jul 29 05:18:40 PM PDT 24
Finished Jul 29 05:18:41 PM PDT 24
Peak memory 205320 kb
Host smart-b7fa5f8b-6ef6-4e64-b7fa-fb3a8d490612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144096531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.1144096531
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.439517560
Short name T14
Test name
Test status
Simulation time 6260426481 ps
CPU time 9.67 seconds
Started Jul 29 05:19:12 PM PDT 24
Finished Jul 29 05:19:22 PM PDT 24
Peak memory 213748 kb
Host smart-9b504bde-ff2f-4db7-8bad-bf9b3b5b395f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439517560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.439517560
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2556179201
Short name T61
Test name
Test status
Simulation time 16698522136 ps
CPU time 9.64 seconds
Started Jul 29 05:18:56 PM PDT 24
Finished Jul 29 05:19:06 PM PDT 24
Peak memory 222168 kb
Host smart-7c4a8abf-68ef-4d4d-a5fa-32d90bd27cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556179201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2556179201
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.479848453
Short name T40
Test name
Test status
Simulation time 4224899012 ps
CPU time 4.64 seconds
Started Jul 29 05:19:19 PM PDT 24
Finished Jul 29 05:19:23 PM PDT 24
Peak memory 222256 kb
Host smart-3d3937d8-7b35-42ea-8832-951498246aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479848453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.479848453
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.226449182
Short name T32
Test name
Test status
Simulation time 128265393 ps
CPU time 1.03 seconds
Started Jul 29 05:18:35 PM PDT 24
Finished Jul 29 05:18:36 PM PDT 24
Peak memory 213612 kb
Host smart-dcf928c0-d45c-413b-a5ac-e2e1e20a7587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226449182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.226449182
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3104843816
Short name T156
Test name
Test status
Simulation time 4185491072 ps
CPU time 23.77 seconds
Started Jul 29 05:18:01 PM PDT 24
Finished Jul 29 05:18:24 PM PDT 24
Peak memory 213864 kb
Host smart-e1c94016-1d06-499b-a5e7-0d8ed766a731
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104843816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3104843816
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2150622066
Short name T129
Test name
Test status
Simulation time 15879018387 ps
CPU time 33.16 seconds
Started Jul 29 05:18:54 PM PDT 24
Finished Jul 29 05:19:27 PM PDT 24
Peak memory 214012 kb
Host smart-83c23557-177f-48ac-87af-fa066c6b396c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150622066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2150622066
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.1380809595
Short name T6
Test name
Test status
Simulation time 4170590265 ps
CPU time 9.84 seconds
Started Jul 29 05:19:00 PM PDT 24
Finished Jul 29 05:19:10 PM PDT 24
Peak memory 213832 kb
Host smart-2ff6fddd-9aba-489f-a0f5-729135c1d742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380809595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.1380809595
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.3500293769
Short name T23
Test name
Test status
Simulation time 308083397 ps
CPU time 1.51 seconds
Started Jul 29 05:18:32 PM PDT 24
Finished Jul 29 05:18:34 PM PDT 24
Peak memory 205320 kb
Host smart-904db74e-bda2-4231-8271-00faef8c758a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500293769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3500293769
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.1630482481
Short name T409
Test name
Test status
Simulation time 28444904291 ps
CPU time 19.72 seconds
Started Jul 29 05:17:41 PM PDT 24
Finished Jul 29 05:18:01 PM PDT 24
Peak memory 217060 kb
Host smart-ffb7cef3-14ab-4786-a7db-b1097818b3cb
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630482481 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.1630482481
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.2246285852
Short name T126
Test name
Test status
Simulation time 5619787834 ps
CPU time 5.31 seconds
Started Jul 29 05:19:09 PM PDT 24
Finished Jul 29 05:19:14 PM PDT 24
Peak memory 213856 kb
Host smart-c031710e-d374-401b-afe8-47b703229ae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246285852 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2246285852
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2112251259
Short name T145
Test name
Test status
Simulation time 6523157873 ps
CPU time 19.36 seconds
Started Jul 29 05:19:04 PM PDT 24
Finished Jul 29 05:19:24 PM PDT 24
Peak memory 213848 kb
Host smart-eedc161a-c756-4aec-b352-d5b27624e32c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112251259 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2112251259
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1587137147
Short name T324
Test name
Test status
Simulation time 849756498 ps
CPU time 1.33 seconds
Started Jul 29 05:17:39 PM PDT 24
Finished Jul 29 05:17:40 PM PDT 24
Peak memory 205364 kb
Host smart-7036607a-18ee-423f-b430-26865f6185ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587137147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1587137147
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3536770407
Short name T41
Test name
Test status
Simulation time 232429414 ps
CPU time 0.99 seconds
Started Jul 29 05:18:34 PM PDT 24
Finished Jul 29 05:18:35 PM PDT 24
Peak memory 205404 kb
Host smart-2aa3a7c3-b18c-401f-826b-e01a1a8f55db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536770407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3536770407
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.233270769
Short name T81
Test name
Test status
Simulation time 7322178220 ps
CPU time 4.43 seconds
Started Jul 29 05:17:40 PM PDT 24
Finished Jul 29 05:17:44 PM PDT 24
Peak memory 205564 kb
Host smart-f9cf9a07-4d70-4d5a-98ae-033078af3014
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233270769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.233270769
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.3767504145
Short name T70
Test name
Test status
Simulation time 307212842 ps
CPU time 6.48 seconds
Started Jul 29 05:17:46 PM PDT 24
Finished Jul 29 05:17:52 PM PDT 24
Peak memory 205664 kb
Host smart-b0fb49c7-18c0-41f7-bcb7-182ae3ae217e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767504145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.3767504145
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2312692958
Short name T31
Test name
Test status
Simulation time 567687494 ps
CPU time 1.06 seconds
Started Jul 29 05:18:28 PM PDT 24
Finished Jul 29 05:18:29 PM PDT 24
Peak memory 205388 kb
Host smart-8b3546d5-7b62-4dc9-aef5-c7b4fcfd45ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312692958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2312692958
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3475215425
Short name T162
Test name
Test status
Simulation time 1395186022 ps
CPU time 11.66 seconds
Started Jul 29 05:18:07 PM PDT 24
Finished Jul 29 05:18:18 PM PDT 24
Peak memory 213796 kb
Host smart-34c041ad-6341-400b-b5a3-dc25cdade26a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475215425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
475215425
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2348658943
Short name T150
Test name
Test status
Simulation time 11985040893 ps
CPU time 16.41 seconds
Started Jul 29 05:18:56 PM PDT 24
Finished Jul 29 05:19:13 PM PDT 24
Peak memory 205844 kb
Host smart-e4543207-e196-4cc3-95ed-a922073a0773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348658943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2348658943
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.2426504258
Short name T133
Test name
Test status
Simulation time 4912551876 ps
CPU time 5.92 seconds
Started Jul 29 05:18:46 PM PDT 24
Finished Jul 29 05:18:52 PM PDT 24
Peak memory 213864 kb
Host smart-0e56e24b-c54a-4015-9af0-bf946fe117f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426504258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.2426504258
Directory /workspace/9.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3298384783
Short name T95
Test name
Test status
Simulation time 14000885299 ps
CPU time 75.59 seconds
Started Jul 29 05:17:43 PM PDT 24
Finished Jul 29 05:18:59 PM PDT 24
Peak memory 213744 kb
Host smart-c443dddd-b556-4d0d-aa23-a5d5c09c713c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298384783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3298384783
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.459397698
Short name T350
Test name
Test status
Simulation time 2455702125 ps
CPU time 28.38 seconds
Started Jul 29 05:17:39 PM PDT 24
Finished Jul 29 05:18:08 PM PDT 24
Peak memory 205656 kb
Host smart-ea95f0e8-d611-4938-8797-e41207a4e7ba
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459397698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.459397698
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.4273796589
Short name T390
Test name
Test status
Simulation time 4953052765 ps
CPU time 64.75 seconds
Started Jul 29 05:17:45 PM PDT 24
Finished Jul 29 05:18:51 PM PDT 24
Peak memory 213840 kb
Host smart-14435f65-c6f1-46af-9afc-181cb7a8f026
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273796589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.4273796589
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3934518982
Short name T91
Test name
Test status
Simulation time 99749920 ps
CPU time 1.69 seconds
Started Jul 29 05:17:43 PM PDT 24
Finished Jul 29 05:17:45 PM PDT 24
Peak memory 213832 kb
Host smart-b3a3c157-4487-41f2-ab7b-d1a7c8ef861a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934518982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3934518982
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.202190600
Short name T413
Test name
Test status
Simulation time 153822212 ps
CPU time 2.48 seconds
Started Jul 29 05:17:47 PM PDT 24
Finished Jul 29 05:17:49 PM PDT 24
Peak memory 222044 kb
Host smart-748953e3-6fcd-4623-b43b-46d673607fe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202190600 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.202190600
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.370635820
Short name T455
Test name
Test status
Simulation time 249638906 ps
CPU time 1.66 seconds
Started Jul 29 05:17:46 PM PDT 24
Finished Jul 29 05:17:48 PM PDT 24
Peak memory 213760 kb
Host smart-7970f0e9-3994-47a3-a511-b1c345b51dbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370635820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.370635820
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.2091169760
Short name T394
Test name
Test status
Simulation time 88971960609 ps
CPU time 67.86 seconds
Started Jul 29 05:17:38 PM PDT 24
Finished Jul 29 05:18:46 PM PDT 24
Peak memory 205520 kb
Host smart-1d87736c-8e83-4413-baad-8f47c630d4cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091169760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.2091169760
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.95421605
Short name T314
Test name
Test status
Simulation time 10664046171 ps
CPU time 30.54 seconds
Started Jul 29 05:17:41 PM PDT 24
Finished Jul 29 05:18:12 PM PDT 24
Peak memory 205484 kb
Host smart-eb18a510-d070-46be-ace7-19c8f3589f4c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95421605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv
_dm_jtag_dmi_csr_bit_bash.95421605
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3592587264
Short name T391
Test name
Test status
Simulation time 2784223537 ps
CPU time 3 seconds
Started Jul 29 05:17:40 PM PDT 24
Finished Jul 29 05:17:43 PM PDT 24
Peak memory 205520 kb
Host smart-e25685d9-176c-4ffe-b755-2fe8dc7d5701
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592587264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
592587264
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3457776218
Short name T461
Test name
Test status
Simulation time 808205661 ps
CPU time 1.19 seconds
Started Jul 29 05:17:39 PM PDT 24
Finished Jul 29 05:17:40 PM PDT 24
Peak memory 205364 kb
Host smart-8d5c3825-f03e-4791-b3fa-e455d3a68ba3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457776218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3457776218
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.135776436
Short name T408
Test name
Test status
Simulation time 5315028301 ps
CPU time 4.94 seconds
Started Jul 29 05:17:40 PM PDT 24
Finished Jul 29 05:17:45 PM PDT 24
Peak memory 205540 kb
Host smart-fcc359e0-8a5e-4008-87b2-a5765b65ff40
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135776436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.135776436
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.953410237
Short name T351
Test name
Test status
Simulation time 276129959 ps
CPU time 1.23 seconds
Started Jul 29 05:17:42 PM PDT 24
Finished Jul 29 05:17:44 PM PDT 24
Peak memory 205292 kb
Host smart-13ca4584-5258-461b-b37b-ec72cb7c9323
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953410237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.953410237
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.587886819
Short name T403
Test name
Test status
Simulation time 155697279 ps
CPU time 0.75 seconds
Started Jul 29 05:17:45 PM PDT 24
Finished Jul 29 05:17:46 PM PDT 24
Peak memory 205396 kb
Host smart-ae0dfbe2-b4f8-4c3f-a3ae-132c319c1669
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587886819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.587886819
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.254477985
Short name T357
Test name
Test status
Simulation time 74969999 ps
CPU time 0.82 seconds
Started Jul 29 05:17:43 PM PDT 24
Finished Jul 29 05:17:45 PM PDT 24
Peak memory 205268 kb
Host smart-8277b11f-4cd6-4dab-acc5-93b4aeec5dc0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254477985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.254477985
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1307000140
Short name T459
Test name
Test status
Simulation time 675901926 ps
CPU time 8.05 seconds
Started Jul 29 05:17:45 PM PDT 24
Finished Jul 29 05:17:53 PM PDT 24
Peak memory 205588 kb
Host smart-a8db386c-93d3-426a-a7f5-b9f212e332d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307000140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1307000140
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.4024637720
Short name T331
Test name
Test status
Simulation time 1087951656 ps
CPU time 6.34 seconds
Started Jul 29 05:17:38 PM PDT 24
Finished Jul 29 05:17:45 PM PDT 24
Peak memory 213892 kb
Host smart-a38c30ce-356d-438a-b246-03436a90380d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024637720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.4024637720
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3280360221
Short name T159
Test name
Test status
Simulation time 4707668845 ps
CPU time 19.85 seconds
Started Jul 29 05:17:45 PM PDT 24
Finished Jul 29 05:18:05 PM PDT 24
Peak memory 213892 kb
Host smart-2267350d-a334-4afc-bf92-b9a82a9f9938
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280360221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3280360221
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2015239532
Short name T100
Test name
Test status
Simulation time 26477076046 ps
CPU time 73.96 seconds
Started Jul 29 05:17:46 PM PDT 24
Finished Jul 29 05:19:01 PM PDT 24
Peak memory 213860 kb
Host smart-162aac7a-1939-4038-82b4-e5793d94bc1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015239532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2015239532
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2397697577
Short name T361
Test name
Test status
Simulation time 476954023 ps
CPU time 1.94 seconds
Started Jul 29 05:17:43 PM PDT 24
Finished Jul 29 05:17:45 PM PDT 24
Peak memory 213872 kb
Host smart-6759f2a9-3880-4b0c-9e57-f19153a9469c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397697577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2397697577
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3404191382
Short name T354
Test name
Test status
Simulation time 261304964 ps
CPU time 2.19 seconds
Started Jul 29 05:17:48 PM PDT 24
Finished Jul 29 05:17:50 PM PDT 24
Peak memory 215836 kb
Host smart-a973b6b4-35b9-4f93-8670-f23e617104ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404191382 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3404191382
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.3457610509
Short name T90
Test name
Test status
Simulation time 1621876506 ps
CPU time 2.74 seconds
Started Jul 29 05:17:44 PM PDT 24
Finished Jul 29 05:17:47 PM PDT 24
Peak memory 213812 kb
Host smart-f4647665-602a-4cd1-b647-8c7cf56ff077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457610509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.3457610509
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1201027152
Short name T358
Test name
Test status
Simulation time 23046804119 ps
CPU time 68.57 seconds
Started Jul 29 05:17:45 PM PDT 24
Finished Jul 29 05:18:53 PM PDT 24
Peak memory 205552 kb
Host smart-f4be044c-9ddc-46b1-bc40-adf835157a36
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201027152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1201027152
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2662347117
Short name T330
Test name
Test status
Simulation time 5788913356 ps
CPU time 18.86 seconds
Started Jul 29 05:17:44 PM PDT 24
Finished Jul 29 05:18:03 PM PDT 24
Peak memory 205516 kb
Host smart-5da033b0-a55e-4198-85be-2f201de561d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662347117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.2662347117
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3353381074
Short name T80
Test name
Test status
Simulation time 12842082139 ps
CPU time 5.53 seconds
Started Jul 29 05:17:44 PM PDT 24
Finished Jul 29 05:17:49 PM PDT 24
Peak memory 205608 kb
Host smart-9e6aea74-34a1-4b96-ad3b-f56a3094a177
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353381074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3353381074
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3761290252
Short name T412
Test name
Test status
Simulation time 2142383657 ps
CPU time 4.45 seconds
Started Jul 29 05:17:43 PM PDT 24
Finished Jul 29 05:17:48 PM PDT 24
Peak memory 205460 kb
Host smart-c54ef1d7-903f-41c9-b023-d4d8db7e2410
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761290252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
761290252
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2308026933
Short name T436
Test name
Test status
Simulation time 1199114896 ps
CPU time 1.21 seconds
Started Jul 29 05:17:43 PM PDT 24
Finished Jul 29 05:17:45 PM PDT 24
Peak memory 205260 kb
Host smart-80eacf71-c9eb-48b6-9452-30b427fc227d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308026933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2308026933
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1206342321
Short name T439
Test name
Test status
Simulation time 17774368837 ps
CPU time 14.65 seconds
Started Jul 29 05:17:44 PM PDT 24
Finished Jul 29 05:17:59 PM PDT 24
Peak memory 205528 kb
Host smart-7ec86c83-f66b-460e-a410-ba26d063f553
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206342321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1206342321
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4044335855
Short name T432
Test name
Test status
Simulation time 115887164 ps
CPU time 0.85 seconds
Started Jul 29 05:17:45 PM PDT 24
Finished Jul 29 05:17:47 PM PDT 24
Peak memory 205360 kb
Host smart-10ca1a98-7826-4ef5-aaea-36ca04454094
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044335855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.4044335855
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3899206109
Short name T367
Test name
Test status
Simulation time 432269089 ps
CPU time 0.88 seconds
Started Jul 29 05:17:43 PM PDT 24
Finished Jul 29 05:17:45 PM PDT 24
Peak memory 205284 kb
Host smart-2c3af638-2530-4df9-8632-571cf3a06296
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899206109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
899206109
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.1916346873
Short name T400
Test name
Test status
Simulation time 125761978 ps
CPU time 0.77 seconds
Started Jul 29 05:17:46 PM PDT 24
Finished Jul 29 05:17:47 PM PDT 24
Peak memory 205388 kb
Host smart-b5d518f5-3fba-4ed0-9f2e-3072050f2f4b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916346873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.1916346873
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.737671874
Short name T315
Test name
Test status
Simulation time 100842715 ps
CPU time 0.71 seconds
Started Jul 29 05:17:47 PM PDT 24
Finished Jul 29 05:17:47 PM PDT 24
Peak memory 205292 kb
Host smart-b0953a09-c15a-4c1c-aa98-89c67d8f90a3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737671874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.737671874
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2469605715
Short name T407
Test name
Test status
Simulation time 28378161249 ps
CPU time 87.89 seconds
Started Jul 29 05:17:43 PM PDT 24
Finished Jul 29 05:19:12 PM PDT 24
Peak memory 222148 kb
Host smart-d2b9381f-3ebf-4470-80fc-620d1dc0ef70
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469605715 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2469605715
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1815446369
Short name T465
Test name
Test status
Simulation time 165529211 ps
CPU time 2.54 seconds
Started Jul 29 05:17:47 PM PDT 24
Finished Jul 29 05:17:50 PM PDT 24
Peak memory 213932 kb
Host smart-cb08f1d8-c8b1-4246-acd5-b89493cd3e30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815446369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1815446369
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.197383269
Short name T154
Test name
Test status
Simulation time 2481996214 ps
CPU time 21.58 seconds
Started Jul 29 05:17:45 PM PDT 24
Finished Jul 29 05:18:06 PM PDT 24
Peak memory 213884 kb
Host smart-6a5db89b-9bd4-43b4-b6cf-aadb937bce84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197383269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.197383269
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3947353434
Short name T392
Test name
Test status
Simulation time 222385303 ps
CPU time 2.35 seconds
Started Jul 29 05:18:08 PM PDT 24
Finished Jul 29 05:18:11 PM PDT 24
Peak memory 214064 kb
Host smart-fc1cf826-27ee-4554-bbb0-a06ccfaaeeea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947353434 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3947353434
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2711949879
Short name T98
Test name
Test status
Simulation time 64036122 ps
CPU time 1.47 seconds
Started Jul 29 05:18:05 PM PDT 24
Finished Jul 29 05:18:07 PM PDT 24
Peak memory 213732 kb
Host smart-c91cb221-41c3-46f5-8c18-0a1e4adf082c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711949879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2711949879
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.1587039425
Short name T312
Test name
Test status
Simulation time 4498454369 ps
CPU time 8.98 seconds
Started Jul 29 05:18:04 PM PDT 24
Finished Jul 29 05:18:13 PM PDT 24
Peak memory 205576 kb
Host smart-23019b04-bf6f-4b08-b46c-d1e34005aa3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587039425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.1587039425
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2405524450
Short name T433
Test name
Test status
Simulation time 2422103345 ps
CPU time 7.1 seconds
Started Jul 29 05:18:05 PM PDT 24
Finished Jul 29 05:18:12 PM PDT 24
Peak memory 205628 kb
Host smart-628583de-8ccc-4abc-9fe9-7f80e7adaacc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405524450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2405524450
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1013530136
Short name T423
Test name
Test status
Simulation time 1031189198 ps
CPU time 3.35 seconds
Started Jul 29 05:18:07 PM PDT 24
Finished Jul 29 05:18:11 PM PDT 24
Peak memory 205216 kb
Host smart-ba03847b-ea18-4198-9dd0-a81a2e474a31
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013530136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1013530136
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2009918670
Short name T424
Test name
Test status
Simulation time 1346419807 ps
CPU time 7.61 seconds
Started Jul 29 05:18:07 PM PDT 24
Finished Jul 29 05:18:15 PM PDT 24
Peak memory 205616 kb
Host smart-6eb40561-5bd5-46e7-b179-5fed9d27671d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009918670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2009918670
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1814751806
Short name T375
Test name
Test status
Simulation time 172671342 ps
CPU time 2.74 seconds
Started Jul 29 05:18:04 PM PDT 24
Finished Jul 29 05:18:07 PM PDT 24
Peak memory 213908 kb
Host smart-9f233dce-612a-485d-98be-e60d798a3054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814751806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1814751806
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.358790633
Short name T435
Test name
Test status
Simulation time 312289886 ps
CPU time 2.39 seconds
Started Jul 29 05:18:06 PM PDT 24
Finished Jul 29 05:18:08 PM PDT 24
Peak memory 218260 kb
Host smart-8e507187-dc80-4c51-8c5f-e69787ca3470
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358790633 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.358790633
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.93558471
Short name T395
Test name
Test status
Simulation time 113354788 ps
CPU time 2.35 seconds
Started Jul 29 05:18:09 PM PDT 24
Finished Jul 29 05:18:11 PM PDT 24
Peak memory 213988 kb
Host smart-1aada8a6-2ec5-4daf-ab64-5b389c52cc5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93558471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.93558471
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.1393719243
Short name T442
Test name
Test status
Simulation time 1658466131 ps
CPU time 1.8 seconds
Started Jul 29 05:18:05 PM PDT 24
Finished Jul 29 05:18:07 PM PDT 24
Peak memory 205488 kb
Host smart-f44975df-8587-4c15-a234-6c7ea48b4d84
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393719243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.1393719243
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3234370127
Short name T445
Test name
Test status
Simulation time 1072635852 ps
CPU time 1.92 seconds
Started Jul 29 05:18:06 PM PDT 24
Finished Jul 29 05:18:08 PM PDT 24
Peak memory 205496 kb
Host smart-75d7e8fb-d8a7-4887-814a-2d2bc81470d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234370127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3234370127
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.703767150
Short name T56
Test name
Test status
Simulation time 190251397 ps
CPU time 0.74 seconds
Started Jul 29 05:18:05 PM PDT 24
Finished Jul 29 05:18:06 PM PDT 24
Peak memory 205308 kb
Host smart-26db0d6a-d51e-43eb-beaa-2d8788e5a330
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703767150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.703767150
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1660314068
Short name T447
Test name
Test status
Simulation time 284991862 ps
CPU time 4.43 seconds
Started Jul 29 05:18:07 PM PDT 24
Finished Jul 29 05:18:12 PM PDT 24
Peak memory 205664 kb
Host smart-65632efe-99bb-47e5-849b-d11190231c36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660314068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1660314068
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.4272747627
Short name T316
Test name
Test status
Simulation time 76021793 ps
CPU time 4.01 seconds
Started Jul 29 05:18:06 PM PDT 24
Finished Jul 29 05:18:10 PM PDT 24
Peak memory 214072 kb
Host smart-2b20a622-7992-479e-8016-f8f46ec38d29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272747627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.4272747627
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1982142762
Short name T338
Test name
Test status
Simulation time 529110990 ps
CPU time 3.57 seconds
Started Jul 29 05:18:05 PM PDT 24
Finished Jul 29 05:18:08 PM PDT 24
Peak memory 219404 kb
Host smart-1af36963-7029-4cd1-95d7-e81a365e32ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982142762 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1982142762
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1207683007
Short name T77
Test name
Test status
Simulation time 192051979 ps
CPU time 1.44 seconds
Started Jul 29 05:18:07 PM PDT 24
Finished Jul 29 05:18:08 PM PDT 24
Peak memory 213712 kb
Host smart-d44b859b-707f-4b6c-9355-1ed8439f76a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207683007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1207683007
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2514589609
Short name T362
Test name
Test status
Simulation time 26001783980 ps
CPU time 21.9 seconds
Started Jul 29 05:18:11 PM PDT 24
Finished Jul 29 05:18:33 PM PDT 24
Peak memory 205576 kb
Host smart-25bec591-5feb-4141-bea6-d874b1e8d7b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514589609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2514589609
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3759955850
Short name T366
Test name
Test status
Simulation time 7286497447 ps
CPU time 19.22 seconds
Started Jul 29 05:18:05 PM PDT 24
Finished Jul 29 05:18:25 PM PDT 24
Peak memory 205576 kb
Host smart-35a3ef72-f760-4b66-af43-9354bee6ce9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759955850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3759955850
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2530736957
Short name T364
Test name
Test status
Simulation time 129163784 ps
CPU time 1.03 seconds
Started Jul 29 05:18:06 PM PDT 24
Finished Jul 29 05:18:07 PM PDT 24
Peak memory 205296 kb
Host smart-39792a02-b20a-4cc4-b31d-498a50bdd88b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530736957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2530736957
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2296457769
Short name T104
Test name
Test status
Simulation time 625713940 ps
CPU time 7.02 seconds
Started Jul 29 05:18:08 PM PDT 24
Finished Jul 29 05:18:15 PM PDT 24
Peak memory 205620 kb
Host smart-ef4b419d-adcb-4960-996e-0d6d1aa25981
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296457769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2296457769
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1801926453
Short name T385
Test name
Test status
Simulation time 704114372 ps
CPU time 2.93 seconds
Started Jul 29 05:18:06 PM PDT 24
Finished Jul 29 05:18:09 PM PDT 24
Peak memory 213908 kb
Host smart-3017084e-d1d4-4bf4-bf89-37b1a393fbea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801926453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1801926453
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2565602237
Short name T450
Test name
Test status
Simulation time 1535592412 ps
CPU time 9.7 seconds
Started Jul 29 05:18:07 PM PDT 24
Finished Jul 29 05:18:16 PM PDT 24
Peak memory 213760 kb
Host smart-d62eb10c-b8b3-4fd3-8672-6349059d9578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565602237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
565602237
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2369753281
Short name T328
Test name
Test status
Simulation time 236220565 ps
CPU time 3.85 seconds
Started Jul 29 05:18:15 PM PDT 24
Finished Jul 29 05:18:19 PM PDT 24
Peak memory 222012 kb
Host smart-df3a20ac-3423-48c7-84d1-b7f010d3f598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369753281 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2369753281
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.25435000
Short name T86
Test name
Test status
Simulation time 125847222 ps
CPU time 1.54 seconds
Started Jul 29 05:18:20 PM PDT 24
Finished Jul 29 05:18:22 PM PDT 24
Peak memory 213724 kb
Host smart-4c67ddb3-1074-4c58-bbbd-e2b0f15838c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25435000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.25435000
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3896295458
Short name T345
Test name
Test status
Simulation time 3371300605 ps
CPU time 5.96 seconds
Started Jul 29 05:18:08 PM PDT 24
Finished Jul 29 05:18:14 PM PDT 24
Peak memory 205552 kb
Host smart-f9b7fdb0-8a8d-4022-8405-adda2549d1b5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896295458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.3896295458
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.4001711911
Short name T428
Test name
Test status
Simulation time 3426865040 ps
CPU time 3.27 seconds
Started Jul 29 05:18:09 PM PDT 24
Finished Jul 29 05:18:12 PM PDT 24
Peak memory 205724 kb
Host smart-8b2b6e1b-1af3-4af9-8bbc-b6232cf6f79c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001711911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
4001711911
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.294978728
Short name T55
Test name
Test status
Simulation time 689337774 ps
CPU time 1.52 seconds
Started Jul 29 05:18:06 PM PDT 24
Finished Jul 29 05:18:07 PM PDT 24
Peak memory 205252 kb
Host smart-7eef36e9-394a-4313-a4ff-686bba0f8bcd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294978728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.294978728
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3244549516
Short name T418
Test name
Test status
Simulation time 435911264 ps
CPU time 7.77 seconds
Started Jul 29 05:18:26 PM PDT 24
Finished Jul 29 05:18:34 PM PDT 24
Peak memory 205532 kb
Host smart-2b207172-2a12-479a-b0e4-b54ecede2fe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244549516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3244549516
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3514183277
Short name T353
Test name
Test status
Simulation time 634304007 ps
CPU time 5.19 seconds
Started Jul 29 05:18:06 PM PDT 24
Finished Jul 29 05:18:12 PM PDT 24
Peak memory 213844 kb
Host smart-4f525b9a-6fbb-4412-a509-e416c9c6683e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514183277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3514183277
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.879662512
Short name T111
Test name
Test status
Simulation time 687006051 ps
CPU time 9.39 seconds
Started Jul 29 05:18:07 PM PDT 24
Finished Jul 29 05:18:16 PM PDT 24
Peak memory 213880 kb
Host smart-c23a09d3-1889-48af-835f-1e89d288c6d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879662512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.879662512
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3830021132
Short name T336
Test name
Test status
Simulation time 413083583 ps
CPU time 2.3 seconds
Started Jul 29 05:18:11 PM PDT 24
Finished Jul 29 05:18:14 PM PDT 24
Peak memory 217200 kb
Host smart-c9269abd-75b8-45ca-aa04-43cfcd098d55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830021132 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3830021132
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.792461052
Short name T468
Test name
Test status
Simulation time 376018290 ps
CPU time 2.52 seconds
Started Jul 29 05:18:28 PM PDT 24
Finished Jul 29 05:18:31 PM PDT 24
Peak memory 213704 kb
Host smart-36c3959d-4981-4c47-82cf-ee2016a7ca22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792461052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.792461052
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.377988987
Short name T434
Test name
Test status
Simulation time 27361203831 ps
CPU time 67.07 seconds
Started Jul 29 05:18:14 PM PDT 24
Finished Jul 29 05:19:21 PM PDT 24
Peak memory 205528 kb
Host smart-20a64aa8-a983-4d4f-84fe-30e3b76ead04
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377988987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
rv_dm_jtag_dmi_csr_bit_bash.377988987
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3223447155
Short name T443
Test name
Test status
Simulation time 3146541866 ps
CPU time 3.01 seconds
Started Jul 29 05:18:26 PM PDT 24
Finished Jul 29 05:18:29 PM PDT 24
Peak memory 205468 kb
Host smart-44c515a5-b683-412d-9366-bd8bc1cdf672
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223447155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3223447155
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3721988171
Short name T446
Test name
Test status
Simulation time 419797057 ps
CPU time 0.9 seconds
Started Jul 29 05:18:12 PM PDT 24
Finished Jul 29 05:18:13 PM PDT 24
Peak memory 205208 kb
Host smart-50a505c6-045f-4584-b06c-4228329ecf4c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721988171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
3721988171
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1415039888
Short name T92
Test name
Test status
Simulation time 175087321 ps
CPU time 6.54 seconds
Started Jul 29 05:18:14 PM PDT 24
Finished Jul 29 05:18:21 PM PDT 24
Peak memory 205632 kb
Host smart-37b2f6c8-7089-4b2b-a974-4a72eb782137
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415039888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1415039888
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3028175818
Short name T346
Test name
Test status
Simulation time 445760218 ps
CPU time 3.27 seconds
Started Jul 29 05:18:16 PM PDT 24
Finished Jul 29 05:18:19 PM PDT 24
Peak memory 213888 kb
Host smart-b752d351-a984-46dd-ba97-0d33e07cea49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028175818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3028175818
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3903723651
Short name T161
Test name
Test status
Simulation time 1535680751 ps
CPU time 10.25 seconds
Started Jul 29 05:18:16 PM PDT 24
Finished Jul 29 05:18:26 PM PDT 24
Peak memory 213752 kb
Host smart-84f2da68-c3aa-4ece-aefd-23d60f850f87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903723651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
903723651
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.2963933182
Short name T374
Test name
Test status
Simulation time 386289703 ps
CPU time 3.98 seconds
Started Jul 29 05:18:11 PM PDT 24
Finished Jul 29 05:18:16 PM PDT 24
Peak memory 219352 kb
Host smart-d02ef9a9-2109-44a2-b920-895aa48fee6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963933182 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.2963933182
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.1268820711
Short name T460
Test name
Test status
Simulation time 299227104 ps
CPU time 2.51 seconds
Started Jul 29 05:18:17 PM PDT 24
Finished Jul 29 05:18:20 PM PDT 24
Peak memory 213800 kb
Host smart-5fa06be3-3e4b-4a67-b9c3-b80fd497cc37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268820711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.1268820711
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2983914801
Short name T376
Test name
Test status
Simulation time 53383228 ps
CPU time 0.74 seconds
Started Jul 29 05:18:12 PM PDT 24
Finished Jul 29 05:18:13 PM PDT 24
Peak memory 205356 kb
Host smart-329d215e-efb3-4324-a177-b80fe4da66e6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983914801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.2983914801
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.4021705357
Short name T313
Test name
Test status
Simulation time 6330998238 ps
CPU time 16.26 seconds
Started Jul 29 05:18:15 PM PDT 24
Finished Jul 29 05:18:32 PM PDT 24
Peak memory 205536 kb
Host smart-7c060d29-a30d-4dad-b3b2-61bd16ec3272
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021705357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
4021705357
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.896932466
Short name T359
Test name
Test status
Simulation time 123804326 ps
CPU time 0.78 seconds
Started Jul 29 05:18:16 PM PDT 24
Finished Jul 29 05:18:17 PM PDT 24
Peak memory 205296 kb
Host smart-59504b4d-7e4d-41e8-8e18-20c9d404161d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896932466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.896932466
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3033863358
Short name T73
Test name
Test status
Simulation time 320216759 ps
CPU time 6.13 seconds
Started Jul 29 05:18:12 PM PDT 24
Finished Jul 29 05:18:18 PM PDT 24
Peak memory 205676 kb
Host smart-4ea883ae-f0d2-4fee-b696-a50db3e06bc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033863358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3033863358
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2744542335
Short name T371
Test name
Test status
Simulation time 551916571 ps
CPU time 5.02 seconds
Started Jul 29 05:18:11 PM PDT 24
Finished Jul 29 05:18:16 PM PDT 24
Peak memory 213876 kb
Host smart-2c0fef3b-802d-4a04-a5f9-bc4062f12aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744542335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2744542335
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3097199609
Short name T163
Test name
Test status
Simulation time 9014716867 ps
CPU time 11.56 seconds
Started Jul 29 05:18:14 PM PDT 24
Finished Jul 29 05:18:26 PM PDT 24
Peak memory 221904 kb
Host smart-5b38e4ac-77d3-4cb6-96d2-7f0f2cbc48dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097199609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
097199609
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2614248500
Short name T332
Test name
Test status
Simulation time 232436215 ps
CPU time 2.43 seconds
Started Jul 29 05:18:22 PM PDT 24
Finished Jul 29 05:18:25 PM PDT 24
Peak memory 222084 kb
Host smart-9b264ef5-41fe-45ee-9866-0b99d5776053
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614248500 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2614248500
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1601831657
Short name T462
Test name
Test status
Simulation time 141448305 ps
CPU time 1.7 seconds
Started Jul 29 05:18:20 PM PDT 24
Finished Jul 29 05:18:22 PM PDT 24
Peak memory 213976 kb
Host smart-f96be67b-7f8b-4c04-9157-161750bf105c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601831657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1601831657
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2281988533
Short name T388
Test name
Test status
Simulation time 2258488593 ps
CPU time 7.93 seconds
Started Jul 29 05:18:16 PM PDT 24
Finished Jul 29 05:18:24 PM PDT 24
Peak memory 205476 kb
Host smart-7f303ef4-1e3c-461a-9420-11717f29416c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281988533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.2281988533
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.38642314
Short name T386
Test name
Test status
Simulation time 7567027783 ps
CPU time 7.65 seconds
Started Jul 29 05:18:22 PM PDT 24
Finished Jul 29 05:18:29 PM PDT 24
Peak memory 205528 kb
Host smart-2f6879de-f5df-4300-a60a-d5e4b4619ee1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38642314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.38642314
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2389071172
Short name T381
Test name
Test status
Simulation time 224895852 ps
CPU time 1.18 seconds
Started Jul 29 05:18:13 PM PDT 24
Finished Jul 29 05:18:14 PM PDT 24
Peak memory 205500 kb
Host smart-f98405c8-018f-476e-8c0e-9b9dce7ad961
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389071172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2389071172
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3662961919
Short name T102
Test name
Test status
Simulation time 815898380 ps
CPU time 7.39 seconds
Started Jul 29 05:18:20 PM PDT 24
Finished Jul 29 05:18:28 PM PDT 24
Peak memory 205588 kb
Host smart-a4ee7462-a06f-49cd-8c29-5ba9cb4e9de1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662961919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3662961919
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.729842696
Short name T438
Test name
Test status
Simulation time 242315793 ps
CPU time 5.08 seconds
Started Jul 29 05:18:14 PM PDT 24
Finished Jul 29 05:18:20 PM PDT 24
Peak memory 213848 kb
Host smart-c7f621ab-74c5-4bfd-a1e6-8525a4a22d24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729842696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.729842696
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.802325031
Short name T113
Test name
Test status
Simulation time 3798515226 ps
CPU time 20.35 seconds
Started Jul 29 05:18:14 PM PDT 24
Finished Jul 29 05:18:35 PM PDT 24
Peak memory 213924 kb
Host smart-31ff7854-759a-42ff-a05c-6ce87a0e5aff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802325031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.802325031
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3381076850
Short name T340
Test name
Test status
Simulation time 343410273 ps
CPU time 2.73 seconds
Started Jul 29 05:18:19 PM PDT 24
Finished Jul 29 05:18:22 PM PDT 24
Peak memory 219896 kb
Host smart-0dbaf734-5326-40f7-b070-12cee6e3ba28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381076850 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3381076850
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1690042193
Short name T419
Test name
Test status
Simulation time 143466117 ps
CPU time 1.77 seconds
Started Jul 29 05:18:17 PM PDT 24
Finished Jul 29 05:18:19 PM PDT 24
Peak memory 213740 kb
Host smart-85162ce5-c596-4fdc-a9db-9fe950dd45b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690042193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1690042193
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.782751914
Short name T319
Test name
Test status
Simulation time 26372713416 ps
CPU time 15.81 seconds
Started Jul 29 05:18:22 PM PDT 24
Finished Jul 29 05:18:38 PM PDT 24
Peak memory 205516 kb
Host smart-4730f2c5-ea4d-4585-86d6-bbfefc21f68b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782751914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
rv_dm_jtag_dmi_csr_bit_bash.782751914
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1023996961
Short name T379
Test name
Test status
Simulation time 14727111087 ps
CPU time 37.04 seconds
Started Jul 29 05:18:16 PM PDT 24
Finished Jul 29 05:18:53 PM PDT 24
Peak memory 205500 kb
Host smart-05ec69ec-5ef3-405a-bc84-bcdd630de0b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023996961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1023996961
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3522443675
Short name T349
Test name
Test status
Simulation time 247270266 ps
CPU time 1.19 seconds
Started Jul 29 05:18:30 PM PDT 24
Finished Jul 29 05:18:31 PM PDT 24
Peak memory 205280 kb
Host smart-bd04d484-9695-446c-88c9-60c926ebd1b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522443675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3522443675
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.4085010941
Short name T458
Test name
Test status
Simulation time 180991889 ps
CPU time 3.51 seconds
Started Jul 29 05:18:19 PM PDT 24
Finished Jul 29 05:18:23 PM PDT 24
Peak memory 205628 kb
Host smart-abcd835e-fd69-46ef-afd7-fa5b65c7fabb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085010941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.4085010941
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1313937528
Short name T333
Test name
Test status
Simulation time 213066380 ps
CPU time 3.64 seconds
Started Jul 29 05:18:18 PM PDT 24
Finished Jul 29 05:18:21 PM PDT 24
Peak memory 213968 kb
Host smart-a3ca39a3-7540-40d9-94fa-e1a54291244a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313937528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1313937528
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3248966417
Short name T383
Test name
Test status
Simulation time 2832109006 ps
CPU time 14.58 seconds
Started Jul 29 05:18:21 PM PDT 24
Finished Jul 29 05:18:35 PM PDT 24
Peak memory 213928 kb
Host smart-3ba6c78f-c9ae-45fd-a79b-213b8d20bf6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248966417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
248966417
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1075619000
Short name T398
Test name
Test status
Simulation time 379124158 ps
CPU time 2.54 seconds
Started Jul 29 05:18:30 PM PDT 24
Finished Jul 29 05:18:33 PM PDT 24
Peak memory 216780 kb
Host smart-db80d460-180f-4126-8cf3-f1a15d9e0999
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075619000 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1075619000
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1140369592
Short name T449
Test name
Test status
Simulation time 488450740 ps
CPU time 1.78 seconds
Started Jul 29 05:18:28 PM PDT 24
Finished Jul 29 05:18:30 PM PDT 24
Peak memory 213836 kb
Host smart-7d05ff37-c40e-4c46-98a8-7b651133091f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140369592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1140369592
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.976856731
Short name T317
Test name
Test status
Simulation time 100651278991 ps
CPU time 138.02 seconds
Started Jul 29 05:18:29 PM PDT 24
Finished Jul 29 05:20:47 PM PDT 24
Peak memory 205584 kb
Host smart-0483091f-e99d-4ca3-be4e-3b2fff1544a4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976856731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
rv_dm_jtag_dmi_csr_bit_bash.976856731
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.1309138293
Short name T329
Test name
Test status
Simulation time 6153354085 ps
CPU time 4.26 seconds
Started Jul 29 05:18:27 PM PDT 24
Finished Jul 29 05:18:31 PM PDT 24
Peak memory 205576 kb
Host smart-0e9859f6-2f54-4b1e-9ade-07903744f436
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309138293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
1309138293
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.299055102
Short name T377
Test name
Test status
Simulation time 1172947312 ps
CPU time 1.71 seconds
Started Jul 29 05:18:18 PM PDT 24
Finished Jul 29 05:18:20 PM PDT 24
Peak memory 205296 kb
Host smart-0cbef150-8ac5-446f-a3dd-4ed98c5e920b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299055102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.299055102
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1869683602
Short name T456
Test name
Test status
Simulation time 615917394 ps
CPU time 6.35 seconds
Started Jul 29 05:18:19 PM PDT 24
Finished Jul 29 05:18:26 PM PDT 24
Peak memory 205632 kb
Host smart-09acdc51-a578-43ce-a035-557f18e153a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869683602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1869683602
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.673965717
Short name T343
Test name
Test status
Simulation time 224662110 ps
CPU time 4.94 seconds
Started Jul 29 05:18:29 PM PDT 24
Finished Jul 29 05:18:34 PM PDT 24
Peak memory 213840 kb
Host smart-16b74854-32d8-43e4-8c5a-fd3a702cebe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673965717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.673965717
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2443847722
Short name T152
Test name
Test status
Simulation time 3505831460 ps
CPU time 10.21 seconds
Started Jul 29 05:18:30 PM PDT 24
Finished Jul 29 05:18:40 PM PDT 24
Peak memory 213856 kb
Host smart-dca7be34-18f1-4ff6-a360-f32dd786e6f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443847722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
443847722
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.301583067
Short name T110
Test name
Test status
Simulation time 145240760 ps
CPU time 2.37 seconds
Started Jul 29 05:18:28 PM PDT 24
Finished Jul 29 05:18:30 PM PDT 24
Peak memory 217632 kb
Host smart-ab01cb03-78a5-4ae9-864a-7b3e9785a1f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301583067 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.301583067
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.3842638485
Short name T348
Test name
Test status
Simulation time 2556414008 ps
CPU time 2.25 seconds
Started Jul 29 05:18:21 PM PDT 24
Finished Jul 29 05:18:23 PM PDT 24
Peak memory 205564 kb
Host smart-bdfe83f2-7f47-4468-b12a-7dc6109f5ae2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842638485 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.3842638485
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1419793035
Short name T341
Test name
Test status
Simulation time 3558829365 ps
CPU time 2.49 seconds
Started Jul 29 05:18:17 PM PDT 24
Finished Jul 29 05:18:20 PM PDT 24
Peak memory 205488 kb
Host smart-cc730515-955e-4653-b4a5-144bde4b21c6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419793035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1419793035
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.586522175
Short name T384
Test name
Test status
Simulation time 527957658 ps
CPU time 0.95 seconds
Started Jul 29 05:18:18 PM PDT 24
Finished Jul 29 05:18:19 PM PDT 24
Peak memory 205248 kb
Host smart-7685631a-eefd-472e-a72f-4f685df6bbb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586522175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.586522175
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1150285585
Short name T71
Test name
Test status
Simulation time 951328162 ps
CPU time 7.94 seconds
Started Jul 29 05:18:27 PM PDT 24
Finished Jul 29 05:18:35 PM PDT 24
Peak memory 205560 kb
Host smart-afd4a554-b7cd-4236-ba61-32ca20d30c0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150285585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1150285585
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3692853624
Short name T448
Test name
Test status
Simulation time 2181464272 ps
CPU time 5.33 seconds
Started Jul 29 05:18:17 PM PDT 24
Finished Jul 29 05:18:23 PM PDT 24
Peak memory 213920 kb
Host smart-4ca1e745-3a10-4a5e-b83d-73b2457ffbb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692853624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3692853624
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2415717758
Short name T425
Test name
Test status
Simulation time 2905537936 ps
CPU time 14.53 seconds
Started Jul 29 05:18:27 PM PDT 24
Finished Jul 29 05:18:41 PM PDT 24
Peak memory 213996 kb
Host smart-55faf461-fea6-4d3f-bded-b365be7ea561
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415717758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
415717758
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1227424133
Short name T74
Test name
Test status
Simulation time 1175745074 ps
CPU time 27.26 seconds
Started Jul 29 05:17:45 PM PDT 24
Finished Jul 29 05:18:12 PM PDT 24
Peak memory 205524 kb
Host smart-d3abaecb-fec5-4e9c-8083-4a6483c66ead
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227424133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1227424133
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2011952014
Short name T88
Test name
Test status
Simulation time 17275369023 ps
CPU time 75.26 seconds
Started Jul 29 05:17:51 PM PDT 24
Finished Jul 29 05:19:07 PM PDT 24
Peak memory 213884 kb
Host smart-2d451c7d-39f4-4ea5-8666-5a6aa43ae6e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011952014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2011952014
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3383609454
Short name T101
Test name
Test status
Simulation time 494655322 ps
CPU time 2.83 seconds
Started Jul 29 05:17:49 PM PDT 24
Finished Jul 29 05:17:52 PM PDT 24
Peak memory 213952 kb
Host smart-db15804b-0a30-4460-821e-046c493ef714
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383609454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3383609454
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.4209926054
Short name T431
Test name
Test status
Simulation time 505648068 ps
CPU time 4.68 seconds
Started Jul 29 05:17:48 PM PDT 24
Finished Jul 29 05:17:53 PM PDT 24
Peak memory 219968 kb
Host smart-90ca7aba-edd5-4487-a4b7-f0d8f8e9d2de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209926054 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.4209926054
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.4169782789
Short name T441
Test name
Test status
Simulation time 972139954 ps
CPU time 2.46 seconds
Started Jul 29 05:17:50 PM PDT 24
Finished Jul 29 05:17:52 PM PDT 24
Peak memory 213816 kb
Host smart-7d15f1f5-546c-488f-b23c-3900aeb1f8af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169782789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.4169782789
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2924615240
Short name T416
Test name
Test status
Simulation time 21028197935 ps
CPU time 62.18 seconds
Started Jul 29 05:17:52 PM PDT 24
Finished Jul 29 05:18:55 PM PDT 24
Peak memory 205580 kb
Host smart-9d188d90-cea2-4076-9ede-8d7772252995
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924615240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2924615240
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1315994749
Short name T411
Test name
Test status
Simulation time 88142198006 ps
CPU time 133.34 seconds
Started Jul 29 05:17:52 PM PDT 24
Finished Jul 29 05:20:06 PM PDT 24
Peak memory 205588 kb
Host smart-d097782b-74db-4497-b4ba-4d8d2cd81a0d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315994749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.1315994749
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3993117990
Short name T79
Test name
Test status
Simulation time 3881361520 ps
CPU time 8.97 seconds
Started Jul 29 05:17:49 PM PDT 24
Finished Jul 29 05:17:59 PM PDT 24
Peak memory 205588 kb
Host smart-041ff944-f359-46bc-ad6e-73e5bd15b8e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993117990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3993117990
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.3776219049
Short name T402
Test name
Test status
Simulation time 6356871597 ps
CPU time 11.08 seconds
Started Jul 29 05:17:48 PM PDT 24
Finished Jul 29 05:17:59 PM PDT 24
Peak memory 205588 kb
Host smart-047eef00-d53e-4b9b-ae33-69490ef5c7a4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776219049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.3
776219049
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2034175314
Short name T463
Test name
Test status
Simulation time 1329274041 ps
CPU time 1.3 seconds
Started Jul 29 05:17:50 PM PDT 24
Finished Jul 29 05:17:51 PM PDT 24
Peak memory 205232 kb
Host smart-faa3c1cd-dcb4-4660-9798-67ff495f4254
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034175314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2034175314
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.472310348
Short name T318
Test name
Test status
Simulation time 16042493888 ps
CPU time 46.62 seconds
Started Jul 29 05:17:46 PM PDT 24
Finished Jul 29 05:18:33 PM PDT 24
Peak memory 205512 kb
Host smart-5b16e050-3fa2-4a68-9d4d-8800476c137e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472310348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.472310348
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.276541321
Short name T380
Test name
Test status
Simulation time 443997784 ps
CPU time 1.4 seconds
Started Jul 29 05:17:44 PM PDT 24
Finished Jul 29 05:17:46 PM PDT 24
Peak memory 205320 kb
Host smart-c43d6fff-face-4b28-b802-b9b4257e8779
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276541321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.276541321
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1573625045
Short name T401
Test name
Test status
Simulation time 113115246 ps
CPU time 0.72 seconds
Started Jul 29 05:17:46 PM PDT 24
Finished Jul 29 05:17:47 PM PDT 24
Peak memory 205320 kb
Host smart-c4cd14ca-9f4e-498e-b4da-7e9c0e495bfb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573625045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
573625045
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.499422555
Short name T421
Test name
Test status
Simulation time 107421454 ps
CPU time 0.94 seconds
Started Jul 29 05:17:48 PM PDT 24
Finished Jul 29 05:17:49 PM PDT 24
Peak memory 205356 kb
Host smart-14042d7d-3d15-40e5-bf72-381c2826cf3e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499422555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.499422555
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2713575436
Short name T311
Test name
Test status
Simulation time 37579535 ps
CPU time 0.75 seconds
Started Jul 29 05:17:52 PM PDT 24
Finished Jul 29 05:17:52 PM PDT 24
Peak memory 205312 kb
Host smart-5e2a6966-1477-48d3-a40a-71957693d434
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713575436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2713575436
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3067072979
Short name T84
Test name
Test status
Simulation time 1683536145 ps
CPU time 7.84 seconds
Started Jul 29 05:17:51 PM PDT 24
Finished Jul 29 05:18:00 PM PDT 24
Peak memory 205612 kb
Host smart-c03d042f-62e8-4671-9bfa-71c5b7000a7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067072979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3067072979
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.244101589
Short name T164
Test name
Test status
Simulation time 64768940024 ps
CPU time 65.05 seconds
Started Jul 29 05:17:50 PM PDT 24
Finished Jul 29 05:18:55 PM PDT 24
Peak memory 222128 kb
Host smart-737a778b-99de-4ffd-983b-9cff62714110
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244101589 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.244101589
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.370157292
Short name T334
Test name
Test status
Simulation time 247889414 ps
CPU time 2.98 seconds
Started Jul 29 05:17:50 PM PDT 24
Finished Jul 29 05:17:54 PM PDT 24
Peak memory 213912 kb
Host smart-51ce0c86-be46-447d-b12d-ae05332f9d7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370157292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.370157292
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.823157100
Short name T153
Test name
Test status
Simulation time 2267802852 ps
CPU time 21.78 seconds
Started Jul 29 05:17:50 PM PDT 24
Finished Jul 29 05:18:12 PM PDT 24
Peak memory 213824 kb
Host smart-1101e7e8-8b6e-46ef-ba03-ed28cbab6213
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823157100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.823157100
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.267380026
Short name T378
Test name
Test status
Simulation time 1985800932 ps
CPU time 32.41 seconds
Started Jul 29 05:17:53 PM PDT 24
Finished Jul 29 05:18:25 PM PDT 24
Peak memory 213788 kb
Host smart-510447ce-2c87-4d54-b73e-88491a829d50
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267380026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.267380026
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2331174348
Short name T339
Test name
Test status
Simulation time 19571465991 ps
CPU time 65.81 seconds
Started Jul 29 05:17:51 PM PDT 24
Finished Jul 29 05:18:57 PM PDT 24
Peak memory 213820 kb
Host smart-4f652866-a6bf-4f50-9d48-89a8bdd75e6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331174348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2331174348
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.911498612
Short name T96
Test name
Test status
Simulation time 410541686 ps
CPU time 3.43 seconds
Started Jul 29 05:17:52 PM PDT 24
Finished Jul 29 05:17:56 PM PDT 24
Peak memory 213996 kb
Host smart-72afadbf-f9d6-4576-896a-b2a14ad17c58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911498612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.911498612
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1688245096
Short name T397
Test name
Test status
Simulation time 145197946 ps
CPU time 2.81 seconds
Started Jul 29 05:17:54 PM PDT 24
Finished Jul 29 05:17:57 PM PDT 24
Peak memory 219904 kb
Host smart-ed6d5fc5-22ac-44a8-961a-227b4b19a029
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688245096 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1688245096
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.1184257524
Short name T94
Test name
Test status
Simulation time 145801196 ps
CPU time 2.13 seconds
Started Jul 29 05:17:50 PM PDT 24
Finished Jul 29 05:17:52 PM PDT 24
Peak memory 213692 kb
Host smart-3ea593ce-0d6f-4860-99d8-69cc6944842b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184257524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.1184257524
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3927136557
Short name T321
Test name
Test status
Simulation time 13218938727 ps
CPU time 20.74 seconds
Started Jul 29 05:17:50 PM PDT 24
Finished Jul 29 05:18:10 PM PDT 24
Peak memory 205564 kb
Host smart-9daa93b1-5775-41e2-b2bd-810f274cecb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927136557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3927136557
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.430808934
Short name T360
Test name
Test status
Simulation time 2282805961 ps
CPU time 2.52 seconds
Started Jul 29 05:17:49 PM PDT 24
Finished Jul 29 05:17:51 PM PDT 24
Peak memory 205544 kb
Host smart-2c413b51-0596-488f-b31b-a6994dd181be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430808934 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.r
v_dm_jtag_dmi_csr_bit_bash.430808934
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2133768913
Short name T83
Test name
Test status
Simulation time 7549703493 ps
CPU time 12.07 seconds
Started Jul 29 05:17:49 PM PDT 24
Finished Jul 29 05:18:01 PM PDT 24
Peak memory 205576 kb
Host smart-ba35d77b-d369-49b5-818c-73402d12f615
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133768913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2133768913
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3179489984
Short name T457
Test name
Test status
Simulation time 15367739003 ps
CPU time 10.52 seconds
Started Jul 29 05:17:50 PM PDT 24
Finished Jul 29 05:18:01 PM PDT 24
Peak memory 205604 kb
Host smart-7cf1a4a9-ea37-4c61-a3c0-d84dacd710d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179489984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
179489984
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.611135923
Short name T440
Test name
Test status
Simulation time 272737519 ps
CPU time 1.46 seconds
Started Jul 29 05:17:50 PM PDT 24
Finished Jul 29 05:17:52 PM PDT 24
Peak memory 205268 kb
Host smart-371f849b-bf92-4afb-9b2d-afaac75aac27
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611135923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.611135923
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2253375100
Short name T414
Test name
Test status
Simulation time 7137026142 ps
CPU time 7.88 seconds
Started Jul 29 05:17:53 PM PDT 24
Finished Jul 29 05:18:01 PM PDT 24
Peak memory 205692 kb
Host smart-34e34ef6-c39f-4f3d-b890-4f93e1ac443e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253375100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2253375100
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.1423602460
Short name T355
Test name
Test status
Simulation time 350255007 ps
CPU time 0.91 seconds
Started Jul 29 05:17:52 PM PDT 24
Finished Jul 29 05:17:53 PM PDT 24
Peak memory 205336 kb
Host smart-de742de2-8579-4560-8374-9cd2f3547118
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423602460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.1423602460
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3597702650
Short name T342
Test name
Test status
Simulation time 653909712 ps
CPU time 1.51 seconds
Started Jul 29 05:17:50 PM PDT 24
Finished Jul 29 05:17:52 PM PDT 24
Peak memory 205260 kb
Host smart-7105bec9-85ae-4162-af32-64c96aa5bda8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597702650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
597702650
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.119241538
Short name T420
Test name
Test status
Simulation time 94902054 ps
CPU time 0.72 seconds
Started Jul 29 05:17:51 PM PDT 24
Finished Jul 29 05:17:52 PM PDT 24
Peak memory 205360 kb
Host smart-fd93b770-d1a3-4bab-8493-073bc580ed05
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119241538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.119241538
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.243806805
Short name T352
Test name
Test status
Simulation time 80325554 ps
CPU time 0.77 seconds
Started Jul 29 05:17:51 PM PDT 24
Finished Jul 29 05:17:52 PM PDT 24
Peak memory 205332 kb
Host smart-c0bf2e6f-a529-405f-8c64-e1007b722d92
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243806805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.243806805
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1972150789
Short name T417
Test name
Test status
Simulation time 160700829 ps
CPU time 6.43 seconds
Started Jul 29 05:17:55 PM PDT 24
Finished Jul 29 05:18:02 PM PDT 24
Peak memory 205584 kb
Host smart-0c014caf-20c9-4695-b791-5250df240902
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972150789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1972150789
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.655633947
Short name T427
Test name
Test status
Simulation time 11378466512 ps
CPU time 37.51 seconds
Started Jul 29 05:17:50 PM PDT 24
Finished Jul 29 05:18:27 PM PDT 24
Peak memory 219484 kb
Host smart-6041b3c1-b207-488d-801d-75c851e73162
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655633947 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.655633947
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.1094746112
Short name T406
Test name
Test status
Simulation time 1379127741 ps
CPU time 4.95 seconds
Started Jul 29 05:17:54 PM PDT 24
Finished Jul 29 05:17:59 PM PDT 24
Peak memory 213852 kb
Host smart-f0be7df1-0814-4c58-a6e5-b83a83ce2861
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094746112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.1094746112
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3819104284
Short name T160
Test name
Test status
Simulation time 4201141814 ps
CPU time 18.32 seconds
Started Jul 29 05:17:50 PM PDT 24
Finished Jul 29 05:18:09 PM PDT 24
Peak memory 213884 kb
Host smart-b9562db8-306d-44cc-ab1f-e7b0f69a7b82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819104284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3819104284
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1905848358
Short name T97
Test name
Test status
Simulation time 6845239822 ps
CPU time 33.41 seconds
Started Jul 29 05:18:01 PM PDT 24
Finished Jul 29 05:18:34 PM PDT 24
Peak memory 213852 kb
Host smart-1867a3e3-c7b9-4174-abae-03dbcfb71f1b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905848358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1905848358
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.270321956
Short name T99
Test name
Test status
Simulation time 3826220706 ps
CPU time 37.38 seconds
Started Jul 29 05:17:59 PM PDT 24
Finished Jul 29 05:18:37 PM PDT 24
Peak memory 213852 kb
Host smart-d8398628-71a8-470e-84ea-412390d5037c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270321956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.270321956
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2613524286
Short name T89
Test name
Test status
Simulation time 371993773 ps
CPU time 2.98 seconds
Started Jul 29 05:17:53 PM PDT 24
Finished Jul 29 05:17:56 PM PDT 24
Peak memory 213788 kb
Host smart-36733261-1e2b-41ce-8e3d-e387781b8719
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613524286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2613524286
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.3644462863
Short name T452
Test name
Test status
Simulation time 126596737 ps
CPU time 2.27 seconds
Started Jul 29 05:17:55 PM PDT 24
Finished Jul 29 05:17:58 PM PDT 24
Peak memory 218032 kb
Host smart-8e587bda-72a2-448a-a1dd-3f80a97e21e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644462863 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.3644462863
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3640586347
Short name T85
Test name
Test status
Simulation time 228389604 ps
CPU time 2.11 seconds
Started Jul 29 05:17:55 PM PDT 24
Finished Jul 29 05:17:58 PM PDT 24
Peak memory 213748 kb
Host smart-b99de716-ada0-45ae-bd3a-219d67f677de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640586347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3640586347
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1726698891
Short name T389
Test name
Test status
Simulation time 51484479596 ps
CPU time 44.37 seconds
Started Jul 29 05:17:55 PM PDT 24
Finished Jul 29 05:18:39 PM PDT 24
Peak memory 205528 kb
Host smart-d5797521-e30d-4621-b3d9-fe011257cb7c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726698891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1726698891
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.841437617
Short name T368
Test name
Test status
Simulation time 10925864414 ps
CPU time 14.87 seconds
Started Jul 29 05:17:54 PM PDT 24
Finished Jul 29 05:18:09 PM PDT 24
Peak memory 205536 kb
Host smart-59c1ee0e-7f6a-46af-b084-42fd61eee089
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841437617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.r
v_dm_jtag_dmi_csr_bit_bash.841437617
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.3671053306
Short name T82
Test name
Test status
Simulation time 2352475603 ps
CPU time 6.91 seconds
Started Jul 29 05:17:54 PM PDT 24
Finished Jul 29 05:18:01 PM PDT 24
Peak memory 205584 kb
Host smart-983e9e36-9abf-4007-af8c-bec6e4015e89
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671053306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.3671053306
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2290621432
Short name T404
Test name
Test status
Simulation time 2340118743 ps
CPU time 4.4 seconds
Started Jul 29 05:17:56 PM PDT 24
Finished Jul 29 05:18:00 PM PDT 24
Peak memory 205560 kb
Host smart-5b32af1d-4435-425b-a512-85f297a9a512
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290621432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
290621432
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.363793771
Short name T327
Test name
Test status
Simulation time 540760373 ps
CPU time 1.04 seconds
Started Jul 29 05:17:55 PM PDT 24
Finished Jul 29 05:17:56 PM PDT 24
Peak memory 205296 kb
Host smart-ce694849-10e7-44cb-9690-734f96a1b014
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363793771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.363793771
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1945426518
Short name T325
Test name
Test status
Simulation time 25864382683 ps
CPU time 24.01 seconds
Started Jul 29 05:17:54 PM PDT 24
Finished Jul 29 05:18:18 PM PDT 24
Peak memory 205632 kb
Host smart-7411921e-0e81-474c-8ba6-8b2f981cf4ff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945426518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1945426518
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2506931709
Short name T320
Test name
Test status
Simulation time 181600064 ps
CPU time 0.85 seconds
Started Jul 29 05:17:57 PM PDT 24
Finished Jul 29 05:17:58 PM PDT 24
Peak memory 205304 kb
Host smart-89cdc92c-fb2f-47f5-8b26-1c4f048f335c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506931709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2506931709
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2169127000
Short name T323
Test name
Test status
Simulation time 149177565 ps
CPU time 0.78 seconds
Started Jul 29 05:18:00 PM PDT 24
Finished Jul 29 05:18:00 PM PDT 24
Peak memory 205288 kb
Host smart-6f2815f5-3269-481f-a972-ee4d89cfd922
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169127000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
169127000
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.224644425
Short name T372
Test name
Test status
Simulation time 172557642 ps
CPU time 0.74 seconds
Started Jul 29 05:18:01 PM PDT 24
Finished Jul 29 05:18:02 PM PDT 24
Peak memory 205304 kb
Host smart-1297b212-b821-4a71-a0c5-fb02c2a65633
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224644425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.224644425
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3283970807
Short name T464
Test name
Test status
Simulation time 35950260 ps
CPU time 0.73 seconds
Started Jul 29 05:17:56 PM PDT 24
Finished Jul 29 05:17:57 PM PDT 24
Peak memory 205208 kb
Host smart-0968d692-3f58-4de1-b731-5e554aec1751
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283970807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3283970807
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3674896174
Short name T103
Test name
Test status
Simulation time 237608746 ps
CPU time 6.77 seconds
Started Jul 29 05:17:54 PM PDT 24
Finished Jul 29 05:18:01 PM PDT 24
Peak memory 205604 kb
Host smart-9d1537e7-efc1-4424-892c-3d7be19d8a92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674896174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3674896174
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1320242795
Short name T52
Test name
Test status
Simulation time 58670155259 ps
CPU time 61.73 seconds
Started Jul 29 05:17:55 PM PDT 24
Finished Jul 29 05:18:57 PM PDT 24
Peak memory 222276 kb
Host smart-08aa2981-7936-4729-b919-56e92f4882eb
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320242795 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1320242795
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3696930294
Short name T335
Test name
Test status
Simulation time 1166615216 ps
CPU time 6.17 seconds
Started Jul 29 05:17:56 PM PDT 24
Finished Jul 29 05:18:02 PM PDT 24
Peak memory 213888 kb
Host smart-d0182efa-9da3-43e0-8b06-4f832dcad94f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696930294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3696930294
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3008684506
Short name T422
Test name
Test status
Simulation time 4980410230 ps
CPU time 20.68 seconds
Started Jul 29 05:17:54 PM PDT 24
Finished Jul 29 05:18:15 PM PDT 24
Peak memory 213836 kb
Host smart-c45c6502-6778-45fa-ad11-0cd8dd0ab549
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008684506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3008684506
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.4058807551
Short name T108
Test name
Test status
Simulation time 338350470 ps
CPU time 2.37 seconds
Started Jul 29 05:17:58 PM PDT 24
Finished Jul 29 05:18:01 PM PDT 24
Peak memory 215408 kb
Host smart-2348131c-2713-464d-b3cd-6a5c0c7faf3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058807551 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.4058807551
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3015049978
Short name T69
Test name
Test status
Simulation time 57216014 ps
CPU time 1.99 seconds
Started Jul 29 05:17:55 PM PDT 24
Finished Jul 29 05:17:57 PM PDT 24
Peak memory 213800 kb
Host smart-1af7b8bf-cef8-402a-a60b-da64a12a35d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015049978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3015049978
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.42581205
Short name T344
Test name
Test status
Simulation time 36198467922 ps
CPU time 38.08 seconds
Started Jul 29 05:17:53 PM PDT 24
Finished Jul 29 05:18:31 PM PDT 24
Peak memory 205568 kb
Host smart-c4402543-c112-4bd7-8ba5-da8aa4672285
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42581205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=r
v_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv
_dm_jtag_dmi_csr_bit_bash.42581205
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.103523398
Short name T454
Test name
Test status
Simulation time 1301262185 ps
CPU time 4.37 seconds
Started Jul 29 05:17:56 PM PDT 24
Finished Jul 29 05:18:00 PM PDT 24
Peak memory 205436 kb
Host smart-a862248e-ec7e-4b77-b157-4ab12d50c05d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103523398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.103523398
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3045852508
Short name T370
Test name
Test status
Simulation time 481437065 ps
CPU time 1.9 seconds
Started Jul 29 05:17:56 PM PDT 24
Finished Jul 29 05:17:59 PM PDT 24
Peak memory 205332 kb
Host smart-e54ad615-07d8-4c25-8999-79ccca797aac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045852508 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
045852508
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1789494265
Short name T437
Test name
Test status
Simulation time 93529431 ps
CPU time 3.42 seconds
Started Jul 29 05:17:53 PM PDT 24
Finished Jul 29 05:17:57 PM PDT 24
Peak memory 205664 kb
Host smart-0fcff694-5ed5-4823-8e97-879075ac90dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789494265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1789494265
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3610514232
Short name T165
Test name
Test status
Simulation time 55323023243 ps
CPU time 47.36 seconds
Started Jul 29 05:17:56 PM PDT 24
Finished Jul 29 05:18:44 PM PDT 24
Peak memory 221900 kb
Host smart-60667213-a7b1-4ed7-9722-c5dc71a5c56d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610514232 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3610514232
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2534635967
Short name T430
Test name
Test status
Simulation time 226064472 ps
CPU time 5.28 seconds
Started Jul 29 05:17:55 PM PDT 24
Finished Jul 29 05:18:00 PM PDT 24
Peak memory 213880 kb
Host smart-0ff76ae6-54fc-4a53-90bb-49f5904abd13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534635967 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2534635967
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.496433397
Short name T356
Test name
Test status
Simulation time 172413434 ps
CPU time 2.75 seconds
Started Jul 29 05:17:59 PM PDT 24
Finished Jul 29 05:18:02 PM PDT 24
Peak memory 222004 kb
Host smart-0bf6059c-9a91-4b8d-a16b-bd9ac7528740
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496433397 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.496433397
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.4060905217
Short name T466
Test name
Test status
Simulation time 71587903465 ps
CPU time 177.39 seconds
Started Jul 29 05:17:54 PM PDT 24
Finished Jul 29 05:20:51 PM PDT 24
Peak memory 205596 kb
Host smart-49bfbec3-da9b-45e9-a071-940b8c784f8e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060905217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.4060905217
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.669183237
Short name T410
Test name
Test status
Simulation time 1335280070 ps
CPU time 1.22 seconds
Started Jul 29 05:17:56 PM PDT 24
Finished Jul 29 05:17:57 PM PDT 24
Peak memory 205468 kb
Host smart-f7fc53e4-36d9-410e-8c67-537257bc8607
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669183237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.669183237
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2685443176
Short name T322
Test name
Test status
Simulation time 729192463 ps
CPU time 1.15 seconds
Started Jul 29 05:17:59 PM PDT 24
Finished Jul 29 05:18:00 PM PDT 24
Peak memory 205316 kb
Host smart-a334c05a-b79e-4179-8e63-6ab8e3384c49
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685443176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
685443176
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.209445174
Short name T76
Test name
Test status
Simulation time 1072804961 ps
CPU time 4.89 seconds
Started Jul 29 05:18:01 PM PDT 24
Finished Jul 29 05:18:06 PM PDT 24
Peak memory 205600 kb
Host smart-4d5f892c-a7b7-4715-9909-850a43e201b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209445174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c
sr_outstanding.209445174
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.895530123
Short name T429
Test name
Test status
Simulation time 100078284953 ps
CPU time 253.14 seconds
Started Jul 29 05:18:01 PM PDT 24
Finished Jul 29 05:22:14 PM PDT 24
Peak memory 225668 kb
Host smart-5d9fd150-83c5-4570-8c9a-83ad59db525b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895530123 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.895530123
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1087498863
Short name T109
Test name
Test status
Simulation time 630139017 ps
CPU time 4.52 seconds
Started Jul 29 05:17:58 PM PDT 24
Finished Jul 29 05:18:03 PM PDT 24
Peak memory 213836 kb
Host smart-6a0944ec-7636-42d5-818e-1eb0fe169e6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087498863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1087498863
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1026790739
Short name T158
Test name
Test status
Simulation time 2429936014 ps
CPU time 21.75 seconds
Started Jul 29 05:17:57 PM PDT 24
Finished Jul 29 05:18:19 PM PDT 24
Peak memory 213848 kb
Host smart-781efac0-f9bb-4ab6-b126-4cabe4c4d46c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026790739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1026790739
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.565027332
Short name T453
Test name
Test status
Simulation time 754316140 ps
CPU time 4.07 seconds
Started Jul 29 05:18:02 PM PDT 24
Finished Jul 29 05:18:06 PM PDT 24
Peak memory 218540 kb
Host smart-55ae2d97-2800-4c1f-be3a-14881f105b59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565027332 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.565027332
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.438341971
Short name T87
Test name
Test status
Simulation time 315893163 ps
CPU time 2.43 seconds
Started Jul 29 05:18:02 PM PDT 24
Finished Jul 29 05:18:04 PM PDT 24
Peak memory 213824 kb
Host smart-9e7cdbd1-6f05-4916-9974-c5a6913541ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438341971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.438341971
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2681055600
Short name T326
Test name
Test status
Simulation time 4475787499 ps
CPU time 3.15 seconds
Started Jul 29 05:17:59 PM PDT 24
Finished Jul 29 05:18:02 PM PDT 24
Peak memory 205488 kb
Host smart-449114e5-c4da-4e50-9251-b3e70846c0cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681055600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2681055600
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.965359657
Short name T382
Test name
Test status
Simulation time 7343333145 ps
CPU time 6.49 seconds
Started Jul 29 05:18:01 PM PDT 24
Finished Jul 29 05:18:08 PM PDT 24
Peak memory 205492 kb
Host smart-536a9714-e71c-4502-ae59-eb17d07afbc5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965359657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.965359657
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1329278249
Short name T347
Test name
Test status
Simulation time 256440592 ps
CPU time 0.87 seconds
Started Jul 29 05:17:59 PM PDT 24
Finished Jul 29 05:18:00 PM PDT 24
Peak memory 205316 kb
Host smart-fe7e14e7-17ae-42c8-ad0a-d21afca3023d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329278249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
329278249
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3603448761
Short name T75
Test name
Test status
Simulation time 624837632 ps
CPU time 7.93 seconds
Started Jul 29 05:18:00 PM PDT 24
Finished Jul 29 05:18:08 PM PDT 24
Peak memory 205644 kb
Host smart-46baaa99-d414-4ed3-89eb-89c573750f55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603448761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3603448761
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.3342713684
Short name T53
Test name
Test status
Simulation time 31649482598 ps
CPU time 364.79 seconds
Started Jul 29 05:17:59 PM PDT 24
Finished Jul 29 05:24:04 PM PDT 24
Peak memory 222084 kb
Host smart-2186eb2f-204b-4dce-865b-a67c7f689314
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342713684 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.3342713684
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.965975963
Short name T467
Test name
Test status
Simulation time 230635845 ps
CPU time 2.27 seconds
Started Jul 29 05:18:00 PM PDT 24
Finished Jul 29 05:18:02 PM PDT 24
Peak memory 213796 kb
Host smart-1bed65d2-def8-4037-91e5-edefae573c74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965975963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.965975963
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2721988081
Short name T444
Test name
Test status
Simulation time 2924686097 ps
CPU time 25.31 seconds
Started Jul 29 05:17:59 PM PDT 24
Finished Jul 29 05:18:25 PM PDT 24
Peak memory 213844 kb
Host smart-e695a8fb-b83b-4dc8-8304-a32ebd2066f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721988081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2721988081
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.475084100
Short name T399
Test name
Test status
Simulation time 138890317 ps
CPU time 2.31 seconds
Started Jul 29 05:18:01 PM PDT 24
Finished Jul 29 05:18:04 PM PDT 24
Peak memory 217260 kb
Host smart-92e9389a-51e9-4b75-9812-f40013597bb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475084100 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.475084100
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.984819016
Short name T365
Test name
Test status
Simulation time 100344864 ps
CPU time 1.63 seconds
Started Jul 29 05:18:00 PM PDT 24
Finished Jul 29 05:18:02 PM PDT 24
Peak memory 213660 kb
Host smart-d5fa2306-8b00-43ba-91f2-88755bd84db1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984819016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.984819016
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.2457959851
Short name T396
Test name
Test status
Simulation time 15002188575 ps
CPU time 14.16 seconds
Started Jul 29 05:18:01 PM PDT 24
Finished Jul 29 05:18:16 PM PDT 24
Peak memory 205508 kb
Host smart-33b4c202-01ab-4e1f-af86-46bbd89b25c9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457959851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.2457959851
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1759199497
Short name T387
Test name
Test status
Simulation time 8283916132 ps
CPU time 15.89 seconds
Started Jul 29 05:18:00 PM PDT 24
Finished Jul 29 05:18:16 PM PDT 24
Peak memory 205576 kb
Host smart-e39cdbac-fbf6-4d1f-8a7f-ee47e841660b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759199497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
759199497
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2716642349
Short name T54
Test name
Test status
Simulation time 295831901 ps
CPU time 0.76 seconds
Started Jul 29 05:18:01 PM PDT 24
Finished Jul 29 05:18:02 PM PDT 24
Peak memory 205500 kb
Host smart-4d17b778-e23e-4303-ace2-f991e9178eff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716642349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
716642349
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.466022874
Short name T105
Test name
Test status
Simulation time 357713629 ps
CPU time 6.81 seconds
Started Jul 29 05:18:02 PM PDT 24
Finished Jul 29 05:18:09 PM PDT 24
Peak memory 205664 kb
Host smart-7f5c5852-fb95-4532-8727-a5573c8c323c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466022874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.466022874
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1365396555
Short name T415
Test name
Test status
Simulation time 90832792294 ps
CPU time 194.93 seconds
Started Jul 29 05:18:02 PM PDT 24
Finished Jul 29 05:21:17 PM PDT 24
Peak memory 230264 kb
Host smart-a30cdadb-56d3-476d-bf84-7318eb8deea7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365396555 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1365396555
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1422078864
Short name T337
Test name
Test status
Simulation time 923870944 ps
CPU time 5.33 seconds
Started Jul 29 05:18:02 PM PDT 24
Finished Jul 29 05:18:07 PM PDT 24
Peak memory 213960 kb
Host smart-4e59e7e8-094e-4b6e-b892-9411ea124778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422078864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1422078864
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.2962378663
Short name T451
Test name
Test status
Simulation time 132462329 ps
CPU time 2.33 seconds
Started Jul 29 05:18:06 PM PDT 24
Finished Jul 29 05:18:09 PM PDT 24
Peak memory 221908 kb
Host smart-97024e98-fef6-46d7-b160-350b72b057c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962378663 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.2962378663
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3861003701
Short name T93
Test name
Test status
Simulation time 253610898 ps
CPU time 1.59 seconds
Started Jul 29 05:18:03 PM PDT 24
Finished Jul 29 05:18:04 PM PDT 24
Peak memory 213720 kb
Host smart-7eefc9a8-37b2-48f4-b4d1-83241cde2462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861003701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3861003701
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.780942719
Short name T369
Test name
Test status
Simulation time 118849385590 ps
CPU time 174.93 seconds
Started Jul 29 05:18:03 PM PDT 24
Finished Jul 29 05:20:58 PM PDT 24
Peak memory 205584 kb
Host smart-a02551ff-e814-4031-803f-285a12548d1d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780942719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r
v_dm_jtag_dmi_csr_bit_bash.780942719
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1809593528
Short name T363
Test name
Test status
Simulation time 1984426908 ps
CPU time 1.64 seconds
Started Jul 29 05:18:03 PM PDT 24
Finished Jul 29 05:18:04 PM PDT 24
Peak memory 205492 kb
Host smart-792702a8-d691-45bc-a2ba-ec548dbbbc64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809593528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
809593528
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4010795377
Short name T426
Test name
Test status
Simulation time 295203081 ps
CPU time 0.98 seconds
Started Jul 29 05:18:02 PM PDT 24
Finished Jul 29 05:18:03 PM PDT 24
Peak memory 205292 kb
Host smart-1c5a724e-5140-4995-8a2d-f62ad1fcf43e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010795377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.4
010795377
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3423855977
Short name T373
Test name
Test status
Simulation time 301438686 ps
CPU time 6.6 seconds
Started Jul 29 05:18:05 PM PDT 24
Finished Jul 29 05:18:12 PM PDT 24
Peak memory 205540 kb
Host smart-6a6cdaa5-6ac4-4062-9168-36098f26d01e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423855977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3423855977
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.3598243352
Short name T393
Test name
Test status
Simulation time 45591362266 ps
CPU time 363.46 seconds
Started Jul 29 05:17:59 PM PDT 24
Finished Jul 29 05:24:02 PM PDT 24
Peak memory 222512 kb
Host smart-63497c8e-76bd-4a1b-b7fa-0b38a86acf29
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598243352 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.3598243352
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1695682494
Short name T405
Test name
Test status
Simulation time 241859535 ps
CPU time 5.74 seconds
Started Jul 29 05:18:00 PM PDT 24
Finished Jul 29 05:18:06 PM PDT 24
Peak memory 213932 kb
Host smart-e1e2eb90-e5c4-4108-b411-c59a0d30a067
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695682494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1695682494
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.994517519
Short name T157
Test name
Test status
Simulation time 798525588 ps
CPU time 9.58 seconds
Started Jul 29 05:18:00 PM PDT 24
Finished Jul 29 05:18:10 PM PDT 24
Peak memory 213792 kb
Host smart-1842b875-23ce-4c22-8203-d5c116ba7989
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994517519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.994517519
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1667365790
Short name T174
Test name
Test status
Simulation time 35318193 ps
CPU time 0.7 seconds
Started Jul 29 05:18:34 PM PDT 24
Finished Jul 29 05:18:34 PM PDT 24
Peak memory 205340 kb
Host smart-a4b69e5a-b2b1-440a-97af-17bff4f3a10e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667365790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1667365790
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.918230267
Short name T120
Test name
Test status
Simulation time 2471090324 ps
CPU time 5.05 seconds
Started Jul 29 05:18:25 PM PDT 24
Finished Jul 29 05:18:30 PM PDT 24
Peak memory 213976 kb
Host smart-e9d4ad1b-5789-4b33-9192-e3ed1eb1e37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918230267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.918230267
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3058186261
Short name T241
Test name
Test status
Simulation time 2288520850 ps
CPU time 8.36 seconds
Started Jul 29 05:18:28 PM PDT 24
Finished Jul 29 05:18:36 PM PDT 24
Peak memory 214004 kb
Host smart-b5244b47-7fc6-462c-becb-3899f24e65c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058186261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3058186261
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1039124971
Short name T245
Test name
Test status
Simulation time 180218277 ps
CPU time 0.96 seconds
Started Jul 29 05:18:26 PM PDT 24
Finished Jul 29 05:18:27 PM PDT 24
Peak memory 205388 kb
Host smart-a7229205-be80-4ac6-a2f1-ac9e7315138f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039124971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1039124971
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2232493449
Short name T255
Test name
Test status
Simulation time 229688377 ps
CPU time 0.84 seconds
Started Jul 29 05:18:26 PM PDT 24
Finished Jul 29 05:18:27 PM PDT 24
Peak memory 205360 kb
Host smart-cebed4a5-8380-4e15-b368-2f3abc38d7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232493449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2232493449
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3112651615
Short name T281
Test name
Test status
Simulation time 324621107 ps
CPU time 0.77 seconds
Started Jul 29 05:18:26 PM PDT 24
Finished Jul 29 05:18:27 PM PDT 24
Peak memory 205420 kb
Host smart-7f4bcd8d-996d-4898-8ded-ac46a2cb3cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112651615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3112651615
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.1362987545
Short name T224
Test name
Test status
Simulation time 54305944 ps
CPU time 0.89 seconds
Started Jul 29 05:18:33 PM PDT 24
Finished Jul 29 05:18:34 PM PDT 24
Peak memory 215748 kb
Host smart-69cabdb4-1c13-41ad-8a81-5ecea1d53ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362987545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.1362987545
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3080184033
Short name T256
Test name
Test status
Simulation time 3724530929 ps
CPU time 10.75 seconds
Started Jul 29 05:18:27 PM PDT 24
Finished Jul 29 05:18:38 PM PDT 24
Peak memory 205780 kb
Host smart-9945c45c-f83f-4067-82c1-8695aa5bcd72
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080184033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3080184033
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.1161472013
Short name T47
Test name
Test status
Simulation time 422506865 ps
CPU time 0.99 seconds
Started Jul 29 05:18:33 PM PDT 24
Finished Jul 29 05:18:34 PM PDT 24
Peak memory 205420 kb
Host smart-1554de88-ae24-4c5f-9eb5-e0a99d368cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161472013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.1161472013
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.3333220244
Short name T227
Test name
Test status
Simulation time 359032923 ps
CPU time 1.18 seconds
Started Jul 29 05:18:27 PM PDT 24
Finished Jul 29 05:18:29 PM PDT 24
Peak memory 205420 kb
Host smart-55f1952e-c0c4-4c9a-a657-8b8ef1e18597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333220244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.3333220244
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.4159148031
Short name T119
Test name
Test status
Simulation time 186569034 ps
CPU time 1.15 seconds
Started Jul 29 05:18:35 PM PDT 24
Finished Jul 29 05:18:36 PM PDT 24
Peak memory 205372 kb
Host smart-bd34347c-115c-40ff-aaa2-ae9cf857e26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159148031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.4159148031
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.417170350
Short name T253
Test name
Test status
Simulation time 153413743 ps
CPU time 0.92 seconds
Started Jul 29 05:18:33 PM PDT 24
Finished Jul 29 05:18:34 PM PDT 24
Peak memory 205368 kb
Host smart-a031bb01-f226-49cd-ac51-2fb6e09e470a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417170350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.417170350
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1830382990
Short name T221
Test name
Test status
Simulation time 697861190 ps
CPU time 2.45 seconds
Started Jul 29 05:18:31 PM PDT 24
Finished Jul 29 05:18:33 PM PDT 24
Peak memory 205320 kb
Host smart-29790022-72c4-4636-96d3-821b9087f453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830382990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1830382990
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2298557309
Short name T209
Test name
Test status
Simulation time 653837353 ps
CPU time 1.75 seconds
Started Jul 29 05:18:33 PM PDT 24
Finished Jul 29 05:18:35 PM PDT 24
Peak memory 205444 kb
Host smart-38948584-ec94-4b95-b7a0-5cd0a7c489ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298557309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2298557309
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3662370524
Short name T272
Test name
Test status
Simulation time 223128844 ps
CPU time 0.92 seconds
Started Jul 29 05:18:40 PM PDT 24
Finished Jul 29 05:18:41 PM PDT 24
Peak memory 205408 kb
Host smart-ceced1be-16c3-4d7b-811c-cd4e6de3e7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662370524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3662370524
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2254854368
Short name T186
Test name
Test status
Simulation time 230377350 ps
CPU time 0.97 seconds
Started Jul 29 05:18:27 PM PDT 24
Finished Jul 29 05:18:28 PM PDT 24
Peak memory 205416 kb
Host smart-3dc3f0f0-c5bb-4844-aa4c-74834f3d716a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254854368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2254854368
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3468116327
Short name T198
Test name
Test status
Simulation time 1197905366 ps
CPU time 2.15 seconds
Started Jul 29 05:18:29 PM PDT 24
Finished Jul 29 05:18:31 PM PDT 24
Peak memory 205328 kb
Host smart-11e79782-2d12-47b5-a198-bc3e0697f7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468116327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3468116327
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.755406965
Short name T107
Test name
Test status
Simulation time 328566915 ps
CPU time 1.62 seconds
Started Jul 29 05:18:34 PM PDT 24
Finished Jul 29 05:18:36 PM PDT 24
Peak memory 213624 kb
Host smart-2db64939-b0f2-4c2d-b6e1-0868f75baac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755406965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.755406965
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1286073325
Short name T28
Test name
Test status
Simulation time 412736897 ps
CPU time 1.35 seconds
Started Jul 29 05:18:29 PM PDT 24
Finished Jul 29 05:18:31 PM PDT 24
Peak memory 205392 kb
Host smart-51ede5ed-9fda-404b-9210-3dff4098b92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286073325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1286073325
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.217407698
Short name T205
Test name
Test status
Simulation time 4903321553 ps
CPU time 5.75 seconds
Started Jul 29 05:18:27 PM PDT 24
Finished Jul 29 05:18:32 PM PDT 24
Peak memory 214032 kb
Host smart-568ea04b-713c-4d65-9deb-ad566d2c57fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217407698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.217407698
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.2274238551
Short name T295
Test name
Test status
Simulation time 910703616 ps
CPU time 2.09 seconds
Started Jul 29 05:18:26 PM PDT 24
Finished Jul 29 05:18:28 PM PDT 24
Peak memory 205444 kb
Host smart-a08659b3-788b-44c9-8fbf-e3506e05f790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274238551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.2274238551
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.1123450288
Short name T34
Test name
Test status
Simulation time 6963097583 ps
CPU time 11.11 seconds
Started Jul 29 05:18:31 PM PDT 24
Finished Jul 29 05:18:43 PM PDT 24
Peak memory 213764 kb
Host smart-dc809546-4adb-4554-948e-c29596ed3a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123450288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.1123450288
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.1167377201
Short name T7
Test name
Test status
Simulation time 536907162610 ps
CPU time 1032.14 seconds
Started Jul 29 05:18:44 PM PDT 24
Finished Jul 29 05:35:57 PM PDT 24
Peak memory 237568 kb
Host smart-077747f2-0ed2-4c88-95b8-982dc2efd4e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167377201 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.1167377201
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3387558564
Short name T42
Test name
Test status
Simulation time 132026511 ps
CPU time 0.87 seconds
Started Jul 29 05:18:36 PM PDT 24
Finished Jul 29 05:18:37 PM PDT 24
Peak memory 205364 kb
Host smart-a5e97650-a35b-460f-b170-ee33d8a746b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387558564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3387558564
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2403535826
Short name T231
Test name
Test status
Simulation time 55878348 ps
CPU time 0.69 seconds
Started Jul 29 05:18:35 PM PDT 24
Finished Jul 29 05:18:36 PM PDT 24
Peak memory 205400 kb
Host smart-7590d40a-0f72-4ed6-984c-e064354d4a95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403535826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2403535826
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.3503536670
Short name T239
Test name
Test status
Simulation time 42133782159 ps
CPU time 32.16 seconds
Started Jul 29 05:18:31 PM PDT 24
Finished Jul 29 05:19:03 PM PDT 24
Peak memory 221168 kb
Host smart-0b58a9dd-2ffc-4a85-b22e-0ffa9b037931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503536670 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.3503536670
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.611015860
Short name T203
Test name
Test status
Simulation time 566207867 ps
CPU time 1.84 seconds
Started Jul 29 05:18:36 PM PDT 24
Finished Jul 29 05:18:38 PM PDT 24
Peak memory 205920 kb
Host smart-e7c2b09b-35ce-4e91-9647-2d9d1e2f6691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611015860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.611015860
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3736032700
Short name T264
Test name
Test status
Simulation time 384355381 ps
CPU time 1.08 seconds
Started Jul 29 05:18:36 PM PDT 24
Finished Jul 29 05:18:37 PM PDT 24
Peak memory 205360 kb
Host smart-a61d302e-06a8-4600-a9d9-0a9f8b7ded0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736032700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3736032700
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2717124463
Short name T15
Test name
Test status
Simulation time 281543304 ps
CPU time 1.43 seconds
Started Jul 29 05:18:40 PM PDT 24
Finished Jul 29 05:18:42 PM PDT 24
Peak memory 205340 kb
Host smart-12f69351-1b8e-40fd-bf5e-3c5ed0068960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717124463 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2717124463
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.4181798444
Short name T30
Test name
Test status
Simulation time 297745060 ps
CPU time 0.89 seconds
Started Jul 29 05:18:37 PM PDT 24
Finished Jul 29 05:18:38 PM PDT 24
Peak memory 205412 kb
Host smart-5cf12198-6fd6-417d-a3f4-ac23c5bcb80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181798444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.4181798444
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1632967100
Short name T228
Test name
Test status
Simulation time 855778936 ps
CPU time 1.89 seconds
Started Jul 29 05:18:44 PM PDT 24
Finished Jul 29 05:18:46 PM PDT 24
Peak memory 205352 kb
Host smart-6db4ba5e-61bd-4bab-8956-e9e836399ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632967100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1632967100
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.341120309
Short name T278
Test name
Test status
Simulation time 301172624 ps
CPU time 1.03 seconds
Started Jul 29 05:18:36 PM PDT 24
Finished Jul 29 05:18:37 PM PDT 24
Peak memory 205556 kb
Host smart-b684cbb3-e470-4fec-ad06-ca9278144dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341120309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.341120309
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.3406009611
Short name T115
Test name
Test status
Simulation time 122574912 ps
CPU time 1.03 seconds
Started Jul 29 05:18:39 PM PDT 24
Finished Jul 29 05:18:40 PM PDT 24
Peak memory 215700 kb
Host smart-60410f4e-fe7f-447c-ab93-79074c50e926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406009611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3406009611
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2359751137
Short name T270
Test name
Test status
Simulation time 3642554534 ps
CPU time 8.14 seconds
Started Jul 29 05:18:32 PM PDT 24
Finished Jul 29 05:18:40 PM PDT 24
Peak memory 205720 kb
Host smart-e436e969-a290-40c5-a14c-ba406f7b0b04
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2359751137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2359751137
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3856837986
Short name T197
Test name
Test status
Simulation time 1075434179 ps
CPU time 3.31 seconds
Started Jul 29 05:18:35 PM PDT 24
Finished Jul 29 05:18:38 PM PDT 24
Peak memory 205368 kb
Host smart-ce156751-1842-4e23-ad71-813b74acdf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856837986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3856837986
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1191649615
Short name T297
Test name
Test status
Simulation time 214500173 ps
CPU time 0.85 seconds
Started Jul 29 05:18:41 PM PDT 24
Finished Jul 29 05:18:41 PM PDT 24
Peak memory 205388 kb
Host smart-3b4255f7-7816-4595-91d5-cc0a506ada87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191649615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1191649615
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.4119994117
Short name T208
Test name
Test status
Simulation time 507893494 ps
CPU time 1.29 seconds
Started Jul 29 05:18:37 PM PDT 24
Finished Jul 29 05:18:39 PM PDT 24
Peak memory 205412 kb
Host smart-04ddf743-5179-45ff-aa07-6a0fe6d50e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119994117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.4119994117
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2880893732
Short name T178
Test name
Test status
Simulation time 2117424708 ps
CPU time 5.91 seconds
Started Jul 29 05:18:39 PM PDT 24
Finished Jul 29 05:18:45 PM PDT 24
Peak memory 205272 kb
Host smart-b51c1549-a084-406e-9a5a-323cad0cddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880893732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2880893732
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1102107118
Short name T240
Test name
Test status
Simulation time 494942631 ps
CPU time 0.82 seconds
Started Jul 29 05:18:44 PM PDT 24
Finished Jul 29 05:18:45 PM PDT 24
Peak memory 205372 kb
Host smart-43d5554f-f851-4a9a-b04d-0b326a1cd064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102107118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1102107118
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.1801591938
Short name T199
Test name
Test status
Simulation time 120587752 ps
CPU time 1.03 seconds
Started Jul 29 05:18:41 PM PDT 24
Finished Jul 29 05:18:42 PM PDT 24
Peak memory 205360 kb
Host smart-34bf0a94-ad03-440e-b78f-ee2790d797be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801591938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.1801591938
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1369353858
Short name T222
Test name
Test status
Simulation time 251031433 ps
CPU time 0.89 seconds
Started Jul 29 05:18:38 PM PDT 24
Finished Jul 29 05:18:39 PM PDT 24
Peak memory 205400 kb
Host smart-f7398fbd-081b-4bc9-9935-ce604125a6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369353858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1369353858
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2704388192
Short name T275
Test name
Test status
Simulation time 505725084 ps
CPU time 1.99 seconds
Started Jul 29 05:18:37 PM PDT 24
Finished Jul 29 05:18:40 PM PDT 24
Peak memory 205400 kb
Host smart-ee4f8aef-4fe5-400e-b029-a52ae3446d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704388192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2704388192
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2407100181
Short name T251
Test name
Test status
Simulation time 417064306 ps
CPU time 1.04 seconds
Started Jul 29 05:18:39 PM PDT 24
Finished Jul 29 05:18:40 PM PDT 24
Peak memory 213616 kb
Host smart-f5d075ec-f9f3-4ec1-8f56-1f3e38666f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407100181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2407100181
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.544244691
Short name T67
Test name
Test status
Simulation time 1232911007 ps
CPU time 2.75 seconds
Started Jul 29 05:18:43 PM PDT 24
Finished Jul 29 05:18:46 PM PDT 24
Peak memory 205376 kb
Host smart-5e838c8b-9687-49ec-abb1-bbf4ccb90d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544244691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.544244691
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.191830128
Short name T33
Test name
Test status
Simulation time 77615744 ps
CPU time 0.89 seconds
Started Jul 29 05:18:45 PM PDT 24
Finished Jul 29 05:18:46 PM PDT 24
Peak memory 213536 kb
Host smart-fcc6ca96-1cfe-42e8-94cf-a046f6a69257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191830128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.191830128
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.4284802119
Short name T22
Test name
Test status
Simulation time 3807378228 ps
CPU time 5.78 seconds
Started Jul 29 05:18:39 PM PDT 24
Finished Jul 29 05:18:44 PM PDT 24
Peak memory 205680 kb
Host smart-a89ea1a4-18cf-427f-95f5-9e2c4e24003b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284802119 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.4284802119
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.922005271
Short name T170
Test name
Test status
Simulation time 3295663145 ps
CPU time 8.75 seconds
Started Jul 29 05:18:38 PM PDT 24
Finished Jul 29 05:18:47 PM PDT 24
Peak memory 205816 kb
Host smart-b4dffe99-01e1-45c4-8077-9e2540602ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922005271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.922005271
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2479103053
Short name T46
Test name
Test status
Simulation time 239021044 ps
CPU time 1.45 seconds
Started Jul 29 05:18:36 PM PDT 24
Finished Jul 29 05:18:38 PM PDT 24
Peak memory 230020 kb
Host smart-03a64d20-5221-4ab9-abeb-494f6b9cc900
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479103053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2479103053
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1038226499
Short name T143
Test name
Test status
Simulation time 823090599 ps
CPU time 2.79 seconds
Started Jul 29 05:18:36 PM PDT 24
Finished Jul 29 05:18:39 PM PDT 24
Peak memory 205616 kb
Host smart-8b77882e-d088-46a6-b916-adb4198a4dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038226499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1038226499
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.3945149542
Short name T122
Test name
Test status
Simulation time 10861163392 ps
CPU time 16.65 seconds
Started Jul 29 05:18:41 PM PDT 24
Finished Jul 29 05:18:58 PM PDT 24
Peak memory 213828 kb
Host smart-261f55b8-0d55-4351-9d05-a224107b32f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945149542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3945149542
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.2706869785
Short name T66
Test name
Test status
Simulation time 22740531646 ps
CPU time 355.59 seconds
Started Jul 29 05:18:40 PM PDT 24
Finished Jul 29 05:24:36 PM PDT 24
Peak memory 222132 kb
Host smart-11b735be-56c4-4977-96d4-2c63f50f5e5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706869785 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.2706869785
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.890161930
Short name T280
Test name
Test status
Simulation time 178447241 ps
CPU time 0.84 seconds
Started Jul 29 05:18:59 PM PDT 24
Finished Jul 29 05:19:01 PM PDT 24
Peak memory 205312 kb
Host smart-4b8db895-1310-456c-bbbd-28575b8e23b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890161930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.890161930
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.540608356
Short name T238
Test name
Test status
Simulation time 1602664365 ps
CPU time 1.82 seconds
Started Jul 29 05:18:59 PM PDT 24
Finished Jul 29 05:19:02 PM PDT 24
Peak memory 205692 kb
Host smart-03284f7d-1908-436e-a6ba-c8ed9b0478ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540608356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.540608356
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1292632244
Short name T252
Test name
Test status
Simulation time 1097027956 ps
CPU time 1.75 seconds
Started Jul 29 05:18:55 PM PDT 24
Finished Jul 29 05:18:57 PM PDT 24
Peak memory 205712 kb
Host smart-847bee40-79b5-4ec3-bab4-6ca7cedecfc9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292632244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1292632244
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3709146470
Short name T195
Test name
Test status
Simulation time 1439246524 ps
CPU time 3.5 seconds
Started Jul 29 05:18:55 PM PDT 24
Finished Jul 29 05:18:59 PM PDT 24
Peak memory 205776 kb
Host smart-389733e1-5109-47ee-b33b-d47f40c203fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709146470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3709146470
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.4153963091
Short name T308
Test name
Test status
Simulation time 6500516113 ps
CPU time 9.85 seconds
Started Jul 29 05:18:55 PM PDT 24
Finished Jul 29 05:19:05 PM PDT 24
Peak memory 213924 kb
Host smart-92570eaa-ffbb-4661-8865-49121c52e5fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153963091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.4153963091
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2725642070
Short name T27
Test name
Test status
Simulation time 92761072 ps
CPU time 0.73 seconds
Started Jul 29 05:18:57 PM PDT 24
Finished Jul 29 05:18:58 PM PDT 24
Peak memory 205364 kb
Host smart-2e2183da-85a9-46b3-a59b-e427ceb68528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725642070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2725642070
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2686638546
Short name T147
Test name
Test status
Simulation time 17207639960 ps
CPU time 11.8 seconds
Started Jul 29 05:18:55 PM PDT 24
Finished Jul 29 05:19:07 PM PDT 24
Peak memory 213916 kb
Host smart-5203f733-f1a6-4bb5-9108-8a7cddf8d343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686638546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2686638546
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.2696735961
Short name T285
Test name
Test status
Simulation time 7360470395 ps
CPU time 7.42 seconds
Started Jul 29 05:18:57 PM PDT 24
Finished Jul 29 05:19:05 PM PDT 24
Peak memory 214756 kb
Host smart-44957b2d-041c-4887-a804-5d53ca32908e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696735961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.2696735961
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.421730169
Short name T249
Test name
Test status
Simulation time 12385100971 ps
CPU time 11.19 seconds
Started Jul 29 05:18:56 PM PDT 24
Finished Jul 29 05:19:07 PM PDT 24
Peak memory 213972 kb
Host smart-1b6ee1ab-23f0-405c-aa69-d527ac19ea0f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421730169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.421730169
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.4275726285
Short name T36
Test name
Test status
Simulation time 8270215865 ps
CPU time 13.73 seconds
Started Jul 29 05:18:58 PM PDT 24
Finished Jul 29 05:19:11 PM PDT 24
Peak memory 213868 kb
Host smart-cc885af4-ce41-45a2-9de6-48557f7df0b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275726285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.4275726285
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2622414416
Short name T166
Test name
Test status
Simulation time 157387131 ps
CPU time 0.74 seconds
Started Jul 29 05:18:56 PM PDT 24
Finished Jul 29 05:18:57 PM PDT 24
Peak memory 205428 kb
Host smart-a59a4ba2-a474-42bd-a208-4e3429be164c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622414416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2622414416
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2833731638
Short name T136
Test name
Test status
Simulation time 68223530529 ps
CPU time 185.81 seconds
Started Jul 29 05:18:56 PM PDT 24
Finished Jul 29 05:22:02 PM PDT 24
Peak memory 215956 kb
Host smart-6afc98ea-63b6-48b3-a973-fd6f113c6b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833731638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2833731638
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2425151957
Short name T181
Test name
Test status
Simulation time 8082456257 ps
CPU time 20.42 seconds
Started Jul 29 05:18:54 PM PDT 24
Finished Jul 29 05:19:15 PM PDT 24
Peak memory 213992 kb
Host smart-786c7a7e-5414-4294-977b-f4d4d85b0f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425151957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2425151957
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.154480929
Short name T214
Test name
Test status
Simulation time 4511006919 ps
CPU time 7.67 seconds
Started Jul 29 05:18:55 PM PDT 24
Finished Jul 29 05:19:03 PM PDT 24
Peak memory 205812 kb
Host smart-690fecf9-be3c-4361-824e-5d8c9b60c189
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154480929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.154480929
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.3040063537
Short name T301
Test name
Test status
Simulation time 1583909014 ps
CPU time 4.76 seconds
Started Jul 29 05:18:54 PM PDT 24
Finished Jul 29 05:18:59 PM PDT 24
Peak memory 205760 kb
Host smart-f6ab022d-a5d5-4f3f-b9ab-ead9d91d31a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040063537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.3040063537
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.2213668889
Short name T286
Test name
Test status
Simulation time 3708368712 ps
CPU time 11.42 seconds
Started Jul 29 05:18:59 PM PDT 24
Finished Jul 29 05:19:10 PM PDT 24
Peak memory 213744 kb
Host smart-e1ab0819-608b-4037-b121-4bc758ad6184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213668889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2213668889
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.2328759776
Short name T194
Test name
Test status
Simulation time 34651998 ps
CPU time 0.82 seconds
Started Jul 29 05:19:01 PM PDT 24
Finished Jul 29 05:19:02 PM PDT 24
Peak memory 205376 kb
Host smart-6fef8f7a-bf8c-4d1a-904d-46c7b3ad42a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328759776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.2328759776
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.908795368
Short name T300
Test name
Test status
Simulation time 7367939734 ps
CPU time 6.69 seconds
Started Jul 29 05:19:01 PM PDT 24
Finished Jul 29 05:19:08 PM PDT 24
Peak memory 213984 kb
Host smart-0249a0a0-7c78-4505-9ca4-84aa382cbc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908795368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.908795368
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2604991573
Short name T242
Test name
Test status
Simulation time 3365283035 ps
CPU time 5.27 seconds
Started Jul 29 05:19:04 PM PDT 24
Finished Jul 29 05:19:10 PM PDT 24
Peak memory 205792 kb
Host smart-d6730343-27cc-4761-86b0-78b165bb7b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604991573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2604991573
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2365490500
Short name T179
Test name
Test status
Simulation time 1436801812 ps
CPU time 2.06 seconds
Started Jul 29 05:18:55 PM PDT 24
Finished Jul 29 05:18:57 PM PDT 24
Peak memory 205708 kb
Host smart-3b71974c-fe85-45a1-8c36-a81e48b20f2e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2365490500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2365490500
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3693001403
Short name T200
Test name
Test status
Simulation time 6257350921 ps
CPU time 5.2 seconds
Started Jul 29 05:18:58 PM PDT 24
Finished Jul 29 05:19:04 PM PDT 24
Peak memory 213912 kb
Host smart-fa1b5d48-ae9c-4c38-bc95-a5fcff73683b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693001403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3693001403
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.973314430
Short name T259
Test name
Test status
Simulation time 30972304 ps
CPU time 0.78 seconds
Started Jul 29 05:19:00 PM PDT 24
Finished Jul 29 05:19:01 PM PDT 24
Peak memory 205360 kb
Host smart-275f36ec-ad3b-4aab-98c6-23759f92963b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973314430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.973314430
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.1097707192
Short name T283
Test name
Test status
Simulation time 17028486721 ps
CPU time 16.31 seconds
Started Jul 29 05:19:03 PM PDT 24
Finished Jul 29 05:19:19 PM PDT 24
Peak memory 213988 kb
Host smart-3fda15e5-f519-4144-9214-4de673fdc1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097707192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.1097707192
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2852742674
Short name T289
Test name
Test status
Simulation time 2525929140 ps
CPU time 8.15 seconds
Started Jul 29 05:19:02 PM PDT 24
Finished Jul 29 05:19:10 PM PDT 24
Peak memory 206036 kb
Host smart-507e33d3-2dc7-4417-ad83-807f1bd728a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852742674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2852742674
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2411930458
Short name T212
Test name
Test status
Simulation time 1618236664 ps
CPU time 3.36 seconds
Started Jul 29 05:19:01 PM PDT 24
Finished Jul 29 05:19:04 PM PDT 24
Peak memory 205700 kb
Host smart-83fc0229-141a-4bdf-a7aa-d7a8350427b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411930458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2411930458
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.2253612183
Short name T138
Test name
Test status
Simulation time 3087835535 ps
CPU time 9.7 seconds
Started Jul 29 05:18:58 PM PDT 24
Finished Jul 29 05:19:08 PM PDT 24
Peak memory 205732 kb
Host smart-e943ce9c-c96c-4c5a-a5f2-1d0001e21506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253612183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2253612183
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1695053688
Short name T211
Test name
Test status
Simulation time 52538493 ps
CPU time 0.83 seconds
Started Jul 29 05:19:03 PM PDT 24
Finished Jul 29 05:19:04 PM PDT 24
Peak memory 205396 kb
Host smart-67942622-2c16-4cc8-b82e-2e1a54cb841f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695053688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1695053688
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1035352820
Short name T232
Test name
Test status
Simulation time 18891238756 ps
CPU time 17.1 seconds
Started Jul 29 05:18:58 PM PDT 24
Finished Jul 29 05:19:15 PM PDT 24
Peak memory 213964 kb
Host smart-008af771-53a8-4056-9531-2bf2c58eb003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035352820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1035352820
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1305781570
Short name T219
Test name
Test status
Simulation time 6188900710 ps
CPU time 8.99 seconds
Started Jul 29 05:18:58 PM PDT 24
Finished Jul 29 05:19:07 PM PDT 24
Peak memory 205796 kb
Host smart-de85a206-1560-47f1-8fe8-d2ea90a443f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305781570 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1305781570
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3363108234
Short name T299
Test name
Test status
Simulation time 2205209413 ps
CPU time 6.85 seconds
Started Jul 29 05:18:57 PM PDT 24
Finished Jul 29 05:19:04 PM PDT 24
Peak memory 205696 kb
Host smart-d86550a5-9e62-4b3c-ad84-ac446d349275
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3363108234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3363108234
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.802894750
Short name T183
Test name
Test status
Simulation time 3237064212 ps
CPU time 3.64 seconds
Started Jul 29 05:18:59 PM PDT 24
Finished Jul 29 05:19:04 PM PDT 24
Peak memory 214008 kb
Host smart-ed468dfc-0159-4e3d-9a66-d042d75663e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802894750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.802894750
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.866932779
Short name T18
Test name
Test status
Simulation time 8169749524 ps
CPU time 7.12 seconds
Started Jul 29 05:18:59 PM PDT 24
Finished Jul 29 05:19:06 PM PDT 24
Peak memory 213888 kb
Host smart-b728123d-b895-48c3-9766-43c0fb22dde0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866932779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.866932779
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.4079438401
Short name T182
Test name
Test status
Simulation time 85899434 ps
CPU time 0.73 seconds
Started Jul 29 05:19:03 PM PDT 24
Finished Jul 29 05:19:04 PM PDT 24
Peak memory 205396 kb
Host smart-cd725eaa-8768-4a10-bc3f-b0e90eaab178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079438401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.4079438401
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.332221948
Short name T192
Test name
Test status
Simulation time 4971960777 ps
CPU time 4.91 seconds
Started Jul 29 05:19:00 PM PDT 24
Finished Jul 29 05:19:05 PM PDT 24
Peak memory 205708 kb
Host smart-7d4d7b44-714f-47b8-849d-0e9c34d479ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332221948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.332221948
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2420310019
Short name T128
Test name
Test status
Simulation time 1821304331 ps
CPU time 3.72 seconds
Started Jul 29 05:19:02 PM PDT 24
Finished Jul 29 05:19:06 PM PDT 24
Peak memory 215160 kb
Host smart-72f21335-076e-432e-bc87-e5bf22069264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420310019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2420310019
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.1674476701
Short name T10
Test name
Test status
Simulation time 3007240363 ps
CPU time 9.45 seconds
Started Jul 29 05:19:01 PM PDT 24
Finished Jul 29 05:19:11 PM PDT 24
Peak memory 214180 kb
Host smart-f706b974-8b36-4b9f-a2cb-919c5481d8d5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1674476701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.1674476701
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.3771504267
Short name T50
Test name
Test status
Simulation time 13296549630 ps
CPU time 36.94 seconds
Started Jul 29 05:19:02 PM PDT 24
Finished Jul 29 05:19:39 PM PDT 24
Peak memory 222092 kb
Host smart-2d0a1244-9d47-4956-a403-a147548c06ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771504267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.3771504267
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2364165467
Short name T57
Test name
Test status
Simulation time 2346545370 ps
CPU time 2.4 seconds
Started Jul 29 05:19:00 PM PDT 24
Finished Jul 29 05:19:02 PM PDT 24
Peak memory 213900 kb
Host smart-5374811d-46b8-471f-9ede-01a17d138299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364165467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2364165467
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.4168697955
Short name T306
Test name
Test status
Simulation time 150840893 ps
CPU time 0.83 seconds
Started Jul 29 05:19:05 PM PDT 24
Finished Jul 29 05:19:06 PM PDT 24
Peak memory 205360 kb
Host smart-3af70f3e-f91f-41e6-acec-1fac41b0f0a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168697955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.4168697955
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3824915840
Short name T250
Test name
Test status
Simulation time 168283036489 ps
CPU time 122.63 seconds
Started Jul 29 05:18:58 PM PDT 24
Finished Jul 29 05:21:00 PM PDT 24
Peak memory 222172 kb
Host smart-844240ee-2e80-4ea3-bc88-3e07f4f73dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824915840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3824915840
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.530158413
Short name T277
Test name
Test status
Simulation time 3031886322 ps
CPU time 6.37 seconds
Started Jul 29 05:19:03 PM PDT 24
Finished Jul 29 05:19:09 PM PDT 24
Peak memory 214060 kb
Host smart-ab51e3bf-860d-48c2-98c4-f1bd102c5b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530158413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.530158413
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1007580446
Short name T177
Test name
Test status
Simulation time 6689930975 ps
CPU time 19.61 seconds
Started Jul 29 05:19:01 PM PDT 24
Finished Jul 29 05:19:20 PM PDT 24
Peak memory 213892 kb
Host smart-967626c3-5cf5-40ff-9663-52be9f42a2cf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1007580446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1007580446
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.1355785148
Short name T184
Test name
Test status
Simulation time 6366414420 ps
CPU time 5.18 seconds
Started Jul 29 05:19:01 PM PDT 24
Finished Jul 29 05:19:06 PM PDT 24
Peak memory 205716 kb
Host smart-0f955705-3afe-46ad-adee-e97c7c67fdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355785148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.1355785148
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.4274616579
Short name T243
Test name
Test status
Simulation time 77037019 ps
CPU time 0.8 seconds
Started Jul 29 05:19:05 PM PDT 24
Finished Jul 29 05:19:07 PM PDT 24
Peak memory 205428 kb
Host smart-fbb5cf7f-6a44-4cce-adfe-00eddd5b7c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274616579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.4274616579
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.720239963
Short name T130
Test name
Test status
Simulation time 12911538226 ps
CPU time 20.94 seconds
Started Jul 29 05:19:07 PM PDT 24
Finished Jul 29 05:19:28 PM PDT 24
Peak memory 213992 kb
Host smart-e83efd14-d54e-4be9-aeae-6c610ad15000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720239963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.720239963
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3963147464
Short name T5
Test name
Test status
Simulation time 8667291184 ps
CPU time 11.69 seconds
Started Jul 29 05:19:06 PM PDT 24
Finished Jul 29 05:19:18 PM PDT 24
Peak memory 213948 kb
Host smart-378c8128-08b4-43c0-9910-0dff0f39891d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963147464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3963147464
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.286909988
Short name T187
Test name
Test status
Simulation time 1040570002 ps
CPU time 2.38 seconds
Started Jul 29 05:19:03 PM PDT 24
Finished Jul 29 05:19:06 PM PDT 24
Peak memory 205792 kb
Host smart-3d0d3c02-4b7c-4857-9078-29b0144220e7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=286909988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.286909988
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1807655253
Short name T305
Test name
Test status
Simulation time 11749365661 ps
CPU time 10.37 seconds
Started Jul 29 05:19:06 PM PDT 24
Finished Jul 29 05:19:17 PM PDT 24
Peak memory 214040 kb
Host smart-6f3bdfbb-59b6-4cc1-a52a-ca07cd5c3a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807655253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1807655253
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.3889344447
Short name T39
Test name
Test status
Simulation time 5598524482 ps
CPU time 5.13 seconds
Started Jul 29 05:19:05 PM PDT 24
Finished Jul 29 05:19:11 PM PDT 24
Peak memory 213832 kb
Host smart-9d366c2f-40ae-4b83-ade8-8e6bfd275705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889344447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.3889344447
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3969059050
Short name T287
Test name
Test status
Simulation time 100317600 ps
CPU time 0.83 seconds
Started Jul 29 05:19:05 PM PDT 24
Finished Jul 29 05:19:06 PM PDT 24
Peak memory 205432 kb
Host smart-14889062-8834-4f8c-a58c-6fad4a04eeaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969059050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3969059050
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2889032116
Short name T210
Test name
Test status
Simulation time 2265052635 ps
CPU time 3.1 seconds
Started Jul 29 05:19:10 PM PDT 24
Finished Jul 29 05:19:13 PM PDT 24
Peak memory 214068 kb
Host smart-580cdbee-07f4-4284-9ae9-5ad4bd929c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889032116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2889032116
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.976190100
Short name T201
Test name
Test status
Simulation time 3756088332 ps
CPU time 6.31 seconds
Started Jul 29 05:19:06 PM PDT 24
Finished Jul 29 05:19:13 PM PDT 24
Peak memory 213988 kb
Host smart-e45ee695-d594-4a72-9706-6c7c5c41d6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976190100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.976190100
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.2126226161
Short name T141
Test name
Test status
Simulation time 5948242727 ps
CPU time 5.2 seconds
Started Jul 29 05:19:04 PM PDT 24
Finished Jul 29 05:19:09 PM PDT 24
Peak memory 214048 kb
Host smart-70d0bd43-3166-4ba5-9137-49de7715452f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126226161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.2126226161
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.1122242350
Short name T236
Test name
Test status
Simulation time 2333939775 ps
CPU time 7.55 seconds
Started Jul 29 05:19:08 PM PDT 24
Finished Jul 29 05:19:15 PM PDT 24
Peak memory 214000 kb
Host smart-c66cab2a-a450-4d33-b4fe-949914f864f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122242350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1122242350
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3048896590
Short name T168
Test name
Test status
Simulation time 50645020 ps
CPU time 0.72 seconds
Started Jul 29 05:18:41 PM PDT 24
Finished Jul 29 05:18:42 PM PDT 24
Peak memory 205420 kb
Host smart-a25640be-43f7-4ba0-858b-47c839c6a39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048896590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3048896590
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3153704105
Short name T290
Test name
Test status
Simulation time 105926819301 ps
CPU time 82.46 seconds
Started Jul 29 05:18:44 PM PDT 24
Finished Jul 29 05:20:07 PM PDT 24
Peak memory 217960 kb
Host smart-37916d74-0a65-4f18-9fab-d3704c672c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153704105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3153704105
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.793547252
Short name T298
Test name
Test status
Simulation time 4020856616 ps
CPU time 9.06 seconds
Started Jul 29 05:18:42 PM PDT 24
Finished Jul 29 05:18:51 PM PDT 24
Peak memory 214028 kb
Host smart-ee0d85c0-7054-400d-906c-41cea6e09093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793547252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.793547252
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2158205393
Short name T268
Test name
Test status
Simulation time 2943133126 ps
CPU time 3.13 seconds
Started Jul 29 05:18:42 PM PDT 24
Finished Jul 29 05:18:45 PM PDT 24
Peak memory 213948 kb
Host smart-d934a389-fbe2-40e8-8a14-95f6a697759e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158205393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2158205393
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.3921745365
Short name T121
Test name
Test status
Simulation time 1425120805 ps
CPU time 4.14 seconds
Started Jul 29 05:18:40 PM PDT 24
Finished Jul 29 05:18:45 PM PDT 24
Peak memory 205404 kb
Host smart-d2e3283d-b460-4352-9677-8741a65f06a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921745365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.3921745365
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3996388436
Short name T237
Test name
Test status
Simulation time 955886781 ps
CPU time 0.96 seconds
Started Jul 29 05:18:45 PM PDT 24
Finished Jul 29 05:18:46 PM PDT 24
Peak memory 205360 kb
Host smart-f7a3b8a5-5977-4de3-bcf1-937c44e2ef36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996388436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3996388436
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.370351370
Short name T207
Test name
Test status
Simulation time 4367907819 ps
CPU time 7.2 seconds
Started Jul 29 05:18:40 PM PDT 24
Finished Jul 29 05:18:48 PM PDT 24
Peak memory 205836 kb
Host smart-9190f66d-be41-48f8-9521-5e7bf453e326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370351370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.370351370
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.865402126
Short name T59
Test name
Test status
Simulation time 551117466 ps
CPU time 2.25 seconds
Started Jul 29 05:18:42 PM PDT 24
Finished Jul 29 05:18:45 PM PDT 24
Peak memory 230096 kb
Host smart-71b74098-6343-4e6b-9ae0-2c6cf5ef3b6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865402126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.865402126
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.1026211285
Short name T149
Test name
Test status
Simulation time 4757087658 ps
CPU time 8.99 seconds
Started Jul 29 05:18:43 PM PDT 24
Finished Jul 29 05:18:52 PM PDT 24
Peak memory 213868 kb
Host smart-7bf74580-a8cb-4688-b48b-4f6e070a9bde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026211285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1026211285
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.3949587192
Short name T64
Test name
Test status
Simulation time 45895807378 ps
CPU time 733.97 seconds
Started Jul 29 05:18:44 PM PDT 24
Finished Jul 29 05:30:58 PM PDT 24
Peak memory 225964 kb
Host smart-1f124c47-2ef7-435e-843f-4903ceb0a4cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949587192 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.3949587192
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2053597419
Short name T282
Test name
Test status
Simulation time 99314623 ps
CPU time 0.72 seconds
Started Jul 29 05:19:04 PM PDT 24
Finished Jul 29 05:19:05 PM PDT 24
Peak memory 205400 kb
Host smart-f2705339-2169-4a04-b0d1-39520d531412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053597419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2053597419
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2769098414
Short name T216
Test name
Test status
Simulation time 6181973170 ps
CPU time 20.37 seconds
Started Jul 29 05:19:06 PM PDT 24
Finished Jul 29 05:19:26 PM PDT 24
Peak memory 213776 kb
Host smart-dfd2b87a-7ed3-4b55-8a2b-153ea80fc6fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769098414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2769098414
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.403570970
Short name T292
Test name
Test status
Simulation time 7082448738 ps
CPU time 5.81 seconds
Started Jul 29 05:19:05 PM PDT 24
Finished Jul 29 05:19:11 PM PDT 24
Peak memory 214144 kb
Host smart-2a979c74-4f3e-4e69-9258-a679ecae204d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403570970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.403570970
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1277919266
Short name T274
Test name
Test status
Simulation time 148718340 ps
CPU time 1.05 seconds
Started Jul 29 05:19:05 PM PDT 24
Finished Jul 29 05:19:06 PM PDT 24
Peak memory 205364 kb
Host smart-f436fa75-961e-42a9-912c-d95f1289beb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277919266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1277919266
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.46079
Short name T124
Test name
Test status
Simulation time 8644616083 ps
CPU time 16.86 seconds
Started Jul 29 05:19:05 PM PDT 24
Finished Jul 29 05:19:22 PM PDT 24
Peak memory 213820 kb
Host smart-de341006-1101-46a0-bed5-9cb12a2d653c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.46079
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.318757988
Short name T193
Test name
Test status
Simulation time 60171787 ps
CPU time 0.71 seconds
Started Jul 29 05:19:06 PM PDT 24
Finished Jul 29 05:19:07 PM PDT 24
Peak memory 205324 kb
Host smart-b99ca3af-c4ed-489c-bf29-44e4d8d632bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318757988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.318757988
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.2869019547
Short name T123
Test name
Test status
Simulation time 8179085256 ps
CPU time 24.87 seconds
Started Jul 29 05:19:04 PM PDT 24
Finished Jul 29 05:19:29 PM PDT 24
Peak memory 205648 kb
Host smart-e86f320e-10dd-444b-afad-b720f10973fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869019547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2869019547
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3572086219
Short name T235
Test name
Test status
Simulation time 108812748 ps
CPU time 0.74 seconds
Started Jul 29 05:19:04 PM PDT 24
Finished Jul 29 05:19:05 PM PDT 24
Peak memory 205372 kb
Host smart-2598a147-2a44-458f-8e04-eb65f625174f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572086219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3572086219
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.3296615902
Short name T151
Test name
Test status
Simulation time 1363088503 ps
CPU time 1.79 seconds
Started Jul 29 05:19:09 PM PDT 24
Finished Jul 29 05:19:10 PM PDT 24
Peak memory 213784 kb
Host smart-8a0e67cc-0834-4383-844d-2a4ffc6a54c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296615902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.3296615902
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.515537886
Short name T310
Test name
Test status
Simulation time 44138577 ps
CPU time 0.75 seconds
Started Jul 29 05:19:10 PM PDT 24
Finished Jul 29 05:19:11 PM PDT 24
Peak memory 205416 kb
Host smart-48a53a3c-534f-4e13-84a0-32d6c6db286c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515537886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.515537886
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1624753170
Short name T246
Test name
Test status
Simulation time 42873215 ps
CPU time 0.75 seconds
Started Jul 29 05:19:08 PM PDT 24
Finished Jul 29 05:19:09 PM PDT 24
Peak memory 205396 kb
Host smart-d47f0cbd-549a-4994-aa97-4a0d3fa54646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624753170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1624753170
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.739635019
Short name T35
Test name
Test status
Simulation time 6659823072 ps
CPU time 16.73 seconds
Started Jul 29 05:19:06 PM PDT 24
Finished Jul 29 05:19:23 PM PDT 24
Peak memory 205672 kb
Host smart-dd5e5da4-c3d4-4e70-9f69-973843e80435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739635019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.739635019
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.2370909237
Short name T185
Test name
Test status
Simulation time 63014343 ps
CPU time 0.72 seconds
Started Jul 29 05:19:13 PM PDT 24
Finished Jul 29 05:19:14 PM PDT 24
Peak memory 205380 kb
Host smart-e4889b68-977d-402a-b2b2-22f2f9e38ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370909237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.2370909237
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.4046788809
Short name T226
Test name
Test status
Simulation time 70735535 ps
CPU time 0.7 seconds
Started Jul 29 05:19:09 PM PDT 24
Finished Jul 29 05:19:10 PM PDT 24
Peak memory 205392 kb
Host smart-ce1a4643-9563-4c53-850a-02ebb96b3ea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046788809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.4046788809
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1019191432
Short name T116
Test name
Test status
Simulation time 5089777882 ps
CPU time 3.52 seconds
Started Jul 29 05:19:13 PM PDT 24
Finished Jul 29 05:19:16 PM PDT 24
Peak memory 213804 kb
Host smart-b783cecd-076b-4b45-9f2f-94a3ec68474c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019191432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1019191432
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.745192580
Short name T169
Test name
Test status
Simulation time 117924249 ps
CPU time 0.94 seconds
Started Jul 29 05:19:10 PM PDT 24
Finished Jul 29 05:19:11 PM PDT 24
Peak memory 205364 kb
Host smart-c88344c0-503d-4d0a-926c-ceef528d18a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745192580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.745192580
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.3465089833
Short name T140
Test name
Test status
Simulation time 4966350196 ps
CPU time 7.4 seconds
Started Jul 29 05:19:12 PM PDT 24
Finished Jul 29 05:19:19 PM PDT 24
Peak memory 213836 kb
Host smart-4791c620-d2cd-4499-bbe1-06786758ce29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465089833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.3465089833
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.2908372277
Short name T215
Test name
Test status
Simulation time 113634274 ps
CPU time 0.73 seconds
Started Jul 29 05:18:42 PM PDT 24
Finished Jul 29 05:18:43 PM PDT 24
Peak memory 205380 kb
Host smart-f1fecaec-b8ff-4338-b0c9-1394d10517fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908372277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.2908372277
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1485099980
Short name T189
Test name
Test status
Simulation time 11919365772 ps
CPU time 11.12 seconds
Started Jul 29 05:18:44 PM PDT 24
Finished Jul 29 05:18:55 PM PDT 24
Peak memory 205732 kb
Host smart-36c102a5-4c90-4ab3-9978-bb0b15ed1a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485099980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1485099980
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.4167755904
Short name T266
Test name
Test status
Simulation time 3285648587 ps
CPU time 11.21 seconds
Started Jul 29 05:18:42 PM PDT 24
Finished Jul 29 05:18:53 PM PDT 24
Peak memory 222176 kb
Host smart-bcb77456-7046-489b-89a4-0edeac85ee4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167755904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.4167755904
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1057968264
Short name T131
Test name
Test status
Simulation time 2531260476 ps
CPU time 1.89 seconds
Started Jul 29 05:18:42 PM PDT 24
Finished Jul 29 05:18:44 PM PDT 24
Peak memory 205788 kb
Host smart-08964f80-0cb9-4571-8d7f-c8dc66ed7fa8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057968264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1057968264
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.2284480394
Short name T257
Test name
Test status
Simulation time 339054222 ps
CPU time 1.2 seconds
Started Jul 29 05:18:40 PM PDT 24
Finished Jul 29 05:18:41 PM PDT 24
Peak memory 205412 kb
Host smart-5296117c-d2bd-411f-8007-261007074341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284480394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.2284480394
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3515671233
Short name T190
Test name
Test status
Simulation time 495886199 ps
CPU time 0.98 seconds
Started Jul 29 05:18:50 PM PDT 24
Finished Jul 29 05:18:51 PM PDT 24
Peak memory 205296 kb
Host smart-88ee4443-a4cf-4c05-9472-394a9e153e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515671233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3515671233
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1563078525
Short name T248
Test name
Test status
Simulation time 10143101726 ps
CPU time 8.25 seconds
Started Jul 29 05:18:43 PM PDT 24
Finished Jul 29 05:18:51 PM PDT 24
Peak memory 214024 kb
Host smart-ca55c41e-963d-4738-b11b-847e5c0d0337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563078525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1563078525
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1828961551
Short name T45
Test name
Test status
Simulation time 646598604 ps
CPU time 1.81 seconds
Started Jul 29 05:18:42 PM PDT 24
Finished Jul 29 05:18:44 PM PDT 24
Peak memory 230068 kb
Host smart-3554417e-add5-4375-a036-029a8999bfc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828961551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1828961551
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.524377471
Short name T254
Test name
Test status
Simulation time 3513538934 ps
CPU time 10.46 seconds
Started Jul 29 05:18:43 PM PDT 24
Finished Jul 29 05:18:53 PM PDT 24
Peak memory 213880 kb
Host smart-08d886db-823b-40bd-ba52-14ea5fcf94a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524377471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.524377471
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.3401575318
Short name T3
Test name
Test status
Simulation time 91378156596 ps
CPU time 1284.15 seconds
Started Jul 29 05:18:43 PM PDT 24
Finished Jul 29 05:40:07 PM PDT 24
Peak memory 235480 kb
Host smart-fbecaf71-7f0e-4f6e-b71c-1755d0870907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401575318 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.3401575318
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2046622040
Short name T262
Test name
Test status
Simulation time 68196292 ps
CPU time 0.79 seconds
Started Jul 29 05:19:11 PM PDT 24
Finished Jul 29 05:19:11 PM PDT 24
Peak memory 205312 kb
Host smart-29d5021b-efb9-4d64-8759-11c27733ae7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046622040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2046622040
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.139932392
Short name T106
Test name
Test status
Simulation time 5062890396 ps
CPU time 4.41 seconds
Started Jul 29 05:19:10 PM PDT 24
Finished Jul 29 05:19:15 PM PDT 24
Peak memory 213824 kb
Host smart-410f255c-4723-45be-97cf-a98bdc096d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139932392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.139932392
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3383598330
Short name T43
Test name
Test status
Simulation time 66171199 ps
CPU time 0.83 seconds
Started Jul 29 05:19:12 PM PDT 24
Finished Jul 29 05:19:13 PM PDT 24
Peak memory 205336 kb
Host smart-3fcea2f5-06d7-49dc-b068-5b321cbc3b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383598330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3383598330
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.61559226
Short name T127
Test name
Test status
Simulation time 7314557643 ps
CPU time 8.55 seconds
Started Jul 29 05:19:11 PM PDT 24
Finished Jul 29 05:19:20 PM PDT 24
Peak memory 205640 kb
Host smart-746ab115-ab57-4a24-983a-98cd29c4dfdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61559226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.61559226
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.114865117
Short name T167
Test name
Test status
Simulation time 133854134 ps
CPU time 0.76 seconds
Started Jul 29 05:19:17 PM PDT 24
Finished Jul 29 05:19:18 PM PDT 24
Peak memory 205380 kb
Host smart-e5134c1d-a3d6-4490-8118-a667c47cd58e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114865117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.114865117
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.1326469677
Short name T139
Test name
Test status
Simulation time 7721462579 ps
CPU time 22.52 seconds
Started Jul 29 05:19:10 PM PDT 24
Finished Jul 29 05:19:33 PM PDT 24
Peak memory 213804 kb
Host smart-255bd0b2-6974-42e5-967e-7d832191881a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326469677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.1326469677
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2222910395
Short name T180
Test name
Test status
Simulation time 87653903 ps
CPU time 0.72 seconds
Started Jul 29 05:19:10 PM PDT 24
Finished Jul 29 05:19:10 PM PDT 24
Peak memory 205404 kb
Host smart-ae87d5fb-149c-4d44-aae6-969967c5741b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222910395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2222910395
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.3083042727
Short name T1
Test name
Test status
Simulation time 2922271036 ps
CPU time 3.87 seconds
Started Jul 29 05:19:10 PM PDT 24
Finished Jul 29 05:19:14 PM PDT 24
Peak memory 213832 kb
Host smart-882ae330-77fd-43f0-b28b-fc557bbfd418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083042727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3083042727
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1912261319
Short name T191
Test name
Test status
Simulation time 95943786 ps
CPU time 0.73 seconds
Started Jul 29 05:19:11 PM PDT 24
Finished Jul 29 05:19:12 PM PDT 24
Peak memory 205320 kb
Host smart-35df3dc1-45c3-4412-8b91-3f02bf0198ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912261319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1912261319
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2078466164
Short name T247
Test name
Test status
Simulation time 4126574496 ps
CPU time 3.86 seconds
Started Jul 29 05:19:17 PM PDT 24
Finished Jul 29 05:19:21 PM PDT 24
Peak memory 213876 kb
Host smart-84f77048-fbab-48b5-b74c-85208b7bcebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078466164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2078466164
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2815317680
Short name T213
Test name
Test status
Simulation time 33178315 ps
CPU time 0.75 seconds
Started Jul 29 05:19:11 PM PDT 24
Finished Jul 29 05:19:12 PM PDT 24
Peak memory 205356 kb
Host smart-07c9d2a3-fae6-49bf-aaef-0ebb4cee595e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815317680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2815317680
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.763209755
Short name T4
Test name
Test status
Simulation time 2655060233 ps
CPU time 8.25 seconds
Started Jul 29 05:19:10 PM PDT 24
Finished Jul 29 05:19:18 PM PDT 24
Peak memory 205688 kb
Host smart-26e44c8f-a39b-4695-a5d7-815e44b1728f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763209755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.763209755
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1534932745
Short name T302
Test name
Test status
Simulation time 62879875 ps
CPU time 0.7 seconds
Started Jul 29 05:19:12 PM PDT 24
Finished Jul 29 05:19:13 PM PDT 24
Peak memory 205416 kb
Host smart-8f8af4a6-b409-44e0-bca3-81cdf177d0a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534932745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1534932745
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.491266243
Short name T233
Test name
Test status
Simulation time 2653694893 ps
CPU time 2.76 seconds
Started Jul 29 05:19:10 PM PDT 24
Finished Jul 29 05:19:13 PM PDT 24
Peak memory 213856 kb
Host smart-c39c99fd-5e70-459c-927f-dc427b0af8fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491266243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.491266243
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3913451242
Short name T171
Test name
Test status
Simulation time 70124038 ps
CPU time 0.86 seconds
Started Jul 29 05:19:11 PM PDT 24
Finished Jul 29 05:19:12 PM PDT 24
Peak memory 205428 kb
Host smart-7783b4ad-ce94-4eb8-bf8c-957513e3cbd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913451242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3913451242
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.4161041185
Short name T132
Test name
Test status
Simulation time 7415010108 ps
CPU time 6.32 seconds
Started Jul 29 05:19:10 PM PDT 24
Finished Jul 29 05:19:17 PM PDT 24
Peak memory 213892 kb
Host smart-66cba7eb-a1a8-4862-aee9-eabd0ea5be26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161041185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.4161041185
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3979257107
Short name T172
Test name
Test status
Simulation time 85060200 ps
CPU time 0.82 seconds
Started Jul 29 05:19:11 PM PDT 24
Finished Jul 29 05:19:12 PM PDT 24
Peak memory 205580 kb
Host smart-7dee8245-f05e-4771-a423-a4ac603e8ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979257107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3979257107
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.399902263
Short name T291
Test name
Test status
Simulation time 3953061871 ps
CPU time 6.63 seconds
Started Jul 29 05:19:12 PM PDT 24
Finished Jul 29 05:19:18 PM PDT 24
Peak memory 214052 kb
Host smart-8c92ab11-c776-4ae5-ad7f-343bdfe9a3b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399902263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.399902263
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2139000543
Short name T217
Test name
Test status
Simulation time 115388800 ps
CPU time 0.93 seconds
Started Jul 29 05:19:12 PM PDT 24
Finished Jul 29 05:19:13 PM PDT 24
Peak memory 205348 kb
Host smart-e58c933e-60d1-4510-af08-3294ea6c7a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139000543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2139000543
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3943637274
Short name T294
Test name
Test status
Simulation time 5122544004 ps
CPU time 8.69 seconds
Started Jul 29 05:19:11 PM PDT 24
Finished Jul 29 05:19:20 PM PDT 24
Peak memory 205668 kb
Host smart-1a4c0188-e778-497e-90ba-4493ddcfd0a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943637274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3943637274
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.726560699
Short name T202
Test name
Test status
Simulation time 131092236 ps
CPU time 1.02 seconds
Started Jul 29 05:18:43 PM PDT 24
Finished Jul 29 05:18:44 PM PDT 24
Peak memory 205388 kb
Host smart-edc16816-f7f1-4a03-a804-27acd779cd17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726560699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.726560699
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.255270726
Short name T206
Test name
Test status
Simulation time 775768769 ps
CPU time 2.08 seconds
Started Jul 29 05:18:41 PM PDT 24
Finished Jul 29 05:18:43 PM PDT 24
Peak memory 205900 kb
Host smart-f80ba96e-d321-43e7-90d6-d5f03b6c917b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255270726 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.255270726
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3321799037
Short name T269
Test name
Test status
Simulation time 7062475169 ps
CPU time 5.89 seconds
Started Jul 29 05:18:43 PM PDT 24
Finished Jul 29 05:18:50 PM PDT 24
Peak memory 214180 kb
Host smart-2cf385aa-7b42-4c49-99b1-de4f1e01363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321799037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3321799037
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2667799446
Short name T273
Test name
Test status
Simulation time 13574066094 ps
CPU time 40.14 seconds
Started Jul 29 05:18:44 PM PDT 24
Finished Jul 29 05:19:24 PM PDT 24
Peak memory 213876 kb
Host smart-ac5ba183-513e-4299-81fd-e8633813eb40
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667799446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2667799446
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.3663531230
Short name T225
Test name
Test status
Simulation time 927674285 ps
CPU time 2.96 seconds
Started Jul 29 05:18:43 PM PDT 24
Finished Jul 29 05:18:47 PM PDT 24
Peak memory 205388 kb
Host smart-83975781-1477-425c-b1ca-59d61762fbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663531230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.3663531230
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2988355720
Short name T204
Test name
Test status
Simulation time 1135422168 ps
CPU time 1.45 seconds
Started Jul 29 05:18:40 PM PDT 24
Finished Jul 29 05:18:42 PM PDT 24
Peak memory 205388 kb
Host smart-000309c2-90c5-4717-844a-6dee7be97707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988355720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2988355720
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1168177535
Short name T304
Test name
Test status
Simulation time 11055565451 ps
CPU time 8.07 seconds
Started Jul 29 05:18:43 PM PDT 24
Finished Jul 29 05:18:51 PM PDT 24
Peak memory 205792 kb
Host smart-469a8b2c-13f4-4af6-9f59-fdac1b056837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168177535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1168177535
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1135511749
Short name T58
Test name
Test status
Simulation time 779377073 ps
CPU time 2.29 seconds
Started Jul 29 05:18:45 PM PDT 24
Finished Jul 29 05:18:47 PM PDT 24
Peak memory 229688 kb
Host smart-6d7f3ad3-af0b-4a73-86d9-915ca7a193e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135511749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1135511749
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.673808077
Short name T284
Test name
Test status
Simulation time 952202416 ps
CPU time 3.18 seconds
Started Jul 29 05:18:42 PM PDT 24
Finished Jul 29 05:18:45 PM PDT 24
Peak memory 213564 kb
Host smart-14936dce-0068-496c-b94c-45696a227c66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673808077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.673808077
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.1002814195
Short name T17
Test name
Test status
Simulation time 92937438399 ps
CPU time 975.36 seconds
Started Jul 29 05:18:43 PM PDT 24
Finished Jul 29 05:34:59 PM PDT 24
Peak memory 237228 kb
Host smart-bde81d41-8040-4b0b-b611-dbc1f4fa0a3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002814195 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.1002814195
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3413112352
Short name T223
Test name
Test status
Simulation time 49924282 ps
CPU time 0.76 seconds
Started Jul 29 05:19:12 PM PDT 24
Finished Jul 29 05:19:13 PM PDT 24
Peak memory 205440 kb
Host smart-6026f735-dfb4-49ff-b4fe-a50999a06d11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413112352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3413112352
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.29856456
Short name T142
Test name
Test status
Simulation time 1086258667 ps
CPU time 2.1 seconds
Started Jul 29 05:19:09 PM PDT 24
Finished Jul 29 05:19:12 PM PDT 24
Peak memory 205612 kb
Host smart-0940b6de-51d1-4025-b487-16ef15debb78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29856456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.29856456
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1792282533
Short name T2
Test name
Test status
Simulation time 32842896 ps
CPU time 0.76 seconds
Started Jul 29 05:19:22 PM PDT 24
Finished Jul 29 05:19:23 PM PDT 24
Peak memory 205580 kb
Host smart-ba30e6bd-4369-4715-8330-1ef74ae729ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792282533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1792282533
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.830363102
Short name T9
Test name
Test status
Simulation time 2614511078 ps
CPU time 6.93 seconds
Started Jul 29 05:19:09 PM PDT 24
Finished Jul 29 05:19:17 PM PDT 24
Peak memory 205604 kb
Host smart-9efd96ff-76eb-4eda-8499-8f67080e0525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830363102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.830363102
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3146006887
Short name T267
Test name
Test status
Simulation time 98613962 ps
CPU time 0.8 seconds
Started Jul 29 05:19:21 PM PDT 24
Finished Jul 29 05:19:22 PM PDT 24
Peak memory 205328 kb
Host smart-847b2b03-9dfe-4982-a6be-67a186c573f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146006887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3146006887
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.2948119006
Short name T220
Test name
Test status
Simulation time 7392125017 ps
CPU time 4.53 seconds
Started Jul 29 05:19:17 PM PDT 24
Finished Jul 29 05:19:21 PM PDT 24
Peak memory 213868 kb
Host smart-b600352e-d028-4062-92cb-bb8168b8a921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948119006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2948119006
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.2695664952
Short name T303
Test name
Test status
Simulation time 82963056 ps
CPU time 0.82 seconds
Started Jul 29 05:19:18 PM PDT 24
Finished Jul 29 05:19:19 PM PDT 24
Peak memory 205308 kb
Host smart-5ff817c3-1065-4529-8f9f-9cec8ad79e06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695664952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2695664952
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.4291870363
Short name T263
Test name
Test status
Simulation time 156493016 ps
CPU time 0.76 seconds
Started Jul 29 05:19:17 PM PDT 24
Finished Jul 29 05:19:17 PM PDT 24
Peak memory 205408 kb
Host smart-556ce4c2-b91b-4fad-b043-31901edca66d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291870363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.4291870363
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.2320652063
Short name T13
Test name
Test status
Simulation time 8423835907 ps
CPU time 7.31 seconds
Started Jul 29 05:19:19 PM PDT 24
Finished Jul 29 05:19:26 PM PDT 24
Peak memory 205668 kb
Host smart-895871c9-e93d-43f6-b69f-6987d9e386ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320652063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.2320652063
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2993367760
Short name T258
Test name
Test status
Simulation time 53808066 ps
CPU time 0.85 seconds
Started Jul 29 05:19:17 PM PDT 24
Finished Jul 29 05:19:18 PM PDT 24
Peak memory 205396 kb
Host smart-229537f0-7f52-44f2-ba9a-6776e3577e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993367760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2993367760
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1573029513
Short name T134
Test name
Test status
Simulation time 4489985753 ps
CPU time 5.64 seconds
Started Jul 29 05:19:18 PM PDT 24
Finished Jul 29 05:19:24 PM PDT 24
Peak memory 213876 kb
Host smart-87f52bfd-555f-43d9-ab42-200df42aa9c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573029513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1573029513
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.187376882
Short name T276
Test name
Test status
Simulation time 84447706 ps
CPU time 0.74 seconds
Started Jul 29 05:19:19 PM PDT 24
Finished Jul 29 05:19:20 PM PDT 24
Peak memory 205376 kb
Host smart-5848feed-0fd4-4887-9f1a-a74dd8204491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187376882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.187376882
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.2892614190
Short name T260
Test name
Test status
Simulation time 1232290711 ps
CPU time 2.8 seconds
Started Jul 29 05:19:16 PM PDT 24
Finished Jul 29 05:19:19 PM PDT 24
Peak memory 213784 kb
Host smart-2da4aa4f-8cfb-47e1-bc8d-fbb20cbdae84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892614190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2892614190
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2236677777
Short name T234
Test name
Test status
Simulation time 151892211 ps
CPU time 0.81 seconds
Started Jul 29 05:19:15 PM PDT 24
Finished Jul 29 05:19:16 PM PDT 24
Peak memory 205428 kb
Host smart-1790c3cf-59dd-47aa-b5f7-0ca828f9634d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236677777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2236677777
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.4116532855
Short name T288
Test name
Test status
Simulation time 9602143888 ps
CPU time 3.92 seconds
Started Jul 29 05:19:18 PM PDT 24
Finished Jul 29 05:19:22 PM PDT 24
Peak memory 205660 kb
Host smart-e4b35d04-83da-45b4-908a-25bfd19b9aa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116532855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.4116532855
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1527176631
Short name T307
Test name
Test status
Simulation time 59314936 ps
CPU time 0.76 seconds
Started Jul 29 05:19:18 PM PDT 24
Finished Jul 29 05:19:19 PM PDT 24
Peak memory 205340 kb
Host smart-6d7537d9-6ac9-41ad-9c4e-0ef17ea7b9b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527176631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1527176631
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.1352130863
Short name T125
Test name
Test status
Simulation time 3938461955 ps
CPU time 3.92 seconds
Started Jul 29 05:19:19 PM PDT 24
Finished Jul 29 05:19:23 PM PDT 24
Peak memory 213864 kb
Host smart-96df4d32-cb62-4a29-974e-b3a71c31e0cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352130863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1352130863
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1861774140
Short name T293
Test name
Test status
Simulation time 88286069 ps
CPU time 0.71 seconds
Started Jul 29 05:19:19 PM PDT 24
Finished Jul 29 05:19:20 PM PDT 24
Peak memory 205444 kb
Host smart-f1ebbe00-63bd-4058-a6d7-a1c53ae4b229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861774140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1861774140
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.1522695866
Short name T137
Test name
Test status
Simulation time 10567381616 ps
CPU time 28.72 seconds
Started Jul 29 05:19:18 PM PDT 24
Finished Jul 29 05:19:47 PM PDT 24
Peak memory 205616 kb
Host smart-f0ff3608-33ba-4a10-8d37-7483f363fc35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522695866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.1522695866
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2877859740
Short name T230
Test name
Test status
Simulation time 33891894 ps
CPU time 0.76 seconds
Started Jul 29 05:18:48 PM PDT 24
Finished Jul 29 05:18:49 PM PDT 24
Peak memory 205388 kb
Host smart-e91fb041-fb95-48a7-91d6-8a5143a33dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877859740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2877859740
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3017425387
Short name T265
Test name
Test status
Simulation time 1661498810 ps
CPU time 3.56 seconds
Started Jul 29 05:18:54 PM PDT 24
Finished Jul 29 05:18:58 PM PDT 24
Peak memory 213908 kb
Host smart-777c3a60-47be-48d2-a1f4-7465ba75f6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017425387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3017425387
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3486336930
Short name T261
Test name
Test status
Simulation time 2888255238 ps
CPU time 3.24 seconds
Started Jul 29 05:18:53 PM PDT 24
Finished Jul 29 05:18:56 PM PDT 24
Peak memory 214076 kb
Host smart-47f0f746-5b10-4b43-b0ba-8c18efade8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486336930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3486336930
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1520350648
Short name T144
Test name
Test status
Simulation time 1871583428 ps
CPU time 2.11 seconds
Started Jul 29 05:18:47 PM PDT 24
Finished Jul 29 05:18:50 PM PDT 24
Peak memory 205696 kb
Host smart-2d3cec27-8d24-42c3-90e2-95a5c8ec3a77
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520350648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1520350648
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.4180675040
Short name T29
Test name
Test status
Simulation time 576284807 ps
CPU time 2.29 seconds
Started Jul 29 05:18:47 PM PDT 24
Finished Jul 29 05:18:50 PM PDT 24
Peak memory 205412 kb
Host smart-74e6b1be-4177-4fe4-beeb-0bf23c6cd462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180675040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.4180675040
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3701019461
Short name T63
Test name
Test status
Simulation time 1769466634 ps
CPU time 3.51 seconds
Started Jul 29 05:18:46 PM PDT 24
Finished Jul 29 05:18:50 PM PDT 24
Peak memory 214000 kb
Host smart-8dc68678-c3d0-45be-a4b9-a0cc55f611ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701019461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3701019461
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.384918031
Short name T21
Test name
Test status
Simulation time 4212753033 ps
CPU time 12.7 seconds
Started Jul 29 05:18:47 PM PDT 24
Finished Jul 29 05:19:00 PM PDT 24
Peak memory 213836 kb
Host smart-4d848b2b-3324-447f-8636-2b559176e907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384918031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.384918031
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1270141729
Short name T309
Test name
Test status
Simulation time 88747745 ps
CPU time 0.82 seconds
Started Jul 29 05:18:46 PM PDT 24
Finished Jul 29 05:18:47 PM PDT 24
Peak memory 205392 kb
Host smart-637f0293-be96-443c-ad4d-172588e7742f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270141729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1270141729
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2950684205
Short name T60
Test name
Test status
Simulation time 1722775398 ps
CPU time 2.39 seconds
Started Jul 29 05:18:49 PM PDT 24
Finished Jul 29 05:18:51 PM PDT 24
Peak memory 213924 kb
Host smart-5e598d95-fd40-4ab0-a14d-b3f17114441a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950684205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2950684205
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1596275407
Short name T229
Test name
Test status
Simulation time 831486994 ps
CPU time 1.61 seconds
Started Jul 29 05:18:48 PM PDT 24
Finished Jul 29 05:18:50 PM PDT 24
Peak memory 205676 kb
Host smart-6cf45c23-c95d-4991-b4a4-3abed688c9c2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1596275407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1596275407
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.1423726729
Short name T37
Test name
Test status
Simulation time 186063071 ps
CPU time 0.93 seconds
Started Jul 29 05:18:56 PM PDT 24
Finished Jul 29 05:18:57 PM PDT 24
Peak memory 205416 kb
Host smart-bed7526e-df4e-4616-8685-ed9e12f08c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423726729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.1423726729
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2443014258
Short name T196
Test name
Test status
Simulation time 9292549768 ps
CPU time 11.71 seconds
Started Jul 29 05:18:59 PM PDT 24
Finished Jul 29 05:19:11 PM PDT 24
Peak memory 214004 kb
Host smart-9d26c5b0-ff82-4688-a0d4-9429a3511cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443014258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2443014258
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.3077112750
Short name T49
Test name
Test status
Simulation time 2717876141 ps
CPU time 2.91 seconds
Started Jul 29 05:18:45 PM PDT 24
Finished Jul 29 05:18:48 PM PDT 24
Peak memory 205660 kb
Host smart-150e4490-b206-4ec0-bffa-a1f6236a793f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077112750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.3077112750
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.3474085140
Short name T12
Test name
Test status
Simulation time 91877212806 ps
CPU time 1520.77 seconds
Started Jul 29 05:18:48 PM PDT 24
Finished Jul 29 05:44:09 PM PDT 24
Peak memory 239660 kb
Host smart-bea56b5b-b894-45d4-9cbe-5d2994ad9d69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474085140 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.3474085140
Directory /workspace/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2446867263
Short name T244
Test name
Test status
Simulation time 148283158 ps
CPU time 1.08 seconds
Started Jul 29 05:18:49 PM PDT 24
Finished Jul 29 05:18:50 PM PDT 24
Peak memory 205360 kb
Host smart-5538d1a8-396b-45d2-b31a-5e7279320c46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446867263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2446867263
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1556809612
Short name T25
Test name
Test status
Simulation time 2552893260 ps
CPU time 6.95 seconds
Started Jul 29 05:18:46 PM PDT 24
Finished Jul 29 05:18:53 PM PDT 24
Peak memory 215332 kb
Host smart-0aa20a61-f433-46db-b43f-05eb15f53bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556809612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1556809612
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.1391972475
Short name T175
Test name
Test status
Simulation time 2541292524 ps
CPU time 2.39 seconds
Started Jul 29 05:18:50 PM PDT 24
Finished Jul 29 05:18:52 PM PDT 24
Peak memory 214028 kb
Host smart-e57d6721-92e0-4d13-bf51-0368bffc73e5
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1391972475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.1391972475
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.2470573477
Short name T218
Test name
Test status
Simulation time 1441765571 ps
CPU time 1.7 seconds
Started Jul 29 05:18:57 PM PDT 24
Finished Jul 29 05:18:58 PM PDT 24
Peak memory 205340 kb
Host smart-db7997e5-5ce7-4a01-8968-f3be19c523fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470573477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.2470573477
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.2943768981
Short name T78
Test name
Test status
Simulation time 3032297211 ps
CPU time 5.02 seconds
Started Jul 29 05:18:49 PM PDT 24
Finished Jul 29 05:18:54 PM PDT 24
Peak memory 205772 kb
Host smart-8321ec4e-21c2-48ea-9d86-72c8225558a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943768981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.2943768981
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.2207062624
Short name T146
Test name
Test status
Simulation time 2251109945 ps
CPU time 6.61 seconds
Started Jul 29 05:18:56 PM PDT 24
Finished Jul 29 05:19:03 PM PDT 24
Peak memory 213920 kb
Host smart-54647a30-0696-4f43-be99-5044e25c0120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207062624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.2207062624
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3336878944
Short name T296
Test name
Test status
Simulation time 44077543 ps
CPU time 0.77 seconds
Started Jul 29 05:18:47 PM PDT 24
Finished Jul 29 05:18:48 PM PDT 24
Peak memory 205420 kb
Host smart-1b934948-d080-4beb-8135-b0e2c3f7caa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336878944 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3336878944
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.3406431926
Short name T271
Test name
Test status
Simulation time 9585709781 ps
CPU time 12.94 seconds
Started Jul 29 05:18:56 PM PDT 24
Finished Jul 29 05:19:09 PM PDT 24
Peak memory 213996 kb
Host smart-1a68f6ba-4922-49ca-8cd5-60a0ee3c34f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406431926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.3406431926
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.3131570742
Short name T279
Test name
Test status
Simulation time 2257492774 ps
CPU time 3.3 seconds
Started Jul 29 05:18:55 PM PDT 24
Finished Jul 29 05:18:58 PM PDT 24
Peak memory 214064 kb
Host smart-8af9fd3a-b654-42c2-95e0-2d83b904bca4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3131570742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.3131570742
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.462643069
Short name T62
Test name
Test status
Simulation time 2323227854 ps
CPU time 2.34 seconds
Started Jul 29 05:18:54 PM PDT 24
Finished Jul 29 05:18:56 PM PDT 24
Peak memory 205760 kb
Host smart-8c0f63ad-4e3b-4fef-a6dd-009bd531e9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462643069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.462643069
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.3795143263
Short name T135
Test name
Test status
Simulation time 4737783854 ps
CPU time 6.83 seconds
Started Jul 29 05:18:55 PM PDT 24
Finished Jul 29 05:19:02 PM PDT 24
Peak memory 205608 kb
Host smart-15c40890-fa9d-4505-8cf6-7e1ee665cf31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795143263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3795143263
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.721573331
Short name T20
Test name
Test status
Simulation time 218772740087 ps
CPU time 480.12 seconds
Started Jul 29 05:18:46 PM PDT 24
Finished Jul 29 05:26:46 PM PDT 24
Peak memory 236752 kb
Host smart-0914e69a-bec0-47f8-9faf-c338ea5e5e9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721573331 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.721573331
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1266793031
Short name T188
Test name
Test status
Simulation time 66027075 ps
CPU time 0.84 seconds
Started Jul 29 05:18:57 PM PDT 24
Finished Jul 29 05:18:58 PM PDT 24
Peak memory 205400 kb
Host smart-21d4aeee-20fc-4cd8-a80f-8634d26c3b04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266793031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1266793031
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1680451582
Short name T11
Test name
Test status
Simulation time 107211999678 ps
CPU time 150.04 seconds
Started Jul 29 05:18:59 PM PDT 24
Finished Jul 29 05:21:30 PM PDT 24
Peak memory 216900 kb
Host smart-9e31d09e-1122-4e88-9370-2a3b3d7b2f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680451582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1680451582
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1633439958
Short name T173
Test name
Test status
Simulation time 3251613638 ps
CPU time 9.65 seconds
Started Jul 29 05:18:55 PM PDT 24
Finished Jul 29 05:19:05 PM PDT 24
Peak memory 214596 kb
Host smart-b6bf9329-f8fb-4d6e-be39-15fcd85993f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633439958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1633439958
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2699739721
Short name T176
Test name
Test status
Simulation time 9494151479 ps
CPU time 5.18 seconds
Started Jul 29 05:18:57 PM PDT 24
Finished Jul 29 05:19:03 PM PDT 24
Peak memory 213700 kb
Host smart-f849cdd7-621d-4c2a-89ba-09d07dbb086c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2699739721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2699739721
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1684892233
Short name T118
Test name
Test status
Simulation time 3345592125 ps
CPU time 3.73 seconds
Started Jul 29 05:18:55 PM PDT 24
Finished Jul 29 05:18:59 PM PDT 24
Peak memory 214008 kb
Host smart-469ea1ae-1fe0-493a-8f8b-80b2c24024bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684892233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1684892233
Directory /workspace/9.rv_dm_sba_tl_access/latest
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