Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.83 96.18 85.34 89.91 72.50 88.33 98.21 56.31


Total test records in report: 467
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html

T314 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.897930682 Jul 30 06:35:24 PM PDT 24 Jul 30 06:36:12 PM PDT 24 35840941625 ps
T93 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4047441472 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:27 PM PDT 24 1443346113 ps
T134 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1526069492 Jul 30 06:35:15 PM PDT 24 Jul 30 06:35:32 PM PDT 24 5653844123 ps
T315 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3509635753 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:21 PM PDT 24 110116023 ps
T316 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2412875711 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:33 PM PDT 24 3556540405 ps
T122 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.129898603 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:32 PM PDT 24 2369132893 ps
T317 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2727475153 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:25 PM PDT 24 6491695391 ps
T84 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.882157529 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:26 PM PDT 24 232317372 ps
T318 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1019201904 Jul 30 06:35:24 PM PDT 24 Jul 30 06:35:30 PM PDT 24 5478773266 ps
T85 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1918739828 Jul 30 06:35:17 PM PDT 24 Jul 30 06:35:21 PM PDT 24 128483798 ps
T319 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2219752396 Jul 30 06:35:18 PM PDT 24 Jul 30 06:35:19 PM PDT 24 56412502 ps
T86 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1644779882 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:29 PM PDT 24 2473177641 ps
T320 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3430555137 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:26 PM PDT 24 974098836 ps
T87 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.951465748 Jul 30 06:35:23 PM PDT 24 Jul 30 06:35:29 PM PDT 24 843061669 ps
T321 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2763251065 Jul 30 06:35:23 PM PDT 24 Jul 30 06:35:38 PM PDT 24 5560421239 ps
T88 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.374366602 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:22 PM PDT 24 115374369 ps
T89 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3358770420 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:23 PM PDT 24 302111426 ps
T135 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2624925578 Jul 30 06:35:24 PM PDT 24 Jul 30 06:35:35 PM PDT 24 802654441 ps
T60 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3511844761 Jul 30 06:35:16 PM PDT 24 Jul 30 06:35:18 PM PDT 24 548847255 ps
T322 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.369977975 Jul 30 06:35:18 PM PDT 24 Jul 30 06:35:31 PM PDT 24 9708065009 ps
T323 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2825267916 Jul 30 06:35:24 PM PDT 24 Jul 30 06:35:27 PM PDT 24 90972832 ps
T324 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.672140051 Jul 30 06:35:30 PM PDT 24 Jul 30 06:35:32 PM PDT 24 154418831 ps
T90 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.922715056 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:28 PM PDT 24 638681989 ps
T91 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1847309201 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:30 PM PDT 24 2071036995 ps
T325 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1863134766 Jul 30 06:35:24 PM PDT 24 Jul 30 06:35:26 PM PDT 24 105817182 ps
T326 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3797664459 Jul 30 06:35:21 PM PDT 24 Jul 30 06:37:50 PM PDT 24 54154734590 ps
T327 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1561257662 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:30 PM PDT 24 2603307853 ps
T328 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3048746159 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:45 PM PDT 24 24644146711 ps
T92 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2955763801 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:21 PM PDT 24 99994691 ps
T57 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.669213419 Jul 30 06:35:18 PM PDT 24 Jul 30 06:40:12 PM PDT 24 44075011349 ps
T61 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2842798341 Jul 30 06:35:15 PM PDT 24 Jul 30 06:35:16 PM PDT 24 241505906 ps
T329 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4023375174 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:32 PM PDT 24 7574105848 ps
T330 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1938916566 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:21 PM PDT 24 90031491 ps
T165 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2458144896 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:32 PM PDT 24 1088786427 ps
T331 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2190457110 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:23 PM PDT 24 105677868 ps
T332 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1403088472 Jul 30 06:35:23 PM PDT 24 Jul 30 06:35:27 PM PDT 24 5485773352 ps
T333 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.992426413 Jul 30 06:35:28 PM PDT 24 Jul 30 06:35:31 PM PDT 24 226558090 ps
T62 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.174204353 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:20 PM PDT 24 122752072 ps
T334 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3760276007 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:26 PM PDT 24 345233721 ps
T335 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1762915797 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:24 PM PDT 24 299004849 ps
T98 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2203792304 Jul 30 06:35:13 PM PDT 24 Jul 30 06:35:47 PM PDT 24 2084413362 ps
T336 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3958458216 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:30 PM PDT 24 12584933030 ps
T94 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4267189625 Jul 30 06:35:18 PM PDT 24 Jul 30 06:35:58 PM PDT 24 15918042414 ps
T337 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.4226808292 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:55 PM PDT 24 22793582436 ps
T338 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2149736281 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:23 PM PDT 24 428320511 ps
T339 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1343572936 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:23 PM PDT 24 155527449 ps
T340 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2527662450 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:22 PM PDT 24 120039509 ps
T123 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1728822949 Jul 30 06:35:29 PM PDT 24 Jul 30 06:35:31 PM PDT 24 223411920 ps
T99 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3473995261 Jul 30 06:35:17 PM PDT 24 Jul 30 06:35:19 PM PDT 24 479250658 ps
T341 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2277035062 Jul 30 06:35:26 PM PDT 24 Jul 30 06:35:29 PM PDT 24 413451813 ps
T342 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2795069661 Jul 30 06:35:14 PM PDT 24 Jul 30 06:35:16 PM PDT 24 629658353 ps
T343 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1218266103 Jul 30 06:35:18 PM PDT 24 Jul 30 06:35:59 PM PDT 24 16111988758 ps
T344 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3290331304 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:36 PM PDT 24 12168489777 ps
T345 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2202880479 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:21 PM PDT 24 477326713 ps
T346 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1996107617 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:28 PM PDT 24 663278225 ps
T347 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2513820250 Jul 30 06:35:29 PM PDT 24 Jul 30 06:35:33 PM PDT 24 316325826 ps
T348 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3130878618 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:23 PM PDT 24 229996158 ps
T349 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4282162768 Jul 30 06:35:16 PM PDT 24 Jul 30 06:35:17 PM PDT 24 303424510 ps
T350 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3357563032 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:23 PM PDT 24 137914609 ps
T124 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.158578872 Jul 30 06:35:13 PM PDT 24 Jul 30 06:35:17 PM PDT 24 219337077 ps
T351 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3094337100 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:25 PM PDT 24 97396152 ps
T352 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.228081475 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:30 PM PDT 24 3371587339 ps
T353 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1684482168 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:21 PM PDT 24 258972648 ps
T100 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3738364428 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:23 PM PDT 24 291959088 ps
T354 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.385754196 Jul 30 06:35:15 PM PDT 24 Jul 30 06:35:18 PM PDT 24 132199300 ps
T101 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2957877531 Jul 30 06:35:31 PM PDT 24 Jul 30 06:35:33 PM PDT 24 100140229 ps
T161 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.484938573 Jul 30 06:35:30 PM PDT 24 Jul 30 06:35:40 PM PDT 24 5133665624 ps
T102 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.318195055 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:23 PM PDT 24 221605355 ps
T103 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1727971721 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:24 PM PDT 24 110190338 ps
T355 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2303450804 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:20 PM PDT 24 39908608 ps
T356 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2114044343 Jul 30 06:35:23 PM PDT 24 Jul 30 06:35:24 PM PDT 24 372600592 ps
T110 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2274675686 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:20 PM PDT 24 122328582 ps
T357 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4292004295 Jul 30 06:35:13 PM PDT 24 Jul 30 06:35:14 PM PDT 24 472829428 ps
T358 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2199606561 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:28 PM PDT 24 213212209 ps
T111 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2757207098 Jul 30 06:35:18 PM PDT 24 Jul 30 06:35:52 PM PDT 24 9285260541 ps
T359 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1709109774 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:25 PM PDT 24 1549703146 ps
T113 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2113161197 Jul 30 06:35:16 PM PDT 24 Jul 30 06:36:45 PM PDT 24 42606580472 ps
T360 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.144059870 Jul 30 06:35:25 PM PDT 24 Jul 30 06:35:26 PM PDT 24 403797832 ps
T115 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2849211292 Jul 30 06:35:24 PM PDT 24 Jul 30 06:35:26 PM PDT 24 125624601 ps
T162 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3878392287 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:32 PM PDT 24 2268511046 ps
T361 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3811561441 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:21 PM PDT 24 899126598 ps
T362 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4070878981 Jul 30 06:35:24 PM PDT 24 Jul 30 06:35:27 PM PDT 24 652583336 ps
T169 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.369881277 Jul 30 06:35:28 PM PDT 24 Jul 30 06:35:50 PM PDT 24 1691667148 ps
T363 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.4294862264 Jul 30 06:35:16 PM PDT 24 Jul 30 06:35:22 PM PDT 24 2485766001 ps
T364 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3012840212 Jul 30 06:35:18 PM PDT 24 Jul 30 06:35:31 PM PDT 24 22113134399 ps
T365 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1787130600 Jul 30 06:35:17 PM PDT 24 Jul 30 06:35:18 PM PDT 24 305361750 ps
T366 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1089395506 Jul 30 06:35:32 PM PDT 24 Jul 30 06:35:37 PM PDT 24 272833058 ps
T367 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2061198311 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:37 PM PDT 24 17635444402 ps
T368 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.223853650 Jul 30 06:35:28 PM PDT 24 Jul 30 06:35:33 PM PDT 24 239154588 ps
T58 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3508047710 Jul 30 06:35:11 PM PDT 24 Jul 30 06:36:24 PM PDT 24 23877010372 ps
T369 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2646567541 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:36 PM PDT 24 10668350175 ps
T370 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.860012813 Jul 30 06:35:24 PM PDT 24 Jul 30 06:35:28 PM PDT 24 930184243 ps
T371 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2434462295 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:21 PM PDT 24 330267859 ps
T372 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.516317511 Jul 30 06:35:15 PM PDT 24 Jul 30 06:35:50 PM PDT 24 5032746526 ps
T119 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1231270498 Jul 30 06:35:18 PM PDT 24 Jul 30 06:35:22 PM PDT 24 421163172 ps
T373 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2180033673 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:26 PM PDT 24 281685543 ps
T170 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2544549816 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:44 PM PDT 24 4932913165 ps
T114 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.533717102 Jul 30 06:35:14 PM PDT 24 Jul 30 06:35:15 PM PDT 24 227748145 ps
T374 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2685075454 Jul 30 06:35:24 PM PDT 24 Jul 30 06:35:25 PM PDT 24 94406173 ps
T375 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3322810459 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:20 PM PDT 24 104312121 ps
T376 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1095156796 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:20 PM PDT 24 283191404 ps
T116 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.639291884 Jul 30 06:35:20 PM PDT 24 Jul 30 06:36:14 PM PDT 24 1618562555 ps
T377 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3606222056 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:23 PM PDT 24 288939832 ps
T378 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.566960865 Jul 30 06:35:26 PM PDT 24 Jul 30 06:35:49 PM PDT 24 8084334365 ps
T173 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.390323935 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:58 PM PDT 24 37308648252 ps
T167 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2456904144 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:39 PM PDT 24 3292829282 ps
T117 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4206012338 Jul 30 06:35:24 PM PDT 24 Jul 30 06:35:31 PM PDT 24 99731971 ps
T104 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.543075935 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:30 PM PDT 24 1950269221 ps
T118 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.952778408 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:23 PM PDT 24 174650099 ps
T164 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1284218741 Jul 30 06:35:12 PM PDT 24 Jul 30 06:35:27 PM PDT 24 2366961535 ps
T176 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.561405182 Jul 30 06:35:12 PM PDT 24 Jul 30 06:36:17 PM PDT 24 21415374685 ps
T379 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2594463086 Jul 30 06:35:19 PM PDT 24 Jul 30 06:36:58 PM PDT 24 76099608858 ps
T380 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1148890396 Jul 30 06:35:24 PM PDT 24 Jul 30 06:36:15 PM PDT 24 18424936870 ps
T95 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2286361911 Jul 30 06:35:11 PM PDT 24 Jul 30 06:35:22 PM PDT 24 6484908927 ps
T381 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1009873820 Jul 30 06:35:29 PM PDT 24 Jul 30 06:35:33 PM PDT 24 329919047 ps
T382 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2099268374 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:23 PM PDT 24 906760247 ps
T383 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2325531477 Jul 30 06:35:26 PM PDT 24 Jul 30 06:35:39 PM PDT 24 4972703108 ps
T174 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2131271721 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:39 PM PDT 24 30553113783 ps
T384 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1772624221 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:25 PM PDT 24 393500676 ps
T385 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.99813296 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:25 PM PDT 24 167192415 ps
T171 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1277236564 Jul 30 06:35:28 PM PDT 24 Jul 30 06:35:46 PM PDT 24 2114877979 ps
T386 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2824560794 Jul 30 06:35:18 PM PDT 24 Jul 30 06:35:22 PM PDT 24 909161205 ps
T387 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4250044768 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:56 PM PDT 24 3080120049 ps
T388 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.467730006 Jul 30 06:35:26 PM PDT 24 Jul 30 06:35:35 PM PDT 24 11022294523 ps
T389 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.296326181 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:23 PM PDT 24 1535704062 ps
T120 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.966219 Jul 30 06:35:29 PM PDT 24 Jul 30 06:35:33 PM PDT 24 587092439 ps
T105 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1090013104 Jul 30 06:35:29 PM PDT 24 Jul 30 06:35:37 PM PDT 24 560472705 ps
T390 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3544316901 Jul 30 06:35:16 PM PDT 24 Jul 30 06:35:18 PM PDT 24 914996410 ps
T391 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1742859588 Jul 30 06:35:16 PM PDT 24 Jul 30 06:35:18 PM PDT 24 1086537566 ps
T392 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4043739810 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:24 PM PDT 24 2224019303 ps
T393 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3655820901 Jul 30 06:35:15 PM PDT 24 Jul 30 06:35:17 PM PDT 24 356524667 ps
T172 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2365892279 Jul 30 06:35:25 PM PDT 24 Jul 30 06:35:50 PM PDT 24 2506417156 ps
T394 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.975986584 Jul 30 06:35:18 PM PDT 24 Jul 30 06:35:56 PM PDT 24 3296426680 ps
T395 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3088959846 Jul 30 06:35:22 PM PDT 24 Jul 30 06:36:16 PM PDT 24 29333093438 ps
T163 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1485380287 Jul 30 06:35:14 PM PDT 24 Jul 30 06:35:25 PM PDT 24 1556025527 ps
T396 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3251171675 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:21 PM PDT 24 464990574 ps
T397 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1779373445 Jul 30 06:35:19 PM PDT 24 Jul 30 06:36:38 PM PDT 24 13660859929 ps
T398 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1411098897 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:23 PM PDT 24 2396274920 ps
T399 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.303222671 Jul 30 06:35:18 PM PDT 24 Jul 30 06:35:20 PM PDT 24 45771930 ps
T400 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1102219197 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:25 PM PDT 24 3964303387 ps
T401 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1633357990 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:25 PM PDT 24 486209254 ps
T402 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1351818004 Jul 30 06:35:17 PM PDT 24 Jul 30 06:35:18 PM PDT 24 132940008 ps
T403 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3469689813 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:30 PM PDT 24 530536901 ps
T404 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3347936696 Jul 30 06:35:13 PM PDT 24 Jul 30 06:35:29 PM PDT 24 17531101281 ps
T106 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2185208344 Jul 30 06:35:26 PM PDT 24 Jul 30 06:35:34 PM PDT 24 1663795469 ps
T405 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3989576037 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:25 PM PDT 24 810974142 ps
T406 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3700763163 Jul 30 06:35:25 PM PDT 24 Jul 30 06:35:28 PM PDT 24 178896219 ps
T407 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1373481736 Jul 30 06:35:15 PM PDT 24 Jul 30 06:36:32 PM PDT 24 36636033822 ps
T408 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3410049134 Jul 30 06:35:18 PM PDT 24 Jul 30 06:35:26 PM PDT 24 1660555200 ps
T409 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.844777686 Jul 30 06:35:38 PM PDT 24 Jul 30 06:35:40 PM PDT 24 573454281 ps
T410 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3587499030 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:41 PM PDT 24 13691366694 ps
T411 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1665855741 Jul 30 06:35:23 PM PDT 24 Jul 30 06:35:25 PM PDT 24 88921890 ps
T412 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1316596251 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:35 PM PDT 24 749538622 ps
T413 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2288513875 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:30 PM PDT 24 162210876 ps
T414 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3341735229 Jul 30 06:35:30 PM PDT 24 Jul 30 06:35:39 PM PDT 24 6386341467 ps
T415 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2754386417 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:21 PM PDT 24 270981652 ps
T416 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.771422411 Jul 30 06:35:16 PM PDT 24 Jul 30 06:35:20 PM PDT 24 913531979 ps
T417 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3415653074 Jul 30 06:35:16 PM PDT 24 Jul 30 06:35:50 PM PDT 24 38098519329 ps
T418 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2794311794 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:25 PM PDT 24 234478727 ps
T419 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2493388544 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:21 PM PDT 24 564263224 ps
T420 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.153462786 Jul 30 06:35:11 PM PDT 24 Jul 30 06:35:14 PM PDT 24 148683888 ps
T421 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1690772153 Jul 30 06:35:16 PM PDT 24 Jul 30 06:35:20 PM PDT 24 2515389461 ps
T107 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2977105537 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:25 PM PDT 24 100677829 ps
T422 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.700366502 Jul 30 06:35:17 PM PDT 24 Jul 30 06:35:20 PM PDT 24 239486173 ps
T423 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.988778843 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:22 PM PDT 24 50311814 ps
T424 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1567036534 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:53 PM PDT 24 12918501427 ps
T168 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.770352020 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:39 PM PDT 24 2921466795 ps
T425 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.346101083 Jul 30 06:35:21 PM PDT 24 Jul 30 06:35:22 PM PDT 24 147602341 ps
T108 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3907632427 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:23 PM PDT 24 881688404 ps
T426 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2544073008 Jul 30 06:35:24 PM PDT 24 Jul 30 06:35:26 PM PDT 24 94774578 ps
T427 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.351665267 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:30 PM PDT 24 1624564714 ps
T428 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4000897618 Jul 30 06:35:20 PM PDT 24 Jul 30 06:36:31 PM PDT 24 14597358978 ps
T429 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2262676655 Jul 30 06:35:18 PM PDT 24 Jul 30 06:37:12 PM PDT 24 95145168520 ps
T96 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.4003577089 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:33 PM PDT 24 4255348126 ps
T430 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3666430914 Jul 30 06:35:18 PM PDT 24 Jul 30 06:35:32 PM PDT 24 8304661726 ps
T431 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2348384909 Jul 30 06:35:25 PM PDT 24 Jul 30 06:44:38 PM PDT 24 71282416001 ps
T175 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.298773953 Jul 30 06:35:21 PM PDT 24 Jul 30 06:38:52 PM PDT 24 60354751477 ps
T109 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3606869627 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:32 PM PDT 24 379890626 ps
T432 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2273753642 Jul 30 06:35:29 PM PDT 24 Jul 30 06:35:34 PM PDT 24 607572431 ps
T433 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3975276046 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:32 PM PDT 24 103400899 ps
T434 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.859874034 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:23 PM PDT 24 634826399 ps
T435 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4253991441 Jul 30 06:35:18 PM PDT 24 Jul 30 06:35:23 PM PDT 24 173839419 ps
T436 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.4176180475 Jul 30 06:35:23 PM PDT 24 Jul 30 06:35:26 PM PDT 24 129188675 ps
T437 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1135180208 Jul 30 06:35:25 PM PDT 24 Jul 30 06:35:26 PM PDT 24 95818035 ps
T438 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2368037265 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:28 PM PDT 24 2372940817 ps
T166 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2191338094 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:34 PM PDT 24 2543843338 ps
T439 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3049065097 Jul 30 06:35:30 PM PDT 24 Jul 30 06:35:41 PM PDT 24 320346560 ps
T440 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1545666018 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:26 PM PDT 24 340038358 ps
T441 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.930137804 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:22 PM PDT 24 901027221 ps
T442 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.920652650 Jul 30 06:35:32 PM PDT 24 Jul 30 06:35:36 PM PDT 24 476666064 ps
T443 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.726467021 Jul 30 06:35:17 PM PDT 24 Jul 30 06:35:19 PM PDT 24 975758687 ps
T444 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3786795771 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:23 PM PDT 24 152470700 ps
T445 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.228415502 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:23 PM PDT 24 267339712 ps
T97 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4173888263 Jul 30 06:35:22 PM PDT 24 Jul 30 06:35:37 PM PDT 24 4901466482 ps
T446 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2299190484 Jul 30 06:35:17 PM PDT 24 Jul 30 06:35:26 PM PDT 24 1318415891 ps
T447 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.873826054 Jul 30 06:35:25 PM PDT 24 Jul 30 06:35:34 PM PDT 24 1493868051 ps
T448 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1414461392 Jul 30 06:35:21 PM PDT 24 Jul 30 06:36:34 PM PDT 24 96524753723 ps
T449 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2148803589 Jul 30 06:35:26 PM PDT 24 Jul 30 06:35:34 PM PDT 24 590477309 ps
T450 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3324402584 Jul 30 06:35:28 PM PDT 24 Jul 30 06:35:30 PM PDT 24 198608352 ps
T451 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3609372920 Jul 30 06:35:17 PM PDT 24 Jul 30 06:35:20 PM PDT 24 166168591 ps
T452 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2638411184 Jul 30 06:35:15 PM PDT 24 Jul 30 06:35:20 PM PDT 24 824551516 ps
T453 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4230878540 Jul 30 06:35:17 PM PDT 24 Jul 30 06:35:20 PM PDT 24 88793451 ps
T454 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1533325372 Jul 30 06:35:16 PM PDT 24 Jul 30 06:35:24 PM PDT 24 3452423424 ps
T455 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.99846525 Jul 30 06:35:15 PM PDT 24 Jul 30 06:35:16 PM PDT 24 80248596 ps
T456 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3958689528 Jul 30 06:35:20 PM PDT 24 Jul 30 06:35:24 PM PDT 24 4612067503 ps
T457 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.841042363 Jul 30 06:35:21 PM PDT 24 Jul 30 06:37:01 PM PDT 24 26499097534 ps
T458 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2073365859 Jul 30 06:35:33 PM PDT 24 Jul 30 06:36:17 PM PDT 24 44619280511 ps
T459 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2372321951 Jul 30 06:35:19 PM PDT 24 Jul 30 06:35:56 PM PDT 24 13964924854 ps
T460 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3452767857 Jul 30 06:35:26 PM PDT 24 Jul 30 06:35:27 PM PDT 24 1398406459 ps
T461 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1735357390 Jul 30 06:35:18 PM PDT 24 Jul 30 06:37:59 PM PDT 24 220141982273 ps
T462 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1834632263 Jul 30 06:35:16 PM PDT 24 Jul 30 06:35:25 PM PDT 24 494537692 ps
T463 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1207090015 Jul 30 06:35:16 PM PDT 24 Jul 30 06:35:17 PM PDT 24 202513673 ps
T464 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1424558780 Jul 30 06:35:25 PM PDT 24 Jul 30 06:35:27 PM PDT 24 210231052 ps
T112 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1956288730 Jul 30 06:35:23 PM PDT 24 Jul 30 06:35:25 PM PDT 24 167726012 ps
T465 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4219065384 Jul 30 06:35:25 PM PDT 24 Jul 30 06:36:05 PM PDT 24 49978282712 ps
T466 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3168770134 Jul 30 06:35:25 PM PDT 24 Jul 30 06:35:36 PM PDT 24 1414716850 ps
T467 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3967907532 Jul 30 06:35:27 PM PDT 24 Jul 30 06:35:57 PM PDT 24 5082921753 ps


Test location /workspace/coverage/default/32.rv_dm_stress_all.3114803283
Short name T8
Test name
Test status
Simulation time 7193483885 ps
CPU time 10.07 seconds
Started Jul 30 05:16:16 PM PDT 24
Finished Jul 30 05:16:27 PM PDT 24
Peak memory 213656 kb
Host smart-6aed4901-da24-4908-b8df-1b7d8b10bddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114803283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3114803283
Directory /workspace/32.rv_dm_stress_all/latest


Test location /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.1938278655
Short name T9
Test name
Test status
Simulation time 91024554239 ps
CPU time 248 seconds
Started Jul 30 05:15:53 PM PDT 24
Finished Jul 30 05:20:01 PM PDT 24
Peak memory 233036 kb
Host smart-1fbec780-2504-45d3-a22b-151c43196db1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938278655 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.1938278655
Directory /workspace/6.rv_dm_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.988100331
Short name T25
Test name
Test status
Simulation time 26344761868 ps
CPU time 71.91 seconds
Started Jul 30 05:16:00 PM PDT 24
Finished Jul 30 05:17:12 PM PDT 24
Peak memory 213936 kb
Host smart-72abd374-e060-42a1-8b3f-c609f1176409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988100331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.988100331
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1526069492
Short name T134
Test name
Test status
Simulation time 5653844123 ps
CPU time 16.58 seconds
Started Jul 30 06:35:15 PM PDT 24
Finished Jul 30 06:35:32 PM PDT 24
Peak memory 213948 kb
Host smart-5d3a7d7f-0255-41f8-8c3c-a0730573502d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526069492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1526069492
Directory /workspace/5.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.669213419
Short name T57
Test name
Test status
Simulation time 44075011349 ps
CPU time 293.27 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:40:12 PM PDT 24
Peak memory 230452 kb
Host smart-356b42b8-0c98-4a88-b765-ed2254e606f8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669213419 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.669213419
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest


Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.374147680
Short name T300
Test name
Test status
Simulation time 87627513515 ps
CPU time 42.37 seconds
Started Jul 30 05:16:07 PM PDT 24
Finished Jul 30 05:16:49 PM PDT 24
Peak memory 214696 kb
Host smart-04604736-bcde-4a5c-be66-e38e455b0fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374147680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.374147680
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.1725509572
Short name T53
Test name
Test status
Simulation time 580993994 ps
CPU time 2.2 seconds
Started Jul 30 05:15:30 PM PDT 24
Finished Jul 30 05:15:33 PM PDT 24
Peak memory 205308 kb
Host smart-b0abc9e6-f842-4235-bc7d-bc3fa6183421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725509572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.1725509572
Directory /workspace/0.rv_dm_dmi_failed_op/latest


Test location /workspace/coverage/default/15.rv_dm_stress_all.3653646222
Short name T15
Test name
Test status
Simulation time 6747888135 ps
CPU time 19.24 seconds
Started Jul 30 05:16:04 PM PDT 24
Finished Jul 30 05:16:23 PM PDT 24
Peak memory 213764 kb
Host smart-c7ca9d3a-187a-4b4a-b62f-b042ffef6b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653646222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.3653646222
Directory /workspace/15.rv_dm_stress_all/latest


Test location /workspace/coverage/default/2.rv_dm_sec_cm.1869402840
Short name T48
Test name
Test status
Simulation time 858544259 ps
CPU time 1.69 seconds
Started Jul 30 05:15:44 PM PDT 24
Finished Jul 30 05:15:45 PM PDT 24
Peak memory 229516 kb
Host smart-ff747fee-ef93-4a33-bf42-02cd6b39cf98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869402840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1869402840
Directory /workspace/2.rv_dm_sec_cm/latest


Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.4030621400
Short name T72
Test name
Test status
Simulation time 4764826057 ps
CPU time 6.77 seconds
Started Jul 30 05:15:38 PM PDT 24
Finished Jul 30 05:15:44 PM PDT 24
Peak memory 205580 kb
Host smart-9c90e21a-7d7c-4886-89ca-1164fb13bd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030621400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.4030621400
Directory /workspace/1.rv_dm_sba_debug_disabled/latest


Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.2924852177
Short name T20
Test name
Test status
Simulation time 353921714718 ps
CPU time 500.51 seconds
Started Jul 30 05:15:54 PM PDT 24
Finished Jul 30 05:24:15 PM PDT 24
Peak memory 230360 kb
Host smart-73c89b47-a31f-4ff2-b7fb-67343d3a8b1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924852177 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.2924852177
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.3835616238
Short name T18
Test name
Test status
Simulation time 259196076 ps
CPU time 1.04 seconds
Started Jul 30 05:15:32 PM PDT 24
Finished Jul 30 05:15:33 PM PDT 24
Peak memory 205168 kb
Host smart-2ea80252-03d3-4d7b-9fd0-2ffdcdfa3c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835616238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.3835616238
Directory /workspace/0.rv_dm_cmderr_exception/latest


Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.1819332222
Short name T140
Test name
Test status
Simulation time 4555052695 ps
CPU time 13.54 seconds
Started Jul 30 05:15:25 PM PDT 24
Finished Jul 30 05:15:39 PM PDT 24
Peak memory 213916 kb
Host smart-41239c74-e905-44de-89b2-d570cb7cbd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819332222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.1819332222
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/3.rv_dm_alert_test.1404307028
Short name T45
Test name
Test status
Simulation time 57195860 ps
CPU time 0.74 seconds
Started Jul 30 05:15:47 PM PDT 24
Finished Jul 30 05:15:48 PM PDT 24
Peak memory 205292 kb
Host smart-480cb544-b114-4058-998e-e5601b4085fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404307028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1404307028
Directory /workspace/3.rv_dm_alert_test/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.129898603
Short name T122
Test name
Test status
Simulation time 2369132893 ps
CPU time 9.74 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:32 PM PDT 24
Peak memory 213964 kb
Host smart-38fe8395-1ae0-4fa0-aebf-5f7d6465da41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129898603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.129898603
Directory /workspace/2.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1918739828
Short name T85
Test name
Test status
Simulation time 128483798 ps
CPU time 3.79 seconds
Started Jul 30 06:35:17 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 205692 kb
Host smart-e4eede47-e725-4d74-93df-ce0cd3679035
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918739828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1918739828
Directory /workspace/1.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/default/0.rv_dm_rom_read_access.4286203766
Short name T36
Test name
Test status
Simulation time 88281245 ps
CPU time 0.97 seconds
Started Jul 30 05:15:27 PM PDT 24
Finished Jul 30 05:15:28 PM PDT 24
Peak memory 213464 kb
Host smart-3e890282-f617-4014-85b1-e3bbd48df360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286203766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.4286203766
Directory /workspace/0.rv_dm_rom_read_access/latest


Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.2019899492
Short name T139
Test name
Test status
Simulation time 10446812608 ps
CPU time 10.48 seconds
Started Jul 30 05:16:05 PM PDT 24
Finished Jul 30 05:16:15 PM PDT 24
Peak memory 215704 kb
Host smart-e756127b-8e0b-43ca-b227-3ec8522e81c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019899492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.2019899492
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/12.rv_dm_stress_all.2064936121
Short name T21
Test name
Test status
Simulation time 5342004632 ps
CPU time 12.07 seconds
Started Jul 30 05:16:02 PM PDT 24
Finished Jul 30 05:16:14 PM PDT 24
Peak memory 213832 kb
Host smart-6a2ec1bc-82e0-4974-b95b-7343c881ebe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064936121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2064936121
Directory /workspace/12.rv_dm_stress_all/latest


Test location /workspace/coverage/default/29.rv_dm_stress_all.1482936481
Short name T41
Test name
Test status
Simulation time 5071033567 ps
CPU time 4.75 seconds
Started Jul 30 05:16:11 PM PDT 24
Finished Jul 30 05:16:16 PM PDT 24
Peak memory 205540 kb
Host smart-7e12755b-cd9e-433a-800f-e576e8fb49bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482936481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.1482936481
Directory /workspace/29.rv_dm_stress_all/latest


Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.3831661544
Short name T27
Test name
Test status
Simulation time 252923354 ps
CPU time 0.92 seconds
Started Jul 30 05:15:30 PM PDT 24
Finished Jul 30 05:15:31 PM PDT 24
Peak memory 205244 kb
Host smart-3b1a96b2-c30b-439e-a103-17fc37a78351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831661544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.3831661544
Directory /workspace/0.rv_dm_hartsel_warl/latest


Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1956288730
Short name T112
Test name
Test status
Simulation time 167726012 ps
CPU time 1.57 seconds
Started Jul 30 06:35:23 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 213824 kb
Host smart-cd7a1349-8146-4cd0-8249-3587d9c4b20d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956288730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1956288730
Directory /workspace/11.rv_dm_csr_rw/latest


Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.1151755797
Short name T40
Test name
Test status
Simulation time 1369925425 ps
CPU time 4.46 seconds
Started Jul 30 05:15:45 PM PDT 24
Finished Jul 30 05:15:49 PM PDT 24
Peak memory 205312 kb
Host smart-2676cfe1-3117-4e63-906c-18e96295ed69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151755797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.1151755797
Directory /workspace/3.rv_dm_halt_resume_whereto/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.390323935
Short name T173
Test name
Test status
Simulation time 37308648252 ps
CPU time 38.67 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:58 PM PDT 24
Peak memory 219676 kb
Host smart-e5e54bd7-0745-4a39-94ec-9e9d2454b4d9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390323935 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.390323935
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2458144896
Short name T165
Test name
Test status
Simulation time 1088786427 ps
CPU time 9.92 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:32 PM PDT 24
Peak memory 213944 kb
Host smart-760ecd4c-9299-4537-afc3-9a8a66291cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458144896 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
458144896
Directory /workspace/11.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/default/14.rv_dm_stress_all.1017000975
Short name T157
Test name
Test status
Simulation time 3195458475 ps
CPU time 5.91 seconds
Started Jul 30 05:16:10 PM PDT 24
Finished Jul 30 05:16:16 PM PDT 24
Peak memory 205580 kb
Host smart-0e6dc840-ef3d-4674-99cf-fed2c61ad1c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017000975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1017000975
Directory /workspace/14.rv_dm_stress_all/latest


Test location /workspace/coverage/default/33.rv_dm_stress_all.1369364378
Short name T82
Test name
Test status
Simulation time 3860805841 ps
CPU time 3.49 seconds
Started Jul 30 05:16:16 PM PDT 24
Finished Jul 30 05:16:20 PM PDT 24
Peak memory 213860 kb
Host smart-113bffd6-e8c8-4081-99ac-cd0b12900f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369364378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.1369364378
Directory /workspace/33.rv_dm_stress_all/latest


Test location /workspace/coverage/default/36.rv_dm_stress_all.2679052865
Short name T121
Test name
Test status
Simulation time 3631563503 ps
CPU time 3.89 seconds
Started Jul 30 05:16:16 PM PDT 24
Finished Jul 30 05:16:20 PM PDT 24
Peak memory 205536 kb
Host smart-72d319c6-e6c8-4458-9510-6bb338898f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679052865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.2679052865
Directory /workspace/36.rv_dm_stress_all/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.4282162768
Short name T349
Test name
Test status
Simulation time 303424510 ps
CPU time 0.9 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:35:17 PM PDT 24
Peak memory 205280 kb
Host smart-7727985e-f282-4849-bf78-3f5ae9fb22d7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282162768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.4282162768
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest


Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.2845156403
Short name T44
Test name
Test status
Simulation time 78974296 ps
CPU time 0.87 seconds
Started Jul 30 05:15:28 PM PDT 24
Finished Jul 30 05:15:29 PM PDT 24
Peak memory 205236 kb
Host smart-3dceb75e-6cb2-4023-b228-6cb17abe6a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845156403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.2845156403
Directory /workspace/0.rv_dm_abstractcmd_status/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.4173888263
Short name T97
Test name
Test status
Simulation time 4901466482 ps
CPU time 15.16 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:37 PM PDT 24
Peak memory 205688 kb
Host smart-51a29942-b445-4114-92c0-d8bc5187562c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173888263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.4173888263
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.318195055
Short name T102
Test name
Test status
Simulation time 221605355 ps
CPU time 1.69 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 213792 kb
Host smart-7543a3eb-c54d-4ee3-ac36-a09b4b9ce87b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318195055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.318195055
Directory /workspace/14.rv_dm_csr_rw/latest


Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2435599188
Short name T34
Test name
Test status
Simulation time 702244620 ps
CPU time 1.5 seconds
Started Jul 30 05:15:26 PM PDT 24
Finished Jul 30 05:15:28 PM PDT 24
Peak memory 205272 kb
Host smart-8b75f536-5284-482c-b708-86c5febdef1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435599188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2435599188
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest


Test location /workspace/coverage/default/1.rv_dm_debug_disabled.2993049333
Short name T70
Test name
Test status
Simulation time 40434459 ps
CPU time 0.92 seconds
Started Jul 30 05:15:37 PM PDT 24
Finished Jul 30 05:15:38 PM PDT 24
Peak memory 215520 kb
Host smart-472f54ff-6315-4e7b-8911-0e3425831901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993049333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.2993049333
Directory /workspace/1.rv_dm_debug_disabled/latest


Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.770352020
Short name T168
Test name
Test status
Simulation time 2921466795 ps
CPU time 19.54 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:39 PM PDT 24
Peak memory 213940 kb
Host smart-0234f4bc-6919-476a-886c-6b3e7debfe42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770352020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.770352020
Directory /workspace/10.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.4294018640
Short name T150
Test name
Test status
Simulation time 311175598 ps
CPU time 1.61 seconds
Started Jul 30 05:15:38 PM PDT 24
Finished Jul 30 05:15:39 PM PDT 24
Peak memory 205296 kb
Host smart-d0ed4eda-863f-4792-8367-7c381b228f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294018640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.4294018640
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest


Test location /workspace/coverage/default/18.rv_dm_stress_all.55020059
Short name T154
Test name
Test status
Simulation time 7921272295 ps
CPU time 20.03 seconds
Started Jul 30 05:16:05 PM PDT 24
Finished Jul 30 05:16:25 PM PDT 24
Peak memory 213808 kb
Host smart-f9dcbf6a-59fa-4de0-a13b-db00103e5a47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55020059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.55020059
Directory /workspace/18.rv_dm_stress_all/latest


Test location /workspace/coverage/default/26.rv_dm_stress_all.349344134
Short name T147
Test name
Test status
Simulation time 3141444993 ps
CPU time 6.34 seconds
Started Jul 30 05:16:15 PM PDT 24
Finished Jul 30 05:16:21 PM PDT 24
Peak memory 213652 kb
Host smart-9ae85a04-e833-4e9b-a5ac-9979752021c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349344134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.349344134
Directory /workspace/26.rv_dm_stress_all/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4000897618
Short name T428
Test name
Test status
Simulation time 14597358978 ps
CPU time 69.69 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:36:31 PM PDT 24
Peak memory 213908 kb
Host smart-2033f4c1-f783-4db7-91aa-b164684c7048
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000897618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.4000897618
Directory /workspace/0.rv_dm_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.639291884
Short name T116
Test name
Test status
Simulation time 1618562555 ps
CPU time 54.03 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:36:14 PM PDT 24
Peak memory 205632 kb
Host smart-1f99c1dd-e415-4a5d-9cbc-3af19d228817
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639291884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.639291884
Directory /workspace/0.rv_dm_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3609372920
Short name T451
Test name
Test status
Simulation time 166168591 ps
CPU time 2.63 seconds
Started Jul 30 06:35:17 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 213840 kb
Host smart-5430409f-6bfc-44b7-98a9-275f9f4e7501
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609372920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3609372920
Directory /workspace/0.rv_dm_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.158578872
Short name T124
Test name
Test status
Simulation time 219337077 ps
CPU time 3.85 seconds
Started Jul 30 06:35:13 PM PDT 24
Finished Jul 30 06:35:17 PM PDT 24
Peak memory 219976 kb
Host smart-f9a234d1-b5b9-4e8e-83e9-33ae88bf3b87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158578872 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.158578872
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3655820901
Short name T393
Test name
Test status
Simulation time 356524667 ps
CPU time 1.63 seconds
Started Jul 30 06:35:15 PM PDT 24
Finished Jul 30 06:35:17 PM PDT 24
Peak memory 213400 kb
Host smart-9da4e57b-854b-4535-90a2-b26f79ae1a76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655820901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3655820901
Directory /workspace/0.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3088959846
Short name T395
Test name
Test status
Simulation time 29333093438 ps
CPU time 53.79 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:36:16 PM PDT 24
Peak memory 205628 kb
Host smart-8dd7e4cf-c215-4d93-8cee-3bf1dc3c1660
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088959846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3088959846
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.1351818004
Short name T402
Test name
Test status
Simulation time 132940008 ps
CPU time 0.8 seconds
Started Jul 30 06:35:17 PM PDT 24
Finished Jul 30 06:35:18 PM PDT 24
Peak memory 205364 kb
Host smart-a8eb7b6a-c0b1-437f-8110-f5ab93b3e423
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351818004 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.1351818004
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.1411098897
Short name T398
Test name
Test status
Simulation time 2396274920 ps
CPU time 3.94 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 205600 kb
Host smart-e66cbb2a-0d16-4157-b631-569ae0788b0e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411098897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.1
411098897
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3415653074
Short name T417
Test name
Test status
Simulation time 38098519329 ps
CPU time 34.36 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:35:50 PM PDT 24
Peak memory 205604 kb
Host smart-16f1ec55-ff17-491b-9f2e-e34a9309d672
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415653074 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3415653074
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1684482168
Short name T353
Test name
Test status
Simulation time 258972648 ps
CPU time 1.41 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 205368 kb
Host smart-a5fff83b-54ae-4a94-be84-429c8bd67e5b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684482168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1684482168
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1207090015
Short name T463
Test name
Test status
Simulation time 202513673 ps
CPU time 0.95 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:35:17 PM PDT 24
Peak memory 205288 kb
Host smart-c81a7686-8217-4252-8cfc-752b3f5745be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207090015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
207090015
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3357563032
Short name T350
Test name
Test status
Simulation time 137914609 ps
CPU time 0.84 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 205424 kb
Host smart-04e9e668-e0da-403e-9737-3dcca4dadad2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357563032 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3357563032
Directory /workspace/0.rv_dm_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.303222671
Short name T399
Test name
Test status
Simulation time 45771930 ps
CPU time 0.71 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 205356 kb
Host smart-5d7c5dce-e633-4d80-be63-c0574131b7f0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303222671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.303222671
Directory /workspace/0.rv_dm_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3410049134
Short name T408
Test name
Test status
Simulation time 1660555200 ps
CPU time 7.65 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 205688 kb
Host smart-8ac98878-bc6b-4096-b8ee-29471a1ee6d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410049134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3410049134
Directory /workspace/0.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.841042363
Short name T457
Test name
Test status
Simulation time 26499097534 ps
CPU time 99.75 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:37:01 PM PDT 24
Peak memory 222200 kb
Host smart-ea00afc0-f377-4d2a-a5e5-d35d7cfc15d9
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841042363 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.841042363
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.4294862264
Short name T363
Test name
Test status
Simulation time 2485766001 ps
CPU time 6.2 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:35:22 PM PDT 24
Peak memory 214104 kb
Host smart-352da414-841a-42cc-8c3c-1d00537998ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294862264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.4294862264
Directory /workspace/0.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1284218741
Short name T164
Test name
Test status
Simulation time 2366961535 ps
CPU time 14.68 seconds
Started Jul 30 06:35:12 PM PDT 24
Finished Jul 30 06:35:27 PM PDT 24
Peak memory 221976 kb
Host smart-6160568b-d048-4eff-b6d2-4fd29328e490
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284218741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1284218741
Directory /workspace/0.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.2113161197
Short name T113
Test name
Test status
Simulation time 42606580472 ps
CPU time 88.82 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:36:45 PM PDT 24
Peak memory 213908 kb
Host smart-3dc22229-4ac6-45f8-a831-8c5aa6109d59
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113161197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.2113161197
Directory /workspace/1.rv_dm_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.975986584
Short name T394
Test name
Test status
Simulation time 3296426680 ps
CPU time 37.56 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:56 PM PDT 24
Peak memory 213912 kb
Host smart-c4e063d3-fd4f-49ef-864c-a6079a06221b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975986584 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.975986584
Directory /workspace/1.rv_dm_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2180033673
Short name T373
Test name
Test status
Simulation time 281685543 ps
CPU time 3.07 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 213848 kb
Host smart-191104ee-7b2f-4585-b7c4-4c99151afddd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180033673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2180033673
Directory /workspace/1.rv_dm_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.4253991441
Short name T435
Test name
Test status
Simulation time 173839419 ps
CPU time 4.96 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 213872 kb
Host smart-55ef4afd-ef30-4f9a-bde3-aecb4b405a7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253991441 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.4253991441
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.1781345977
Short name T83
Test name
Test status
Simulation time 70333293 ps
CPU time 1.41 seconds
Started Jul 30 06:35:17 PM PDT 24
Finished Jul 30 06:35:18 PM PDT 24
Peak memory 213808 kb
Host smart-0af62623-4172-48f0-aa78-b2da434b7715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781345977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.1781345977
Directory /workspace/1.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2262676655
Short name T429
Test name
Test status
Simulation time 95145168520 ps
CPU time 114.12 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:37:12 PM PDT 24
Peak memory 205632 kb
Host smart-48fd890a-f39a-46c4-87f3-675e7175fae1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262676655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2262676655
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.2372321951
Short name T459
Test name
Test status
Simulation time 13964924854 ps
CPU time 37.36 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:56 PM PDT 24
Peak memory 205652 kb
Host smart-1b85fd1b-ee24-438c-a15c-758b7a1043fc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372321951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.2372321951
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.4003577089
Short name T96
Test name
Test status
Simulation time 4255348126 ps
CPU time 13.03 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:33 PM PDT 24
Peak memory 205692 kb
Host smart-584cf408-93fa-4266-b3ca-ac8075d1f5cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003577089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.4003577089
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.860012813
Short name T370
Test name
Test status
Simulation time 930184243 ps
CPU time 3.41 seconds
Started Jul 30 06:35:24 PM PDT 24
Finished Jul 30 06:35:28 PM PDT 24
Peak memory 205472 kb
Host smart-7d6bf0ea-4ffc-4c2a-88ee-97fad7070a2b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860012813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.860012813
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1742859588
Short name T391
Test name
Test status
Simulation time 1086537566 ps
CPU time 1.99 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:35:18 PM PDT 24
Peak memory 205296 kb
Host smart-e6d81b3d-1636-46ea-b3b8-21c1c648190a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742859588 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1742859588
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.1218266103
Short name T343
Test name
Test status
Simulation time 16111988758 ps
CPU time 40.83 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:59 PM PDT 24
Peak memory 205772 kb
Host smart-9c93b5af-9dbe-4829-b3fc-e08611459ffb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218266103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.1218266103
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.144059870
Short name T360
Test name
Test status
Simulation time 403797832 ps
CPU time 1.26 seconds
Started Jul 30 06:35:25 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 205364 kb
Host smart-a65275c4-01b1-409e-a095-2fd086a8b996
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144059870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.144059870
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2149736281
Short name T338
Test name
Test status
Simulation time 428320511 ps
CPU time 1.32 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 205328 kb
Host smart-23c86ce8-da29-4a0d-a63b-6abdf5c409da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149736281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
149736281
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.99846525
Short name T455
Test name
Test status
Simulation time 80248596 ps
CPU time 0.74 seconds
Started Jul 30 06:35:15 PM PDT 24
Finished Jul 30 06:35:16 PM PDT 24
Peak memory 205404 kb
Host smart-3e8a292d-f9b5-43af-9dc2-0056436b906d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99846525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_parti
al_access.99846525
Directory /workspace/1.rv_dm_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1938916566
Short name T330
Test name
Test status
Simulation time 90031491 ps
CPU time 0.7 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 205320 kb
Host smart-022f9da3-7a3a-4e4f-873d-2e100228803b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938916566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1938916566
Directory /workspace/1.rv_dm_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.2638411184
Short name T452
Test name
Test status
Simulation time 824551516 ps
CPU time 5.43 seconds
Started Jul 30 06:35:15 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 213904 kb
Host smart-a46aa66b-111c-4ef5-800a-f7afe25de911
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638411184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.2638411184
Directory /workspace/1.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1485380287
Short name T163
Test name
Test status
Simulation time 1556025527 ps
CPU time 10.68 seconds
Started Jul 30 06:35:14 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 213900 kb
Host smart-bdcc19dc-ac27-4cdb-a6b6-1ec8081f03b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485380287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1485380287
Directory /workspace/1.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1772624221
Short name T384
Test name
Test status
Simulation time 393500676 ps
CPU time 4.32 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 219332 kb
Host smart-541e5b2a-e858-460b-8e95-f666b850ce73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772624221 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1772624221
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.1665855741
Short name T411
Test name
Test status
Simulation time 88921890 ps
CPU time 2.2 seconds
Started Jul 30 06:35:23 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 213828 kb
Host smart-5c5ea8be-348c-43e6-b284-299e6f2c84e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665855741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.1665855741
Directory /workspace/10.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.2368037265
Short name T438
Test name
Test status
Simulation time 2372940817 ps
CPU time 7.31 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:28 PM PDT 24
Peak memory 205600 kb
Host smart-b90142c2-f8a0-4494-9b3b-c26d66fb34a3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368037265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.2368037265
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.1709109774
Short name T359
Test name
Test status
Simulation time 1549703146 ps
CPU time 2.74 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 205524 kb
Host smart-2d1486df-353d-436e-914a-b54b4ce04fd6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709109774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
1709109774
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.346101083
Short name T425
Test name
Test status
Simulation time 147602341 ps
CPU time 1.01 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:22 PM PDT 24
Peak memory 205356 kb
Host smart-9fce5333-4169-4b90-8797-bfcabbdc320e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346101083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.346101083
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3907632427
Short name T108
Test name
Test status
Simulation time 881688404 ps
CPU time 4.11 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 205640 kb
Host smart-fbdad930-7c0b-41cb-b179-9075c1071afe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907632427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3907632427
Directory /workspace/10.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2794311794
Short name T418
Test name
Test status
Simulation time 234478727 ps
CPU time 2.55 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 213904 kb
Host smart-71b3cca8-fb75-45b3-915f-86af8535a655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794311794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2794311794
Directory /workspace/10.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3989576037
Short name T405
Test name
Test status
Simulation time 810974142 ps
CPU time 3.92 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 222088 kb
Host smart-db57281a-790e-4448-b57e-1892f6e84fce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989576037 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3989576037
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.3048746159
Short name T328
Test name
Test status
Simulation time 24644146711 ps
CPU time 17.79 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:45 PM PDT 24
Peak memory 205656 kb
Host smart-9671787d-cca4-4805-9848-5182bb195946
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048746159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.3048746159
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3587499030
Short name T410
Test name
Test status
Simulation time 13691366694 ps
CPU time 19.46 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:41 PM PDT 24
Peak memory 205624 kb
Host smart-1b8f01a1-866c-4ce0-8aa9-ebe8a671ba61
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587499030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3587499030
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3811561441
Short name T361
Test name
Test status
Simulation time 899126598 ps
CPU time 1.95 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 205292 kb
Host smart-3abae0a5-08f8-4b75-8509-00bd8ce2ed80
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811561441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3811561441
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.882157529
Short name T84
Test name
Test status
Simulation time 232317372 ps
CPU time 3.78 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 205652 kb
Host smart-4a23beb8-7ac1-416d-8c27-54f79a96a043
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882157529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.882157529
Directory /workspace/11.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.3094337100
Short name T351
Test name
Test status
Simulation time 97396152 ps
CPU time 5.12 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 213920 kb
Host smart-f41ca431-96ee-4810-83bc-eb4364c122ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094337100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.3094337100
Directory /workspace/11.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1633357990
Short name T401
Test name
Test status
Simulation time 486209254 ps
CPU time 3.59 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 220272 kb
Host smart-e4651164-b195-4869-8432-8a4d74bbe794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633357990 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1633357990
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.4206012338
Short name T117
Test name
Test status
Simulation time 99731971 ps
CPU time 2.34 seconds
Started Jul 30 06:35:24 PM PDT 24
Finished Jul 30 06:35:31 PM PDT 24
Peak memory 213848 kb
Host smart-34b4a1f0-6564-43ee-846e-344c11b0eab3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206012338 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.4206012338
Directory /workspace/12.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.369977975
Short name T322
Test name
Test status
Simulation time 9708065009 ps
CPU time 12.77 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:31 PM PDT 24
Peak memory 205620 kb
Host smart-c8e04773-18b4-4a7f-9427-d7dc69eea6d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369977975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rv_dm_jtag_dmi_csr_bit_bash.369977975
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4023375174
Short name T329
Test name
Test status
Simulation time 7574105848 ps
CPU time 12.03 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:32 PM PDT 24
Peak memory 205608 kb
Host smart-7c266138-8473-4c92-9966-9d4a46fbdadc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023375174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
4023375174
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2099268374
Short name T382
Test name
Test status
Simulation time 906760247 ps
CPU time 1.33 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 205288 kb
Host smart-48552385-1ef8-4a2c-89bd-f4acb8c87d90
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099268374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2099268374
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1231270498
Short name T119
Test name
Test status
Simulation time 421163172 ps
CPU time 3.53 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:22 PM PDT 24
Peak memory 205620 kb
Host smart-79565997-6823-419a-8dbf-2f28797c5d16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231270498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1231270498
Directory /workspace/12.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2825267916
Short name T323
Test name
Test status
Simulation time 90972832 ps
CPU time 2.52 seconds
Started Jul 30 06:35:24 PM PDT 24
Finished Jul 30 06:35:27 PM PDT 24
Peak memory 213896 kb
Host smart-01d5088a-cf30-4ded-a316-6eb700eee073
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825267916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2825267916
Directory /workspace/12.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1277236564
Short name T171
Test name
Test status
Simulation time 2114877979 ps
CPU time 17.68 seconds
Started Jul 30 06:35:28 PM PDT 24
Finished Jul 30 06:35:46 PM PDT 24
Peak memory 213876 kb
Host smart-5e7b9a2d-2a09-4884-8d4f-478d0a5caf9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277236564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
277236564
Directory /workspace/12.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2513820250
Short name T347
Test name
Test status
Simulation time 316325826 ps
CPU time 4.15 seconds
Started Jul 30 06:35:29 PM PDT 24
Finished Jul 30 06:35:33 PM PDT 24
Peak memory 220280 kb
Host smart-09404b95-a839-4451-a530-7c745b700380
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513820250 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2513820250
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.952778408
Short name T118
Test name
Test status
Simulation time 174650099 ps
CPU time 1.53 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 213816 kb
Host smart-9b8a7e4a-36bb-4388-80a0-4da4318dd2f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952778408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.952778408
Directory /workspace/13.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.3290331304
Short name T344
Test name
Test status
Simulation time 12168489777 ps
CPU time 14.9 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:36 PM PDT 24
Peak memory 205604 kb
Host smart-00c57836-8b34-4319-83dc-61a014bc7cec
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290331304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.3290331304
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3958689528
Short name T456
Test name
Test status
Simulation time 4612067503 ps
CPU time 3.5 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:24 PM PDT 24
Peak memory 205648 kb
Host smart-834d8592-6331-4085-a0e5-c3d606c32d3f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958689528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3958689528
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3606222056
Short name T377
Test name
Test status
Simulation time 288939832 ps
CPU time 0.8 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 205352 kb
Host smart-5ce45948-11de-4030-95b3-d98e0f782899
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606222056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3606222056
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2185208344
Short name T106
Test name
Test status
Simulation time 1663795469 ps
CPU time 7.7 seconds
Started Jul 30 06:35:26 PM PDT 24
Finished Jul 30 06:35:34 PM PDT 24
Peak memory 205732 kb
Host smart-78ad0208-9937-40bc-a947-f35587e6fc39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185208344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2185208344
Directory /workspace/13.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.4176180475
Short name T436
Test name
Test status
Simulation time 129188675 ps
CPU time 3.06 seconds
Started Jul 30 06:35:23 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 214012 kb
Host smart-a4b7a1bf-cfa6-4289-8d4c-913ae0613295
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176180475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.4176180475
Directory /workspace/13.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2191338094
Short name T166
Test name
Test status
Simulation time 2543843338 ps
CPU time 13.96 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:34 PM PDT 24
Peak memory 214000 kb
Host smart-acf2eddc-5326-4e20-ab21-aaeff6d4f1e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191338094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
191338094
Directory /workspace/13.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1009873820
Short name T381
Test name
Test status
Simulation time 329919047 ps
CPU time 3.94 seconds
Started Jul 30 06:35:29 PM PDT 24
Finished Jul 30 06:35:33 PM PDT 24
Peak memory 219436 kb
Host smart-b6edbdf0-839f-4a77-a7b7-17596b42c1da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009873820 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1009873820
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.566960865
Short name T378
Test name
Test status
Simulation time 8084334365 ps
CPU time 23.23 seconds
Started Jul 30 06:35:26 PM PDT 24
Finished Jul 30 06:35:49 PM PDT 24
Peak memory 205636 kb
Host smart-883cbce0-fe86-44db-8a3b-4a341e907a88
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566960865 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
rv_dm_jtag_dmi_csr_bit_bash.566960865
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.1567036534
Short name T424
Test name
Test status
Simulation time 12918501427 ps
CPU time 31.93 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:53 PM PDT 24
Peak memory 205660 kb
Host smart-1cd8c4fa-93e4-4428-ace6-c910aab39b57
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567036534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
1567036534
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2527662450
Short name T340
Test name
Test status
Simulation time 120039509 ps
CPU time 0.83 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:22 PM PDT 24
Peak memory 205320 kb
Host smart-7674443f-f711-4a89-b9f4-6f71d7a89336
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527662450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2527662450
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1316596251
Short name T412
Test name
Test status
Simulation time 749538622 ps
CPU time 7.87 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:35 PM PDT 24
Peak memory 205716 kb
Host smart-4891887d-252d-464c-a672-ae5af249900e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316596251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1316596251
Directory /workspace/14.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2273753642
Short name T432
Test name
Test status
Simulation time 607572431 ps
CPU time 4.54 seconds
Started Jul 30 06:35:29 PM PDT 24
Finished Jul 30 06:35:34 PM PDT 24
Peak memory 213888 kb
Host smart-71151eb6-00f6-472a-bf4c-08d3f98528ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273753642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2273753642
Directory /workspace/14.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3967907532
Short name T467
Test name
Test status
Simulation time 5082921753 ps
CPU time 29.43 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:57 PM PDT 24
Peak memory 214000 kb
Host smart-fb06bcf3-79b7-4710-9ef3-54952bebea0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967907532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
967907532
Directory /workspace/14.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1728822949
Short name T123
Test name
Test status
Simulation time 223411920 ps
CPU time 2.25 seconds
Started Jul 30 06:35:29 PM PDT 24
Finished Jul 30 06:35:31 PM PDT 24
Peak memory 217764 kb
Host smart-1e286369-54d2-4de0-96c2-b1e0c998b781
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728822949 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1728822949
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2849211292
Short name T115
Test name
Test status
Simulation time 125624601 ps
CPU time 2.4 seconds
Started Jul 30 06:35:24 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 213756 kb
Host smart-cb2cc9cd-5a94-403a-b00d-07bd4ad317d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849211292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2849211292
Directory /workspace/15.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.2325531477
Short name T383
Test name
Test status
Simulation time 4972703108 ps
CPU time 12.98 seconds
Started Jul 30 06:35:26 PM PDT 24
Finished Jul 30 06:35:39 PM PDT 24
Peak memory 205776 kb
Host smart-7a22bc79-f9b1-4383-a8cf-7deff0eca772
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325531477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.2325531477
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3452767857
Short name T460
Test name
Test status
Simulation time 1398406459 ps
CPU time 1.34 seconds
Started Jul 30 06:35:26 PM PDT 24
Finished Jul 30 06:35:27 PM PDT 24
Peak memory 205544 kb
Host smart-f1cd4674-24e0-4244-aa13-1ccae3cdd3ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452767857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3452767857
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3251171675
Short name T396
Test name
Test status
Simulation time 464990574 ps
CPU time 1.81 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 205288 kb
Host smart-6f3fcb59-1f28-44b5-8b7b-8001e46f4bab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251171675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3251171675
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1090013104
Short name T105
Test name
Test status
Simulation time 560472705 ps
CPU time 7.92 seconds
Started Jul 30 06:35:29 PM PDT 24
Finished Jul 30 06:35:37 PM PDT 24
Peak memory 205668 kb
Host smart-a1bed1ff-7122-4950-a5f6-7ad4a6917c0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090013104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1090013104
Directory /workspace/15.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.1863134766
Short name T325
Test name
Test status
Simulation time 105817182 ps
CPU time 2.53 seconds
Started Jul 30 06:35:24 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 214008 kb
Host smart-09844e9c-d262-4c21-a921-9b8bf5d51f87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863134766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.1863134766
Directory /workspace/15.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.484938573
Short name T161
Test name
Test status
Simulation time 5133665624 ps
CPU time 10.08 seconds
Started Jul 30 06:35:30 PM PDT 24
Finished Jul 30 06:35:40 PM PDT 24
Peak memory 213904 kb
Host smart-3cf1476d-bc12-4635-a3f1-914264537035
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484938573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.484938573
Directory /workspace/15.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.3469689813
Short name T403
Test name
Test status
Simulation time 530536901 ps
CPU time 3.64 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:30 PM PDT 24
Peak memory 219212 kb
Host smart-6a248f85-7344-4d2b-8b6d-022874f77b60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469689813 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.3469689813
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.2957877531
Short name T101
Test name
Test status
Simulation time 100140229 ps
CPU time 1.67 seconds
Started Jul 30 06:35:31 PM PDT 24
Finished Jul 30 06:35:33 PM PDT 24
Peak memory 213804 kb
Host smart-fd2d0744-d8ad-468f-8af9-f0f488e7fa6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957877531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.2957877531
Directory /workspace/16.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.3958458216
Short name T336
Test name
Test status
Simulation time 12584933030 ps
CPU time 10.63 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:30 PM PDT 24
Peak memory 205656 kb
Host smart-f97e26ff-e93e-49c5-b5cb-006a795255db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958458216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.3958458216
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.467730006
Short name T388
Test name
Test status
Simulation time 11022294523 ps
CPU time 8.32 seconds
Started Jul 30 06:35:26 PM PDT 24
Finished Jul 30 06:35:35 PM PDT 24
Peak memory 205600 kb
Host smart-fba5202f-0f56-4e3b-bb9a-0b451631a3d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467730006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.467730006
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1135180208
Short name T437
Test name
Test status
Simulation time 95818035 ps
CPU time 0.89 seconds
Started Jul 30 06:35:25 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 205344 kb
Host smart-d4c0fc13-5293-4670-8a44-a33ebdf6f41a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135180208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1135180208
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3606869627
Short name T109
Test name
Test status
Simulation time 379890626 ps
CPU time 4.68 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:32 PM PDT 24
Peak memory 205640 kb
Host smart-42cd3d31-b6ec-40d4-be60-1370723b84af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606869627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3606869627
Directory /workspace/16.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3049065097
Short name T439
Test name
Test status
Simulation time 320346560 ps
CPU time 5.91 seconds
Started Jul 30 06:35:30 PM PDT 24
Finished Jul 30 06:35:41 PM PDT 24
Peak memory 213936 kb
Host smart-9f386e53-b5f9-45a5-9f2d-edd7bd8c984d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049065097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3049065097
Directory /workspace/16.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.2624925578
Short name T135
Test name
Test status
Simulation time 802654441 ps
CPU time 10.48 seconds
Started Jul 30 06:35:24 PM PDT 24
Finished Jul 30 06:35:35 PM PDT 24
Peak memory 213872 kb
Host smart-8babfa9e-4666-4549-a1bb-b444aba65588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624925578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.2
624925578
Directory /workspace/16.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.223853650
Short name T368
Test name
Test status
Simulation time 239154588 ps
CPU time 4.82 seconds
Started Jul 30 06:35:28 PM PDT 24
Finished Jul 30 06:35:33 PM PDT 24
Peak memory 213924 kb
Host smart-c670b063-81c8-4e98-8e29-be3fe104d23e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223853650 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.223853650
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1424558780
Short name T464
Test name
Test status
Simulation time 210231052 ps
CPU time 1.5 seconds
Started Jul 30 06:35:25 PM PDT 24
Finished Jul 30 06:35:27 PM PDT 24
Peak memory 213872 kb
Host smart-16042c15-311e-46bc-a0c9-73fb3f46aa33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424558780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1424558780
Directory /workspace/17.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.4226808292
Short name T337
Test name
Test status
Simulation time 22793582436 ps
CPU time 28.42 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:55 PM PDT 24
Peak memory 205628 kb
Host smart-fe720a5f-de2c-4c11-b7ab-d0dc1e822dee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226808292 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.4226808292
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.351665267
Short name T427
Test name
Test status
Simulation time 1624564714 ps
CPU time 3.19 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:30 PM PDT 24
Peak memory 205492 kb
Host smart-c83fc845-6dc7-498c-9d7c-9a400c987606
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351665267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.351665267
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2199606561
Short name T358
Test name
Test status
Simulation time 213212209 ps
CPU time 0.71 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:28 PM PDT 24
Peak memory 205320 kb
Host smart-a38d0ff2-99a9-4883-8a58-9489ad305646
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199606561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2199606561
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1545666018
Short name T440
Test name
Test status
Simulation time 340038358 ps
CPU time 3.54 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 205680 kb
Host smart-a8eca0ea-8d69-467d-8aba-6b5caf6af40e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545666018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1545666018
Directory /workspace/17.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.672140051
Short name T324
Test name
Test status
Simulation time 154418831 ps
CPU time 2.09 seconds
Started Jul 30 06:35:30 PM PDT 24
Finished Jul 30 06:35:32 PM PDT 24
Peak memory 213912 kb
Host smart-ec0ff70c-9a91-448a-beec-2fdbee5ae149
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672140051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.672140051
Directory /workspace/17.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.369881277
Short name T169
Test name
Test status
Simulation time 1691667148 ps
CPU time 22.21 seconds
Started Jul 30 06:35:28 PM PDT 24
Finished Jul 30 06:35:50 PM PDT 24
Peak memory 213864 kb
Host smart-97fb37a6-92ec-44c2-8abd-e5b3c4a77359
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369881277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.369881277
Directory /workspace/17.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3324402584
Short name T450
Test name
Test status
Simulation time 198608352 ps
CPU time 2.46 seconds
Started Jul 30 06:35:28 PM PDT 24
Finished Jul 30 06:35:30 PM PDT 24
Peak memory 222056 kb
Host smart-8cc3e15b-39fb-4e11-87ae-1dcc75f6f1b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324402584 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3324402584
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2288513875
Short name T413
Test name
Test status
Simulation time 162210876 ps
CPU time 2.57 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:30 PM PDT 24
Peak memory 213744 kb
Host smart-e63a5076-2b24-40d3-9119-e21f30b8b106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288513875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2288513875
Directory /workspace/18.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2073365859
Short name T458
Test name
Test status
Simulation time 44619280511 ps
CPU time 44.42 seconds
Started Jul 30 06:35:33 PM PDT 24
Finished Jul 30 06:36:17 PM PDT 24
Peak memory 205620 kb
Host smart-9f85b227-71c2-4bf8-bb03-50b2a945c79e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073365859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2073365859
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2727475153
Short name T317
Test name
Test status
Simulation time 6491695391 ps
CPU time 3.08 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 205640 kb
Host smart-0496d9f8-6539-4fce-a2a2-1d7088f9dff3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727475153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2727475153
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4070878981
Short name T362
Test name
Test status
Simulation time 652583336 ps
CPU time 2.4 seconds
Started Jul 30 06:35:24 PM PDT 24
Finished Jul 30 06:35:27 PM PDT 24
Peak memory 205336 kb
Host smart-7bfa8b9b-45fe-4054-93ea-db42c2e7f381
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070878981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
4070878981
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.966219
Short name T120
Test name
Test status
Simulation time 587092439 ps
CPU time 4.44 seconds
Started Jul 30 06:35:29 PM PDT 24
Finished Jul 30 06:35:33 PM PDT 24
Peak memory 205616 kb
Host smart-1e77041b-8e70-4cd1-9112-19007867d1cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966219 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_csr
_outstanding.966219
Directory /workspace/18.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.1089395506
Short name T366
Test name
Test status
Simulation time 272833058 ps
CPU time 5.26 seconds
Started Jul 30 06:35:32 PM PDT 24
Finished Jul 30 06:35:37 PM PDT 24
Peak memory 213984 kb
Host smart-559685d9-6944-42cf-9e5b-244e2ac3299b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089395506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.1089395506
Directory /workspace/18.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.873826054
Short name T447
Test name
Test status
Simulation time 1493868051 ps
CPU time 8.73 seconds
Started Jul 30 06:35:25 PM PDT 24
Finished Jul 30 06:35:34 PM PDT 24
Peak memory 213896 kb
Host smart-82152778-bae8-493f-98f2-78bfe88c9c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873826054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.873826054
Directory /workspace/18.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.3975276046
Short name T433
Test name
Test status
Simulation time 103400899 ps
CPU time 4.68 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:32 PM PDT 24
Peak memory 219336 kb
Host smart-e52c7977-042a-4ff7-af46-f432cdad2590
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975276046 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.3975276046
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.2977105537
Short name T107
Test name
Test status
Simulation time 100677829 ps
CPU time 2.27 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 213748 kb
Host smart-0d709cdc-d1cd-4753-ad73-0ba0295d0bca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977105537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.2977105537
Directory /workspace/19.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2646567541
Short name T369
Test name
Test status
Simulation time 10668350175 ps
CPU time 9.02 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:36 PM PDT 24
Peak memory 205612 kb
Host smart-1d622298-e090-41dc-8c3a-bc056913c0ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646567541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2646567541
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.3341735229
Short name T414
Test name
Test status
Simulation time 6386341467 ps
CPU time 9.56 seconds
Started Jul 30 06:35:30 PM PDT 24
Finished Jul 30 06:35:39 PM PDT 24
Peak memory 205664 kb
Host smart-beac8939-a2d8-4a74-835c-35678dfb2768
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341735229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
3341735229
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3786795771
Short name T444
Test name
Test status
Simulation time 152470700 ps
CPU time 0.81 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 205404 kb
Host smart-d0f527fe-9441-499f-b994-7c47ae52ef6f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786795771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3786795771
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.920652650
Short name T442
Test name
Test status
Simulation time 476666064 ps
CPU time 3.69 seconds
Started Jul 30 06:35:32 PM PDT 24
Finished Jul 30 06:35:36 PM PDT 24
Peak memory 205620 kb
Host smart-a196bdc1-6b8a-4e6e-a6f9-db3072f704bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920652650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.920652650
Directory /workspace/19.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.992426413
Short name T333
Test name
Test status
Simulation time 226558090 ps
CPU time 3.08 seconds
Started Jul 30 06:35:28 PM PDT 24
Finished Jul 30 06:35:31 PM PDT 24
Peak memory 213928 kb
Host smart-32efdfba-4f89-459a-be5d-2660e1dec64e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992426413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.992426413
Directory /workspace/19.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2544549816
Short name T170
Test name
Test status
Simulation time 4932913165 ps
CPU time 16.85 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:44 PM PDT 24
Peak memory 214124 kb
Host smart-2e7ca68f-85c2-4ee9-bcb2-71b240055dec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544549816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
544549816
Directory /workspace/19.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2757207098
Short name T111
Test name
Test status
Simulation time 9285260541 ps
CPU time 33.77 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:52 PM PDT 24
Peak memory 205728 kb
Host smart-f901b949-862c-41b5-9e28-d341235868ff
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757207098 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2757207098
Directory /workspace/2.rv_dm_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.516317511
Short name T372
Test name
Test status
Simulation time 5032746526 ps
CPU time 35.35 seconds
Started Jul 30 06:35:15 PM PDT 24
Finished Jul 30 06:35:50 PM PDT 24
Peak memory 213944 kb
Host smart-3b99c11f-e850-48da-bfc7-ba808901806b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516317511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.516317511
Directory /workspace/2.rv_dm_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3358770420
Short name T89
Test name
Test status
Simulation time 302111426 ps
CPU time 1.72 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 213808 kb
Host smart-df42a131-f913-45fe-a110-e4d952b8157d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358770420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3358770420
Directory /workspace/2.rv_dm_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1560237070
Short name T133
Test name
Test status
Simulation time 154428366 ps
CPU time 2.97 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 219624 kb
Host smart-73bc0e26-9bb7-4456-9a84-0ef7e8d366ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560237070 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1560237070
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.2955763801
Short name T92
Test name
Test status
Simulation time 99994691 ps
CPU time 1.42 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 213796 kb
Host smart-7cafcd5b-0bfd-4289-81cc-7fb7b31bb1ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955763801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.2955763801
Directory /workspace/2.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1735357390
Short name T461
Test name
Test status
Simulation time 220141982273 ps
CPU time 160.74 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:37:59 PM PDT 24
Peak memory 205684 kb
Host smart-ff013f52-d398-49b3-94a2-a1ee93d8be7f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735357390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1735357390
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3347936696
Short name T404
Test name
Test status
Simulation time 17531101281 ps
CPU time 15.28 seconds
Started Jul 30 06:35:13 PM PDT 24
Finished Jul 30 06:35:29 PM PDT 24
Peak memory 205788 kb
Host smart-670cc697-9b8a-4c2e-9187-cf423f05ccd1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347936696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.3347936696
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2286361911
Short name T95
Test name
Test status
Simulation time 6484908927 ps
CPU time 11.56 seconds
Started Jul 30 06:35:11 PM PDT 24
Finished Jul 30 06:35:22 PM PDT 24
Peak memory 205728 kb
Host smart-c4816662-1774-4314-94b3-c08dcab43393
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286361911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2286361911
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.930137804
Short name T441
Test name
Test status
Simulation time 901027221 ps
CPU time 1.41 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:22 PM PDT 24
Peak memory 205504 kb
Host smart-de192772-417b-489c-87e7-3e2d7565c909
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930137804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.930137804
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4292004295
Short name T357
Test name
Test status
Simulation time 472829428 ps
CPU time 0.98 seconds
Started Jul 30 06:35:13 PM PDT 24
Finished Jul 30 06:35:14 PM PDT 24
Peak memory 205304 kb
Host smart-c7b50d25-165d-44a6-a884-2369386a8077
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292004295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.4292004295
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1533325372
Short name T454
Test name
Test status
Simulation time 3452423424 ps
CPU time 8.18 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:35:24 PM PDT 24
Peak memory 205628 kb
Host smart-57fd1b64-a623-420b-99ff-a7caaef5796a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533325372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1533325372
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2754386417
Short name T415
Test name
Test status
Simulation time 270981652 ps
CPU time 0.91 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 205348 kb
Host smart-91d8e497-13fa-4284-b6e4-22f860d4db19
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754386417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2754386417
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.2842798341
Short name T61
Test name
Test status
Simulation time 241505906 ps
CPU time 0.83 seconds
Started Jul 30 06:35:15 PM PDT 24
Finished Jul 30 06:35:16 PM PDT 24
Peak memory 205324 kb
Host smart-7a3fd1e8-c2b6-46a6-ae94-32a2b3adfdd5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842798341 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.2
842798341
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3322810459
Short name T375
Test name
Test status
Simulation time 104312121 ps
CPU time 0.72 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 205380 kb
Host smart-68243e18-ccac-4b92-93cc-5979f2798a64
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322810459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3322810459
Directory /workspace/2.rv_dm_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2685075454
Short name T374
Test name
Test status
Simulation time 94406173 ps
CPU time 0.8 seconds
Started Jul 30 06:35:24 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 205324 kb
Host smart-52a1ec6f-e7ef-4ee4-9f76-4d8e282f686f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685075454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2685075454
Directory /workspace/2.rv_dm_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.771422411
Short name T416
Test name
Test status
Simulation time 913531979 ps
CPU time 4.03 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 205668 kb
Host smart-471124a4-7495-4878-81d3-8cb938934eda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771422411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.771422411
Directory /workspace/2.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.561405182
Short name T176
Test name
Test status
Simulation time 21415374685 ps
CPU time 64.71 seconds
Started Jul 30 06:35:12 PM PDT 24
Finished Jul 30 06:36:17 PM PDT 24
Peak memory 222268 kb
Host smart-9bce3c77-4db3-4bb0-8936-fa64349ef427
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561405182 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.561405182
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1996107617
Short name T346
Test name
Test status
Simulation time 663278225 ps
CPU time 5.18 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:28 PM PDT 24
Peak memory 214044 kb
Host smart-777ff556-6158-4fe4-9091-c8c13a02182b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996107617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1996107617
Directory /workspace/2.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.1779373445
Short name T397
Test name
Test status
Simulation time 13660859929 ps
CPU time 78.76 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:36:38 PM PDT 24
Peak memory 213980 kb
Host smart-2d10ee1a-206c-4b0c-9d81-2208f207af41
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779373445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.1779373445
Directory /workspace/3.rv_dm_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1373481736
Short name T407
Test name
Test status
Simulation time 36636033822 ps
CPU time 76.96 seconds
Started Jul 30 06:35:15 PM PDT 24
Finished Jul 30 06:36:32 PM PDT 24
Peak memory 213912 kb
Host smart-ecd2f37f-417d-49b7-bb64-cd28511483cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373481736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1373481736
Directory /workspace/3.rv_dm_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3738364428
Short name T100
Test name
Test status
Simulation time 291959088 ps
CPU time 1.6 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 213812 kb
Host smart-195ecad5-70e2-4752-90b8-a639c341558c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738364428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3738364428
Directory /workspace/3.rv_dm_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.844777686
Short name T409
Test name
Test status
Simulation time 573454281 ps
CPU time 2.31 seconds
Started Jul 30 06:35:38 PM PDT 24
Finished Jul 30 06:35:40 PM PDT 24
Peak memory 213952 kb
Host smart-5f419a8a-c651-422e-83eb-2f0768de42ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844777686 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.844777686
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.533717102
Short name T114
Test name
Test status
Simulation time 227748145 ps
CPU time 1.57 seconds
Started Jul 30 06:35:14 PM PDT 24
Finished Jul 30 06:35:15 PM PDT 24
Peak memory 213868 kb
Host smart-6253ab68-7032-406a-acc7-780aa11b26d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533717102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.533717102
Directory /workspace/3.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3797664459
Short name T326
Test name
Test status
Simulation time 54154734590 ps
CPU time 148.08 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:37:50 PM PDT 24
Peak memory 205588 kb
Host smart-05b38415-44fa-49fa-93f7-1d8f0d2e2507
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797664459 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3797664459
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3666430914
Short name T430
Test name
Test status
Simulation time 8304661726 ps
CPU time 13.99 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:32 PM PDT 24
Peak memory 205636 kb
Host smart-6b6b533e-c54c-489e-b02c-23511abde668
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666430914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.3666430914
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.4047441472
Short name T93
Test name
Test status
Simulation time 1443346113 ps
CPU time 4.93 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:27 PM PDT 24
Peak memory 205648 kb
Host smart-7521c15a-8460-42f7-9381-d8c3f8097eb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047441472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.4047441472
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2412875711
Short name T316
Test name
Test status
Simulation time 3556540405 ps
CPU time 10.3 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:33 PM PDT 24
Peak memory 205660 kb
Host smart-cd90d725-5217-43e4-8db1-427979f7ccc4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412875711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
412875711
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.726467021
Short name T443
Test name
Test status
Simulation time 975758687 ps
CPU time 1.64 seconds
Started Jul 30 06:35:17 PM PDT 24
Finished Jul 30 06:35:19 PM PDT 24
Peak memory 205304 kb
Host smart-cc765ab3-b904-4b61-86a0-e7f0070983ff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726467021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.726467021
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3012840212
Short name T364
Test name
Test status
Simulation time 22113134399 ps
CPU time 12.52 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:31 PM PDT 24
Peak memory 205692 kb
Host smart-0f20b8aa-2295-4090-a0c8-a605daa62be5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012840212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3012840212
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2202880479
Short name T345
Test name
Test status
Simulation time 477326713 ps
CPU time 1 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 205384 kb
Host smart-a01d61f1-bb3d-4758-a921-ef0730b8928c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202880479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2202880479
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.2114044343
Short name T356
Test name
Test status
Simulation time 372600592 ps
CPU time 1.02 seconds
Started Jul 30 06:35:23 PM PDT 24
Finished Jul 30 06:35:24 PM PDT 24
Peak memory 205288 kb
Host smart-f171436e-e9f9-46ad-8c88-23575b54841f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114044343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.2
114044343
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2219752396
Short name T319
Test name
Test status
Simulation time 56412502 ps
CPU time 0.76 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:19 PM PDT 24
Peak memory 205384 kb
Host smart-c82fd8bf-bab5-462e-9a23-a6b5aaa2c4dd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219752396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2219752396
Directory /workspace/3.rv_dm_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2303450804
Short name T355
Test name
Test status
Simulation time 39908608 ps
CPU time 0.71 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 205348 kb
Host smart-e9b93834-cc23-46b0-ba84-f78148a2bce5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303450804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2303450804
Directory /workspace/3.rv_dm_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1644779882
Short name T86
Test name
Test status
Simulation time 2473177641 ps
CPU time 6.77 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:29 PM PDT 24
Peak memory 205832 kb
Host smart-f2d57b51-e141-432f-9bea-707afe6cf4b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644779882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1644779882
Directory /workspace/3.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.2348384909
Short name T431
Test name
Test status
Simulation time 71282416001 ps
CPU time 553.53 seconds
Started Jul 30 06:35:25 PM PDT 24
Finished Jul 30 06:44:38 PM PDT 24
Peak memory 230468 kb
Host smart-b3de6b90-136f-4107-8b6f-de4a8e598203
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348384909 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.2348384909
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.99813296
Short name T385
Test name
Test status
Simulation time 167192415 ps
CPU time 2.68 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 216380 kb
Host smart-7bb4ced6-9ab9-4877-9244-2ef740e35917
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99813296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.99813296
Directory /workspace/3.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2299190484
Short name T446
Test name
Test status
Simulation time 1318415891 ps
CPU time 8.2 seconds
Started Jul 30 06:35:17 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 213800 kb
Host smart-c76283d9-b052-4628-ba02-af69e6a6342c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299190484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2299190484
Directory /workspace/3.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2203792304
Short name T98
Test name
Test status
Simulation time 2084413362 ps
CPU time 33.08 seconds
Started Jul 30 06:35:13 PM PDT 24
Finished Jul 30 06:35:47 PM PDT 24
Peak memory 213836 kb
Host smart-4a74a38b-4b4e-4ca0-847b-73e544f4b809
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203792304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2203792304
Directory /workspace/4.rv_dm_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4250044768
Short name T387
Test name
Test status
Simulation time 3080120049 ps
CPU time 28.61 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:56 PM PDT 24
Peak memory 205696 kb
Host smart-9b70c54e-7463-4fc0-b5d4-fa80d3910e1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250044768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.4250044768
Directory /workspace/4.rv_dm_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.153462786
Short name T420
Test name
Test status
Simulation time 148683888 ps
CPU time 2.63 seconds
Started Jul 30 06:35:11 PM PDT 24
Finished Jul 30 06:35:14 PM PDT 24
Peak memory 213912 kb
Host smart-2c785d17-4ce1-47d8-ae11-23c66210f776
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153462786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.153462786
Directory /workspace/4.rv_dm_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.2277035062
Short name T341
Test name
Test status
Simulation time 413451813 ps
CPU time 2.9 seconds
Started Jul 30 06:35:26 PM PDT 24
Finished Jul 30 06:35:29 PM PDT 24
Peak memory 218656 kb
Host smart-b1264652-50cf-49b1-838f-49074a9693a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277035062 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.2277035062
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.2274675686
Short name T110
Test name
Test status
Simulation time 122328582 ps
CPU time 1.56 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 213768 kb
Host smart-8288eb0d-2beb-47a6-b301-39260be9bce5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274675686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.2274675686
Directory /workspace/4.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2594463086
Short name T379
Test name
Test status
Simulation time 76099608858 ps
CPU time 98.52 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:36:58 PM PDT 24
Peak memory 205720 kb
Host smart-e3d20154-2594-4864-95d9-293d85ec951a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594463086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2594463086
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2763251065
Short name T321
Test name
Test status
Simulation time 5560421239 ps
CPU time 14.7 seconds
Started Jul 30 06:35:23 PM PDT 24
Finished Jul 30 06:35:38 PM PDT 24
Peak memory 205572 kb
Host smart-2172ec62-3d00-40a2-9c6a-422a4bcd8164
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763251065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.2763251065
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.4267189625
Short name T94
Test name
Test status
Simulation time 15918042414 ps
CPU time 39.95 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:58 PM PDT 24
Peak memory 205716 kb
Host smart-a098da87-9fe6-4138-9507-34f4fb731559
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267189625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.4267189625
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.228081475
Short name T352
Test name
Test status
Simulation time 3371587339 ps
CPU time 2.7 seconds
Started Jul 30 06:35:27 PM PDT 24
Finished Jul 30 06:35:30 PM PDT 24
Peak memory 205668 kb
Host smart-ea1e4b36-e04b-4b87-8e45-aa9d8e02bdf6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228081475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.228081475
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.4043739810
Short name T392
Test name
Test status
Simulation time 2224019303 ps
CPU time 2.27 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:24 PM PDT 24
Peak memory 205388 kb
Host smart-6862fb32-24f3-4677-9be3-cc124f93389c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043739810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.4043739810
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2061198311
Short name T367
Test name
Test status
Simulation time 17635444402 ps
CPU time 15.27 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:37 PM PDT 24
Peak memory 205616 kb
Host smart-7e983ba8-1d4c-44f1-8a10-156188a298c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061198311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2061198311
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.174204353
Short name T62
Test name
Test status
Simulation time 122752072 ps
CPU time 1 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 205356 kb
Host smart-11c8a214-d24d-4364-ae88-2d0de111352b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174204353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_hw_reset.174204353
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2493388544
Short name T419
Test name
Test status
Simulation time 564263224 ps
CPU time 1.11 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 205284 kb
Host smart-b50fd199-d9cf-4cbe-8e60-1e8300f63224
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493388544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
493388544
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.3509635753
Short name T315
Test name
Test status
Simulation time 110116023 ps
CPU time 0.78 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 205364 kb
Host smart-c9b50949-2465-42ff-ac91-493706f80819
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509635753 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.3509635753
Directory /workspace/4.rv_dm_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.988778843
Short name T423
Test name
Test status
Simulation time 50311814 ps
CPU time 0.76 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:22 PM PDT 24
Peak memory 205296 kb
Host smart-5f5ef643-6d5c-47e0-bb04-b4c4a6488e5c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988778843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.988778843
Directory /workspace/4.rv_dm_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.543075935
Short name T104
Test name
Test status
Simulation time 1950269221 ps
CPU time 7.88 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:30 PM PDT 24
Peak memory 205608 kb
Host smart-4c5bdb66-ebbf-4a7e-8d08-8a585b51e5f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543075935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.543075935
Directory /workspace/4.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.3508047710
Short name T58
Test name
Test status
Simulation time 23877010372 ps
CPU time 72.68 seconds
Started Jul 30 06:35:11 PM PDT 24
Finished Jul 30 06:36:24 PM PDT 24
Peak memory 220756 kb
Host smart-d5eff349-6386-4428-ae00-21edddcec574
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508047710 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.3508047710
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2190457110
Short name T331
Test name
Test status
Simulation time 105677868 ps
CPU time 1.81 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 213932 kb
Host smart-0b0c7724-36cc-46f3-89ef-809ea8c78cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190457110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2190457110
Directory /workspace/4.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3168770134
Short name T466
Test name
Test status
Simulation time 1414716850 ps
CPU time 10.78 seconds
Started Jul 30 06:35:25 PM PDT 24
Finished Jul 30 06:35:36 PM PDT 24
Peak memory 213888 kb
Host smart-7ecdf734-66aa-4f5d-8ca1-57c3655feb40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168770134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3168770134
Directory /workspace/4.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3430555137
Short name T320
Test name
Test status
Simulation time 974098836 ps
CPU time 4.33 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 222152 kb
Host smart-19b15480-29c6-494a-82c1-de0f0940d7b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430555137 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3430555137
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3544316901
Short name T390
Test name
Test status
Simulation time 914996410 ps
CPU time 1.79 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:35:18 PM PDT 24
Peak memory 213888 kb
Host smart-70181aec-69f4-4e63-89ba-25fdd261b627
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544316901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3544316901
Directory /workspace/5.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.897930682
Short name T314
Test name
Test status
Simulation time 35840941625 ps
CPU time 47.92 seconds
Started Jul 30 06:35:24 PM PDT 24
Finished Jul 30 06:36:12 PM PDT 24
Peak memory 205680 kb
Host smart-e860542b-fe67-41ac-bbd8-6a2f8a631dbd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897930682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.r
v_dm_jtag_dmi_csr_bit_bash.897930682
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1561257662
Short name T327
Test name
Test status
Simulation time 2603307853 ps
CPU time 7.67 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:30 PM PDT 24
Peak memory 205588 kb
Host smart-e62f8ae8-0227-447c-9b4f-ac8957db9d55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561257662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
561257662
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.228415502
Short name T445
Test name
Test status
Simulation time 267339712 ps
CPU time 1.12 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 204976 kb
Host smart-3d28c694-7087-4cdf-9e3b-b16b005b3454
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228415502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.228415502
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.951465748
Short name T87
Test name
Test status
Simulation time 843061669 ps
CPU time 6.29 seconds
Started Jul 30 06:35:23 PM PDT 24
Finished Jul 30 06:35:29 PM PDT 24
Peak memory 205660 kb
Host smart-57ce985f-7a89-4bd0-82f5-dadc4dadfe66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951465748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.951465748
Directory /workspace/5.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2131271721
Short name T174
Test name
Test status
Simulation time 30553113783 ps
CPU time 18.59 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:39 PM PDT 24
Peak memory 220504 kb
Host smart-a9ecc289-d177-40c2-b0b4-e9c9eb088294
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131271721 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2131271721
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.385754196
Short name T354
Test name
Test status
Simulation time 132199300 ps
CPU time 3.24 seconds
Started Jul 30 06:35:15 PM PDT 24
Finished Jul 30 06:35:18 PM PDT 24
Peak memory 213896 kb
Host smart-f5c846c4-e0ea-4d68-b8a4-ad1b30e3bdff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385754196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.385754196
Directory /workspace/5.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.3130878618
Short name T348
Test name
Test status
Simulation time 229996158 ps
CPU time 2.81 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 213916 kb
Host smart-1789d4d0-f89a-445d-aa63-7ec74c40416f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130878618 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.3130878618
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.3473995261
Short name T99
Test name
Test status
Simulation time 479250658 ps
CPU time 2.48 seconds
Started Jul 30 06:35:17 PM PDT 24
Finished Jul 30 06:35:19 PM PDT 24
Peak memory 213908 kb
Host smart-ba175975-53fa-4859-9b29-003d3a2d2f7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473995261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.3473995261
Directory /workspace/6.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.1414461392
Short name T448
Test name
Test status
Simulation time 96524753723 ps
CPU time 73.16 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:36:34 PM PDT 24
Peak memory 205628 kb
Host smart-4d2802a2-4fb4-4c9a-9d70-14e6d48e52ff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414461392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.1414461392
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1102219197
Short name T400
Test name
Test status
Simulation time 3964303387 ps
CPU time 4.39 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 205656 kb
Host smart-f86dfca5-bd63-4061-ad5b-623929e75bb5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102219197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
102219197
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1787130600
Short name T365
Test name
Test status
Simulation time 305361750 ps
CPU time 0.87 seconds
Started Jul 30 06:35:17 PM PDT 24
Finished Jul 30 06:35:18 PM PDT 24
Peak memory 205356 kb
Host smart-065c1e0c-a28a-49a2-9c69-f862e8498cbf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787130600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
787130600
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2148803589
Short name T449
Test name
Test status
Simulation time 590477309 ps
CPU time 7.75 seconds
Started Jul 30 06:35:26 PM PDT 24
Finished Jul 30 06:35:34 PM PDT 24
Peak memory 205636 kb
Host smart-63838689-20fe-430e-8eee-acc1230ffa91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148803589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2148803589
Directory /workspace/6.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.4230878540
Short name T453
Test name
Test status
Simulation time 88793451 ps
CPU time 2.86 seconds
Started Jul 30 06:35:17 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 213976 kb
Host smart-0451ee26-c7a1-40ce-91cd-c208d6fcdea3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230878540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.4230878540
Directory /workspace/6.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3878392287
Short name T162
Test name
Test status
Simulation time 2268511046 ps
CPU time 10.72 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:32 PM PDT 24
Peak memory 213960 kb
Host smart-46d474b8-232b-472d-a80a-94d9deeab00c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878392287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3878392287
Directory /workspace/6.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3700763163
Short name T406
Test name
Test status
Simulation time 178896219 ps
CPU time 3.54 seconds
Started Jul 30 06:35:25 PM PDT 24
Finished Jul 30 06:35:28 PM PDT 24
Peak memory 221816 kb
Host smart-d5912459-820d-4c78-82b6-3b4e27ced910
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700763163 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3700763163
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2544073008
Short name T426
Test name
Test status
Simulation time 94774578 ps
CPU time 1.57 seconds
Started Jul 30 06:35:24 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 213784 kb
Host smart-5ccb7ada-0502-49b8-81e1-4a12852da3a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544073008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2544073008
Directory /workspace/7.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.1343572936
Short name T339
Test name
Test status
Simulation time 155527449 ps
CPU time 0.69 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 205320 kb
Host smart-56eae67b-7a19-4c28-bf2b-6682982543d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343572936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.1343572936
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.1690772153
Short name T421
Test name
Test status
Simulation time 2515389461 ps
CPU time 4.18 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 205608 kb
Host smart-a071e2e2-ea89-4402-963c-2e125d8259f9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690772153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.1
690772153
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2824560794
Short name T386
Test name
Test status
Simulation time 909161205 ps
CPU time 2.81 seconds
Started Jul 30 06:35:18 PM PDT 24
Finished Jul 30 06:35:22 PM PDT 24
Peak memory 205300 kb
Host smart-417bc588-b556-443b-98ec-7abf723b358b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824560794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
824560794
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.922715056
Short name T90
Test name
Test status
Simulation time 638681989 ps
CPU time 7.79 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:28 PM PDT 24
Peak memory 205664 kb
Host smart-beb4b92d-af84-4b0d-9922-0c72485d79e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922715056 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.922715056
Directory /workspace/7.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1762915797
Short name T335
Test name
Test status
Simulation time 299004849 ps
CPU time 3.46 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:24 PM PDT 24
Peak memory 213848 kb
Host smart-ea489458-5aea-43c9-b2d4-2fd617606f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762915797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1762915797
Directory /workspace/7.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2456904144
Short name T167
Test name
Test status
Simulation time 3292829282 ps
CPU time 17.09 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:39 PM PDT 24
Peak memory 214052 kb
Host smart-8166a214-e554-486b-806c-eea55ada0243
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456904144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2456904144
Directory /workspace/7.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2434462295
Short name T371
Test name
Test status
Simulation time 330267859 ps
CPU time 2.42 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:21 PM PDT 24
Peak memory 219180 kb
Host smart-5d5f0aed-c263-4d72-a5d2-dc887b914b43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434462295 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2434462295
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.374366602
Short name T88
Test name
Test status
Simulation time 115374369 ps
CPU time 1.59 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:22 PM PDT 24
Peak memory 213792 kb
Host smart-ec8e627d-5c4e-400b-a199-765e836e86d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374366602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.374366602
Directory /workspace/8.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1148890396
Short name T380
Test name
Test status
Simulation time 18424936870 ps
CPU time 51.2 seconds
Started Jul 30 06:35:24 PM PDT 24
Finished Jul 30 06:36:15 PM PDT 24
Peak memory 205596 kb
Host smart-aed591b7-0b1d-440e-ae88-905bb24ccb62
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148890396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.1148890396
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.296326181
Short name T389
Test name
Test status
Simulation time 1535704062 ps
CPU time 1.19 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 205520 kb
Host smart-df1daf0e-61e6-465a-8dc2-edd52f6b2143
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296326181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.296326181
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2795069661
Short name T342
Test name
Test status
Simulation time 629658353 ps
CPU time 2.17 seconds
Started Jul 30 06:35:14 PM PDT 24
Finished Jul 30 06:35:16 PM PDT 24
Peak memory 205292 kb
Host smart-b481a5c2-1dda-49ae-8cbc-b46c48ed2ff5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795069661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
795069661
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1847309201
Short name T91
Test name
Test status
Simulation time 2071036995 ps
CPU time 8.07 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:35:30 PM PDT 24
Peak memory 205656 kb
Host smart-3debbafd-7e50-48c5-b79c-a705344c559d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847309201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1847309201
Directory /workspace/8.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4219065384
Short name T465
Test name
Test status
Simulation time 49978282712 ps
CPU time 39.73 seconds
Started Jul 30 06:35:25 PM PDT 24
Finished Jul 30 06:36:05 PM PDT 24
Peak memory 222152 kb
Host smart-2d6c49f5-58c6-485a-942e-7a8dacebb714
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219065384 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.4219065384
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.700366502
Short name T422
Test name
Test status
Simulation time 239486173 ps
CPU time 2.77 seconds
Started Jul 30 06:35:17 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 213876 kb
Host smart-efdca140-6def-477e-8aef-17ed60b985a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700366502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.700366502
Directory /workspace/8.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2365892279
Short name T172
Test name
Test status
Simulation time 2506417156 ps
CPU time 25.39 seconds
Started Jul 30 06:35:25 PM PDT 24
Finished Jul 30 06:35:50 PM PDT 24
Peak memory 213964 kb
Host smart-d57429cb-80f4-4ae7-b3f2-8c077f8cd3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365892279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2365892279
Directory /workspace/8.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3760276007
Short name T334
Test name
Test status
Simulation time 345233721 ps
CPU time 3.73 seconds
Started Jul 30 06:35:22 PM PDT 24
Finished Jul 30 06:35:26 PM PDT 24
Peak memory 219256 kb
Host smart-f125db0b-101e-41c7-8e5a-8d4c81ccfcbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760276007 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3760276007
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1095156796
Short name T376
Test name
Test status
Simulation time 283191404 ps
CPU time 1.53 seconds
Started Jul 30 06:35:19 PM PDT 24
Finished Jul 30 06:35:20 PM PDT 24
Peak memory 213756 kb
Host smart-4337253a-1eba-417f-adb2-6f9f3d15b73f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095156796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1095156796
Directory /workspace/9.rv_dm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.1403088472
Short name T332
Test name
Test status
Simulation time 5485773352 ps
CPU time 3.88 seconds
Started Jul 30 06:35:23 PM PDT 24
Finished Jul 30 06:35:27 PM PDT 24
Peak memory 205580 kb
Host smart-ccec03af-61a4-4a58-b6dd-4971fb3843ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403088472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.1403088472
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1019201904
Short name T318
Test name
Test status
Simulation time 5478773266 ps
CPU time 5.67 seconds
Started Jul 30 06:35:24 PM PDT 24
Finished Jul 30 06:35:30 PM PDT 24
Peak memory 205636 kb
Host smart-468c4067-fe93-4976-a102-fd44132fb72b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019201904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
019201904
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3511844761
Short name T60
Test name
Test status
Simulation time 548847255 ps
CPU time 2.15 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:35:18 PM PDT 24
Peak memory 205348 kb
Host smart-4df15a3b-7bae-40e0-8ca1-ba02a3e868cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511844761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
511844761
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1727971721
Short name T103
Test name
Test status
Simulation time 110190338 ps
CPU time 3.58 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:24 PM PDT 24
Peak memory 205612 kb
Host smart-75cde8b5-eb5c-4845-a287-8a6eb82b9348
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727971721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1727971721
Directory /workspace/9.rv_dm_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.298773953
Short name T175
Test name
Test status
Simulation time 60354751477 ps
CPU time 210.89 seconds
Started Jul 30 06:35:21 PM PDT 24
Finished Jul 30 06:38:52 PM PDT 24
Peak memory 222240 kb
Host smart-2f162888-f46f-490a-8543-863480dbc899
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298773953 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.298773953
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.859874034
Short name T434
Test name
Test status
Simulation time 634826399 ps
CPU time 3.65 seconds
Started Jul 30 06:35:20 PM PDT 24
Finished Jul 30 06:35:23 PM PDT 24
Peak memory 213876 kb
Host smart-5eeb9589-d302-40b2-8305-f76bb31bfc7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859874034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.859874034
Directory /workspace/9.rv_dm_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1834632263
Short name T462
Test name
Test status
Simulation time 494537692 ps
CPU time 9.01 seconds
Started Jul 30 06:35:16 PM PDT 24
Finished Jul 30 06:35:25 PM PDT 24
Peak memory 213880 kb
Host smart-51699780-34fc-4f28-8f2c-02fe69634ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834632263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1834632263
Directory /workspace/9.rv_dm_tl_intg_err/latest


Test location /workspace/coverage/default/0.rv_dm_alert_test.1692288146
Short name T278
Test name
Test status
Simulation time 87108809 ps
CPU time 0.94 seconds
Started Jul 30 05:15:34 PM PDT 24
Finished Jul 30 05:15:35 PM PDT 24
Peak memory 205164 kb
Host smart-14ef8b3f-319f-48d5-a978-4cdf6186b705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692288146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1692288146
Directory /workspace/0.rv_dm_alert_test/latest


Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3886232993
Short name T248
Test name
Test status
Simulation time 1780310169 ps
CPU time 2.57 seconds
Started Jul 30 05:15:22 PM PDT 24
Finished Jul 30 05:15:25 PM PDT 24
Peak memory 213860 kb
Host smart-08dbe175-7dfc-4b3d-b721-e4385a8d32b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886232993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3886232993
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1910531679
Short name T260
Test name
Test status
Simulation time 259956459 ps
CPU time 1.14 seconds
Started Jul 30 05:15:23 PM PDT 24
Finished Jul 30 05:15:24 PM PDT 24
Peak memory 205300 kb
Host smart-41fa430a-ed18-473c-864a-460214bd74ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910531679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1910531679
Directory /workspace/0.rv_dm_cmderr_busy/latest


Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2521211685
Short name T286
Test name
Test status
Simulation time 454822643 ps
CPU time 0.8 seconds
Started Jul 30 05:15:27 PM PDT 24
Finished Jul 30 05:15:28 PM PDT 24
Peak memory 205324 kb
Host smart-d32ceda6-32ea-400e-9fb9-e9a765124983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521211685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2521211685
Directory /workspace/0.rv_dm_cmderr_not_supported/latest


Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3629152922
Short name T55
Test name
Test status
Simulation time 287686134 ps
CPU time 0.87 seconds
Started Jul 30 05:15:26 PM PDT 24
Finished Jul 30 05:15:27 PM PDT 24
Peak memory 205264 kb
Host smart-3dbdab2a-e024-4d0a-a695-1631af09fb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629152922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3629152922
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest


Test location /workspace/coverage/default/0.rv_dm_debug_disabled.3826456883
Short name T275
Test name
Test status
Simulation time 111659512 ps
CPU time 1.06 seconds
Started Jul 30 05:15:31 PM PDT 24
Finished Jul 30 05:15:33 PM PDT 24
Peak memory 215552 kb
Host smart-7a893623-644c-42d1-a8eb-8bffc4600966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826456883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3826456883
Directory /workspace/0.rv_dm_debug_disabled/latest


Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3728892543
Short name T190
Test name
Test status
Simulation time 3580240743 ps
CPU time 6.22 seconds
Started Jul 30 05:15:27 PM PDT 24
Finished Jul 30 05:15:33 PM PDT 24
Peak memory 213980 kb
Host smart-6dbccf44-725e-49a6-9375-14bbafe948e6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728892543 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3728892543
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2581564623
Short name T238
Test name
Test status
Simulation time 600360074 ps
CPU time 1.03 seconds
Started Jul 30 05:15:32 PM PDT 24
Finished Jul 30 05:15:33 PM PDT 24
Peak memory 205172 kb
Host smart-632f69b4-85ec-4893-952b-31c6b0b1a0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581564623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2581564623
Directory /workspace/0.rv_dm_halt_resume_whereto/latest


Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1572257021
Short name T79
Test name
Test status
Simulation time 1291441397 ps
CPU time 1.22 seconds
Started Jul 30 05:15:27 PM PDT 24
Finished Jul 30 05:15:28 PM PDT 24
Peak memory 205284 kb
Host smart-ea67e6ea-df43-434d-b03b-5d56476f732b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572257021 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1572257021
Directory /workspace/0.rv_dm_hart_unavail/latest


Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2863931191
Short name T204
Test name
Test status
Simulation time 147485973 ps
CPU time 0.79 seconds
Started Jul 30 05:15:28 PM PDT 24
Finished Jul 30 05:15:29 PM PDT 24
Peak memory 205276 kb
Host smart-bece97ca-7f07-417a-9dfe-60eda9528755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863931191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2863931191
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest


Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1807051622
Short name T292
Test name
Test status
Simulation time 302064760 ps
CPU time 1.39 seconds
Started Jul 30 05:15:29 PM PDT 24
Finished Jul 30 05:15:30 PM PDT 24
Peak memory 205144 kb
Host smart-f67228e3-c251-4d16-befb-3fd6f0c4c380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807051622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1807051622
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest


Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3468222374
Short name T28
Test name
Test status
Simulation time 168652283 ps
CPU time 0.91 seconds
Started Jul 30 05:15:27 PM PDT 24
Finished Jul 30 05:15:28 PM PDT 24
Peak memory 205256 kb
Host smart-5b008ead-00da-4ac5-9df1-153b678ba2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468222374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3468222374
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest


Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3432274781
Short name T310
Test name
Test status
Simulation time 156382995 ps
CPU time 0.87 seconds
Started Jul 30 05:15:29 PM PDT 24
Finished Jul 30 05:15:30 PM PDT 24
Peak memory 205268 kb
Host smart-c4d077f6-5729-4735-a56b-2ff123c569a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432274781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3432274781
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest


Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3562672210
Short name T280
Test name
Test status
Simulation time 217560077 ps
CPU time 1.25 seconds
Started Jul 30 05:15:28 PM PDT 24
Finished Jul 30 05:15:29 PM PDT 24
Peak memory 205292 kb
Host smart-f8cc385e-20c7-4b57-bd91-9c485269f904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562672210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3562672210
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest


Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.526584227
Short name T212
Test name
Test status
Simulation time 1507526129 ps
CPU time 4.62 seconds
Started Jul 30 05:15:27 PM PDT 24
Finished Jul 30 05:15:32 PM PDT 24
Peak memory 205516 kb
Host smart-af2b9a17-16ab-4f95-a07b-4dfbb26de36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526584227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.526584227
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest


Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.1899877559
Short name T223
Test name
Test status
Simulation time 106318590 ps
CPU time 1 seconds
Started Jul 30 05:15:27 PM PDT 24
Finished Jul 30 05:15:28 PM PDT 24
Peak memory 213444 kb
Host smart-2a5913c4-4caf-464e-a640-40eb1869a803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899877559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.1899877559
Directory /workspace/0.rv_dm_ndmreset_req/latest


Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.215363294
Short name T42
Test name
Test status
Simulation time 272285959 ps
CPU time 1.01 seconds
Started Jul 30 05:15:28 PM PDT 24
Finished Jul 30 05:15:29 PM PDT 24
Peak memory 205240 kb
Host smart-94e7a1c8-bf52-4bdc-9412-c1a0ce7a0d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215363294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.215363294
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest


Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.3594338255
Short name T71
Test name
Test status
Simulation time 872028692 ps
CPU time 1.37 seconds
Started Jul 30 05:15:27 PM PDT 24
Finished Jul 30 05:15:28 PM PDT 24
Peak memory 205508 kb
Host smart-acf45a79-0b22-4357-aef2-90f2f149ad7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594338255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.3594338255
Directory /workspace/0.rv_dm_sba_debug_disabled/latest


Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2052016347
Short name T37
Test name
Test status
Simulation time 3749804904 ps
CPU time 12.02 seconds
Started Jul 30 05:15:22 PM PDT 24
Finished Jul 30 05:15:34 PM PDT 24
Peak memory 205760 kb
Host smart-03482ff2-8b09-4284-b3ad-005352155b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052016347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2052016347
Directory /workspace/0.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/0.rv_dm_sec_cm.465510471
Short name T63
Test name
Test status
Simulation time 490651192 ps
CPU time 1.5 seconds
Started Jul 30 05:15:29 PM PDT 24
Finished Jul 30 05:15:30 PM PDT 24
Peak memory 229864 kb
Host smart-1e595e23-ff1b-425e-940c-c7822e811df6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465510471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.465510471
Directory /workspace/0.rv_dm_sec_cm/latest


Test location /workspace/coverage/default/0.rv_dm_smoke.3660190317
Short name T267
Test name
Test status
Simulation time 4013082212 ps
CPU time 3.17 seconds
Started Jul 30 05:15:21 PM PDT 24
Finished Jul 30 05:15:24 PM PDT 24
Peak memory 205588 kb
Host smart-ae364e11-1d3d-4358-a974-3ca81584df30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660190317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3660190317
Directory /workspace/0.rv_dm_smoke/latest


Test location /workspace/coverage/default/0.rv_dm_stress_all.1307592846
Short name T256
Test name
Test status
Simulation time 5997541191 ps
CPU time 17.47 seconds
Started Jul 30 05:15:33 PM PDT 24
Finished Jul 30 05:15:50 PM PDT 24
Peak memory 205600 kb
Host smart-a7865a4b-ebef-45b5-acd6-44dd3b8b40a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307592846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.1307592846
Directory /workspace/0.rv_dm_stress_all/latest


Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.662806423
Short name T78
Test name
Test status
Simulation time 290078485817 ps
CPU time 572.57 seconds
Started Jul 30 05:15:31 PM PDT 24
Finished Jul 30 05:25:03 PM PDT 24
Peak memory 234616 kb
Host smart-51acea15-95c9-4980-be26-a79157a63034
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662806423 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.662806423
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3960624146
Short name T56
Test name
Test status
Simulation time 6715855433 ps
CPU time 17.86 seconds
Started Jul 30 05:15:24 PM PDT 24
Finished Jul 30 05:15:42 PM PDT 24
Peak memory 205488 kb
Host smart-6bffe47a-9382-4807-9842-3ed7992d447a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960624146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3960624146
Directory /workspace/0.rv_dm_tap_fsm/latest


Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3432569044
Short name T43
Test name
Test status
Simulation time 168601803 ps
CPU time 0.93 seconds
Started Jul 30 05:15:41 PM PDT 24
Finished Jul 30 05:15:42 PM PDT 24
Peak memory 205272 kb
Host smart-b0ba71ae-179f-4bc5-bed8-4d43c154b759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432569044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3432569044
Directory /workspace/1.rv_dm_abstractcmd_status/latest


Test location /workspace/coverage/default/1.rv_dm_alert_test.4059450936
Short name T128
Test name
Test status
Simulation time 38090979 ps
CPU time 0.72 seconds
Started Jul 30 05:15:39 PM PDT 24
Finished Jul 30 05:15:40 PM PDT 24
Peak memory 205256 kb
Host smart-bed90944-7fe0-45cb-82b1-bc7e5123979b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059450936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.4059450936
Directory /workspace/1.rv_dm_alert_test/latest


Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1004576452
Short name T50
Test name
Test status
Simulation time 2905536417 ps
CPU time 4.86 seconds
Started Jul 30 05:15:34 PM PDT 24
Finished Jul 30 05:15:39 PM PDT 24
Peak memory 214656 kb
Host smart-8762a0fa-bbcb-45ab-a46d-f14c82eecb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004576452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1004576452
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.3047928912
Short name T277
Test name
Test status
Simulation time 2159929647 ps
CPU time 6.05 seconds
Started Jul 30 05:15:32 PM PDT 24
Finished Jul 30 05:15:38 PM PDT 24
Peak memory 205720 kb
Host smart-5fe473d7-08f6-4910-821e-82faad42c25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047928912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3047928912
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1262985835
Short name T288
Test name
Test status
Simulation time 385302809 ps
CPU time 0.86 seconds
Started Jul 30 05:15:32 PM PDT 24
Finished Jul 30 05:15:33 PM PDT 24
Peak memory 205256 kb
Host smart-36ca510d-294b-4a91-adda-2f45b0cf6efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262985835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1262985835
Directory /workspace/1.rv_dm_cmderr_busy/latest


Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2378669210
Short name T17
Test name
Test status
Simulation time 190549191 ps
CPU time 1.14 seconds
Started Jul 30 05:15:32 PM PDT 24
Finished Jul 30 05:15:33 PM PDT 24
Peak memory 205224 kb
Host smart-4c523de8-983a-4adf-b347-969641dc6b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378669210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2378669210
Directory /workspace/1.rv_dm_cmderr_exception/latest


Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2882968740
Short name T33
Test name
Test status
Simulation time 990382646 ps
CPU time 1.55 seconds
Started Jul 30 05:15:40 PM PDT 24
Finished Jul 30 05:15:41 PM PDT 24
Peak memory 205284 kb
Host smart-2d1dc947-208b-4ba8-b86c-36134b56ba40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882968740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2882968740
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest


Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.709567707
Short name T177
Test name
Test status
Simulation time 450648760 ps
CPU time 1.76 seconds
Started Jul 30 05:15:32 PM PDT 24
Finished Jul 30 05:15:34 PM PDT 24
Peak memory 205280 kb
Host smart-1d8066d2-d569-4072-aa6f-0e3068d386e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709567707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.709567707
Directory /workspace/1.rv_dm_cmderr_not_supported/latest


Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.323169801
Short name T179
Test name
Test status
Simulation time 142630266 ps
CPU time 0.71 seconds
Started Jul 30 05:15:38 PM PDT 24
Finished Jul 30 05:15:39 PM PDT 24
Peak memory 205304 kb
Host smart-0adf5a68-d86f-43a7-9545-17c02ac71d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323169801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.323169801
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest


Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2772093460
Short name T80
Test name
Test status
Simulation time 3406564402 ps
CPU time 4.88 seconds
Started Jul 30 05:15:30 PM PDT 24
Finished Jul 30 05:15:35 PM PDT 24
Peak memory 213916 kb
Host smart-88ce93b9-6091-48cd-956e-71b315ae5549
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772093460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2772093460
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.3240635555
Short name T52
Test name
Test status
Simulation time 229614108 ps
CPU time 0.75 seconds
Started Jul 30 05:15:37 PM PDT 24
Finished Jul 30 05:15:38 PM PDT 24
Peak memory 205252 kb
Host smart-8f34c8af-e39d-4d3b-add5-f00f8d19431f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240635555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3240635555
Directory /workspace/1.rv_dm_dmi_failed_op/latest


Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2122088945
Short name T38
Test name
Test status
Simulation time 1110400898 ps
CPU time 2.26 seconds
Started Jul 30 05:15:40 PM PDT 24
Finished Jul 30 05:15:42 PM PDT 24
Peak memory 205284 kb
Host smart-e491b947-caaf-402b-8157-6a3e11e97e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122088945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2122088945
Directory /workspace/1.rv_dm_halt_resume_whereto/latest


Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3916072069
Short name T265
Test name
Test status
Simulation time 870042754 ps
CPU time 1.01 seconds
Started Jul 30 05:15:33 PM PDT 24
Finished Jul 30 05:15:34 PM PDT 24
Peak memory 205188 kb
Host smart-c7d56481-8ce8-4536-8aad-d040b52f4a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916072069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3916072069
Directory /workspace/1.rv_dm_hart_unavail/latest


Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.598339489
Short name T225
Test name
Test status
Simulation time 146386628 ps
CPU time 0.83 seconds
Started Jul 30 05:15:36 PM PDT 24
Finished Jul 30 05:15:37 PM PDT 24
Peak memory 205188 kb
Host smart-2cf98a8d-0128-407d-8456-cc8fd8b01a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598339489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.598339489
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest


Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1449910854
Short name T202
Test name
Test status
Simulation time 350933299 ps
CPU time 1.04 seconds
Started Jul 30 05:15:42 PM PDT 24
Finished Jul 30 05:15:43 PM PDT 24
Peak memory 205144 kb
Host smart-3489ddf3-a4e8-46d7-81ab-cb7b64b8c4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449910854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1449910854
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest


Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.154517596
Short name T197
Test name
Test status
Simulation time 760648089 ps
CPU time 1.28 seconds
Started Jul 30 05:15:38 PM PDT 24
Finished Jul 30 05:15:39 PM PDT 24
Peak memory 205264 kb
Host smart-a9ba41ef-da47-4b54-a992-a453b9e8b2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154517596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.154517596
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest


Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.3349244703
Short name T308
Test name
Test status
Simulation time 440721724 ps
CPU time 1.97 seconds
Started Jul 30 05:15:33 PM PDT 24
Finished Jul 30 05:15:35 PM PDT 24
Peak memory 205276 kb
Host smart-9735d364-5144-491e-bdd7-eb10debe1a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349244703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.3349244703
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest


Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.3771058874
Short name T285
Test name
Test status
Simulation time 913645072 ps
CPU time 2.95 seconds
Started Jul 30 05:15:32 PM PDT 24
Finished Jul 30 05:15:35 PM PDT 24
Peak memory 205272 kb
Host smart-41a47a70-9131-4c25-a0e4-fddebec4bf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771058874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.3771058874
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest


Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.1069947538
Short name T216
Test name
Test status
Simulation time 809571024 ps
CPU time 0.99 seconds
Started Jul 30 05:15:36 PM PDT 24
Finished Jul 30 05:15:38 PM PDT 24
Peak memory 213408 kb
Host smart-ae4d18fa-a180-4f14-a90e-5456e3f76f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069947538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1069947538
Directory /workspace/1.rv_dm_ndmreset_req/latest


Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.1878355868
Short name T231
Test name
Test status
Simulation time 195916631 ps
CPU time 1.24 seconds
Started Jul 30 05:15:38 PM PDT 24
Finished Jul 30 05:15:39 PM PDT 24
Peak memory 205256 kb
Host smart-8c4df1ad-c196-4ee4-b478-644d4fdd706c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878355868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.1878355868
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest


Test location /workspace/coverage/default/1.rv_dm_rom_read_access.166875993
Short name T35
Test name
Test status
Simulation time 74651937 ps
CPU time 0.93 seconds
Started Jul 30 05:15:37 PM PDT 24
Finished Jul 30 05:15:38 PM PDT 24
Peak memory 213408 kb
Host smart-ee8757a3-4e2b-4a02-b35c-d09c6751e6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166875993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.166875993
Directory /workspace/1.rv_dm_rom_read_access/latest


Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3959605724
Short name T272
Test name
Test status
Simulation time 3577251218 ps
CPU time 3.27 seconds
Started Jul 30 05:15:32 PM PDT 24
Finished Jul 30 05:15:35 PM PDT 24
Peak memory 205808 kb
Host smart-aa528592-725d-4e5c-8e30-df972e72fd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959605724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3959605724
Directory /workspace/1.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/1.rv_dm_sec_cm.3991819992
Short name T49
Test name
Test status
Simulation time 568233732 ps
CPU time 2.42 seconds
Started Jul 30 05:15:42 PM PDT 24
Finished Jul 30 05:15:44 PM PDT 24
Peak memory 228964 kb
Host smart-0fd59af3-bdc9-40af-8823-db1d49ee172d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991819992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3991819992
Directory /workspace/1.rv_dm_sec_cm/latest


Test location /workspace/coverage/default/1.rv_dm_smoke.3218253289
Short name T156
Test name
Test status
Simulation time 840961191 ps
CPU time 2.2 seconds
Started Jul 30 05:15:33 PM PDT 24
Finished Jul 30 05:15:35 PM PDT 24
Peak memory 205412 kb
Host smart-871fe438-aa59-4dd4-99a1-6fabeaeee085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218253289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3218253289
Directory /workspace/1.rv_dm_smoke/latest


Test location /workspace/coverage/default/1.rv_dm_stress_all.2016140973
Short name T22
Test name
Test status
Simulation time 4242194161 ps
CPU time 12.22 seconds
Started Jul 30 05:15:41 PM PDT 24
Finished Jul 30 05:15:54 PM PDT 24
Peak memory 205632 kb
Host smart-aa52f961-f12e-4963-82b6-263fc5fa4aae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016140973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2016140973
Directory /workspace/1.rv_dm_stress_all/latest


Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.2157103083
Short name T75
Test name
Test status
Simulation time 97169673410 ps
CPU time 1093.96 seconds
Started Jul 30 05:15:40 PM PDT 24
Finished Jul 30 05:33:54 PM PDT 24
Peak memory 239032 kb
Host smart-7b4908d6-029c-4f3c-893e-e759da197b81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157103083 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.2157103083
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/10.rv_dm_alert_test.1553471709
Short name T46
Test name
Test status
Simulation time 94881539 ps
CPU time 0.77 seconds
Started Jul 30 05:15:59 PM PDT 24
Finished Jul 30 05:16:00 PM PDT 24
Peak memory 205272 kb
Host smart-e9987025-5956-43f8-9afd-97f989de2e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553471709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1553471709
Directory /workspace/10.rv_dm_alert_test/latest


Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3631471784
Short name T227
Test name
Test status
Simulation time 3377337530 ps
CPU time 3.8 seconds
Started Jul 30 05:15:58 PM PDT 24
Finished Jul 30 05:16:02 PM PDT 24
Peak memory 213968 kb
Host smart-50941c9c-9966-4605-b6f0-4c88d8bca6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631471784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3631471784
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.565446915
Short name T203
Test name
Test status
Simulation time 1629062183 ps
CPU time 3.03 seconds
Started Jul 30 05:15:59 PM PDT 24
Finished Jul 30 05:16:02 PM PDT 24
Peak memory 205612 kb
Host smart-e3ddd4c4-9bd4-410f-9c1b-ce14f53acc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565446915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.565446915
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1119457034
Short name T1
Test name
Test status
Simulation time 9350683272 ps
CPU time 26.39 seconds
Started Jul 30 05:15:57 PM PDT 24
Finished Jul 30 05:16:23 PM PDT 24
Peak memory 213900 kb
Host smart-3ea76238-325e-4ddb-8aac-ef0e7e0d4d87
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1119457034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1119457034
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.4129209918
Short name T125
Test name
Test status
Simulation time 3177118182 ps
CPU time 9.48 seconds
Started Jul 30 05:15:56 PM PDT 24
Finished Jul 30 05:16:05 PM PDT 24
Peak memory 213892 kb
Host smart-7adadf6e-c0e8-4057-882c-38007d5b4016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129209918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.4129209918
Directory /workspace/10.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/10.rv_dm_stress_all.230756712
Short name T160
Test name
Test status
Simulation time 2888009769 ps
CPU time 4.61 seconds
Started Jul 30 05:16:00 PM PDT 24
Finished Jul 30 05:16:04 PM PDT 24
Peak memory 213816 kb
Host smart-60ea6cf6-c183-4912-8972-64f82cfeb723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230756712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.230756712
Directory /workspace/10.rv_dm_stress_all/latest


Test location /workspace/coverage/default/11.rv_dm_alert_test.2266072825
Short name T250
Test name
Test status
Simulation time 76631419 ps
CPU time 0.84 seconds
Started Jul 30 05:16:01 PM PDT 24
Finished Jul 30 05:16:02 PM PDT 24
Peak memory 205300 kb
Host smart-3594d99d-1651-44c1-b8b0-8fe2ea19961b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266072825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2266072825
Directory /workspace/11.rv_dm_alert_test/latest


Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.2809133793
Short name T215
Test name
Test status
Simulation time 1841873220 ps
CPU time 6.35 seconds
Started Jul 30 05:16:10 PM PDT 24
Finished Jul 30 05:16:16 PM PDT 24
Peak memory 213780 kb
Host smart-c92d3853-4a2d-4987-84c2-a61f55adde4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809133793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.2809133793
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.176365552
Short name T141
Test name
Test status
Simulation time 1496574613 ps
CPU time 4.89 seconds
Started Jul 30 05:16:02 PM PDT 24
Finished Jul 30 05:16:07 PM PDT 24
Peak memory 213820 kb
Host smart-ece6dd80-001f-4899-89b6-9c3769c9e375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176365552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.176365552
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2706684206
Short name T51
Test name
Test status
Simulation time 3931704483 ps
CPU time 3.97 seconds
Started Jul 30 05:16:08 PM PDT 24
Finished Jul 30 05:16:12 PM PDT 24
Peak memory 213896 kb
Host smart-ee097545-f90d-4fe4-a6e8-7b3a93809b50
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706684206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2706684206
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3921073407
Short name T253
Test name
Test status
Simulation time 2409947484 ps
CPU time 2.95 seconds
Started Jul 30 05:16:02 PM PDT 24
Finished Jul 30 05:16:06 PM PDT 24
Peak memory 205792 kb
Host smart-0186bcca-2455-4ddd-97ec-bcd43096927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921073407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3921073407
Directory /workspace/11.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/11.rv_dm_stress_all.2760566530
Short name T301
Test name
Test status
Simulation time 10464066933 ps
CPU time 10.47 seconds
Started Jul 30 05:16:09 PM PDT 24
Finished Jul 30 05:16:20 PM PDT 24
Peak memory 213780 kb
Host smart-f35e95d0-c5ff-43f9-ad01-8099d7a5f91f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760566530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.2760566530
Directory /workspace/11.rv_dm_stress_all/latest


Test location /workspace/coverage/default/12.rv_dm_alert_test.3833413457
Short name T132
Test name
Test status
Simulation time 43842184 ps
CPU time 0.77 seconds
Started Jul 30 05:16:09 PM PDT 24
Finished Jul 30 05:16:10 PM PDT 24
Peak memory 205268 kb
Host smart-5e0450bb-1350-4cbb-a0d6-566e49839641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833413457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3833413457
Directory /workspace/12.rv_dm_alert_test/latest


Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3020140007
Short name T143
Test name
Test status
Simulation time 29806349862 ps
CPU time 16.15 seconds
Started Jul 30 05:16:03 PM PDT 24
Finished Jul 30 05:16:19 PM PDT 24
Peak memory 205752 kb
Host smart-c8486013-a4c6-44fc-8fed-d0824dd3dc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020140007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3020140007
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3962093750
Short name T261
Test name
Test status
Simulation time 4995473406 ps
CPU time 5.21 seconds
Started Jul 30 05:16:00 PM PDT 24
Finished Jul 30 05:16:05 PM PDT 24
Peak memory 213876 kb
Host smart-134c0a53-94a9-4841-9d74-4d603f5ec724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962093750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3962093750
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.973348458
Short name T245
Test name
Test status
Simulation time 6385392406 ps
CPU time 9.66 seconds
Started Jul 30 05:16:10 PM PDT 24
Finished Jul 30 05:16:19 PM PDT 24
Peak memory 205700 kb
Host smart-1673471d-99b1-4323-95bb-62cee7668dc6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=973348458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.973348458
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.1775510051
Short name T195
Test name
Test status
Simulation time 4037350983 ps
CPU time 10.47 seconds
Started Jul 30 05:16:00 PM PDT 24
Finished Jul 30 05:16:11 PM PDT 24
Peak memory 214128 kb
Host smart-6d7a7ecd-00f2-4526-8f54-b1754608848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775510051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1775510051
Directory /workspace/12.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/13.rv_dm_alert_test.358799402
Short name T293
Test name
Test status
Simulation time 43213135 ps
CPU time 0.77 seconds
Started Jul 30 05:16:00 PM PDT 24
Finished Jul 30 05:16:01 PM PDT 24
Peak memory 205228 kb
Host smart-24472eb6-82ee-4085-a92a-8a7a6b08b0c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358799402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.358799402
Directory /workspace/13.rv_dm_alert_test/latest


Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.2334801849
Short name T29
Test name
Test status
Simulation time 11762411565 ps
CPU time 8.96 seconds
Started Jul 30 05:16:00 PM PDT 24
Finished Jul 30 05:16:09 PM PDT 24
Peak memory 214052 kb
Host smart-65187fac-38c5-499a-9b26-4c12aa4ef27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334801849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.2334801849
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1570735438
Short name T152
Test name
Test status
Simulation time 11458523356 ps
CPU time 11.13 seconds
Started Jul 30 05:16:02 PM PDT 24
Finished Jul 30 05:16:13 PM PDT 24
Peak memory 213920 kb
Host smart-b7495e7f-38ad-4c2d-b7bd-0d679263d8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570735438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1570735438
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.652841005
Short name T192
Test name
Test status
Simulation time 1980554540 ps
CPU time 2.03 seconds
Started Jul 30 05:16:04 PM PDT 24
Finished Jul 30 05:16:06 PM PDT 24
Peak memory 205560 kb
Host smart-57e80e71-47df-4ff9-90fe-d1a22999e313
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652841005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.652841005
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.402706709
Short name T67
Test name
Test status
Simulation time 4541264405 ps
CPU time 12.49 seconds
Started Jul 30 05:16:01 PM PDT 24
Finished Jul 30 05:16:14 PM PDT 24
Peak memory 205696 kb
Host smart-90432e96-0167-40a9-8a7c-5643468b8f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402706709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.402706709
Directory /workspace/13.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/13.rv_dm_stress_all.942360490
Short name T5
Test name
Test status
Simulation time 3621169335 ps
CPU time 3.64 seconds
Started Jul 30 05:16:03 PM PDT 24
Finished Jul 30 05:16:06 PM PDT 24
Peak memory 213744 kb
Host smart-8903e090-13d4-4233-a96e-3643e3b53914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942360490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.942360490
Directory /workspace/13.rv_dm_stress_all/latest


Test location /workspace/coverage/default/14.rv_dm_alert_test.3012168419
Short name T30
Test name
Test status
Simulation time 47951536 ps
CPU time 0.8 seconds
Started Jul 30 05:16:01 PM PDT 24
Finished Jul 30 05:16:02 PM PDT 24
Peak memory 205308 kb
Host smart-21ecff7a-bd3a-4c19-b5e6-1d8a4170fec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012168419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3012168419
Directory /workspace/14.rv_dm_alert_test/latest


Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2568469268
Short name T186
Test name
Test status
Simulation time 2526949336 ps
CPU time 6.81 seconds
Started Jul 30 05:16:01 PM PDT 24
Finished Jul 30 05:16:08 PM PDT 24
Peak memory 222052 kb
Host smart-9481d135-9a06-40a9-9522-590e671bfbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568469268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2568469268
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3307479556
Short name T199
Test name
Test status
Simulation time 1360441379 ps
CPU time 3.29 seconds
Started Jul 30 05:16:04 PM PDT 24
Finished Jul 30 05:16:07 PM PDT 24
Peak memory 205700 kb
Host smart-00d7a443-b9fe-4200-8293-1558a9cc2ad4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3307479556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3307479556
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.306472077
Short name T2
Test name
Test status
Simulation time 3044098314 ps
CPU time 3.22 seconds
Started Jul 30 05:16:02 PM PDT 24
Finished Jul 30 05:16:05 PM PDT 24
Peak memory 205720 kb
Host smart-425a26ec-812f-42c2-9efa-0da2c9b5f92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306472077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.306472077
Directory /workspace/14.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/15.rv_dm_alert_test.757378500
Short name T222
Test name
Test status
Simulation time 81929945 ps
CPU time 0.71 seconds
Started Jul 30 05:16:06 PM PDT 24
Finished Jul 30 05:16:07 PM PDT 24
Peak memory 205276 kb
Host smart-d4b067ee-6445-4ff7-b863-fcbfea4c87bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757378500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.757378500
Directory /workspace/15.rv_dm_alert_test/latest


Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.722539301
Short name T73
Test name
Test status
Simulation time 39921029667 ps
CPU time 96.9 seconds
Started Jul 30 05:16:07 PM PDT 24
Finished Jul 30 05:17:44 PM PDT 24
Peak memory 213920 kb
Host smart-d58bc527-578a-4316-b3a3-6930d5094253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722539301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.722539301
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1902131656
Short name T255
Test name
Test status
Simulation time 7601416971 ps
CPU time 11.4 seconds
Started Jul 30 05:16:07 PM PDT 24
Finished Jul 30 05:16:18 PM PDT 24
Peak memory 213848 kb
Host smart-d4cf1438-82be-4489-942e-f464ca41a86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902131656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1902131656
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1941579973
Short name T304
Test name
Test status
Simulation time 12398894390 ps
CPU time 13.17 seconds
Started Jul 30 05:16:00 PM PDT 24
Finished Jul 30 05:16:13 PM PDT 24
Peak memory 213948 kb
Host smart-47c0ac3b-f3c4-45f8-912c-8bbb63a03e98
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1941579973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.1941579973
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1387172655
Short name T210
Test name
Test status
Simulation time 4443666361 ps
CPU time 7.15 seconds
Started Jul 30 05:16:15 PM PDT 24
Finished Jul 30 05:16:22 PM PDT 24
Peak memory 205672 kb
Host smart-d699fb75-9e9d-498a-b8c3-b79aff4da9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387172655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1387172655
Directory /workspace/15.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/16.rv_dm_alert_test.106788638
Short name T194
Test name
Test status
Simulation time 194632812 ps
CPU time 0.79 seconds
Started Jul 30 05:16:04 PM PDT 24
Finished Jul 30 05:16:05 PM PDT 24
Peak memory 205304 kb
Host smart-d1947c79-19bd-41f6-a620-6f775c6d96ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106788638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.106788638
Directory /workspace/16.rv_dm_alert_test/latest


Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.1753113421
Short name T136
Test name
Test status
Simulation time 3962142753 ps
CPU time 10.73 seconds
Started Jul 30 05:16:07 PM PDT 24
Finished Jul 30 05:16:18 PM PDT 24
Peak memory 213968 kb
Host smart-a9007784-bb82-4325-bfb9-e6836236ecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753113421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.1753113421
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.351517330
Short name T81
Test name
Test status
Simulation time 6713220635 ps
CPU time 18.88 seconds
Started Jul 30 05:16:05 PM PDT 24
Finished Jul 30 05:16:24 PM PDT 24
Peak memory 205692 kb
Host smart-b3e8a572-56ae-45e0-850b-d3acb5ca0149
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351517330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.351517330
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.4215266532
Short name T145
Test name
Test status
Simulation time 13866695912 ps
CPU time 24.09 seconds
Started Jul 30 05:16:06 PM PDT 24
Finished Jul 30 05:16:31 PM PDT 24
Peak memory 213880 kb
Host smart-a4d93fd3-722b-4311-a20f-b7b15eaa667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215266532 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.4215266532
Directory /workspace/16.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/16.rv_dm_stress_all.2698607820
Short name T144
Test name
Test status
Simulation time 5990655585 ps
CPU time 7 seconds
Started Jul 30 05:16:08 PM PDT 24
Finished Jul 30 05:16:15 PM PDT 24
Peak memory 205600 kb
Host smart-460bc43e-1b6c-49fc-9bb9-1c9a3d7d0b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698607820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2698607820
Directory /workspace/16.rv_dm_stress_all/latest


Test location /workspace/coverage/default/17.rv_dm_alert_test.1255030346
Short name T307
Test name
Test status
Simulation time 49524977 ps
CPU time 0.76 seconds
Started Jul 30 05:16:09 PM PDT 24
Finished Jul 30 05:16:10 PM PDT 24
Peak memory 205204 kb
Host smart-af42f975-3d90-4db8-9571-76463ce30599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255030346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.1255030346
Directory /workspace/17.rv_dm_alert_test/latest


Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3141679917
Short name T182
Test name
Test status
Simulation time 1479490346 ps
CPU time 5.31 seconds
Started Jul 30 05:16:06 PM PDT 24
Finished Jul 30 05:16:12 PM PDT 24
Peak memory 205680 kb
Host smart-94036806-242a-4b23-bcfa-fe65e184bc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141679917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3141679917
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1811706911
Short name T211
Test name
Test status
Simulation time 2078833170 ps
CPU time 6.02 seconds
Started Jul 30 05:16:07 PM PDT 24
Finished Jul 30 05:16:13 PM PDT 24
Peak memory 214060 kb
Host smart-0ffdb232-5be1-4b63-a3be-e187d5e1fbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811706911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1811706911
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1801399993
Short name T151
Test name
Test status
Simulation time 3749117006 ps
CPU time 6.51 seconds
Started Jul 30 05:16:06 PM PDT 24
Finished Jul 30 05:16:13 PM PDT 24
Peak memory 205752 kb
Host smart-629186fc-4f87-41e4-889c-58c9dd6eea6a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1801399993 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1801399993
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.942834389
Short name T31
Test name
Test status
Simulation time 1720563375 ps
CPU time 3.67 seconds
Started Jul 30 05:16:06 PM PDT 24
Finished Jul 30 05:16:10 PM PDT 24
Peak memory 205664 kb
Host smart-83c84e7d-cf15-4d2f-a7c8-2c62884a8673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942834389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.942834389
Directory /workspace/17.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/17.rv_dm_stress_all.2559004710
Short name T217
Test name
Test status
Simulation time 5652347001 ps
CPU time 5.61 seconds
Started Jul 30 05:16:06 PM PDT 24
Finished Jul 30 05:16:12 PM PDT 24
Peak memory 213756 kb
Host smart-ab9fb48b-0b1a-40fd-9b75-612aaca63776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559004710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2559004710
Directory /workspace/17.rv_dm_stress_all/latest


Test location /workspace/coverage/default/18.rv_dm_alert_test.2089206241
Short name T183
Test name
Test status
Simulation time 214267229 ps
CPU time 0.76 seconds
Started Jul 30 05:16:07 PM PDT 24
Finished Jul 30 05:16:08 PM PDT 24
Peak memory 205296 kb
Host smart-d4a77192-bfab-4a8e-9903-32382e63abdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089206241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2089206241
Directory /workspace/18.rv_dm_alert_test/latest


Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3995701879
Short name T279
Test name
Test status
Simulation time 51955358183 ps
CPU time 72.95 seconds
Started Jul 30 05:16:06 PM PDT 24
Finished Jul 30 05:17:19 PM PDT 24
Peak memory 205820 kb
Host smart-30014927-fac7-4a80-ba4d-6f51332d8103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995701879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3995701879
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1671632424
Short name T224
Test name
Test status
Simulation time 2151848477 ps
CPU time 2.74 seconds
Started Jul 30 05:16:05 PM PDT 24
Finished Jul 30 05:16:08 PM PDT 24
Peak memory 213880 kb
Host smart-b2ae2191-3bd9-4280-9726-40025a2e6cbd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1671632424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1671632424
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1423648057
Short name T249
Test name
Test status
Simulation time 2317943015 ps
CPU time 7.62 seconds
Started Jul 30 05:16:05 PM PDT 24
Finished Jul 30 05:16:13 PM PDT 24
Peak memory 213928 kb
Host smart-01f49e1f-4404-4639-a124-6673a26f714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423648057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1423648057
Directory /workspace/18.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/19.rv_dm_alert_test.2113357309
Short name T240
Test name
Test status
Simulation time 59385337 ps
CPU time 0.8 seconds
Started Jul 30 05:16:11 PM PDT 24
Finished Jul 30 05:16:12 PM PDT 24
Peak memory 205296 kb
Host smart-cb7835c2-8a90-494c-9c19-e61265fad35c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113357309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2113357309
Directory /workspace/19.rv_dm_alert_test/latest


Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.730654043
Short name T142
Test name
Test status
Simulation time 2461355255 ps
CPU time 7.06 seconds
Started Jul 30 05:16:09 PM PDT 24
Finished Jul 30 05:16:16 PM PDT 24
Peak memory 213916 kb
Host smart-617f79a7-7614-4e83-9619-f2bf8a2b8b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730654043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.730654043
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2664016681
Short name T26
Test name
Test status
Simulation time 2260297660 ps
CPU time 3.1 seconds
Started Jul 30 05:16:12 PM PDT 24
Finished Jul 30 05:16:15 PM PDT 24
Peak memory 213912 kb
Host smart-2bd4941c-1cb5-4f82-a966-a333401143fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664016681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2664016681
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1682895312
Short name T14
Test name
Test status
Simulation time 2564045538 ps
CPU time 9.47 seconds
Started Jul 30 05:16:12 PM PDT 24
Finished Jul 30 05:16:21 PM PDT 24
Peak memory 205772 kb
Host smart-2b4fdb8d-5256-4ff1-8612-018389d98dc3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1682895312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1682895312
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.679845861
Short name T273
Test name
Test status
Simulation time 735929818 ps
CPU time 2.02 seconds
Started Jul 30 05:16:07 PM PDT 24
Finished Jul 30 05:16:09 PM PDT 24
Peak memory 205604 kb
Host smart-ba73b70a-e051-4f64-a6fd-2569d36b1745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679845861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.679845861
Directory /workspace/19.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/19.rv_dm_stress_all.4019040454
Short name T201
Test name
Test status
Simulation time 7874069730 ps
CPU time 4.07 seconds
Started Jul 30 05:16:10 PM PDT 24
Finished Jul 30 05:16:14 PM PDT 24
Peak memory 213784 kb
Host smart-51a0fbec-61d5-41e9-b00f-ca27bb5bb2f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019040454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.4019040454
Directory /workspace/19.rv_dm_stress_all/latest


Test location /workspace/coverage/default/2.rv_dm_alert_test.4120023367
Short name T252
Test name
Test status
Simulation time 72369222 ps
CPU time 0.7 seconds
Started Jul 30 05:15:40 PM PDT 24
Finished Jul 30 05:15:41 PM PDT 24
Peak memory 205312 kb
Host smart-61cd0240-78c2-4952-a6d4-c1d40977b2fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120023367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.4120023367
Directory /workspace/2.rv_dm_alert_test/latest


Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.2894819958
Short name T305
Test name
Test status
Simulation time 32288220374 ps
CPU time 97.29 seconds
Started Jul 30 05:15:43 PM PDT 24
Finished Jul 30 05:17:20 PM PDT 24
Peak memory 213952 kb
Host smart-fa0e0501-c9d3-467a-8c78-3ecd07b9b3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894819958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2894819958
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1988963840
Short name T220
Test name
Test status
Simulation time 10508999560 ps
CPU time 29.02 seconds
Started Jul 30 05:15:41 PM PDT 24
Finished Jul 30 05:16:10 PM PDT 24
Peak memory 213928 kb
Host smart-454afe7e-7858-4821-847a-91aa09e6faaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988963840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1988963840
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1727976608
Short name T32
Test name
Test status
Simulation time 3063489749 ps
CPU time 2.28 seconds
Started Jul 30 05:15:40 PM PDT 24
Finished Jul 30 05:15:43 PM PDT 24
Peak memory 213908 kb
Host smart-942b50b0-e69c-4bb8-b852-75f9df212fd2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1727976608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1727976608
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.4202651728
Short name T3
Test name
Test status
Simulation time 304277370 ps
CPU time 0.9 seconds
Started Jul 30 05:15:41 PM PDT 24
Finished Jul 30 05:15:42 PM PDT 24
Peak memory 205304 kb
Host smart-aad7aad4-dedc-4fb1-9d2e-7e79737943a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202651728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.4202651728
Directory /workspace/2.rv_dm_halt_resume_whereto/latest


Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3553274420
Short name T7
Test name
Test status
Simulation time 416384838 ps
CPU time 1.16 seconds
Started Jul 30 05:15:42 PM PDT 24
Finished Jul 30 05:15:44 PM PDT 24
Peak memory 205256 kb
Host smart-5eb968cf-bf4b-40f0-ba9d-6d53af81df5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553274420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3553274420
Directory /workspace/2.rv_dm_hart_unavail/latest


Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.756394668
Short name T126
Test name
Test status
Simulation time 1222372114 ps
CPU time 2.2 seconds
Started Jul 30 05:15:39 PM PDT 24
Finished Jul 30 05:15:41 PM PDT 24
Peak memory 205600 kb
Host smart-38318d65-ea99-41e0-8994-fadebfe80ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756394668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.756394668
Directory /workspace/2.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/2.rv_dm_stress_all.1087037780
Short name T159
Test name
Test status
Simulation time 20389444452 ps
CPU time 45.92 seconds
Started Jul 30 05:15:40 PM PDT 24
Finished Jul 30 05:16:26 PM PDT 24
Peak memory 213756 kb
Host smart-93f266c9-f7a1-498f-a3c1-d8b0771109fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087037780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.1087037780
Directory /workspace/2.rv_dm_stress_all/latest


Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.524203431
Short name T74
Test name
Test status
Simulation time 490711634421 ps
CPU time 2203.01 seconds
Started Jul 30 05:15:43 PM PDT 24
Finished Jul 30 05:52:27 PM PDT 24
Peak memory 250704 kb
Host smart-df49fc53-2455-40e2-b5d0-23f2c3df2281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524203431 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.524203431
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/20.rv_dm_alert_test.887376843
Short name T68
Test name
Test status
Simulation time 76898678 ps
CPU time 0.85 seconds
Started Jul 30 05:16:10 PM PDT 24
Finished Jul 30 05:16:11 PM PDT 24
Peak memory 205260 kb
Host smart-8be67384-068a-4ebb-9381-e352449da9a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887376843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.887376843
Directory /workspace/20.rv_dm_alert_test/latest


Test location /workspace/coverage/default/20.rv_dm_stress_all.3477189679
Short name T39
Test name
Test status
Simulation time 2426023544 ps
CPU time 4.81 seconds
Started Jul 30 05:16:14 PM PDT 24
Finished Jul 30 05:16:19 PM PDT 24
Peak memory 205516 kb
Host smart-f928a64e-6090-4515-bb7e-f50ed670bc28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477189679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3477189679
Directory /workspace/20.rv_dm_stress_all/latest


Test location /workspace/coverage/default/21.rv_dm_alert_test.2439938787
Short name T207
Test name
Test status
Simulation time 92063944 ps
CPU time 0.74 seconds
Started Jul 30 05:16:10 PM PDT 24
Finished Jul 30 05:16:11 PM PDT 24
Peak memory 205288 kb
Host smart-e24633b1-3bfe-47b1-abf1-b6d1711ba5d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439938787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.2439938787
Directory /workspace/21.rv_dm_alert_test/latest


Test location /workspace/coverage/default/21.rv_dm_stress_all.4292262115
Short name T6
Test name
Test status
Simulation time 2842473593 ps
CPU time 5.17 seconds
Started Jul 30 05:16:10 PM PDT 24
Finished Jul 30 05:16:15 PM PDT 24
Peak memory 205524 kb
Host smart-b7499c8b-035c-4268-9c50-c88d0e46a3fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292262115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.4292262115
Directory /workspace/21.rv_dm_stress_all/latest


Test location /workspace/coverage/default/22.rv_dm_alert_test.2496212680
Short name T208
Test name
Test status
Simulation time 74796418 ps
CPU time 0.71 seconds
Started Jul 30 05:16:15 PM PDT 24
Finished Jul 30 05:16:16 PM PDT 24
Peak memory 205236 kb
Host smart-245d1fb8-210e-48f5-81d6-3426738cc28e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496212680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.2496212680
Directory /workspace/22.rv_dm_alert_test/latest


Test location /workspace/coverage/default/22.rv_dm_stress_all.1900211194
Short name T259
Test name
Test status
Simulation time 6265050035 ps
CPU time 8.66 seconds
Started Jul 30 05:16:11 PM PDT 24
Finished Jul 30 05:16:20 PM PDT 24
Peak memory 213824 kb
Host smart-39a50a24-d5d0-49b7-a6dd-3b548ea0f89f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900211194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1900211194
Directory /workspace/22.rv_dm_stress_all/latest


Test location /workspace/coverage/default/23.rv_dm_alert_test.4275699544
Short name T251
Test name
Test status
Simulation time 152087623 ps
CPU time 1.06 seconds
Started Jul 30 05:16:09 PM PDT 24
Finished Jul 30 05:16:10 PM PDT 24
Peak memory 205276 kb
Host smart-f1228938-633d-4b54-92f4-1b2adcef9f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275699544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.4275699544
Directory /workspace/23.rv_dm_alert_test/latest


Test location /workspace/coverage/default/23.rv_dm_stress_all.2850339574
Short name T131
Test name
Test status
Simulation time 4452751142 ps
CPU time 7.29 seconds
Started Jul 30 05:16:14 PM PDT 24
Finished Jul 30 05:16:21 PM PDT 24
Peak memory 205448 kb
Host smart-23d52b9e-63fd-4d24-9256-b870d0a079cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850339574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2850339574
Directory /workspace/23.rv_dm_stress_all/latest


Test location /workspace/coverage/default/24.rv_dm_alert_test.3658673560
Short name T244
Test name
Test status
Simulation time 28928401 ps
CPU time 0.73 seconds
Started Jul 30 05:16:10 PM PDT 24
Finished Jul 30 05:16:11 PM PDT 24
Peak memory 205288 kb
Host smart-7733c7a6-e6ed-41bd-b36b-4d74b9644bdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658673560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3658673560
Directory /workspace/24.rv_dm_alert_test/latest


Test location /workspace/coverage/default/24.rv_dm_stress_all.3352708428
Short name T258
Test name
Test status
Simulation time 4649574472 ps
CPU time 8.44 seconds
Started Jul 30 05:16:10 PM PDT 24
Finished Jul 30 05:16:19 PM PDT 24
Peak memory 213852 kb
Host smart-75109b73-c99e-49e0-bec8-14a023e75fb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352708428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.3352708428
Directory /workspace/24.rv_dm_stress_all/latest


Test location /workspace/coverage/default/25.rv_dm_alert_test.370310405
Short name T270
Test name
Test status
Simulation time 156518111 ps
CPU time 0.78 seconds
Started Jul 30 05:16:11 PM PDT 24
Finished Jul 30 05:16:12 PM PDT 24
Peak memory 205244 kb
Host smart-59b8069b-f14f-4acc-84cd-a1ea19f0675a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370310405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.370310405
Directory /workspace/25.rv_dm_alert_test/latest


Test location /workspace/coverage/default/25.rv_dm_stress_all.1682880328
Short name T158
Test name
Test status
Simulation time 4698327350 ps
CPU time 6.88 seconds
Started Jul 30 05:16:12 PM PDT 24
Finished Jul 30 05:16:19 PM PDT 24
Peak memory 213800 kb
Host smart-4357adb1-efac-4c60-ad71-00d5f10794dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682880328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.1682880328
Directory /workspace/25.rv_dm_stress_all/latest


Test location /workspace/coverage/default/26.rv_dm_alert_test.4164352324
Short name T312
Test name
Test status
Simulation time 91926235 ps
CPU time 0.73 seconds
Started Jul 30 05:16:11 PM PDT 24
Finished Jul 30 05:16:12 PM PDT 24
Peak memory 205324 kb
Host smart-2c550524-52b5-4d9c-b836-dce050fc8de3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164352324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.4164352324
Directory /workspace/26.rv_dm_alert_test/latest


Test location /workspace/coverage/default/27.rv_dm_alert_test.1755927429
Short name T130
Test name
Test status
Simulation time 73479805 ps
CPU time 0.75 seconds
Started Jul 30 05:16:11 PM PDT 24
Finished Jul 30 05:16:12 PM PDT 24
Peak memory 205260 kb
Host smart-fc1e7443-79ea-4765-af85-21a6e48b1665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755927429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1755927429
Directory /workspace/27.rv_dm_alert_test/latest


Test location /workspace/coverage/default/27.rv_dm_stress_all.323283494
Short name T13
Test name
Test status
Simulation time 4868317585 ps
CPU time 7.66 seconds
Started Jul 30 05:16:10 PM PDT 24
Finished Jul 30 05:16:18 PM PDT 24
Peak memory 213812 kb
Host smart-f1bed773-5e1d-49f5-82a5-35321d943a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323283494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.323283494
Directory /workspace/27.rv_dm_stress_all/latest


Test location /workspace/coverage/default/28.rv_dm_alert_test.3637762818
Short name T198
Test name
Test status
Simulation time 102840372 ps
CPU time 0.75 seconds
Started Jul 30 05:16:10 PM PDT 24
Finished Jul 30 05:16:11 PM PDT 24
Peak memory 205204 kb
Host smart-7226a260-550f-4c06-af3e-2882608502d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637762818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3637762818
Directory /workspace/28.rv_dm_alert_test/latest


Test location /workspace/coverage/default/28.rv_dm_stress_all.364421142
Short name T23
Test name
Test status
Simulation time 3791589387 ps
CPU time 5.71 seconds
Started Jul 30 05:16:12 PM PDT 24
Finished Jul 30 05:16:17 PM PDT 24
Peak memory 205652 kb
Host smart-ab9b17ff-21e0-440f-8f89-f5ed4ba77781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364421142 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.364421142
Directory /workspace/28.rv_dm_stress_all/latest


Test location /workspace/coverage/default/29.rv_dm_alert_test.3106665886
Short name T254
Test name
Test status
Simulation time 33140056 ps
CPU time 0.76 seconds
Started Jul 30 05:16:12 PM PDT 24
Finished Jul 30 05:16:13 PM PDT 24
Peak memory 205280 kb
Host smart-eb98e59a-56b3-4526-bceb-4944668daa9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106665886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3106665886
Directory /workspace/29.rv_dm_alert_test/latest


Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.2904449730
Short name T303
Test name
Test status
Simulation time 59887213512 ps
CPU time 26.42 seconds
Started Jul 30 05:15:41 PM PDT 24
Finished Jul 30 05:16:07 PM PDT 24
Peak memory 222104 kb
Host smart-b9dc6bbe-c14d-4161-ba4c-f3bc40af1bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904449730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.2904449730
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.4198437693
Short name T191
Test name
Test status
Simulation time 2902129923 ps
CPU time 3.3 seconds
Started Jul 30 05:15:41 PM PDT 24
Finished Jul 30 05:15:44 PM PDT 24
Peak memory 214000 kb
Host smart-2e8ededc-5ae9-42b8-8260-5214e74db500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198437693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.4198437693
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.2462357539
Short name T65
Test name
Test status
Simulation time 2273352863 ps
CPU time 2.16 seconds
Started Jul 30 05:15:44 PM PDT 24
Finished Jul 30 05:15:46 PM PDT 24
Peak memory 213932 kb
Host smart-bf6efe44-c0dc-46cb-b4e4-688802caf778
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2462357539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.2462357539
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3200954207
Short name T185
Test name
Test status
Simulation time 1289750446 ps
CPU time 2.3 seconds
Started Jul 30 05:15:42 PM PDT 24
Finished Jul 30 05:15:44 PM PDT 24
Peak memory 205196 kb
Host smart-c9516106-1712-4d62-bdc4-1532d4621d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200954207 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3200954207
Directory /workspace/3.rv_dm_hart_unavail/latest


Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3131616544
Short name T155
Test name
Test status
Simulation time 3129189235 ps
CPU time 9.3 seconds
Started Jul 30 05:15:44 PM PDT 24
Finished Jul 30 05:15:53 PM PDT 24
Peak memory 205848 kb
Host smart-e60d8fe4-f7b9-46df-a6bb-e44b4d6a173b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131616544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3131616544
Directory /workspace/3.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/3.rv_dm_sec_cm.1136891346
Short name T64
Test name
Test status
Simulation time 689039532 ps
CPU time 1.83 seconds
Started Jul 30 05:15:45 PM PDT 24
Finished Jul 30 05:15:47 PM PDT 24
Peak memory 229620 kb
Host smart-9dadb03c-84c5-4b6f-bb06-243d66efb5d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136891346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1136891346
Directory /workspace/3.rv_dm_sec_cm/latest


Test location /workspace/coverage/default/3.rv_dm_stress_all.325448145
Short name T309
Test name
Test status
Simulation time 5954467278 ps
CPU time 8.25 seconds
Started Jul 30 05:15:44 PM PDT 24
Finished Jul 30 05:15:52 PM PDT 24
Peak memory 213752 kb
Host smart-0b38c73b-c7b9-42d9-94c0-d0e4a10ea503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325448145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.325448145
Directory /workspace/3.rv_dm_stress_all/latest


Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.332777961
Short name T54
Test name
Test status
Simulation time 55852589361 ps
CPU time 621.08 seconds
Started Jul 30 05:15:48 PM PDT 24
Finished Jul 30 05:26:09 PM PDT 24
Peak memory 229392 kb
Host smart-0d3a3bd7-b211-4dc3-adfb-9ae49cfb426f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332777961 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.332777961
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/30.rv_dm_alert_test.2369684530
Short name T281
Test name
Test status
Simulation time 73597153 ps
CPU time 0.76 seconds
Started Jul 30 05:16:11 PM PDT 24
Finished Jul 30 05:16:12 PM PDT 24
Peak memory 205300 kb
Host smart-40bc1fe3-e2ee-4721-960a-b29086964d58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369684530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2369684530
Directory /workspace/30.rv_dm_alert_test/latest


Test location /workspace/coverage/default/30.rv_dm_stress_all.1714957868
Short name T69
Test name
Test status
Simulation time 1409417940 ps
CPU time 2.1 seconds
Started Jul 30 05:16:11 PM PDT 24
Finished Jul 30 05:16:13 PM PDT 24
Peak memory 205412 kb
Host smart-938879d1-40eb-4f55-a150-04ec0eae58cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714957868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.1714957868
Directory /workspace/30.rv_dm_stress_all/latest


Test location /workspace/coverage/default/31.rv_dm_alert_test.2079872953
Short name T209
Test name
Test status
Simulation time 200380357 ps
CPU time 0.74 seconds
Started Jul 30 05:16:13 PM PDT 24
Finished Jul 30 05:16:14 PM PDT 24
Peak memory 205204 kb
Host smart-5ae8712c-f5bb-4c31-9c34-5f0a20bc9653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079872953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2079872953
Directory /workspace/31.rv_dm_alert_test/latest


Test location /workspace/coverage/default/31.rv_dm_stress_all.2758572496
Short name T282
Test name
Test status
Simulation time 2532378166 ps
CPU time 3.23 seconds
Started Jul 30 05:16:13 PM PDT 24
Finished Jul 30 05:16:16 PM PDT 24
Peak memory 213784 kb
Host smart-137adc74-6077-4564-a998-d4a9d3af78b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758572496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2758572496
Directory /workspace/31.rv_dm_stress_all/latest


Test location /workspace/coverage/default/32.rv_dm_alert_test.2228041306
Short name T290
Test name
Test status
Simulation time 131327788 ps
CPU time 0.86 seconds
Started Jul 30 05:16:15 PM PDT 24
Finished Jul 30 05:16:16 PM PDT 24
Peak memory 205328 kb
Host smart-24ad1536-01d1-4cc4-b429-fe21efd2b640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228041306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2228041306
Directory /workspace/32.rv_dm_alert_test/latest


Test location /workspace/coverage/default/33.rv_dm_alert_test.3282479618
Short name T287
Test name
Test status
Simulation time 240993253 ps
CPU time 0.75 seconds
Started Jul 30 05:16:12 PM PDT 24
Finished Jul 30 05:16:13 PM PDT 24
Peak memory 205324 kb
Host smart-d8387ca5-49b1-4f1a-a1cb-71a3bebecd69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282479618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3282479618
Directory /workspace/33.rv_dm_alert_test/latest


Test location /workspace/coverage/default/34.rv_dm_alert_test.1452569284
Short name T241
Test name
Test status
Simulation time 148999415 ps
CPU time 0.87 seconds
Started Jul 30 05:16:16 PM PDT 24
Finished Jul 30 05:16:17 PM PDT 24
Peak memory 205140 kb
Host smart-7e8727df-c24e-4951-a65f-46ed8ee8f014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452569284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1452569284
Directory /workspace/34.rv_dm_alert_test/latest


Test location /workspace/coverage/default/34.rv_dm_stress_all.3429067932
Short name T146
Test name
Test status
Simulation time 11583576699 ps
CPU time 33.57 seconds
Started Jul 30 05:16:14 PM PDT 24
Finished Jul 30 05:16:48 PM PDT 24
Peak memory 205456 kb
Host smart-d101de63-5104-44a6-9394-ac80f41586a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429067932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3429067932
Directory /workspace/34.rv_dm_stress_all/latest


Test location /workspace/coverage/default/35.rv_dm_alert_test.2760183105
Short name T228
Test name
Test status
Simulation time 64079423 ps
CPU time 0.84 seconds
Started Jul 30 05:16:20 PM PDT 24
Finished Jul 30 05:16:21 PM PDT 24
Peak memory 205168 kb
Host smart-17bb4899-14ef-4e28-aded-843231ee1d1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760183105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2760183105
Directory /workspace/35.rv_dm_alert_test/latest


Test location /workspace/coverage/default/35.rv_dm_stress_all.1935787554
Short name T11
Test name
Test status
Simulation time 6330045563 ps
CPU time 5.49 seconds
Started Jul 30 05:16:15 PM PDT 24
Finished Jul 30 05:16:20 PM PDT 24
Peak memory 213832 kb
Host smart-a858763a-f5b0-49fb-a2e2-e0129ca81877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935787554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1935787554
Directory /workspace/35.rv_dm_stress_all/latest


Test location /workspace/coverage/default/36.rv_dm_alert_test.3375770554
Short name T306
Test name
Test status
Simulation time 87669436 ps
CPU time 0.81 seconds
Started Jul 30 05:16:15 PM PDT 24
Finished Jul 30 05:16:16 PM PDT 24
Peak memory 205224 kb
Host smart-85c86ba8-c623-4629-a27e-3062bac3fdb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375770554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3375770554
Directory /workspace/36.rv_dm_alert_test/latest


Test location /workspace/coverage/default/37.rv_dm_alert_test.3400600403
Short name T313
Test name
Test status
Simulation time 100742302 ps
CPU time 0.77 seconds
Started Jul 30 05:16:15 PM PDT 24
Finished Jul 30 05:16:17 PM PDT 24
Peak memory 205268 kb
Host smart-b7ca874b-47f3-4996-9866-600ed73d1f28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400600403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3400600403
Directory /workspace/37.rv_dm_alert_test/latest


Test location /workspace/coverage/default/37.rv_dm_stress_all.1598091704
Short name T229
Test name
Test status
Simulation time 1299798594 ps
CPU time 3.01 seconds
Started Jul 30 05:16:17 PM PDT 24
Finished Jul 30 05:16:20 PM PDT 24
Peak memory 213676 kb
Host smart-7782ac8b-eebf-4536-8303-7e147a28376c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598091704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.1598091704
Directory /workspace/37.rv_dm_stress_all/latest


Test location /workspace/coverage/default/38.rv_dm_alert_test.3510290141
Short name T193
Test name
Test status
Simulation time 130701075 ps
CPU time 0.74 seconds
Started Jul 30 05:16:16 PM PDT 24
Finished Jul 30 05:16:17 PM PDT 24
Peak memory 205312 kb
Host smart-2c1fe6b9-3726-46d6-9ee5-14bc0a16cb93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510290141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3510290141
Directory /workspace/38.rv_dm_alert_test/latest


Test location /workspace/coverage/default/38.rv_dm_stress_all.4093376971
Short name T266
Test name
Test status
Simulation time 4585361359 ps
CPU time 7.68 seconds
Started Jul 30 05:16:14 PM PDT 24
Finished Jul 30 05:16:22 PM PDT 24
Peak memory 205612 kb
Host smart-464b4376-e4be-4b78-b545-dcf331e5ecb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093376971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.4093376971
Directory /workspace/38.rv_dm_stress_all/latest


Test location /workspace/coverage/default/39.rv_dm_alert_test.1776959378
Short name T276
Test name
Test status
Simulation time 35156339 ps
CPU time 0.75 seconds
Started Jul 30 05:16:17 PM PDT 24
Finished Jul 30 05:16:18 PM PDT 24
Peak memory 205316 kb
Host smart-9d2c3a7d-df34-4c2c-9a19-25a24b8202ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776959378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1776959378
Directory /workspace/39.rv_dm_alert_test/latest


Test location /workspace/coverage/default/39.rv_dm_stress_all.4074043513
Short name T12
Test name
Test status
Simulation time 8147346365 ps
CPU time 11.9 seconds
Started Jul 30 05:16:17 PM PDT 24
Finished Jul 30 05:16:29 PM PDT 24
Peak memory 205556 kb
Host smart-cb6611d8-3029-4151-a973-724cad27f9f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074043513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.4074043513
Directory /workspace/39.rv_dm_stress_all/latest


Test location /workspace/coverage/default/4.rv_dm_alert_test.2943667121
Short name T206
Test name
Test status
Simulation time 62462023 ps
CPU time 0.7 seconds
Started Jul 30 05:15:47 PM PDT 24
Finished Jul 30 05:15:48 PM PDT 24
Peak memory 205204 kb
Host smart-31264b25-a6aa-4133-ba28-285b865b4ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943667121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2943667121
Directory /workspace/4.rv_dm_alert_test/latest


Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3811314071
Short name T289
Test name
Test status
Simulation time 62744071983 ps
CPU time 58.34 seconds
Started Jul 30 05:15:47 PM PDT 24
Finished Jul 30 05:16:45 PM PDT 24
Peak memory 222220 kb
Host smart-903f1b02-e54d-4767-b151-a331bbd58183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811314071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3811314071
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.4011173367
Short name T187
Test name
Test status
Simulation time 4722556884 ps
CPU time 14.09 seconds
Started Jul 30 05:15:47 PM PDT 24
Finished Jul 30 05:16:01 PM PDT 24
Peak memory 213944 kb
Host smart-0c83e6b4-0279-4a9e-a652-391929cb13a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011173367 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.4011173367
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.419920356
Short name T66
Test name
Test status
Simulation time 4168024842 ps
CPU time 10.27 seconds
Started Jul 30 05:15:47 PM PDT 24
Finished Jul 30 05:15:58 PM PDT 24
Peak memory 213904 kb
Host smart-4b08aeeb-923c-4c09-b435-6efff14d9fe8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419920356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl
_access.419920356
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.1808496839
Short name T299
Test name
Test status
Simulation time 481747117 ps
CPU time 1.32 seconds
Started Jul 30 05:15:49 PM PDT 24
Finished Jul 30 05:15:51 PM PDT 24
Peak memory 205176 kb
Host smart-893e8f2a-cfb4-4fda-be50-b709eabf630b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808496839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.1808496839
Directory /workspace/4.rv_dm_halt_resume_whereto/latest


Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2011061730
Short name T263
Test name
Test status
Simulation time 301050688 ps
CPU time 0.82 seconds
Started Jul 30 05:15:46 PM PDT 24
Finished Jul 30 05:15:47 PM PDT 24
Peak memory 205256 kb
Host smart-07cd61c1-2332-4b4d-a02c-9112dcd183a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011061730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2011061730
Directory /workspace/4.rv_dm_hart_unavail/latest


Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1765290279
Short name T284
Test name
Test status
Simulation time 3946276876 ps
CPU time 11.9 seconds
Started Jul 30 05:15:45 PM PDT 24
Finished Jul 30 05:15:57 PM PDT 24
Peak memory 213976 kb
Host smart-09f0732e-bd67-4c98-b615-a70beb4ec7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765290279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1765290279
Directory /workspace/4.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/4.rv_dm_sec_cm.1511557511
Short name T47
Test name
Test status
Simulation time 724244758 ps
CPU time 1.43 seconds
Started Jul 30 05:15:45 PM PDT 24
Finished Jul 30 05:15:46 PM PDT 24
Peak memory 228968 kb
Host smart-cc5c4c7e-6bcf-4f5a-bcf9-40d9979e419d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511557511 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1511557511
Directory /workspace/4.rv_dm_sec_cm/latest


Test location /workspace/coverage/default/4.rv_dm_stress_all.183794182
Short name T291
Test name
Test status
Simulation time 16361721619 ps
CPU time 13.2 seconds
Started Jul 30 05:15:48 PM PDT 24
Finished Jul 30 05:16:01 PM PDT 24
Peak memory 205560 kb
Host smart-ce086370-cf70-442b-a862-e0446aeb5d2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183794182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.183794182
Directory /workspace/4.rv_dm_stress_all/latest


Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.3474851201
Short name T76
Test name
Test status
Simulation time 73504263253 ps
CPU time 1060.9 seconds
Started Jul 30 05:15:49 PM PDT 24
Finished Jul 30 05:33:30 PM PDT 24
Peak memory 233368 kb
Host smart-5985a9b3-3090-4116-8a33-bde5caf192cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474851201 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.3474851201
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/40.rv_dm_alert_test.392627531
Short name T188
Test name
Test status
Simulation time 56295920 ps
CPU time 0.72 seconds
Started Jul 30 05:16:16 PM PDT 24
Finished Jul 30 05:16:17 PM PDT 24
Peak memory 205284 kb
Host smart-e9c2273c-df94-4d55-9b64-df068ceeb919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392627531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.392627531
Directory /workspace/40.rv_dm_alert_test/latest


Test location /workspace/coverage/default/40.rv_dm_stress_all.2382541270
Short name T302
Test name
Test status
Simulation time 3410541765 ps
CPU time 3.85 seconds
Started Jul 30 05:16:17 PM PDT 24
Finished Jul 30 05:16:21 PM PDT 24
Peak memory 205528 kb
Host smart-bad513b0-3443-4e69-8b98-1d0fcaec7a91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382541270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.2382541270
Directory /workspace/40.rv_dm_stress_all/latest


Test location /workspace/coverage/default/41.rv_dm_alert_test.4179395533
Short name T236
Test name
Test status
Simulation time 51923298 ps
CPU time 0.71 seconds
Started Jul 30 05:16:14 PM PDT 24
Finished Jul 30 05:16:15 PM PDT 24
Peak memory 205204 kb
Host smart-38f33e4c-63d0-4dc5-804f-5908a2eee532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179395533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.4179395533
Directory /workspace/41.rv_dm_alert_test/latest


Test location /workspace/coverage/default/41.rv_dm_stress_all.2171860912
Short name T296
Test name
Test status
Simulation time 5809742728 ps
CPU time 9.24 seconds
Started Jul 30 05:16:14 PM PDT 24
Finished Jul 30 05:16:24 PM PDT 24
Peak memory 205564 kb
Host smart-5ebda449-9f85-41e8-8ebe-d7d975fbedc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171860912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.2171860912
Directory /workspace/41.rv_dm_stress_all/latest


Test location /workspace/coverage/default/42.rv_dm_alert_test.2341374892
Short name T232
Test name
Test status
Simulation time 149411680 ps
CPU time 0.88 seconds
Started Jul 30 05:16:16 PM PDT 24
Finished Jul 30 05:16:17 PM PDT 24
Peak memory 205276 kb
Host smart-ff27c5d7-c0d2-42dd-b85e-49a7a9345a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341374892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2341374892
Directory /workspace/42.rv_dm_alert_test/latest


Test location /workspace/coverage/default/42.rv_dm_stress_all.2299481593
Short name T243
Test name
Test status
Simulation time 4361816187 ps
CPU time 12.33 seconds
Started Jul 30 05:16:19 PM PDT 24
Finished Jul 30 05:16:31 PM PDT 24
Peak memory 213720 kb
Host smart-659211e4-eaf6-4bba-ad25-3ebdd17a6a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299481593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.2299481593
Directory /workspace/42.rv_dm_stress_all/latest


Test location /workspace/coverage/default/43.rv_dm_alert_test.2762168322
Short name T189
Test name
Test status
Simulation time 158808558 ps
CPU time 0.81 seconds
Started Jul 30 05:16:17 PM PDT 24
Finished Jul 30 05:16:18 PM PDT 24
Peak memory 205280 kb
Host smart-bf98215a-32ed-4ba2-9edd-30177eb98f02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762168322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.2762168322
Directory /workspace/43.rv_dm_alert_test/latest


Test location /workspace/coverage/default/43.rv_dm_stress_all.2265423402
Short name T262
Test name
Test status
Simulation time 3647521211 ps
CPU time 2.94 seconds
Started Jul 30 05:16:15 PM PDT 24
Finished Jul 30 05:16:18 PM PDT 24
Peak memory 213760 kb
Host smart-5adf0c89-df93-4556-b941-ef679517fe19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265423402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.2265423402
Directory /workspace/43.rv_dm_stress_all/latest


Test location /workspace/coverage/default/44.rv_dm_alert_test.1079573627
Short name T219
Test name
Test status
Simulation time 36638912 ps
CPU time 0.76 seconds
Started Jul 30 05:16:21 PM PDT 24
Finished Jul 30 05:16:21 PM PDT 24
Peak memory 205268 kb
Host smart-68010044-27b1-4871-b549-2e31dcecd742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079573627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1079573627
Directory /workspace/44.rv_dm_alert_test/latest


Test location /workspace/coverage/default/44.rv_dm_stress_all.3547554733
Short name T138
Test name
Test status
Simulation time 2160809860 ps
CPU time 5.84 seconds
Started Jul 30 05:16:18 PM PDT 24
Finished Jul 30 05:16:24 PM PDT 24
Peak memory 205508 kb
Host smart-db755164-d8f2-4c56-8b81-f7877c1a7abe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547554733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3547554733
Directory /workspace/44.rv_dm_stress_all/latest


Test location /workspace/coverage/default/45.rv_dm_alert_test.187553088
Short name T283
Test name
Test status
Simulation time 121860375 ps
CPU time 0.71 seconds
Started Jul 30 05:16:21 PM PDT 24
Finished Jul 30 05:16:22 PM PDT 24
Peak memory 205280 kb
Host smart-e4634c9a-eaca-4a91-9384-eb3b4b4ff6f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187553088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.187553088
Directory /workspace/45.rv_dm_alert_test/latest


Test location /workspace/coverage/default/45.rv_dm_stress_all.462598411
Short name T268
Test name
Test status
Simulation time 8123293830 ps
CPU time 23.11 seconds
Started Jul 30 05:16:22 PM PDT 24
Finished Jul 30 05:16:46 PM PDT 24
Peak memory 205556 kb
Host smart-c16522e4-40d1-4551-8c45-df8001b210cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462598411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.462598411
Directory /workspace/45.rv_dm_stress_all/latest


Test location /workspace/coverage/default/46.rv_dm_alert_test.3439971920
Short name T196
Test name
Test status
Simulation time 162586707 ps
CPU time 0.88 seconds
Started Jul 30 05:16:20 PM PDT 24
Finished Jul 30 05:16:21 PM PDT 24
Peak memory 205256 kb
Host smart-28715429-c01a-4045-92b9-62695994ea0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439971920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3439971920
Directory /workspace/46.rv_dm_alert_test/latest


Test location /workspace/coverage/default/46.rv_dm_stress_all.742670926
Short name T230
Test name
Test status
Simulation time 2882990461 ps
CPU time 3.21 seconds
Started Jul 30 05:16:20 PM PDT 24
Finished Jul 30 05:16:23 PM PDT 24
Peak memory 205540 kb
Host smart-88a6f100-a5d9-48f6-b273-c1368e91936e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742670926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.742670926
Directory /workspace/46.rv_dm_stress_all/latest


Test location /workspace/coverage/default/47.rv_dm_alert_test.319795674
Short name T246
Test name
Test status
Simulation time 63158467 ps
CPU time 0.76 seconds
Started Jul 30 05:16:21 PM PDT 24
Finished Jul 30 05:16:22 PM PDT 24
Peak memory 205276 kb
Host smart-968d6713-2ed5-4221-9857-c2571ddc3c65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319795674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.319795674
Directory /workspace/47.rv_dm_alert_test/latest


Test location /workspace/coverage/default/47.rv_dm_stress_all.1515259970
Short name T19
Test name
Test status
Simulation time 3693900314 ps
CPU time 10.91 seconds
Started Jul 30 05:16:22 PM PDT 24
Finished Jul 30 05:16:33 PM PDT 24
Peak memory 205572 kb
Host smart-7ebdb95e-c4ad-4127-86e0-4abd952b706c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515259970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1515259970
Directory /workspace/47.rv_dm_stress_all/latest


Test location /workspace/coverage/default/48.rv_dm_alert_test.3206926933
Short name T257
Test name
Test status
Simulation time 40253710 ps
CPU time 0.81 seconds
Started Jul 30 05:16:20 PM PDT 24
Finished Jul 30 05:16:21 PM PDT 24
Peak memory 205228 kb
Host smart-cc30d9c1-8e56-4dcd-bde3-be5fbdadd7e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206926933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3206926933
Directory /workspace/48.rv_dm_alert_test/latest


Test location /workspace/coverage/default/48.rv_dm_stress_all.2023250705
Short name T239
Test name
Test status
Simulation time 2640032049 ps
CPU time 2.92 seconds
Started Jul 30 05:16:19 PM PDT 24
Finished Jul 30 05:16:22 PM PDT 24
Peak memory 205548 kb
Host smart-ba2ab991-1e64-42a7-8f0e-5d430103c51d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023250705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2023250705
Directory /workspace/48.rv_dm_stress_all/latest


Test location /workspace/coverage/default/49.rv_dm_alert_test.683465343
Short name T234
Test name
Test status
Simulation time 84688495 ps
CPU time 0.68 seconds
Started Jul 30 05:16:22 PM PDT 24
Finished Jul 30 05:16:23 PM PDT 24
Peak memory 205168 kb
Host smart-a80c742b-207f-498f-ab10-712238df130b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683465343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.683465343
Directory /workspace/49.rv_dm_alert_test/latest


Test location /workspace/coverage/default/49.rv_dm_stress_all.3645515873
Short name T137
Test name
Test status
Simulation time 6028155717 ps
CPU time 6.39 seconds
Started Jul 30 05:16:20 PM PDT 24
Finished Jul 30 05:16:26 PM PDT 24
Peak memory 213848 kb
Host smart-002ef6e4-6f9a-46a1-bbd1-1225c7802ce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645515873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.3645515873
Directory /workspace/49.rv_dm_stress_all/latest


Test location /workspace/coverage/default/5.rv_dm_alert_test.3184034016
Short name T221
Test name
Test status
Simulation time 178074747 ps
CPU time 0.89 seconds
Started Jul 30 05:15:50 PM PDT 24
Finished Jul 30 05:15:51 PM PDT 24
Peak memory 205240 kb
Host smart-166de804-942d-4582-aad7-e7e9ea1f5013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184034016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.3184034016
Directory /workspace/5.rv_dm_alert_test/latest


Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1180713792
Short name T297
Test name
Test status
Simulation time 11828911916 ps
CPU time 12.17 seconds
Started Jul 30 05:15:48 PM PDT 24
Finished Jul 30 05:16:01 PM PDT 24
Peak memory 205692 kb
Host smart-cd62270d-f753-469e-85da-b8ab3b04dca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180713792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1180713792
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3500266741
Short name T153
Test name
Test status
Simulation time 2618360305 ps
CPU time 1.94 seconds
Started Jul 30 05:16:11 PM PDT 24
Finished Jul 30 05:16:13 PM PDT 24
Peak memory 213940 kb
Host smart-78410e69-469c-47c5-9fd6-e41338c1cd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500266741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3500266741
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.166329872
Short name T269
Test name
Test status
Simulation time 599590651 ps
CPU time 2.61 seconds
Started Jul 30 05:15:48 PM PDT 24
Finished Jul 30 05:15:51 PM PDT 24
Peak memory 205596 kb
Host smart-0491be16-b8c7-4fff-b443-aab0832ac567
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166329872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.166329872
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.1452031556
Short name T178
Test name
Test status
Simulation time 206421025 ps
CPU time 1.03 seconds
Started Jul 30 05:15:47 PM PDT 24
Finished Jul 30 05:15:48 PM PDT 24
Peak memory 205260 kb
Host smart-b01ef5db-513e-4756-a572-86c6a3a92bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452031556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.1452031556
Directory /workspace/5.rv_dm_halt_resume_whereto/latest


Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.3624231699
Short name T200
Test name
Test status
Simulation time 5106782129 ps
CPU time 9.42 seconds
Started Jul 30 05:15:48 PM PDT 24
Finished Jul 30 05:15:58 PM PDT 24
Peak memory 213876 kb
Host smart-2b387a7a-937f-4aaa-8705-6e24b5dd2835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624231699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.3624231699
Directory /workspace/5.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/5.rv_dm_stress_all.3705943343
Short name T59
Test name
Test status
Simulation time 1301077471 ps
CPU time 4.72 seconds
Started Jul 30 05:15:53 PM PDT 24
Finished Jul 30 05:15:58 PM PDT 24
Peak memory 205412 kb
Host smart-8faf3393-79cb-487d-b107-04a986d36ca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705943343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3705943343
Directory /workspace/5.rv_dm_stress_all/latest


Test location /workspace/coverage/default/6.rv_dm_alert_test.330648034
Short name T271
Test name
Test status
Simulation time 88614049 ps
CPU time 0.72 seconds
Started Jul 30 05:15:55 PM PDT 24
Finished Jul 30 05:15:56 PM PDT 24
Peak memory 205204 kb
Host smart-bd1ea2e5-ae17-48bf-8db3-9e8e35bdf608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330648034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.330648034
Directory /workspace/6.rv_dm_alert_test/latest


Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.1892381864
Short name T24
Test name
Test status
Simulation time 14298280150 ps
CPU time 30.52 seconds
Started Jul 30 05:15:54 PM PDT 24
Finished Jul 30 05:16:25 PM PDT 24
Peak memory 213976 kb
Host smart-88aa89e0-a4d3-41f1-af7d-b61eb837d458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892381864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.1892381864
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2275732058
Short name T237
Test name
Test status
Simulation time 1234847828 ps
CPU time 1.57 seconds
Started Jul 30 05:15:53 PM PDT 24
Finished Jul 30 05:15:55 PM PDT 24
Peak memory 205572 kb
Host smart-4e56e255-294b-435f-b8d8-262b269b7c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275732058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2275732058
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.153234231
Short name T311
Test name
Test status
Simulation time 2264368912 ps
CPU time 1.68 seconds
Started Jul 30 05:15:51 PM PDT 24
Finished Jul 30 05:15:52 PM PDT 24
Peak memory 213972 kb
Host smart-9282b235-000e-4b36-ba7b-f1390b840f3e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=153234231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.153234231
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.3031699122
Short name T298
Test name
Test status
Simulation time 252479435 ps
CPU time 0.91 seconds
Started Jul 30 05:15:59 PM PDT 24
Finished Jul 30 05:16:00 PM PDT 24
Peak memory 205288 kb
Host smart-40f26479-8034-4755-aae2-145789401e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031699122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3031699122
Directory /workspace/6.rv_dm_halt_resume_whereto/latest


Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2782425611
Short name T233
Test name
Test status
Simulation time 2852696510 ps
CPU time 2.02 seconds
Started Jul 30 05:15:51 PM PDT 24
Finished Jul 30 05:15:53 PM PDT 24
Peak memory 213888 kb
Host smart-edbaec89-93c3-4350-aba9-5c530010c018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782425611 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2782425611
Directory /workspace/6.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/6.rv_dm_stress_all.2161206096
Short name T180
Test name
Test status
Simulation time 4551009061 ps
CPU time 4.84 seconds
Started Jul 30 05:15:50 PM PDT 24
Finished Jul 30 05:15:55 PM PDT 24
Peak memory 213732 kb
Host smart-26599b04-88b8-4dbc-ba4b-a1a0b2661bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161206096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.2161206096
Directory /workspace/6.rv_dm_stress_all/latest


Test location /workspace/coverage/default/7.rv_dm_alert_test.3292324696
Short name T184
Test name
Test status
Simulation time 95292635 ps
CPU time 0.73 seconds
Started Jul 30 05:15:53 PM PDT 24
Finished Jul 30 05:15:54 PM PDT 24
Peak memory 205300 kb
Host smart-af470fc2-23a1-4072-aa4a-d02e8a934fcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292324696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.3292324696
Directory /workspace/7.rv_dm_alert_test/latest


Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.668568995
Short name T127
Test name
Test status
Simulation time 1097852200 ps
CPU time 2.41 seconds
Started Jul 30 05:15:52 PM PDT 24
Finished Jul 30 05:15:55 PM PDT 24
Peak memory 213804 kb
Host smart-dc8f2702-f2e0-4936-9d5a-c6baf0e95e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668568995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.668568995
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1485536043
Short name T148
Test name
Test status
Simulation time 873768634 ps
CPU time 2.74 seconds
Started Jul 30 05:15:51 PM PDT 24
Finished Jul 30 05:15:54 PM PDT 24
Peak memory 205648 kb
Host smart-873a2025-19db-4d1d-98ec-af60fcfc0f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485536043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1485536043
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.3353538745
Short name T295
Test name
Test status
Simulation time 10991938674 ps
CPU time 11.13 seconds
Started Jul 30 05:15:52 PM PDT 24
Finished Jul 30 05:16:03 PM PDT 24
Peak memory 213976 kb
Host smart-10bcc1b0-7c9d-405d-ae4e-331c6f0b55bf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3353538745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.3353538745
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.1244136496
Short name T214
Test name
Test status
Simulation time 442951268 ps
CPU time 1.28 seconds
Started Jul 30 05:15:52 PM PDT 24
Finished Jul 30 05:15:54 PM PDT 24
Peak memory 205208 kb
Host smart-8dca94e7-2c38-4dc1-9753-22824d8c73b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244136496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.1244136496
Directory /workspace/7.rv_dm_halt_resume_whereto/latest


Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1097584365
Short name T294
Test name
Test status
Simulation time 3597818418 ps
CPU time 5.93 seconds
Started Jul 30 05:15:52 PM PDT 24
Finished Jul 30 05:15:58 PM PDT 24
Peak memory 205804 kb
Host smart-8adc34cd-9326-466d-b431-6bc7cc5dd98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097584365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1097584365
Directory /workspace/7.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/7.rv_dm_stress_all.1928713549
Short name T181
Test name
Test status
Simulation time 9774068410 ps
CPU time 13.48 seconds
Started Jul 30 05:15:51 PM PDT 24
Finished Jul 30 05:16:05 PM PDT 24
Peak memory 205588 kb
Host smart-401b1e71-9bcc-41df-bcc2-4ff9b1801b7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928713549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1928713549
Directory /workspace/7.rv_dm_stress_all/latest


Test location /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.3846527356
Short name T4
Test name
Test status
Simulation time 393340629010 ps
CPU time 1680.96 seconds
Started Jul 30 05:15:52 PM PDT 24
Finished Jul 30 05:43:54 PM PDT 24
Peak memory 243332 kb
Host smart-9e66c6c7-6edd-4954-85f5-a36d1f3e6d5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846527356 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.3846527356
Directory /workspace/7.rv_dm_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/8.rv_dm_alert_test.1286921825
Short name T242
Test name
Test status
Simulation time 40681317 ps
CPU time 0.79 seconds
Started Jul 30 05:15:57 PM PDT 24
Finished Jul 30 05:15:58 PM PDT 24
Peak memory 205272 kb
Host smart-6445f6fe-b2ec-4750-9b50-ffd4c283e3c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286921825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1286921825
Directory /workspace/8.rv_dm_alert_test/latest


Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.1698041765
Short name T274
Test name
Test status
Simulation time 13192575903 ps
CPU time 39.59 seconds
Started Jul 30 05:15:58 PM PDT 24
Finished Jul 30 05:16:37 PM PDT 24
Peak memory 213912 kb
Host smart-a1e37021-8f59-4349-8669-fc7f5f700fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698041765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.1698041765
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.1413362851
Short name T264
Test name
Test status
Simulation time 2160579830 ps
CPU time 7.48 seconds
Started Jul 30 05:15:58 PM PDT 24
Finished Jul 30 05:16:05 PM PDT 24
Peak memory 213948 kb
Host smart-cfbf682c-7e59-4ecd-90fc-1f00e1258aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413362851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.1413362851
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.27996767
Short name T213
Test name
Test status
Simulation time 5259952429 ps
CPU time 4.33 seconds
Started Jul 30 05:15:55 PM PDT 24
Finished Jul 30 05:15:59 PM PDT 24
Peak memory 213840 kb
Host smart-d720b77a-bdbf-4f01-894f-3bf8f5d03877
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=27996767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_
access.27996767
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.201573402
Short name T149
Test name
Test status
Simulation time 4490520718 ps
CPU time 13.26 seconds
Started Jul 30 05:15:50 PM PDT 24
Finished Jul 30 05:16:04 PM PDT 24
Peak memory 213972 kb
Host smart-ffe03c60-8349-4776-8edb-686daa9f3261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201573402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.201573402
Directory /workspace/8.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/8.rv_dm_stress_all.2232257357
Short name T129
Test name
Test status
Simulation time 4344382382 ps
CPU time 7.52 seconds
Started Jul 30 05:15:57 PM PDT 24
Finished Jul 30 05:16:04 PM PDT 24
Peak memory 213808 kb
Host smart-c22fc552-bb3b-4c04-943f-16fbae68d56b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232257357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2232257357
Directory /workspace/8.rv_dm_stress_all/latest


Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.1599896564
Short name T77
Test name
Test status
Simulation time 269665375441 ps
CPU time 1554.63 seconds
Started Jul 30 05:15:55 PM PDT 24
Finished Jul 30 05:41:50 PM PDT 24
Peak memory 246044 kb
Host smart-765ca630-ab56-4efb-9af0-2f9e881c930c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599896564 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.1599896564
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/9.rv_dm_alert_test.3140015092
Short name T226
Test name
Test status
Simulation time 138932075 ps
CPU time 0.9 seconds
Started Jul 30 05:15:58 PM PDT 24
Finished Jul 30 05:15:59 PM PDT 24
Peak memory 205288 kb
Host smart-9b7d8990-8b83-426e-8beb-620888e7ba7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140015092 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.3140015092
Directory /workspace/9.rv_dm_alert_test/latest


Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1109029042
Short name T218
Test name
Test status
Simulation time 18366575061 ps
CPU time 25.63 seconds
Started Jul 30 05:15:57 PM PDT 24
Finished Jul 30 05:16:23 PM PDT 24
Peak memory 213864 kb
Host smart-4f44f2e9-489f-4197-b80f-b1cc10dc5d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109029042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1109029042
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest


Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.2584341145
Short name T247
Test name
Test status
Simulation time 990838327 ps
CPU time 2.04 seconds
Started Jul 30 05:15:59 PM PDT 24
Finished Jul 30 05:16:01 PM PDT 24
Peak memory 214104 kb
Host smart-6f7c414f-e836-4b4b-8ba1-9756360e53f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584341145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.2584341145
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest


Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3226961158
Short name T235
Test name
Test status
Simulation time 2634684188 ps
CPU time 8.4 seconds
Started Jul 30 05:15:56 PM PDT 24
Finished Jul 30 05:16:05 PM PDT 24
Peak memory 205704 kb
Host smart-d80757bd-ff1d-44ec-9dd5-28feb5cf0ebf
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3226961158 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3226961158
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest


Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3809874157
Short name T205
Test name
Test status
Simulation time 2278152715 ps
CPU time 6.7 seconds
Started Jul 30 05:15:57 PM PDT 24
Finished Jul 30 05:16:04 PM PDT 24
Peak memory 205924 kb
Host smart-a6e6af7f-d844-4eb3-acde-49b3ca71cbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809874157 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3809874157
Directory /workspace/9.rv_dm_sba_tl_access/latest


Test location /workspace/coverage/default/9.rv_dm_stress_all.3843621389
Short name T10
Test name
Test status
Simulation time 4946883677 ps
CPU time 9.09 seconds
Started Jul 30 05:15:55 PM PDT 24
Finished Jul 30 05:16:04 PM PDT 24
Peak memory 213704 kb
Host smart-16203e85-c85d-4114-92ff-debbdc3793a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843621389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.3843621389
Directory /workspace/9.rv_dm_stress_all/latest


Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.1102703459
Short name T16
Test name
Test status
Simulation time 218655842395 ps
CPU time 788.44 seconds
Started Jul 30 05:15:57 PM PDT 24
Finished Jul 30 05:29:06 PM PDT 24
Peak memory 238232 kb
Host smart-89563043-daa5-45db-baf5-367a0f2176db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102703459 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.1102703459
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%