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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
84.00 96.18 85.20 89.91 73.75 88.33 98.32 56.31


Total test records in report: 465
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T84 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1532012820 Jul 31 06:08:02 PM PDT 24 Jul 31 06:08:24 PM PDT 24 2758223417 ps
T85 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2145336232 Jul 31 06:08:44 PM PDT 24 Jul 31 06:08:48 PM PDT 24 255554267 ps
T69 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3864547198 Jul 31 06:07:57 PM PDT 24 Jul 31 06:08:10 PM PDT 24 8099048195 ps
T96 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3948282713 Jul 31 06:08:58 PM PDT 24 Jul 31 06:09:01 PM PDT 24 228603715 ps
T306 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.724450102 Jul 31 06:07:58 PM PDT 24 Jul 31 06:07:59 PM PDT 24 196041017 ps
T86 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1349357193 Jul 31 06:09:01 PM PDT 24 Jul 31 06:09:08 PM PDT 24 668850249 ps
T307 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3542253799 Jul 31 06:08:08 PM PDT 24 Jul 31 06:08:09 PM PDT 24 141772696 ps
T308 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1958409886 Jul 31 06:09:12 PM PDT 24 Jul 31 06:09:21 PM PDT 24 3027517504 ps
T309 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2204441129 Jul 31 06:08:52 PM PDT 24 Jul 31 06:08:58 PM PDT 24 1971297998 ps
T310 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4064632714 Jul 31 06:08:22 PM PDT 24 Jul 31 06:08:38 PM PDT 24 25824055919 ps
T311 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1310854152 Jul 31 06:09:21 PM PDT 24 Jul 31 06:09:38 PM PDT 24 5213337631 ps
T87 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1943120163 Jul 31 06:08:17 PM PDT 24 Jul 31 06:08:54 PM PDT 24 15329375660 ps
T124 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1305318866 Jul 31 06:09:23 PM PDT 24 Jul 31 06:09:35 PM PDT 24 1188203759 ps
T312 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1969145439 Jul 31 06:08:07 PM PDT 24 Jul 31 06:09:54 PM PDT 24 41739733245 ps
T88 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3046396036 Jul 31 06:08:27 PM PDT 24 Jul 31 06:09:38 PM PDT 24 44609117801 ps
T313 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1893894574 Jul 31 06:07:51 PM PDT 24 Jul 31 06:07:52 PM PDT 24 162239671 ps
T314 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.416624153 Jul 31 06:08:02 PM PDT 24 Jul 31 06:17:33 PM PDT 24 241795479341 ps
T315 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.366033826 Jul 31 06:07:56 PM PDT 24 Jul 31 06:07:57 PM PDT 24 119823131 ps
T89 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2036079922 Jul 31 06:07:58 PM PDT 24 Jul 31 06:08:00 PM PDT 24 250126337 ps
T316 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4091522708 Jul 31 06:09:12 PM PDT 24 Jul 31 06:09:13 PM PDT 24 193140486 ps
T317 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1641105713 Jul 31 06:08:16 PM PDT 24 Jul 31 06:10:02 PM PDT 24 74616878217 ps
T318 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3449114468 Jul 31 06:07:49 PM PDT 24 Jul 31 06:07:50 PM PDT 24 229630940 ps
T319 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1891646459 Jul 31 06:08:08 PM PDT 24 Jul 31 06:08:12 PM PDT 24 115584825 ps
T320 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2393137425 Jul 31 06:08:24 PM PDT 24 Jul 31 06:09:33 PM PDT 24 24307868677 ps
T90 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2166028343 Jul 31 06:07:54 PM PDT 24 Jul 31 06:08:47 PM PDT 24 5251088343 ps
T321 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.258833361 Jul 31 06:09:02 PM PDT 24 Jul 31 06:09:29 PM PDT 24 15607836677 ps
T91 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.994333188 Jul 31 06:09:16 PM PDT 24 Jul 31 06:09:21 PM PDT 24 348612251 ps
T92 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3565325600 Jul 31 06:08:40 PM PDT 24 Jul 31 06:08:42 PM PDT 24 114926391 ps
T322 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.549219084 Jul 31 06:08:38 PM PDT 24 Jul 31 06:08:41 PM PDT 24 2407262775 ps
T323 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.777539014 Jul 31 06:08:26 PM PDT 24 Jul 31 06:08:27 PM PDT 24 261701366 ps
T93 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1120151334 Jul 31 06:08:16 PM PDT 24 Jul 31 06:09:38 PM PDT 24 13418832773 ps
T94 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4037263145 Jul 31 06:08:34 PM PDT 24 Jul 31 06:08:37 PM PDT 24 480182152 ps
T324 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2952538101 Jul 31 06:09:24 PM PDT 24 Jul 31 06:09:28 PM PDT 24 9830553814 ps
T325 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1140349016 Jul 31 06:08:37 PM PDT 24 Jul 31 06:08:38 PM PDT 24 285040983 ps
T326 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4052393344 Jul 31 06:09:20 PM PDT 24 Jul 31 06:09:22 PM PDT 24 1102178847 ps
T95 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4166722070 Jul 31 06:08:07 PM PDT 24 Jul 31 06:08:43 PM PDT 24 34026669124 ps
T100 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4046606300 Jul 31 06:08:43 PM PDT 24 Jul 31 06:08:47 PM PDT 24 505428463 ps
T327 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2907022534 Jul 31 06:08:28 PM PDT 24 Jul 31 06:08:31 PM PDT 24 155173012 ps
T328 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4238041166 Jul 31 06:08:09 PM PDT 24 Jul 31 06:08:11 PM PDT 24 157021919 ps
T329 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2649680525 Jul 31 06:08:23 PM PDT 24 Jul 31 06:08:24 PM PDT 24 74704282 ps
T330 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2967816509 Jul 31 06:09:26 PM PDT 24 Jul 31 06:09:30 PM PDT 24 2915929106 ps
T331 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1321840205 Jul 31 06:08:44 PM PDT 24 Jul 31 06:08:47 PM PDT 24 1063172125 ps
T332 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2571821061 Jul 31 06:08:02 PM PDT 24 Jul 31 06:08:03 PM PDT 24 32102914 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3106724407 Jul 31 06:07:52 PM PDT 24 Jul 31 06:07:54 PM PDT 24 388470782 ps
T101 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3779790693 Jul 31 06:09:09 PM PDT 24 Jul 31 06:09:11 PM PDT 24 979934976 ps
T334 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4128667221 Jul 31 06:08:07 PM PDT 24 Jul 31 06:08:09 PM PDT 24 476380099 ps
T335 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4224818137 Jul 31 06:08:02 PM PDT 24 Jul 31 06:08:06 PM PDT 24 2962318731 ps
T336 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3068457307 Jul 31 06:07:50 PM PDT 24 Jul 31 06:08:01 PM PDT 24 34182456370 ps
T337 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2801739754 Jul 31 06:09:21 PM PDT 24 Jul 31 06:09:29 PM PDT 24 7415551771 ps
T338 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1644433869 Jul 31 06:08:01 PM PDT 24 Jul 31 06:08:06 PM PDT 24 258541475 ps
T102 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3953252864 Jul 31 06:08:00 PM PDT 24 Jul 31 06:08:02 PM PDT 24 225371856 ps
T103 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3435041773 Jul 31 06:08:46 PM PDT 24 Jul 31 06:08:48 PM PDT 24 113841874 ps
T339 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1517872249 Jul 31 06:08:33 PM PDT 24 Jul 31 06:08:35 PM PDT 24 632141835 ps
T118 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2667221034 Jul 31 06:07:57 PM PDT 24 Jul 31 06:08:02 PM PDT 24 675182699 ps
T112 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3468199635 Jul 31 06:08:39 PM PDT 24 Jul 31 06:08:42 PM PDT 24 280847529 ps
T340 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2656303379 Jul 31 06:09:23 PM PDT 24 Jul 31 06:09:27 PM PDT 24 152117893 ps
T113 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1875410240 Jul 31 06:08:34 PM PDT 24 Jul 31 06:08:37 PM PDT 24 214082002 ps
T125 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2678467201 Jul 31 06:09:23 PM PDT 24 Jul 31 06:09:48 PM PDT 24 2761668870 ps
T126 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.296562478 Jul 31 06:09:19 PM PDT 24 Jul 31 06:09:22 PM PDT 24 1468601729 ps
T341 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2456391146 Jul 31 06:08:36 PM PDT 24 Jul 31 06:10:34 PM PDT 24 43766664561 ps
T342 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3668433882 Jul 31 06:08:13 PM PDT 24 Jul 31 06:08:26 PM PDT 24 3034819689 ps
T161 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3619075351 Jul 31 06:09:18 PM PDT 24 Jul 31 06:09:28 PM PDT 24 8973558183 ps
T343 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2077415920 Jul 31 06:08:43 PM PDT 24 Jul 31 06:08:46 PM PDT 24 1776918443 ps
T344 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1923591547 Jul 31 06:09:06 PM PDT 24 Jul 31 06:09:09 PM PDT 24 1887324238 ps
T168 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1797861644 Jul 31 06:09:02 PM PDT 24 Jul 31 06:09:24 PM PDT 24 4649720307 ps
T345 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1294532472 Jul 31 06:07:53 PM PDT 24 Jul 31 06:07:58 PM PDT 24 4291607854 ps
T346 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2083644693 Jul 31 06:09:03 PM PDT 24 Jul 31 06:09:53 PM PDT 24 17633393592 ps
T104 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1084743410 Jul 31 06:09:07 PM PDT 24 Jul 31 06:09:15 PM PDT 24 534530577 ps
T119 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1496887900 Jul 31 06:09:25 PM PDT 24 Jul 31 06:09:31 PM PDT 24 602833101 ps
T347 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.985863317 Jul 31 06:08:42 PM PDT 24 Jul 31 06:09:04 PM PDT 24 7677318150 ps
T348 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.70259230 Jul 31 06:07:55 PM PDT 24 Jul 31 06:07:57 PM PDT 24 425717780 ps
T349 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.737113649 Jul 31 06:08:12 PM PDT 24 Jul 31 06:08:13 PM PDT 24 39710746 ps
T164 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2853699260 Jul 31 06:08:52 PM PDT 24 Jul 31 06:09:03 PM PDT 24 823945996 ps
T105 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1429912589 Jul 31 06:09:18 PM PDT 24 Jul 31 06:09:25 PM PDT 24 603028877 ps
T350 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2712690792 Jul 31 06:08:52 PM PDT 24 Jul 31 06:08:57 PM PDT 24 5426360791 ps
T65 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.190226304 Jul 31 06:08:24 PM PDT 24 Jul 31 06:08:56 PM PDT 24 18254520410 ps
T351 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2407390113 Jul 31 06:08:34 PM PDT 24 Jul 31 06:09:04 PM PDT 24 10666257348 ps
T352 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3439365805 Jul 31 06:08:33 PM PDT 24 Jul 31 06:08:38 PM PDT 24 211248721 ps
T353 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3611067556 Jul 31 06:07:56 PM PDT 24 Jul 31 06:08:07 PM PDT 24 7622217706 ps
T354 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4076792491 Jul 31 06:09:16 PM PDT 24 Jul 31 06:09:17 PM PDT 24 197537252 ps
T120 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.860301507 Jul 31 06:08:28 PM PDT 24 Jul 31 06:08:32 PM PDT 24 172838119 ps
T162 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1630650193 Jul 31 06:09:08 PM PDT 24 Jul 31 06:09:21 PM PDT 24 2925841747 ps
T355 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2480014033 Jul 31 06:09:08 PM PDT 24 Jul 31 06:09:11 PM PDT 24 1954002172 ps
T356 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3735601853 Jul 31 06:08:15 PM PDT 24 Jul 31 06:08:16 PM PDT 24 37508470 ps
T66 /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3077760114 Jul 31 06:07:48 PM PDT 24 Jul 31 06:10:11 PM PDT 24 46945540326 ps
T357 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2645577403 Jul 31 06:09:22 PM PDT 24 Jul 31 06:09:32 PM PDT 24 16317368714 ps
T358 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4221383716 Jul 31 06:08:59 PM PDT 24 Jul 31 06:09:06 PM PDT 24 296397858 ps
T114 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.496287528 Jul 31 06:09:02 PM PDT 24 Jul 31 06:09:03 PM PDT 24 229871757 ps
T359 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2858946687 Jul 31 06:07:47 PM PDT 24 Jul 31 06:07:53 PM PDT 24 3230018005 ps
T360 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2359294586 Jul 31 06:09:03 PM PDT 24 Jul 31 06:09:07 PM PDT 24 342260039 ps
T361 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.267625895 Jul 31 06:09:01 PM PDT 24 Jul 31 06:09:03 PM PDT 24 89842320 ps
T362 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4108458697 Jul 31 06:07:43 PM PDT 24 Jul 31 06:08:58 PM PDT 24 13917023661 ps
T160 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1088397278 Jul 31 06:09:11 PM PDT 24 Jul 31 06:09:35 PM PDT 24 16057853426 ps
T363 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3737304235 Jul 31 06:08:48 PM PDT 24 Jul 31 06:09:06 PM PDT 24 19858197194 ps
T364 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3482130895 Jul 31 06:07:57 PM PDT 24 Jul 31 06:07:57 PM PDT 24 31435158 ps
T365 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.557782176 Jul 31 06:07:48 PM PDT 24 Jul 31 06:07:55 PM PDT 24 4739209219 ps
T170 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.607940603 Jul 31 06:08:14 PM PDT 24 Jul 31 06:08:23 PM PDT 24 15654951703 ps
T366 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.598515124 Jul 31 06:08:31 PM PDT 24 Jul 31 06:08:44 PM PDT 24 4177952710 ps
T121 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3829255217 Jul 31 06:08:38 PM PDT 24 Jul 31 06:08:43 PM PDT 24 672309628 ps
T115 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1303163088 Jul 31 06:08:22 PM PDT 24 Jul 31 06:08:25 PM PDT 24 370064157 ps
T117 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3887208034 Jul 31 06:08:04 PM PDT 24 Jul 31 06:08:39 PM PDT 24 10219621397 ps
T367 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3586833402 Jul 31 06:09:07 PM PDT 24 Jul 31 06:09:11 PM PDT 24 157370309 ps
T169 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1719106005 Jul 31 06:09:16 PM PDT 24 Jul 31 06:09:34 PM PDT 24 1403075624 ps
T368 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1041613192 Jul 31 06:08:47 PM PDT 24 Jul 31 06:08:56 PM PDT 24 870270421 ps
T116 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.972056067 Jul 31 06:08:02 PM PDT 24 Jul 31 06:08:04 PM PDT 24 107669053 ps
T369 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3659034749 Jul 31 06:07:39 PM PDT 24 Jul 31 06:07:41 PM PDT 24 523043556 ps
T370 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1151814674 Jul 31 06:09:03 PM PDT 24 Jul 31 06:09:04 PM PDT 24 765481938 ps
T371 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3129217982 Jul 31 06:08:18 PM PDT 24 Jul 31 06:08:19 PM PDT 24 124154675 ps
T106 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3321744911 Jul 31 06:07:48 PM PDT 24 Jul 31 06:07:50 PM PDT 24 133752461 ps
T372 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1633287203 Jul 31 06:07:55 PM PDT 24 Jul 31 06:08:29 PM PDT 24 4360673465 ps
T373 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.879147818 Jul 31 06:09:26 PM PDT 24 Jul 31 06:09:29 PM PDT 24 314537771 ps
T374 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.703161646 Jul 31 06:09:18 PM PDT 24 Jul 31 06:09:20 PM PDT 24 172221455 ps
T375 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4251846623 Jul 31 06:08:38 PM PDT 24 Jul 31 06:08:52 PM PDT 24 1804628320 ps
T376 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3907175820 Jul 31 06:08:23 PM PDT 24 Jul 31 06:08:26 PM PDT 24 88731790 ps
T377 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.354601050 Jul 31 06:09:12 PM PDT 24 Jul 31 06:09:17 PM PDT 24 372767855 ps
T378 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2081750998 Jul 31 06:09:19 PM PDT 24 Jul 31 06:09:23 PM PDT 24 278082844 ps
T98 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2647792201 Jul 31 06:07:49 PM PDT 24 Jul 31 06:07:56 PM PDT 24 2218757447 ps
T379 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2691280420 Jul 31 06:09:02 PM PDT 24 Jul 31 06:09:05 PM PDT 24 458255100 ps
T380 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4122872053 Jul 31 06:08:39 PM PDT 24 Jul 31 06:08:41 PM PDT 24 2176718592 ps
T381 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.4029927507 Jul 31 06:09:24 PM PDT 24 Jul 31 06:09:29 PM PDT 24 333773102 ps
T163 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3075289394 Jul 31 06:08:22 PM PDT 24 Jul 31 06:08:33 PM PDT 24 1236600461 ps
T382 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1273284416 Jul 31 06:08:57 PM PDT 24 Jul 31 06:09:00 PM PDT 24 224070619 ps
T107 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.805163866 Jul 31 06:08:48 PM PDT 24 Jul 31 06:08:55 PM PDT 24 1571208100 ps
T383 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.4211578166 Jul 31 06:07:44 PM PDT 24 Jul 31 06:07:46 PM PDT 24 146907041 ps
T384 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4070134116 Jul 31 06:08:40 PM PDT 24 Jul 31 06:08:52 PM PDT 24 1576271154 ps
T385 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3110315439 Jul 31 06:08:02 PM PDT 24 Jul 31 06:08:06 PM PDT 24 74701469 ps
T386 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.513995783 Jul 31 06:08:00 PM PDT 24 Jul 31 06:08:00 PM PDT 24 601281698 ps
T387 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3782410118 Jul 31 06:08:51 PM PDT 24 Jul 31 06:08:52 PM PDT 24 891949676 ps
T388 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2440064087 Jul 31 06:08:18 PM PDT 24 Jul 31 06:08:19 PM PDT 24 168157460 ps
T389 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3304699171 Jul 31 06:07:59 PM PDT 24 Jul 31 06:08:03 PM PDT 24 200949614 ps
T171 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1775374512 Jul 31 06:08:44 PM PDT 24 Jul 31 06:11:54 PM PDT 24 42536934869 ps
T390 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.288630331 Jul 31 06:07:48 PM PDT 24 Jul 31 06:08:47 PM PDT 24 20840356322 ps
T391 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.749452605 Jul 31 06:08:57 PM PDT 24 Jul 31 06:08:58 PM PDT 24 342829901 ps
T392 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3734718471 Jul 31 06:09:17 PM PDT 24 Jul 31 06:09:21 PM PDT 24 2600510994 ps
T393 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.697600037 Jul 31 06:08:46 PM PDT 24 Jul 31 06:09:02 PM PDT 24 13810541500 ps
T394 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2226504225 Jul 31 06:08:41 PM PDT 24 Jul 31 06:09:50 PM PDT 24 21685303172 ps
T395 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1401902063 Jul 31 06:08:52 PM PDT 24 Jul 31 06:08:54 PM PDT 24 363092278 ps
T396 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4288696121 Jul 31 06:08:14 PM PDT 24 Jul 31 06:08:39 PM PDT 24 11384497139 ps
T108 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.639791652 Jul 31 06:08:59 PM PDT 24 Jul 31 06:09:03 PM PDT 24 187013893 ps
T397 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2211814238 Jul 31 06:08:22 PM PDT 24 Jul 31 06:08:22 PM PDT 24 165631609 ps
T398 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1476724633 Jul 31 06:09:13 PM PDT 24 Jul 31 06:09:21 PM PDT 24 438468914 ps
T399 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2043837955 Jul 31 06:09:21 PM PDT 24 Jul 31 06:09:47 PM PDT 24 17440974859 ps
T109 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3191255684 Jul 31 06:08:13 PM PDT 24 Jul 31 06:08:16 PM PDT 24 127170114 ps
T400 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1920875214 Jul 31 06:08:33 PM PDT 24 Jul 31 06:09:54 PM PDT 24 33514714256 ps
T401 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3588424613 Jul 31 06:08:39 PM PDT 24 Jul 31 06:08:41 PM PDT 24 87911015 ps
T402 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2601556377 Jul 31 06:08:14 PM PDT 24 Jul 31 06:08:15 PM PDT 24 1381131491 ps
T403 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3537397681 Jul 31 06:09:22 PM PDT 24 Jul 31 06:09:25 PM PDT 24 175669931 ps
T404 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1528003421 Jul 31 06:07:48 PM PDT 24 Jul 31 06:09:22 PM PDT 24 68773985464 ps
T405 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2608353356 Jul 31 06:08:14 PM PDT 24 Jul 31 06:08:18 PM PDT 24 223932602 ps
T406 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1870583682 Jul 31 06:07:49 PM PDT 24 Jul 31 06:07:51 PM PDT 24 191455286 ps
T407 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.996939845 Jul 31 06:07:57 PM PDT 24 Jul 31 06:08:06 PM PDT 24 9597876941 ps
T408 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3735235460 Jul 31 06:07:53 PM PDT 24 Jul 31 06:07:57 PM PDT 24 2106451134 ps
T409 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3733001003 Jul 31 06:07:56 PM PDT 24 Jul 31 06:07:59 PM PDT 24 2255969801 ps
T410 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2729635621 Jul 31 06:08:47 PM PDT 24 Jul 31 06:08:50 PM PDT 24 496173269 ps
T411 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.584765380 Jul 31 06:07:58 PM PDT 24 Jul 31 06:07:59 PM PDT 24 154409678 ps
T110 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1049431748 Jul 31 06:07:48 PM PDT 24 Jul 31 06:08:20 PM PDT 24 1837101736 ps
T412 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3171891339 Jul 31 06:09:07 PM PDT 24 Jul 31 06:09:09 PM PDT 24 378096589 ps
T413 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3995178728 Jul 31 06:08:19 PM PDT 24 Jul 31 06:08:23 PM PDT 24 446928956 ps
T111 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.680176917 Jul 31 06:08:37 PM PDT 24 Jul 31 06:08:44 PM PDT 24 2087801098 ps
T414 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1105877652 Jul 31 06:08:32 PM PDT 24 Jul 31 06:08:36 PM PDT 24 178330631 ps
T415 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1357300991 Jul 31 06:08:38 PM PDT 24 Jul 31 06:08:39 PM PDT 24 439572229 ps
T416 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.382642727 Jul 31 06:09:21 PM PDT 24 Jul 31 06:09:24 PM PDT 24 233613224 ps
T417 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2387073494 Jul 31 06:08:47 PM PDT 24 Jul 31 06:09:27 PM PDT 24 55145815088 ps
T418 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2577537781 Jul 31 06:09:05 PM PDT 24 Jul 31 06:09:06 PM PDT 24 380026578 ps
T419 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2334109959 Jul 31 06:09:06 PM PDT 24 Jul 31 06:09:08 PM PDT 24 252049627 ps
T420 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.823204694 Jul 31 06:07:54 PM PDT 24 Jul 31 06:08:03 PM PDT 24 548822173 ps
T421 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2370045541 Jul 31 06:08:21 PM PDT 24 Jul 31 06:08:25 PM PDT 24 629744389 ps
T422 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2578264231 Jul 31 06:07:48 PM PDT 24 Jul 31 06:09:00 PM PDT 24 6657882336 ps
T423 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2600887380 Jul 31 06:08:01 PM PDT 24 Jul 31 06:08:10 PM PDT 24 5925196590 ps
T424 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.272816943 Jul 31 06:08:47 PM PDT 24 Jul 31 06:08:48 PM PDT 24 267150557 ps
T425 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1187010618 Jul 31 06:08:01 PM PDT 24 Jul 31 06:08:02 PM PDT 24 91250739 ps
T426 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2105639290 Jul 31 06:09:13 PM PDT 24 Jul 31 06:09:16 PM PDT 24 528947985 ps
T427 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1778315759 Jul 31 06:08:28 PM PDT 24 Jul 31 06:08:33 PM PDT 24 470419279 ps
T428 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.660220183 Jul 31 06:08:50 PM PDT 24 Jul 31 06:08:52 PM PDT 24 326798058 ps
T429 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1336942060 Jul 31 06:08:23 PM PDT 24 Jul 31 06:08:29 PM PDT 24 2713681694 ps
T430 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1921317939 Jul 31 06:08:27 PM PDT 24 Jul 31 06:08:28 PM PDT 24 81017519 ps
T431 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3147093127 Jul 31 06:09:04 PM PDT 24 Jul 31 06:09:13 PM PDT 24 6712347897 ps
T432 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.707975996 Jul 31 06:08:36 PM PDT 24 Jul 31 06:08:40 PM PDT 24 304642521 ps
T433 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2519781537 Jul 31 06:08:43 PM PDT 24 Jul 31 06:08:45 PM PDT 24 245077577 ps
T434 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1913248175 Jul 31 06:09:12 PM PDT 24 Jul 31 06:09:17 PM PDT 24 760480323 ps
T99 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2476320540 Jul 31 06:08:24 PM PDT 24 Jul 31 06:08:49 PM PDT 24 9677393635 ps
T435 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3687595631 Jul 31 06:08:57 PM PDT 24 Jul 31 06:09:01 PM PDT 24 378826601 ps
T436 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.469457240 Jul 31 06:07:47 PM PDT 24 Jul 31 06:07:49 PM PDT 24 1376609731 ps
T437 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.944108434 Jul 31 06:07:57 PM PDT 24 Jul 31 06:07:59 PM PDT 24 127064878 ps
T438 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.691765363 Jul 31 06:08:47 PM PDT 24 Jul 31 06:09:04 PM PDT 24 6050330502 ps
T439 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3922963740 Jul 31 06:07:48 PM PDT 24 Jul 31 06:07:51 PM PDT 24 206667944 ps
T165 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3991039804 Jul 31 06:09:02 PM PDT 24 Jul 31 06:09:13 PM PDT 24 1865830083 ps
T440 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2210039078 Jul 31 06:09:17 PM PDT 24 Jul 31 06:09:19 PM PDT 24 125924773 ps
T441 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1453723204 Jul 31 06:09:12 PM PDT 24 Jul 31 06:09:13 PM PDT 24 36936236 ps
T442 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1733399711 Jul 31 06:07:53 PM PDT 24 Jul 31 06:07:54 PM PDT 24 190345842 ps
T443 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3854252930 Jul 31 06:09:28 PM PDT 24 Jul 31 06:09:29 PM PDT 24 100451248 ps
T444 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3205633311 Jul 31 06:08:01 PM PDT 24 Jul 31 06:08:08 PM PDT 24 1037610602 ps
T166 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2369132566 Jul 31 06:08:32 PM PDT 24 Jul 31 06:08:52 PM PDT 24 1940248721 ps
T445 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2699555120 Jul 31 06:08:12 PM PDT 24 Jul 31 06:08:17 PM PDT 24 4800190538 ps
T446 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3694019024 Jul 31 06:08:33 PM PDT 24 Jul 31 06:08:44 PM PDT 24 1332998741 ps
T447 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2462759413 Jul 31 06:08:48 PM PDT 24 Jul 31 06:09:12 PM PDT 24 6082137533 ps
T448 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1983416262 Jul 31 06:08:59 PM PDT 24 Jul 31 06:09:07 PM PDT 24 2605772328 ps
T449 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2363051488 Jul 31 06:08:37 PM PDT 24 Jul 31 06:08:41 PM PDT 24 88460516 ps
T450 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.4021288871 Jul 31 06:07:53 PM PDT 24 Jul 31 06:07:55 PM PDT 24 142965465 ps
T451 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.504098336 Jul 31 06:08:47 PM PDT 24 Jul 31 06:08:51 PM PDT 24 480502912 ps
T452 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2068947209 Jul 31 06:09:06 PM PDT 24 Jul 31 06:09:07 PM PDT 24 443627227 ps
T453 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2823264153 Jul 31 06:08:27 PM PDT 24 Jul 31 06:12:21 PM PDT 24 30349336378 ps
T454 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3258228172 Jul 31 06:09:21 PM PDT 24 Jul 31 06:09:24 PM PDT 24 464057841 ps
T455 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1386961875 Jul 31 06:09:19 PM PDT 24 Jul 31 06:09:24 PM PDT 24 439054238 ps
T456 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2840466194 Jul 31 06:08:25 PM PDT 24 Jul 31 06:08:31 PM PDT 24 3123533535 ps
T457 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2419123679 Jul 31 06:08:01 PM PDT 24 Jul 31 06:09:37 PM PDT 24 58208000528 ps
T458 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3054798430 Jul 31 06:07:56 PM PDT 24 Jul 31 06:09:24 PM PDT 24 52991848039 ps
T459 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.86519666 Jul 31 06:09:24 PM PDT 24 Jul 31 06:09:26 PM PDT 24 704511695 ps
T460 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2339833969 Jul 31 06:08:50 PM PDT 24 Jul 31 06:08:54 PM PDT 24 808837481 ps
T461 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3479684716 Jul 31 06:09:27 PM PDT 24 Jul 31 06:09:31 PM PDT 24 262984669 ps
T462 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3662748958 Jul 31 06:08:52 PM PDT 24 Jul 31 06:08:54 PM PDT 24 51051296 ps
T463 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2475689288 Jul 31 06:08:37 PM PDT 24 Jul 31 06:08:41 PM PDT 24 176225073 ps
T167 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2900393676 Jul 31 06:07:56 PM PDT 24 Jul 31 06:08:11 PM PDT 24 2412679099 ps
T464 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1376224949 Jul 31 06:08:18 PM PDT 24 Jul 31 06:08:25 PM PDT 24 7755155721 ps
T465 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2725988050 Jul 31 06:08:19 PM PDT 24 Jul 31 06:08:27 PM PDT 24 1016895469 ps

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.815248774
Short name T5
Test name
Test status
Simulation time 131924742186 ps
CPU time 1065.74 seconds
Started Jul 31 06:35:40 PM PDT 24
Finished Jul 31 06:53:26 PM PDT 24
Peak memory 240900 kb
Host smart-2463734c-c820-4b4a-8b7a-8101a562a3de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815248774 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.815248774
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1321261635
Short name T14
Test name
Test status
Simulation time 8264088423 ps
CPU time 6.61 seconds
Started Jul 31 06:36:20 PM PDT 24
Finished Jul 31 06:36:26 PM PDT 24
Peak memory 213924 kb
Host smart-81ebfbe0-a576-44fa-9417-2fc902a0802d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321261635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1321261635
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.910071391
Short name T16
Test name
Test status
Simulation time 9457404544 ps
CPU time 26.74 seconds
Started Jul 31 06:36:23 PM PDT 24
Finished Jul 31 06:36:49 PM PDT 24
Peak memory 213812 kb
Host smart-e3447645-a745-4b91-9726-9f44dde93467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910071391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.910071391
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1829441078
Short name T64
Test name
Test status
Simulation time 9553215915 ps
CPU time 7.74 seconds
Started Jul 31 06:33:53 PM PDT 24
Finished Jul 31 06:34:00 PM PDT 24
Peak memory 205544 kb
Host smart-b27c3ab2-0b34-48ec-a995-8f02347380c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829441078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1829441078
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.1532012820
Short name T84
Test name
Test status
Simulation time 2758223417 ps
CPU time 21.6 seconds
Started Jul 31 06:08:02 PM PDT 24
Finished Jul 31 06:08:24 PM PDT 24
Peak memory 214032 kb
Host smart-c62a5272-6595-4dc0-bab8-04e1db3a0edb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532012820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.1532012820
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.786194206
Short name T288
Test name
Test status
Simulation time 16352439724 ps
CPU time 15.93 seconds
Started Jul 31 06:36:31 PM PDT 24
Finished Jul 31 06:36:47 PM PDT 24
Peak memory 222144 kb
Host smart-bd8c9aa2-449f-4e0e-b570-abae3b6b84df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786194206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.786194206
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all_with_rand_reset.4009045993
Short name T11
Test name
Test status
Simulation time 517388527334 ps
CPU time 994.25 seconds
Started Jul 31 06:35:56 PM PDT 24
Finished Jul 31 06:52:30 PM PDT 24
Peak memory 237032 kb
Host smart-15cfcf46-e4e7-4c28-8268-5d80727ff63e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009045993 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all_with_rand_reset.4009045993
Directory /workspace/6.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.460408167
Short name T141
Test name
Test status
Simulation time 5522864838 ps
CPU time 16.15 seconds
Started Jul 31 06:36:09 PM PDT 24
Finished Jul 31 06:36:25 PM PDT 24
Peak memory 213944 kb
Host smart-4bedb04e-4bc1-484f-897b-67b093685935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460408167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.460408167
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.1842339227
Short name T57
Test name
Test status
Simulation time 683382687 ps
CPU time 2.97 seconds
Started Jul 31 06:35:40 PM PDT 24
Finished Jul 31 06:35:43 PM PDT 24
Peak memory 229576 kb
Host smart-86ed545d-7446-44fa-9641-c9e3edc24ab6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842339227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.1842339227
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.2493595974
Short name T62
Test name
Test status
Simulation time 727010015 ps
CPU time 1.02 seconds
Started Jul 31 06:34:36 PM PDT 24
Finished Jul 31 06:34:38 PM PDT 24
Peak memory 205304 kb
Host smart-51dc0e6d-5173-451b-854a-72db56f1cd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493595974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.2493595974
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.1064617794
Short name T59
Test name
Test status
Simulation time 60184302375 ps
CPU time 353.12 seconds
Started Jul 31 06:35:39 PM PDT 24
Finished Jul 31 06:41:32 PM PDT 24
Peak memory 223812 kb
Host smart-05bf8ca0-ec38-429c-8527-0bc64c11f9f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064617794 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.1064617794
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.2082499941
Short name T154
Test name
Test status
Simulation time 4150950875 ps
CPU time 10.88 seconds
Started Jul 31 06:37:39 PM PDT 24
Finished Jul 31 06:37:50 PM PDT 24
Peak memory 213800 kb
Host smart-31ead3e4-7ed9-48a7-9215-6d705a3e5236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082499941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.2082499941
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3953252864
Short name T102
Test name
Test status
Simulation time 225371856 ps
CPU time 2.37 seconds
Started Jul 31 06:08:00 PM PDT 24
Finished Jul 31 06:08:02 PM PDT 24
Peak memory 213884 kb
Host smart-33dd10f2-0361-441a-8fb8-c74a25c65266
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953252864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3953252864
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.3262101209
Short name T63
Test name
Test status
Simulation time 163815829 ps
CPU time 1.16 seconds
Started Jul 31 06:35:13 PM PDT 24
Finished Jul 31 06:35:14 PM PDT 24
Peak memory 205264 kb
Host smart-f369155a-f7f1-43c4-897f-62836bb05f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262101209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.3262101209
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.642131837
Short name T138
Test name
Test status
Simulation time 627626317 ps
CPU time 2.56 seconds
Started Jul 31 06:34:29 PM PDT 24
Finished Jul 31 06:34:31 PM PDT 24
Peak memory 205448 kb
Host smart-da92717a-2f3e-4fb0-a225-cbf81395bb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642131837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.642131837
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2369132566
Short name T166
Test name
Test status
Simulation time 1940248721 ps
CPU time 20.51 seconds
Started Jul 31 06:08:32 PM PDT 24
Finished Jul 31 06:08:52 PM PDT 24
Peak memory 213860 kb
Host smart-cef60bfb-c465-4624-b222-853d0c2c00d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369132566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2369132566
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2364658161
Short name T73
Test name
Test status
Simulation time 78907542 ps
CPU time 0.87 seconds
Started Jul 31 06:37:25 PM PDT 24
Finished Jul 31 06:37:26 PM PDT 24
Peak memory 205264 kb
Host smart-d49db062-651b-49b2-b141-c3850ef488c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364658161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2364658161
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.3239616
Short name T42
Test name
Test status
Simulation time 245634928 ps
CPU time 0.86 seconds
Started Jul 31 06:35:08 PM PDT 24
Finished Jul 31 06:35:09 PM PDT 24
Peak memory 213512 kb
Host smart-d5814323-5f6a-4012-8ed6-733d15901b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.3239616
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2268853648
Short name T19
Test name
Test status
Simulation time 113984456 ps
CPU time 0.99 seconds
Started Jul 31 06:34:10 PM PDT 24
Finished Jul 31 06:34:11 PM PDT 24
Peak memory 205328 kb
Host smart-d6613192-f106-4617-ae8f-92437db2b98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268853648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2268853648
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.837002477
Short name T9
Test name
Test status
Simulation time 5852330414 ps
CPU time 6.92 seconds
Started Jul 31 06:37:38 PM PDT 24
Finished Jul 31 06:37:46 PM PDT 24
Peak memory 213804 kb
Host smart-46547918-a24b-4ad2-8c1d-7858c17277d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837002477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.837002477
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.1349357193
Short name T86
Test name
Test status
Simulation time 668850249 ps
CPU time 7.25 seconds
Started Jul 31 06:09:01 PM PDT 24
Finished Jul 31 06:09:08 PM PDT 24
Peak memory 205676 kb
Host smart-5389e440-9e33-41a4-bbb7-fa5965df2310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349357193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.1349357193
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.2246476015
Short name T31
Test name
Test status
Simulation time 70672226 ps
CPU time 0.72 seconds
Started Jul 31 06:34:37 PM PDT 24
Finished Jul 31 06:34:37 PM PDT 24
Peak memory 205272 kb
Host smart-eb6d2db6-a683-4008-b85f-cdd19b2b58b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246476015 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.2246476015
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3077760114
Short name T66
Test name
Test status
Simulation time 46945540326 ps
CPU time 142.65 seconds
Started Jul 31 06:07:48 PM PDT 24
Finished Jul 31 06:10:11 PM PDT 24
Peak memory 222320 kb
Host smart-25ec04be-9b91-4879-8f42-8e3f8858b18e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077760114 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3077760114
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1432474070
Short name T40
Test name
Test status
Simulation time 155094727 ps
CPU time 0.81 seconds
Started Jul 31 06:35:01 PM PDT 24
Finished Jul 31 06:35:02 PM PDT 24
Peak memory 205256 kb
Host smart-339d08a8-029b-453b-8313-0b514fdbbc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432474070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1432474070
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.3463091787
Short name T147
Test name
Test status
Simulation time 1129775014 ps
CPU time 2.48 seconds
Started Jul 31 06:37:21 PM PDT 24
Finished Jul 31 06:37:24 PM PDT 24
Peak memory 205456 kb
Host smart-6617afcf-4b90-4b83-ae66-867f46292000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463091787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.3463091787
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1288905795
Short name T224
Test name
Test status
Simulation time 5362925174 ps
CPU time 4.89 seconds
Started Jul 31 06:36:39 PM PDT 24
Finished Jul 31 06:36:44 PM PDT 24
Peak memory 213996 kb
Host smart-a7df1f9e-2c63-442f-a16a-f3868247bc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288905795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1288905795
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3449114468
Short name T318
Test name
Test status
Simulation time 229630940 ps
CPU time 0.81 seconds
Started Jul 31 06:07:49 PM PDT 24
Finished Jul 31 06:07:50 PM PDT 24
Peak memory 205240 kb
Host smart-4a3db4cc-9175-41fc-863d-b23b08e90828
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449114468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
449114468
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.3694599737
Short name T6
Test name
Test status
Simulation time 273043421 ps
CPU time 0.9 seconds
Started Jul 31 06:34:32 PM PDT 24
Finished Jul 31 06:34:33 PM PDT 24
Peak memory 205208 kb
Host smart-e6a76666-89b7-42be-ab13-07c1f23d50e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694599737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.3694599737
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2647792201
Short name T98
Test name
Test status
Simulation time 2218757447 ps
CPU time 7.06 seconds
Started Jul 31 06:07:49 PM PDT 24
Finished Jul 31 06:07:56 PM PDT 24
Peak memory 205664 kb
Host smart-b0923fef-da63-4769-9e97-e56cc8761cb2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647792201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2647792201
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3991039804
Short name T165
Test name
Test status
Simulation time 1865830083 ps
CPU time 10.78 seconds
Started Jul 31 06:09:02 PM PDT 24
Finished Jul 31 06:09:13 PM PDT 24
Peak memory 213820 kb
Host smart-a1e1cd6a-023f-4b8f-be48-e6361b0fdad2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991039804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
991039804
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3281696009
Short name T225
Test name
Test status
Simulation time 5950067989 ps
CPU time 7.77 seconds
Started Jul 31 06:33:57 PM PDT 24
Finished Jul 31 06:34:04 PM PDT 24
Peak memory 213932 kb
Host smart-051e54c2-c8ae-44c5-bdcc-c485187a6d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281696009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3281696009
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3926013499
Short name T155
Test name
Test status
Simulation time 4867771548 ps
CPU time 8.2 seconds
Started Jul 31 06:36:45 PM PDT 24
Finished Jul 31 06:36:53 PM PDT 24
Peak memory 213952 kb
Host smart-6428828e-2117-4afb-8e94-e84587ea07c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926013499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3926013499
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3321744911
Short name T106
Test name
Test status
Simulation time 133752461 ps
CPU time 1.82 seconds
Started Jul 31 06:07:48 PM PDT 24
Finished Jul 31 06:07:50 PM PDT 24
Peak memory 213804 kb
Host smart-e0faeda9-6d2e-4311-8a28-0d8a7d4df906
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321744911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3321744911
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4108458697
Short name T362
Test name
Test status
Simulation time 13917023661 ps
CPU time 74.37 seconds
Started Jul 31 06:07:43 PM PDT 24
Finished Jul 31 06:08:58 PM PDT 24
Peak memory 213940 kb
Host smart-11e2a677-9036-45e6-9c02-d3abe42f806a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108458697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.4108458697
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2578264231
Short name T422
Test name
Test status
Simulation time 6657882336 ps
CPU time 72.61 seconds
Started Jul 31 06:07:48 PM PDT 24
Finished Jul 31 06:09:00 PM PDT 24
Peak memory 213944 kb
Host smart-523a204c-9a66-4fdb-a6d1-ccaafb0519cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578264231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2578264231
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.4021288871
Short name T450
Test name
Test status
Simulation time 142965465 ps
CPU time 2.33 seconds
Started Jul 31 06:07:53 PM PDT 24
Finished Jul 31 06:07:55 PM PDT 24
Peak memory 217556 kb
Host smart-c4e7e0df-b430-4e09-a985-a04b92245112
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021288871 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.4021288871
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.1870583682
Short name T406
Test name
Test status
Simulation time 191455286 ps
CPU time 1.58 seconds
Started Jul 31 06:07:49 PM PDT 24
Finished Jul 31 06:07:51 PM PDT 24
Peak memory 213744 kb
Host smart-bb2a7bb6-eba6-475c-ae8f-b3abf25aaaf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870583682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.1870583682
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1528003421
Short name T404
Test name
Test status
Simulation time 68773985464 ps
CPU time 93.86 seconds
Started Jul 31 06:07:48 PM PDT 24
Finished Jul 31 06:09:22 PM PDT 24
Peak memory 205600 kb
Host smart-74299aba-f0f7-4cf9-842a-e016a93ffcaf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528003421 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1528003421
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3068457307
Short name T336
Test name
Test status
Simulation time 34182456370 ps
CPU time 11.66 seconds
Started Jul 31 06:07:50 PM PDT 24
Finished Jul 31 06:08:01 PM PDT 24
Peak memory 205620 kb
Host smart-18892476-ee3b-417f-9042-e0a91ce19781
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068457307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.3068457307
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.557782176
Short name T365
Test name
Test status
Simulation time 4739209219 ps
CPU time 7.77 seconds
Started Jul 31 06:07:48 PM PDT 24
Finished Jul 31 06:07:55 PM PDT 24
Peak memory 205600 kb
Host smart-ed30a713-abba-47d9-be56-b31a54a7c7d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557782176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.557782176
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.469457240
Short name T436
Test name
Test status
Simulation time 1376609731 ps
CPU time 1.6 seconds
Started Jul 31 06:07:47 PM PDT 24
Finished Jul 31 06:07:49 PM PDT 24
Peak memory 205300 kb
Host smart-aebe7e86-95e5-4843-910f-9a3bc3769fc8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469457240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.469457240
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.2858946687
Short name T359
Test name
Test status
Simulation time 3230018005 ps
CPU time 5.77 seconds
Started Jul 31 06:07:47 PM PDT 24
Finished Jul 31 06:07:53 PM PDT 24
Peak memory 205596 kb
Host smart-16e0a7cc-ee64-43be-9778-cad239d9177a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858946687 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.2858946687
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3659034749
Short name T369
Test name
Test status
Simulation time 523043556 ps
CPU time 1.31 seconds
Started Jul 31 06:07:39 PM PDT 24
Finished Jul 31 06:07:41 PM PDT 24
Peak memory 205388 kb
Host smart-6a0ada06-837e-4cd8-b8b7-f80c768b5ba9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659034749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3659034749
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1893894574
Short name T313
Test name
Test status
Simulation time 162239671 ps
CPU time 0.75 seconds
Started Jul 31 06:07:51 PM PDT 24
Finished Jul 31 06:07:52 PM PDT 24
Peak memory 205360 kb
Host smart-48bde760-9c8c-4324-bb80-c4a9733c66ad
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893894574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1893894574
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.4211578166
Short name T383
Test name
Test status
Simulation time 146907041 ps
CPU time 1.03 seconds
Started Jul 31 06:07:44 PM PDT 24
Finished Jul 31 06:07:46 PM PDT 24
Peak memory 205336 kb
Host smart-2ad695a9-2bed-4a5f-a8d3-6157af0ed5b3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211578166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.4211578166
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2667221034
Short name T118
Test name
Test status
Simulation time 675182699 ps
CPU time 4.38 seconds
Started Jul 31 06:07:57 PM PDT 24
Finished Jul 31 06:08:02 PM PDT 24
Peak memory 205644 kb
Host smart-6190d11d-155c-4603-a379-24f21cc04494
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667221034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2667221034
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.3922963740
Short name T439
Test name
Test status
Simulation time 206667944 ps
CPU time 2.53 seconds
Started Jul 31 06:07:48 PM PDT 24
Finished Jul 31 06:07:51 PM PDT 24
Peak memory 213876 kb
Host smart-cf0ab930-f71e-437c-ac75-ff86d51f922c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922963740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.3922963740
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.1752662924
Short name T83
Test name
Test status
Simulation time 4866000184 ps
CPU time 21.19 seconds
Started Jul 31 06:07:48 PM PDT 24
Finished Jul 31 06:08:09 PM PDT 24
Peak memory 213980 kb
Host smart-f1014815-0478-4b21-91ac-a5492c556111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752662924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.1752662924
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.1049431748
Short name T110
Test name
Test status
Simulation time 1837101736 ps
CPU time 32.15 seconds
Started Jul 31 06:07:48 PM PDT 24
Finished Jul 31 06:08:20 PM PDT 24
Peak memory 205640 kb
Host smart-c3f3a04a-fa19-4ed5-a4cb-e13f67eee64f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049431748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.1049431748
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2166028343
Short name T90
Test name
Test status
Simulation time 5251088343 ps
CPU time 53.23 seconds
Started Jul 31 06:07:54 PM PDT 24
Finished Jul 31 06:08:47 PM PDT 24
Peak memory 213940 kb
Host smart-0cc479a8-e91b-4ab8-8fea-96970fdf18ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166028343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2166028343
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2036079922
Short name T89
Test name
Test status
Simulation time 250126337 ps
CPU time 1.66 seconds
Started Jul 31 06:07:58 PM PDT 24
Finished Jul 31 06:08:00 PM PDT 24
Peak memory 213788 kb
Host smart-c5964503-1537-46ec-9bde-e50f4e088e34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036079922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2036079922
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3304699171
Short name T389
Test name
Test status
Simulation time 200949614 ps
CPU time 4.1 seconds
Started Jul 31 06:07:59 PM PDT 24
Finished Jul 31 06:08:03 PM PDT 24
Peak memory 221840 kb
Host smart-ea21fd1d-f21d-4f21-b633-d089c33ae592
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304699171 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3304699171
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.944108434
Short name T437
Test name
Test status
Simulation time 127064878 ps
CPU time 2.42 seconds
Started Jul 31 06:07:57 PM PDT 24
Finished Jul 31 06:07:59 PM PDT 24
Peak memory 213744 kb
Host smart-91243215-8d0d-4b35-9821-1e9dbb6fbabe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944108434 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.944108434
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.288630331
Short name T390
Test name
Test status
Simulation time 20840356322 ps
CPU time 58.08 seconds
Started Jul 31 06:07:48 PM PDT 24
Finished Jul 31 06:08:47 PM PDT 24
Peak memory 205636 kb
Host smart-5df591c2-b1f6-4f7a-8d00-c9086698d7ac
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288630331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_aliasing.288630331
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1294532472
Short name T345
Test name
Test status
Simulation time 4291607854 ps
CPU time 4.16 seconds
Started Jul 31 06:07:53 PM PDT 24
Finished Jul 31 06:07:58 PM PDT 24
Peak memory 205584 kb
Host smart-b548aa51-ba8c-4108-a5fa-7231fcea750d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294532472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
rv_dm_jtag_dmi_csr_bit_bash.1294532472
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3733001003
Short name T409
Test name
Test status
Simulation time 2255969801 ps
CPU time 2.68 seconds
Started Jul 31 06:07:56 PM PDT 24
Finished Jul 31 06:07:59 PM PDT 24
Peak memory 205712 kb
Host smart-b6546fd4-8ef1-4287-9cb4-5ab406764940
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733001003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3733001003
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3735235460
Short name T408
Test name
Test status
Simulation time 2106451134 ps
CPU time 4.12 seconds
Started Jul 31 06:07:53 PM PDT 24
Finished Jul 31 06:07:57 PM PDT 24
Peak memory 205476 kb
Host smart-568c7f72-3cff-45f7-a2d4-d29b13bf174a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735235460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
735235460
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.3106724407
Short name T333
Test name
Test status
Simulation time 388470782 ps
CPU time 1.49 seconds
Started Jul 31 06:07:52 PM PDT 24
Finished Jul 31 06:07:54 PM PDT 24
Peak memory 205340 kb
Host smart-70db5acf-1ec2-4919-ad33-b12227eca310
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106724407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.3106724407
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.996939845
Short name T407
Test name
Test status
Simulation time 9597876941 ps
CPU time 8.55 seconds
Started Jul 31 06:07:57 PM PDT 24
Finished Jul 31 06:08:06 PM PDT 24
Peak memory 205572 kb
Host smart-908e97f4-aa0e-4644-9a47-48a365553e5b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996939845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.996939845
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.1733399711
Short name T442
Test name
Test status
Simulation time 190345842 ps
CPU time 1.1 seconds
Started Jul 31 06:07:53 PM PDT 24
Finished Jul 31 06:07:54 PM PDT 24
Peak memory 205372 kb
Host smart-325c417b-f064-443a-a69d-faf6ab179145
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733399711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.1733399711
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.584765380
Short name T411
Test name
Test status
Simulation time 154409678 ps
CPU time 1.07 seconds
Started Jul 31 06:07:58 PM PDT 24
Finished Jul 31 06:07:59 PM PDT 24
Peak memory 205296 kb
Host smart-30c8be68-0b54-40ab-96b7-64a148463c4f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584765380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.584765380
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3482130895
Short name T364
Test name
Test status
Simulation time 31435158 ps
CPU time 0.74 seconds
Started Jul 31 06:07:57 PM PDT 24
Finished Jul 31 06:07:57 PM PDT 24
Peak memory 205412 kb
Host smart-68da4c25-3cf5-4bc8-93b6-cca23bd708b5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482130895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3482130895
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.366033826
Short name T315
Test name
Test status
Simulation time 119823131 ps
CPU time 0.74 seconds
Started Jul 31 06:07:56 PM PDT 24
Finished Jul 31 06:07:57 PM PDT 24
Peak memory 205308 kb
Host smart-95dcea53-092f-4ae6-b988-e59b262964aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366033826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.366033826
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.823204694
Short name T420
Test name
Test status
Simulation time 548822173 ps
CPU time 8.54 seconds
Started Jul 31 06:07:54 PM PDT 24
Finished Jul 31 06:08:03 PM PDT 24
Peak memory 205648 kb
Host smart-6a9ebbe4-7995-4b12-b427-c66f47ba903c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823204694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_c
sr_outstanding.823204694
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3054798430
Short name T458
Test name
Test status
Simulation time 52991848039 ps
CPU time 87.52 seconds
Started Jul 31 06:07:56 PM PDT 24
Finished Jul 31 06:09:24 PM PDT 24
Peak memory 222348 kb
Host smart-41f81af0-7fd1-4e6e-8d40-4722ba965825
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054798430 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3054798430
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1644433869
Short name T338
Test name
Test status
Simulation time 258541475 ps
CPU time 5.3 seconds
Started Jul 31 06:08:01 PM PDT 24
Finished Jul 31 06:08:06 PM PDT 24
Peak memory 213900 kb
Host smart-f5d96539-dd23-4cd2-9816-63e16f9cee16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644433869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1644433869
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2900393676
Short name T167
Test name
Test status
Simulation time 2412679099 ps
CPU time 14.91 seconds
Started Jul 31 06:07:56 PM PDT 24
Finished Jul 31 06:08:11 PM PDT 24
Peak memory 213948 kb
Host smart-5aac4080-8d52-4f42-ae50-cc6ad196fab0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900393676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2900393676
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2564833679
Short name T82
Test name
Test status
Simulation time 254533538 ps
CPU time 4.94 seconds
Started Jul 31 06:08:50 PM PDT 24
Finished Jul 31 06:08:55 PM PDT 24
Peak memory 222092 kb
Host smart-8185d9b6-0c9a-4273-b6c1-75388e977d57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564833679 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2564833679
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3662748958
Short name T462
Test name
Test status
Simulation time 51051296 ps
CPU time 2.03 seconds
Started Jul 31 06:08:52 PM PDT 24
Finished Jul 31 06:08:54 PM PDT 24
Peak memory 213772 kb
Host smart-7663cfd5-dea8-4b0e-85f1-7f346201dda4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662748958 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3662748958
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3737304235
Short name T363
Test name
Test status
Simulation time 19858197194 ps
CPU time 17.08 seconds
Started Jul 31 06:08:48 PM PDT 24
Finished Jul 31 06:09:06 PM PDT 24
Peak memory 205556 kb
Host smart-398670f2-085c-43b8-a745-e876f7e966e7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737304235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.3737304235
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.691765363
Short name T438
Test name
Test status
Simulation time 6050330502 ps
CPU time 16.98 seconds
Started Jul 31 06:08:47 PM PDT 24
Finished Jul 31 06:09:04 PM PDT 24
Peak memory 205636 kb
Host smart-32f445db-0458-4f25-8d9a-06dc00f197fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691765363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.691765363
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.272816943
Short name T424
Test name
Test status
Simulation time 267150557 ps
CPU time 1.41 seconds
Started Jul 31 06:08:47 PM PDT 24
Finished Jul 31 06:08:48 PM PDT 24
Peak memory 205320 kb
Host smart-545d3ecf-3a1d-4a7f-a494-c2edabe57b99
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272816943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.272816943
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2339833969
Short name T460
Test name
Test status
Simulation time 808837481 ps
CPU time 3.97 seconds
Started Jul 31 06:08:50 PM PDT 24
Finished Jul 31 06:08:54 PM PDT 24
Peak memory 205712 kb
Host smart-cc90f52b-d40b-4818-9bc4-0fc71caba2ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339833969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2339833969
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.504098336
Short name T451
Test name
Test status
Simulation time 480502912 ps
CPU time 4.14 seconds
Started Jul 31 06:08:47 PM PDT 24
Finished Jul 31 06:08:51 PM PDT 24
Peak memory 213944 kb
Host smart-49c58d09-e099-47b7-b8f5-34c88b39ecc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504098336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.504098336
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.1041613192
Short name T368
Test name
Test status
Simulation time 870270421 ps
CPU time 8.81 seconds
Started Jul 31 06:08:47 PM PDT 24
Finished Jul 31 06:08:56 PM PDT 24
Peak memory 213760 kb
Host smart-acb52e5d-20fe-4828-ba94-9b6b55249996
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041613192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.1
041613192
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3948282713
Short name T96
Test name
Test status
Simulation time 228603715 ps
CPU time 2.43 seconds
Started Jul 31 06:08:58 PM PDT 24
Finished Jul 31 06:09:01 PM PDT 24
Peak memory 218384 kb
Host smart-997581a9-6335-4e24-b217-ce133935b47d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948282713 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3948282713
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.1273284416
Short name T382
Test name
Test status
Simulation time 224070619 ps
CPU time 2.38 seconds
Started Jul 31 06:08:57 PM PDT 24
Finished Jul 31 06:09:00 PM PDT 24
Peak memory 213780 kb
Host smart-115d7f16-5181-4664-beeb-e11544ae8ac1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273284416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.1273284416
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2712690792
Short name T350
Test name
Test status
Simulation time 5426360791 ps
CPU time 5.29 seconds
Started Jul 31 06:08:52 PM PDT 24
Finished Jul 31 06:08:57 PM PDT 24
Peak memory 205644 kb
Host smart-35968f89-e542-44ba-ac07-8db0d8355820
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712690792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.2712690792
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2204441129
Short name T309
Test name
Test status
Simulation time 1971297998 ps
CPU time 6.04 seconds
Started Jul 31 06:08:52 PM PDT 24
Finished Jul 31 06:08:58 PM PDT 24
Peak memory 205488 kb
Host smart-56c73e7c-6918-4177-be1d-5e7601eb0bba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204441129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2204441129
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.3782410118
Short name T387
Test name
Test status
Simulation time 891949676 ps
CPU time 0.82 seconds
Started Jul 31 06:08:51 PM PDT 24
Finished Jul 31 06:08:52 PM PDT 24
Peak memory 205332 kb
Host smart-dc383f1e-b144-4b81-9f24-78dcebab3853
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782410118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
3782410118
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3687595631
Short name T435
Test name
Test status
Simulation time 378826601 ps
CPU time 3.7 seconds
Started Jul 31 06:08:57 PM PDT 24
Finished Jul 31 06:09:01 PM PDT 24
Peak memory 205664 kb
Host smart-e24095ea-2f05-4318-890b-f49fe727d841
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687595631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3687595631
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1401902063
Short name T395
Test name
Test status
Simulation time 363092278 ps
CPU time 2.39 seconds
Started Jul 31 06:08:52 PM PDT 24
Finished Jul 31 06:08:54 PM PDT 24
Peak memory 213948 kb
Host smart-b2614509-50c0-4d6b-b3c6-8ca8cad0b531
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401902063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1401902063
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2853699260
Short name T164
Test name
Test status
Simulation time 823945996 ps
CPU time 11.08 seconds
Started Jul 31 06:08:52 PM PDT 24
Finished Jul 31 06:09:03 PM PDT 24
Peak memory 222068 kb
Host smart-99a7be0f-8824-4c27-8e8d-85e57f4036ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853699260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
853699260
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2691280420
Short name T379
Test name
Test status
Simulation time 458255100 ps
CPU time 2.38 seconds
Started Jul 31 06:09:02 PM PDT 24
Finished Jul 31 06:09:05 PM PDT 24
Peak memory 217932 kb
Host smart-13a445b8-c85d-4b57-9559-1ed79fb9f707
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691280420 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2691280420
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.267625895
Short name T361
Test name
Test status
Simulation time 89842320 ps
CPU time 1.73 seconds
Started Jul 31 06:09:01 PM PDT 24
Finished Jul 31 06:09:03 PM PDT 24
Peak memory 213728 kb
Host smart-b1395c67-a023-47cb-8dd8-bea7b341da2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267625895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.267625895
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.258833361
Short name T321
Test name
Test status
Simulation time 15607836677 ps
CPU time 26.55 seconds
Started Jul 31 06:09:02 PM PDT 24
Finished Jul 31 06:09:29 PM PDT 24
Peak memory 205632 kb
Host smart-7ea8b0bf-10c1-466d-930a-93b2060637b2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258833361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
rv_dm_jtag_dmi_csr_bit_bash.258833361
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1723380187
Short name T305
Test name
Test status
Simulation time 5674184154 ps
CPU time 15.75 seconds
Started Jul 31 06:08:56 PM PDT 24
Finished Jul 31 06:09:12 PM PDT 24
Peak memory 205624 kb
Host smart-8608b446-871c-41f3-a584-5c83fb2c40e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723380187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1723380187
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.749452605
Short name T391
Test name
Test status
Simulation time 342829901 ps
CPU time 0.93 seconds
Started Jul 31 06:08:57 PM PDT 24
Finished Jul 31 06:08:58 PM PDT 24
Peak memory 205212 kb
Host smart-f0d2ca35-51b1-4252-a3c9-7f61f404a2ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749452605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.749452605
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.639791652
Short name T108
Test name
Test status
Simulation time 187013893 ps
CPU time 4.01 seconds
Started Jul 31 06:08:59 PM PDT 24
Finished Jul 31 06:09:03 PM PDT 24
Peak memory 205692 kb
Host smart-6e990c50-ee66-4ae4-a2e9-fc76424caa51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639791652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same_
csr_outstanding.639791652
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.4221383716
Short name T358
Test name
Test status
Simulation time 296397858 ps
CPU time 6.33 seconds
Started Jul 31 06:08:59 PM PDT 24
Finished Jul 31 06:09:06 PM PDT 24
Peak memory 213952 kb
Host smart-8f15b611-fb63-44ef-af97-132be69bf907
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221383716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.4221383716
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.2334109959
Short name T419
Test name
Test status
Simulation time 252049627 ps
CPU time 2.48 seconds
Started Jul 31 06:09:06 PM PDT 24
Finished Jul 31 06:09:08 PM PDT 24
Peak memory 219140 kb
Host smart-15585ba7-0193-4273-8c70-3d923ac21d09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334109959 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.2334109959
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.496287528
Short name T114
Test name
Test status
Simulation time 229871757 ps
CPU time 1.65 seconds
Started Jul 31 06:09:02 PM PDT 24
Finished Jul 31 06:09:03 PM PDT 24
Peak memory 213760 kb
Host smart-c765d8f9-fd26-4534-a8aa-a5f6acec93da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496287528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.496287528
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.2083644693
Short name T346
Test name
Test status
Simulation time 17633393592 ps
CPU time 50.56 seconds
Started Jul 31 06:09:03 PM PDT 24
Finished Jul 31 06:09:53 PM PDT 24
Peak memory 205656 kb
Host smart-dd0a00db-7edf-42e6-a179-c22e7527c164
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083644693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.2083644693
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.1983416262
Short name T448
Test name
Test status
Simulation time 2605772328 ps
CPU time 7.48 seconds
Started Jul 31 06:08:59 PM PDT 24
Finished Jul 31 06:09:07 PM PDT 24
Peak memory 205648 kb
Host smart-f6ffdcf5-2c86-44a8-9780-aacb5a5f9e67
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983416262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
1983416262
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1151814674
Short name T370
Test name
Test status
Simulation time 765481938 ps
CPU time 1.44 seconds
Started Jul 31 06:09:03 PM PDT 24
Finished Jul 31 06:09:04 PM PDT 24
Peak memory 205332 kb
Host smart-7a91ecd7-252d-4be3-9923-2b7fc270a48c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151814674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1151814674
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2359294586
Short name T360
Test name
Test status
Simulation time 342260039 ps
CPU time 4.02 seconds
Started Jul 31 06:09:03 PM PDT 24
Finished Jul 31 06:09:07 PM PDT 24
Peak memory 213864 kb
Host smart-541b590c-5ce5-42b8-9cf4-bad58e60c508
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359294586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2359294586
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.1797861644
Short name T168
Test name
Test status
Simulation time 4649720307 ps
CPU time 21.43 seconds
Started Jul 31 06:09:02 PM PDT 24
Finished Jul 31 06:09:24 PM PDT 24
Peak memory 213960 kb
Host smart-325f4c13-1694-48b2-bf0b-690140eeff24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797861644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.1
797861644
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3171891339
Short name T412
Test name
Test status
Simulation time 378096589 ps
CPU time 2.48 seconds
Started Jul 31 06:09:07 PM PDT 24
Finished Jul 31 06:09:09 PM PDT 24
Peak memory 219204 kb
Host smart-cf3426e0-8f0f-4116-b038-e79b73871ce9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171891339 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3171891339
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3779790693
Short name T101
Test name
Test status
Simulation time 979934976 ps
CPU time 1.74 seconds
Started Jul 31 06:09:09 PM PDT 24
Finished Jul 31 06:09:11 PM PDT 24
Peak memory 213768 kb
Host smart-2bfb649f-12d7-4234-aa61-e2a002b65333
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779790693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3779790693
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1923591547
Short name T344
Test name
Test status
Simulation time 1887324238 ps
CPU time 2.55 seconds
Started Jul 31 06:09:06 PM PDT 24
Finished Jul 31 06:09:09 PM PDT 24
Peak memory 205548 kb
Host smart-1a9b1a28-180b-4bdb-842f-a4981d5d5793
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923591547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.1923591547
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2480014033
Short name T355
Test name
Test status
Simulation time 1954002172 ps
CPU time 2.69 seconds
Started Jul 31 06:09:08 PM PDT 24
Finished Jul 31 06:09:11 PM PDT 24
Peak memory 205476 kb
Host smart-96274f2c-4622-4b9a-9fe6-c7ce4fcc6a03
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480014033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2480014033
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2068947209
Short name T452
Test name
Test status
Simulation time 443627227 ps
CPU time 1.09 seconds
Started Jul 31 06:09:06 PM PDT 24
Finished Jul 31 06:09:07 PM PDT 24
Peak memory 205300 kb
Host smart-6a650903-0cf2-4f91-b102-32da9d371ed3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068947209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2068947209
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.1084743410
Short name T104
Test name
Test status
Simulation time 534530577 ps
CPU time 7.82 seconds
Started Jul 31 06:09:07 PM PDT 24
Finished Jul 31 06:09:15 PM PDT 24
Peak memory 205588 kb
Host smart-56d59cd2-c1b6-4ad1-a826-0a48be77178b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084743410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.1084743410
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.3586833402
Short name T367
Test name
Test status
Simulation time 157370309 ps
CPU time 4.51 seconds
Started Jul 31 06:09:07 PM PDT 24
Finished Jul 31 06:09:11 PM PDT 24
Peak memory 213856 kb
Host smart-4f472496-d11b-434f-9971-904e40b1a0d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586833402 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.3586833402
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1630650193
Short name T162
Test name
Test status
Simulation time 2925841747 ps
CPU time 12.96 seconds
Started Jul 31 06:09:08 PM PDT 24
Finished Jul 31 06:09:21 PM PDT 24
Peak memory 214012 kb
Host smart-d357c5f1-b269-4f9f-bb56-0f5f929c1b9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630650193 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
630650193
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1913248175
Short name T434
Test name
Test status
Simulation time 760480323 ps
CPU time 3.99 seconds
Started Jul 31 06:09:12 PM PDT 24
Finished Jul 31 06:09:17 PM PDT 24
Peak memory 218900 kb
Host smart-d64b692d-3936-4b1d-a81c-2277bfa793db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913248175 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1913248175
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2105639290
Short name T426
Test name
Test status
Simulation time 528947985 ps
CPU time 2.68 seconds
Started Jul 31 06:09:13 PM PDT 24
Finished Jul 31 06:09:16 PM PDT 24
Peak memory 213724 kb
Host smart-7246bcc1-ffc2-4a5d-856d-d5a7bfc8855c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105639290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2105639290
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1453723204
Short name T441
Test name
Test status
Simulation time 36936236 ps
CPU time 0.77 seconds
Started Jul 31 06:09:12 PM PDT 24
Finished Jul 31 06:09:13 PM PDT 24
Peak memory 205320 kb
Host smart-17efa143-1e2a-4c1a-ad8c-55433192e711
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453723204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.1453723204
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3147093127
Short name T431
Test name
Test status
Simulation time 6712347897 ps
CPU time 8.37 seconds
Started Jul 31 06:09:04 PM PDT 24
Finished Jul 31 06:09:13 PM PDT 24
Peak memory 205660 kb
Host smart-d8538c48-4b11-45f1-b30c-c3551ed1122c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147093127 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3147093127
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2577537781
Short name T418
Test name
Test status
Simulation time 380026578 ps
CPU time 0.95 seconds
Started Jul 31 06:09:05 PM PDT 24
Finished Jul 31 06:09:06 PM PDT 24
Peak memory 205240 kb
Host smart-0a2c372b-de52-4b3b-ac77-2fa0310e95e1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577537781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2577537781
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1476724633
Short name T398
Test name
Test status
Simulation time 438468914 ps
CPU time 7.46 seconds
Started Jul 31 06:09:13 PM PDT 24
Finished Jul 31 06:09:21 PM PDT 24
Peak memory 205592 kb
Host smart-11c54a07-66aa-4241-87f7-54c4ddf864d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476724633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1476724633
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.354601050
Short name T377
Test name
Test status
Simulation time 372767855 ps
CPU time 4.96 seconds
Started Jul 31 06:09:12 PM PDT 24
Finished Jul 31 06:09:17 PM PDT 24
Peak memory 213904 kb
Host smart-6075a3af-efdd-4f8f-a28c-939f81d53229
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354601050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.354601050
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1088397278
Short name T160
Test name
Test status
Simulation time 16057853426 ps
CPU time 23.46 seconds
Started Jul 31 06:09:11 PM PDT 24
Finished Jul 31 06:09:35 PM PDT 24
Peak memory 214376 kb
Host smart-8063023c-ca42-43c3-9b04-44d05efa9347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088397278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
088397278
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2081750998
Short name T378
Test name
Test status
Simulation time 278082844 ps
CPU time 3.61 seconds
Started Jul 31 06:09:19 PM PDT 24
Finished Jul 31 06:09:23 PM PDT 24
Peak memory 217648 kb
Host smart-6997f076-53ec-430f-8deb-9eb88c20d668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081750998 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2081750998
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.382642727
Short name T416
Test name
Test status
Simulation time 233613224 ps
CPU time 2.36 seconds
Started Jul 31 06:09:21 PM PDT 24
Finished Jul 31 06:09:24 PM PDT 24
Peak memory 213540 kb
Host smart-459e3c56-692a-4c77-8c73-75604e8cb047
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382642727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.382642727
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.1310854152
Short name T311
Test name
Test status
Simulation time 5213337631 ps
CPU time 17.05 seconds
Started Jul 31 06:09:21 PM PDT 24
Finished Jul 31 06:09:38 PM PDT 24
Peak memory 205628 kb
Host smart-b2e921eb-b82d-4fef-9010-5221c350dddf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310854152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.1310854152
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1958409886
Short name T308
Test name
Test status
Simulation time 3027517504 ps
CPU time 9.62 seconds
Started Jul 31 06:09:12 PM PDT 24
Finished Jul 31 06:09:21 PM PDT 24
Peak memory 205648 kb
Host smart-29fe57f1-7982-4715-b515-15a6380dd73d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958409886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1958409886
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4091522708
Short name T316
Test name
Test status
Simulation time 193140486 ps
CPU time 0.84 seconds
Started Jul 31 06:09:12 PM PDT 24
Finished Jul 31 06:09:13 PM PDT 24
Peak memory 205324 kb
Host smart-1faebee3-0771-437e-a463-61184230ae0a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091522708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
4091522708
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.994333188
Short name T91
Test name
Test status
Simulation time 348612251 ps
CPU time 4.62 seconds
Started Jul 31 06:09:16 PM PDT 24
Finished Jul 31 06:09:21 PM PDT 24
Peak memory 205580 kb
Host smart-157d4aef-549a-40e4-b29d-785e6b08a064
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994333188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.994333188
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.296562478
Short name T126
Test name
Test status
Simulation time 1468601729 ps
CPU time 3.28 seconds
Started Jul 31 06:09:19 PM PDT 24
Finished Jul 31 06:09:22 PM PDT 24
Peak memory 213908 kb
Host smart-7ed1a4ca-31db-4b8e-a71d-100bcaf3052a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296562478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.296562478
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3619075351
Short name T161
Test name
Test status
Simulation time 8973558183 ps
CPU time 9.87 seconds
Started Jul 31 06:09:18 PM PDT 24
Finished Jul 31 06:09:28 PM PDT 24
Peak memory 213932 kb
Host smart-c4e284c5-78d1-4e8f-a50f-5d30c7535ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619075351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
619075351
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1386961875
Short name T455
Test name
Test status
Simulation time 439054238 ps
CPU time 4.18 seconds
Started Jul 31 06:09:19 PM PDT 24
Finished Jul 31 06:09:24 PM PDT 24
Peak memory 222012 kb
Host smart-c9bb5114-4f67-4410-a7ca-829d0c57bf46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386961875 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1386961875
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.703161646
Short name T374
Test name
Test status
Simulation time 172221455 ps
CPU time 2.52 seconds
Started Jul 31 06:09:18 PM PDT 24
Finished Jul 31 06:09:20 PM PDT 24
Peak memory 213752 kb
Host smart-d7d65e7c-31f7-493b-8985-07e171ecc027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703161646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.703161646
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.2043837955
Short name T399
Test name
Test status
Simulation time 17440974859 ps
CPU time 25.43 seconds
Started Jul 31 06:09:21 PM PDT 24
Finished Jul 31 06:09:47 PM PDT 24
Peak memory 205496 kb
Host smart-d6c0102b-f299-483b-8b29-6eeb60829dfa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043837955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.2043837955
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3734718471
Short name T392
Test name
Test status
Simulation time 2600510994 ps
CPU time 4.01 seconds
Started Jul 31 06:09:17 PM PDT 24
Finished Jul 31 06:09:21 PM PDT 24
Peak memory 205604 kb
Host smart-ed1e5691-b6d3-411d-99b9-ecaf6154afd6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734718471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3734718471
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.4076792491
Short name T354
Test name
Test status
Simulation time 197537252 ps
CPU time 1.27 seconds
Started Jul 31 06:09:16 PM PDT 24
Finished Jul 31 06:09:17 PM PDT 24
Peak memory 205212 kb
Host smart-bc15e97d-2869-487b-96c6-ddfe28ed4617
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076792491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
4076792491
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.1429912589
Short name T105
Test name
Test status
Simulation time 603028877 ps
CPU time 7.75 seconds
Started Jul 31 06:09:18 PM PDT 24
Finished Jul 31 06:09:25 PM PDT 24
Peak memory 205608 kb
Host smart-867bed27-2fc9-486a-bc58-6c2099b64e30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429912589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.1429912589
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2210039078
Short name T440
Test name
Test status
Simulation time 125924773 ps
CPU time 1.96 seconds
Started Jul 31 06:09:17 PM PDT 24
Finished Jul 31 06:09:19 PM PDT 24
Peak memory 213908 kb
Host smart-ef4d54cb-9dd6-4678-931a-0d502dd22a43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210039078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2210039078
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1719106005
Short name T169
Test name
Test status
Simulation time 1403075624 ps
CPU time 17.89 seconds
Started Jul 31 06:09:16 PM PDT 24
Finished Jul 31 06:09:34 PM PDT 24
Peak memory 213836 kb
Host smart-cf394ba9-ea74-417b-999b-640f42d6a988
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719106005 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
719106005
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.4029927507
Short name T381
Test name
Test status
Simulation time 333773102 ps
CPU time 3.84 seconds
Started Jul 31 06:09:24 PM PDT 24
Finished Jul 31 06:09:29 PM PDT 24
Peak memory 219776 kb
Host smart-7bf023bb-8030-4315-8607-0de02d6dd953
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029927507 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.4029927507
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3258228172
Short name T454
Test name
Test status
Simulation time 464057841 ps
CPU time 2.53 seconds
Started Jul 31 06:09:21 PM PDT 24
Finished Jul 31 06:09:24 PM PDT 24
Peak memory 213764 kb
Host smart-ff09cf4d-9de0-4bbf-af22-3cdcf7c88b9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258228172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3258228172
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.2952538101
Short name T324
Test name
Test status
Simulation time 9830553814 ps
CPU time 4.59 seconds
Started Jul 31 06:09:24 PM PDT 24
Finished Jul 31 06:09:28 PM PDT 24
Peak memory 205620 kb
Host smart-44eccd82-1c68-40ab-81a7-334048b140fc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952538101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.2952538101
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2801739754
Short name T337
Test name
Test status
Simulation time 7415551771 ps
CPU time 8.16 seconds
Started Jul 31 06:09:21 PM PDT 24
Finished Jul 31 06:09:29 PM PDT 24
Peak memory 205652 kb
Host smart-1815b93e-de46-4213-a15b-88595105d8ca
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801739754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2801739754
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.4052393344
Short name T326
Test name
Test status
Simulation time 1102178847 ps
CPU time 2.28 seconds
Started Jul 31 06:09:20 PM PDT 24
Finished Jul 31 06:09:22 PM PDT 24
Peak memory 205332 kb
Host smart-fa5e9cb4-f4d8-43a3-b274-79d118f46779
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052393344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
4052393344
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.1496887900
Short name T119
Test name
Test status
Simulation time 602833101 ps
CPU time 6.06 seconds
Started Jul 31 06:09:25 PM PDT 24
Finished Jul 31 06:09:31 PM PDT 24
Peak memory 205680 kb
Host smart-1a2de733-0a52-4b9a-85b9-c8f8524f32a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496887900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.1496887900
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2656303379
Short name T340
Test name
Test status
Simulation time 152117893 ps
CPU time 3.24 seconds
Started Jul 31 06:09:23 PM PDT 24
Finished Jul 31 06:09:27 PM PDT 24
Peak memory 213932 kb
Host smart-a10c1906-eaf0-417e-8dfd-1e9799e39105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656303379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2656303379
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1305318866
Short name T124
Test name
Test status
Simulation time 1188203759 ps
CPU time 11.42 seconds
Started Jul 31 06:09:23 PM PDT 24
Finished Jul 31 06:09:35 PM PDT 24
Peak memory 213848 kb
Host smart-8faec502-442b-408d-ba3f-d85d128862ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305318866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
305318866
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.879147818
Short name T373
Test name
Test status
Simulation time 314537771 ps
CPU time 2.23 seconds
Started Jul 31 06:09:26 PM PDT 24
Finished Jul 31 06:09:29 PM PDT 24
Peak memory 217376 kb
Host smart-9a74ceb8-2738-4292-b5cd-3c02efddea81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879147818 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.879147818
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3854252930
Short name T443
Test name
Test status
Simulation time 100451248 ps
CPU time 1.56 seconds
Started Jul 31 06:09:28 PM PDT 24
Finished Jul 31 06:09:29 PM PDT 24
Peak memory 213752 kb
Host smart-7842203b-31fc-4923-8925-3d30189c1264
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854252930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3854252930
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.2645577403
Short name T357
Test name
Test status
Simulation time 16317368714 ps
CPU time 10.28 seconds
Started Jul 31 06:09:22 PM PDT 24
Finished Jul 31 06:09:32 PM PDT 24
Peak memory 205616 kb
Host smart-299d77ed-b119-4078-94a8-7b411ba82370
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645577403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.rv_dm_jtag_dmi_csr_bit_bash.2645577403
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2967816509
Short name T330
Test name
Test status
Simulation time 2915929106 ps
CPU time 4.47 seconds
Started Jul 31 06:09:26 PM PDT 24
Finished Jul 31 06:09:30 PM PDT 24
Peak memory 205648 kb
Host smart-210a4e5b-02ee-4c6e-a11b-55045dae11e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967816509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2967816509
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.86519666
Short name T459
Test name
Test status
Simulation time 704511695 ps
CPU time 1.13 seconds
Started Jul 31 06:09:24 PM PDT 24
Finished Jul 31 06:09:26 PM PDT 24
Peak memory 205248 kb
Host smart-5981312e-1c4b-43d8-85ae-ccb95bc50006
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86519666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.86519666
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3479684716
Short name T461
Test name
Test status
Simulation time 262984669 ps
CPU time 4.31 seconds
Started Jul 31 06:09:27 PM PDT 24
Finished Jul 31 06:09:31 PM PDT 24
Peak memory 205644 kb
Host smart-f7e4cd2a-ec15-4f36-bc0c-9e11d7f4990a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479684716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3479684716
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3537397681
Short name T403
Test name
Test status
Simulation time 175669931 ps
CPU time 3.2 seconds
Started Jul 31 06:09:22 PM PDT 24
Finished Jul 31 06:09:25 PM PDT 24
Peak memory 213880 kb
Host smart-de68bd90-efd3-4c1b-8148-9d964d9bd1b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537397681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3537397681
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.2678467201
Short name T125
Test name
Test status
Simulation time 2761668870 ps
CPU time 24.63 seconds
Started Jul 31 06:09:23 PM PDT 24
Finished Jul 31 06:09:48 PM PDT 24
Peak memory 213968 kb
Host smart-dd3bcb59-b388-471c-a6be-6947b5c6911f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678467201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.2
678467201
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1633287203
Short name T372
Test name
Test status
Simulation time 4360673465 ps
CPU time 34.42 seconds
Started Jul 31 06:07:55 PM PDT 24
Finished Jul 31 06:08:29 PM PDT 24
Peak memory 205708 kb
Host smart-6e6d1124-1a96-4cbb-aade-487484b4a47e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633287203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1633287203
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3887208034
Short name T117
Test name
Test status
Simulation time 10219621397 ps
CPU time 35.21 seconds
Started Jul 31 06:08:04 PM PDT 24
Finished Jul 31 06:08:39 PM PDT 24
Peak memory 205712 kb
Host smart-cff2dc9a-869b-4ce4-a6de-1f049a553d04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887208034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3887208034
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1891646459
Short name T319
Test name
Test status
Simulation time 115584825 ps
CPU time 3.87 seconds
Started Jul 31 06:08:08 PM PDT 24
Finished Jul 31 06:08:12 PM PDT 24
Peak memory 219976 kb
Host smart-9a962014-e926-453b-bf6c-0e9a3f16669b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891646459 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1891646459
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.972056067
Short name T116
Test name
Test status
Simulation time 107669053 ps
CPU time 1.87 seconds
Started Jul 31 06:08:02 PM PDT 24
Finished Jul 31 06:08:04 PM PDT 24
Peak memory 213704 kb
Host smart-d468cfc1-597b-40dc-97a1-cb7aaa604c49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972056067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.972056067
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.416624153
Short name T314
Test name
Test status
Simulation time 241795479341 ps
CPU time 571.03 seconds
Started Jul 31 06:08:02 PM PDT 24
Finished Jul 31 06:17:33 PM PDT 24
Peak memory 212464 kb
Host smart-220edf0d-697a-46e4-95a6-c10072f937d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416624153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.416624153
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.2600887380
Short name T423
Test name
Test status
Simulation time 5925196590 ps
CPU time 8.98 seconds
Started Jul 31 06:08:01 PM PDT 24
Finished Jul 31 06:08:10 PM PDT 24
Peak memory 205644 kb
Host smart-12b7356e-bfed-4615-8151-a3e6cb32cf4e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600887380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.2600887380
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.3611067556
Short name T353
Test name
Test status
Simulation time 7622217706 ps
CPU time 10.91 seconds
Started Jul 31 06:07:56 PM PDT 24
Finished Jul 31 06:08:07 PM PDT 24
Peak memory 205768 kb
Host smart-2d16bedf-7465-435c-89aa-ec6078b6ae3a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611067556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.3611067556
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.4224818137
Short name T335
Test name
Test status
Simulation time 2962318731 ps
CPU time 3.21 seconds
Started Jul 31 06:08:02 PM PDT 24
Finished Jul 31 06:08:06 PM PDT 24
Peak memory 205696 kb
Host smart-c047ed24-6932-40c5-bcf3-e0827b4ed77f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224818137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.4
224818137
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.70259230
Short name T348
Test name
Test status
Simulation time 425717780 ps
CPU time 1.52 seconds
Started Jul 31 06:07:55 PM PDT 24
Finished Jul 31 06:07:57 PM PDT 24
Peak memory 205320 kb
Host smart-e0feeb9d-cb25-4f91-8e6e-c93b939f2098
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70259230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_
aliasing.70259230
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3864547198
Short name T69
Test name
Test status
Simulation time 8099048195 ps
CPU time 12.09 seconds
Started Jul 31 06:07:57 PM PDT 24
Finished Jul 31 06:08:10 PM PDT 24
Peak memory 205624 kb
Host smart-e867b8c9-41ec-437a-be5c-95f1305f0dcd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864547198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.3864547198
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.724450102
Short name T306
Test name
Test status
Simulation time 196041017 ps
CPU time 0.81 seconds
Started Jul 31 06:07:58 PM PDT 24
Finished Jul 31 06:07:59 PM PDT 24
Peak memory 205380 kb
Host smart-5291a5a1-9aa4-4bb3-be66-6ab4924578d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724450102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.724450102
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.513995783
Short name T386
Test name
Test status
Simulation time 601281698 ps
CPU time 0.84 seconds
Started Jul 31 06:08:00 PM PDT 24
Finished Jul 31 06:08:00 PM PDT 24
Peak memory 205328 kb
Host smart-f9241a88-acd7-417c-b9d7-5331e3250654
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513995783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.513995783
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2571821061
Short name T332
Test name
Test status
Simulation time 32102914 ps
CPU time 0.78 seconds
Started Jul 31 06:08:02 PM PDT 24
Finished Jul 31 06:08:03 PM PDT 24
Peak memory 205412 kb
Host smart-5a089ab3-628c-4d9a-99dc-92eb93668420
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571821061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2571821061
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.1187010618
Short name T425
Test name
Test status
Simulation time 91250739 ps
CPU time 0.88 seconds
Started Jul 31 06:08:01 PM PDT 24
Finished Jul 31 06:08:02 PM PDT 24
Peak memory 205348 kb
Host smart-611c94b9-278b-4405-8152-5668dedcf51f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187010618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.1187010618
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3205633311
Short name T444
Test name
Test status
Simulation time 1037610602 ps
CPU time 7.51 seconds
Started Jul 31 06:08:01 PM PDT 24
Finished Jul 31 06:08:08 PM PDT 24
Peak memory 205644 kb
Host smart-96a84c93-395d-4544-9c1c-a43b55c154c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205633311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3205633311
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2419123679
Short name T457
Test name
Test status
Simulation time 58208000528 ps
CPU time 95.64 seconds
Started Jul 31 06:08:01 PM PDT 24
Finished Jul 31 06:09:37 PM PDT 24
Peak memory 224400 kb
Host smart-d09a78c3-f85b-4bad-a355-9467953ab480
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419123679 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2419123679
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.3110315439
Short name T385
Test name
Test status
Simulation time 74701469 ps
CPU time 3.87 seconds
Started Jul 31 06:08:02 PM PDT 24
Finished Jul 31 06:08:06 PM PDT 24
Peak memory 213940 kb
Host smart-ff645710-dccb-4d5c-80da-912bd8f91b17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110315439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.3110315439
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.4166722070
Short name T95
Test name
Test status
Simulation time 34026669124 ps
CPU time 35.26 seconds
Started Jul 31 06:08:07 PM PDT 24
Finished Jul 31 06:08:43 PM PDT 24
Peak memory 213972 kb
Host smart-3577b198-4071-4e79-820f-298a9893abfa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166722070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.4166722070
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1943120163
Short name T87
Test name
Test status
Simulation time 15329375660 ps
CPU time 37.41 seconds
Started Jul 31 06:08:17 PM PDT 24
Finished Jul 31 06:08:54 PM PDT 24
Peak memory 205756 kb
Host smart-bcf4fc48-a820-4b80-b043-32f4d090337f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943120163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1943120163
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3191255684
Short name T109
Test name
Test status
Simulation time 127170114 ps
CPU time 2.27 seconds
Started Jul 31 06:08:13 PM PDT 24
Finished Jul 31 06:08:16 PM PDT 24
Peak memory 213848 kb
Host smart-b4247d67-f2a6-41fd-8d68-423e4c3cad46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191255684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3191255684
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3995178728
Short name T413
Test name
Test status
Simulation time 446928956 ps
CPU time 4.08 seconds
Started Jul 31 06:08:19 PM PDT 24
Finished Jul 31 06:08:23 PM PDT 24
Peak memory 219704 kb
Host smart-ae55ef87-079e-4bc7-a926-655dca9abaec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995178728 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3995178728
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4238041166
Short name T328
Test name
Test status
Simulation time 157021919 ps
CPU time 1.7 seconds
Started Jul 31 06:08:09 PM PDT 24
Finished Jul 31 06:08:11 PM PDT 24
Peak memory 213840 kb
Host smart-14ee5761-d333-4ffc-8d8e-79330d4c1b5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238041166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.4238041166
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.1641105713
Short name T317
Test name
Test status
Simulation time 74616878217 ps
CPU time 105.66 seconds
Started Jul 31 06:08:16 PM PDT 24
Finished Jul 31 06:10:02 PM PDT 24
Peak memory 205636 kb
Host smart-4546b453-0990-4658-8470-53b83622a666
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641105713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.1641105713
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.4288696121
Short name T396
Test name
Test status
Simulation time 11384497139 ps
CPU time 25.37 seconds
Started Jul 31 06:08:14 PM PDT 24
Finished Jul 31 06:08:39 PM PDT 24
Peak memory 205632 kb
Host smart-bf872015-d2bb-48c1-93ee-a735947fd6f6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288696121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.4288696121
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.2699555120
Short name T445
Test name
Test status
Simulation time 4800190538 ps
CPU time 5.42 seconds
Started Jul 31 06:08:12 PM PDT 24
Finished Jul 31 06:08:17 PM PDT 24
Peak memory 205656 kb
Host smart-a30fc2ea-aca2-48a2-bf1c-d2d1a24522bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699555120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.2699555120
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2601556377
Short name T402
Test name
Test status
Simulation time 1381131491 ps
CPU time 1.14 seconds
Started Jul 31 06:08:14 PM PDT 24
Finished Jul 31 06:08:15 PM PDT 24
Peak memory 205504 kb
Host smart-f2d8843b-74e7-4b24-8fbf-77040df9ed13
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601556377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
601556377
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4128667221
Short name T334
Test name
Test status
Simulation time 476380099 ps
CPU time 1.98 seconds
Started Jul 31 06:08:07 PM PDT 24
Finished Jul 31 06:08:09 PM PDT 24
Peak memory 205324 kb
Host smart-7dbf1cc9-7763-4085-b02d-aaf3d8ee2247
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128667221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.4128667221
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1969145439
Short name T312
Test name
Test status
Simulation time 41739733245 ps
CPU time 106.84 seconds
Started Jul 31 06:08:07 PM PDT 24
Finished Jul 31 06:09:54 PM PDT 24
Peak memory 205552 kb
Host smart-99398fdf-d604-4858-aa90-8b918d773d5f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969145439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1969145439
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3542253799
Short name T307
Test name
Test status
Simulation time 141772696 ps
CPU time 1.02 seconds
Started Jul 31 06:08:08 PM PDT 24
Finished Jul 31 06:08:09 PM PDT 24
Peak memory 205336 kb
Host smart-a3e6ad81-6cf3-4a5e-a0ed-6f4eaa357304
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542253799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3542253799
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3774955147
Short name T67
Test name
Test status
Simulation time 297664186 ps
CPU time 1.39 seconds
Started Jul 31 06:08:08 PM PDT 24
Finished Jul 31 06:08:09 PM PDT 24
Peak memory 205320 kb
Host smart-132c9094-4a30-4c26-b25b-59f14f4fcb04
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774955147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
774955147
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.737113649
Short name T349
Test name
Test status
Simulation time 39710746 ps
CPU time 0.76 seconds
Started Jul 31 06:08:12 PM PDT 24
Finished Jul 31 06:08:13 PM PDT 24
Peak memory 205368 kb
Host smart-7e28b4f1-2b2a-48aa-a36d-be594eac2bf2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737113649 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.737113649
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3735601853
Short name T356
Test name
Test status
Simulation time 37508470 ps
CPU time 0.8 seconds
Started Jul 31 06:08:15 PM PDT 24
Finished Jul 31 06:08:16 PM PDT 24
Peak memory 205296 kb
Host smart-528c9892-ae74-40de-a026-546ef6e0447d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735601853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3735601853
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.2725988050
Short name T465
Test name
Test status
Simulation time 1016895469 ps
CPU time 7.91 seconds
Started Jul 31 06:08:19 PM PDT 24
Finished Jul 31 06:08:27 PM PDT 24
Peak memory 205624 kb
Host smart-d76d63b4-16f8-4449-a4a3-92ebf2bd06de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725988050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.2725988050
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.607940603
Short name T170
Test name
Test status
Simulation time 15654951703 ps
CPU time 8.75 seconds
Started Jul 31 06:08:14 PM PDT 24
Finished Jul 31 06:08:23 PM PDT 24
Peak memory 221516 kb
Host smart-9017eeae-0450-4ba2-9933-a4c892753fa4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607940603 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.607940603
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2608353356
Short name T405
Test name
Test status
Simulation time 223932602 ps
CPU time 3.63 seconds
Started Jul 31 06:08:14 PM PDT 24
Finished Jul 31 06:08:18 PM PDT 24
Peak memory 213860 kb
Host smart-d9503ddb-183d-4008-abe5-ef0dc9a856bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608353356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2608353356
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.3668433882
Short name T342
Test name
Test status
Simulation time 3034819689 ps
CPU time 12.52 seconds
Started Jul 31 06:08:13 PM PDT 24
Finished Jul 31 06:08:26 PM PDT 24
Peak memory 213992 kb
Host smart-23853e6f-aa1a-45d0-a913-64669a6e24f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668433882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.3668433882
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1120151334
Short name T93
Test name
Test status
Simulation time 13418832773 ps
CPU time 81.94 seconds
Started Jul 31 06:08:16 PM PDT 24
Finished Jul 31 06:09:38 PM PDT 24
Peak memory 213820 kb
Host smart-5537100c-a888-48da-8105-e2fdb31fa02b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120151334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1120151334
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3046396036
Short name T88
Test name
Test status
Simulation time 44609117801 ps
CPU time 70.3 seconds
Started Jul 31 06:08:27 PM PDT 24
Finished Jul 31 06:09:38 PM PDT 24
Peak memory 213956 kb
Host smart-d2cffc9e-5bc4-4ea9-9d07-a268ab81adef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046396036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3046396036
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.3907175820
Short name T376
Test name
Test status
Simulation time 88731790 ps
CPU time 2.37 seconds
Started Jul 31 06:08:23 PM PDT 24
Finished Jul 31 06:08:26 PM PDT 24
Peak memory 213828 kb
Host smart-57086f2d-2064-4c0a-8f60-4e536ebf7edc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907175820 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.3907175820
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1778315759
Short name T427
Test name
Test status
Simulation time 470419279 ps
CPU time 5.15 seconds
Started Jul 31 06:08:28 PM PDT 24
Finished Jul 31 06:08:33 PM PDT 24
Peak memory 220296 kb
Host smart-5fa66709-da5f-422c-a2fe-4aa20046d3ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778315759 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1778315759
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1303163088
Short name T115
Test name
Test status
Simulation time 370064157 ps
CPU time 2.23 seconds
Started Jul 31 06:08:22 PM PDT 24
Finished Jul 31 06:08:25 PM PDT 24
Peak memory 213784 kb
Host smart-e984a60d-d6c8-4c22-857a-e0125345cd2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303163088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1303163088
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4064632714
Short name T310
Test name
Test status
Simulation time 25824055919 ps
CPU time 15.99 seconds
Started Jul 31 06:08:22 PM PDT 24
Finished Jul 31 06:08:38 PM PDT 24
Peak memory 205636 kb
Host smart-61688ce9-a0c3-4133-bf5c-448a250a1489
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064632714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.4064632714
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2393137425
Short name T320
Test name
Test status
Simulation time 24307868677 ps
CPU time 68.37 seconds
Started Jul 31 06:08:24 PM PDT 24
Finished Jul 31 06:09:33 PM PDT 24
Peak memory 205604 kb
Host smart-ba30339d-4ef6-431b-8d8b-61c7a1590564
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393137425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.2393137425
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2476320540
Short name T99
Test name
Test status
Simulation time 9677393635 ps
CPU time 24.8 seconds
Started Jul 31 06:08:24 PM PDT 24
Finished Jul 31 06:08:49 PM PDT 24
Peak memory 205660 kb
Host smart-504226a2-011d-4eb8-b899-3e8231a46ef4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476320540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2476320540
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1336942060
Short name T429
Test name
Test status
Simulation time 2713681694 ps
CPU time 5.46 seconds
Started Jul 31 06:08:23 PM PDT 24
Finished Jul 31 06:08:29 PM PDT 24
Peak memory 205648 kb
Host smart-9a3c68d5-e46c-49e9-aaa5-4c851e197e58
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336942060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
336942060
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.1710875277
Short name T68
Test name
Test status
Simulation time 1010158513 ps
CPU time 1.39 seconds
Started Jul 31 06:08:19 PM PDT 24
Finished Jul 31 06:08:20 PM PDT 24
Peak memory 205336 kb
Host smart-e60c74b1-5423-4ea7-b7a6-230afa4135fb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710875277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.1710875277
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.1376224949
Short name T464
Test name
Test status
Simulation time 7755155721 ps
CPU time 7.22 seconds
Started Jul 31 06:08:18 PM PDT 24
Finished Jul 31 06:08:25 PM PDT 24
Peak memory 205544 kb
Host smart-6bb07f87-6bb9-4b63-95a3-6bcf3f0c9787
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376224949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.1376224949
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3129217982
Short name T371
Test name
Test status
Simulation time 124154675 ps
CPU time 0.95 seconds
Started Jul 31 06:08:18 PM PDT 24
Finished Jul 31 06:08:19 PM PDT 24
Peak memory 205372 kb
Host smart-4ad0cd60-8b9b-4a9d-be43-88e8a9143ba3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129217982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3129217982
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2440064087
Short name T388
Test name
Test status
Simulation time 168157460 ps
CPU time 0.84 seconds
Started Jul 31 06:08:18 PM PDT 24
Finished Jul 31 06:08:19 PM PDT 24
Peak memory 205348 kb
Host smart-161e80e9-b51b-48cb-9963-f9dcb81abf7e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440064087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
440064087
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2211814238
Short name T397
Test name
Test status
Simulation time 165631609 ps
CPU time 0.78 seconds
Started Jul 31 06:08:22 PM PDT 24
Finished Jul 31 06:08:22 PM PDT 24
Peak memory 205412 kb
Host smart-e6464703-e2ff-4eb3-94c0-d88dec99fdd7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211814238 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2211814238
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.2649680525
Short name T329
Test name
Test status
Simulation time 74704282 ps
CPU time 0.68 seconds
Started Jul 31 06:08:23 PM PDT 24
Finished Jul 31 06:08:24 PM PDT 24
Peak memory 205316 kb
Host smart-a89f0f28-2a49-4c7e-bd85-e4638a8f4450
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649680525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.2649680525
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.860301507
Short name T120
Test name
Test status
Simulation time 172838119 ps
CPU time 3.88 seconds
Started Jul 31 06:08:28 PM PDT 24
Finished Jul 31 06:08:32 PM PDT 24
Peak memory 205688 kb
Host smart-bf7dce89-a70f-4e05-b6b6-844faf2463f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860301507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_c
sr_outstanding.860301507
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.190226304
Short name T65
Test name
Test status
Simulation time 18254520410 ps
CPU time 32.25 seconds
Started Jul 31 06:08:24 PM PDT 24
Finished Jul 31 06:08:56 PM PDT 24
Peak memory 222196 kb
Host smart-75a97627-accd-4437-994e-420349f43ccc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190226304 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.190226304
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2370045541
Short name T421
Test name
Test status
Simulation time 629744389 ps
CPU time 3.58 seconds
Started Jul 31 06:08:21 PM PDT 24
Finished Jul 31 06:08:25 PM PDT 24
Peak memory 213900 kb
Host smart-879cd3fe-1d34-41d4-9f70-fb3643bd684c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370045541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2370045541
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3075289394
Short name T163
Test name
Test status
Simulation time 1236600461 ps
CPU time 11.1 seconds
Started Jul 31 06:08:22 PM PDT 24
Finished Jul 31 06:08:33 PM PDT 24
Peak memory 213844 kb
Host smart-55be2c44-4dc8-4b10-9694-a3aa5dbfd138
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075289394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3075289394
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3439365805
Short name T352
Test name
Test status
Simulation time 211248721 ps
CPU time 4.7 seconds
Started Jul 31 06:08:33 PM PDT 24
Finished Jul 31 06:08:38 PM PDT 24
Peak memory 222092 kb
Host smart-e8a7662d-1ce6-472f-ad79-6374df137974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439365805 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3439365805
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.4037263145
Short name T94
Test name
Test status
Simulation time 480182152 ps
CPU time 2.56 seconds
Started Jul 31 06:08:34 PM PDT 24
Finished Jul 31 06:08:37 PM PDT 24
Peak memory 213736 kb
Host smart-857d9b43-2113-474c-b370-a84011ee7f23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037263145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.4037263145
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1921317939
Short name T430
Test name
Test status
Simulation time 81017519 ps
CPU time 0.86 seconds
Started Jul 31 06:08:27 PM PDT 24
Finished Jul 31 06:08:28 PM PDT 24
Peak memory 205296 kb
Host smart-3d234783-7faa-4f0e-ad22-d1174fc7488d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921317939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.1921317939
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2840466194
Short name T456
Test name
Test status
Simulation time 3123533535 ps
CPU time 5.44 seconds
Started Jul 31 06:08:25 PM PDT 24
Finished Jul 31 06:08:31 PM PDT 24
Peak memory 205540 kb
Host smart-431f2298-f9df-47c6-9aae-91401cc86759
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840466194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
840466194
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.777539014
Short name T323
Test name
Test status
Simulation time 261701366 ps
CPU time 1.37 seconds
Started Jul 31 06:08:26 PM PDT 24
Finished Jul 31 06:08:27 PM PDT 24
Peak memory 205348 kb
Host smart-796c8769-81ee-4962-8a55-4779b71e6a90
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777539014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.777539014
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1105877652
Short name T414
Test name
Test status
Simulation time 178330631 ps
CPU time 3.71 seconds
Started Jul 31 06:08:32 PM PDT 24
Finished Jul 31 06:08:36 PM PDT 24
Peak memory 205672 kb
Host smart-d6adccdb-a4c6-437c-8604-3ffb918dbe58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105877652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1105877652
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.2823264153
Short name T453
Test name
Test status
Simulation time 30349336378 ps
CPU time 234.29 seconds
Started Jul 31 06:08:27 PM PDT 24
Finished Jul 31 06:12:21 PM PDT 24
Peak memory 219748 kb
Host smart-3dfe4c1c-a68e-4a8e-ac03-75d603d0b04a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823264153 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.2823264153
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2907022534
Short name T327
Test name
Test status
Simulation time 155173012 ps
CPU time 3.29 seconds
Started Jul 31 06:08:28 PM PDT 24
Finished Jul 31 06:08:31 PM PDT 24
Peak memory 213868 kb
Host smart-5261df93-f239-48b1-b73f-7d361db31cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907022534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2907022534
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.707975996
Short name T432
Test name
Test status
Simulation time 304642521 ps
CPU time 3.88 seconds
Started Jul 31 06:08:36 PM PDT 24
Finished Jul 31 06:08:40 PM PDT 24
Peak memory 218724 kb
Host smart-67f2bb50-4b16-45b9-9734-c3bdc8af17d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707975996 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.707975996
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1875410240
Short name T113
Test name
Test status
Simulation time 214082002 ps
CPU time 2.34 seconds
Started Jul 31 06:08:34 PM PDT 24
Finished Jul 31 06:08:37 PM PDT 24
Peak memory 213724 kb
Host smart-c974f218-ced1-43ca-8bf2-bb01c7cd6293
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875410240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1875410240
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.598515124
Short name T366
Test name
Test status
Simulation time 4177952710 ps
CPU time 12.18 seconds
Started Jul 31 06:08:31 PM PDT 24
Finished Jul 31 06:08:44 PM PDT 24
Peak memory 205592 kb
Host smart-e82ca4df-1a9c-460b-b7cd-5ae03bb45c5f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598515124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.r
v_dm_jtag_dmi_csr_bit_bash.598515124
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2407390113
Short name T351
Test name
Test status
Simulation time 10666257348 ps
CPU time 29.31 seconds
Started Jul 31 06:08:34 PM PDT 24
Finished Jul 31 06:09:04 PM PDT 24
Peak memory 205656 kb
Host smart-bdcc2d85-41d5-4d4f-9adf-1a651e6a1720
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407390113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
407390113
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.1517872249
Short name T339
Test name
Test status
Simulation time 632141835 ps
CPU time 2.31 seconds
Started Jul 31 06:08:33 PM PDT 24
Finished Jul 31 06:08:35 PM PDT 24
Peak memory 205296 kb
Host smart-28014eb0-873d-4cae-a2c3-c2ac85f8d8da
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517872249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.1
517872249
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.680176917
Short name T111
Test name
Test status
Simulation time 2087801098 ps
CPU time 7.11 seconds
Started Jul 31 06:08:37 PM PDT 24
Finished Jul 31 06:08:44 PM PDT 24
Peak memory 205632 kb
Host smart-ed79e1ee-78e6-4a06-b944-0daa3b6920db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680176917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c
sr_outstanding.680176917
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1920875214
Short name T400
Test name
Test status
Simulation time 33514714256 ps
CPU time 80.75 seconds
Started Jul 31 06:08:33 PM PDT 24
Finished Jul 31 06:09:54 PM PDT 24
Peak memory 222192 kb
Host smart-82c6942d-a5d1-4390-ac87-06990c9e7cc5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920875214 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.1920875214
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.2363051488
Short name T449
Test name
Test status
Simulation time 88460516 ps
CPU time 2.93 seconds
Started Jul 31 06:08:37 PM PDT 24
Finished Jul 31 06:08:41 PM PDT 24
Peak memory 213836 kb
Host smart-788f1bca-83be-41d4-9647-437ecfb76db0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363051488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.2363051488
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3694019024
Short name T446
Test name
Test status
Simulation time 1332998741 ps
CPU time 11.15 seconds
Started Jul 31 06:08:33 PM PDT 24
Finished Jul 31 06:08:44 PM PDT 24
Peak memory 213896 kb
Host smart-8ee4623a-a6d9-412e-84db-ae12aa61e8ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694019024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3694019024
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3588424613
Short name T401
Test name
Test status
Simulation time 87911015 ps
CPU time 2.78 seconds
Started Jul 31 06:08:39 PM PDT 24
Finished Jul 31 06:08:41 PM PDT 24
Peak memory 218600 kb
Host smart-2283328b-b346-479f-a71e-0d7c9b4c1bd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588424613 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3588424613
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3565325600
Short name T92
Test name
Test status
Simulation time 114926391 ps
CPU time 1.54 seconds
Started Jul 31 06:08:40 PM PDT 24
Finished Jul 31 06:08:42 PM PDT 24
Peak memory 213780 kb
Host smart-d7e36fe0-f759-4415-92b8-992ad573e5b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565325600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3565325600
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2456391146
Short name T341
Test name
Test status
Simulation time 43766664561 ps
CPU time 116.97 seconds
Started Jul 31 06:08:36 PM PDT 24
Finished Jul 31 06:10:34 PM PDT 24
Peak memory 205604 kb
Host smart-d6feccdb-82d1-48a9-88c1-e7b7bc6c53c4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456391146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2456391146
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4122872053
Short name T380
Test name
Test status
Simulation time 2176718592 ps
CPU time 2.5 seconds
Started Jul 31 06:08:39 PM PDT 24
Finished Jul 31 06:08:41 PM PDT 24
Peak memory 205660 kb
Host smart-eaf97b0c-7bdb-4331-9e9a-b95bf0784c7e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122872053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.4
122872053
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1140349016
Short name T325
Test name
Test status
Simulation time 285040983 ps
CPU time 0.84 seconds
Started Jul 31 06:08:37 PM PDT 24
Finished Jul 31 06:08:38 PM PDT 24
Peak memory 205288 kb
Host smart-f0c8b520-d58c-4e0b-a2aa-a7b4a2412f65
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140349016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
140349016
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3829255217
Short name T121
Test name
Test status
Simulation time 672309628 ps
CPU time 4.55 seconds
Started Jul 31 06:08:38 PM PDT 24
Finished Jul 31 06:08:43 PM PDT 24
Peak memory 205444 kb
Host smart-0d48324d-a8fb-41b5-8fa0-a073cfd54ef8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829255217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3829255217
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.2226504225
Short name T394
Test name
Test status
Simulation time 21685303172 ps
CPU time 68.63 seconds
Started Jul 31 06:08:41 PM PDT 24
Finished Jul 31 06:09:50 PM PDT 24
Peak memory 222136 kb
Host smart-6cf5e0db-1734-4aff-ad04-73013e6da13a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226504225 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.2226504225
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2475689288
Short name T463
Test name
Test status
Simulation time 176225073 ps
CPU time 3.82 seconds
Started Jul 31 06:08:37 PM PDT 24
Finished Jul 31 06:08:41 PM PDT 24
Peak memory 213868 kb
Host smart-68e8d63c-57a9-422c-a77a-f1153f6e6407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475689288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2475689288
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.4251846623
Short name T375
Test name
Test status
Simulation time 1804628320 ps
CPU time 13.09 seconds
Started Jul 31 06:08:38 PM PDT 24
Finished Jul 31 06:08:52 PM PDT 24
Peak memory 213680 kb
Host smart-3dba695d-babc-4e6c-b450-f3e91c1b3a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251846623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.4251846623
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1321840205
Short name T331
Test name
Test status
Simulation time 1063172125 ps
CPU time 2.67 seconds
Started Jul 31 06:08:44 PM PDT 24
Finished Jul 31 06:08:47 PM PDT 24
Peak memory 213888 kb
Host smart-9e51f218-4d54-4dd8-a235-9baa4dd78837
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321840205 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1321840205
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3468199635
Short name T112
Test name
Test status
Simulation time 280847529 ps
CPU time 2.79 seconds
Started Jul 31 06:08:39 PM PDT 24
Finished Jul 31 06:08:42 PM PDT 24
Peak memory 213784 kb
Host smart-ae12d90c-a905-46b9-89e5-86265bcd5dc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468199635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3468199635
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.985863317
Short name T347
Test name
Test status
Simulation time 7677318150 ps
CPU time 21.5 seconds
Started Jul 31 06:08:42 PM PDT 24
Finished Jul 31 06:09:04 PM PDT 24
Peak memory 205588 kb
Host smart-d1e09a3a-dda6-4159-9019-e3531167c8fe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985863317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.r
v_dm_jtag_dmi_csr_bit_bash.985863317
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.549219084
Short name T322
Test name
Test status
Simulation time 2407262775 ps
CPU time 2.4 seconds
Started Jul 31 06:08:38 PM PDT 24
Finished Jul 31 06:08:41 PM PDT 24
Peak memory 205596 kb
Host smart-e95f538e-9531-4842-bbad-6b0eefb71605
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549219084 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.549219084
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.1357300991
Short name T415
Test name
Test status
Simulation time 439572229 ps
CPU time 0.84 seconds
Started Jul 31 06:08:38 PM PDT 24
Finished Jul 31 06:08:39 PM PDT 24
Peak memory 205312 kb
Host smart-fa2f7d0f-5ef3-4e39-aad3-35e69ebd5b96
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357300991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.1
357300991
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4046606300
Short name T100
Test name
Test status
Simulation time 505428463 ps
CPU time 4.33 seconds
Started Jul 31 06:08:43 PM PDT 24
Finished Jul 31 06:08:47 PM PDT 24
Peak memory 205656 kb
Host smart-42ed57bd-7c67-4bfa-afd3-2dd7bcec8051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046606300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.4046606300
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1775374512
Short name T171
Test name
Test status
Simulation time 42536934869 ps
CPU time 190.83 seconds
Started Jul 31 06:08:44 PM PDT 24
Finished Jul 31 06:11:54 PM PDT 24
Peak memory 222084 kb
Host smart-f335f971-6fd9-4ccd-9571-afe5546851bc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775374512 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1775374512
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2145336232
Short name T85
Test name
Test status
Simulation time 255554267 ps
CPU time 3.59 seconds
Started Jul 31 06:08:44 PM PDT 24
Finished Jul 31 06:08:48 PM PDT 24
Peak memory 213864 kb
Host smart-654e862d-fbea-4661-ad4a-46b41c39d658
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145336232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2145336232
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.4070134116
Short name T384
Test name
Test status
Simulation time 1576271154 ps
CPU time 11.43 seconds
Started Jul 31 06:08:40 PM PDT 24
Finished Jul 31 06:08:52 PM PDT 24
Peak memory 213828 kb
Host smart-80b09354-bc42-4984-a223-382aa9e0f381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070134116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.4070134116
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.660220183
Short name T428
Test name
Test status
Simulation time 326798058 ps
CPU time 2.59 seconds
Started Jul 31 06:08:50 PM PDT 24
Finished Jul 31 06:08:52 PM PDT 24
Peak memory 218328 kb
Host smart-96785a7b-77de-47f8-87f4-1c1c2a736f87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660220183 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.660220183
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3435041773
Short name T103
Test name
Test status
Simulation time 113841874 ps
CPU time 1.53 seconds
Started Jul 31 06:08:46 PM PDT 24
Finished Jul 31 06:08:48 PM PDT 24
Peak memory 213756 kb
Host smart-b63702ad-93e8-49be-8b8b-cb24477b9a34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435041773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3435041773
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.697600037
Short name T393
Test name
Test status
Simulation time 13810541500 ps
CPU time 16.16 seconds
Started Jul 31 06:08:46 PM PDT 24
Finished Jul 31 06:09:02 PM PDT 24
Peak memory 205584 kb
Host smart-3c8cbe9d-3318-4f2c-a2f7-28cd1c18654a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697600037 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.r
v_dm_jtag_dmi_csr_bit_bash.697600037
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2077415920
Short name T343
Test name
Test status
Simulation time 1776918443 ps
CPU time 2.55 seconds
Started Jul 31 06:08:43 PM PDT 24
Finished Jul 31 06:08:46 PM PDT 24
Peak memory 205496 kb
Host smart-1dad1403-65f3-448f-b5ba-8b088b0eaa25
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077415920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
077415920
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.2519781537
Short name T433
Test name
Test status
Simulation time 245077577 ps
CPU time 0.99 seconds
Started Jul 31 06:08:43 PM PDT 24
Finished Jul 31 06:08:45 PM PDT 24
Peak memory 205344 kb
Host smart-4024b5fe-ab0e-460f-98c1-55d0920ada5f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519781537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.2
519781537
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.805163866
Short name T107
Test name
Test status
Simulation time 1571208100 ps
CPU time 7.77 seconds
Started Jul 31 06:08:48 PM PDT 24
Finished Jul 31 06:08:55 PM PDT 24
Peak memory 205632 kb
Host smart-bfb33b9f-2603-47a6-8c91-c875c736d741
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805163866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_c
sr_outstanding.805163866
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2387073494
Short name T417
Test name
Test status
Simulation time 55145815088 ps
CPU time 39.23 seconds
Started Jul 31 06:08:47 PM PDT 24
Finished Jul 31 06:09:27 PM PDT 24
Peak memory 223084 kb
Host smart-8c382e31-34ea-406c-a137-93c8d6493a21
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387073494 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2387073494
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2729635621
Short name T410
Test name
Test status
Simulation time 496173269 ps
CPU time 3.01 seconds
Started Jul 31 06:08:47 PM PDT 24
Finished Jul 31 06:08:50 PM PDT 24
Peak memory 213840 kb
Host smart-e1ecaa85-42f5-44ba-b636-b9ba46b89954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729635621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2729635621
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2462759413
Short name T447
Test name
Test status
Simulation time 6082137533 ps
CPU time 24.19 seconds
Started Jul 31 06:08:48 PM PDT 24
Finished Jul 31 06:09:12 PM PDT 24
Peak memory 213968 kb
Host smart-51d3c058-21d2-4ac1-b60d-94f86635319a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462759413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2462759413
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.532935080
Short name T74
Test name
Test status
Simulation time 46293725 ps
CPU time 0.8 seconds
Started Jul 31 06:34:45 PM PDT 24
Finished Jul 31 06:34:46 PM PDT 24
Peak memory 205316 kb
Host smart-84251e6c-0367-4574-bbf7-347ac91d304a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532935080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.532935080
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.766445173
Short name T216
Test name
Test status
Simulation time 123108617191 ps
CPU time 53.12 seconds
Started Jul 31 06:34:04 PM PDT 24
Finished Jul 31 06:34:57 PM PDT 24
Peak memory 213964 kb
Host smart-73394cca-c3a4-489a-9e3e-bbe501c3bd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766445173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.766445173
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1049791794
Short name T17
Test name
Test status
Simulation time 272237253 ps
CPU time 1.45 seconds
Started Jul 31 06:34:07 PM PDT 24
Finished Jul 31 06:34:08 PM PDT 24
Peak memory 205340 kb
Host smart-d82ee646-3f3d-4c37-8e5b-3012a802eeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049791794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1049791794
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.463935300
Short name T41
Test name
Test status
Simulation time 286425848 ps
CPU time 1.08 seconds
Started Jul 31 06:34:21 PM PDT 24
Finished Jul 31 06:34:22 PM PDT 24
Peak memory 205300 kb
Host smart-0764f38e-2e14-476d-8e54-ae851f7dd2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463935300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.463935300
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.4236208223
Short name T211
Test name
Test status
Simulation time 196735517 ps
CPU time 1.16 seconds
Started Jul 31 06:34:06 PM PDT 24
Finished Jul 31 06:34:07 PM PDT 24
Peak memory 205308 kb
Host smart-85666d61-e813-479e-9149-3d9178ee5bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236208223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.4236208223
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2804792807
Short name T247
Test name
Test status
Simulation time 419111812 ps
CPU time 0.73 seconds
Started Jul 31 06:34:23 PM PDT 24
Finished Jul 31 06:34:24 PM PDT 24
Peak memory 205256 kb
Host smart-b69bf02f-d9f9-4acb-8b1f-cf8fa84f2560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804792807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2804792807
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.1240283929
Short name T70
Test name
Test status
Simulation time 61884824 ps
CPU time 0.88 seconds
Started Jul 31 06:34:36 PM PDT 24
Finished Jul 31 06:34:37 PM PDT 24
Peak memory 215512 kb
Host smart-1b11f0ba-2c41-4e41-9fee-2a5034d3fd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240283929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.1240283929
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.466793348
Short name T197
Test name
Test status
Simulation time 5079230547 ps
CPU time 5.1 seconds
Started Jul 31 06:33:57 PM PDT 24
Finished Jul 31 06:34:02 PM PDT 24
Peak memory 205736 kb
Host smart-6034f5b6-0bc1-4b75-b73f-a7cc2f37705f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466793348 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_tl
_access.466793348
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2467364371
Short name T49
Test name
Test status
Simulation time 424164638 ps
CPU time 1.01 seconds
Started Jul 31 06:34:23 PM PDT 24
Finished Jul 31 06:34:24 PM PDT 24
Peak memory 205276 kb
Host smart-56e2f3e1-393b-404a-85ff-b908369501dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467364371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2467364371
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.2232464836
Short name T212
Test name
Test status
Simulation time 844627332 ps
CPU time 2.81 seconds
Started Jul 31 06:34:20 PM PDT 24
Finished Jul 31 06:34:23 PM PDT 24
Peak memory 205164 kb
Host smart-e6b98744-fca1-4914-a30d-20dd68dea304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232464836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.2232464836
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.45443539
Short name T213
Test name
Test status
Simulation time 192968990 ps
CPU time 0.92 seconds
Started Jul 31 06:34:28 PM PDT 24
Finished Jul 31 06:34:29 PM PDT 24
Peak memory 205300 kb
Host smart-9c544837-872a-478c-970f-3a811fd7b143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45443539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.45443539
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.4063205213
Short name T281
Test name
Test status
Simulation time 2091002311 ps
CPU time 5.75 seconds
Started Jul 31 06:34:28 PM PDT 24
Finished Jul 31 06:34:34 PM PDT 24
Peak memory 205164 kb
Host smart-cf019567-9698-4920-aa79-15412061569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063205213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.4063205213
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.480588278
Short name T36
Test name
Test status
Simulation time 114697597 ps
CPU time 1.05 seconds
Started Jul 31 06:34:33 PM PDT 24
Finished Jul 31 06:34:34 PM PDT 24
Peak memory 205244 kb
Host smart-bf12a64c-42c5-4fcb-bbfb-32d5d59ac69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480588278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.480588278
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.860093388
Short name T140
Test name
Test status
Simulation time 278056598 ps
CPU time 1.39 seconds
Started Jul 31 06:34:30 PM PDT 24
Finished Jul 31 06:34:31 PM PDT 24
Peak memory 205252 kb
Host smart-a1581eaa-6e96-407b-92ef-215e683dbcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860093388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.860093388
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.1024919619
Short name T295
Test name
Test status
Simulation time 176358810 ps
CPU time 0.9 seconds
Started Jul 31 06:34:12 PM PDT 24
Finished Jul 31 06:34:13 PM PDT 24
Peak memory 205288 kb
Host smart-25b9bbf0-437e-43b0-885d-1e92b9a7a5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024919619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.1024919619
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.1526188364
Short name T123
Test name
Test status
Simulation time 2267684365 ps
CPU time 2.31 seconds
Started Jul 31 06:34:12 PM PDT 24
Finished Jul 31 06:34:14 PM PDT 24
Peak memory 205400 kb
Host smart-44e45037-7ff1-4b60-bddd-746fa3820ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526188364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.1526188364
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.4244339091
Short name T279
Test name
Test status
Simulation time 186796582 ps
CPU time 1.25 seconds
Started Jul 31 06:34:24 PM PDT 24
Finished Jul 31 06:34:25 PM PDT 24
Peak memory 213484 kb
Host smart-d45ec5ef-d3d1-4c2f-bd48-7c07f67cf2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244339091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.4244339091
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.1581953384
Short name T256
Test name
Test status
Simulation time 1272788475 ps
CPU time 2.45 seconds
Started Jul 31 06:34:37 PM PDT 24
Finished Jul 31 06:34:40 PM PDT 24
Peak memory 205220 kb
Host smart-48e73742-096c-40f8-ba54-afbd04785f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581953384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.1581953384
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3774457635
Short name T43
Test name
Test status
Simulation time 204052964 ps
CPU time 0.89 seconds
Started Jul 31 06:34:33 PM PDT 24
Finished Jul 31 06:34:34 PM PDT 24
Peak memory 213468 kb
Host smart-0decb2b7-dbfb-4592-b02f-f498783e4559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774457635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3774457635
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2319513403
Short name T282
Test name
Test status
Simulation time 1750171493 ps
CPU time 2.55 seconds
Started Jul 31 06:33:55 PM PDT 24
Finished Jul 31 06:33:58 PM PDT 24
Peak memory 205680 kb
Host smart-a3fb5435-7b95-4921-98f4-de26f853f835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319513403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2319513403
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3219001331
Short name T38
Test name
Test status
Simulation time 582617143 ps
CPU time 2.3 seconds
Started Jul 31 06:34:41 PM PDT 24
Finished Jul 31 06:34:44 PM PDT 24
Peak memory 229580 kb
Host smart-0ab084b7-96a0-407e-9cbb-17da121ae72e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219001331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3219001331
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3876184907
Short name T189
Test name
Test status
Simulation time 1594798277 ps
CPU time 1.78 seconds
Started Jul 31 06:33:51 PM PDT 24
Finished Jul 31 06:33:53 PM PDT 24
Peak memory 205304 kb
Host smart-a3a988d6-0f7f-46c0-82ae-56138ba03996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876184907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3876184907
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.1241367915
Short name T239
Test name
Test status
Simulation time 2611396886 ps
CPU time 4.78 seconds
Started Jul 31 06:34:37 PM PDT 24
Finished Jul 31 06:34:42 PM PDT 24
Peak memory 205576 kb
Host smart-e8305a2b-798b-4dfd-bf14-e6023a46bf1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241367915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.1241367915
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.4249210279
Short name T51
Test name
Test status
Simulation time 186017068 ps
CPU time 0.95 seconds
Started Jul 31 06:35:08 PM PDT 24
Finished Jul 31 06:35:09 PM PDT 24
Peak memory 205308 kb
Host smart-11d8c3ef-46d6-4b42-919b-297202729e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249210279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.4249210279
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1265698327
Short name T266
Test name
Test status
Simulation time 78866975 ps
CPU time 0.77 seconds
Started Jul 31 06:35:14 PM PDT 24
Finished Jul 31 06:35:14 PM PDT 24
Peak memory 205288 kb
Host smart-f5d32a2f-3e46-48ad-b88a-44b1c264ee2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265698327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1265698327
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.2140170395
Short name T291
Test name
Test status
Simulation time 5730738101 ps
CPU time 4.52 seconds
Started Jul 31 06:34:51 PM PDT 24
Finished Jul 31 06:34:56 PM PDT 24
Peak memory 213936 kb
Host smart-83e9d5a0-a9b5-4869-aedc-b182b2ff97ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140170395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.2140170395
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2735385351
Short name T230
Test name
Test status
Simulation time 4360491332 ps
CPU time 6.3 seconds
Started Jul 31 06:34:52 PM PDT 24
Finished Jul 31 06:34:58 PM PDT 24
Peak memory 213944 kb
Host smart-8959b355-950a-4e37-b9f8-2bb8a09a873b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735385351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2735385351
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.4137215573
Short name T7
Test name
Test status
Simulation time 857424615 ps
CPU time 3.03 seconds
Started Jul 31 06:34:49 PM PDT 24
Finished Jul 31 06:34:52 PM PDT 24
Peak memory 205296 kb
Host smart-380bbd4f-9029-4968-8fac-a6cddca7e7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137215573 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.4137215573
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1292923334
Short name T18
Test name
Test status
Simulation time 190433854 ps
CPU time 0.87 seconds
Started Jul 31 06:34:52 PM PDT 24
Finished Jul 31 06:34:53 PM PDT 24
Peak memory 205200 kb
Host smart-a1e622ca-b0fa-4001-9fd2-96280430897b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292923334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1292923334
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1814623767
Short name T217
Test name
Test status
Simulation time 500336031 ps
CPU time 1 seconds
Started Jul 31 06:34:49 PM PDT 24
Finished Jul 31 06:34:50 PM PDT 24
Peak memory 205208 kb
Host smart-e685a920-bf1a-43c9-a35d-8db9d97cebbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814623767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1814623767
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3682599885
Short name T302
Test name
Test status
Simulation time 184402380 ps
CPU time 0.74 seconds
Started Jul 31 06:35:00 PM PDT 24
Finished Jul 31 06:35:01 PM PDT 24
Peak memory 205276 kb
Host smart-9c4ecff0-54f4-4f2f-9812-c7d92a0a0793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682599885 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3682599885
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.1480835023
Short name T137
Test name
Test status
Simulation time 268219496 ps
CPU time 0.87 seconds
Started Jul 31 06:35:09 PM PDT 24
Finished Jul 31 06:35:10 PM PDT 24
Peak memory 215508 kb
Host smart-a0721633-e23c-46a2-a02f-2138c3db26ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480835023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.1480835023
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1958912254
Short name T159
Test name
Test status
Simulation time 899862181 ps
CPU time 3.45 seconds
Started Jul 31 06:34:44 PM PDT 24
Finished Jul 31 06:34:47 PM PDT 24
Peak memory 205640 kb
Host smart-20e385c8-7c3b-4b83-a3fb-2154bec3f251
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1958912254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.1958912254
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.874855603
Short name T181
Test name
Test status
Simulation time 177000836 ps
CPU time 0.95 seconds
Started Jul 31 06:35:00 PM PDT 24
Finished Jul 31 06:35:01 PM PDT 24
Peak memory 205300 kb
Host smart-e506a050-c392-409e-9519-2840b8e55e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874855603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.874855603
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2335788412
Short name T231
Test name
Test status
Simulation time 332054541 ps
CPU time 0.98 seconds
Started Jul 31 06:34:56 PM PDT 24
Finished Jul 31 06:34:57 PM PDT 24
Peak memory 205256 kb
Host smart-9c884449-7a04-4e04-8699-2cf2029bade1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335788412 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2335788412
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.991426071
Short name T301
Test name
Test status
Simulation time 430391398 ps
CPU time 1.74 seconds
Started Jul 31 06:35:04 PM PDT 24
Finished Jul 31 06:35:06 PM PDT 24
Peak memory 205168 kb
Host smart-d3c433c3-35ea-4600-b2da-991a034d521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991426071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.991426071
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3774288733
Short name T286
Test name
Test status
Simulation time 279162997 ps
CPU time 1.51 seconds
Started Jul 31 06:35:06 PM PDT 24
Finished Jul 31 06:35:08 PM PDT 24
Peak memory 205172 kb
Host smart-9a4c7618-5ef8-4b2e-8dc5-a64b898f0a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774288733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3774288733
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.3713603356
Short name T208
Test name
Test status
Simulation time 353211416 ps
CPU time 1.67 seconds
Started Jul 31 06:35:10 PM PDT 24
Finished Jul 31 06:35:12 PM PDT 24
Peak memory 205304 kb
Host smart-c931fa83-56dc-4292-acbc-0e6cde29e8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713603356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.3713603356
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.4110920014
Short name T196
Test name
Test status
Simulation time 702691613 ps
CPU time 2.45 seconds
Started Jul 31 06:35:10 PM PDT 24
Finished Jul 31 06:35:12 PM PDT 24
Peak memory 205252 kb
Host smart-15a1d453-b56a-4ab6-bc6a-07433bb99391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110920014 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.4110920014
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1864984688
Short name T250
Test name
Test status
Simulation time 497938558 ps
CPU time 1.36 seconds
Started Jul 31 06:34:56 PM PDT 24
Finished Jul 31 06:34:58 PM PDT 24
Peak memory 205288 kb
Host smart-21e647ce-2307-4866-bb98-5db8c22ebb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864984688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1864984688
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2569551565
Short name T127
Test name
Test status
Simulation time 1701358598 ps
CPU time 1.39 seconds
Started Jul 31 06:34:56 PM PDT 24
Finished Jul 31 06:34:58 PM PDT 24
Peak memory 205264 kb
Host smart-bc7e5ede-dadc-480f-ae25-03c28f936fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569551565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2569551565
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3473484374
Short name T1
Test name
Test status
Simulation time 425334802 ps
CPU time 1.92 seconds
Started Jul 31 06:35:05 PM PDT 24
Finished Jul 31 06:35:07 PM PDT 24
Peak memory 213480 kb
Host smart-351b2dff-f970-4c8f-a272-0730e1784c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473484374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3473484374
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.3656986878
Short name T55
Test name
Test status
Simulation time 392914067 ps
CPU time 1.9 seconds
Started Jul 31 06:35:09 PM PDT 24
Finished Jul 31 06:35:11 PM PDT 24
Peak memory 205304 kb
Host smart-0fc3e98b-caa2-472d-87c5-9269fb34288c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656986878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.3656986878
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.1633787104
Short name T139
Test name
Test status
Simulation time 4422458931 ps
CPU time 12.24 seconds
Started Jul 31 06:35:07 PM PDT 24
Finished Jul 31 06:35:20 PM PDT 24
Peak memory 205640 kb
Host smart-5a2d4b50-67fe-4f57-abb4-bd6e40b48153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633787104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.1633787104
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1829797823
Short name T275
Test name
Test status
Simulation time 5311197084 ps
CPU time 15.62 seconds
Started Jul 31 06:34:43 PM PDT 24
Finished Jul 31 06:34:59 PM PDT 24
Peak memory 214028 kb
Host smart-a1d2067a-91af-4d42-b12b-7a2029b13ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829797823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1829797823
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.3597349635
Short name T71
Test name
Test status
Simulation time 1125121116 ps
CPU time 1.35 seconds
Started Jul 31 06:35:13 PM PDT 24
Finished Jul 31 06:35:15 PM PDT 24
Peak memory 229556 kb
Host smart-c9934ffb-a1ca-4c91-bd90-a3505c362e14
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597349635 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.3597349635
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.3928433796
Short name T130
Test name
Test status
Simulation time 2275858315 ps
CPU time 3.59 seconds
Started Jul 31 06:34:48 PM PDT 24
Finished Jul 31 06:34:52 PM PDT 24
Peak memory 205568 kb
Host smart-1ecd129d-fec0-48c8-a72d-783e45f6f328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928433796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.3928433796
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.223897082
Short name T26
Test name
Test status
Simulation time 2281456032 ps
CPU time 7.37 seconds
Started Jul 31 06:35:15 PM PDT 24
Finished Jul 31 06:35:22 PM PDT 24
Peak memory 205608 kb
Host smart-3875360a-72b1-47d5-ba30-8eb0f552ba6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223897082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.223897082
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.959300330
Short name T218
Test name
Test status
Simulation time 80697811 ps
CPU time 0.76 seconds
Started Jul 31 06:36:19 PM PDT 24
Finished Jul 31 06:36:20 PM PDT 24
Peak memory 205156 kb
Host smart-889c8da8-e755-474f-925a-d90f264359c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959300330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.959300330
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1529121064
Short name T298
Test name
Test status
Simulation time 150397997748 ps
CPU time 138.84 seconds
Started Jul 31 06:36:19 PM PDT 24
Finished Jul 31 06:38:38 PM PDT 24
Peak memory 219332 kb
Host smart-02754f13-2b75-4ae6-87e8-7a2600488b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529121064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1529121064
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2337370145
Short name T145
Test name
Test status
Simulation time 2193088549 ps
CPU time 1.58 seconds
Started Jul 31 06:36:19 PM PDT 24
Finished Jul 31 06:36:21 PM PDT 24
Peak memory 214528 kb
Host smart-15ca2558-b049-4aad-ab05-23849f314643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337370145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2337370145
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1203135180
Short name T304
Test name
Test status
Simulation time 2233054154 ps
CPU time 7.03 seconds
Started Jul 31 06:36:21 PM PDT 24
Finished Jul 31 06:36:28 PM PDT 24
Peak memory 205812 kb
Host smart-024ac062-1f38-41fd-8ab0-86e1fb1612b6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203135180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1203135180
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1428196143
Short name T254
Test name
Test status
Simulation time 2573695495 ps
CPU time 7.32 seconds
Started Jul 31 06:36:12 PM PDT 24
Finished Jul 31 06:36:20 PM PDT 24
Peak memory 205772 kb
Host smart-c2bd97d2-c6aa-4f6b-a279-fa7c2d92ac0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428196143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1428196143
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2456174475
Short name T260
Test name
Test status
Simulation time 70942170 ps
CPU time 0.87 seconds
Started Jul 31 06:36:19 PM PDT 24
Finished Jul 31 06:36:20 PM PDT 24
Peak memory 205300 kb
Host smart-a896c94a-ec36-414e-ba66-88ed4b3fc209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456174475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2456174475
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3557972051
Short name T28
Test name
Test status
Simulation time 2206845342 ps
CPU time 4.74 seconds
Started Jul 31 06:36:20 PM PDT 24
Finished Jul 31 06:36:25 PM PDT 24
Peak memory 205724 kb
Host smart-1f7d78ea-f7f9-4bfd-b42d-ed72934665f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557972051 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3557972051
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.4229226591
Short name T13
Test name
Test status
Simulation time 5143328063 ps
CPU time 16.4 seconds
Started Jul 31 06:36:19 PM PDT 24
Finished Jul 31 06:36:36 PM PDT 24
Peak memory 213912 kb
Host smart-e2f1820e-9441-4225-a750-a18d3c2806ed
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229226591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.4229226591
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.475236889
Short name T204
Test name
Test status
Simulation time 3268259673 ps
CPU time 3.65 seconds
Started Jul 31 06:36:19 PM PDT 24
Finished Jul 31 06:36:23 PM PDT 24
Peak memory 214004 kb
Host smart-6892fbb6-5dae-4667-bcfc-a0c0e81baa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475236889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.475236889
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.3791977868
Short name T289
Test name
Test status
Simulation time 3195427145 ps
CPU time 5.55 seconds
Started Jul 31 06:36:21 PM PDT 24
Finished Jul 31 06:36:27 PM PDT 24
Peak memory 205532 kb
Host smart-94bbadfc-f245-44fb-924a-84d7f815aa41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791977868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.3791977868
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3392963366
Short name T80
Test name
Test status
Simulation time 209278431 ps
CPU time 0.75 seconds
Started Jul 31 06:36:24 PM PDT 24
Finished Jul 31 06:36:25 PM PDT 24
Peak memory 205292 kb
Host smart-ebb022b5-e42d-4c77-864d-5118c3d98eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392963366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3392963366
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.2603911727
Short name T267
Test name
Test status
Simulation time 8468185519 ps
CPU time 25.28 seconds
Started Jul 31 06:36:19 PM PDT 24
Finished Jul 31 06:36:45 PM PDT 24
Peak memory 213996 kb
Host smart-e177265d-343f-41dc-8450-34c048d5b08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603911727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.2603911727
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1043168019
Short name T77
Test name
Test status
Simulation time 1828257528 ps
CPU time 3.57 seconds
Started Jul 31 06:36:21 PM PDT 24
Finished Jul 31 06:36:25 PM PDT 24
Peak memory 213808 kb
Host smart-5176ed08-fdbe-46f9-a158-2297e25bd523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043168019 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1043168019
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.224367059
Short name T205
Test name
Test status
Simulation time 12129070295 ps
CPU time 10.66 seconds
Started Jul 31 06:36:20 PM PDT 24
Finished Jul 31 06:36:31 PM PDT 24
Peak memory 213904 kb
Host smart-e0d75bf4-3399-4b88-a68c-f0b96f043da7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224367059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.224367059
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2097805328
Short name T202
Test name
Test status
Simulation time 785136288 ps
CPU time 3.06 seconds
Started Jul 31 06:36:22 PM PDT 24
Finished Jul 31 06:36:25 PM PDT 24
Peak memory 205612 kb
Host smart-ee0c951d-ea8e-4ba3-92f4-3a25e2eb5328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097805328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2097805328
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.3319749793
Short name T131
Test name
Test status
Simulation time 1827903119 ps
CPU time 5.62 seconds
Started Jul 31 06:36:26 PM PDT 24
Finished Jul 31 06:36:32 PM PDT 24
Peak memory 205456 kb
Host smart-dd1126f4-fbbe-4227-9c04-d16801da4b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319749793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.3319749793
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.4032688099
Short name T209
Test name
Test status
Simulation time 190094840 ps
CPU time 0.93 seconds
Started Jul 31 06:36:31 PM PDT 24
Finished Jul 31 06:36:32 PM PDT 24
Peak memory 205288 kb
Host smart-994badff-8801-4e98-89cc-4b367acf4322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032688099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4032688099
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2336377212
Short name T253
Test name
Test status
Simulation time 13691881717 ps
CPU time 10.42 seconds
Started Jul 31 06:36:32 PM PDT 24
Finished Jul 31 06:36:42 PM PDT 24
Peak memory 213904 kb
Host smart-e5a889cc-2d25-49ee-a248-7a19fd6ab619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336377212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2336377212
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.696316853
Short name T79
Test name
Test status
Simulation time 5210896938 ps
CPU time 4.62 seconds
Started Jul 31 06:36:23 PM PDT 24
Finished Jul 31 06:36:28 PM PDT 24
Peak memory 205748 kb
Host smart-d54194c7-01c7-4ae3-9c22-9c5dd5f4ff6e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=696316853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.696316853
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3917859375
Short name T201
Test name
Test status
Simulation time 717406510 ps
CPU time 2.66 seconds
Started Jul 31 06:36:25 PM PDT 24
Finished Jul 31 06:36:28 PM PDT 24
Peak memory 213816 kb
Host smart-096288f0-7561-42e2-9a13-883a026e43e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917859375 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3917859375
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.350948542
Short name T280
Test name
Test status
Simulation time 6017624873 ps
CPU time 7.25 seconds
Started Jul 31 06:36:27 PM PDT 24
Finished Jul 31 06:36:34 PM PDT 24
Peak memory 213716 kb
Host smart-787d01c3-6524-4456-97f3-4e367e224c7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350948542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.350948542
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.613933173
Short name T214
Test name
Test status
Simulation time 63128849 ps
CPU time 0.84 seconds
Started Jul 31 06:36:35 PM PDT 24
Finished Jul 31 06:36:36 PM PDT 24
Peak memory 205304 kb
Host smart-0dc30e60-34f4-4d6b-b49f-5f8e657814f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613933173 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.613933173
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.380634248
Short name T271
Test name
Test status
Simulation time 16619515311 ps
CPU time 42.64 seconds
Started Jul 31 06:36:34 PM PDT 24
Finished Jul 31 06:37:17 PM PDT 24
Peak memory 213992 kb
Host smart-a2b1ec9a-337d-455e-a82b-fe7e9aba3fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380634248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.380634248
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2889373237
Short name T187
Test name
Test status
Simulation time 2097632764 ps
CPU time 1.55 seconds
Started Jul 31 06:36:35 PM PDT 24
Finished Jul 31 06:36:37 PM PDT 24
Peak memory 205616 kb
Host smart-c4ec0b61-f258-4bd1-a69c-583b31809049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889373237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2889373237
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1065462016
Short name T222
Test name
Test status
Simulation time 5125788745 ps
CPU time 8.57 seconds
Started Jul 31 06:36:33 PM PDT 24
Finished Jul 31 06:36:42 PM PDT 24
Peak memory 214032 kb
Host smart-a373e287-90cc-4049-af04-4d9de0053b56
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1065462016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1065462016
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.233154680
Short name T237
Test name
Test status
Simulation time 1885491250 ps
CPU time 5.96 seconds
Started Jul 31 06:36:36 PM PDT 24
Finished Jul 31 06:36:42 PM PDT 24
Peak memory 205668 kb
Host smart-e3aa3177-ee73-49ed-a83d-cb67a6a27b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233154680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.233154680
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.2359064808
Short name T290
Test name
Test status
Simulation time 4791361667 ps
CPU time 7.52 seconds
Started Jul 31 06:36:35 PM PDT 24
Finished Jul 31 06:36:43 PM PDT 24
Peak memory 213772 kb
Host smart-7c287e3b-d715-4943-87a0-cedd2c28745d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359064808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.2359064808
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.841149187
Short name T133
Test name
Test status
Simulation time 231885602 ps
CPU time 0.76 seconds
Started Jul 31 06:36:43 PM PDT 24
Finished Jul 31 06:36:44 PM PDT 24
Peak memory 205296 kb
Host smart-7d099ebc-54b6-464a-bdc1-3b006d0f6da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841149187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.841149187
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1469411748
Short name T29
Test name
Test status
Simulation time 3434653432 ps
CPU time 10.71 seconds
Started Jul 31 06:36:40 PM PDT 24
Finished Jul 31 06:36:50 PM PDT 24
Peak memory 213832 kb
Host smart-43a52078-112e-43bc-98f0-2314d716d5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469411748 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1469411748
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3565118815
Short name T150
Test name
Test status
Simulation time 8801364091 ps
CPU time 7.5 seconds
Started Jul 31 06:36:34 PM PDT 24
Finished Jul 31 06:36:42 PM PDT 24
Peak memory 213952 kb
Host smart-a33820f8-fb5b-46df-aea7-eeb7e37b22f4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3565118815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3565118815
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.3579421271
Short name T135
Test name
Test status
Simulation time 4534482516 ps
CPU time 7.15 seconds
Started Jul 31 06:36:34 PM PDT 24
Finished Jul 31 06:36:41 PM PDT 24
Peak memory 205624 kb
Host smart-daf8d00d-ea63-4827-b428-733e31fd2a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579421271 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3579421271
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.4165971847
Short name T27
Test name
Test status
Simulation time 2271085366 ps
CPU time 6.09 seconds
Started Jul 31 06:36:46 PM PDT 24
Finished Jul 31 06:36:52 PM PDT 24
Peak memory 213804 kb
Host smart-c5564e3f-7ba4-4a67-b9ad-0155830a7564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165971847 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.4165971847
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3784697638
Short name T296
Test name
Test status
Simulation time 51974431 ps
CPU time 0.75 seconds
Started Jul 31 06:36:44 PM PDT 24
Finished Jul 31 06:36:45 PM PDT 24
Peak memory 205268 kb
Host smart-39ef5fa5-ec9a-412e-9943-504ae20d0a21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784697638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3784697638
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3088724607
Short name T228
Test name
Test status
Simulation time 22462654715 ps
CPU time 17.41 seconds
Started Jul 31 06:36:45 PM PDT 24
Finished Jul 31 06:37:02 PM PDT 24
Peak memory 222156 kb
Host smart-1a587ac9-5a82-4171-8abd-dcba4270a80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088724607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3088724607
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.884332035
Short name T129
Test name
Test status
Simulation time 6524899639 ps
CPU time 10.87 seconds
Started Jul 31 06:36:47 PM PDT 24
Finished Jul 31 06:36:58 PM PDT 24
Peak memory 213920 kb
Host smart-552879ad-0bda-480d-b0c4-c610ea13cdac
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=884332035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.884332035
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2823288159
Short name T274
Test name
Test status
Simulation time 717886916 ps
CPU time 1.23 seconds
Started Jul 31 06:36:45 PM PDT 24
Finished Jul 31 06:36:46 PM PDT 24
Peak memory 205676 kb
Host smart-7df66af2-9e60-436b-9f59-4d5ab1494288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823288159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2823288159
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.387146399
Short name T54
Test name
Test status
Simulation time 4741513606 ps
CPU time 4.27 seconds
Started Jul 31 06:36:43 PM PDT 24
Finished Jul 31 06:36:48 PM PDT 24
Peak memory 205560 kb
Host smart-f86f58c0-ae69-486e-8cb5-2e229e3917e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387146399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.387146399
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2722146559
Short name T241
Test name
Test status
Simulation time 96489352 ps
CPU time 0.85 seconds
Started Jul 31 06:36:57 PM PDT 24
Finished Jul 31 06:36:58 PM PDT 24
Peak memory 205348 kb
Host smart-e4ae7116-8bf7-4897-868b-68def12e9af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722146559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2722146559
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.3756683729
Short name T233
Test name
Test status
Simulation time 24758808607 ps
CPU time 14.08 seconds
Started Jul 31 06:36:51 PM PDT 24
Finished Jul 31 06:37:05 PM PDT 24
Peak memory 213956 kb
Host smart-ebc4aa5c-579a-4822-9266-bd373a56b2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756683729 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.3756683729
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1406617492
Short name T149
Test name
Test status
Simulation time 1646124912 ps
CPU time 4.98 seconds
Started Jul 31 06:36:48 PM PDT 24
Finished Jul 31 06:36:54 PM PDT 24
Peak memory 205576 kb
Host smart-e3215d91-6b21-4183-b2bc-b9e8a7652a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406617492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1406617492
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1533719711
Short name T240
Test name
Test status
Simulation time 8264084427 ps
CPU time 24.14 seconds
Started Jul 31 06:36:50 PM PDT 24
Finished Jul 31 06:37:14 PM PDT 24
Peak memory 213976 kb
Host smart-5147c4d9-680b-4c03-bbd5-2000157a590f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1533719711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1533719711
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.2977943152
Short name T206
Test name
Test status
Simulation time 2559581251 ps
CPU time 2.89 seconds
Started Jul 31 06:36:52 PM PDT 24
Finished Jul 31 06:36:55 PM PDT 24
Peak memory 205708 kb
Host smart-289c4b3a-11cf-4a47-88c3-8f455819bd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977943152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.2977943152
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.2957558878
Short name T47
Test name
Test status
Simulation time 2198804844 ps
CPU time 1.75 seconds
Started Jul 31 06:36:53 PM PDT 24
Finished Jul 31 06:36:55 PM PDT 24
Peak memory 213808 kb
Host smart-78711e24-de2b-4ee2-b44d-9a8ed66e1f54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957558878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2957558878
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.119460882
Short name T263
Test name
Test status
Simulation time 66245330 ps
CPU time 0.76 seconds
Started Jul 31 06:36:54 PM PDT 24
Finished Jul 31 06:36:54 PM PDT 24
Peak memory 205224 kb
Host smart-2df9d2a9-ead8-4e28-94bc-317f80508883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119460882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.119460882
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2153414116
Short name T75
Test name
Test status
Simulation time 1137107695 ps
CPU time 2.03 seconds
Started Jul 31 06:36:55 PM PDT 24
Finished Jul 31 06:36:57 PM PDT 24
Peak memory 205916 kb
Host smart-bf31fdfe-0b61-441b-a8c7-d7279bb06836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153414116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2153414116
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.190708470
Short name T151
Test name
Test status
Simulation time 9214857245 ps
CPU time 25.86 seconds
Started Jul 31 06:36:54 PM PDT 24
Finished Jul 31 06:37:20 PM PDT 24
Peak memory 213904 kb
Host smart-8aed26c1-2600-40ad-af99-10a3f98cbce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190708470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.190708470
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.3678425893
Short name T194
Test name
Test status
Simulation time 4368091299 ps
CPU time 4.22 seconds
Started Jul 31 06:36:58 PM PDT 24
Finished Jul 31 06:37:02 PM PDT 24
Peak memory 205784 kb
Host smart-a8c50095-dde1-4f48-b2c7-57a90ced3a5a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3678425893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.3678425893
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.2422131769
Short name T15
Test name
Test status
Simulation time 3422225991 ps
CPU time 9.96 seconds
Started Jul 31 06:36:52 PM PDT 24
Finished Jul 31 06:37:02 PM PDT 24
Peak memory 205704 kb
Host smart-5b41018f-852a-4e5d-bcac-3eacc58fc137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422131769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.2422131769
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.3478807197
Short name T12
Test name
Test status
Simulation time 2700390340 ps
CPU time 1.76 seconds
Started Jul 31 06:36:54 PM PDT 24
Finished Jul 31 06:36:56 PM PDT 24
Peak memory 213756 kb
Host smart-e124cde5-3436-43f5-961a-099dfe9803ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478807197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.3478807197
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3434128075
Short name T252
Test name
Test status
Simulation time 32427318 ps
CPU time 0.73 seconds
Started Jul 31 06:36:58 PM PDT 24
Finished Jul 31 06:36:58 PM PDT 24
Peak memory 205280 kb
Host smart-7340a490-c7ac-43f8-b04b-4956029d5db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434128075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3434128075
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.44860837
Short name T272
Test name
Test status
Simulation time 32868340569 ps
CPU time 34.24 seconds
Started Jul 31 06:37:04 PM PDT 24
Finished Jul 31 06:37:39 PM PDT 24
Peak memory 213988 kb
Host smart-9af92483-fbd4-4197-a0aa-e6a3a849bb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44860837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.44860837
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3533428299
Short name T128
Test name
Test status
Simulation time 8989569223 ps
CPU time 25.1 seconds
Started Jul 31 06:36:58 PM PDT 24
Finished Jul 31 06:37:23 PM PDT 24
Peak memory 205812 kb
Host smart-6bd0db06-3352-4ee9-9f07-b3add3f2e0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533428299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3533428299
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1435706899
Short name T226
Test name
Test status
Simulation time 987312465 ps
CPU time 3.22 seconds
Started Jul 31 06:37:00 PM PDT 24
Finished Jul 31 06:37:03 PM PDT 24
Peak memory 205736 kb
Host smart-77120786-d723-43f3-b3cf-51210bea0bc8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435706899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1435706899
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.1258972647
Short name T232
Test name
Test status
Simulation time 3842002389 ps
CPU time 2.98 seconds
Started Jul 31 06:36:57 PM PDT 24
Finished Jul 31 06:37:00 PM PDT 24
Peak memory 213920 kb
Host smart-ae0bfdeb-2099-4395-8e18-ac106748bd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258972647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.1258972647
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.291413960
Short name T234
Test name
Test status
Simulation time 7127372007 ps
CPU time 6.86 seconds
Started Jul 31 06:36:58 PM PDT 24
Finished Jul 31 06:37:05 PM PDT 24
Peak memory 205580 kb
Host smart-f8315772-738c-4c9b-95b2-17def3dd673f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291413960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.291413960
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3393593500
Short name T210
Test name
Test status
Simulation time 35096049 ps
CPU time 0.73 seconds
Started Jul 31 06:35:30 PM PDT 24
Finished Jul 31 06:35:31 PM PDT 24
Peak memory 205228 kb
Host smart-11dbc3dc-32b2-43fc-80b5-6e3573b126b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393593500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3393593500
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.3243642381
Short name T180
Test name
Test status
Simulation time 12112207124 ps
CPU time 17.16 seconds
Started Jul 31 06:35:22 PM PDT 24
Finished Jul 31 06:35:39 PM PDT 24
Peak memory 213916 kb
Host smart-134eb237-fd87-444b-b219-dc1c6c7ae441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243642381 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.3243642381
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.1879318020
Short name T142
Test name
Test status
Simulation time 845463678 ps
CPU time 1.85 seconds
Started Jul 31 06:35:16 PM PDT 24
Finished Jul 31 06:35:18 PM PDT 24
Peak memory 213904 kb
Host smart-386c5077-10c5-4fcd-90ca-f244ba66db53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879318020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.1879318020
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1517314526
Short name T248
Test name
Test status
Simulation time 2623247422 ps
CPU time 2.91 seconds
Started Jul 31 06:35:18 PM PDT 24
Finished Jul 31 06:35:21 PM PDT 24
Peak memory 205736 kb
Host smart-9dd5f182-f564-4030-8001-36571573f0f3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1517314526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1517314526
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.1460101443
Short name T53
Test name
Test status
Simulation time 585123033 ps
CPU time 1.14 seconds
Started Jul 31 06:35:22 PM PDT 24
Finished Jul 31 06:35:24 PM PDT 24
Peak memory 205296 kb
Host smart-8939996a-9b71-4ae5-9a2f-dcad668c3be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460101443 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.1460101443
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.108721086
Short name T37
Test name
Test status
Simulation time 263300826 ps
CPU time 0.91 seconds
Started Jul 31 06:35:22 PM PDT 24
Finished Jul 31 06:35:23 PM PDT 24
Peak memory 205308 kb
Host smart-3c84773c-a4a0-4a22-812b-fc42cd6c07c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108721086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.108721086
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.2340117965
Short name T294
Test name
Test status
Simulation time 912835935 ps
CPU time 2.43 seconds
Started Jul 31 06:35:14 PM PDT 24
Finished Jul 31 06:35:16 PM PDT 24
Peak memory 205692 kb
Host smart-ec8937ac-405e-4f9b-b4dd-b8ab76d489ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340117965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.2340117965
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1867503252
Short name T58
Test name
Test status
Simulation time 951722438 ps
CPU time 3.58 seconds
Started Jul 31 06:35:26 PM PDT 24
Finished Jul 31 06:35:30 PM PDT 24
Peak memory 229664 kb
Host smart-1aa53280-9731-4633-9e59-747b04a20588
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867503252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1867503252
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.3741284113
Short name T285
Test name
Test status
Simulation time 2408283102 ps
CPU time 4.1 seconds
Started Jul 31 06:35:21 PM PDT 24
Finished Jul 31 06:35:26 PM PDT 24
Peak memory 213708 kb
Host smart-1b3b6c39-5c81-4f2e-b1d0-f706586672ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741284113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.3741284113
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.1540774473
Short name T61
Test name
Test status
Simulation time 795264715141 ps
CPU time 2145.66 seconds
Started Jul 31 06:35:26 PM PDT 24
Finished Jul 31 07:11:12 PM PDT 24
Peak memory 249780 kb
Host smart-c50d0347-f792-41cc-a784-075c24d58cfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540774473 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.1540774473
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.682508848
Short name T270
Test name
Test status
Simulation time 114225745 ps
CPU time 0.88 seconds
Started Jul 31 06:36:59 PM PDT 24
Finished Jul 31 06:37:00 PM PDT 24
Peak memory 205320 kb
Host smart-ecc1d3db-5bf8-4673-9621-55e4cb121069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682508848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.682508848
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.2668652419
Short name T44
Test name
Test status
Simulation time 2725899589 ps
CPU time 4.3 seconds
Started Jul 31 06:36:59 PM PDT 24
Finished Jul 31 06:37:03 PM PDT 24
Peak memory 213700 kb
Host smart-5425a3b8-18c8-4f08-adec-9bcef18e0b52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668652419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.2668652419
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.682434072
Short name T175
Test name
Test status
Simulation time 78328992 ps
CPU time 0.87 seconds
Started Jul 31 06:37:07 PM PDT 24
Finished Jul 31 06:37:08 PM PDT 24
Peak memory 205288 kb
Host smart-260c92b1-e3ad-41e8-93b6-12d209f3aa5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682434072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.682434072
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.51117106
Short name T220
Test name
Test status
Simulation time 3662528305 ps
CPU time 2.95 seconds
Started Jul 31 06:37:00 PM PDT 24
Finished Jul 31 06:37:03 PM PDT 24
Peak memory 213668 kb
Host smart-5fe4e75a-15bd-4095-8a2e-fad94c9fd713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51117106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.51117106
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1109067174
Short name T246
Test name
Test status
Simulation time 41777520 ps
CPU time 0.73 seconds
Started Jul 31 06:37:06 PM PDT 24
Finished Jul 31 06:37:07 PM PDT 24
Peak memory 205288 kb
Host smart-9bb59b09-5395-4dfd-b48f-4d6b71ecef4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109067174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1109067174
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.1110173439
Short name T122
Test name
Test status
Simulation time 8140427994 ps
CPU time 7.78 seconds
Started Jul 31 06:37:04 PM PDT 24
Finished Jul 31 06:37:12 PM PDT 24
Peak memory 205580 kb
Host smart-b8823f0a-2173-4b16-bf81-b4b268a7f850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110173439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.1110173439
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2236787440
Short name T185
Test name
Test status
Simulation time 41651030 ps
CPU time 0.8 seconds
Started Jul 31 06:37:05 PM PDT 24
Finished Jul 31 06:37:06 PM PDT 24
Peak memory 205308 kb
Host smart-844c79db-3fa4-4638-a947-ba059590428f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236787440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2236787440
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.2745793504
Short name T283
Test name
Test status
Simulation time 4382546088 ps
CPU time 13.34 seconds
Started Jul 31 06:37:05 PM PDT 24
Finished Jul 31 06:37:18 PM PDT 24
Peak memory 213780 kb
Host smart-1a282bdf-7384-4eff-8df9-894a2d81c402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745793504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.2745793504
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.4076835124
Short name T264
Test name
Test status
Simulation time 157622081 ps
CPU time 0.75 seconds
Started Jul 31 06:37:05 PM PDT 24
Finished Jul 31 06:37:05 PM PDT 24
Peak memory 205268 kb
Host smart-d604ec15-8c50-47dd-a54f-24554ac02617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076835124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.4076835124
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.523265146
Short name T4
Test name
Test status
Simulation time 5738414366 ps
CPU time 16.42 seconds
Started Jul 31 06:37:04 PM PDT 24
Finished Jul 31 06:37:21 PM PDT 24
Peak memory 213752 kb
Host smart-43f9ba2f-1a6a-4026-add7-036e3e42e1b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523265146 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.523265146
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.231892600
Short name T190
Test name
Test status
Simulation time 107126518 ps
CPU time 0.81 seconds
Started Jul 31 06:37:10 PM PDT 24
Finished Jul 31 06:37:11 PM PDT 24
Peak memory 205300 kb
Host smart-6a5e7b39-790f-4204-9c1b-d5c80a20870b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231892600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.231892600
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2032786818
Short name T157
Test name
Test status
Simulation time 2873915928 ps
CPU time 3.78 seconds
Started Jul 31 06:37:05 PM PDT 24
Finished Jul 31 06:37:09 PM PDT 24
Peak memory 213780 kb
Host smart-2e78bf0e-5c9b-4194-b6e5-381f9b38b6bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032786818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2032786818
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1921754481
Short name T255
Test name
Test status
Simulation time 49966701 ps
CPU time 0.79 seconds
Started Jul 31 06:37:09 PM PDT 24
Finished Jul 31 06:37:10 PM PDT 24
Peak memory 205320 kb
Host smart-c09afa85-04b0-4947-afee-37157a3fb2e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921754481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1921754481
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.4055969366
Short name T156
Test name
Test status
Simulation time 4491803493 ps
CPU time 7.58 seconds
Started Jul 31 06:37:10 PM PDT 24
Finished Jul 31 06:37:17 PM PDT 24
Peak memory 205608 kb
Host smart-6d5cde12-2d4e-4750-a123-2f144687dde7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055969366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.4055969366
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1749577403
Short name T273
Test name
Test status
Simulation time 70471900 ps
CPU time 0.72 seconds
Started Jul 31 06:37:09 PM PDT 24
Finished Jul 31 06:37:10 PM PDT 24
Peak memory 205284 kb
Host smart-e89a8041-0d39-4d8e-91b4-49c3b0132eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749577403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1749577403
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.1434651694
Short name T21
Test name
Test status
Simulation time 5856922456 ps
CPU time 5.05 seconds
Started Jul 31 06:37:10 PM PDT 24
Finished Jul 31 06:37:15 PM PDT 24
Peak memory 213760 kb
Host smart-39f9b350-cb9e-4666-adc5-b687944a4373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434651694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.1434651694
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.396343418
Short name T136
Test name
Test status
Simulation time 103019039 ps
CPU time 0.74 seconds
Started Jul 31 06:37:09 PM PDT 24
Finished Jul 31 06:37:10 PM PDT 24
Peak memory 205300 kb
Host smart-8b28dbc2-e5e8-47f6-8371-6a2d17cf2df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396343418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.396343418
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.155172410
Short name T132
Test name
Test status
Simulation time 3616928349 ps
CPU time 10.52 seconds
Started Jul 31 06:37:11 PM PDT 24
Finished Jul 31 06:37:22 PM PDT 24
Peak memory 213860 kb
Host smart-e68d78a3-626b-4592-95e4-c4b4f6383ea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155172410 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.155172410
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.1800103965
Short name T178
Test name
Test status
Simulation time 166983394 ps
CPU time 0.89 seconds
Started Jul 31 06:37:10 PM PDT 24
Finished Jul 31 06:37:11 PM PDT 24
Peak memory 205244 kb
Host smart-7e78f064-7548-4136-8318-5a496ec1b1dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800103965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.1800103965
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.2625671140
Short name T244
Test name
Test status
Simulation time 2454746995 ps
CPU time 3 seconds
Started Jul 31 06:37:11 PM PDT 24
Finished Jul 31 06:37:14 PM PDT 24
Peak memory 213812 kb
Host smart-11ae9adc-a666-4dc0-b6e5-44f09cf4a184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625671140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.2625671140
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.3508778701
Short name T183
Test name
Test status
Simulation time 94449864 ps
CPU time 0.89 seconds
Started Jul 31 06:35:32 PM PDT 24
Finished Jul 31 06:35:33 PM PDT 24
Peak memory 205264 kb
Host smart-96e4f363-b527-4d9a-8444-f7c568dcf379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508778701 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.3508778701
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.3208815700
Short name T268
Test name
Test status
Simulation time 19554527523 ps
CPU time 26.77 seconds
Started Jul 31 06:35:29 PM PDT 24
Finished Jul 31 06:35:56 PM PDT 24
Peak memory 213932 kb
Host smart-7252a22a-4739-4c15-bede-0bca112a13b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208815700 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.3208815700
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3302857199
Short name T76
Test name
Test status
Simulation time 13319723197 ps
CPU time 10.81 seconds
Started Jul 31 06:35:31 PM PDT 24
Finished Jul 31 06:35:42 PM PDT 24
Peak memory 222064 kb
Host smart-18324279-14e4-4c1b-aaab-0ac6b9eb3daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302857199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3302857199
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3716483040
Short name T143
Test name
Test status
Simulation time 4492329560 ps
CPU time 12.65 seconds
Started Jul 31 06:35:34 PM PDT 24
Finished Jul 31 06:35:47 PM PDT 24
Peak memory 205668 kb
Host smart-ac508c6a-2e16-4fb9-b37e-e5996e240f82
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716483040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3716483040
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.3522784709
Short name T174
Test name
Test status
Simulation time 314300473 ps
CPU time 1 seconds
Started Jul 31 06:35:34 PM PDT 24
Finished Jul 31 06:35:35 PM PDT 24
Peak memory 205232 kb
Host smart-78263a0e-5447-42b8-a208-89586ef41b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522784709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.3522784709
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1834301807
Short name T277
Test name
Test status
Simulation time 1304893469 ps
CPU time 2.49 seconds
Started Jul 31 06:35:32 PM PDT 24
Finished Jul 31 06:35:35 PM PDT 24
Peak memory 205220 kb
Host smart-ae34bd86-7442-4b8b-af23-cd498267c78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834301807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1834301807
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.2273495915
Short name T78
Test name
Test status
Simulation time 4138594991 ps
CPU time 4.59 seconds
Started Jul 31 06:35:32 PM PDT 24
Finished Jul 31 06:35:36 PM PDT 24
Peak memory 205816 kb
Host smart-d7c6502c-8bd5-4462-aabf-642298892f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273495915 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.2273495915
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.997480312
Short name T72
Test name
Test status
Simulation time 716124413 ps
CPU time 1.77 seconds
Started Jul 31 06:35:36 PM PDT 24
Finished Jul 31 06:35:38 PM PDT 24
Peak memory 229864 kb
Host smart-c809f782-5de0-4bd1-a418-ed46e939bb08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997480312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.997480312
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.172113854
Short name T152
Test name
Test status
Simulation time 4698365141 ps
CPU time 4.57 seconds
Started Jul 31 06:35:33 PM PDT 24
Finished Jul 31 06:35:37 PM PDT 24
Peak memory 205584 kb
Host smart-0a4cceec-4405-4d4f-9296-e44c65ae964e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172113854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.172113854
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2522053754
Short name T243
Test name
Test status
Simulation time 61484801 ps
CPU time 0.84 seconds
Started Jul 31 06:37:15 PM PDT 24
Finished Jul 31 06:37:16 PM PDT 24
Peak memory 205212 kb
Host smart-38cbc8ac-3449-4ed3-a0ba-896ac5535ce4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522053754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2522053754
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.4001647945
Short name T46
Test name
Test status
Simulation time 2849578016 ps
CPU time 5.03 seconds
Started Jul 31 06:37:14 PM PDT 24
Finished Jul 31 06:37:19 PM PDT 24
Peak memory 213760 kb
Host smart-699a1ae9-ac37-4057-9d4c-6d8edcd40507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001647945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.4001647945
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.3071040160
Short name T293
Test name
Test status
Simulation time 58907537 ps
CPU time 0.7 seconds
Started Jul 31 06:37:25 PM PDT 24
Finished Jul 31 06:37:26 PM PDT 24
Peak memory 205296 kb
Host smart-3c28a45d-3ade-4da6-b16e-1f648a315a49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071040160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.3071040160
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.2842307440
Short name T24
Test name
Test status
Simulation time 3163905085 ps
CPU time 4.69 seconds
Started Jul 31 06:37:16 PM PDT 24
Finished Jul 31 06:37:20 PM PDT 24
Peak memory 205636 kb
Host smart-177b3342-9f0f-4cd2-9f50-44eed674d3ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842307440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.2842307440
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3120987849
Short name T297
Test name
Test status
Simulation time 32737089 ps
CPU time 0.74 seconds
Started Jul 31 06:37:21 PM PDT 24
Finished Jul 31 06:37:22 PM PDT 24
Peak memory 205236 kb
Host smart-45cf6d5b-3d4d-4bed-90db-a06b0d086e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120987849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3120987849
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.458733892
Short name T192
Test name
Test status
Simulation time 34632336 ps
CPU time 0.76 seconds
Started Jul 31 06:37:20 PM PDT 24
Finished Jul 31 06:37:21 PM PDT 24
Peak memory 205300 kb
Host smart-e4c8b561-252a-40f5-94a3-ffde5837eeaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458733892 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.458733892
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.647655929
Short name T23
Test name
Test status
Simulation time 3190839632 ps
CPU time 3.78 seconds
Started Jul 31 06:37:21 PM PDT 24
Finished Jul 31 06:37:24 PM PDT 24
Peak memory 205596 kb
Host smart-fbe5cfbd-30a9-41e5-9c71-22be8e515d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647655929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.647655929
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.249439935
Short name T188
Test name
Test status
Simulation time 86252817 ps
CPU time 0.72 seconds
Started Jul 31 06:37:24 PM PDT 24
Finished Jul 31 06:37:25 PM PDT 24
Peak memory 205304 kb
Host smart-7c0f506c-739d-4bbb-aada-bac923f25000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249439935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.249439935
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.2683117478
Short name T30
Test name
Test status
Simulation time 3708735143 ps
CPU time 10.98 seconds
Started Jul 31 06:37:23 PM PDT 24
Finished Jul 31 06:37:34 PM PDT 24
Peak memory 213856 kb
Host smart-e7c4171b-e535-45c1-bf80-b78228858406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683117478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.2683117478
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.734842842
Short name T193
Test name
Test status
Simulation time 154567942 ps
CPU time 1.04 seconds
Started Jul 31 06:37:21 PM PDT 24
Finished Jul 31 06:37:22 PM PDT 24
Peak memory 205300 kb
Host smart-795d888b-269a-4b6d-80d5-037139a03779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734842842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.734842842
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.1479168222
Short name T219
Test name
Test status
Simulation time 2684827777 ps
CPU time 3.58 seconds
Started Jul 31 06:37:21 PM PDT 24
Finished Jul 31 06:37:25 PM PDT 24
Peak memory 213740 kb
Host smart-217db6a1-0666-486f-b53c-d24ca0e18fd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479168222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.1479168222
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.174117291
Short name T229
Test name
Test status
Simulation time 91168280 ps
CPU time 0.87 seconds
Started Jul 31 06:37:22 PM PDT 24
Finished Jul 31 06:37:23 PM PDT 24
Peak memory 205264 kb
Host smart-b344a1bd-4986-4325-8796-8ce6259ad775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174117291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.174117291
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.1703062242
Short name T153
Test name
Test status
Simulation time 2132158223 ps
CPU time 3.84 seconds
Started Jul 31 06:37:26 PM PDT 24
Finished Jul 31 06:37:31 PM PDT 24
Peak memory 213724 kb
Host smart-31972126-2b31-48ba-a897-537716ede641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703062242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1703062242
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.3033068644
Short name T52
Test name
Test status
Simulation time 12090627097 ps
CPU time 6.8 seconds
Started Jul 31 06:37:20 PM PDT 24
Finished Jul 31 06:37:27 PM PDT 24
Peak memory 213724 kb
Host smart-6a273e53-f633-4e3f-84e6-b3cbc1288305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033068644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3033068644
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.173435830
Short name T2
Test name
Test status
Simulation time 32671447 ps
CPU time 0.74 seconds
Started Jul 31 06:37:26 PM PDT 24
Finished Jul 31 06:37:27 PM PDT 24
Peak memory 205288 kb
Host smart-ab390083-4118-488a-ad90-4fa1d86e07d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173435830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.173435830
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.3236273323
Short name T245
Test name
Test status
Simulation time 7195405516 ps
CPU time 7.42 seconds
Started Jul 31 06:37:25 PM PDT 24
Finished Jul 31 06:37:32 PM PDT 24
Peak memory 213804 kb
Host smart-be7d2adb-51e0-4add-8ff6-186c243e2ad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236273323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3236273323
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.835713949
Short name T261
Test name
Test status
Simulation time 58398611 ps
CPU time 0.77 seconds
Started Jul 31 06:37:24 PM PDT 24
Finished Jul 31 06:37:25 PM PDT 24
Peak memory 205320 kb
Host smart-b37585d3-4e6b-4c37-b5a1-8e8902a7813d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835713949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.835713949
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.2386275225
Short name T235
Test name
Test status
Simulation time 5735002652 ps
CPU time 17.17 seconds
Started Jul 31 06:37:27 PM PDT 24
Finished Jul 31 06:37:44 PM PDT 24
Peak memory 213804 kb
Host smart-19f7dbd5-8c81-4d2b-8b16-e4008e9a3040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386275225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.2386275225
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.691290800
Short name T300
Test name
Test status
Simulation time 210973788 ps
CPU time 0.8 seconds
Started Jul 31 06:35:41 PM PDT 24
Finished Jul 31 06:35:42 PM PDT 24
Peak memory 205256 kb
Host smart-a9b28150-5895-44f9-99d1-5512186da2bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691290800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.691290800
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.4268551987
Short name T33
Test name
Test status
Simulation time 2381329040 ps
CPU time 2.97 seconds
Started Jul 31 06:35:38 PM PDT 24
Finished Jul 31 06:35:41 PM PDT 24
Peak memory 213972 kb
Host smart-0c0310ab-b0d4-4592-bb7d-47d082cbfcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268551987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.4268551987
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1601105858
Short name T269
Test name
Test status
Simulation time 1721764874 ps
CPU time 5.92 seconds
Started Jul 31 06:35:36 PM PDT 24
Finished Jul 31 06:35:42 PM PDT 24
Peak memory 213892 kb
Host smart-bdedf728-8ef5-45c0-bb85-96e1527edbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601105858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1601105858
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2755346471
Short name T215
Test name
Test status
Simulation time 10855288510 ps
CPU time 9.48 seconds
Started Jul 31 06:35:39 PM PDT 24
Finished Jul 31 06:35:49 PM PDT 24
Peak memory 214020 kb
Host smart-2679b073-2f75-4691-836f-58cea99faaff
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2755346471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2755346471
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.13066939
Short name T172
Test name
Test status
Simulation time 286951443 ps
CPU time 1.39 seconds
Started Jul 31 06:35:39 PM PDT 24
Finished Jul 31 06:35:41 PM PDT 24
Peak memory 205312 kb
Host smart-506bf297-b8fc-4733-bae3-66cb61865241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13066939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.13066939
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.397953215
Short name T221
Test name
Test status
Simulation time 310852645 ps
CPU time 0.91 seconds
Started Jul 31 06:35:37 PM PDT 24
Finished Jul 31 06:35:38 PM PDT 24
Peak memory 205268 kb
Host smart-4c3862bb-0080-4624-a5ff-cd1c3530de9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397953215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.397953215
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1716360720
Short name T184
Test name
Test status
Simulation time 1878916539 ps
CPU time 1.6 seconds
Started Jul 31 06:35:33 PM PDT 24
Finished Jul 31 06:35:35 PM PDT 24
Peak memory 205692 kb
Host smart-8eb06451-5e1d-4603-8db9-f091658226ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716360720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1716360720
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.64915405
Short name T48
Test name
Test status
Simulation time 3411045725 ps
CPU time 9.99 seconds
Started Jul 31 06:35:38 PM PDT 24
Finished Jul 31 06:35:48 PM PDT 24
Peak memory 213724 kb
Host smart-c9d952da-4a5e-43b5-924e-fb7b10ae4da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64915405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.64915405
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.4175153355
Short name T299
Test name
Test status
Simulation time 315127423 ps
CPU time 0.79 seconds
Started Jul 31 06:37:33 PM PDT 24
Finished Jul 31 06:37:34 PM PDT 24
Peak memory 205268 kb
Host smart-d2554c7c-741a-46ae-bbe0-ab112cc68be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175153355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.4175153355
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.1608455234
Short name T22
Test name
Test status
Simulation time 7201525961 ps
CPU time 14.9 seconds
Started Jul 31 06:37:26 PM PDT 24
Finished Jul 31 06:37:41 PM PDT 24
Peak memory 213796 kb
Host smart-bf5c62d4-ce0f-444c-9e87-2f3c73a89f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608455234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.1608455234
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.4165694673
Short name T39
Test name
Test status
Simulation time 161298781 ps
CPU time 0.86 seconds
Started Jul 31 06:37:30 PM PDT 24
Finished Jul 31 06:37:31 PM PDT 24
Peak memory 205300 kb
Host smart-5a2d9d68-a7fa-490d-8c26-8d3c186301d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165694673 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.4165694673
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.3408810951
Short name T287
Test name
Test status
Simulation time 3284494998 ps
CPU time 3.66 seconds
Started Jul 31 06:37:30 PM PDT 24
Finished Jul 31 06:37:34 PM PDT 24
Peak memory 205576 kb
Host smart-df9628cb-1231-44b2-b72e-6793742a3c97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408810951 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.3408810951
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3022985453
Short name T186
Test name
Test status
Simulation time 70698135 ps
CPU time 0.73 seconds
Started Jul 31 06:37:29 PM PDT 24
Finished Jul 31 06:37:30 PM PDT 24
Peak memory 205276 kb
Host smart-aace038a-08c4-4eb5-ab31-da9f88975525
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022985453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3022985453
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.87095236
Short name T25
Test name
Test status
Simulation time 2981446110 ps
CPU time 5.76 seconds
Started Jul 31 06:37:32 PM PDT 24
Finished Jul 31 06:37:38 PM PDT 24
Peak memory 205544 kb
Host smart-6e94219d-5584-4489-9f29-e6722e135b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87095236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.87095236
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.529060077
Short name T200
Test name
Test status
Simulation time 45641127 ps
CPU time 0.8 seconds
Started Jul 31 06:37:33 PM PDT 24
Finished Jul 31 06:37:34 PM PDT 24
Peak memory 205288 kb
Host smart-845e1d0c-5308-48b6-ba26-6f8eb55130dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529060077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.529060077
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.714383433
Short name T173
Test name
Test status
Simulation time 3766561125 ps
CPU time 4.77 seconds
Started Jul 31 06:37:32 PM PDT 24
Finished Jul 31 06:37:37 PM PDT 24
Peak memory 213708 kb
Host smart-5d71ed88-24d4-40ba-b50b-48f926188f44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714383433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.714383433
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.3559907679
Short name T251
Test name
Test status
Simulation time 88319086 ps
CPU time 0.9 seconds
Started Jul 31 06:37:32 PM PDT 24
Finished Jul 31 06:37:33 PM PDT 24
Peak memory 205228 kb
Host smart-f6e25375-18bd-448c-9bd9-789da8ab9495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559907679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.3559907679
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.479587830
Short name T292
Test name
Test status
Simulation time 5306457982 ps
CPU time 5.01 seconds
Started Jul 31 06:37:31 PM PDT 24
Finished Jul 31 06:37:36 PM PDT 24
Peak memory 214404 kb
Host smart-7f08a6f5-29bb-4b62-86f3-f71290127861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479587830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.479587830
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.1591042403
Short name T134
Test name
Test status
Simulation time 41852883 ps
CPU time 0.77 seconds
Started Jul 31 06:37:38 PM PDT 24
Finished Jul 31 06:37:39 PM PDT 24
Peak memory 205184 kb
Host smart-2835b562-70ab-44a8-81cf-f30493e4008b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591042403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.1591042403
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.3392464091
Short name T191
Test name
Test status
Simulation time 2444173423 ps
CPU time 2.91 seconds
Started Jul 31 06:37:37 PM PDT 24
Finished Jul 31 06:37:40 PM PDT 24
Peak memory 205644 kb
Host smart-f6f5b1a2-b9c6-4d29-9cc0-a8cdd9fd9f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392464091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.3392464091
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2055713001
Short name T179
Test name
Test status
Simulation time 77053303 ps
CPU time 0.73 seconds
Started Jul 31 06:37:36 PM PDT 24
Finished Jul 31 06:37:37 PM PDT 24
Peak memory 205300 kb
Host smart-14741753-3fd3-41cd-9ba9-694d5641359d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055713001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2055713001
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.2807235462
Short name T303
Test name
Test status
Simulation time 4694755779 ps
CPU time 12.41 seconds
Started Jul 31 06:37:35 PM PDT 24
Finished Jul 31 06:37:48 PM PDT 24
Peak memory 213724 kb
Host smart-633341c9-4028-4bb1-bf76-7b8659953d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807235462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.2807235462
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.954523980
Short name T203
Test name
Test status
Simulation time 30327981 ps
CPU time 0.77 seconds
Started Jul 31 06:37:38 PM PDT 24
Finished Jul 31 06:37:38 PM PDT 24
Peak memory 205280 kb
Host smart-075d0049-9155-4896-973b-006f9dae7c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954523980 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.954523980
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1606193837
Short name T258
Test name
Test status
Simulation time 107208878 ps
CPU time 0.82 seconds
Started Jul 31 06:37:37 PM PDT 24
Finished Jul 31 06:37:38 PM PDT 24
Peak memory 205288 kb
Host smart-8527dedc-f937-47c4-b72a-2c767196356f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606193837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1606193837
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.2099044533
Short name T20
Test name
Test status
Simulation time 5400238857 ps
CPU time 15.23 seconds
Started Jul 31 06:37:39 PM PDT 24
Finished Jul 31 06:37:54 PM PDT 24
Peak memory 205660 kb
Host smart-b86fbafe-7927-425d-ae82-bc1691e9acb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099044533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.2099044533
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3005221163
Short name T238
Test name
Test status
Simulation time 55411708 ps
CPU time 0.83 seconds
Started Jul 31 06:37:36 PM PDT 24
Finished Jul 31 06:37:36 PM PDT 24
Peak memory 205252 kb
Host smart-ce1aa7f1-d5d0-43c1-9aaa-477384e08338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005221163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3005221163
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.4175965118
Short name T198
Test name
Test status
Simulation time 73386724 ps
CPU time 0.83 seconds
Started Jul 31 06:35:52 PM PDT 24
Finished Jul 31 06:35:53 PM PDT 24
Peak memory 205200 kb
Host smart-3f873f1c-20eb-4187-81d1-907c3f76ce87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175965118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.4175965118
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3310113680
Short name T259
Test name
Test status
Simulation time 34432286601 ps
CPU time 23.35 seconds
Started Jul 31 06:35:44 PM PDT 24
Finished Jul 31 06:36:07 PM PDT 24
Peak memory 222152 kb
Host smart-545651ec-263b-4cc6-9289-2917502fab11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310113680 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3310113680
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.3953034862
Short name T144
Test name
Test status
Simulation time 12199268109 ps
CPU time 11.48 seconds
Started Jul 31 06:35:46 PM PDT 24
Finished Jul 31 06:35:57 PM PDT 24
Peak memory 216008 kb
Host smart-d4519597-093c-49ac-9cd0-b585178baa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953034862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.3953034862
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.1880155713
Short name T195
Test name
Test status
Simulation time 9222351391 ps
CPU time 7.68 seconds
Started Jul 31 06:35:46 PM PDT 24
Finished Jul 31 06:35:53 PM PDT 24
Peak memory 213900 kb
Host smart-ccd01a79-faaf-49ab-a072-ae8c589d3464
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1880155713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.1880155713
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.3012835254
Short name T249
Test name
Test status
Simulation time 841074679 ps
CPU time 2.92 seconds
Started Jul 31 06:35:44 PM PDT 24
Finished Jul 31 06:35:47 PM PDT 24
Peak memory 205296 kb
Host smart-5b8aba03-22f8-425c-a60e-441525623116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012835254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3012835254
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.438607990
Short name T207
Test name
Test status
Simulation time 4182748004 ps
CPU time 1.93 seconds
Started Jul 31 06:35:41 PM PDT 24
Finished Jul 31 06:35:43 PM PDT 24
Peak memory 213916 kb
Host smart-f3d49efd-59a7-409b-bf18-04082a33df9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438607990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.438607990
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.3358072455
Short name T148
Test name
Test status
Simulation time 4715775429 ps
CPU time 8.44 seconds
Started Jul 31 06:35:43 PM PDT 24
Finished Jul 31 06:35:52 PM PDT 24
Peak memory 205596 kb
Host smart-eb9a330d-2259-4ccd-b8a5-fa94f38036c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358072455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.3358072455
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.3798833536
Short name T81
Test name
Test status
Simulation time 114592695130 ps
CPU time 1744.44 seconds
Started Jul 31 06:35:52 PM PDT 24
Finished Jul 31 07:04:57 PM PDT 24
Peak memory 248988 kb
Host smart-fab65f40-e8e4-465b-a2bf-8924b529c8ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798833536 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.3798833536
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2648385408
Short name T182
Test name
Test status
Simulation time 57271781 ps
CPU time 0.83 seconds
Started Jul 31 06:35:58 PM PDT 24
Finished Jul 31 06:35:59 PM PDT 24
Peak memory 205300 kb
Host smart-28482e1b-d1a4-46bc-924b-1a73404938ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648385408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2648385408
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2565027058
Short name T146
Test name
Test status
Simulation time 22148114531 ps
CPU time 62.31 seconds
Started Jul 31 06:35:54 PM PDT 24
Finished Jul 31 06:36:57 PM PDT 24
Peak memory 213888 kb
Host smart-773ab8b4-b569-4dcc-8bf2-340da7d93186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565027058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2565027058
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.464363000
Short name T278
Test name
Test status
Simulation time 2397328670 ps
CPU time 6.45 seconds
Started Jul 31 06:35:50 PM PDT 24
Finished Jul 31 06:35:57 PM PDT 24
Peak memory 205816 kb
Host smart-3c5abd31-19ae-4c64-8e3a-e69179fafbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464363000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.464363000
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.492471513
Short name T276
Test name
Test status
Simulation time 6215546902 ps
CPU time 6.11 seconds
Started Jul 31 06:35:50 PM PDT 24
Finished Jul 31 06:35:56 PM PDT 24
Peak memory 213804 kb
Host smart-4f53081c-7502-4385-8a47-c61228b2003b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492471513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.492471513
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.3450938080
Short name T262
Test name
Test status
Simulation time 384777227 ps
CPU time 1.81 seconds
Started Jul 31 06:35:56 PM PDT 24
Finished Jul 31 06:35:58 PM PDT 24
Peak memory 205336 kb
Host smart-35c44c25-897f-4aaa-906f-fd665297beea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450938080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.3450938080
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.660164679
Short name T265
Test name
Test status
Simulation time 8481664356 ps
CPU time 3.61 seconds
Started Jul 31 06:35:51 PM PDT 24
Finished Jul 31 06:35:55 PM PDT 24
Peak memory 214028 kb
Host smart-98edcad3-1042-4fcf-a1e6-c29c7ed05505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660164679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.660164679
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.1307224756
Short name T3
Test name
Test status
Simulation time 2338487089 ps
CPU time 5.08 seconds
Started Jul 31 06:35:54 PM PDT 24
Finished Jul 31 06:35:59 PM PDT 24
Peak memory 213752 kb
Host smart-2f8d20cf-6826-42ae-9ce8-6cfe8acb91aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307224756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.1307224756
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1719107545
Short name T56
Test name
Test status
Simulation time 99522037 ps
CPU time 0.95 seconds
Started Jul 31 06:36:07 PM PDT 24
Finished Jul 31 06:36:08 PM PDT 24
Peak memory 205276 kb
Host smart-b09417c7-67a7-4158-bf47-136d3bd4c43c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719107545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1719107545
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.1642539398
Short name T34
Test name
Test status
Simulation time 7644278413 ps
CPU time 17.45 seconds
Started Jul 31 06:36:01 PM PDT 24
Finished Jul 31 06:36:19 PM PDT 24
Peak memory 222072 kb
Host smart-b73374c0-0fe6-41da-82f3-d86cf56bbf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642539398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.1642539398
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.173783105
Short name T176
Test name
Test status
Simulation time 5059821060 ps
CPU time 15.37 seconds
Started Jul 31 06:35:59 PM PDT 24
Finished Jul 31 06:36:15 PM PDT 24
Peak memory 213940 kb
Host smart-fd4c2017-6ccf-4cc9-a18c-4ff492551b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173783105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.173783105
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.382986524
Short name T97
Test name
Test status
Simulation time 1661929360 ps
CPU time 2.05 seconds
Started Jul 31 06:35:59 PM PDT 24
Finished Jul 31 06:36:01 PM PDT 24
Peak memory 205624 kb
Host smart-82e1e748-4f63-47f5-a2e5-1adee3499d51
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382986524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl
_access.382986524
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.4051519321
Short name T45
Test name
Test status
Simulation time 332591993 ps
CPU time 0.97 seconds
Started Jul 31 06:36:07 PM PDT 24
Finished Jul 31 06:36:08 PM PDT 24
Peak memory 205304 kb
Host smart-7f4575b4-9cbe-4694-bc96-82964b61bc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051519321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.4051519321
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.274712310
Short name T284
Test name
Test status
Simulation time 16037680411 ps
CPU time 48.18 seconds
Started Jul 31 06:36:02 PM PDT 24
Finished Jul 31 06:36:51 PM PDT 24
Peak memory 213968 kb
Host smart-e60a7fb8-726c-4d28-a2dc-3057556a8633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274712310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.274712310
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.1568075998
Short name T10
Test name
Test status
Simulation time 2762984213 ps
CPU time 4.52 seconds
Started Jul 31 06:36:04 PM PDT 24
Finished Jul 31 06:36:09 PM PDT 24
Peak memory 213740 kb
Host smart-97cd2df6-d69e-465d-ac0c-84c9d028ef9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568075998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.1568075998
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.4080106504
Short name T177
Test name
Test status
Simulation time 62576353 ps
CPU time 0.73 seconds
Started Jul 31 06:36:07 PM PDT 24
Finished Jul 31 06:36:08 PM PDT 24
Peak memory 205252 kb
Host smart-1699e1a8-8a7e-44d4-a909-deb20307e0c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080106504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.4080106504
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.515164576
Short name T242
Test name
Test status
Simulation time 13746432194 ps
CPU time 27.59 seconds
Started Jul 31 06:36:03 PM PDT 24
Finished Jul 31 06:36:30 PM PDT 24
Peak memory 213976 kb
Host smart-ef652bf3-f1ff-4db4-9370-c66a5532c984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515164576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.515164576
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.539697534
Short name T236
Test name
Test status
Simulation time 7142883721 ps
CPU time 12.85 seconds
Started Jul 31 06:36:03 PM PDT 24
Finished Jul 31 06:36:16 PM PDT 24
Peak memory 213932 kb
Host smart-4b9f69b9-605d-47c3-a874-ac587d59f810
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=539697534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.539697534
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1370985827
Short name T199
Test name
Test status
Simulation time 6565093283 ps
CPU time 10.05 seconds
Started Jul 31 06:36:09 PM PDT 24
Finished Jul 31 06:36:19 PM PDT 24
Peak memory 205660 kb
Host smart-2665eaa0-0e52-4c3d-8fe2-4b440176fd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370985827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1370985827
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all.2567518026
Short name T8
Test name
Test status
Simulation time 4162562010 ps
CPU time 8.44 seconds
Started Jul 31 06:36:10 PM PDT 24
Finished Jul 31 06:36:19 PM PDT 24
Peak memory 213864 kb
Host smart-3b6b7b7a-1c01-4ec7-87db-a93ca4e89aa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567518026 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.2567518026
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.1074326439
Short name T60
Test name
Test status
Simulation time 49690675878 ps
CPU time 456.06 seconds
Started Jul 31 06:36:07 PM PDT 24
Finished Jul 31 06:43:43 PM PDT 24
Peak memory 224464 kb
Host smart-5b628b91-2e7f-49ea-b1d7-962a414a853d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074326439 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.1074326439
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.747212196
Short name T227
Test name
Test status
Simulation time 49018996 ps
CPU time 0.79 seconds
Started Jul 31 06:36:11 PM PDT 24
Finished Jul 31 06:36:12 PM PDT 24
Peak memory 205256 kb
Host smart-23fc8502-ae26-4297-9433-0fd6198a2ed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747212196 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.747212196
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.3621334436
Short name T32
Test name
Test status
Simulation time 23726815112 ps
CPU time 22.37 seconds
Started Jul 31 06:36:11 PM PDT 24
Finished Jul 31 06:36:33 PM PDT 24
Peak memory 213940 kb
Host smart-22b53c5a-dda5-4992-9de1-17f29f9eba6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621334436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.3621334436
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1591773487
Short name T257
Test name
Test status
Simulation time 13327320939 ps
CPU time 31.45 seconds
Started Jul 31 06:36:13 PM PDT 24
Finished Jul 31 06:36:45 PM PDT 24
Peak memory 222052 kb
Host smart-8ae35234-885d-4521-822d-8197d6c8b6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591773487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1591773487
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.2533342231
Short name T158
Test name
Test status
Simulation time 3279608386 ps
CPU time 10.18 seconds
Started Jul 31 06:36:12 PM PDT 24
Finished Jul 31 06:36:22 PM PDT 24
Peak memory 205832 kb
Host smart-526bd3f9-ad75-4ed3-b6f2-93a2068be984
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533342231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.2533342231
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1922980816
Short name T223
Test name
Test status
Simulation time 12839751611 ps
CPU time 13.46 seconds
Started Jul 31 06:36:16 PM PDT 24
Finished Jul 31 06:36:30 PM PDT 24
Peak memory 213952 kb
Host smart-a0248ca6-9994-48b8-acbe-0b656fed1d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922980816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1922980816
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.2534032591
Short name T35
Test name
Test status
Simulation time 3953043640 ps
CPU time 2.85 seconds
Started Jul 31 06:36:12 PM PDT 24
Finished Jul 31 06:36:15 PM PDT 24
Peak memory 213864 kb
Host smart-7b8dda90-4280-496c-ac47-51427501bf35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534032591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.2534032591
Directory /workspace/9.rv_dm_stress_all/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.701071267
Short name T50
Test name
Test status
Simulation time 14103674220 ps
CPU time 146.03 seconds
Started Jul 31 06:36:14 PM PDT 24
Finished Jul 31 06:38:40 PM PDT 24
Peak memory 221416 kb
Host smart-d8cf1e60-d5b3-4c4b-896f-55b5350aa85e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701071267 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.701071267
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest
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