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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
83.90 96.18 85.20 89.91 75.00 88.33 98.53 54.13


Total test records in report: 467
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T129 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2728009601 Aug 01 05:27:04 PM PDT 24 Aug 01 05:27:23 PM PDT 24 2587778740 ps
T306 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1888554057 Aug 01 05:27:28 PM PDT 24 Aug 01 05:28:24 PM PDT 24 22921082591 ps
T81 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.53716228 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:23 PM PDT 24 1057909257 ps
T307 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1928319343 Aug 01 05:27:17 PM PDT 24 Aug 01 05:27:21 PM PDT 24 3636882274 ps
T130 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3380290948 Aug 01 05:27:14 PM PDT 24 Aug 01 05:27:24 PM PDT 24 3800588420 ps
T308 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.694139221 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:18 PM PDT 24 197393639 ps
T309 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2679616365 Aug 01 05:27:28 PM PDT 24 Aug 01 05:27:35 PM PDT 24 4503028138 ps
T159 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.271883388 Aug 01 05:27:28 PM PDT 24 Aug 01 05:27:33 PM PDT 24 499846969 ps
T310 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2739375871 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:39 PM PDT 24 2625638053 ps
T57 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4222212364 Aug 01 05:26:58 PM PDT 24 Aug 01 05:28:57 PM PDT 24 41369996617 ps
T58 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2945393197 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:08 PM PDT 24 988381688 ps
T311 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1289694091 Aug 01 05:27:40 PM PDT 24 Aug 01 05:27:45 PM PDT 24 314647220 ps
T312 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1943537888 Aug 01 05:26:56 PM PDT 24 Aug 01 05:28:28 PM PDT 24 56755461840 ps
T82 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3767735813 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:33 PM PDT 24 630487164 ps
T313 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.58172143 Aug 01 05:27:07 PM PDT 24 Aug 01 05:27:08 PM PDT 24 76884528 ps
T83 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2620265969 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:33 PM PDT 24 74222428 ps
T84 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4016495790 Aug 01 05:26:57 PM PDT 24 Aug 01 05:28:15 PM PDT 24 10168976254 ps
T116 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2126060043 Aug 01 05:27:32 PM PDT 24 Aug 01 05:27:43 PM PDT 24 3720222471 ps
T314 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2293056983 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:19 PM PDT 24 83376533 ps
T315 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3398682312 Aug 01 05:27:04 PM PDT 24 Aug 01 05:27:07 PM PDT 24 136593716 ps
T85 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1017437307 Aug 01 05:27:19 PM PDT 24 Aug 01 05:27:26 PM PDT 24 551186076 ps
T59 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2421620568 Aug 01 05:27:04 PM PDT 24 Aug 01 05:28:44 PM PDT 24 36014743053 ps
T316 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.387384408 Aug 01 05:27:39 PM PDT 24 Aug 01 05:28:06 PM PDT 24 19098144925 ps
T117 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.482512323 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:43 PM PDT 24 1097207310 ps
T317 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1013809077 Aug 01 05:26:58 PM PDT 24 Aug 01 05:27:01 PM PDT 24 1398329599 ps
T318 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3971910893 Aug 01 05:27:14 PM PDT 24 Aug 01 05:27:23 PM PDT 24 6160349785 ps
T319 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2688552667 Aug 01 05:27:20 PM PDT 24 Aug 01 05:27:24 PM PDT 24 628027101 ps
T86 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2731611749 Aug 01 05:27:28 PM PDT 24 Aug 01 05:27:30 PM PDT 24 208158972 ps
T56 /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2470902682 Aug 01 05:27:04 PM PDT 24 Aug 01 05:28:07 PM PDT 24 20626107112 ps
T320 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4009173380 Aug 01 05:26:54 PM PDT 24 Aug 01 05:26:56 PM PDT 24 1037606699 ps
T321 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2452505911 Aug 01 05:26:58 PM PDT 24 Aug 01 05:27:01 PM PDT 24 130956314 ps
T118 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1926481561 Aug 01 05:27:40 PM PDT 24 Aug 01 05:27:45 PM PDT 24 776411235 ps
T322 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2838183795 Aug 01 05:27:29 PM PDT 24 Aug 01 05:27:30 PM PDT 24 76663604 ps
T323 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3388973995 Aug 01 05:27:41 PM PDT 24 Aug 01 05:27:45 PM PDT 24 2558087842 ps
T119 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2659851327 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:07 PM PDT 24 114242717 ps
T324 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3903699887 Aug 01 05:27:00 PM PDT 24 Aug 01 05:27:07 PM PDT 24 6834500097 ps
T325 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.282616779 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:34 PM PDT 24 237663438 ps
T120 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3499558699 Aug 01 05:27:17 PM PDT 24 Aug 01 05:27:23 PM PDT 24 230004692 ps
T87 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.460731956 Aug 01 05:27:46 PM PDT 24 Aug 01 05:27:54 PM PDT 24 1282881530 ps
T88 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3959347950 Aug 01 05:26:55 PM PDT 24 Aug 01 05:26:57 PM PDT 24 185564767 ps
T160 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.444309081 Aug 01 05:27:18 PM PDT 24 Aug 01 05:28:02 PM PDT 24 39207790186 ps
T326 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4142244248 Aug 01 05:26:56 PM PDT 24 Aug 01 05:27:07 PM PDT 24 15460551692 ps
T89 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1164088641 Aug 01 05:27:39 PM PDT 24 Aug 01 05:27:42 PM PDT 24 219996211 ps
T327 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2583605997 Aug 01 05:27:07 PM PDT 24 Aug 01 05:27:08 PM PDT 24 106097394 ps
T92 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1793437703 Aug 01 05:27:01 PM PDT 24 Aug 01 05:27:22 PM PDT 24 7717902263 ps
T328 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1327806642 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:06 PM PDT 24 567029799 ps
T329 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.355632327 Aug 01 05:27:16 PM PDT 24 Aug 01 05:27:20 PM PDT 24 2547346654 ps
T96 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4067819356 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:07 PM PDT 24 197860769 ps
T97 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.918010647 Aug 01 05:27:40 PM PDT 24 Aug 01 05:27:48 PM PDT 24 2095441209 ps
T98 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3289111212 Aug 01 05:27:21 PM PDT 24 Aug 01 05:27:24 PM PDT 24 95332273 ps
T330 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1539939483 Aug 01 05:27:16 PM PDT 24 Aug 01 05:27:17 PM PDT 24 220356392 ps
T331 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1172591195 Aug 01 05:26:54 PM PDT 24 Aug 01 05:26:55 PM PDT 24 139863700 ps
T99 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.680287727 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:39 PM PDT 24 531300583 ps
T332 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3852627394 Aug 01 05:26:55 PM PDT 24 Aug 01 05:27:00 PM PDT 24 491323362 ps
T100 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.804025807 Aug 01 05:27:04 PM PDT 24 Aug 01 05:27:38 PM PDT 24 9796238047 ps
T333 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2760818710 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:34 PM PDT 24 5710810976 ps
T334 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.382279203 Aug 01 05:27:08 PM PDT 24 Aug 01 05:27:09 PM PDT 24 56692721 ps
T335 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2603560696 Aug 01 05:27:29 PM PDT 24 Aug 01 05:27:30 PM PDT 24 152006465 ps
T93 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2330132387 Aug 01 05:27:06 PM PDT 24 Aug 01 05:27:30 PM PDT 24 18491009471 ps
T336 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.202426309 Aug 01 05:27:16 PM PDT 24 Aug 01 05:27:20 PM PDT 24 164265917 ps
T337 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4282341905 Aug 01 05:27:27 PM PDT 24 Aug 01 05:27:30 PM PDT 24 387568390 ps
T338 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3291876123 Aug 01 05:27:37 PM PDT 24 Aug 01 05:28:32 PM PDT 24 20229954251 ps
T339 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2980398645 Aug 01 05:27:07 PM PDT 24 Aug 01 05:33:23 PM PDT 24 136369609546 ps
T340 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.964258784 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:17 PM PDT 24 67470320 ps
T341 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2382899976 Aug 01 05:27:41 PM PDT 24 Aug 01 05:27:44 PM PDT 24 604539350 ps
T150 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.313786258 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:22 PM PDT 24 3677961886 ps
T101 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3389450135 Aug 01 05:27:38 PM PDT 24 Aug 01 05:27:40 PM PDT 24 241614048 ps
T342 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1749732467 Aug 01 05:26:57 PM PDT 24 Aug 01 05:32:46 PM PDT 24 120748877132 ps
T343 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3370430871 Aug 01 05:27:44 PM PDT 24 Aug 01 05:28:01 PM PDT 24 3452465440 ps
T344 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3651364571 Aug 01 05:26:58 PM PDT 24 Aug 01 05:26:59 PM PDT 24 114234405 ps
T102 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2634205804 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:20 PM PDT 24 429726767 ps
T111 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.4028215268 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:23 PM PDT 24 723489509 ps
T103 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1004416836 Aug 01 05:27:06 PM PDT 24 Aug 01 05:27:09 PM PDT 24 504369857 ps
T345 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2169415571 Aug 01 05:27:17 PM PDT 24 Aug 01 05:27:21 PM PDT 24 701025312 ps
T346 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.309775237 Aug 01 05:27:29 PM PDT 24 Aug 01 05:27:30 PM PDT 24 226041235 ps
T155 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3984621241 Aug 01 05:27:16 PM PDT 24 Aug 01 05:27:28 PM PDT 24 6555718562 ps
T347 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.217977163 Aug 01 05:27:26 PM PDT 24 Aug 01 05:27:31 PM PDT 24 245301438 ps
T112 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1722845742 Aug 01 05:27:28 PM PDT 24 Aug 01 05:27:36 PM PDT 24 4095916204 ps
T104 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3307036435 Aug 01 05:27:06 PM PDT 24 Aug 01 05:27:08 PM PDT 24 320224516 ps
T108 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4275580473 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:06 PM PDT 24 242222298 ps
T348 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.773755635 Aug 01 05:27:46 PM PDT 24 Aug 01 05:27:50 PM PDT 24 1312887455 ps
T349 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1869819533 Aug 01 05:27:40 PM PDT 24 Aug 01 05:27:45 PM PDT 24 442262263 ps
T350 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3034827216 Aug 01 05:27:07 PM PDT 24 Aug 01 05:27:19 PM PDT 24 1099284847 ps
T351 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1049824569 Aug 01 05:27:06 PM PDT 24 Aug 01 05:27:08 PM PDT 24 2710729680 ps
T352 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4192660052 Aug 01 05:27:27 PM PDT 24 Aug 01 05:27:30 PM PDT 24 993426201 ps
T94 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3657143187 Aug 01 05:27:07 PM PDT 24 Aug 01 05:27:33 PM PDT 24 19131860394 ps
T353 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3184615498 Aug 01 05:27:46 PM PDT 24 Aug 01 05:27:56 PM PDT 24 1298501422 ps
T354 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.636452069 Aug 01 05:26:55 PM PDT 24 Aug 01 05:28:07 PM PDT 24 96295019546 ps
T355 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2164581020 Aug 01 05:27:29 PM PDT 24 Aug 01 05:27:30 PM PDT 24 220022656 ps
T356 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1158488832 Aug 01 05:27:08 PM PDT 24 Aug 01 05:27:10 PM PDT 24 153397353 ps
T357 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2451375559 Aug 01 05:26:56 PM PDT 24 Aug 01 05:26:58 PM PDT 24 1733720603 ps
T358 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1985547988 Aug 01 05:27:41 PM PDT 24 Aug 01 05:27:42 PM PDT 24 129638823 ps
T109 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3096029191 Aug 01 05:26:49 PM PDT 24 Aug 01 05:28:07 PM PDT 24 5439870263 ps
T359 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4068998974 Aug 01 05:27:06 PM PDT 24 Aug 01 05:34:27 PM PDT 24 152943377119 ps
T360 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2005236962 Aug 01 05:27:07 PM PDT 24 Aug 01 05:28:01 PM PDT 24 7058242466 ps
T361 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3743990401 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:32 PM PDT 24 351669725 ps
T362 /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3077473633 Aug 01 05:27:39 PM PDT 24 Aug 01 05:27:41 PM PDT 24 177552471 ps
T363 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3581846312 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:34 PM PDT 24 10389864468 ps
T364 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2112048017 Aug 01 05:27:39 PM PDT 24 Aug 01 05:27:40 PM PDT 24 235784683 ps
T365 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.730872153 Aug 01 05:27:27 PM PDT 24 Aug 01 05:27:30 PM PDT 24 808156528 ps
T366 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2223145295 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:16 PM PDT 24 136463411 ps
T367 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1860125527 Aug 01 05:26:54 PM PDT 24 Aug 01 05:27:01 PM PDT 24 5502385915 ps
T368 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3132034299 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:35 PM PDT 24 2034373195 ps
T113 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2160517960 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:35 PM PDT 24 941761844 ps
T369 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.105810583 Aug 01 05:27:29 PM PDT 24 Aug 01 05:27:31 PM PDT 24 177285168 ps
T370 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1905895983 Aug 01 05:27:39 PM PDT 24 Aug 01 05:27:41 PM PDT 24 81305407 ps
T371 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3051552561 Aug 01 05:27:30 PM PDT 24 Aug 01 05:27:41 PM PDT 24 1639684252 ps
T372 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3109530736 Aug 01 05:27:29 PM PDT 24 Aug 01 05:27:31 PM PDT 24 87707143 ps
T373 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2890525358 Aug 01 05:27:01 PM PDT 24 Aug 01 05:27:03 PM PDT 24 182870285 ps
T374 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3741907588 Aug 01 05:27:29 PM PDT 24 Aug 01 05:27:33 PM PDT 24 575001131 ps
T375 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1168482131 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:39 PM PDT 24 14803793375 ps
T376 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.642546224 Aug 01 05:27:14 PM PDT 24 Aug 01 05:27:19 PM PDT 24 221280794 ps
T105 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.99557479 Aug 01 05:27:06 PM PDT 24 Aug 01 05:27:08 PM PDT 24 286884955 ps
T377 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2375436970 Aug 01 05:27:16 PM PDT 24 Aug 01 05:27:20 PM PDT 24 343098782 ps
T378 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4080045073 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:27 PM PDT 24 24312757525 ps
T379 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2090165237 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:30 PM PDT 24 16026557896 ps
T114 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3940720360 Aug 01 05:27:27 PM PDT 24 Aug 01 05:27:34 PM PDT 24 926196200 ps
T380 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.989121736 Aug 01 05:27:06 PM PDT 24 Aug 01 05:27:35 PM PDT 24 15956166063 ps
T151 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.418377560 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:44 PM PDT 24 4668230418 ps
T381 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.56341799 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:06 PM PDT 24 418011702 ps
T382 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2192776011 Aug 01 05:26:55 PM PDT 24 Aug 01 05:26:56 PM PDT 24 41846080 ps
T383 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.713063665 Aug 01 05:27:36 PM PDT 24 Aug 01 05:27:38 PM PDT 24 265311008 ps
T161 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1870827187 Aug 01 05:27:18 PM PDT 24 Aug 01 05:27:44 PM PDT 24 32697142916 ps
T384 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.223967905 Aug 01 05:27:41 PM PDT 24 Aug 01 05:27:45 PM PDT 24 287638866 ps
T154 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2723855180 Aug 01 05:27:16 PM PDT 24 Aug 01 05:27:32 PM PDT 24 8005835996 ps
T385 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1288703345 Aug 01 05:27:38 PM PDT 24 Aug 01 05:27:39 PM PDT 24 352708568 ps
T386 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3755150234 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:33 PM PDT 24 6088941496 ps
T387 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4055688180 Aug 01 05:27:04 PM PDT 24 Aug 01 05:27:08 PM PDT 24 1087894828 ps
T388 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.882093414 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:10 PM PDT 24 513143538 ps
T389 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.264809839 Aug 01 05:27:39 PM PDT 24 Aug 01 05:27:43 PM PDT 24 254205579 ps
T390 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2206258442 Aug 01 05:27:18 PM PDT 24 Aug 01 05:27:24 PM PDT 24 3321996945 ps
T391 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1221623678 Aug 01 05:26:58 PM PDT 24 Aug 01 05:27:10 PM PDT 24 4489991576 ps
T392 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.878092287 Aug 01 05:27:06 PM PDT 24 Aug 01 05:27:11 PM PDT 24 959479573 ps
T393 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1175340506 Aug 01 05:27:40 PM PDT 24 Aug 01 05:27:47 PM PDT 24 3751680539 ps
T394 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3142197744 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:06 PM PDT 24 90119164 ps
T395 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2044507393 Aug 01 05:27:30 PM PDT 24 Aug 01 05:27:55 PM PDT 24 16090310942 ps
T396 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.93867928 Aug 01 05:27:06 PM PDT 24 Aug 01 05:27:10 PM PDT 24 100933027 ps
T397 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1078989682 Aug 01 05:27:30 PM PDT 24 Aug 01 05:27:35 PM PDT 24 169625976 ps
T398 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1120010616 Aug 01 05:27:41 PM PDT 24 Aug 01 05:27:49 PM PDT 24 1137038498 ps
T399 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.517657241 Aug 01 05:27:19 PM PDT 24 Aug 01 05:27:22 PM PDT 24 480096312 ps
T400 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4015179251 Aug 01 05:26:58 PM PDT 24 Aug 01 05:27:30 PM PDT 24 10653281241 ps
T401 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1254383033 Aug 01 05:27:18 PM PDT 24 Aug 01 05:27:24 PM PDT 24 2282162240 ps
T153 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4159320661 Aug 01 05:27:30 PM PDT 24 Aug 01 05:27:50 PM PDT 24 3596946509 ps
T402 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1862053333 Aug 01 05:27:00 PM PDT 24 Aug 01 05:27:02 PM PDT 24 107193830 ps
T403 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3609591630 Aug 01 05:27:15 PM PDT 24 Aug 01 05:29:06 PM PDT 24 52032183222 ps
T404 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2301603245 Aug 01 05:27:06 PM PDT 24 Aug 01 05:27:45 PM PDT 24 14723371918 ps
T405 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3437999034 Aug 01 05:26:58 PM PDT 24 Aug 01 05:26:59 PM PDT 24 172814164 ps
T406 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1305386444 Aug 01 05:27:40 PM PDT 24 Aug 01 05:27:56 PM PDT 24 20401179352 ps
T407 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3737532254 Aug 01 05:26:57 PM PDT 24 Aug 01 05:27:34 PM PDT 24 21090746843 ps
T408 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2747396546 Aug 01 05:27:40 PM PDT 24 Aug 01 05:27:42 PM PDT 24 140770344 ps
T409 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1100579537 Aug 01 05:27:41 PM PDT 24 Aug 01 05:27:49 PM PDT 24 16289368130 ps
T410 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3251943039 Aug 01 05:27:07 PM PDT 24 Aug 01 05:27:35 PM PDT 24 1131541052 ps
T411 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2923010979 Aug 01 05:27:36 PM PDT 24 Aug 01 05:27:39 PM PDT 24 588311109 ps
T412 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1509179068 Aug 01 05:27:06 PM PDT 24 Aug 01 05:27:07 PM PDT 24 119452940 ps
T413 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1148449644 Aug 01 05:27:07 PM PDT 24 Aug 01 05:27:07 PM PDT 24 63550126 ps
T414 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1318047031 Aug 01 05:27:07 PM PDT 24 Aug 01 05:27:12 PM PDT 24 196274954 ps
T415 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3336710764 Aug 01 05:27:18 PM PDT 24 Aug 01 05:27:20 PM PDT 24 430999734 ps
T95 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3800370646 Aug 01 05:26:57 PM PDT 24 Aug 01 05:27:05 PM PDT 24 5998000798 ps
T416 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1552860599 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:42 PM PDT 24 31468981909 ps
T417 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2959627214 Aug 01 05:27:40 PM PDT 24 Aug 01 05:27:41 PM PDT 24 141885330 ps
T418 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.683431494 Aug 01 05:27:04 PM PDT 24 Aug 01 05:27:05 PM PDT 24 47210592 ps
T156 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3355222771 Aug 01 05:27:32 PM PDT 24 Aug 01 05:27:49 PM PDT 24 4302532678 ps
T419 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1281736777 Aug 01 05:26:58 PM PDT 24 Aug 01 05:27:02 PM PDT 24 96627336 ps
T420 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.80646914 Aug 01 05:27:29 PM PDT 24 Aug 01 05:27:30 PM PDT 24 181999074 ps
T421 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.194384771 Aug 01 05:27:28 PM PDT 24 Aug 01 05:27:32 PM PDT 24 1229663353 ps
T422 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.922465040 Aug 01 05:26:57 PM PDT 24 Aug 01 05:26:59 PM PDT 24 705010384 ps
T423 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3909608614 Aug 01 05:27:40 PM PDT 24 Aug 01 05:27:44 PM PDT 24 1744038822 ps
T110 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3053715602 Aug 01 05:27:18 PM PDT 24 Aug 01 05:28:12 PM PDT 24 1483301559 ps
T424 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.581132345 Aug 01 05:26:57 PM PDT 24 Aug 01 05:27:04 PM PDT 24 14029255668 ps
T425 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2527166559 Aug 01 05:27:07 PM PDT 24 Aug 01 05:27:09 PM PDT 24 274913614 ps
T152 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1151708251 Aug 01 05:26:54 PM PDT 24 Aug 01 05:27:03 PM PDT 24 1207721809 ps
T426 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3241081177 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:16 PM PDT 24 283463222 ps
T427 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2686647868 Aug 01 05:27:08 PM PDT 24 Aug 01 05:27:42 PM PDT 24 43439339689 ps
T106 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3835816562 Aug 01 05:27:17 PM PDT 24 Aug 01 05:27:21 PM PDT 24 605619628 ps
T428 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2138776333 Aug 01 05:27:07 PM PDT 24 Aug 01 05:27:08 PM PDT 24 271378466 ps
T429 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1930755233 Aug 01 05:27:07 PM PDT 24 Aug 01 05:27:09 PM PDT 24 211133610 ps
T430 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3760978828 Aug 01 05:27:28 PM PDT 24 Aug 01 05:27:45 PM PDT 24 6347727118 ps
T431 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3895066016 Aug 01 05:27:17 PM PDT 24 Aug 01 05:27:28 PM PDT 24 830293067 ps
T432 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2172682969 Aug 01 05:26:54 PM PDT 24 Aug 01 05:27:44 PM PDT 24 15179576999 ps
T433 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1333591508 Aug 01 05:27:39 PM PDT 24 Aug 01 05:27:41 PM PDT 24 768182255 ps
T434 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.4157760070 Aug 01 05:27:04 PM PDT 24 Aug 01 05:27:05 PM PDT 24 33195296 ps
T435 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1698891674 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:32 PM PDT 24 26552848734 ps
T436 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3379759615 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:07 PM PDT 24 272526735 ps
T107 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1681420959 Aug 01 05:26:58 PM PDT 24 Aug 01 05:28:17 PM PDT 24 13396519140 ps
T437 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3622963049 Aug 01 05:26:58 PM PDT 24 Aug 01 05:26:58 PM PDT 24 40770295 ps
T438 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2307556126 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:16 PM PDT 24 145851092 ps
T439 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2863909171 Aug 01 05:26:56 PM PDT 24 Aug 01 05:27:00 PM PDT 24 194609620 ps
T440 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2653494276 Aug 01 05:27:38 PM PDT 24 Aug 01 05:27:41 PM PDT 24 2552518712 ps
T441 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1706082836 Aug 01 05:27:07 PM PDT 24 Aug 01 05:27:11 PM PDT 24 466137858 ps
T442 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.658815354 Aug 01 05:27:28 PM PDT 24 Aug 01 05:27:30 PM PDT 24 285966853 ps
T157 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2509663550 Aug 01 05:26:55 PM PDT 24 Aug 01 05:27:06 PM PDT 24 1187977212 ps
T443 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4265818639 Aug 01 05:27:06 PM PDT 24 Aug 01 05:27:08 PM PDT 24 561749306 ps
T444 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2839442480 Aug 01 05:27:30 PM PDT 24 Aug 01 05:27:39 PM PDT 24 3543095181 ps
T445 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2512936280 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:59 PM PDT 24 10328756269 ps
T446 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.164636953 Aug 01 05:27:18 PM PDT 24 Aug 01 05:27:21 PM PDT 24 187043503 ps
T447 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1426028039 Aug 01 05:27:05 PM PDT 24 Aug 01 05:27:13 PM PDT 24 3058107023 ps
T448 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.929668060 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:24 PM PDT 24 1873234087 ps
T449 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2248915155 Aug 01 05:27:16 PM PDT 24 Aug 01 05:28:07 PM PDT 24 51491969317 ps
T450 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3930029994 Aug 01 05:26:57 PM PDT 24 Aug 01 05:26:59 PM PDT 24 780525568 ps
T451 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.782761612 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:37 PM PDT 24 384648423 ps
T158 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3660331326 Aug 01 05:27:39 PM PDT 24 Aug 01 05:27:57 PM PDT 24 2116477090 ps
T452 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.408319304 Aug 01 05:27:39 PM PDT 24 Aug 01 05:27:46 PM PDT 24 303004023 ps
T453 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1808586284 Aug 01 05:26:54 PM PDT 24 Aug 01 05:27:50 PM PDT 24 2949403707 ps
T454 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1638023102 Aug 01 05:27:30 PM PDT 24 Aug 01 05:27:32 PM PDT 24 68472323 ps
T455 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.952159657 Aug 01 05:26:58 PM PDT 24 Aug 01 05:27:07 PM PDT 24 5190325937 ps
T456 /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1223464456 Aug 01 05:27:18 PM PDT 24 Aug 01 05:27:31 PM PDT 24 20561180626 ps
T457 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3991853194 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:16 PM PDT 24 259277103 ps
T458 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1031159572 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:36 PM PDT 24 214704915 ps
T459 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3509901617 Aug 01 05:27:19 PM PDT 24 Aug 01 05:27:24 PM PDT 24 4720482066 ps
T460 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4108898696 Aug 01 05:26:57 PM PDT 24 Aug 01 05:26:59 PM PDT 24 392731579 ps
T461 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1000435881 Aug 01 05:27:17 PM PDT 24 Aug 01 05:27:21 PM PDT 24 322108265 ps
T462 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.63415694 Aug 01 05:26:55 PM PDT 24 Aug 01 05:27:29 PM PDT 24 5719359013 ps
T463 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1786811604 Aug 01 05:27:31 PM PDT 24 Aug 01 05:27:42 PM PDT 24 12925359387 ps
T464 /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3295405437 Aug 01 05:27:40 PM PDT 24 Aug 01 05:28:03 PM PDT 24 7509262862 ps
T465 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.616023688 Aug 01 05:27:15 PM PDT 24 Aug 01 05:27:19 PM PDT 24 811310054 ps
T466 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2558523437 Aug 01 05:27:16 PM PDT 24 Aug 01 05:27:28 PM PDT 24 2429119167 ps
T467 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2674357117 Aug 01 05:27:02 PM PDT 24 Aug 01 05:27:03 PM PDT 24 113379603 ps

Test location /workspace/coverage/default/8.rv_dm_stress_all.3356906519
Short name T4
Test name
Test status
Simulation time 4988032464 ps
CPU time 12.76 seconds
Started Aug 01 05:28:12 PM PDT 24
Finished Aug 01 05:28:25 PM PDT 24
Peak memory 205596 kb
Host smart-d9395f97-a776-4bb9-bad4-a3d4cca1a974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356906519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all.3356906519
Directory /workspace/8.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all_with_rand_reset.2572488419
Short name T5
Test name
Test status
Simulation time 1254060908434 ps
CPU time 2247.85 seconds
Started Aug 01 05:27:49 PM PDT 24
Finished Aug 01 06:05:17 PM PDT 24
Peak memory 245100 kb
Host smart-cedcd554-be84-4b64-934d-be619ef9f746
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572488419 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all_with_rand_reset.2572488419
Directory /workspace/1.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.3881560214
Short name T1
Test name
Test status
Simulation time 10156784503 ps
CPU time 16.21 seconds
Started Aug 01 05:28:12 PM PDT 24
Finished Aug 01 05:28:29 PM PDT 24
Peak memory 214028 kb
Host smart-bb659c92-8f8d-4e84-bd67-1d2fecda688d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881560214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.3881560214
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2728009601
Short name T129
Test name
Test status
Simulation time 2587778740 ps
CPU time 18.22 seconds
Started Aug 01 05:27:04 PM PDT 24
Finished Aug 01 05:27:23 PM PDT 24
Peak memory 213964 kb
Host smart-2424ac5c-c70c-41d2-b2c4-c4f99111982d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728009601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2728009601
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.2470902682
Short name T56
Test name
Test status
Simulation time 20626107112 ps
CPU time 62.16 seconds
Started Aug 01 05:27:04 PM PDT 24
Finished Aug 01 05:28:07 PM PDT 24
Peak memory 214272 kb
Host smart-eea9d5f7-a010-4be9-ab76-c21519f7c7d3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470902682 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.2470902682
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all_with_rand_reset.4237511828
Short name T11
Test name
Test status
Simulation time 484103586700 ps
CPU time 1746.92 seconds
Started Aug 01 05:28:13 PM PDT 24
Finished Aug 01 05:57:20 PM PDT 24
Peak memory 244952 kb
Host smart-787656b6-359f-427d-8689-5ab63bb26e40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237511828 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all_with_rand_reset.4237511828
Directory /workspace/9.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.4121810143
Short name T42
Test name
Test status
Simulation time 152296799 ps
CPU time 0.73 seconds
Started Aug 01 05:28:28 PM PDT 24
Finished Aug 01 05:28:29 PM PDT 24
Peak memory 205248 kb
Host smart-26d7dbc4-9ade-454e-87a5-03e88c136a49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121810143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.4121810143
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.1597836419
Short name T221
Test name
Test status
Simulation time 82394224588 ps
CPU time 64.83 seconds
Started Aug 01 05:28:16 PM PDT 24
Finished Aug 01 05:29:21 PM PDT 24
Peak memory 214676 kb
Host smart-3af0ff86-2eee-4b9a-aea7-fedd5f2d5eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597836419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.1597836419
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_dmi_failed_op.3152979707
Short name T51
Test name
Test status
Simulation time 166236438 ps
CPU time 0.74 seconds
Started Aug 01 05:27:55 PM PDT 24
Finished Aug 01 05:27:56 PM PDT 24
Peak memory 205196 kb
Host smart-62739bb9-9b2b-4d2a-83f6-d63d65477f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152979707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dmi_failed_op.3152979707
Directory /workspace/0.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/0.rv_dm_debug_disabled.3338792830
Short name T50
Test name
Test status
Simulation time 63330936 ps
CPU time 0.96 seconds
Started Aug 01 05:27:47 PM PDT 24
Finished Aug 01 05:27:48 PM PDT 24
Peak memory 215472 kb
Host smart-79efb2b2-0da2-459f-ad21-c30fd39d5378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338792830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_debug_disabled.3338792830
Directory /workspace/0.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_sba_debug_disabled.87993589
Short name T131
Test name
Test status
Simulation time 1111248459 ps
CPU time 1.61 seconds
Started Aug 01 05:27:42 PM PDT 24
Finished Aug 01 05:27:44 PM PDT 24
Peak memory 205392 kb
Host smart-fdbcdbac-a91d-40fa-81e0-98016487cab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87993589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_debug_disabled.87993589
Directory /workspace/0.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4067819356
Short name T96
Test name
Test status
Simulation time 197860769 ps
CPU time 2.46 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:07 PM PDT 24
Peak memory 213656 kb
Host smart-d037891e-3539-4d92-b5fa-b18c249229bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067819356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.4067819356
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/default/1.rv_dm_dmi_failed_op.573291420
Short name T52
Test name
Test status
Simulation time 302085305 ps
CPU time 1.55 seconds
Started Aug 01 05:27:54 PM PDT 24
Finished Aug 01 05:27:56 PM PDT 24
Peak memory 205212 kb
Host smart-07dde5f5-1d20-4674-a342-ebdefa4c50e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573291420 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dmi_failed_op_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dmi_failed_op.573291420
Directory /workspace/1.rv_dm_dmi_failed_op/latest

Test location /workspace/coverage/default/8.rv_dm_stress_all_with_rand_reset.822119218
Short name T23
Test name
Test status
Simulation time 986817873758 ps
CPU time 964.67 seconds
Started Aug 01 05:28:11 PM PDT 24
Finished Aug 01 05:44:16 PM PDT 24
Peak memory 238248 kb
Host smart-f9d556a5-be16-4d9a-aee1-a1deb5c78fa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822119218 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.rv_dm_stress_all_with_rand_reset.822119218
Directory /workspace/8.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3916687294
Short name T125
Test name
Test status
Simulation time 120916809687 ps
CPU time 196.98 seconds
Started Aug 01 05:27:40 PM PDT 24
Finished Aug 01 05:30:57 PM PDT 24
Peak memory 221040 kb
Host smart-2ff46779-4c7e-49a2-98cc-9f94428aaad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916687294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3916687294
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.1743330467
Short name T43
Test name
Test status
Simulation time 449605230 ps
CPU time 1.21 seconds
Started Aug 01 05:27:58 PM PDT 24
Finished Aug 01 05:27:59 PM PDT 24
Peak memory 228832 kb
Host smart-2c5a6675-8e86-4056-a0b2-96f2f26b637f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743330467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.1743330467
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3380290948
Short name T130
Test name
Test status
Simulation time 3800588420 ps
CPU time 9.55 seconds
Started Aug 01 05:27:14 PM PDT 24
Finished Aug 01 05:27:24 PM PDT 24
Peak memory 213988 kb
Host smart-daf46d3a-de8d-4bbe-a51e-9147c23eaf52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380290948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3380290948
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.2555811953
Short name T18
Test name
Test status
Simulation time 303825179 ps
CPU time 1.07 seconds
Started Aug 01 05:27:42 PM PDT 24
Finished Aug 01 05:27:43 PM PDT 24
Peak memory 205012 kb
Host smart-d113b898-fae5-48f7-b243-d4e2af1e71b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555811953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.2555811953
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.2495942178
Short name T10
Test name
Test status
Simulation time 4893494546 ps
CPU time 4.69 seconds
Started Aug 01 05:27:59 PM PDT 24
Finished Aug 01 05:28:04 PM PDT 24
Peak memory 213652 kb
Host smart-f455262d-1b78-40e2-bbe4-f387e0065d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495942178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.2495942178
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.1957737099
Short name T31
Test name
Test status
Simulation time 42084996 ps
CPU time 0.83 seconds
Started Aug 01 05:27:50 PM PDT 24
Finished Aug 01 05:27:51 PM PDT 24
Peak memory 213356 kb
Host smart-04adb8aa-1ac3-4edc-a97e-f876b01911f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957737099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.1957737099
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.2359517456
Short name T80
Test name
Test status
Simulation time 580015526 ps
CPU time 7.6 seconds
Started Aug 01 05:27:27 PM PDT 24
Finished Aug 01 05:27:35 PM PDT 24
Peak memory 205568 kb
Host smart-24e92ce9-e5ff-41b5-8b34-171701dee6b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359517456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.2359517456
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.1526211696
Short name T139
Test name
Test status
Simulation time 8955136330 ps
CPU time 7.58 seconds
Started Aug 01 05:28:30 PM PDT 24
Finished Aug 01 05:28:38 PM PDT 24
Peak memory 213792 kb
Host smart-d7789d9c-15c9-42c8-97ea-17f8fb91262e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526211696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.1526211696
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_hartsel_warl.2430009801
Short name T25
Test name
Test status
Simulation time 72245010 ps
CPU time 0.85 seconds
Started Aug 01 05:27:47 PM PDT 24
Finished Aug 01 05:27:48 PM PDT 24
Peak memory 205200 kb
Host smart-0a0b77ba-4a52-4cf7-acc0-e8ec3711b5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430009801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hartsel_warl_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hartsel_warl.2430009801
Directory /workspace/0.rv_dm_hartsel_warl/latest

Test location /workspace/coverage/default/1.rv_dm_sba_debug_disabled.1333267257
Short name T132
Test name
Test status
Simulation time 1708204485 ps
CPU time 4.39 seconds
Started Aug 01 05:27:50 PM PDT 24
Finished Aug 01 05:27:55 PM PDT 24
Peak memory 205492 kb
Host smart-c8e98a32-fc50-4d6e-9301-6af4a23b15ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333267257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_debug_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_debug_disabled.1333267257
Directory /workspace/1.rv_dm_sba_debug_disabled/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.3150769297
Short name T34
Test name
Test status
Simulation time 3777652353 ps
CPU time 10.68 seconds
Started Aug 01 05:28:12 PM PDT 24
Finished Aug 01 05:28:23 PM PDT 24
Peak memory 213676 kb
Host smart-21049db6-9fd3-4d90-a09d-8ccb64ed4f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150769297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.3150769297
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.4222212364
Short name T57
Test name
Test status
Simulation time 41369996617 ps
CPU time 119.45 seconds
Started Aug 01 05:26:58 PM PDT 24
Finished Aug 01 05:28:57 PM PDT 24
Peak memory 205536 kb
Host smart-570db163-e53d-4243-8393-d7cf87383e9d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222212364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.4222212364
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_abstractcmd_status.76646946
Short name T41
Test name
Test status
Simulation time 117094457 ps
CPU time 0.79 seconds
Started Aug 01 05:27:48 PM PDT 24
Finished Aug 01 05:27:49 PM PDT 24
Peak memory 205128 kb
Host smart-fc40bc8d-db4c-47f9-8540-59056d8a8e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76646946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_abstractcmd_status.76646946
Directory /workspace/0.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3800370646
Short name T95
Test name
Test status
Simulation time 5998000798 ps
CPU time 7.78 seconds
Started Aug 01 05:26:57 PM PDT 24
Finished Aug 01 05:27:05 PM PDT 24
Peak memory 205672 kb
Host smart-296e8645-fdc8-4d9f-870d-a3821382e34f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800370646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3800370646
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1681420959
Short name T107
Test name
Test status
Simulation time 13396519140 ps
CPU time 79.03 seconds
Started Aug 01 05:26:58 PM PDT 24
Finished Aug 01 05:28:17 PM PDT 24
Peak memory 205712 kb
Host smart-fc7d8caf-8aab-446f-acdb-3f9778de5114
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681420959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1681420959
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.223515602
Short name T21
Test name
Test status
Simulation time 2901711831 ps
CPU time 2.47 seconds
Started Aug 01 05:28:27 PM PDT 24
Finished Aug 01 05:28:29 PM PDT 24
Peak memory 213812 kb
Host smart-19f847e2-0bbf-4a8d-aed7-a4221d792ed4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223515602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.223515602
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3931857322
Short name T29
Test name
Test status
Simulation time 2225177919 ps
CPU time 7.2 seconds
Started Aug 01 05:27:41 PM PDT 24
Finished Aug 01 05:27:49 PM PDT 24
Peak memory 205336 kb
Host smart-aab97301-283c-46ce-8277-92d0710474f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931857322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3931857322
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3899979763
Short name T55
Test name
Test status
Simulation time 22105522102 ps
CPU time 28.77 seconds
Started Aug 01 05:26:57 PM PDT 24
Finished Aug 01 05:27:26 PM PDT 24
Peak memory 221816 kb
Host smart-96f8f10e-c6cf-4a20-b888-3864f6737428
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899979763 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3899979763
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1151708251
Short name T152
Test name
Test status
Simulation time 1207721809 ps
CPU time 8.48 seconds
Started Aug 01 05:26:54 PM PDT 24
Finished Aug 01 05:27:03 PM PDT 24
Peak memory 213692 kb
Host smart-c94db6ea-9d5c-403f-8b92-d152f38bf8d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151708251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1151708251
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1518507677
Short name T145
Test name
Test status
Simulation time 186110103 ps
CPU time 0.88 seconds
Started Aug 01 05:27:39 PM PDT 24
Finished Aug 01 05:27:40 PM PDT 24
Peak memory 205240 kb
Host smart-66dfc553-4786-4b23-9e99-ff5e5930ae19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518507677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1518507677
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.4114645387
Short name T126
Test name
Test status
Simulation time 1198295423 ps
CPU time 3.31 seconds
Started Aug 01 05:28:13 PM PDT 24
Finished Aug 01 05:28:16 PM PDT 24
Peak memory 205576 kb
Host smart-a23fcaf8-ebf3-4592-b95f-ad74f0ea7ebe
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4114645387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.4114645387
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.882999183
Short name T71
Test name
Test status
Simulation time 2007430874 ps
CPU time 6.12 seconds
Started Aug 01 05:28:14 PM PDT 24
Finished Aug 01 05:28:20 PM PDT 24
Peak memory 205836 kb
Host smart-ed3af344-a1d7-4a63-8c2b-42f2f48a3880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882999183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.882999183
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3096029191
Short name T109
Test name
Test status
Simulation time 5439870263 ps
CPU time 77.1 seconds
Started Aug 01 05:26:49 PM PDT 24
Finished Aug 01 05:28:07 PM PDT 24
Peak memory 218992 kb
Host smart-bd38808e-d838-497d-bacb-7aca53f88ca9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096029191 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3096029191
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1926481561
Short name T118
Test name
Test status
Simulation time 776411235 ps
CPU time 4.27 seconds
Started Aug 01 05:27:40 PM PDT 24
Finished Aug 01 05:27:45 PM PDT 24
Peak memory 219308 kb
Host smart-52663f08-8573-47f1-a28d-53021e7c7dde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926481561 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1926481561
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.63415694
Short name T462
Test name
Test status
Simulation time 5719359013 ps
CPU time 34.28 seconds
Started Aug 01 05:26:55 PM PDT 24
Finished Aug 01 05:27:29 PM PDT 24
Peak memory 213912 kb
Host smart-c647347b-9526-4fe7-b18f-0290caf12245
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63415694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.63415694
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4108898696
Short name T460
Test name
Test status
Simulation time 392731579 ps
CPU time 1.72 seconds
Started Aug 01 05:26:57 PM PDT 24
Finished Aug 01 05:26:59 PM PDT 24
Peak memory 213788 kb
Host smart-08227131-c8a0-4e8d-b2eb-312287bb5ca4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108898696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.4108898696
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2863909171
Short name T439
Test name
Test status
Simulation time 194609620 ps
CPU time 3.68 seconds
Started Aug 01 05:26:56 PM PDT 24
Finished Aug 01 05:27:00 PM PDT 24
Peak memory 218384 kb
Host smart-ada6d39e-248d-4e21-a7bd-9474e04f772c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863909171 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2863909171
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.3959347950
Short name T88
Test name
Test status
Simulation time 185564767 ps
CPU time 2.5 seconds
Started Aug 01 05:26:55 PM PDT 24
Finished Aug 01 05:26:57 PM PDT 24
Peak memory 213672 kb
Host smart-1fde9d3c-588a-42c2-9a64-71cdc4497b1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959347950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.3959347950
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.636452069
Short name T354
Test name
Test status
Simulation time 96295019546 ps
CPU time 72.45 seconds
Started Aug 01 05:26:55 PM PDT 24
Finished Aug 01 05:28:07 PM PDT 24
Peak memory 205568 kb
Host smart-31455a9d-c08d-4bb3-a2c9-494da962119c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636452069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.636452069
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.3903699887
Short name T324
Test name
Test status
Simulation time 6834500097 ps
CPU time 6 seconds
Started Aug 01 05:27:00 PM PDT 24
Finished Aug 01 05:27:07 PM PDT 24
Peak memory 205492 kb
Host smart-47564a37-2d87-4dcc-906d-13d5530b5592
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903699887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
rv_dm_jtag_dmi_csr_bit_bash.3903699887
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.581132345
Short name T424
Test name
Test status
Simulation time 14029255668 ps
CPU time 6.34 seconds
Started Aug 01 05:26:57 PM PDT 24
Finished Aug 01 05:27:04 PM PDT 24
Peak memory 205644 kb
Host smart-5b3809d5-efb5-44d2-9f5e-f6a382fe4056
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581132345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.581132345
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2451375559
Short name T357
Test name
Test status
Simulation time 1733720603 ps
CPU time 1.17 seconds
Started Aug 01 05:26:56 PM PDT 24
Finished Aug 01 05:26:58 PM PDT 24
Peak memory 205268 kb
Host smart-40fe1e97-0271-432d-af8d-f959ebfa016f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451375559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2451375559
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3930029994
Short name T450
Test name
Test status
Simulation time 780525568 ps
CPU time 1.74 seconds
Started Aug 01 05:26:57 PM PDT 24
Finished Aug 01 05:26:59 PM PDT 24
Peak memory 205296 kb
Host smart-ab207593-ecca-4138-9209-40c5074d4714
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930029994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3930029994
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1172591195
Short name T331
Test name
Test status
Simulation time 139863700 ps
CPU time 0.78 seconds
Started Aug 01 05:26:54 PM PDT 24
Finished Aug 01 05:26:55 PM PDT 24
Peak memory 205260 kb
Host smart-06b99786-36a1-4756-b69c-42083559bc20
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172591195 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
172591195
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.3622963049
Short name T437
Test name
Test status
Simulation time 40770295 ps
CPU time 0.74 seconds
Started Aug 01 05:26:58 PM PDT 24
Finished Aug 01 05:26:58 PM PDT 24
Peak memory 205432 kb
Host smart-29b578a3-af38-4eb1-86e7-ec44305c04b0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622963049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.3622963049
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.2192776011
Short name T382
Test name
Test status
Simulation time 41846080 ps
CPU time 0.71 seconds
Started Aug 01 05:26:55 PM PDT 24
Finished Aug 01 05:26:56 PM PDT 24
Peak memory 205284 kb
Host smart-69d73aa1-c456-42cd-aa15-bb21220dc4bb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192776011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.2192776011
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1281736777
Short name T419
Test name
Test status
Simulation time 96627336 ps
CPU time 3.82 seconds
Started Aug 01 05:26:58 PM PDT 24
Finished Aug 01 05:27:02 PM PDT 24
Peak memory 205600 kb
Host smart-c2d28392-697f-4f8a-b2fe-3493f2d776f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281736777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1281736777
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2452505911
Short name T321
Test name
Test status
Simulation time 130956314 ps
CPU time 3 seconds
Started Aug 01 05:26:58 PM PDT 24
Finished Aug 01 05:27:01 PM PDT 24
Peak memory 213712 kb
Host smart-1593e00b-a5d3-4710-9179-15c2e6c270f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452505911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2452505911
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2509663550
Short name T157
Test name
Test status
Simulation time 1187977212 ps
CPU time 10.9 seconds
Started Aug 01 05:26:55 PM PDT 24
Finished Aug 01 05:27:06 PM PDT 24
Peak memory 213824 kb
Host smart-dbadd85e-5265-4fd4-bec4-cb7905521672
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509663550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2509663550
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4016495790
Short name T84
Test name
Test status
Simulation time 10168976254 ps
CPU time 78.03 seconds
Started Aug 01 05:26:57 PM PDT 24
Finished Aug 01 05:28:15 PM PDT 24
Peak memory 213916 kb
Host smart-2894cf20-63cd-4c65-8de2-a5806c2fc0fd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016495790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.4016495790
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.1808586284
Short name T453
Test name
Test status
Simulation time 2949403707 ps
CPU time 55.04 seconds
Started Aug 01 05:26:54 PM PDT 24
Finished Aug 01 05:27:50 PM PDT 24
Peak memory 205508 kb
Host smart-4519839e-9ef8-47b9-860d-d1509708f5c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808586284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.1808586284
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2527166559
Short name T425
Test name
Test status
Simulation time 274913614 ps
CPU time 2.24 seconds
Started Aug 01 05:27:07 PM PDT 24
Finished Aug 01 05:27:09 PM PDT 24
Peak memory 214204 kb
Host smart-544a7527-5b9b-44eb-bbfa-61d70d9de533
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527166559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2527166559
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3852627394
Short name T332
Test name
Test status
Simulation time 491323362 ps
CPU time 4.88 seconds
Started Aug 01 05:26:55 PM PDT 24
Finished Aug 01 05:27:00 PM PDT 24
Peak memory 221916 kb
Host smart-11e66116-048f-4aa1-8be5-dbc8b1ba9be1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852627394 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3852627394
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2674357117
Short name T467
Test name
Test status
Simulation time 113379603 ps
CPU time 1.41 seconds
Started Aug 01 05:27:02 PM PDT 24
Finished Aug 01 05:27:03 PM PDT 24
Peak memory 213704 kb
Host smart-e53454d9-32fb-4494-9c97-8d004896cdc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674357117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2674357117
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.1943537888
Short name T312
Test name
Test status
Simulation time 56755461840 ps
CPU time 91.82 seconds
Started Aug 01 05:26:56 PM PDT 24
Finished Aug 01 05:28:28 PM PDT 24
Peak memory 205572 kb
Host smart-f89a7105-5160-4603-96bc-82a03137dcad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943537888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.1943537888
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.952159657
Short name T455
Test name
Test status
Simulation time 5190325937 ps
CPU time 8.98 seconds
Started Aug 01 05:26:58 PM PDT 24
Finished Aug 01 05:27:07 PM PDT 24
Peak memory 205588 kb
Host smart-672be85b-8f42-4310-a3ee-1d5e4ee29ee8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952159657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.r
v_dm_jtag_dmi_csr_bit_bash.952159657
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1221623678
Short name T391
Test name
Test status
Simulation time 4489991576 ps
CPU time 11.7 seconds
Started Aug 01 05:26:58 PM PDT 24
Finished Aug 01 05:27:10 PM PDT 24
Peak memory 205716 kb
Host smart-75e1e651-4b51-4009-9c3b-e3370e6aad35
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221623678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1221623678
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.1049824569
Short name T351
Test name
Test status
Simulation time 2710729680 ps
CPU time 1.49 seconds
Started Aug 01 05:27:06 PM PDT 24
Finished Aug 01 05:27:08 PM PDT 24
Peak memory 205548 kb
Host smart-608b9ab4-43e5-4e8a-9ee2-2dd4a949d7ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049824569 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.1
049824569
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1013809077
Short name T317
Test name
Test status
Simulation time 1398329599 ps
CPU time 2.62 seconds
Started Aug 01 05:26:58 PM PDT 24
Finished Aug 01 05:27:01 PM PDT 24
Peak memory 205280 kb
Host smart-56b41fe4-1d1c-40b2-bddf-a24dd1060f1f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013809077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1013809077
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.4142244248
Short name T326
Test name
Test status
Simulation time 15460551692 ps
CPU time 10.33 seconds
Started Aug 01 05:26:56 PM PDT 24
Finished Aug 01 05:27:07 PM PDT 24
Peak memory 205588 kb
Host smart-30037195-5b01-4b24-89c4-7da0f00e70f9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142244248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.4142244248
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.3651364571
Short name T344
Test name
Test status
Simulation time 114234405 ps
CPU time 0.91 seconds
Started Aug 01 05:26:58 PM PDT 24
Finished Aug 01 05:26:59 PM PDT 24
Peak memory 205316 kb
Host smart-5b277ee7-8556-478f-96da-6b3bd0b18cff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651364571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.3651364571
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.3142197744
Short name T394
Test name
Test status
Simulation time 90119164 ps
CPU time 0.9 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:06 PM PDT 24
Peak memory 205232 kb
Host smart-94a4b023-b113-4ed3-8399-d7265b836e39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142197744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.3
142197744
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3437999034
Short name T405
Test name
Test status
Simulation time 172814164 ps
CPU time 1.09 seconds
Started Aug 01 05:26:58 PM PDT 24
Finished Aug 01 05:26:59 PM PDT 24
Peak memory 205296 kb
Host smart-7239ba6b-5122-42e0-bf58-f830cf061c63
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437999034 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3437999034
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1509179068
Short name T412
Test name
Test status
Simulation time 119452940 ps
CPU time 0.74 seconds
Started Aug 01 05:27:06 PM PDT 24
Finished Aug 01 05:27:07 PM PDT 24
Peak memory 205216 kb
Host smart-3ac904d4-5e05-403f-ba4b-3e861380b799
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509179068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1509179068
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.93867928
Short name T396
Test name
Test status
Simulation time 100933027 ps
CPU time 3.75 seconds
Started Aug 01 05:27:06 PM PDT 24
Finished Aug 01 05:27:10 PM PDT 24
Peak memory 205568 kb
Host smart-af8d7d77-475c-4c4c-8385-f24842200489
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93867928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_cs
r_outstanding.93867928
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3737532254
Short name T407
Test name
Test status
Simulation time 21090746843 ps
CPU time 36.76 seconds
Started Aug 01 05:26:57 PM PDT 24
Finished Aug 01 05:27:34 PM PDT 24
Peak memory 222092 kb
Host smart-69021703-e015-4c28-8ef6-5eb84b86e857
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737532254 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3737532254
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.1862053333
Short name T402
Test name
Test status
Simulation time 107193830 ps
CPU time 2.15 seconds
Started Aug 01 05:27:00 PM PDT 24
Finished Aug 01 05:27:02 PM PDT 24
Peak memory 213856 kb
Host smart-a69b4c38-7fa6-495f-b99a-a687b08300ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862053333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.1862053333
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.271883388
Short name T159
Test name
Test status
Simulation time 499846969 ps
CPU time 4.27 seconds
Started Aug 01 05:27:28 PM PDT 24
Finished Aug 01 05:27:33 PM PDT 24
Peak memory 222028 kb
Host smart-6a907b9e-99fb-4a31-9612-063ecc7b40a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271883388 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.271883388
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3109530736
Short name T372
Test name
Test status
Simulation time 87707143 ps
CPU time 1.62 seconds
Started Aug 01 05:27:29 PM PDT 24
Finished Aug 01 05:27:31 PM PDT 24
Peak memory 213708 kb
Host smart-cbdb56d1-1009-44df-bec7-527e4768bfcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109530736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3109530736
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_bit_bash.3760978828
Short name T430
Test name
Test status
Simulation time 6347727118 ps
CPU time 16.05 seconds
Started Aug 01 05:27:28 PM PDT 24
Finished Aug 01 05:27:45 PM PDT 24
Peak memory 205524 kb
Host smart-1a9fcbd6-6b60-4594-a431-45755b9a4f98
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760978828 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.rv_dm_jtag_dmi_csr_bit_bash.3760978828
Directory /workspace/10.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.2512936280
Short name T445
Test name
Test status
Simulation time 10328756269 ps
CPU time 27.54 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:59 PM PDT 24
Peak memory 205560 kb
Host smart-a8f18461-71ba-43bc-9db8-843e151a66d6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512936280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
2512936280
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.4192660052
Short name T352
Test name
Test status
Simulation time 993426201 ps
CPU time 2.25 seconds
Started Aug 01 05:27:27 PM PDT 24
Finished Aug 01 05:27:30 PM PDT 24
Peak memory 205260 kb
Host smart-6b652872-5972-41bd-a17c-e99e81479e17
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192660052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
4192660052
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3940720360
Short name T114
Test name
Test status
Simulation time 926196200 ps
CPU time 7.34 seconds
Started Aug 01 05:27:27 PM PDT 24
Finished Aug 01 05:27:34 PM PDT 24
Peak memory 205652 kb
Host smart-783ae58d-6238-4417-afd2-b08cf1dfa1d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940720360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3940720360
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1031159572
Short name T458
Test name
Test status
Simulation time 214704915 ps
CPU time 4.21 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:36 PM PDT 24
Peak memory 213804 kb
Host smart-d3fcff5c-49fc-4704-89e5-fbc94bca4d7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031159572 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1031159572
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2126060043
Short name T116
Test name
Test status
Simulation time 3720222471 ps
CPU time 10.84 seconds
Started Aug 01 05:27:32 PM PDT 24
Finished Aug 01 05:27:43 PM PDT 24
Peak memory 213888 kb
Host smart-f5dc0e2b-3d1f-41a3-9eea-71c70de36007
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126060043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
126060043
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.194384771
Short name T421
Test name
Test status
Simulation time 1229663353 ps
CPU time 3.73 seconds
Started Aug 01 05:27:28 PM PDT 24
Finished Aug 01 05:27:32 PM PDT 24
Peak memory 218556 kb
Host smart-86f74532-8921-45fe-b3d0-ca22332ec0a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194384771 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.194384771
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2731611749
Short name T86
Test name
Test status
Simulation time 208158972 ps
CPU time 2.13 seconds
Started Aug 01 05:27:28 PM PDT 24
Finished Aug 01 05:27:30 PM PDT 24
Peak memory 213708 kb
Host smart-f16cf8a6-7a4e-4ad4-afe5-4a18ae752c66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731611749 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2731611749
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_bit_bash.2838183795
Short name T322
Test name
Test status
Simulation time 76663604 ps
CPU time 0.69 seconds
Started Aug 01 05:27:29 PM PDT 24
Finished Aug 01 05:27:30 PM PDT 24
Peak memory 205248 kb
Host smart-1e57d89a-8230-48fb-bcb1-c8133dd84068
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838183795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.rv_dm_jtag_dmi_csr_bit_bash.2838183795
Directory /workspace/11.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.2839442480
Short name T444
Test name
Test status
Simulation time 3543095181 ps
CPU time 9.29 seconds
Started Aug 01 05:27:30 PM PDT 24
Finished Aug 01 05:27:39 PM PDT 24
Peak memory 205624 kb
Host smart-a40027d6-b779-40a8-945d-e3e8aae44b68
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839442480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
2839442480
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.309775237
Short name T346
Test name
Test status
Simulation time 226041235 ps
CPU time 0.84 seconds
Started Aug 01 05:27:29 PM PDT 24
Finished Aug 01 05:27:30 PM PDT 24
Peak memory 205284 kb
Host smart-39df8cfc-d4c8-410b-a5d8-fa99e092b6db
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309775237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.309775237
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1722845742
Short name T112
Test name
Test status
Simulation time 4095916204 ps
CPU time 8.44 seconds
Started Aug 01 05:27:28 PM PDT 24
Finished Aug 01 05:27:36 PM PDT 24
Peak memory 205588 kb
Host smart-343491e8-ca71-4d7a-b5d2-bdb0abbcb383
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722845742 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1722845742
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1078989682
Short name T397
Test name
Test status
Simulation time 169625976 ps
CPU time 4.62 seconds
Started Aug 01 05:27:30 PM PDT 24
Finished Aug 01 05:27:35 PM PDT 24
Peak memory 213796 kb
Host smart-917a095b-2627-45b4-8fcc-83fcbccd44e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078989682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1078989682
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.418377560
Short name T151
Test name
Test status
Simulation time 4668230418 ps
CPU time 12.34 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:44 PM PDT 24
Peak memory 213988 kb
Host smart-92467611-90fb-41ae-af28-f4ac17312dff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418377560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.418377560
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.4282341905
Short name T337
Test name
Test status
Simulation time 387568390 ps
CPU time 2.34 seconds
Started Aug 01 05:27:27 PM PDT 24
Finished Aug 01 05:27:30 PM PDT 24
Peak memory 218464 kb
Host smart-2bfcbe89-21bc-47fa-b485-67c4b4176294
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282341905 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.4282341905
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.658815354
Short name T442
Test name
Test status
Simulation time 285966853 ps
CPU time 1.57 seconds
Started Aug 01 05:27:28 PM PDT 24
Finished Aug 01 05:27:30 PM PDT 24
Peak memory 213756 kb
Host smart-c54cd129-2d9b-49ac-af24-290fc66e1e69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658815354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.658815354
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_bit_bash.2679616365
Short name T309
Test name
Test status
Simulation time 4503028138 ps
CPU time 6.75 seconds
Started Aug 01 05:27:28 PM PDT 24
Finished Aug 01 05:27:35 PM PDT 24
Peak memory 205496 kb
Host smart-2b61c4b0-3917-422c-8232-5aa93174a624
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679616365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.rv_dm_jtag_dmi_csr_bit_bash.2679616365
Directory /workspace/12.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3132034299
Short name T368
Test name
Test status
Simulation time 2034373195 ps
CPU time 3.98 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:35 PM PDT 24
Peak memory 205496 kb
Host smart-4e3c4d55-8ccb-42c6-baf7-44542f743ae4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132034299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3132034299
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.80646914
Short name T420
Test name
Test status
Simulation time 181999074 ps
CPU time 0.92 seconds
Started Aug 01 05:27:29 PM PDT 24
Finished Aug 01 05:27:30 PM PDT 24
Peak memory 205288 kb
Host smart-7d881447-ab16-4c97-bf9e-3c3691d4b90a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80646914 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.80646914
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.782761612
Short name T451
Test name
Test status
Simulation time 384648423 ps
CPU time 5.12 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:37 PM PDT 24
Peak memory 213732 kb
Host smart-318f0358-8472-4b25-9b00-7af759d5bc36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782761612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.782761612
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.482512323
Short name T117
Test name
Test status
Simulation time 1097207310 ps
CPU time 12.09 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:43 PM PDT 24
Peak memory 213740 kb
Host smart-70f94541-d823-4985-bd73-92d420879c94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482512323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.482512323
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.217977163
Short name T347
Test name
Test status
Simulation time 245301438 ps
CPU time 4.44 seconds
Started Aug 01 05:27:26 PM PDT 24
Finished Aug 01 05:27:31 PM PDT 24
Peak memory 220068 kb
Host smart-7baeb129-79aa-445f-9618-7eb071957eba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217977163 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.217977163
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.1638023102
Short name T454
Test name
Test status
Simulation time 68472323 ps
CPU time 1.56 seconds
Started Aug 01 05:27:30 PM PDT 24
Finished Aug 01 05:27:32 PM PDT 24
Peak memory 213820 kb
Host smart-c6b9a1bb-3feb-4e16-b1ee-71ef6395e349
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638023102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.1638023102
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_bit_bash.1168482131
Short name T375
Test name
Test status
Simulation time 14803793375 ps
CPU time 7.71 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:39 PM PDT 24
Peak memory 205592 kb
Host smart-fc0da803-1831-44f9-b240-1731250c5bc5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168482131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.rv_dm_jtag_dmi_csr_bit_bash.1168482131
Directory /workspace/13.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2760818710
Short name T333
Test name
Test status
Simulation time 5710810976 ps
CPU time 2.97 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:34 PM PDT 24
Peak memory 205568 kb
Host smart-a75be693-3f55-452e-b51e-d8bd8ecdc9e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760818710 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2760818710
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.2164581020
Short name T355
Test name
Test status
Simulation time 220022656 ps
CPU time 0.82 seconds
Started Aug 01 05:27:29 PM PDT 24
Finished Aug 01 05:27:30 PM PDT 24
Peak memory 205224 kb
Host smart-72c6cbb3-e836-41a5-a908-b32ffbb4c59c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164581020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
2164581020
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2160517960
Short name T113
Test name
Test status
Simulation time 941761844 ps
CPU time 4 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:35 PM PDT 24
Peak memory 205644 kb
Host smart-c5980aa1-0a5c-49b3-bb22-c292a980badc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160517960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2160517960
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.730872153
Short name T365
Test name
Test status
Simulation time 808156528 ps
CPU time 2.56 seconds
Started Aug 01 05:27:27 PM PDT 24
Finished Aug 01 05:27:30 PM PDT 24
Peak memory 213880 kb
Host smart-182bb360-9c37-4663-8ec4-177a7bad7894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730872153 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.730872153
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4159320661
Short name T153
Test name
Test status
Simulation time 3596946509 ps
CPU time 19.09 seconds
Started Aug 01 05:27:30 PM PDT 24
Finished Aug 01 05:27:50 PM PDT 24
Peak memory 213900 kb
Host smart-0a3d3e28-dc05-4aba-88c3-1946e0580523
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159320661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.4
159320661
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3741907588
Short name T374
Test name
Test status
Simulation time 575001131 ps
CPU time 3.64 seconds
Started Aug 01 05:27:29 PM PDT 24
Finished Aug 01 05:27:33 PM PDT 24
Peak memory 218616 kb
Host smart-f10bd42c-5ce6-4837-9327-7e5f774ab0ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741907588 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3741907588
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.105810583
Short name T369
Test name
Test status
Simulation time 177285168 ps
CPU time 2.02 seconds
Started Aug 01 05:27:29 PM PDT 24
Finished Aug 01 05:27:31 PM PDT 24
Peak memory 213676 kb
Host smart-8d92be05-4d89-4cb4-9471-46cc8d0ff73c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105810583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.105810583
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_bit_bash.1888554057
Short name T306
Test name
Test status
Simulation time 22921082591 ps
CPU time 55.65 seconds
Started Aug 01 05:27:28 PM PDT 24
Finished Aug 01 05:28:24 PM PDT 24
Peak memory 205500 kb
Host smart-a3d72c52-1a82-4f69-b904-2c18942dfa78
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888554057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.rv_dm_jtag_dmi_csr_bit_bash.1888554057
Directory /workspace/14.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2739375871
Short name T310
Test name
Test status
Simulation time 2625638053 ps
CPU time 7.59 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:39 PM PDT 24
Peak memory 205604 kb
Host smart-82e59fe5-1b37-4878-85f7-b45141fa1688
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739375871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2739375871
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.2603560696
Short name T335
Test name
Test status
Simulation time 152006465 ps
CPU time 0.76 seconds
Started Aug 01 05:27:29 PM PDT 24
Finished Aug 01 05:27:30 PM PDT 24
Peak memory 205292 kb
Host smart-f5b4bd94-b0b0-4a35-bff0-5d2f22eb585f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603560696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
2603560696
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.680287727
Short name T99
Test name
Test status
Simulation time 531300583 ps
CPU time 7.35 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:39 PM PDT 24
Peak memory 205556 kb
Host smart-d0dc97f3-8d3a-412f-9962-9a2c49d1ddf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680287727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_
csr_outstanding.680287727
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.282616779
Short name T325
Test name
Test status
Simulation time 237663438 ps
CPU time 2.57 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:34 PM PDT 24
Peak memory 213844 kb
Host smart-c9e1b369-ca6f-4324-a1b6-bfdb4ccbf98e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282616779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.282616779
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3051552561
Short name T371
Test name
Test status
Simulation time 1639684252 ps
CPU time 10.78 seconds
Started Aug 01 05:27:30 PM PDT 24
Finished Aug 01 05:27:41 PM PDT 24
Peak memory 213860 kb
Host smart-44a49885-26f0-4ef4-8d5c-14d8a2808bac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051552561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
051552561
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2620265969
Short name T83
Test name
Test status
Simulation time 74222428 ps
CPU time 1.6 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:33 PM PDT 24
Peak memory 213700 kb
Host smart-8d5188f1-9d0b-4ad4-9050-9d7dc09b4afe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620265969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2620265969
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_bit_bash.1100579537
Short name T409
Test name
Test status
Simulation time 16289368130 ps
CPU time 7.88 seconds
Started Aug 01 05:27:41 PM PDT 24
Finished Aug 01 05:27:49 PM PDT 24
Peak memory 205512 kb
Host smart-7d005be3-75c0-4019-940f-8d280a956cf4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100579537 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.rv_dm_jtag_dmi_csr_bit_bash.1100579537
Directory /workspace/15.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.1786811604
Short name T463
Test name
Test status
Simulation time 12925359387 ps
CPU time 10.87 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:42 PM PDT 24
Peak memory 205572 kb
Host smart-0e662980-6088-4cc7-b748-cedc21ab9019
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786811604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
1786811604
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3743990401
Short name T361
Test name
Test status
Simulation time 351669725 ps
CPU time 0.93 seconds
Started Aug 01 05:27:31 PM PDT 24
Finished Aug 01 05:27:32 PM PDT 24
Peak memory 205252 kb
Host smart-92f324ab-5a69-4b0a-888c-062c7f1a5ba6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743990401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3743990401
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1120010616
Short name T398
Test name
Test status
Simulation time 1137038498 ps
CPU time 8.29 seconds
Started Aug 01 05:27:41 PM PDT 24
Finished Aug 01 05:27:49 PM PDT 24
Peak memory 205584 kb
Host smart-fc6b1495-ef81-4e63-b314-445a41b64ca8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120010616 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1120010616
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2382899976
Short name T341
Test name
Test status
Simulation time 604539350 ps
CPU time 3.01 seconds
Started Aug 01 05:27:41 PM PDT 24
Finished Aug 01 05:27:44 PM PDT 24
Peak memory 213764 kb
Host smart-4e543b1e-e3d7-4833-b8bd-80aaff3eefbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382899976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2382899976
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3355222771
Short name T156
Test name
Test status
Simulation time 4302532678 ps
CPU time 16.24 seconds
Started Aug 01 05:27:32 PM PDT 24
Finished Aug 01 05:27:49 PM PDT 24
Peak memory 214040 kb
Host smart-cf57e70a-347a-4d40-97fe-63dfd4104ba2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355222771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
355222771
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1869819533
Short name T349
Test name
Test status
Simulation time 442262263 ps
CPU time 4.1 seconds
Started Aug 01 05:27:40 PM PDT 24
Finished Aug 01 05:27:45 PM PDT 24
Peak memory 220076 kb
Host smart-f0b71497-0761-40f4-9b92-9a66db3acc7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869819533 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1869819533
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1164088641
Short name T89
Test name
Test status
Simulation time 219996211 ps
CPU time 1.8 seconds
Started Aug 01 05:27:39 PM PDT 24
Finished Aug 01 05:27:42 PM PDT 24
Peak memory 213656 kb
Host smart-f8015885-76c8-4d96-a92b-f814241cb7c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164088641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1164088641
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_bit_bash.2044507393
Short name T395
Test name
Test status
Simulation time 16090310942 ps
CPU time 25.07 seconds
Started Aug 01 05:27:30 PM PDT 24
Finished Aug 01 05:27:55 PM PDT 24
Peak memory 205588 kb
Host smart-5f6ee013-87d0-4658-afe3-c67788be8f1b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044507393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.rv_dm_jtag_dmi_csr_bit_bash.2044507393
Directory /workspace/16.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3388973995
Short name T323
Test name
Test status
Simulation time 2558087842 ps
CPU time 3.56 seconds
Started Aug 01 05:27:41 PM PDT 24
Finished Aug 01 05:27:45 PM PDT 24
Peak memory 205524 kb
Host smart-554be83d-c8c5-4dc3-b276-c9beac17126c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388973995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3388973995
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.1985547988
Short name T358
Test name
Test status
Simulation time 129638823 ps
CPU time 0.81 seconds
Started Aug 01 05:27:41 PM PDT 24
Finished Aug 01 05:27:42 PM PDT 24
Peak memory 205208 kb
Host smart-2da7f93b-aaa5-4aba-9e4e-d09ce8aea871
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985547988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
1985547988
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.408319304
Short name T452
Test name
Test status
Simulation time 303004023 ps
CPU time 6.65 seconds
Started Aug 01 05:27:39 PM PDT 24
Finished Aug 01 05:27:46 PM PDT 24
Peak memory 205604 kb
Host smart-0bd4b1a9-2b5a-4717-84ba-9ebf1ac499ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408319304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.408319304
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.1289694091
Short name T311
Test name
Test status
Simulation time 314647220 ps
CPU time 4.93 seconds
Started Aug 01 05:27:40 PM PDT 24
Finished Aug 01 05:27:45 PM PDT 24
Peak memory 213760 kb
Host smart-46248599-75b3-4ea0-9f75-6e6111d4d0fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289694091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.1289694091
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.3370430871
Short name T343
Test name
Test status
Simulation time 3452465440 ps
CPU time 16.44 seconds
Started Aug 01 05:27:44 PM PDT 24
Finished Aug 01 05:28:01 PM PDT 24
Peak memory 213872 kb
Host smart-4a5cbbd1-7f27-4bbe-a9a9-1820c3b505ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370430871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.3
370430871
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.1333591508
Short name T433
Test name
Test status
Simulation time 768182255 ps
CPU time 2.15 seconds
Started Aug 01 05:27:39 PM PDT 24
Finished Aug 01 05:27:41 PM PDT 24
Peak memory 217084 kb
Host smart-de1ca6be-8ef7-48d8-970f-c53723c4fbce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333591508 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.1333591508
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.1905895983
Short name T370
Test name
Test status
Simulation time 81305407 ps
CPU time 1.57 seconds
Started Aug 01 05:27:39 PM PDT 24
Finished Aug 01 05:27:41 PM PDT 24
Peak memory 213676 kb
Host smart-6a453b99-ece8-4ba0-badd-b01c14b469b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905895983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.1905895983
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_bit_bash.1305386444
Short name T406
Test name
Test status
Simulation time 20401179352 ps
CPU time 16.04 seconds
Started Aug 01 05:27:40 PM PDT 24
Finished Aug 01 05:27:56 PM PDT 24
Peak memory 205584 kb
Host smart-fac0694c-730e-494f-b5c0-87e048fa205d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305386444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.rv_dm_jtag_dmi_csr_bit_bash.1305386444
Directory /workspace/17.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.1175340506
Short name T393
Test name
Test status
Simulation time 3751680539 ps
CPU time 6.12 seconds
Started Aug 01 05:27:40 PM PDT 24
Finished Aug 01 05:27:47 PM PDT 24
Peak memory 205680 kb
Host smart-a5303332-a3f5-482c-b9b6-2abe75680c3d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175340506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
1175340506
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2959627214
Short name T417
Test name
Test status
Simulation time 141885330 ps
CPU time 0.75 seconds
Started Aug 01 05:27:40 PM PDT 24
Finished Aug 01 05:27:41 PM PDT 24
Peak memory 205296 kb
Host smart-ae66f87d-94d6-41ed-a3c3-0690b6770067
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959627214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2959627214
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.460731956
Short name T87
Test name
Test status
Simulation time 1282881530 ps
CPU time 8.13 seconds
Started Aug 01 05:27:46 PM PDT 24
Finished Aug 01 05:27:54 PM PDT 24
Peak memory 205584 kb
Host smart-0a51e11c-91dc-4cb5-9b21-0eddd7454a4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460731956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.460731956
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2747396546
Short name T408
Test name
Test status
Simulation time 140770344 ps
CPU time 2.57 seconds
Started Aug 01 05:27:40 PM PDT 24
Finished Aug 01 05:27:42 PM PDT 24
Peak memory 213844 kb
Host smart-b290715b-4b5b-4b0e-a0a8-e89f13a77899
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747396546 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2747396546
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3660331326
Short name T158
Test name
Test status
Simulation time 2116477090 ps
CPU time 17.47 seconds
Started Aug 01 05:27:39 PM PDT 24
Finished Aug 01 05:27:57 PM PDT 24
Peak memory 213856 kb
Host smart-4de5d9d1-dc78-4f7b-a477-fe490c1329c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660331326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
660331326
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.773755635
Short name T348
Test name
Test status
Simulation time 1312887455 ps
CPU time 3.91 seconds
Started Aug 01 05:27:46 PM PDT 24
Finished Aug 01 05:27:50 PM PDT 24
Peak memory 222060 kb
Host smart-c213d5b1-6fe0-464c-8cd7-37f0b002507d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773755635 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.773755635
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.3389450135
Short name T101
Test name
Test status
Simulation time 241614048 ps
CPU time 2.2 seconds
Started Aug 01 05:27:38 PM PDT 24
Finished Aug 01 05:27:40 PM PDT 24
Peak memory 213716 kb
Host smart-a91073b5-868d-4d12-835e-357f9844d51d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389450135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.3389450135
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_bit_bash.3291876123
Short name T338
Test name
Test status
Simulation time 20229954251 ps
CPU time 55.61 seconds
Started Aug 01 05:27:37 PM PDT 24
Finished Aug 01 05:28:32 PM PDT 24
Peak memory 205504 kb
Host smart-18fd9276-a096-4cf0-a2aa-037e0010d577
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291876123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.rv_dm_jtag_dmi_csr_bit_bash.3291876123
Directory /workspace/18.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3909608614
Short name T423
Test name
Test status
Simulation time 1744038822 ps
CPU time 4.26 seconds
Started Aug 01 05:27:40 PM PDT 24
Finished Aug 01 05:27:44 PM PDT 24
Peak memory 205480 kb
Host smart-ec2bf2c7-98a9-40af-b3b8-79e805be0069
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909608614 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3909608614
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1288703345
Short name T385
Test name
Test status
Simulation time 352708568 ps
CPU time 0.92 seconds
Started Aug 01 05:27:38 PM PDT 24
Finished Aug 01 05:27:39 PM PDT 24
Peak memory 205160 kb
Host smart-7616742e-9657-4e45-8f58-83336d7a7760
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288703345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1288703345
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.264809839
Short name T389
Test name
Test status
Simulation time 254205579 ps
CPU time 4.2 seconds
Started Aug 01 05:27:39 PM PDT 24
Finished Aug 01 05:27:43 PM PDT 24
Peak memory 205664 kb
Host smart-8495d662-c2a3-4309-805f-30204b52d833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264809839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.264809839
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.223967905
Short name T384
Test name
Test status
Simulation time 287638866 ps
CPU time 3.5 seconds
Started Aug 01 05:27:41 PM PDT 24
Finished Aug 01 05:27:45 PM PDT 24
Peak memory 213916 kb
Host smart-1d6b1b41-4b4b-450c-b4cd-a90ade5d3829
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223967905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.223967905
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.3184615498
Short name T353
Test name
Test status
Simulation time 1298501422 ps
CPU time 10.12 seconds
Started Aug 01 05:27:46 PM PDT 24
Finished Aug 01 05:27:56 PM PDT 24
Peak memory 213792 kb
Host smart-63bea0df-2f27-4f2d-bcd6-c1857e508404
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184615498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.3
184615498
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.2923010979
Short name T411
Test name
Test status
Simulation time 588311109 ps
CPU time 2.25 seconds
Started Aug 01 05:27:36 PM PDT 24
Finished Aug 01 05:27:39 PM PDT 24
Peak memory 213872 kb
Host smart-e36d35ce-88fc-4570-bacd-3cff87804a54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923010979 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.2923010979
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.713063665
Short name T383
Test name
Test status
Simulation time 265311008 ps
CPU time 1.59 seconds
Started Aug 01 05:27:36 PM PDT 24
Finished Aug 01 05:27:38 PM PDT 24
Peak memory 213804 kb
Host smart-9e98600a-c111-442e-9a59-9dce2ac6ccaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713063665 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.713063665
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_bit_bash.387384408
Short name T316
Test name
Test status
Simulation time 19098144925 ps
CPU time 26.96 seconds
Started Aug 01 05:27:39 PM PDT 24
Finished Aug 01 05:28:06 PM PDT 24
Peak memory 205572 kb
Host smart-62f9ce61-2731-4471-b8f8-75636a131fde
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387384408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=
rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
rv_dm_jtag_dmi_csr_bit_bash.387384408
Directory /workspace/19.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2653494276
Short name T440
Test name
Test status
Simulation time 2552518712 ps
CPU time 2.84 seconds
Started Aug 01 05:27:38 PM PDT 24
Finished Aug 01 05:27:41 PM PDT 24
Peak memory 205532 kb
Host smart-a1a65c34-64e9-4609-9bc6-25b927b86e55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653494276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2653494276
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2112048017
Short name T364
Test name
Test status
Simulation time 235784683 ps
CPU time 0.77 seconds
Started Aug 01 05:27:39 PM PDT 24
Finished Aug 01 05:27:40 PM PDT 24
Peak memory 205252 kb
Host smart-9ca00903-e14e-4606-abdf-8762da0b579e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112048017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2112048017
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.918010647
Short name T97
Test name
Test status
Simulation time 2095441209 ps
CPU time 7.8 seconds
Started Aug 01 05:27:40 PM PDT 24
Finished Aug 01 05:27:48 PM PDT 24
Peak memory 205600 kb
Host smart-0a931a7d-8f8b-405e-96bc-4a7d2a41b18e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918010647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_
csr_outstanding.918010647
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3077473633
Short name T362
Test name
Test status
Simulation time 177552471 ps
CPU time 2.13 seconds
Started Aug 01 05:27:39 PM PDT 24
Finished Aug 01 05:27:41 PM PDT 24
Peak memory 213880 kb
Host smart-6babe944-f071-4b8b-86c7-3c9f05eb944a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077473633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3077473633
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3295405437
Short name T464
Test name
Test status
Simulation time 7509262862 ps
CPU time 23.03 seconds
Started Aug 01 05:27:40 PM PDT 24
Finished Aug 01 05:28:03 PM PDT 24
Peak memory 221824 kb
Host smart-7a26e286-2e6e-42f9-add7-1ed7427c7991
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295405437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
295405437
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.2005236962
Short name T360
Test name
Test status
Simulation time 7058242466 ps
CPU time 54.05 seconds
Started Aug 01 05:27:07 PM PDT 24
Finished Aug 01 05:28:01 PM PDT 24
Peak memory 213816 kb
Host smart-01857343-908c-43cf-a9a6-ec1960abfcc9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005236962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.2005236962
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1004416836
Short name T103
Test name
Test status
Simulation time 504369857 ps
CPU time 2.53 seconds
Started Aug 01 05:27:06 PM PDT 24
Finished Aug 01 05:27:09 PM PDT 24
Peak memory 213740 kb
Host smart-3aeea4e6-e58f-4d45-8c35-7e1d879e98a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004416836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1004416836
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.3398682312
Short name T315
Test name
Test status
Simulation time 136593716 ps
CPU time 2.86 seconds
Started Aug 01 05:27:04 PM PDT 24
Finished Aug 01 05:27:07 PM PDT 24
Peak memory 213852 kb
Host smart-8f664ea0-df6b-4e4e-a593-0f408195b0f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398682312 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.3398682312
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3307036435
Short name T104
Test name
Test status
Simulation time 320224516 ps
CPU time 1.99 seconds
Started Aug 01 05:27:06 PM PDT 24
Finished Aug 01 05:27:08 PM PDT 24
Peak memory 213768 kb
Host smart-7961323f-7670-4cd6-b24d-70add0d8f7e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307036435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3307036435
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.1749732467
Short name T342
Test name
Test status
Simulation time 120748877132 ps
CPU time 349.22 seconds
Started Aug 01 05:26:57 PM PDT 24
Finished Aug 01 05:32:46 PM PDT 24
Peak memory 205600 kb
Host smart-88e9ce95-8fb6-4f89-b911-8b1fd235a836
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749732467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.1749732467
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.4015179251
Short name T400
Test name
Test status
Simulation time 10653281241 ps
CPU time 31.85 seconds
Started Aug 01 05:26:58 PM PDT 24
Finished Aug 01 05:27:30 PM PDT 24
Peak memory 205552 kb
Host smart-61e2d16a-0b45-45f6-b368-9a1678247f03
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015179251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
rv_dm_jtag_dmi_csr_bit_bash.4015179251
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1793437703
Short name T92
Test name
Test status
Simulation time 7717902263 ps
CPU time 21.26 seconds
Started Aug 01 05:27:01 PM PDT 24
Finished Aug 01 05:27:22 PM PDT 24
Peak memory 205620 kb
Host smart-d8fa9f83-cb55-4c11-86ec-f22c9fa51796
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793437703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1793437703
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1860125527
Short name T367
Test name
Test status
Simulation time 5502385915 ps
CPU time 7.53 seconds
Started Aug 01 05:26:54 PM PDT 24
Finished Aug 01 05:27:01 PM PDT 24
Peak memory 205600 kb
Host smart-3d24e77e-e109-485a-bf40-99d57921d378
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860125527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
860125527
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.4009173380
Short name T320
Test name
Test status
Simulation time 1037606699 ps
CPU time 2.2 seconds
Started Aug 01 05:26:54 PM PDT 24
Finished Aug 01 05:26:56 PM PDT 24
Peak memory 205292 kb
Host smart-31506466-ed22-4ddc-b643-62ae217a55bc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009173380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.4009173380
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.989121736
Short name T380
Test name
Test status
Simulation time 15956166063 ps
CPU time 28.31 seconds
Started Aug 01 05:27:06 PM PDT 24
Finished Aug 01 05:27:35 PM PDT 24
Peak memory 205512 kb
Host smart-23e2cf78-6697-4776-877e-54e8f3710f3d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989121736 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_bit_bash.989121736
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2890525358
Short name T373
Test name
Test status
Simulation time 182870285 ps
CPU time 1.18 seconds
Started Aug 01 05:27:01 PM PDT 24
Finished Aug 01 05:27:03 PM PDT 24
Peak memory 205256 kb
Host smart-73547e14-d534-40fc-bd62-c60d591cfb22
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890525358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2890525358
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.922465040
Short name T422
Test name
Test status
Simulation time 705010384 ps
CPU time 1.51 seconds
Started Aug 01 05:26:57 PM PDT 24
Finished Aug 01 05:26:59 PM PDT 24
Peak memory 205232 kb
Host smart-aff65756-3789-4c1e-aa42-586bfbdf2d0e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922465040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.922465040
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.58172143
Short name T313
Test name
Test status
Simulation time 76884528 ps
CPU time 0.68 seconds
Started Aug 01 05:27:07 PM PDT 24
Finished Aug 01 05:27:08 PM PDT 24
Peak memory 205332 kb
Host smart-f07fb525-8a38-4f1a-aaa6-e744ca064e1e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58172143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_parti
al_access.58172143
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.683431494
Short name T418
Test name
Test status
Simulation time 47210592 ps
CPU time 0.72 seconds
Started Aug 01 05:27:04 PM PDT 24
Finished Aug 01 05:27:05 PM PDT 24
Peak memory 205284 kb
Host smart-bc266146-6d27-4184-ac08-be5b4f8cf2a8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683431494 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.683431494
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.878092287
Short name T392
Test name
Test status
Simulation time 959479573 ps
CPU time 4.49 seconds
Started Aug 01 05:27:06 PM PDT 24
Finished Aug 01 05:27:11 PM PDT 24
Peak memory 205644 kb
Host smart-f414b852-74e5-4421-a227-5b66d7ad9216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878092287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_c
sr_outstanding.878092287
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2172682969
Short name T432
Test name
Test status
Simulation time 15179576999 ps
CPU time 50.31 seconds
Started Aug 01 05:26:54 PM PDT 24
Finished Aug 01 05:27:44 PM PDT 24
Peak memory 221888 kb
Host smart-644884cf-cec9-4caf-b904-52ec497d69dc
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172682969 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2172682969
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1930755233
Short name T429
Test name
Test status
Simulation time 211133610 ps
CPU time 2.49 seconds
Started Aug 01 05:27:07 PM PDT 24
Finished Aug 01 05:27:09 PM PDT 24
Peak memory 213880 kb
Host smart-4b85c35d-036c-4f40-a6c7-dcb83c1cbd4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930755233 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1930755233
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.313786258
Short name T150
Test name
Test status
Simulation time 3677961886 ps
CPU time 16.94 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:22 PM PDT 24
Peak memory 213980 kb
Host smart-293c7f0d-5b54-4d12-bbb8-b354f8f2cdc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313786258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.313786258
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3251943039
Short name T410
Test name
Test status
Simulation time 1131541052 ps
CPU time 27.15 seconds
Started Aug 01 05:27:07 PM PDT 24
Finished Aug 01 05:27:35 PM PDT 24
Peak memory 205456 kb
Host smart-8ceac296-faa8-4531-905b-e7f849ccfa26
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251943039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3251943039
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.804025807
Short name T100
Test name
Test status
Simulation time 9796238047 ps
CPU time 33.73 seconds
Started Aug 01 05:27:04 PM PDT 24
Finished Aug 01 05:27:38 PM PDT 24
Peak memory 205620 kb
Host smart-e72cb505-76f9-4f8b-b80a-d4d1fb55aece
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804025807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.804025807
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1158488832
Short name T356
Test name
Test status
Simulation time 153397353 ps
CPU time 1.75 seconds
Started Aug 01 05:27:08 PM PDT 24
Finished Aug 01 05:27:10 PM PDT 24
Peak memory 213760 kb
Host smart-49f1a80e-4090-4e57-aadb-30c1f07b57e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158488832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1158488832
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.1706082836
Short name T441
Test name
Test status
Simulation time 466137858 ps
CPU time 3.9 seconds
Started Aug 01 05:27:07 PM PDT 24
Finished Aug 01 05:27:11 PM PDT 24
Peak memory 221676 kb
Host smart-a52b260f-228d-4bfa-8d5f-96817c179244
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706082836 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.1706082836
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2980398645
Short name T339
Test name
Test status
Simulation time 136369609546 ps
CPU time 374.94 seconds
Started Aug 01 05:27:07 PM PDT 24
Finished Aug 01 05:33:23 PM PDT 24
Peak memory 205784 kb
Host smart-8e50d088-865b-4bb2-9ad4-93ad7d0110c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980398645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2980398645
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1426028039
Short name T447
Test name
Test status
Simulation time 3058107023 ps
CPU time 7.91 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:13 PM PDT 24
Peak memory 205552 kb
Host smart-96fecbfc-5593-4192-878a-3ed8fb12f118
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426028039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
rv_dm_jtag_dmi_csr_bit_bash.1426028039
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3657143187
Short name T94
Test name
Test status
Simulation time 19131860394 ps
CPU time 25.13 seconds
Started Aug 01 05:27:07 PM PDT 24
Finished Aug 01 05:27:33 PM PDT 24
Peak memory 205664 kb
Host smart-a59e77de-57c9-47b7-a9bc-63c5e2e1f609
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657143187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3657143187
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.2301603245
Short name T404
Test name
Test status
Simulation time 14723371918 ps
CPU time 38.75 seconds
Started Aug 01 05:27:06 PM PDT 24
Finished Aug 01 05:27:45 PM PDT 24
Peak memory 205588 kb
Host smart-09ec1768-d91d-4a3b-a3a1-0e2caf9c6185
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301603245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.2
301603245
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1327806642
Short name T328
Test name
Test status
Simulation time 567029799 ps
CPU time 0.95 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:06 PM PDT 24
Peak memory 205208 kb
Host smart-97d41ce0-0f6f-4d9f-9e54-f7132a20eea1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327806642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1327806642
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2421620568
Short name T59
Test name
Test status
Simulation time 36014743053 ps
CPU time 100.51 seconds
Started Aug 01 05:27:04 PM PDT 24
Finished Aug 01 05:28:44 PM PDT 24
Peak memory 205512 kb
Host smart-1fcc5335-bc04-473b-a001-4fbde20c4a0b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421620568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2421620568
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.4265818639
Short name T443
Test name
Test status
Simulation time 561749306 ps
CPU time 2.31 seconds
Started Aug 01 05:27:06 PM PDT 24
Finished Aug 01 05:27:08 PM PDT 24
Peak memory 205340 kb
Host smart-56e7df61-2448-4a68-9d9c-3d14231cbbf0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265818639 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.4265818639
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.3379759615
Short name T436
Test name
Test status
Simulation time 272526735 ps
CPU time 1.39 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:07 PM PDT 24
Peak memory 205224 kb
Host smart-0339d99b-f525-48b5-9437-ef35110d4a67
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379759615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.3
379759615
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.1148449644
Short name T413
Test name
Test status
Simulation time 63550126 ps
CPU time 0.68 seconds
Started Aug 01 05:27:07 PM PDT 24
Finished Aug 01 05:27:07 PM PDT 24
Peak memory 205432 kb
Host smart-3ddb5e5c-ddb3-481d-87e1-fd2f0c80acc1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148449644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.1148449644
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.382279203
Short name T334
Test name
Test status
Simulation time 56692721 ps
CPU time 0.77 seconds
Started Aug 01 05:27:08 PM PDT 24
Finished Aug 01 05:27:09 PM PDT 24
Peak memory 205144 kb
Host smart-0ff00dc9-bf00-4302-b1f4-8e84833b7470
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382279203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.382279203
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.1318047031
Short name T414
Test name
Test status
Simulation time 196274954 ps
CPU time 3.95 seconds
Started Aug 01 05:27:07 PM PDT 24
Finished Aug 01 05:27:12 PM PDT 24
Peak memory 205632 kb
Host smart-8b1f41bd-30dc-4f14-82cb-58365afd5e73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318047031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.1318047031
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.4080045073
Short name T378
Test name
Test status
Simulation time 24312757525 ps
CPU time 22.04 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:27 PM PDT 24
Peak memory 221808 kb
Host smart-95e67fa7-3fcc-4c74-be71-4dda9aff6f5e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080045073 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.4080045073
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.2659851327
Short name T119
Test name
Test status
Simulation time 114242717 ps
CPU time 2.6 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:07 PM PDT 24
Peak memory 213892 kb
Host smart-4b8381bf-c574-4f2c-83e8-0f6325fb5c16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659851327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.2659851327
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3767735813
Short name T82
Test name
Test status
Simulation time 630487164 ps
CPU time 27.15 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:33 PM PDT 24
Peak memory 205572 kb
Host smart-3bab6931-78ac-41d4-81d9-0bf62624173a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767735813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3767735813
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3053715602
Short name T110
Test name
Test status
Simulation time 1483301559 ps
CPU time 53.47 seconds
Started Aug 01 05:27:18 PM PDT 24
Finished Aug 01 05:28:12 PM PDT 24
Peak memory 205424 kb
Host smart-d96dcd7d-e61d-46ae-b156-e854d417bbbb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053715602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3053715602
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.99557479
Short name T105
Test name
Test status
Simulation time 286884955 ps
CPU time 2.39 seconds
Started Aug 01 05:27:06 PM PDT 24
Finished Aug 01 05:27:08 PM PDT 24
Peak memory 213788 kb
Host smart-25d6d42c-b8f8-4256-ba52-234fbb800a08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99557479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.99557479
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1000435881
Short name T461
Test name
Test status
Simulation time 322108265 ps
CPU time 3.93 seconds
Started Aug 01 05:27:17 PM PDT 24
Finished Aug 01 05:27:21 PM PDT 24
Peak memory 219172 kb
Host smart-3fde192d-744d-40ab-83f8-df374d50841d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000435881 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1000435881
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.4275580473
Short name T108
Test name
Test status
Simulation time 242222298 ps
CPU time 1.46 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:06 PM PDT 24
Peak memory 213704 kb
Host smart-7a1adab5-2ffd-4da5-866d-37dbc3d42ffa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275580473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.4275580473
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.4068998974
Short name T359
Test name
Test status
Simulation time 152943377119 ps
CPU time 440.63 seconds
Started Aug 01 05:27:06 PM PDT 24
Finished Aug 01 05:34:27 PM PDT 24
Peak memory 206668 kb
Host smart-8fe5ee15-0ab9-439c-8425-da9242a5b8a8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068998974 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.4068998974
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.2686647868
Short name T427
Test name
Test status
Simulation time 43439339689 ps
CPU time 34.44 seconds
Started Aug 01 05:27:08 PM PDT 24
Finished Aug 01 05:27:42 PM PDT 24
Peak memory 205468 kb
Host smart-9654aaab-3aa6-43fd-a6f9-249782b32a9b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686647868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
rv_dm_jtag_dmi_csr_bit_bash.2686647868
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2330132387
Short name T93
Test name
Test status
Simulation time 18491009471 ps
CPU time 23.58 seconds
Started Aug 01 05:27:06 PM PDT 24
Finished Aug 01 05:27:30 PM PDT 24
Peak memory 205656 kb
Host smart-162d1057-b6dc-4093-b5a5-4ba0287b67fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330132387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2330132387
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.4055688180
Short name T387
Test name
Test status
Simulation time 1087894828 ps
CPU time 3.54 seconds
Started Aug 01 05:27:04 PM PDT 24
Finished Aug 01 05:27:08 PM PDT 24
Peak memory 205472 kb
Host smart-8b7240a5-453e-4990-a61b-9f7f06f0e1c0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055688180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.4
055688180
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2945393197
Short name T58
Test name
Test status
Simulation time 988381688 ps
CPU time 3.07 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:08 PM PDT 24
Peak memory 205256 kb
Host smart-2894d037-de43-444e-abf4-29c5778e0900
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945393197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2945393197
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.3581846312
Short name T363
Test name
Test status
Simulation time 10389864468 ps
CPU time 28.92 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:34 PM PDT 24
Peak memory 205496 kb
Host smart-e4d2e25b-ed00-4063-b508-a8f68e08a025
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581846312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.3581846312
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.2138776333
Short name T428
Test name
Test status
Simulation time 271378466 ps
CPU time 0.84 seconds
Started Aug 01 05:27:07 PM PDT 24
Finished Aug 01 05:27:08 PM PDT 24
Peak memory 205312 kb
Host smart-36e80ae8-0e8c-48cc-aecb-27b7d124432e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138776333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.2138776333
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.56341799
Short name T381
Test name
Test status
Simulation time 418011702 ps
CPU time 1.15 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:06 PM PDT 24
Peak memory 205188 kb
Host smart-261dc6b8-a093-4df4-9916-3b68f59a2563
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56341799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.56341799
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.2583605997
Short name T327
Test name
Test status
Simulation time 106097394 ps
CPU time 0.91 seconds
Started Aug 01 05:27:07 PM PDT 24
Finished Aug 01 05:27:08 PM PDT 24
Peak memory 205432 kb
Host smart-59d1e929-a1e0-4230-a06c-6e2c7db2d35d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583605997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.2583605997
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.4157760070
Short name T434
Test name
Test status
Simulation time 33195296 ps
CPU time 0.78 seconds
Started Aug 01 05:27:04 PM PDT 24
Finished Aug 01 05:27:05 PM PDT 24
Peak memory 205288 kb
Host smart-09e9192e-36d9-4a33-a6cc-fe2aae6442de
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157760070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.4157760070
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.4028215268
Short name T111
Test name
Test status
Simulation time 723489509 ps
CPU time 7.91 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:23 PM PDT 24
Peak memory 205680 kb
Host smart-8bd224a2-c634-4ee1-b90d-fe8abd2e8001
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028215268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.4028215268
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.882093414
Short name T388
Test name
Test status
Simulation time 513143538 ps
CPU time 4.91 seconds
Started Aug 01 05:27:05 PM PDT 24
Finished Aug 01 05:27:10 PM PDT 24
Peak memory 213884 kb
Host smart-60d441e4-968d-479a-b4fc-cc2e9599279e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882093414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.882093414
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.3034827216
Short name T350
Test name
Test status
Simulation time 1099284847 ps
CPU time 11.14 seconds
Started Aug 01 05:27:07 PM PDT 24
Finished Aug 01 05:27:19 PM PDT 24
Peak memory 213812 kb
Host smart-56f5d65c-a038-4434-9e48-f4b8768ee9c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034827216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.3034827216
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2375436970
Short name T377
Test name
Test status
Simulation time 343098782 ps
CPU time 3.49 seconds
Started Aug 01 05:27:16 PM PDT 24
Finished Aug 01 05:27:20 PM PDT 24
Peak memory 222068 kb
Host smart-f93456e1-d03f-4f27-9279-4c8731155c29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375436970 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2375436970
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.517657241
Short name T399
Test name
Test status
Simulation time 480096312 ps
CPU time 2.43 seconds
Started Aug 01 05:27:19 PM PDT 24
Finished Aug 01 05:27:22 PM PDT 24
Peak memory 213776 kb
Host smart-50a3f384-049a-44ad-8e77-8dfe4a6f26ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517657241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.517657241
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_bit_bash.1928319343
Short name T307
Test name
Test status
Simulation time 3636882274 ps
CPU time 3.85 seconds
Started Aug 01 05:27:17 PM PDT 24
Finished Aug 01 05:27:21 PM PDT 24
Peak memory 205572 kb
Host smart-35249a1c-4b6e-446a-a569-7c4848135706
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928319343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
rv_dm_jtag_dmi_csr_bit_bash.1928319343
Directory /workspace/5.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.355632327
Short name T329
Test name
Test status
Simulation time 2547346654 ps
CPU time 3.3 seconds
Started Aug 01 05:27:16 PM PDT 24
Finished Aug 01 05:27:20 PM PDT 24
Peak memory 205560 kb
Host smart-4215c195-604a-4e43-b0b6-6e1b602c88d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355632327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.355632327
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1539939483
Short name T330
Test name
Test status
Simulation time 220356392 ps
CPU time 1 seconds
Started Aug 01 05:27:16 PM PDT 24
Finished Aug 01 05:27:17 PM PDT 24
Peak memory 205284 kb
Host smart-7feb1439-2ef9-4d80-a5e5-716b837f5629
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539939483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
539939483
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2634205804
Short name T102
Test name
Test status
Simulation time 429726767 ps
CPU time 4.05 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:20 PM PDT 24
Peak memory 205588 kb
Host smart-cb3f09c7-9741-4de3-87bb-c81cbb2bb8b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634205804 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2634205804
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.3609591630
Short name T403
Test name
Test status
Simulation time 52032183222 ps
CPU time 110.53 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:29:06 PM PDT 24
Peak memory 222052 kb
Host smart-220ae5a1-b196-475f-9cf2-7f0864860902
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609591630 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.3609591630
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.642546224
Short name T376
Test name
Test status
Simulation time 221280794 ps
CPU time 4.38 seconds
Started Aug 01 05:27:14 PM PDT 24
Finished Aug 01 05:27:19 PM PDT 24
Peak memory 213880 kb
Host smart-1396d591-51a4-43bb-81a2-572546b4859c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642546224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.642546224
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.2723855180
Short name T154
Test name
Test status
Simulation time 8005835996 ps
CPU time 16.33 seconds
Started Aug 01 05:27:16 PM PDT 24
Finished Aug 01 05:27:32 PM PDT 24
Peak memory 213948 kb
Host smart-ead68d62-f047-42d0-ba61-1bc558821a60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723855180 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.2723855180
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.694139221
Short name T308
Test name
Test status
Simulation time 197393639 ps
CPU time 2.44 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:18 PM PDT 24
Peak memory 218676 kb
Host smart-0e69c7a7-8fc5-47e9-8c4b-3f898043938a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694139221 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.694139221
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.964258784
Short name T340
Test name
Test status
Simulation time 67470320 ps
CPU time 1.67 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:17 PM PDT 24
Peak memory 213700 kb
Host smart-d72683f6-a30b-4e0d-b17d-46746f2c8572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964258784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.964258784
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_bit_bash.2090165237
Short name T379
Test name
Test status
Simulation time 16026557896 ps
CPU time 14.61 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:30 PM PDT 24
Peak memory 205592 kb
Host smart-a49aaf86-3355-4690-a099-2003696196a2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090165237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
rv_dm_jtag_dmi_csr_bit_bash.2090165237
Directory /workspace/6.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3755150234
Short name T386
Test name
Test status
Simulation time 6088941496 ps
CPU time 17.24 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:33 PM PDT 24
Peak memory 205600 kb
Host smart-bc1502a5-059a-4a30-9e5f-5c4ef8f46144
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755150234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
755150234
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2307556126
Short name T438
Test name
Test status
Simulation time 145851092 ps
CPU time 0.82 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:16 PM PDT 24
Peak memory 205300 kb
Host smart-149aae85-fd57-41c7-9bef-c42fec4da5df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307556126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
307556126
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.929668060
Short name T448
Test name
Test status
Simulation time 1873234087 ps
CPU time 8.84 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:24 PM PDT 24
Peak memory 205576 kb
Host smart-8792bb0e-86cc-4ac5-a564-b4dc4a237f9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929668060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_c
sr_outstanding.929668060
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tap_fsm_rand_reset.1223464456
Short name T456
Test name
Test status
Simulation time 20561180626 ps
CPU time 12.88 seconds
Started Aug 01 05:27:18 PM PDT 24
Finished Aug 01 05:27:31 PM PDT 24
Peak memory 222028 kb
Host smart-a1d8d099-e5bc-439a-98f2-dafedcfffdff
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223464456 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rv_dm_tap_fsm_rand_reset.1223464456
Directory /workspace/6.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.202426309
Short name T336
Test name
Test status
Simulation time 164265917 ps
CPU time 3.88 seconds
Started Aug 01 05:27:16 PM PDT 24
Finished Aug 01 05:27:20 PM PDT 24
Peak memory 213900 kb
Host smart-b1b5c37e-444e-49b4-af33-761e33b32d8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202426309 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.202426309
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.3486962440
Short name T76
Test name
Test status
Simulation time 376718446 ps
CPU time 2.68 seconds
Started Aug 01 05:27:18 PM PDT 24
Finished Aug 01 05:27:21 PM PDT 24
Peak memory 213924 kb
Host smart-0ac8778e-45c7-4f8d-979a-9d50d1b432fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486962440 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.3486962440
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3289111212
Short name T98
Test name
Test status
Simulation time 95332273 ps
CPU time 2.23 seconds
Started Aug 01 05:27:21 PM PDT 24
Finished Aug 01 05:27:24 PM PDT 24
Peak memory 213696 kb
Host smart-033607ae-6582-409e-82e6-d122eea6f73c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289111212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3289111212
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_bit_bash.2206258442
Short name T390
Test name
Test status
Simulation time 3321996945 ps
CPU time 5.65 seconds
Started Aug 01 05:27:18 PM PDT 24
Finished Aug 01 05:27:24 PM PDT 24
Peak memory 205464 kb
Host smart-baadbb2d-6b66-437d-b311-ab8f002c8c90
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206258442 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
rv_dm_jtag_dmi_csr_bit_bash.2206258442
Directory /workspace/7.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.3971910893
Short name T318
Test name
Test status
Simulation time 6160349785 ps
CPU time 8.98 seconds
Started Aug 01 05:27:14 PM PDT 24
Finished Aug 01 05:27:23 PM PDT 24
Peak memory 205556 kb
Host smart-b88f56fa-91ee-429b-bac5-2d5bfb775c39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971910893 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.3
971910893
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.3241081177
Short name T426
Test name
Test status
Simulation time 283463222 ps
CPU time 0.77 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:16 PM PDT 24
Peak memory 205268 kb
Host smart-1478d411-1a48-4728-b521-83cbfe026722
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241081177 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.3
241081177
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.53716228
Short name T81
Test name
Test status
Simulation time 1057909257 ps
CPU time 7.68 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:23 PM PDT 24
Peak memory 205668 kb
Host smart-3563cbb9-47d1-4770-bb36-36bc2691b470
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53716228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_cs
r_outstanding.53716228
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.444309081
Short name T160
Test name
Test status
Simulation time 39207790186 ps
CPU time 44.26 seconds
Started Aug 01 05:27:18 PM PDT 24
Finished Aug 01 05:28:02 PM PDT 24
Peak memory 222040 kb
Host smart-c6777c1e-ebc2-4dc9-8d3b-3773592828d7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444309081 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.444309081
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.3499558699
Short name T120
Test name
Test status
Simulation time 230004692 ps
CPU time 5.44 seconds
Started Aug 01 05:27:17 PM PDT 24
Finished Aug 01 05:27:23 PM PDT 24
Peak memory 213876 kb
Host smart-3c6400a1-db38-45fb-afd5-748aa3940c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499558699 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.3499558699
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2558523437
Short name T466
Test name
Test status
Simulation time 2429119167 ps
CPU time 11.36 seconds
Started Aug 01 05:27:16 PM PDT 24
Finished Aug 01 05:27:28 PM PDT 24
Peak memory 213940 kb
Host smart-901c9261-511c-437f-bd84-3fdfb106a2b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558523437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2558523437
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2169415571
Short name T345
Test name
Test status
Simulation time 701025312 ps
CPU time 4.02 seconds
Started Aug 01 05:27:17 PM PDT 24
Finished Aug 01 05:27:21 PM PDT 24
Peak memory 221892 kb
Host smart-a2cd4bf7-5c79-4060-b204-fd34f0e68399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169415571 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2169415571
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.164636953
Short name T446
Test name
Test status
Simulation time 187043503 ps
CPU time 2.57 seconds
Started Aug 01 05:27:18 PM PDT 24
Finished Aug 01 05:27:21 PM PDT 24
Peak memory 213640 kb
Host smart-f10dca94-f7ad-4561-9338-a8f8a47acc5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164636953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.164636953
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_bit_bash.1698891674
Short name T435
Test name
Test status
Simulation time 26552848734 ps
CPU time 17.27 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:32 PM PDT 24
Peak memory 205544 kb
Host smart-9056f1c6-5d45-4601-a45e-18b9205601b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698891674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
rv_dm_jtag_dmi_csr_bit_bash.1698891674
Directory /workspace/8.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.3509901617
Short name T459
Test name
Test status
Simulation time 4720482066 ps
CPU time 4.27 seconds
Started Aug 01 05:27:19 PM PDT 24
Finished Aug 01 05:27:24 PM PDT 24
Peak memory 205524 kb
Host smart-e41193fc-88e9-4812-8339-955e3fa23710
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509901617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.3
509901617
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2223145295
Short name T366
Test name
Test status
Simulation time 136463411 ps
CPU time 0.86 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:16 PM PDT 24
Peak memory 205228 kb
Host smart-c4ff747d-4b72-4968-8c46-eba60496e80e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223145295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
223145295
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.3835816562
Short name T106
Test name
Test status
Simulation time 605619628 ps
CPU time 4.44 seconds
Started Aug 01 05:27:17 PM PDT 24
Finished Aug 01 05:27:21 PM PDT 24
Peak memory 205556 kb
Host smart-39fa20b7-66d7-4468-b895-c144efd37be3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835816562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.3835816562
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.1552860599
Short name T416
Test name
Test status
Simulation time 31468981909 ps
CPU time 26.99 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:42 PM PDT 24
Peak memory 230280 kb
Host smart-43d13f3c-626f-4e94-a1eb-d9c16dd1768f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552860599 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.1552860599
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2688552667
Short name T319
Test name
Test status
Simulation time 628027101 ps
CPU time 4.88 seconds
Started Aug 01 05:27:20 PM PDT 24
Finished Aug 01 05:27:24 PM PDT 24
Peak memory 213844 kb
Host smart-d4afc25e-d154-407c-8f0a-46929c4c1dbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688552667 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2688552667
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3984621241
Short name T155
Test name
Test status
Simulation time 6555718562 ps
CPU time 11.48 seconds
Started Aug 01 05:27:16 PM PDT 24
Finished Aug 01 05:27:28 PM PDT 24
Peak memory 213876 kb
Host smart-2e255779-d74e-4c35-96ec-c87f83c1d33f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984621241 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3984621241
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.616023688
Short name T465
Test name
Test status
Simulation time 811310054 ps
CPU time 3.97 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:19 PM PDT 24
Peak memory 221844 kb
Host smart-da129c4e-4e01-4a28-b1fc-53135b8ee804
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616023688 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.616023688
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.3336710764
Short name T415
Test name
Test status
Simulation time 430999734 ps
CPU time 2.32 seconds
Started Aug 01 05:27:18 PM PDT 24
Finished Aug 01 05:27:20 PM PDT 24
Peak memory 213756 kb
Host smart-082e145f-4ca9-4b79-a208-dc647aac58ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336710764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.3336710764
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_bit_bash.2248915155
Short name T449
Test name
Test status
Simulation time 51491969317 ps
CPU time 50.55 seconds
Started Aug 01 05:27:16 PM PDT 24
Finished Aug 01 05:28:07 PM PDT 24
Peak memory 205548 kb
Host smart-9a8c1bdd-2251-48d6-8772-a05f9ee337f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +num_test_csrs=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu
e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248915155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ
=rv_dm_jtag_dmi_csr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
rv_dm_jtag_dmi_csr_bit_bash.2248915155
Directory /workspace/9.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.1254383033
Short name T401
Test name
Test status
Simulation time 2282162240 ps
CPU time 6.38 seconds
Started Aug 01 05:27:18 PM PDT 24
Finished Aug 01 05:27:24 PM PDT 24
Peak memory 205624 kb
Host smart-ddedf86b-c5c2-4f25-b094-e06d465c6b2c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254383033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.1
254383033
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3991853194
Short name T457
Test name
Test status
Simulation time 259277103 ps
CPU time 0.88 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:16 PM PDT 24
Peak memory 205224 kb
Host smart-6e808083-37f8-4ac7-91c8-8053a561b582
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991853194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
991853194
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1017437307
Short name T85
Test name
Test status
Simulation time 551186076 ps
CPU time 6.69 seconds
Started Aug 01 05:27:19 PM PDT 24
Finished Aug 01 05:27:26 PM PDT 24
Peak memory 205484 kb
Host smart-dc93d88d-e6ce-47d4-b547-30d3606aedea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017437307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1017437307
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.1870827187
Short name T161
Test name
Test status
Simulation time 32697142916 ps
CPU time 25.33 seconds
Started Aug 01 05:27:18 PM PDT 24
Finished Aug 01 05:27:44 PM PDT 24
Peak memory 222168 kb
Host smart-8c7ec7d9-d5e1-4abf-a4c6-63704487766f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870827187 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.1870827187
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2293056983
Short name T314
Test name
Test status
Simulation time 83376533 ps
CPU time 3.9 seconds
Started Aug 01 05:27:15 PM PDT 24
Finished Aug 01 05:27:19 PM PDT 24
Peak memory 213848 kb
Host smart-185f62a2-939f-4945-9d96-13411a464de5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293056983 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2293056983
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.3895066016
Short name T431
Test name
Test status
Simulation time 830293067 ps
CPU time 10.73 seconds
Started Aug 01 05:27:17 PM PDT 24
Finished Aug 01 05:27:28 PM PDT 24
Peak memory 213680 kb
Host smart-617ccb09-ed25-46f7-b459-794850783956
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895066016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.3895066016
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2365227400
Short name T115
Test name
Test status
Simulation time 115992468 ps
CPU time 0.79 seconds
Started Aug 01 05:27:49 PM PDT 24
Finished Aug 01 05:27:50 PM PDT 24
Peak memory 205144 kb
Host smart-9b58f4f1-08f8-4dd0-8825-b4ac216c8e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365227400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2365227400
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.3843996634
Short name T170
Test name
Test status
Simulation time 16294973208 ps
CPU time 45.02 seconds
Started Aug 01 05:27:38 PM PDT 24
Finished Aug 01 05:28:24 PM PDT 24
Peak memory 213956 kb
Host smart-9300f421-b90e-4a5d-b698-0540f55099c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843996634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.3843996634
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3434987480
Short name T22
Test name
Test status
Simulation time 243201098 ps
CPU time 1.35 seconds
Started Aug 01 05:27:38 PM PDT 24
Finished Aug 01 05:27:39 PM PDT 24
Peak memory 205228 kb
Host smart-f110e071-d9c4-4fcb-90e8-a798a0fe8f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434987480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3434987480
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3445885445
Short name T187
Test name
Test status
Simulation time 910739386 ps
CPU time 1.66 seconds
Started Aug 01 05:27:40 PM PDT 24
Finished Aug 01 05:27:42 PM PDT 24
Peak memory 205152 kb
Host smart-bcd227b0-8287-4811-a8f3-7442077d71b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445885445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3445885445
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1858289895
Short name T293
Test name
Test status
Simulation time 2569393664 ps
CPU time 1.42 seconds
Started Aug 01 05:27:42 PM PDT 24
Finished Aug 01 05:27:44 PM PDT 24
Peak memory 205700 kb
Host smart-9d9a4665-bd37-4b4e-8caf-13eb242f14d1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1858289895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1858289895
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2120926795
Short name T260
Test name
Test status
Simulation time 1302154750 ps
CPU time 4.14 seconds
Started Aug 01 05:27:42 PM PDT 24
Finished Aug 01 05:27:46 PM PDT 24
Peak memory 205232 kb
Host smart-690702b8-e72c-466b-aae6-5040d96b6d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120926795 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2120926795
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1555121627
Short name T304
Test name
Test status
Simulation time 396808245 ps
CPU time 0.91 seconds
Started Aug 01 05:27:39 PM PDT 24
Finished Aug 01 05:27:40 PM PDT 24
Peak memory 205236 kb
Host smart-f1e068fc-5f22-4602-a4ad-e60e82863d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555121627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1555121627
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.3476234829
Short name T186
Test name
Test status
Simulation time 90372112 ps
CPU time 0.9 seconds
Started Aug 01 05:27:48 PM PDT 24
Finished Aug 01 05:27:50 PM PDT 24
Peak memory 205240 kb
Host smart-16fbdd93-de68-4f8f-80b5-183defa0ae4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476234829 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.3476234829
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3205549965
Short name T219
Test name
Test status
Simulation time 1331812012 ps
CPU time 4.11 seconds
Started Aug 01 05:27:50 PM PDT 24
Finished Aug 01 05:27:54 PM PDT 24
Peak memory 205116 kb
Host smart-320ba7e6-ab7e-4eb6-a7fb-e9566a50edbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205549965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3205549965
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.723323306
Short name T255
Test name
Test status
Simulation time 101389561 ps
CPU time 0.94 seconds
Started Aug 01 05:27:49 PM PDT 24
Finished Aug 01 05:27:50 PM PDT 24
Peak memory 205184 kb
Host smart-944593e0-02ad-4f79-aad7-6f99d3b91dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723323306 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.723323306
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.2838530655
Short name T27
Test name
Test status
Simulation time 232890274 ps
CPU time 1.32 seconds
Started Aug 01 05:27:40 PM PDT 24
Finished Aug 01 05:27:41 PM PDT 24
Peak memory 205232 kb
Host smart-9327ee62-eac7-4a98-b1ea-95152e0c04c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838530655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.2838530655
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.276210198
Short name T206
Test name
Test status
Simulation time 521719985 ps
CPU time 2.21 seconds
Started Aug 01 05:27:39 PM PDT 24
Finished Aug 01 05:27:41 PM PDT 24
Peak memory 205256 kb
Host smart-9e5be60d-e8fe-400f-95dd-f3740f233f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276210198 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.276210198
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.646597251
Short name T291
Test name
Test status
Simulation time 404463873 ps
CPU time 0.98 seconds
Started Aug 01 05:27:42 PM PDT 24
Finished Aug 01 05:27:43 PM PDT 24
Peak memory 204992 kb
Host smart-21da64a1-78f2-4318-a56d-62674594224f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646597251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.646597251
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2752090346
Short name T178
Test name
Test status
Simulation time 158305833 ps
CPU time 0.82 seconds
Started Aug 01 05:27:39 PM PDT 24
Finished Aug 01 05:27:40 PM PDT 24
Peak memory 213400 kb
Host smart-b487757e-3e60-41d9-bb28-4c5755fed5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752090346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2752090346
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_read_write_execute.2904355066
Short name T128
Test name
Test status
Simulation time 403071923 ps
CPU time 1.76 seconds
Started Aug 01 05:27:47 PM PDT 24
Finished Aug 01 05:27:49 PM PDT 24
Peak memory 205240 kb
Host smart-f4ad9e61-9685-4a7f-b4f1-5cad44584218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904355066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_read_write_execute.2904355066
Directory /workspace/0.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.2697970010
Short name T133
Test name
Test status
Simulation time 1952163175 ps
CPU time 2.06 seconds
Started Aug 01 05:27:38 PM PDT 24
Finished Aug 01 05:27:41 PM PDT 24
Peak memory 205444 kb
Host smart-1ae39f94-32b2-4587-bc97-c2649ab90e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697970010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.2697970010
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.1734584392
Short name T211
Test name
Test status
Simulation time 2997675621 ps
CPU time 1.62 seconds
Started Aug 01 05:27:37 PM PDT 24
Finished Aug 01 05:27:39 PM PDT 24
Peak memory 205356 kb
Host smart-660ac353-dc5a-4c48-a357-4ceb4b172fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734584392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.1734584392
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all.2528290282
Short name T73
Test name
Test status
Simulation time 4688954433 ps
CPU time 4.08 seconds
Started Aug 01 05:27:48 PM PDT 24
Finished Aug 01 05:27:52 PM PDT 24
Peak memory 213792 kb
Host smart-ddb43632-1fba-48ad-b9be-5b3067a833d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528290282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all.2528290282
Directory /workspace/0.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_stress_all_with_rand_reset.2228267658
Short name T49
Test name
Test status
Simulation time 73536086656 ps
CPU time 275.49 seconds
Started Aug 01 05:28:02 PM PDT 24
Finished Aug 01 05:32:38 PM PDT 24
Peak memory 225308 kb
Host smart-ce61502b-e61b-4193-a536-fdf97cc13d2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228267658 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.rv_dm_stress_all_with_rand_reset.2228267658
Directory /workspace/0.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3364998148
Short name T54
Test name
Test status
Simulation time 10267035477 ps
CPU time 7.48 seconds
Started Aug 01 05:27:38 PM PDT 24
Finished Aug 01 05:27:46 PM PDT 24
Peak memory 213700 kb
Host smart-27968f4f-9789-4590-97c2-cda4d5364445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364998148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3364998148
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_abstractcmd_status.3097401982
Short name T40
Test name
Test status
Simulation time 112793800 ps
CPU time 1 seconds
Started Aug 01 05:27:51 PM PDT 24
Finished Aug 01 05:27:52 PM PDT 24
Peak memory 205236 kb
Host smart-54f05c1a-ac00-410f-8884-0fb6f327c497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097401982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_abstractcmd_status_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_abstractcmd_status.3097401982
Directory /workspace/1.rv_dm_abstractcmd_status/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1794854937
Short name T225
Test name
Test status
Simulation time 129567190 ps
CPU time 0.75 seconds
Started Aug 01 05:27:50 PM PDT 24
Finished Aug 01 05:27:51 PM PDT 24
Peak memory 205008 kb
Host smart-fa7634ed-47da-4c03-aabf-a68ff5f144dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794854937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1794854937
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.1249379312
Short name T122
Test name
Test status
Simulation time 2275647125 ps
CPU time 6.55 seconds
Started Aug 01 05:27:50 PM PDT 24
Finished Aug 01 05:27:57 PM PDT 24
Peak memory 213828 kb
Host smart-c7f806ab-e54e-419f-8e8e-4ec2a9aab734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249379312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.1249379312
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.3905833808
Short name T127
Test name
Test status
Simulation time 3109979940 ps
CPU time 6.65 seconds
Started Aug 01 05:27:55 PM PDT 24
Finished Aug 01 05:28:01 PM PDT 24
Peak memory 213892 kb
Host smart-1aabc831-742a-42b7-bd57-391814e65f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905833808 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.3905833808
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2324319544
Short name T13
Test name
Test status
Simulation time 974351096 ps
CPU time 1.58 seconds
Started Aug 01 05:27:47 PM PDT 24
Finished Aug 01 05:27:48 PM PDT 24
Peak memory 205484 kb
Host smart-7d04b40b-cd53-479a-90c0-b35510121d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324319544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2324319544
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.764540946
Short name T8
Test name
Test status
Simulation time 141073322 ps
CPU time 0.89 seconds
Started Aug 01 05:27:48 PM PDT 24
Finished Aug 01 05:27:49 PM PDT 24
Peak memory 205212 kb
Host smart-0248b26b-0ade-4c39-8199-a5faf7387abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764540946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.764540946
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1398875500
Short name T30
Test name
Test status
Simulation time 861337477 ps
CPU time 2.84 seconds
Started Aug 01 05:27:48 PM PDT 24
Finished Aug 01 05:27:52 PM PDT 24
Peak memory 205188 kb
Host smart-ab0f3894-c89e-4c85-b390-9a5ec9250ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398875500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1398875500
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1890199287
Short name T189
Test name
Test status
Simulation time 203645785 ps
CPU time 0.84 seconds
Started Aug 01 05:27:51 PM PDT 24
Finished Aug 01 05:27:52 PM PDT 24
Peak memory 205240 kb
Host smart-21c690f1-97f1-43dc-bf3d-795e4fe92c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890199287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1890199287
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1334586452
Short name T259
Test name
Test status
Simulation time 153982840 ps
CPU time 0.78 seconds
Started Aug 01 05:28:03 PM PDT 24
Finished Aug 01 05:28:03 PM PDT 24
Peak memory 205228 kb
Host smart-7a58a2df-37c0-452a-8a15-d30bd0640c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334586452 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1334586452
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_debug_disabled.3232094124
Short name T273
Test name
Test status
Simulation time 69193056 ps
CPU time 0.94 seconds
Started Aug 01 05:27:48 PM PDT 24
Finished Aug 01 05:27:49 PM PDT 24
Peak memory 215604 kb
Host smart-f5cfdf2c-99f9-4f9d-acb2-1e93ef0e0492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232094124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_debug_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_debug_disabled.3232094124
Directory /workspace/1.rv_dm_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.2387481783
Short name T167
Test name
Test status
Simulation time 3437573349 ps
CPU time 2.02 seconds
Started Aug 01 05:27:49 PM PDT 24
Finished Aug 01 05:27:51 PM PDT 24
Peak memory 205760 kb
Host smart-81cbfc82-f463-4d02-9ead-f719b083dd64
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2387481783 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.2387481783
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2049061864
Short name T277
Test name
Test status
Simulation time 854190190 ps
CPU time 2.09 seconds
Started Aug 01 05:27:50 PM PDT 24
Finished Aug 01 05:27:52 PM PDT 24
Peak memory 205180 kb
Host smart-2acfe42d-92f9-4756-89bd-5fa206ed1696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049061864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2049061864
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.182057184
Short name T215
Test name
Test status
Simulation time 1072846474 ps
CPU time 3.57 seconds
Started Aug 01 05:27:51 PM PDT 24
Finished Aug 01 05:27:55 PM PDT 24
Peak memory 205256 kb
Host smart-2dfefff1-6214-4f8d-b967-9510a1aa3f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182057184 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.182057184
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3101754009
Short name T47
Test name
Test status
Simulation time 314991193 ps
CPU time 1.5 seconds
Started Aug 01 05:27:51 PM PDT 24
Finished Aug 01 05:27:53 PM PDT 24
Peak memory 205256 kb
Host smart-b724dcae-61ba-4297-870c-2fa07c688271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101754009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3101754009
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3652484165
Short name T248
Test name
Test status
Simulation time 368491538 ps
CPU time 1.4 seconds
Started Aug 01 05:27:48 PM PDT 24
Finished Aug 01 05:27:50 PM PDT 24
Peak memory 205140 kb
Host smart-f8543b98-bb82-4b26-9d09-f5a338248ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652484165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3652484165
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.2975264263
Short name T275
Test name
Test status
Simulation time 288983239 ps
CPU time 0.88 seconds
Started Aug 01 05:27:50 PM PDT 24
Finished Aug 01 05:27:51 PM PDT 24
Peak memory 205240 kb
Host smart-80d83482-acbc-4d4b-bb01-34b397e04ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975264263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.2975264263
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.2668713957
Short name T191
Test name
Test status
Simulation time 446592071 ps
CPU time 0.94 seconds
Started Aug 01 05:27:55 PM PDT 24
Finished Aug 01 05:27:56 PM PDT 24
Peak memory 205192 kb
Host smart-64a0c280-c3e4-43da-8114-d720221b8e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668713957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.2668713957
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1775778907
Short name T194
Test name
Test status
Simulation time 514377152 ps
CPU time 1.12 seconds
Started Aug 01 05:27:50 PM PDT 24
Finished Aug 01 05:27:51 PM PDT 24
Peak memory 205248 kb
Host smart-7ae56119-7cd5-499b-8adc-13b1c567249c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775778907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1775778907
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.1997765839
Short name T216
Test name
Test status
Simulation time 867342043 ps
CPU time 2 seconds
Started Aug 01 05:27:48 PM PDT 24
Finished Aug 01 05:27:50 PM PDT 24
Peak memory 205456 kb
Host smart-2a49875b-594f-4829-93ca-db4d29ebc187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997765839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.1997765839
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.3600041254
Short name T9
Test name
Test status
Simulation time 825177279 ps
CPU time 1.32 seconds
Started Aug 01 05:28:02 PM PDT 24
Finished Aug 01 05:28:04 PM PDT 24
Peak memory 213420 kb
Host smart-75a6de9d-275f-4873-a7a1-939c66e1cc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600041254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.3600041254
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_read_write_execute.880721566
Short name T272
Test name
Test status
Simulation time 427246250 ps
CPU time 0.88 seconds
Started Aug 01 05:27:48 PM PDT 24
Finished Aug 01 05:27:50 PM PDT 24
Peak memory 205228 kb
Host smart-03020841-2593-4d9b-ae14-3d518b31a111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880721566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_read_write_execute_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_read_write_execute.880721566
Directory /workspace/1.rv_dm_progbuf_read_write_execute/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1043262669
Short name T32
Test name
Test status
Simulation time 66136059 ps
CPU time 0.96 seconds
Started Aug 01 05:27:50 PM PDT 24
Finished Aug 01 05:27:51 PM PDT 24
Peak memory 213396 kb
Host smart-e358fdfb-14c6-4373-bfb2-ea4d9c14e3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043262669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1043262669
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.271962897
Short name T196
Test name
Test status
Simulation time 9801705460 ps
CPU time 3.26 seconds
Started Aug 01 05:27:48 PM PDT 24
Finished Aug 01 05:27:52 PM PDT 24
Peak memory 213928 kb
Host smart-f8bb7052-8014-4810-b8f9-735a57fdb451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271962897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.271962897
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2718653817
Short name T63
Test name
Test status
Simulation time 1287060639 ps
CPU time 2.34 seconds
Started Aug 01 05:27:51 PM PDT 24
Finished Aug 01 05:27:53 PM PDT 24
Peak memory 230352 kb
Host smart-837d3cc6-7a76-41d0-8231-97a5f70a5b16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718653817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2718653817
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.4085006253
Short name T173
Test name
Test status
Simulation time 963736562 ps
CPU time 1.8 seconds
Started Aug 01 05:27:48 PM PDT 24
Finished Aug 01 05:27:50 PM PDT 24
Peak memory 205436 kb
Host smart-9b087b94-9023-4721-b02e-e5795e28eb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085006253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.4085006253
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.2222818169
Short name T78
Test name
Test status
Simulation time 3169368185 ps
CPU time 5.72 seconds
Started Aug 01 05:28:02 PM PDT 24
Finished Aug 01 05:28:08 PM PDT 24
Peak memory 213708 kb
Host smart-a1e21991-b2f0-45a8-a323-cee2afa0e424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222818169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.2222818169
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.3384105666
Short name T290
Test name
Test status
Simulation time 49104556 ps
CPU time 0.71 seconds
Started Aug 01 05:28:10 PM PDT 24
Finished Aug 01 05:28:11 PM PDT 24
Peak memory 205228 kb
Host smart-ebc30850-1911-4f65-b26c-da8b4e3cd57e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384105666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.3384105666
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1139450324
Short name T257
Test name
Test status
Simulation time 17769438271 ps
CPU time 26.28 seconds
Started Aug 01 05:28:09 PM PDT 24
Finished Aug 01 05:28:35 PM PDT 24
Peak memory 213948 kb
Host smart-4edae01c-4b3a-4175-8870-cdb0b632292f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139450324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1139450324
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.2409698556
Short name T268
Test name
Test status
Simulation time 14805223456 ps
CPU time 45.93 seconds
Started Aug 01 05:28:13 PM PDT 24
Finished Aug 01 05:28:59 PM PDT 24
Peak memory 216112 kb
Host smart-062654b9-02cb-4a9e-b22d-70f29a091663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409698556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.2409698556
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.3327071677
Short name T274
Test name
Test status
Simulation time 1885694651 ps
CPU time 3.82 seconds
Started Aug 01 05:28:11 PM PDT 24
Finished Aug 01 05:28:15 PM PDT 24
Peak memory 205568 kb
Host smart-49d785e6-8e18-488b-94b0-21f11640a77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327071677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.3327071677
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.878426036
Short name T147
Test name
Test status
Simulation time 4288538394 ps
CPU time 3.07 seconds
Started Aug 01 05:28:12 PM PDT 24
Finished Aug 01 05:28:15 PM PDT 24
Peak memory 205572 kb
Host smart-70eca96a-28f1-4476-ac9b-38397ed219bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878426036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.878426036
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.632601629
Short name T231
Test name
Test status
Simulation time 124132778 ps
CPU time 0.83 seconds
Started Aug 01 05:28:13 PM PDT 24
Finished Aug 01 05:28:14 PM PDT 24
Peak memory 205224 kb
Host smart-81ad40fa-4ac3-4850-a9ab-b9d21274041a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632601629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.632601629
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3689455900
Short name T276
Test name
Test status
Simulation time 87702654150 ps
CPU time 65.08 seconds
Started Aug 01 05:28:11 PM PDT 24
Finished Aug 01 05:29:17 PM PDT 24
Peak memory 222044 kb
Host smart-f5cb6354-bb71-49a7-9130-9f7b5ce9f901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689455900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3689455900
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.4018225401
Short name T46
Test name
Test status
Simulation time 2608651790 ps
CPU time 8.48 seconds
Started Aug 01 05:28:12 PM PDT 24
Finished Aug 01 05:28:21 PM PDT 24
Peak memory 214764 kb
Host smart-f9c7fdd8-09c8-46bf-90ee-c212ae5b4602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018225401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.4018225401
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.198954272
Short name T285
Test name
Test status
Simulation time 16654575495 ps
CPU time 25.4 seconds
Started Aug 01 05:28:11 PM PDT 24
Finished Aug 01 05:28:37 PM PDT 24
Peak memory 213868 kb
Host smart-31e41ebf-0d72-4088-ba77-904aa8f6ae3f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=198954272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.198954272
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2826241425
Short name T296
Test name
Test status
Simulation time 1772683539 ps
CPU time 2.17 seconds
Started Aug 01 05:28:17 PM PDT 24
Finished Aug 01 05:28:19 PM PDT 24
Peak memory 205656 kb
Host smart-d7de0d1f-4b9f-41d9-98da-02312f7f1a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826241425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2826241425
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_stress_all.341360213
Short name T17
Test name
Test status
Simulation time 9276033532 ps
CPU time 9.82 seconds
Started Aug 01 05:28:12 PM PDT 24
Finished Aug 01 05:28:22 PM PDT 24
Peak memory 213724 kb
Host smart-a6beee44-9221-4e7f-af6f-9250594ce31b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341360213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_stress_all.341360213
Directory /workspace/11.rv_dm_stress_all/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3766199812
Short name T175
Test name
Test status
Simulation time 37157246 ps
CPU time 0.74 seconds
Started Aug 01 05:28:12 PM PDT 24
Finished Aug 01 05:28:13 PM PDT 24
Peak memory 205212 kb
Host smart-33e7391c-d4da-469b-a365-9996c5c55da1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766199812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3766199812
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.3748112981
Short name T177
Test name
Test status
Simulation time 2190348644 ps
CPU time 6.29 seconds
Started Aug 01 05:28:11 PM PDT 24
Finished Aug 01 05:28:18 PM PDT 24
Peak memory 205716 kb
Host smart-9f3f3d75-1ccf-42a4-9e69-5f4830cf6950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748112981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.3748112981
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.719891045
Short name T294
Test name
Test status
Simulation time 4471153603 ps
CPU time 14.7 seconds
Started Aug 01 05:28:10 PM PDT 24
Finished Aug 01 05:28:25 PM PDT 24
Peak memory 205752 kb
Host smart-d53fdeeb-b697-4076-97da-7b10ab55372b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=719891045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_t
l_access.719891045
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.1842055377
Short name T264
Test name
Test status
Simulation time 890346938 ps
CPU time 2.97 seconds
Started Aug 01 05:28:11 PM PDT 24
Finished Aug 01 05:28:14 PM PDT 24
Peak memory 213788 kb
Host smart-49c87597-5a7a-4b19-97bf-84c928480ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842055377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.1842055377
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.2367577703
Short name T140
Test name
Test status
Simulation time 11288787852 ps
CPU time 16.03 seconds
Started Aug 01 05:28:11 PM PDT 24
Finished Aug 01 05:28:27 PM PDT 24
Peak memory 205524 kb
Host smart-c9f70f12-3fe1-4d74-9958-a04303c19632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367577703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.2367577703
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3019099312
Short name T190
Test name
Test status
Simulation time 55620266 ps
CPU time 0.72 seconds
Started Aug 01 05:28:11 PM PDT 24
Finished Aug 01 05:28:12 PM PDT 24
Peak memory 205124 kb
Host smart-a5607921-75fc-4dd2-818e-2af48e9cd650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019099312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3019099312
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.1205153714
Short name T242
Test name
Test status
Simulation time 185398376326 ps
CPU time 520.38 seconds
Started Aug 01 05:28:13 PM PDT 24
Finished Aug 01 05:36:53 PM PDT 24
Peak memory 230276 kb
Host smart-8b033a6b-77ed-4407-a9a7-8c7cd71c497b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205153714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.1205153714
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1982076291
Short name T149
Test name
Test status
Simulation time 3111896839 ps
CPU time 4.03 seconds
Started Aug 01 05:28:13 PM PDT 24
Finished Aug 01 05:28:17 PM PDT 24
Peak memory 213848 kb
Host smart-b9c3824a-0a63-4d19-9737-f96b11375def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982076291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1982076291
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.620351602
Short name T270
Test name
Test status
Simulation time 2114527574 ps
CPU time 6.59 seconds
Started Aug 01 05:28:11 PM PDT 24
Finished Aug 01 05:28:18 PM PDT 24
Peak memory 213824 kb
Host smart-4e4c10a2-f918-4e3a-af5d-a8db56ced922
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=620351602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.620351602
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1622137790
Short name T174
Test name
Test status
Simulation time 4375599547 ps
CPU time 7.13 seconds
Started Aug 01 05:28:12 PM PDT 24
Finished Aug 01 05:28:19 PM PDT 24
Peak memory 205748 kb
Host smart-27f7c1d7-5722-42e0-8def-17c118cc48d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622137790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1622137790
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.130789422
Short name T208
Test name
Test status
Simulation time 1880373197 ps
CPU time 5.88 seconds
Started Aug 01 05:28:14 PM PDT 24
Finished Aug 01 05:28:20 PM PDT 24
Peak memory 205464 kb
Host smart-3c9e2aa5-cdde-440b-9d95-3e0b785ee061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130789422 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.130789422
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2559745759
Short name T185
Test name
Test status
Simulation time 89008707 ps
CPU time 0.93 seconds
Started Aug 01 05:28:14 PM PDT 24
Finished Aug 01 05:28:15 PM PDT 24
Peak memory 205244 kb
Host smart-c3a47eb1-db43-4304-9475-8b49fdde91ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559745759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2559745759
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.3819405941
Short name T24
Test name
Test status
Simulation time 60337602003 ps
CPU time 174.97 seconds
Started Aug 01 05:28:13 PM PDT 24
Finished Aug 01 05:31:09 PM PDT 24
Peak memory 213796 kb
Host smart-f4613305-d162-40c5-907e-8a34191b981a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819405941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.3819405941
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1943954055
Short name T297
Test name
Test status
Simulation time 5419936619 ps
CPU time 8.62 seconds
Started Aug 01 05:28:14 PM PDT 24
Finished Aug 01 05:28:23 PM PDT 24
Peak memory 213860 kb
Host smart-7a3543d9-b755-4470-b048-4d6b153c08f9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943954055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1943954055
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3485037376
Short name T223
Test name
Test status
Simulation time 1087821779 ps
CPU time 1.1 seconds
Started Aug 01 05:28:13 PM PDT 24
Finished Aug 01 05:28:14 PM PDT 24
Peak memory 205528 kb
Host smart-9a3baa78-b41c-4e74-b844-db7c0ab82305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485037376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3485037376
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.4200386641
Short name T121
Test name
Test status
Simulation time 4335345895 ps
CPU time 3.32 seconds
Started Aug 01 05:28:12 PM PDT 24
Finished Aug 01 05:28:16 PM PDT 24
Peak memory 213828 kb
Host smart-8e5ad3b8-28ff-4931-9cdc-850964ec8158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200386641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.4200386641
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.4086109871
Short name T77
Test name
Test status
Simulation time 73425172 ps
CPU time 0.71 seconds
Started Aug 01 05:28:12 PM PDT 24
Finished Aug 01 05:28:13 PM PDT 24
Peak memory 205180 kb
Host smart-e4023b7e-1609-45ba-807b-dc2910edfb13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086109871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.4086109871
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1581337886
Short name T16
Test name
Test status
Simulation time 5789462874 ps
CPU time 15.22 seconds
Started Aug 01 05:28:14 PM PDT 24
Finished Aug 01 05:28:30 PM PDT 24
Peak memory 205684 kb
Host smart-952169f1-abea-4cfb-8c06-45cd7075e86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581337886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1581337886
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2110891930
Short name T300
Test name
Test status
Simulation time 1461182542 ps
CPU time 4.87 seconds
Started Aug 01 05:28:16 PM PDT 24
Finished Aug 01 05:28:21 PM PDT 24
Peak memory 205568 kb
Host smart-d09a19aa-fe55-4814-8500-4247950515e6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2110891930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2110891930
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.1220173583
Short name T200
Test name
Test status
Simulation time 3662877461 ps
CPU time 11.63 seconds
Started Aug 01 05:28:14 PM PDT 24
Finished Aug 01 05:28:26 PM PDT 24
Peak memory 213888 kb
Host smart-d1da38fa-9c1e-43c7-bda9-1d122a994606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220173583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.1220173583
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.4242933692
Short name T280
Test name
Test status
Simulation time 1771260490 ps
CPU time 5.69 seconds
Started Aug 01 05:28:16 PM PDT 24
Finished Aug 01 05:28:22 PM PDT 24
Peak memory 205416 kb
Host smart-1c793f2a-9112-43e3-9c54-a60274991166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242933692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.4242933692
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.1267037377
Short name T239
Test name
Test status
Simulation time 75951475 ps
CPU time 0.71 seconds
Started Aug 01 05:28:13 PM PDT 24
Finished Aug 01 05:28:14 PM PDT 24
Peak memory 205220 kb
Host smart-3daf3d58-3e14-4d63-8dfa-5618d9cb934d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267037377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.1267037377
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.100558835
Short name T188
Test name
Test status
Simulation time 5210105706 ps
CPU time 4.04 seconds
Started Aug 01 05:28:18 PM PDT 24
Finished Aug 01 05:28:22 PM PDT 24
Peak memory 213920 kb
Host smart-32ff07c4-68e2-44fb-a459-aba1eaef06a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100558835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.100558835
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.674822258
Short name T229
Test name
Test status
Simulation time 7381370966 ps
CPU time 9.96 seconds
Started Aug 01 05:28:17 PM PDT 24
Finished Aug 01 05:28:27 PM PDT 24
Peak memory 213920 kb
Host smart-e419e57e-2f8a-4290-b590-64a6622332fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674822258 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.674822258
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2666371039
Short name T162
Test name
Test status
Simulation time 8668203161 ps
CPU time 12.43 seconds
Started Aug 01 05:28:15 PM PDT 24
Finished Aug 01 05:28:28 PM PDT 24
Peak memory 213804 kb
Host smart-3cbafedc-c6e7-4d98-88d2-124b0e6170e4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2666371039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2666371039
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.4251695972
Short name T179
Test name
Test status
Simulation time 2383520963 ps
CPU time 3 seconds
Started Aug 01 05:28:13 PM PDT 24
Finished Aug 01 05:28:16 PM PDT 24
Peak memory 205716 kb
Host smart-fd5a6424-50e1-4c2e-961d-d6398d4e2fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251695972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.4251695972
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2313845897
Short name T212
Test name
Test status
Simulation time 102081937 ps
CPU time 0.73 seconds
Started Aug 01 05:28:15 PM PDT 24
Finished Aug 01 05:28:16 PM PDT 24
Peak memory 205280 kb
Host smart-3db0a8f0-4897-41d6-b103-8cc8ec592e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313845897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2313845897
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.2634715054
Short name T254
Test name
Test status
Simulation time 15072236969 ps
CPU time 13.89 seconds
Started Aug 01 05:28:12 PM PDT 24
Finished Aug 01 05:28:26 PM PDT 24
Peak memory 216840 kb
Host smart-00b45350-bca8-4634-ade7-83f0fcc1c5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634715054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.2634715054
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.919297652
Short name T67
Test name
Test status
Simulation time 2426871462 ps
CPU time 6.9 seconds
Started Aug 01 05:28:14 PM PDT 24
Finished Aug 01 05:28:21 PM PDT 24
Peak memory 213932 kb
Host smart-5573ce75-78d2-4edb-b8bd-d9d61e1fdd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919297652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.919297652
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.2332450505
Short name T207
Test name
Test status
Simulation time 2425581456 ps
CPU time 4.61 seconds
Started Aug 01 05:28:14 PM PDT 24
Finished Aug 01 05:28:19 PM PDT 24
Peak memory 213912 kb
Host smart-a2de09ed-2339-4abb-a739-5f282100da12
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332450505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.2332450505
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3259882024
Short name T168
Test name
Test status
Simulation time 893425980 ps
CPU time 3.15 seconds
Started Aug 01 05:28:18 PM PDT 24
Finished Aug 01 05:28:21 PM PDT 24
Peak memory 205576 kb
Host smart-fb26aed7-8f50-4355-9acd-a4b6cd87270d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259882024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3259882024
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.60467988
Short name T20
Test name
Test status
Simulation time 5466765195 ps
CPU time 4.71 seconds
Started Aug 01 05:28:15 PM PDT 24
Finished Aug 01 05:28:20 PM PDT 24
Peak memory 213764 kb
Host smart-b32575f7-539d-412a-9815-801944664aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60467988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.60467988
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.2340514912
Short name T199
Test name
Test status
Simulation time 60175178 ps
CPU time 0.77 seconds
Started Aug 01 05:28:21 PM PDT 24
Finished Aug 01 05:28:22 PM PDT 24
Peak memory 205252 kb
Host smart-fa19daaa-7b9f-4d1b-9c97-cd9b9f2c11d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340514912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.2340514912
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2217298282
Short name T203
Test name
Test status
Simulation time 28854963037 ps
CPU time 80.32 seconds
Started Aug 01 05:28:22 PM PDT 24
Finished Aug 01 05:29:43 PM PDT 24
Peak memory 213928 kb
Host smart-6386fb28-529d-4614-9a76-0573068e8735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217298282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2217298282
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1149351205
Short name T249
Test name
Test status
Simulation time 1025856496 ps
CPU time 3.44 seconds
Started Aug 01 05:28:26 PM PDT 24
Finished Aug 01 05:28:29 PM PDT 24
Peak memory 213716 kb
Host smart-2a0a4bb9-bb64-46ae-a372-1de8102e6409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149351205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1149351205
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.4219499530
Short name T148
Test name
Test status
Simulation time 5830288282 ps
CPU time 9.44 seconds
Started Aug 01 05:28:15 PM PDT 24
Finished Aug 01 05:28:25 PM PDT 24
Peak memory 205728 kb
Host smart-cebcc3d0-246c-4fe9-80ca-d235d8b7d673
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4219499530 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.4219499530
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3387035182
Short name T295
Test name
Test status
Simulation time 4849080848 ps
CPU time 5.29 seconds
Started Aug 01 05:28:14 PM PDT 24
Finished Aug 01 05:28:19 PM PDT 24
Peak memory 213852 kb
Host smart-30a01a1d-cd2d-40bc-b5c5-028ba4f9d80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387035182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3387035182
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.1374084414
Short name T299
Test name
Test status
Simulation time 2531177962 ps
CPU time 2.62 seconds
Started Aug 01 05:28:29 PM PDT 24
Finished Aug 01 05:28:32 PM PDT 24
Peak memory 213588 kb
Host smart-18b6e961-e424-4d44-8d1d-89e015eb4c80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374084414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.1374084414
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2776838641
Short name T237
Test name
Test status
Simulation time 42495903 ps
CPU time 0.75 seconds
Started Aug 01 05:28:28 PM PDT 24
Finished Aug 01 05:28:29 PM PDT 24
Peak memory 205228 kb
Host smart-c804e929-cffa-4c8c-80aa-90c5496b138e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776838641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2776838641
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3553604237
Short name T271
Test name
Test status
Simulation time 2554887001 ps
CPU time 3.33 seconds
Started Aug 01 05:28:22 PM PDT 24
Finished Aug 01 05:28:26 PM PDT 24
Peak memory 213908 kb
Host smart-79b0c51c-c47d-4c1c-b5c4-6c2b40656893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553604237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3553604237
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.349069576
Short name T253
Test name
Test status
Simulation time 4035507701 ps
CPU time 3.83 seconds
Started Aug 01 05:28:27 PM PDT 24
Finished Aug 01 05:28:31 PM PDT 24
Peak memory 222000 kb
Host smart-9dc0ef95-9440-430a-be4c-a13171064404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349069576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.349069576
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1244069230
Short name T228
Test name
Test status
Simulation time 9276756268 ps
CPU time 8.28 seconds
Started Aug 01 05:28:22 PM PDT 24
Finished Aug 01 05:28:30 PM PDT 24
Peak memory 213848 kb
Host smart-aace431b-9582-4a2b-8bd4-d36a866189ed
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244069230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1244069230
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2149843939
Short name T265
Test name
Test status
Simulation time 1670488936 ps
CPU time 5.39 seconds
Started Aug 01 05:28:23 PM PDT 24
Finished Aug 01 05:28:28 PM PDT 24
Peak memory 205584 kb
Host smart-4239d078-9865-4c16-838d-d734e9227dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149843939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2149843939
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.2457209714
Short name T289
Test name
Test status
Simulation time 16733023711 ps
CPU time 8.89 seconds
Started Aug 01 05:28:23 PM PDT 24
Finished Aug 01 05:28:32 PM PDT 24
Peak memory 213756 kb
Host smart-01af6e34-ad81-4485-b068-55e33850887c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457209714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.2457209714
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2533399648
Short name T278
Test name
Test status
Simulation time 100205538 ps
CPU time 0.79 seconds
Started Aug 01 05:27:52 PM PDT 24
Finished Aug 01 05:27:53 PM PDT 24
Peak memory 205340 kb
Host smart-899f7887-c390-4577-aeae-cb4d74cd24da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533399648 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2533399648
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.4254981364
Short name T182
Test name
Test status
Simulation time 38006544059 ps
CPU time 105.69 seconds
Started Aug 01 05:28:02 PM PDT 24
Finished Aug 01 05:29:48 PM PDT 24
Peak memory 213880 kb
Host smart-f7e42e33-0a62-4cfc-80e3-80c981ff1f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254981364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.4254981364
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3387960002
Short name T287
Test name
Test status
Simulation time 2176622732 ps
CPU time 3.09 seconds
Started Aug 01 05:27:50 PM PDT 24
Finished Aug 01 05:27:53 PM PDT 24
Peak memory 213648 kb
Host smart-ef0f4108-ad39-4cb3-b750-a29c0cc85db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387960002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3387960002
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.466006163
Short name T205
Test name
Test status
Simulation time 1891216103 ps
CPU time 7.08 seconds
Started Aug 01 05:27:50 PM PDT 24
Finished Aug 01 05:27:58 PM PDT 24
Peak memory 213844 kb
Host smart-c711c70b-b956-4aad-a1d2-f0e56a55b35f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466006163 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.466006163
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_halt_resume_whereto.1366007236
Short name T38
Test name
Test status
Simulation time 717397724 ps
CPU time 0.9 seconds
Started Aug 01 05:27:50 PM PDT 24
Finished Aug 01 05:27:51 PM PDT 24
Peak memory 205292 kb
Host smart-0d7ce69d-eda1-4e4c-b5b1-039eaebfa204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366007236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_halt_resume_whereto.1366007236
Directory /workspace/2.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.3329805876
Short name T269
Test name
Test status
Simulation time 208724123 ps
CPU time 1.19 seconds
Started Aug 01 05:27:53 PM PDT 24
Finished Aug 01 05:27:55 PM PDT 24
Peak memory 205212 kb
Host smart-801891ea-969d-4e12-bf2f-9cfd03d6860c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329805876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.3329805876
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1628469277
Short name T256
Test name
Test status
Simulation time 8731203974 ps
CPU time 14.29 seconds
Started Aug 01 05:27:51 PM PDT 24
Finished Aug 01 05:28:05 PM PDT 24
Peak memory 205632 kb
Host smart-c82cf0b8-853c-4119-aa5f-7a58963087b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628469277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1628469277
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1966021124
Short name T44
Test name
Test status
Simulation time 904358702 ps
CPU time 1.63 seconds
Started Aug 01 05:28:02 PM PDT 24
Finished Aug 01 05:28:04 PM PDT 24
Peak memory 229852 kb
Host smart-2fc5f795-274a-4015-a08e-3352bae09875
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966021124 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1966021124
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.2671238877
Short name T7
Test name
Test status
Simulation time 4388882583 ps
CPU time 12.9 seconds
Started Aug 01 05:27:53 PM PDT 24
Finished Aug 01 05:28:07 PM PDT 24
Peak memory 213776 kb
Host smart-a06e293e-07aa-4e79-84f0-d41fa399134d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671238877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.2671238877
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all_with_rand_reset.2250588529
Short name T39
Test name
Test status
Simulation time 102983195365 ps
CPU time 789.5 seconds
Started Aug 01 05:27:55 PM PDT 24
Finished Aug 01 05:41:05 PM PDT 24
Peak memory 231824 kb
Host smart-47f28d6d-4ae5-4d45-9b86-c80d63dd515c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250588529 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all_with_rand_reset.2250588529
Directory /workspace/2.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.1113678549
Short name T214
Test name
Test status
Simulation time 76875035 ps
CPU time 0.78 seconds
Started Aug 01 05:28:24 PM PDT 24
Finished Aug 01 05:28:24 PM PDT 24
Peak memory 205284 kb
Host smart-9d851c88-87d7-4855-9b47-f9578c083f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113678549 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.1113678549
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.4140140833
Short name T235
Test name
Test status
Simulation time 2368921803 ps
CPU time 2.87 seconds
Started Aug 01 05:28:23 PM PDT 24
Finished Aug 01 05:28:26 PM PDT 24
Peak memory 213800 kb
Host smart-c253d126-90e8-4d96-abea-3bd76608f5b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140140833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.4140140833
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3041131520
Short name T3
Test name
Test status
Simulation time 62111362 ps
CPU time 0.82 seconds
Started Aug 01 05:28:25 PM PDT 24
Finished Aug 01 05:28:26 PM PDT 24
Peak memory 205160 kb
Host smart-8cf3027d-5ab7-4152-b934-2bd3d8d3a18b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041131520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3041131520
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_stress_all.1795324765
Short name T141
Test name
Test status
Simulation time 3428543776 ps
CPU time 10.32 seconds
Started Aug 01 05:28:29 PM PDT 24
Finished Aug 01 05:28:40 PM PDT 24
Peak memory 213612 kb
Host smart-b360520b-519f-4e24-a337-9ab3f07a2b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795324765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_stress_all.1795324765
Directory /workspace/21.rv_dm_stress_all/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3614690291
Short name T197
Test name
Test status
Simulation time 143827200 ps
CPU time 0.75 seconds
Started Aug 01 05:28:31 PM PDT 24
Finished Aug 01 05:28:32 PM PDT 24
Peak memory 205308 kb
Host smart-f5891c66-3205-411e-9071-627abc68407f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614690291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3614690291
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.2130491657
Short name T142
Test name
Test status
Simulation time 3134100355 ps
CPU time 3.4 seconds
Started Aug 01 05:28:23 PM PDT 24
Finished Aug 01 05:28:27 PM PDT 24
Peak memory 213696 kb
Host smart-18d6dbf5-52cd-4c8e-835f-d88785406237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130491657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2130491657
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3734617323
Short name T166
Test name
Test status
Simulation time 140498523 ps
CPU time 0.94 seconds
Started Aug 01 05:28:23 PM PDT 24
Finished Aug 01 05:28:24 PM PDT 24
Peak memory 205164 kb
Host smart-e0ddb843-0712-4825-91d1-31072f2ede81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734617323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3734617323
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.198865629
Short name T251
Test name
Test status
Simulation time 1834813314 ps
CPU time 2.09 seconds
Started Aug 01 05:28:24 PM PDT 24
Finished Aug 01 05:28:27 PM PDT 24
Peak memory 205324 kb
Host smart-3682965d-6932-423e-b05d-cc7e5c1211df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198865629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.198865629
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3415062199
Short name T202
Test name
Test status
Simulation time 82701538 ps
CPU time 0.72 seconds
Started Aug 01 05:28:29 PM PDT 24
Finished Aug 01 05:28:29 PM PDT 24
Peak memory 205256 kb
Host smart-5acbb17d-dfee-49e7-af9d-36452c0bf428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415062199 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3415062199
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_stress_all.2519417059
Short name T35
Test name
Test status
Simulation time 4015280544 ps
CPU time 7.07 seconds
Started Aug 01 05:28:23 PM PDT 24
Finished Aug 01 05:28:30 PM PDT 24
Peak memory 205612 kb
Host smart-561e4dff-ced9-4c38-af36-fc3100cb5e5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519417059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_stress_all.2519417059
Directory /workspace/24.rv_dm_stress_all/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3996398513
Short name T192
Test name
Test status
Simulation time 91461609 ps
CPU time 0.92 seconds
Started Aug 01 05:28:27 PM PDT 24
Finished Aug 01 05:28:28 PM PDT 24
Peak memory 205204 kb
Host smart-3b615011-6769-400f-a5b3-82ab8b44805d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996398513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3996398513
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_stress_all.2709545954
Short name T232
Test name
Test status
Simulation time 6190749498 ps
CPU time 10.46 seconds
Started Aug 01 05:28:28 PM PDT 24
Finished Aug 01 05:28:39 PM PDT 24
Peak memory 213668 kb
Host smart-4b61029b-9c76-4465-93cc-9f3b5270c98c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709545954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_stress_all.2709545954
Directory /workspace/25.rv_dm_stress_all/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2243947571
Short name T184
Test name
Test status
Simulation time 64060052 ps
CPU time 0.76 seconds
Started Aug 01 05:28:27 PM PDT 24
Finished Aug 01 05:28:28 PM PDT 24
Peak memory 205236 kb
Host smart-606a8aa1-8915-40a7-859c-0d7137eb7ff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243947571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2243947571
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_stress_all.3954370721
Short name T134
Test name
Test status
Simulation time 8707589148 ps
CPU time 24.6 seconds
Started Aug 01 05:28:27 PM PDT 24
Finished Aug 01 05:28:52 PM PDT 24
Peak memory 205484 kb
Host smart-fb1398a2-f01e-4e68-83fb-ae5b10dbb1d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954370721 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_stress_all.3954370721
Directory /workspace/26.rv_dm_stress_all/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1463093686
Short name T180
Test name
Test status
Simulation time 39167190 ps
CPU time 0.73 seconds
Started Aug 01 05:28:26 PM PDT 24
Finished Aug 01 05:28:27 PM PDT 24
Peak memory 205236 kb
Host smart-bc481b28-b142-4722-b80a-12a23991a2f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463093686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1463093686
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_stress_all.984822533
Short name T72
Test name
Test status
Simulation time 1316418896 ps
CPU time 4.44 seconds
Started Aug 01 05:28:29 PM PDT 24
Finished Aug 01 05:28:33 PM PDT 24
Peak memory 213616 kb
Host smart-f7691770-b94c-4cfc-93c8-0ec153e66c3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984822533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_stress_all.984822533
Directory /workspace/27.rv_dm_stress_all/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.3859273945
Short name T244
Test name
Test status
Simulation time 202533527 ps
CPU time 0.73 seconds
Started Aug 01 05:28:24 PM PDT 24
Finished Aug 01 05:28:25 PM PDT 24
Peak memory 205096 kb
Host smart-94d53ddb-41c3-419e-8c14-b9de1be31dac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859273945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.3859273945
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1724353686
Short name T14
Test name
Test status
Simulation time 1809015777 ps
CPU time 3.99 seconds
Started Aug 01 05:28:23 PM PDT 24
Finished Aug 01 05:28:27 PM PDT 24
Peak memory 213568 kb
Host smart-aad6cc8f-3e4b-430a-beba-640992532d41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724353686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1724353686
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.2673881003
Short name T284
Test name
Test status
Simulation time 76253696 ps
CPU time 0.73 seconds
Started Aug 01 05:28:31 PM PDT 24
Finished Aug 01 05:28:32 PM PDT 24
Peak memory 205220 kb
Host smart-d2e3f497-ce47-4e87-a8bc-3e9cb85d16bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673881003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.2673881003
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.434177222
Short name T213
Test name
Test status
Simulation time 2333806025 ps
CPU time 7.6 seconds
Started Aug 01 05:28:28 PM PDT 24
Finished Aug 01 05:28:36 PM PDT 24
Peak memory 205532 kb
Host smart-628d4bc6-ce2e-4f6f-a8c4-daa7002b11b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434177222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.434177222
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.4038282497
Short name T233
Test name
Test status
Simulation time 96203693 ps
CPU time 0.81 seconds
Started Aug 01 05:27:58 PM PDT 24
Finished Aug 01 05:27:58 PM PDT 24
Peak memory 205476 kb
Host smart-ff97c9fa-01ce-423b-a854-28419cd30fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038282497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.4038282497
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.843360973
Short name T230
Test name
Test status
Simulation time 1641834746 ps
CPU time 2.32 seconds
Started Aug 01 05:27:50 PM PDT 24
Finished Aug 01 05:27:53 PM PDT 24
Peak memory 213856 kb
Host smart-058278e5-376e-4c34-b8c5-8de7d7c8c371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843360973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.843360973
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.466668364
Short name T279
Test name
Test status
Simulation time 6440317712 ps
CPU time 10.87 seconds
Started Aug 01 05:27:51 PM PDT 24
Finished Aug 01 05:28:03 PM PDT 24
Peak memory 213924 kb
Host smart-2a8d75fb-9a68-4310-be38-506fc865eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466668364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.466668364
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.509292345
Short name T164
Test name
Test status
Simulation time 3941092795 ps
CPU time 6.38 seconds
Started Aug 01 05:27:51 PM PDT 24
Finished Aug 01 05:27:58 PM PDT 24
Peak memory 205612 kb
Host smart-a41a93e7-55fc-4c21-83df-2e8c49f22d5d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=509292345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.509292345
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_halt_resume_whereto.2230685819
Short name T198
Test name
Test status
Simulation time 348841331 ps
CPU time 1.43 seconds
Started Aug 01 05:27:54 PM PDT 24
Finished Aug 01 05:27:55 PM PDT 24
Peak memory 205236 kb
Host smart-de84e1cd-70d7-4767-9c24-197ea9f088ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230685819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_halt_resume_whereto.2230685819
Directory /workspace/3.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.2082630024
Short name T288
Test name
Test status
Simulation time 208392824 ps
CPU time 0.94 seconds
Started Aug 01 05:27:54 PM PDT 24
Finished Aug 01 05:27:55 PM PDT 24
Peak memory 205160 kb
Host smart-86b6c1d3-2f5c-477d-b40b-6962d1b86b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082630024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.2082630024
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1880893178
Short name T266
Test name
Test status
Simulation time 1843855359 ps
CPU time 5.52 seconds
Started Aug 01 05:28:02 PM PDT 24
Finished Aug 01 05:28:08 PM PDT 24
Peak memory 205524 kb
Host smart-e446f7c1-0f68-42f5-bd4b-a3d6a45e5219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880893178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1880893178
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3195946835
Short name T62
Test name
Test status
Simulation time 1019730076 ps
CPU time 1.2 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:28:01 PM PDT 24
Peak memory 236984 kb
Host smart-adeca06e-5a60-4b02-b4aa-edea47b88751
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195946835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3195946835
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all_with_rand_reset.141649027
Short name T74
Test name
Test status
Simulation time 28695756753 ps
CPU time 114.79 seconds
Started Aug 01 05:27:59 PM PDT 24
Finished Aug 01 05:29:54 PM PDT 24
Peak memory 222076 kb
Host smart-54dac473-6ccb-4983-8737-0b9dc5c6a2cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141649027 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all_with_rand_reset.141649027
Directory /workspace/3.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2936837451
Short name T281
Test name
Test status
Simulation time 82557147 ps
CPU time 0.71 seconds
Started Aug 01 05:28:21 PM PDT 24
Finished Aug 01 05:28:22 PM PDT 24
Peak memory 205232 kb
Host smart-0acc00b0-5f05-40c0-99b7-51e56a8f29a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936837451 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2936837451
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.3632372515
Short name T267
Test name
Test status
Simulation time 6121378755 ps
CPU time 10.52 seconds
Started Aug 01 05:28:22 PM PDT 24
Finished Aug 01 05:28:33 PM PDT 24
Peak memory 213724 kb
Host smart-5f6c7db6-4030-488c-a847-1afbbf1a758c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632372515 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.3632372515
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2352957436
Short name T262
Test name
Test status
Simulation time 29228642 ps
CPU time 0.75 seconds
Started Aug 01 05:28:32 PM PDT 24
Finished Aug 01 05:28:33 PM PDT 24
Peak memory 205312 kb
Host smart-232d37ad-c540-4d66-b6e2-2aef09dadabe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352957436 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2352957436
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_stress_all.1716313137
Short name T12
Test name
Test status
Simulation time 7363591932 ps
CPU time 3.46 seconds
Started Aug 01 05:28:26 PM PDT 24
Finished Aug 01 05:28:30 PM PDT 24
Peak memory 213732 kb
Host smart-cc399952-0655-4520-87c9-d85d07886dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716313137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_stress_all.1716313137
Directory /workspace/31.rv_dm_stress_all/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.1366790159
Short name T298
Test name
Test status
Simulation time 149694419 ps
CPU time 0.89 seconds
Started Aug 01 05:28:28 PM PDT 24
Finished Aug 01 05:28:29 PM PDT 24
Peak memory 205128 kb
Host smart-948082d7-f4ee-49a6-b345-c967e97ea33f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366790159 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.1366790159
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_stress_all.174973336
Short name T217
Test name
Test status
Simulation time 3137505130 ps
CPU time 2.98 seconds
Started Aug 01 05:28:24 PM PDT 24
Finished Aug 01 05:28:27 PM PDT 24
Peak memory 213740 kb
Host smart-35da2c54-b06f-4bae-9b26-90492b6b1c3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174973336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_stress_all.174973336
Directory /workspace/32.rv_dm_stress_all/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.993102597
Short name T226
Test name
Test status
Simulation time 36446570 ps
CPU time 0.76 seconds
Started Aug 01 05:28:25 PM PDT 24
Finished Aug 01 05:28:26 PM PDT 24
Peak memory 205200 kb
Host smart-d34a7153-0a4f-4014-8b8b-a66dcba149ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993102597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.993102597
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_stress_all.3699911020
Short name T238
Test name
Test status
Simulation time 3237782305 ps
CPU time 9.26 seconds
Started Aug 01 05:28:26 PM PDT 24
Finished Aug 01 05:28:35 PM PDT 24
Peak memory 213832 kb
Host smart-3310a4cd-56b4-46e7-8d27-ddad4e532675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699911020 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_stress_all.3699911020
Directory /workspace/33.rv_dm_stress_all/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3215856541
Short name T261
Test name
Test status
Simulation time 85448696 ps
CPU time 0.76 seconds
Started Aug 01 05:28:28 PM PDT 24
Finished Aug 01 05:28:29 PM PDT 24
Peak memory 205240 kb
Host smart-2c84f1cb-eb77-4097-ad1c-b896fee00b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215856541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3215856541
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.3825844135
Short name T138
Test name
Test status
Simulation time 3897636853 ps
CPU time 11.79 seconds
Started Aug 01 05:28:30 PM PDT 24
Finished Aug 01 05:28:41 PM PDT 24
Peak memory 205588 kb
Host smart-badf67d3-8bb3-432e-8d83-0f7f5f488151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825844135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.3825844135
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2633906566
Short name T165
Test name
Test status
Simulation time 101573612 ps
CPU time 0.71 seconds
Started Aug 01 05:28:24 PM PDT 24
Finished Aug 01 05:28:24 PM PDT 24
Peak memory 205124 kb
Host smart-7ab0cfcb-5853-4afb-9740-9e538aa1f7dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633906566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2633906566
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_stress_all.2973272524
Short name T193
Test name
Test status
Simulation time 8199546796 ps
CPU time 11.9 seconds
Started Aug 01 05:28:25 PM PDT 24
Finished Aug 01 05:28:37 PM PDT 24
Peak memory 213760 kb
Host smart-b2d6e16d-59aa-4f75-b4f1-6e7ee9ad8508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973272524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_stress_all.2973272524
Directory /workspace/35.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3953679516
Short name T282
Test name
Test status
Simulation time 41880630 ps
CPU time 0.71 seconds
Started Aug 01 05:28:31 PM PDT 24
Finished Aug 01 05:28:32 PM PDT 24
Peak memory 205216 kb
Host smart-10f5e9ac-c581-41ca-9511-a33d4cf1e3bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953679516 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3953679516
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3325790192
Short name T241
Test name
Test status
Simulation time 159747287 ps
CPU time 0.99 seconds
Started Aug 01 05:28:26 PM PDT 24
Finished Aug 01 05:28:27 PM PDT 24
Peak memory 205128 kb
Host smart-35f0c4a6-2444-4fef-9850-b28240d202a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325790192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3325790192
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_stress_all.3593992851
Short name T201
Test name
Test status
Simulation time 2835840497 ps
CPU time 2.83 seconds
Started Aug 01 05:28:31 PM PDT 24
Finished Aug 01 05:28:34 PM PDT 24
Peak memory 205548 kb
Host smart-0b7783f5-18ea-4b9b-b38f-0b206852e338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593992851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_stress_all.3593992851
Directory /workspace/37.rv_dm_stress_all/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1328544703
Short name T70
Test name
Test status
Simulation time 72475424 ps
CPU time 0.75 seconds
Started Aug 01 05:28:25 PM PDT 24
Finished Aug 01 05:28:25 PM PDT 24
Peak memory 205164 kb
Host smart-8d2fc72e-489c-4565-a4b9-e421e28c9b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328544703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1328544703
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.1686891916
Short name T33
Test name
Test status
Simulation time 3645171264 ps
CPU time 3.8 seconds
Started Aug 01 05:28:24 PM PDT 24
Finished Aug 01 05:28:28 PM PDT 24
Peak memory 205492 kb
Host smart-33317c8e-1bf6-4ea8-a751-d20f75829bad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686891916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.1686891916
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3762163166
Short name T209
Test name
Test status
Simulation time 3047331158 ps
CPU time 9.23 seconds
Started Aug 01 05:28:29 PM PDT 24
Finished Aug 01 05:28:38 PM PDT 24
Peak memory 205380 kb
Host smart-84bf0343-2910-40d2-9434-7937464af87b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762163166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3762163166
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.3971609031
Short name T258
Test name
Test status
Simulation time 72948009 ps
CPU time 0.81 seconds
Started Aug 01 05:28:02 PM PDT 24
Finished Aug 01 05:28:02 PM PDT 24
Peak memory 205236 kb
Host smart-919a133e-108f-4615-b770-7e55ad4a2f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971609031 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.3971609031
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.641049464
Short name T195
Test name
Test status
Simulation time 27143680577 ps
CPU time 44.7 seconds
Started Aug 01 05:28:01 PM PDT 24
Finished Aug 01 05:28:46 PM PDT 24
Peak memory 213908 kb
Host smart-deb9c7d7-ed4f-450d-9aa1-91acf1510e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641049464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.641049464
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3768717790
Short name T204
Test name
Test status
Simulation time 1446529229 ps
CPU time 1.5 seconds
Started Aug 01 05:28:02 PM PDT 24
Finished Aug 01 05:28:03 PM PDT 24
Peak memory 205644 kb
Host smart-662336d4-143c-48f3-a38f-e31a22338f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768717790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3768717790
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2802953853
Short name T210
Test name
Test status
Simulation time 2083593556 ps
CPU time 4.11 seconds
Started Aug 01 05:27:58 PM PDT 24
Finished Aug 01 05:28:02 PM PDT 24
Peak memory 205604 kb
Host smart-159f31f5-acad-4aac-afa7-c0b492ba85fd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2802953853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2802953853
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_halt_resume_whereto.301891890
Short name T247
Test name
Test status
Simulation time 226685118 ps
CPU time 1.03 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:28:01 PM PDT 24
Peak memory 205220 kb
Host smart-a6f7042d-c5c0-4279-9b48-5f00d00a2a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301891890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_halt_resume_whereto.301891890
Directory /workspace/4.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.344118988
Short name T171
Test name
Test status
Simulation time 745889800 ps
CPU time 1.88 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:28:02 PM PDT 24
Peak memory 205240 kb
Host smart-f29ab637-1133-485a-87de-f3d8d23a7271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344118988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.344118988
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.2440727597
Short name T292
Test name
Test status
Simulation time 11508489620 ps
CPU time 8.51 seconds
Started Aug 01 05:27:59 PM PDT 24
Finished Aug 01 05:28:07 PM PDT 24
Peak memory 213856 kb
Host smart-b1a57c95-db54-4097-9979-e5c0a4d97213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440727597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.2440727597
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3840837596
Short name T45
Test name
Test status
Simulation time 1624766142 ps
CPU time 1.97 seconds
Started Aug 01 05:27:59 PM PDT 24
Finished Aug 01 05:28:01 PM PDT 24
Peak memory 229840 kb
Host smart-73bac725-c962-4728-a8b2-ff37499df521
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840837596 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3840837596
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.403244414
Short name T65
Test name
Test status
Simulation time 2948806375 ps
CPU time 3.53 seconds
Started Aug 01 05:28:03 PM PDT 24
Finished Aug 01 05:28:06 PM PDT 24
Peak memory 213660 kb
Host smart-1c55cb42-81d4-44e5-b8e9-e49e085d3485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403244414 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.403244414
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all_with_rand_reset.547033891
Short name T75
Test name
Test status
Simulation time 81711105755 ps
CPU time 687 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:39:27 PM PDT 24
Peak memory 230544 kb
Host smart-4f688120-8a9e-488d-b144-911faa7131c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547033891 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all_with_rand_reset.547033891
Directory /workspace/4.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1799371237
Short name T286
Test name
Test status
Simulation time 51039441 ps
CPU time 0.77 seconds
Started Aug 01 05:28:29 PM PDT 24
Finished Aug 01 05:28:30 PM PDT 24
Peak memory 205036 kb
Host smart-85e8bd7d-3fe6-465f-9acf-ebfdd8ff3784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799371237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1799371237
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/40.rv_dm_stress_all.3067854087
Short name T302
Test name
Test status
Simulation time 2805905445 ps
CPU time 2.2 seconds
Started Aug 01 05:28:25 PM PDT 24
Finished Aug 01 05:28:28 PM PDT 24
Peak memory 205472 kb
Host smart-8c4c9595-aab7-4c8c-aa04-74f67a5e3ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067854087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_stress_all.3067854087
Directory /workspace/40.rv_dm_stress_all/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3757637835
Short name T243
Test name
Test status
Simulation time 46917853 ps
CPU time 0.76 seconds
Started Aug 01 05:28:28 PM PDT 24
Finished Aug 01 05:28:29 PM PDT 24
Peak memory 205244 kb
Host smart-3cdc7e28-07fc-4df4-9758-8133c796516f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757637835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3757637835
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.1803243874
Short name T144
Test name
Test status
Simulation time 3892717664 ps
CPU time 2.62 seconds
Started Aug 01 05:28:29 PM PDT 24
Finished Aug 01 05:28:32 PM PDT 24
Peak memory 213640 kb
Host smart-0d23992e-e8a1-4f17-a494-2e808c77d03e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803243874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.1803243874
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.4144666426
Short name T250
Test name
Test status
Simulation time 49521283 ps
CPU time 0.74 seconds
Started Aug 01 05:28:26 PM PDT 24
Finished Aug 01 05:28:27 PM PDT 24
Peak memory 205248 kb
Host smart-cac05e03-5e8a-4c9c-8578-4ad2588850ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144666426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.4144666426
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_stress_all.1301078878
Short name T136
Test name
Test status
Simulation time 3811238247 ps
CPU time 3.02 seconds
Started Aug 01 05:28:27 PM PDT 24
Finished Aug 01 05:28:30 PM PDT 24
Peak memory 205580 kb
Host smart-37c554bc-e01c-4179-b2e6-a2f0fc208418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301078878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_stress_all.1301078878
Directory /workspace/42.rv_dm_stress_all/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.741271780
Short name T236
Test name
Test status
Simulation time 39881522 ps
CPU time 0.73 seconds
Started Aug 01 05:28:31 PM PDT 24
Finished Aug 01 05:28:32 PM PDT 24
Peak memory 205312 kb
Host smart-b2279289-ab7c-460a-8716-23dbaea91c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741271780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.741271780
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.935806612
Short name T303
Test name
Test status
Simulation time 8025445032 ps
CPU time 20.97 seconds
Started Aug 01 05:28:31 PM PDT 24
Finished Aug 01 05:28:52 PM PDT 24
Peak memory 205596 kb
Host smart-4cb450e0-d825-4a4d-a3f8-7a90edd84be3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935806612 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.935806612
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1720599975
Short name T90
Test name
Test status
Simulation time 134985275 ps
CPU time 0.76 seconds
Started Aug 01 05:28:26 PM PDT 24
Finished Aug 01 05:28:27 PM PDT 24
Peak memory 205224 kb
Host smart-1f755531-862c-4cea-b022-015118027d56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720599975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1720599975
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.3139032140
Short name T246
Test name
Test status
Simulation time 6309944281 ps
CPU time 19.9 seconds
Started Aug 01 05:28:26 PM PDT 24
Finished Aug 01 05:28:46 PM PDT 24
Peak memory 205508 kb
Host smart-997be5e8-a350-4e50-a138-9a0337d6e8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139032140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.3139032140
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.531670954
Short name T169
Test name
Test status
Simulation time 94568716 ps
CPU time 0.8 seconds
Started Aug 01 05:28:25 PM PDT 24
Finished Aug 01 05:28:26 PM PDT 24
Peak memory 205204 kb
Host smart-d29448a9-810d-4a7e-9600-73e816679e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531670954 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.531670954
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.229436930
Short name T61
Test name
Test status
Simulation time 71962156 ps
CPU time 0.85 seconds
Started Aug 01 05:28:26 PM PDT 24
Finished Aug 01 05:28:27 PM PDT 24
Peak memory 205220 kb
Host smart-be9288aa-ee41-42d4-a507-1869c10bcd4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229436930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.229436930
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_stress_all.697622495
Short name T19
Test name
Test status
Simulation time 2693410828 ps
CPU time 2.78 seconds
Started Aug 01 05:28:24 PM PDT 24
Finished Aug 01 05:28:27 PM PDT 24
Peak memory 213784 kb
Host smart-6503eacc-8ec1-4756-ac3c-8ddf5d250e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697622495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_stress_all.697622495
Directory /workspace/46.rv_dm_stress_all/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.364147040
Short name T176
Test name
Test status
Simulation time 68819809 ps
CPU time 0.86 seconds
Started Aug 01 05:28:31 PM PDT 24
Finished Aug 01 05:28:32 PM PDT 24
Peak memory 205316 kb
Host smart-476cc779-a947-4522-b30b-90d181637015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364147040 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.364147040
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.1485792703
Short name T2
Test name
Test status
Simulation time 3528726691 ps
CPU time 5.62 seconds
Started Aug 01 05:28:24 PM PDT 24
Finished Aug 01 05:28:30 PM PDT 24
Peak memory 213748 kb
Host smart-bd3c1a88-3de9-4899-8538-405eec15b42a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485792703 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.1485792703
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2517074807
Short name T66
Test name
Test status
Simulation time 180307080 ps
CPU time 0.69 seconds
Started Aug 01 05:28:23 PM PDT 24
Finished Aug 01 05:28:24 PM PDT 24
Peak memory 205340 kb
Host smart-9038e229-23aa-42fb-adac-9e1fcd989b9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517074807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2517074807
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_stress_all.1282135373
Short name T79
Test name
Test status
Simulation time 16413025893 ps
CPU time 11.99 seconds
Started Aug 01 05:28:23 PM PDT 24
Finished Aug 01 05:28:35 PM PDT 24
Peak memory 213776 kb
Host smart-b6392e4a-013c-4acd-b320-eba3d30e80d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282135373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_stress_all.1282135373
Directory /workspace/48.rv_dm_stress_all/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1385555317
Short name T301
Test name
Test status
Simulation time 51281669 ps
CPU time 0.78 seconds
Started Aug 01 05:28:31 PM PDT 24
Finished Aug 01 05:28:33 PM PDT 24
Peak memory 205316 kb
Host smart-47bcdeb4-8ef0-4b71-a80a-b1d398641818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385555317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1385555317
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_stress_all.173584793
Short name T64
Test name
Test status
Simulation time 3454724317 ps
CPU time 5.95 seconds
Started Aug 01 05:28:22 PM PDT 24
Finished Aug 01 05:28:28 PM PDT 24
Peak memory 205580 kb
Host smart-b296d70b-c3de-4c2e-a484-0355de9865ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173584793 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_stress_all.173584793
Directory /workspace/49.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.615659858
Short name T234
Test name
Test status
Simulation time 74288642 ps
CPU time 0.76 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:28:01 PM PDT 24
Peak memory 205268 kb
Host smart-a27e4a4d-bd06-4f08-976a-51a600c3cd2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615659858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.615659858
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.3059886827
Short name T143
Test name
Test status
Simulation time 13911125873 ps
CPU time 39.31 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:28:39 PM PDT 24
Peak memory 222072 kb
Host smart-e2244da1-aaa5-4504-ac68-caf38563826d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059886827 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.3059886827
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1120067870
Short name T48
Test name
Test status
Simulation time 1513056323 ps
CPU time 4.3 seconds
Started Aug 01 05:28:01 PM PDT 24
Finished Aug 01 05:28:06 PM PDT 24
Peak memory 213784 kb
Host smart-05f6494a-c075-436a-b01d-9ac8dccf05e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120067870 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1120067870
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.2396522108
Short name T91
Test name
Test status
Simulation time 13618541670 ps
CPU time 36.33 seconds
Started Aug 01 05:28:01 PM PDT 24
Finished Aug 01 05:28:38 PM PDT 24
Peak memory 222048 kb
Host smart-9c7aaebc-aab2-4d38-bc04-8d917134639a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2396522108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.2396522108
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_halt_resume_whereto.3562524621
Short name T240
Test name
Test status
Simulation time 177345584 ps
CPU time 0.93 seconds
Started Aug 01 05:27:59 PM PDT 24
Finished Aug 01 05:28:00 PM PDT 24
Peak memory 205188 kb
Host smart-4600eb86-3117-41d1-9918-22e89ee07637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562524621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_halt_resume_whereto.3562524621
Directory /workspace/5.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2319396638
Short name T263
Test name
Test status
Simulation time 577663640 ps
CPU time 2.51 seconds
Started Aug 01 05:27:59 PM PDT 24
Finished Aug 01 05:28:02 PM PDT 24
Peak memory 205636 kb
Host smart-9cf07a89-a3ee-430a-8bd5-b2230403b7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319396638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2319396638
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.1024652059
Short name T135
Test name
Test status
Simulation time 6201567885 ps
CPU time 19.13 seconds
Started Aug 01 05:28:02 PM PDT 24
Finished Aug 01 05:28:22 PM PDT 24
Peak memory 205512 kb
Host smart-445e5534-a0e1-4f03-b14e-4454673bddf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024652059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.1024652059
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all_with_rand_reset.564585780
Short name T37
Test name
Test status
Simulation time 97215553497 ps
CPU time 314.19 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:33:14 PM PDT 24
Peak memory 237644 kb
Host smart-64216133-c636-4748-b70e-026a229c9e23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564585780 -assert nopostp
roc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all_with_rand_reset.564585780
Directory /workspace/5.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2683474282
Short name T222
Test name
Test status
Simulation time 73744719 ps
CPU time 0.76 seconds
Started Aug 01 05:27:59 PM PDT 24
Finished Aug 01 05:28:00 PM PDT 24
Peak memory 205340 kb
Host smart-5372094b-3a89-467f-a6f8-c9df1c943ec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683474282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2683474282
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.947413842
Short name T305
Test name
Test status
Simulation time 7430537435 ps
CPU time 22.83 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:28:23 PM PDT 24
Peak memory 205716 kb
Host smart-14c8b88a-5b21-407b-9d49-a5055151d00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947413842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.947413842
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2247226724
Short name T227
Test name
Test status
Simulation time 1830757508 ps
CPU time 2.48 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:28:02 PM PDT 24
Peak memory 205592 kb
Host smart-6d366d52-c91c-4fb3-89e9-4f4b9c698fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247226724 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2247226724
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1908071290
Short name T60
Test name
Test status
Simulation time 2558190054 ps
CPU time 5.12 seconds
Started Aug 01 05:27:59 PM PDT 24
Finished Aug 01 05:28:05 PM PDT 24
Peak memory 205676 kb
Host smart-d6d70d84-8ca3-487a-a53f-c54099eb77cc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1908071290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1908071290
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_halt_resume_whereto.1892512298
Short name T36
Test name
Test status
Simulation time 287835209 ps
CPU time 0.94 seconds
Started Aug 01 05:28:03 PM PDT 24
Finished Aug 01 05:28:04 PM PDT 24
Peak memory 205256 kb
Host smart-ec0222c9-c20e-43e3-8be6-fd83af28988b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892512298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_halt_resume_whereto.1892512298
Directory /workspace/6.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.3309368605
Short name T53
Test name
Test status
Simulation time 7917553227 ps
CPU time 9.77 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:28:10 PM PDT 24
Peak memory 213892 kb
Host smart-fa67d286-8a56-4403-afd4-13b85932ff02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309368605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.3309368605
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.4225183928
Short name T137
Test name
Test status
Simulation time 6328352022 ps
CPU time 5.06 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:28:05 PM PDT 24
Peak memory 205492 kb
Host smart-b1384489-b31a-42d0-93fd-24896ac7caa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225183928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.4225183928
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.705505257
Short name T28
Test name
Test status
Simulation time 122101297 ps
CPU time 0.83 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:28:01 PM PDT 24
Peak memory 205264 kb
Host smart-4cc0bf40-8ead-4e73-8047-e83793e573ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705505257 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.705505257
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.4130892675
Short name T69
Test name
Test status
Simulation time 4489547875 ps
CPU time 6.95 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:28:07 PM PDT 24
Peak memory 205684 kb
Host smart-386bed20-daed-4a2c-ad5b-1e819267c744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130892675 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.4130892675
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2670820360
Short name T218
Test name
Test status
Simulation time 7504674927 ps
CPU time 11.52 seconds
Started Aug 01 05:27:57 PM PDT 24
Finished Aug 01 05:28:09 PM PDT 24
Peak memory 213872 kb
Host smart-ddb262a6-4664-48a4-af2a-9d18c0c19482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670820360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2670820360
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.4081717472
Short name T15
Test name
Test status
Simulation time 15176484719 ps
CPU time 13.32 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:28:14 PM PDT 24
Peak memory 213924 kb
Host smart-6686f937-ae61-470c-a981-a52a3d642c1e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4081717472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.4081717472
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_halt_resume_whereto.1401876239
Short name T245
Test name
Test status
Simulation time 1026660950 ps
CPU time 0.99 seconds
Started Aug 01 05:28:02 PM PDT 24
Finished Aug 01 05:28:04 PM PDT 24
Peak memory 205180 kb
Host smart-a8d62094-c2c0-4b5b-8446-68a4e20c44ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401876239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_halt_resume_whereto.1401876239
Directory /workspace/7.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3607859166
Short name T283
Test name
Test status
Simulation time 4183007335 ps
CPU time 11.26 seconds
Started Aug 01 05:27:59 PM PDT 24
Finished Aug 01 05:28:11 PM PDT 24
Peak memory 205656 kb
Host smart-b1ab389c-a8c6-4282-9c55-d8c374b4581f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607859166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3607859166
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all.3496938160
Short name T146
Test name
Test status
Simulation time 4339973085 ps
CPU time 12.29 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:28:12 PM PDT 24
Peak memory 205544 kb
Host smart-68dccb69-5751-4721-b6e1-0b9b1ba27c2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496938160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all.3496938160
Directory /workspace/7.rv_dm_stress_all/latest

Test location /workspace/coverage/default/7.rv_dm_stress_all_with_rand_reset.3302615329
Short name T6
Test name
Test status
Simulation time 28323920115 ps
CPU time 298.02 seconds
Started Aug 01 05:28:00 PM PDT 24
Finished Aug 01 05:32:59 PM PDT 24
Peak memory 221936 kb
Host smart-c4b75fd2-1368-4616-986c-774aa58658ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_dm_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302615329 -assert nopost
proc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.rv_dm_stress_all_with_rand_reset.3302615329
Directory /workspace/7.rv_dm_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1344190411
Short name T252
Test name
Test status
Simulation time 137788642 ps
CPU time 0.78 seconds
Started Aug 01 05:28:11 PM PDT 24
Finished Aug 01 05:28:12 PM PDT 24
Peak memory 205248 kb
Host smart-6f09999d-15d7-47ef-8775-f3337d664a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344190411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1344190411
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.253023561
Short name T26
Test name
Test status
Simulation time 22490537257 ps
CPU time 60.35 seconds
Started Aug 01 05:28:17 PM PDT 24
Finished Aug 01 05:29:18 PM PDT 24
Peak memory 213852 kb
Host smart-f41231d5-bc37-4a17-8993-ac52df610974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253023561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.253023561
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.2475604227
Short name T68
Test name
Test status
Simulation time 3768790232 ps
CPU time 5.92 seconds
Started Aug 01 05:28:10 PM PDT 24
Finished Aug 01 05:28:16 PM PDT 24
Peak memory 205768 kb
Host smart-2eb549ab-43f6-49f8-8893-dab53734efe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475604227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.2475604227
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.295095645
Short name T172
Test name
Test status
Simulation time 2738877146 ps
CPU time 6.08 seconds
Started Aug 01 05:28:13 PM PDT 24
Finished Aug 01 05:28:19 PM PDT 24
Peak memory 213860 kb
Host smart-d79a5192-5ebf-4c81-bfa3-c71701b494da
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=295095645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl
_access.295095645
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.274363990
Short name T224
Test name
Test status
Simulation time 3099055366 ps
CPU time 5.71 seconds
Started Aug 01 05:27:59 PM PDT 24
Finished Aug 01 05:28:05 PM PDT 24
Peak memory 205712 kb
Host smart-81a30ee3-84f0-454c-a000-2715ad915528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274363990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.274363990
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2665141662
Short name T123
Test name
Test status
Simulation time 169839369 ps
CPU time 0.73 seconds
Started Aug 01 05:28:12 PM PDT 24
Finished Aug 01 05:28:13 PM PDT 24
Peak memory 205248 kb
Host smart-d0f59e83-1e1b-4de7-839a-9e3262c9b492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665141662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2665141662
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_autoincr_sba_tl_access.1207760803
Short name T220
Test name
Test status
Simulation time 17161546545 ps
CPU time 7.29 seconds
Started Aug 01 05:28:13 PM PDT 24
Finished Aug 01 05:28:20 PM PDT 24
Peak memory 213840 kb
Host smart-99396514-cd58-45b5-871c-4f38617bd84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207760803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_autoincr_sba_tl_access.1207760803
Directory /workspace/9.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.3006678214
Short name T163
Test name
Test status
Simulation time 5083442618 ps
CPU time 5.3 seconds
Started Aug 01 05:28:12 PM PDT 24
Finished Aug 01 05:28:17 PM PDT 24
Peak memory 213864 kb
Host smart-88bc0cc1-59a9-4a33-9075-0ec11f0230ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006678214 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.3006678214
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.4040063621
Short name T183
Test name
Test status
Simulation time 5832307258 ps
CPU time 9.09 seconds
Started Aug 01 05:28:14 PM PDT 24
Finished Aug 01 05:28:23 PM PDT 24
Peak memory 205784 kb
Host smart-e2ab157e-5d51-4a61-b009-aabc13852774
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040063621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.4040063621
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3286521321
Short name T181
Test name
Test status
Simulation time 3202454081 ps
CPU time 6.43 seconds
Started Aug 01 05:28:17 PM PDT 24
Finished Aug 01 05:28:23 PM PDT 24
Peak memory 205784 kb
Host smart-b6964288-9056-4e24-8b0b-0142c5a8f791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286521321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3286521321
Directory /workspace/9.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_stress_all.68860970
Short name T124
Test name
Test status
Simulation time 13288004915 ps
CPU time 37.27 seconds
Started Aug 01 05:28:16 PM PDT 24
Finished Aug 01 05:28:53 PM PDT 24
Peak memory 213772 kb
Host smart-5ae577e0-d7d0-4fe2-9ba2-ad62df5ef742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68860970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_stress_all.68860970
Directory /workspace/9.rv_dm_stress_all/latest
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